1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/platform_data/mv88e6xxx.h> 32 #include <linux/netdevice.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/phy.h> 35 #include <linux/phylink.h> 36 #include <net/dsa.h> 37 38 #include "chip.h" 39 #include "global1.h" 40 #include "global2.h" 41 #include "hwtstamp.h" 42 #include "phy.h" 43 #include "port.h" 44 #include "ptp.h" 45 #include "serdes.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 57 * 58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 59 * is the only device connected to the SMI master. In this mode it responds to 60 * all 32 possible SMI addresses, and thus maps directly the internal devices. 61 * 62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 63 * multiple devices to share the SMI interface. In this mode it responds to only 64 * 2 registers, used to indirectly access the internal SMI devices. 65 */ 66 67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 68 int addr, int reg, u16 *val) 69 { 70 if (!chip->smi_ops) 71 return -EOPNOTSUPP; 72 73 return chip->smi_ops->read(chip, addr, reg, val); 74 } 75 76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 77 int addr, int reg, u16 val) 78 { 79 if (!chip->smi_ops) 80 return -EOPNOTSUPP; 81 82 return chip->smi_ops->write(chip, addr, reg, val); 83 } 84 85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 86 int addr, int reg, u16 *val) 87 { 88 int ret; 89 90 ret = mdiobus_read_nested(chip->bus, addr, reg); 91 if (ret < 0) 92 return ret; 93 94 *val = ret & 0xffff; 95 96 return 0; 97 } 98 99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 100 int addr, int reg, u16 val) 101 { 102 int ret; 103 104 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 105 if (ret < 0) 106 return ret; 107 108 return 0; 109 } 110 111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 112 .read = mv88e6xxx_smi_single_chip_read, 113 .write = mv88e6xxx_smi_single_chip_write, 114 }; 115 116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 117 { 118 int ret; 119 int i; 120 121 for (i = 0; i < 16; i++) { 122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 123 if (ret < 0) 124 return ret; 125 126 if ((ret & SMI_CMD_BUSY) == 0) 127 return 0; 128 } 129 130 return -ETIMEDOUT; 131 } 132 133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 134 int addr, int reg, u16 *val) 135 { 136 int ret; 137 138 /* Wait for the bus to become free. */ 139 ret = mv88e6xxx_smi_multi_chip_wait(chip); 140 if (ret < 0) 141 return ret; 142 143 /* Transmit the read command. */ 144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 145 SMI_CMD_OP_22_READ | (addr << 5) | reg); 146 if (ret < 0) 147 return ret; 148 149 /* Wait for the read command to complete. */ 150 ret = mv88e6xxx_smi_multi_chip_wait(chip); 151 if (ret < 0) 152 return ret; 153 154 /* Read the data. */ 155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 156 if (ret < 0) 157 return ret; 158 159 *val = ret & 0xffff; 160 161 return 0; 162 } 163 164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 165 int addr, int reg, u16 val) 166 { 167 int ret; 168 169 /* Wait for the bus to become free. */ 170 ret = mv88e6xxx_smi_multi_chip_wait(chip); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the data to write. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 176 if (ret < 0) 177 return ret; 178 179 /* Transmit the write command. */ 180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 182 if (ret < 0) 183 return ret; 184 185 /* Wait for the write command to complete. */ 186 ret = mv88e6xxx_smi_multi_chip_wait(chip); 187 if (ret < 0) 188 return ret; 189 190 return 0; 191 } 192 193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 194 .read = mv88e6xxx_smi_multi_chip_read, 195 .write = mv88e6xxx_smi_multi_chip_write, 196 }; 197 198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 199 { 200 int err; 201 202 assert_reg_lock(chip); 203 204 err = mv88e6xxx_smi_read(chip, addr, reg, val); 205 if (err) 206 return err; 207 208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 209 addr, reg, *val); 210 211 return 0; 212 } 213 214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 215 { 216 int err; 217 218 assert_reg_lock(chip); 219 220 err = mv88e6xxx_smi_write(chip, addr, reg, val); 221 if (err) 222 return err; 223 224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 225 addr, reg, val); 226 227 return 0; 228 } 229 230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 231 { 232 struct mv88e6xxx_mdio_bus *mdio_bus; 233 234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 235 list); 236 if (!mdio_bus) 237 return NULL; 238 239 return mdio_bus->bus; 240 } 241 242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 243 { 244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 245 unsigned int n = d->hwirq; 246 247 chip->g1_irq.masked |= (1 << n); 248 } 249 250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 251 { 252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 253 unsigned int n = d->hwirq; 254 255 chip->g1_irq.masked &= ~(1 << n); 256 } 257 258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 259 { 260 unsigned int nhandled = 0; 261 unsigned int sub_irq; 262 unsigned int n; 263 u16 reg; 264 int err; 265 266 mutex_lock(&chip->reg_lock); 267 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 268 mutex_unlock(&chip->reg_lock); 269 270 if (err) 271 goto out; 272 273 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 274 if (reg & (1 << n)) { 275 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 276 handle_nested_irq(sub_irq); 277 ++nhandled; 278 } 279 } 280 out: 281 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 282 } 283 284 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 285 { 286 struct mv88e6xxx_chip *chip = dev_id; 287 288 return mv88e6xxx_g1_irq_thread_work(chip); 289 } 290 291 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 292 { 293 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 294 295 mutex_lock(&chip->reg_lock); 296 } 297 298 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 299 { 300 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 301 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 302 u16 reg; 303 int err; 304 305 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 306 if (err) 307 goto out; 308 309 reg &= ~mask; 310 reg |= (~chip->g1_irq.masked & mask); 311 312 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 313 if (err) 314 goto out; 315 316 out: 317 mutex_unlock(&chip->reg_lock); 318 } 319 320 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 321 .name = "mv88e6xxx-g1", 322 .irq_mask = mv88e6xxx_g1_irq_mask, 323 .irq_unmask = mv88e6xxx_g1_irq_unmask, 324 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 325 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 326 }; 327 328 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 329 unsigned int irq, 330 irq_hw_number_t hwirq) 331 { 332 struct mv88e6xxx_chip *chip = d->host_data; 333 334 irq_set_chip_data(irq, d->host_data); 335 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 336 irq_set_noprobe(irq); 337 338 return 0; 339 } 340 341 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 342 .map = mv88e6xxx_g1_irq_domain_map, 343 .xlate = irq_domain_xlate_twocell, 344 }; 345 346 /* To be called with reg_lock held */ 347 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 348 { 349 int irq, virq; 350 u16 mask; 351 352 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 353 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 354 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 355 356 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 357 virq = irq_find_mapping(chip->g1_irq.domain, irq); 358 irq_dispose_mapping(virq); 359 } 360 361 irq_domain_remove(chip->g1_irq.domain); 362 } 363 364 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 365 { 366 /* 367 * free_irq must be called without reg_lock taken because the irq 368 * handler takes this lock, too. 369 */ 370 free_irq(chip->irq, chip); 371 372 mutex_lock(&chip->reg_lock); 373 mv88e6xxx_g1_irq_free_common(chip); 374 mutex_unlock(&chip->reg_lock); 375 } 376 377 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 378 { 379 int err, irq, virq; 380 u16 reg, mask; 381 382 chip->g1_irq.nirqs = chip->info->g1_irqs; 383 chip->g1_irq.domain = irq_domain_add_simple( 384 NULL, chip->g1_irq.nirqs, 0, 385 &mv88e6xxx_g1_irq_domain_ops, chip); 386 if (!chip->g1_irq.domain) 387 return -ENOMEM; 388 389 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 390 irq_create_mapping(chip->g1_irq.domain, irq); 391 392 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 393 chip->g1_irq.masked = ~0; 394 395 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 396 if (err) 397 goto out_mapping; 398 399 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 400 401 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 402 if (err) 403 goto out_disable; 404 405 /* Reading the interrupt status clears (most of) them */ 406 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 407 if (err) 408 goto out_disable; 409 410 return 0; 411 412 out_disable: 413 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 414 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 415 416 out_mapping: 417 for (irq = 0; irq < 16; irq++) { 418 virq = irq_find_mapping(chip->g1_irq.domain, irq); 419 irq_dispose_mapping(virq); 420 } 421 422 irq_domain_remove(chip->g1_irq.domain); 423 424 return err; 425 } 426 427 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 428 { 429 int err; 430 431 err = mv88e6xxx_g1_irq_setup_common(chip); 432 if (err) 433 return err; 434 435 err = request_threaded_irq(chip->irq, NULL, 436 mv88e6xxx_g1_irq_thread_fn, 437 IRQF_ONESHOT | IRQF_SHARED, 438 dev_name(chip->dev), chip); 439 if (err) 440 mv88e6xxx_g1_irq_free_common(chip); 441 442 return err; 443 } 444 445 static void mv88e6xxx_irq_poll(struct kthread_work *work) 446 { 447 struct mv88e6xxx_chip *chip = container_of(work, 448 struct mv88e6xxx_chip, 449 irq_poll_work.work); 450 mv88e6xxx_g1_irq_thread_work(chip); 451 452 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 453 msecs_to_jiffies(100)); 454 } 455 456 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 457 { 458 int err; 459 460 err = mv88e6xxx_g1_irq_setup_common(chip); 461 if (err) 462 return err; 463 464 kthread_init_delayed_work(&chip->irq_poll_work, 465 mv88e6xxx_irq_poll); 466 467 chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); 468 if (IS_ERR(chip->kworker)) 469 return PTR_ERR(chip->kworker); 470 471 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 472 msecs_to_jiffies(100)); 473 474 return 0; 475 } 476 477 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 478 { 479 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 480 kthread_destroy_worker(chip->kworker); 481 482 mutex_lock(&chip->reg_lock); 483 mv88e6xxx_g1_irq_free_common(chip); 484 mutex_unlock(&chip->reg_lock); 485 } 486 487 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 488 { 489 int i; 490 491 for (i = 0; i < 16; i++) { 492 u16 val; 493 int err; 494 495 err = mv88e6xxx_read(chip, addr, reg, &val); 496 if (err) 497 return err; 498 499 if (!(val & mask)) 500 return 0; 501 502 usleep_range(1000, 2000); 503 } 504 505 dev_err(chip->dev, "Timeout while waiting for switch\n"); 506 return -ETIMEDOUT; 507 } 508 509 /* Indirect write to single pointer-data register with an Update bit */ 510 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 511 { 512 u16 val; 513 int err; 514 515 /* Wait until the previous operation is completed */ 516 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 517 if (err) 518 return err; 519 520 /* Set the Update bit to trigger a write operation */ 521 val = BIT(15) | update; 522 523 return mv88e6xxx_write(chip, addr, reg, val); 524 } 525 526 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 527 int link, int speed, int duplex, int pause, 528 phy_interface_t mode) 529 { 530 int err; 531 532 if (!chip->info->ops->port_set_link) 533 return 0; 534 535 /* Port's MAC control must not be changed unless the link is down */ 536 err = chip->info->ops->port_set_link(chip, port, 0); 537 if (err) 538 return err; 539 540 if (chip->info->ops->port_set_speed) { 541 err = chip->info->ops->port_set_speed(chip, port, speed); 542 if (err && err != -EOPNOTSUPP) 543 goto restore_link; 544 } 545 546 if (chip->info->ops->port_set_pause) { 547 err = chip->info->ops->port_set_pause(chip, port, pause); 548 if (err) 549 goto restore_link; 550 } 551 552 if (chip->info->ops->port_set_duplex) { 553 err = chip->info->ops->port_set_duplex(chip, port, duplex); 554 if (err && err != -EOPNOTSUPP) 555 goto restore_link; 556 } 557 558 if (chip->info->ops->port_set_rgmii_delay) { 559 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 560 if (err && err != -EOPNOTSUPP) 561 goto restore_link; 562 } 563 564 if (chip->info->ops->port_set_cmode) { 565 err = chip->info->ops->port_set_cmode(chip, port, mode); 566 if (err && err != -EOPNOTSUPP) 567 goto restore_link; 568 } 569 570 err = 0; 571 restore_link: 572 if (chip->info->ops->port_set_link(chip, port, link)) 573 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 574 575 return err; 576 } 577 578 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 579 { 580 struct mv88e6xxx_chip *chip = ds->priv; 581 582 return port < chip->info->num_internal_phys; 583 } 584 585 /* We expect the switch to perform auto negotiation if there is a real 586 * phy. However, in the case of a fixed link phy, we force the port 587 * settings from the fixed link settings. 588 */ 589 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 590 struct phy_device *phydev) 591 { 592 struct mv88e6xxx_chip *chip = ds->priv; 593 int err; 594 595 if (!phy_is_pseudo_fixed_link(phydev) && 596 mv88e6xxx_phy_is_internal(ds, port)) 597 return; 598 599 mutex_lock(&chip->reg_lock); 600 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 601 phydev->duplex, phydev->pause, 602 phydev->interface); 603 mutex_unlock(&chip->reg_lock); 604 605 if (err && err != -EOPNOTSUPP) 606 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 607 } 608 609 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 610 unsigned long *mask, 611 struct phylink_link_state *state) 612 { 613 if (!phy_interface_mode_is_8023z(state->interface)) { 614 /* 10M and 100M are only supported in non-802.3z mode */ 615 phylink_set(mask, 10baseT_Half); 616 phylink_set(mask, 10baseT_Full); 617 phylink_set(mask, 100baseT_Half); 618 phylink_set(mask, 100baseT_Full); 619 } 620 } 621 622 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 623 unsigned long *mask, 624 struct phylink_link_state *state) 625 { 626 /* FIXME: if the port is in 1000Base-X mode, then it only supports 627 * 1000M FD speeds. In this case, CMODE will indicate 5. 628 */ 629 phylink_set(mask, 1000baseT_Full); 630 phylink_set(mask, 1000baseX_Full); 631 632 mv88e6065_phylink_validate(chip, port, mask, state); 633 } 634 635 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 636 unsigned long *mask, 637 struct phylink_link_state *state) 638 { 639 /* No ethtool bits for 200Mbps */ 640 phylink_set(mask, 1000baseT_Full); 641 phylink_set(mask, 1000baseX_Full); 642 643 mv88e6065_phylink_validate(chip, port, mask, state); 644 } 645 646 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 647 unsigned long *mask, 648 struct phylink_link_state *state) 649 { 650 if (port >= 9) 651 phylink_set(mask, 2500baseX_Full); 652 653 /* No ethtool bits for 200Mbps */ 654 phylink_set(mask, 1000baseT_Full); 655 phylink_set(mask, 1000baseX_Full); 656 657 mv88e6065_phylink_validate(chip, port, mask, state); 658 } 659 660 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 661 unsigned long *mask, 662 struct phylink_link_state *state) 663 { 664 if (port >= 9) { 665 phylink_set(mask, 10000baseT_Full); 666 phylink_set(mask, 10000baseKR_Full); 667 } 668 669 mv88e6390_phylink_validate(chip, port, mask, state); 670 } 671 672 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 673 unsigned long *supported, 674 struct phylink_link_state *state) 675 { 676 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 677 struct mv88e6xxx_chip *chip = ds->priv; 678 679 /* Allow all the expected bits */ 680 phylink_set(mask, Autoneg); 681 phylink_set(mask, Pause); 682 phylink_set_port_modes(mask); 683 684 if (chip->info->ops->phylink_validate) 685 chip->info->ops->phylink_validate(chip, port, mask, state); 686 687 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 688 bitmap_and(state->advertising, state->advertising, mask, 689 __ETHTOOL_LINK_MODE_MASK_NBITS); 690 691 /* We can only operate at 2500BaseX or 1000BaseX. If requested 692 * to advertise both, only report advertising at 2500BaseX. 693 */ 694 phylink_helper_basex_speed(state); 695 } 696 697 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 698 struct phylink_link_state *state) 699 { 700 struct mv88e6xxx_chip *chip = ds->priv; 701 int err; 702 703 mutex_lock(&chip->reg_lock); 704 if (chip->info->ops->port_link_state) 705 err = chip->info->ops->port_link_state(chip, port, state); 706 else 707 err = -EOPNOTSUPP; 708 mutex_unlock(&chip->reg_lock); 709 710 return err; 711 } 712 713 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 714 unsigned int mode, 715 const struct phylink_link_state *state) 716 { 717 struct mv88e6xxx_chip *chip = ds->priv; 718 int speed, duplex, link, pause, err; 719 720 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 721 return; 722 723 if (mode == MLO_AN_FIXED) { 724 link = LINK_FORCED_UP; 725 speed = state->speed; 726 duplex = state->duplex; 727 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 728 link = state->link; 729 speed = state->speed; 730 duplex = state->duplex; 731 } else { 732 speed = SPEED_UNFORCED; 733 duplex = DUPLEX_UNFORCED; 734 link = LINK_UNFORCED; 735 } 736 pause = !!phylink_test(state->advertising, Pause); 737 738 mutex_lock(&chip->reg_lock); 739 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 740 state->interface); 741 mutex_unlock(&chip->reg_lock); 742 743 if (err && err != -EOPNOTSUPP) 744 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 745 } 746 747 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 748 { 749 struct mv88e6xxx_chip *chip = ds->priv; 750 int err; 751 752 mutex_lock(&chip->reg_lock); 753 err = chip->info->ops->port_set_link(chip, port, link); 754 mutex_unlock(&chip->reg_lock); 755 756 if (err) 757 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 758 } 759 760 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 761 unsigned int mode, 762 phy_interface_t interface) 763 { 764 if (mode == MLO_AN_FIXED) 765 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 766 } 767 768 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 769 unsigned int mode, phy_interface_t interface, 770 struct phy_device *phydev) 771 { 772 if (mode == MLO_AN_FIXED) 773 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 774 } 775 776 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 777 { 778 if (!chip->info->ops->stats_snapshot) 779 return -EOPNOTSUPP; 780 781 return chip->info->ops->stats_snapshot(chip, port); 782 } 783 784 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 785 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 786 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 787 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 788 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 789 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 790 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 791 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 792 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 793 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 794 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 795 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 796 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 797 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 798 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 799 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 800 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 801 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 802 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 803 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 804 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 805 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 806 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 807 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 808 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 809 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 810 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 811 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 812 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 813 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 814 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 815 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 816 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 817 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 818 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 819 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 820 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 821 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 822 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 823 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 824 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 825 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 826 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 827 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 828 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 829 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 830 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 831 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 832 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 833 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 834 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 835 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 836 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 837 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 838 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 839 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 840 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 841 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 842 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 843 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 844 }; 845 846 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 847 struct mv88e6xxx_hw_stat *s, 848 int port, u16 bank1_select, 849 u16 histogram) 850 { 851 u32 low; 852 u32 high = 0; 853 u16 reg = 0; 854 int err; 855 u64 value; 856 857 switch (s->type) { 858 case STATS_TYPE_PORT: 859 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 860 if (err) 861 return U64_MAX; 862 863 low = reg; 864 if (s->size == 4) { 865 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 866 if (err) 867 return U64_MAX; 868 high = reg; 869 } 870 break; 871 case STATS_TYPE_BANK1: 872 reg = bank1_select; 873 /* fall through */ 874 case STATS_TYPE_BANK0: 875 reg |= s->reg | histogram; 876 mv88e6xxx_g1_stats_read(chip, reg, &low); 877 if (s->size == 8) 878 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 879 break; 880 default: 881 return U64_MAX; 882 } 883 value = (((u64)high) << 16) | low; 884 return value; 885 } 886 887 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 888 uint8_t *data, int types) 889 { 890 struct mv88e6xxx_hw_stat *stat; 891 int i, j; 892 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 894 stat = &mv88e6xxx_hw_stats[i]; 895 if (stat->type & types) { 896 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 897 ETH_GSTRING_LEN); 898 j++; 899 } 900 } 901 902 return j; 903 } 904 905 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 906 uint8_t *data) 907 { 908 return mv88e6xxx_stats_get_strings(chip, data, 909 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 910 } 911 912 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 913 uint8_t *data) 914 { 915 return mv88e6xxx_stats_get_strings(chip, data, 916 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 917 } 918 919 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 920 "atu_member_violation", 921 "atu_miss_violation", 922 "atu_full_violation", 923 "vtu_member_violation", 924 "vtu_miss_violation", 925 }; 926 927 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 928 { 929 unsigned int i; 930 931 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 932 strlcpy(data + i * ETH_GSTRING_LEN, 933 mv88e6xxx_atu_vtu_stats_strings[i], 934 ETH_GSTRING_LEN); 935 } 936 937 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 938 u32 stringset, uint8_t *data) 939 { 940 struct mv88e6xxx_chip *chip = ds->priv; 941 int count = 0; 942 943 if (stringset != ETH_SS_STATS) 944 return; 945 946 mutex_lock(&chip->reg_lock); 947 948 if (chip->info->ops->stats_get_strings) 949 count = chip->info->ops->stats_get_strings(chip, data); 950 951 if (chip->info->ops->serdes_get_strings) { 952 data += count * ETH_GSTRING_LEN; 953 count = chip->info->ops->serdes_get_strings(chip, port, data); 954 } 955 956 data += count * ETH_GSTRING_LEN; 957 mv88e6xxx_atu_vtu_get_strings(data); 958 959 mutex_unlock(&chip->reg_lock); 960 } 961 962 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 963 int types) 964 { 965 struct mv88e6xxx_hw_stat *stat; 966 int i, j; 967 968 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 969 stat = &mv88e6xxx_hw_stats[i]; 970 if (stat->type & types) 971 j++; 972 } 973 return j; 974 } 975 976 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 977 { 978 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 979 STATS_TYPE_PORT); 980 } 981 982 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 983 { 984 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 985 STATS_TYPE_BANK1); 986 } 987 988 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 989 { 990 struct mv88e6xxx_chip *chip = ds->priv; 991 int serdes_count = 0; 992 int count = 0; 993 994 if (sset != ETH_SS_STATS) 995 return 0; 996 997 mutex_lock(&chip->reg_lock); 998 if (chip->info->ops->stats_get_sset_count) 999 count = chip->info->ops->stats_get_sset_count(chip); 1000 if (count < 0) 1001 goto out; 1002 1003 if (chip->info->ops->serdes_get_sset_count) 1004 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1005 port); 1006 if (serdes_count < 0) { 1007 count = serdes_count; 1008 goto out; 1009 } 1010 count += serdes_count; 1011 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1012 1013 out: 1014 mutex_unlock(&chip->reg_lock); 1015 1016 return count; 1017 } 1018 1019 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1020 uint64_t *data, int types, 1021 u16 bank1_select, u16 histogram) 1022 { 1023 struct mv88e6xxx_hw_stat *stat; 1024 int i, j; 1025 1026 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1027 stat = &mv88e6xxx_hw_stats[i]; 1028 if (stat->type & types) { 1029 mutex_lock(&chip->reg_lock); 1030 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1031 bank1_select, 1032 histogram); 1033 mutex_unlock(&chip->reg_lock); 1034 1035 j++; 1036 } 1037 } 1038 return j; 1039 } 1040 1041 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1042 uint64_t *data) 1043 { 1044 return mv88e6xxx_stats_get_stats(chip, port, data, 1045 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1046 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1047 } 1048 1049 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1050 uint64_t *data) 1051 { 1052 return mv88e6xxx_stats_get_stats(chip, port, data, 1053 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1054 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1055 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1056 } 1057 1058 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1059 uint64_t *data) 1060 { 1061 return mv88e6xxx_stats_get_stats(chip, port, data, 1062 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1063 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1064 0); 1065 } 1066 1067 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1068 uint64_t *data) 1069 { 1070 *data++ = chip->ports[port].atu_member_violation; 1071 *data++ = chip->ports[port].atu_miss_violation; 1072 *data++ = chip->ports[port].atu_full_violation; 1073 *data++ = chip->ports[port].vtu_member_violation; 1074 *data++ = chip->ports[port].vtu_miss_violation; 1075 } 1076 1077 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1078 uint64_t *data) 1079 { 1080 int count = 0; 1081 1082 if (chip->info->ops->stats_get_stats) 1083 count = chip->info->ops->stats_get_stats(chip, port, data); 1084 1085 mutex_lock(&chip->reg_lock); 1086 if (chip->info->ops->serdes_get_stats) { 1087 data += count; 1088 count = chip->info->ops->serdes_get_stats(chip, port, data); 1089 } 1090 data += count; 1091 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1092 mutex_unlock(&chip->reg_lock); 1093 } 1094 1095 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1096 uint64_t *data) 1097 { 1098 struct mv88e6xxx_chip *chip = ds->priv; 1099 int ret; 1100 1101 mutex_lock(&chip->reg_lock); 1102 1103 ret = mv88e6xxx_stats_snapshot(chip, port); 1104 mutex_unlock(&chip->reg_lock); 1105 1106 if (ret < 0) 1107 return; 1108 1109 mv88e6xxx_get_stats(chip, port, data); 1110 1111 } 1112 1113 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1114 { 1115 return 32 * sizeof(u16); 1116 } 1117 1118 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1119 struct ethtool_regs *regs, void *_p) 1120 { 1121 struct mv88e6xxx_chip *chip = ds->priv; 1122 int err; 1123 u16 reg; 1124 u16 *p = _p; 1125 int i; 1126 1127 regs->version = chip->info->prod_num; 1128 1129 memset(p, 0xff, 32 * sizeof(u16)); 1130 1131 mutex_lock(&chip->reg_lock); 1132 1133 for (i = 0; i < 32; i++) { 1134 1135 err = mv88e6xxx_port_read(chip, port, i, ®); 1136 if (!err) 1137 p[i] = reg; 1138 } 1139 1140 mutex_unlock(&chip->reg_lock); 1141 } 1142 1143 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1144 struct ethtool_eee *e) 1145 { 1146 /* Nothing to do on the port's MAC */ 1147 return 0; 1148 } 1149 1150 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1151 struct ethtool_eee *e) 1152 { 1153 /* Nothing to do on the port's MAC */ 1154 return 0; 1155 } 1156 1157 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1158 { 1159 struct dsa_switch *ds = NULL; 1160 struct net_device *br; 1161 u16 pvlan; 1162 int i; 1163 1164 if (dev < DSA_MAX_SWITCHES) 1165 ds = chip->ds->dst->ds[dev]; 1166 1167 /* Prevent frames from unknown switch or port */ 1168 if (!ds || port >= ds->num_ports) 1169 return 0; 1170 1171 /* Frames from DSA links and CPU ports can egress any local port */ 1172 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1173 return mv88e6xxx_port_mask(chip); 1174 1175 br = ds->ports[port].bridge_dev; 1176 pvlan = 0; 1177 1178 /* Frames from user ports can egress any local DSA links and CPU ports, 1179 * as well as any local member of their bridge group. 1180 */ 1181 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1182 if (dsa_is_cpu_port(chip->ds, i) || 1183 dsa_is_dsa_port(chip->ds, i) || 1184 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1185 pvlan |= BIT(i); 1186 1187 return pvlan; 1188 } 1189 1190 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1191 { 1192 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1193 1194 /* prevent frames from going back out of the port they came in on */ 1195 output_ports &= ~BIT(port); 1196 1197 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1198 } 1199 1200 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1201 u8 state) 1202 { 1203 struct mv88e6xxx_chip *chip = ds->priv; 1204 int err; 1205 1206 mutex_lock(&chip->reg_lock); 1207 err = mv88e6xxx_port_set_state(chip, port, state); 1208 mutex_unlock(&chip->reg_lock); 1209 1210 if (err) 1211 dev_err(ds->dev, "p%d: failed to update state\n", port); 1212 } 1213 1214 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1215 { 1216 int err; 1217 1218 if (chip->info->ops->ieee_pri_map) { 1219 err = chip->info->ops->ieee_pri_map(chip); 1220 if (err) 1221 return err; 1222 } 1223 1224 if (chip->info->ops->ip_pri_map) { 1225 err = chip->info->ops->ip_pri_map(chip); 1226 if (err) 1227 return err; 1228 } 1229 1230 return 0; 1231 } 1232 1233 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1234 { 1235 int target, port; 1236 int err; 1237 1238 if (!chip->info->global2_addr) 1239 return 0; 1240 1241 /* Initialize the routing port to the 32 possible target devices */ 1242 for (target = 0; target < 32; target++) { 1243 port = 0x1f; 1244 if (target < DSA_MAX_SWITCHES) 1245 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1246 port = chip->ds->rtable[target]; 1247 1248 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1249 if (err) 1250 return err; 1251 } 1252 1253 if (chip->info->ops->set_cascade_port) { 1254 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1255 err = chip->info->ops->set_cascade_port(chip, port); 1256 if (err) 1257 return err; 1258 } 1259 1260 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1261 if (err) 1262 return err; 1263 1264 return 0; 1265 } 1266 1267 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1268 { 1269 /* Clear all trunk masks and mapping */ 1270 if (chip->info->global2_addr) 1271 return mv88e6xxx_g2_trunk_clear(chip); 1272 1273 return 0; 1274 } 1275 1276 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1277 { 1278 if (chip->info->ops->rmu_disable) 1279 return chip->info->ops->rmu_disable(chip); 1280 1281 return 0; 1282 } 1283 1284 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1285 { 1286 if (chip->info->ops->pot_clear) 1287 return chip->info->ops->pot_clear(chip); 1288 1289 return 0; 1290 } 1291 1292 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1293 { 1294 if (chip->info->ops->mgmt_rsvd2cpu) 1295 return chip->info->ops->mgmt_rsvd2cpu(chip); 1296 1297 return 0; 1298 } 1299 1300 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1301 { 1302 int err; 1303 1304 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1305 if (err) 1306 return err; 1307 1308 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1309 if (err) 1310 return err; 1311 1312 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1313 } 1314 1315 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1316 { 1317 int port; 1318 int err; 1319 1320 if (!chip->info->ops->irl_init_all) 1321 return 0; 1322 1323 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1324 /* Disable ingress rate limiting by resetting all per port 1325 * ingress rate limit resources to their initial state. 1326 */ 1327 err = chip->info->ops->irl_init_all(chip, port); 1328 if (err) 1329 return err; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1336 { 1337 if (chip->info->ops->set_switch_mac) { 1338 u8 addr[ETH_ALEN]; 1339 1340 eth_random_addr(addr); 1341 1342 return chip->info->ops->set_switch_mac(chip, addr); 1343 } 1344 1345 return 0; 1346 } 1347 1348 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1349 { 1350 u16 pvlan = 0; 1351 1352 if (!mv88e6xxx_has_pvt(chip)) 1353 return -EOPNOTSUPP; 1354 1355 /* Skip the local source device, which uses in-chip port VLAN */ 1356 if (dev != chip->ds->index) 1357 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1358 1359 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1360 } 1361 1362 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1363 { 1364 int dev, port; 1365 int err; 1366 1367 if (!mv88e6xxx_has_pvt(chip)) 1368 return 0; 1369 1370 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1371 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1372 */ 1373 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1374 if (err) 1375 return err; 1376 1377 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1378 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1379 err = mv88e6xxx_pvt_map(chip, dev, port); 1380 if (err) 1381 return err; 1382 } 1383 } 1384 1385 return 0; 1386 } 1387 1388 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1389 { 1390 struct mv88e6xxx_chip *chip = ds->priv; 1391 int err; 1392 1393 mutex_lock(&chip->reg_lock); 1394 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1395 mutex_unlock(&chip->reg_lock); 1396 1397 if (err) 1398 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1399 } 1400 1401 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1402 { 1403 if (!chip->info->max_vid) 1404 return 0; 1405 1406 return mv88e6xxx_g1_vtu_flush(chip); 1407 } 1408 1409 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1410 struct mv88e6xxx_vtu_entry *entry) 1411 { 1412 if (!chip->info->ops->vtu_getnext) 1413 return -EOPNOTSUPP; 1414 1415 return chip->info->ops->vtu_getnext(chip, entry); 1416 } 1417 1418 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1419 struct mv88e6xxx_vtu_entry *entry) 1420 { 1421 if (!chip->info->ops->vtu_loadpurge) 1422 return -EOPNOTSUPP; 1423 1424 return chip->info->ops->vtu_loadpurge(chip, entry); 1425 } 1426 1427 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1428 { 1429 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1430 struct mv88e6xxx_vtu_entry vlan = { 1431 .vid = chip->info->max_vid, 1432 }; 1433 int i, err; 1434 1435 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1436 1437 /* Set every FID bit used by the (un)bridged ports */ 1438 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1439 err = mv88e6xxx_port_get_fid(chip, i, fid); 1440 if (err) 1441 return err; 1442 1443 set_bit(*fid, fid_bitmap); 1444 } 1445 1446 /* Set every FID bit used by the VLAN entries */ 1447 do { 1448 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1449 if (err) 1450 return err; 1451 1452 if (!vlan.valid) 1453 break; 1454 1455 set_bit(vlan.fid, fid_bitmap); 1456 } while (vlan.vid < chip->info->max_vid); 1457 1458 /* The reset value 0x000 is used to indicate that multiple address 1459 * databases are not needed. Return the next positive available. 1460 */ 1461 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1462 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1463 return -ENOSPC; 1464 1465 /* Clear the database */ 1466 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1467 } 1468 1469 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1470 struct mv88e6xxx_vtu_entry *entry, bool new) 1471 { 1472 int err; 1473 1474 if (!vid) 1475 return -EINVAL; 1476 1477 entry->vid = vid - 1; 1478 entry->valid = false; 1479 1480 err = mv88e6xxx_vtu_getnext(chip, entry); 1481 if (err) 1482 return err; 1483 1484 if (entry->vid == vid && entry->valid) 1485 return 0; 1486 1487 if (new) { 1488 int i; 1489 1490 /* Initialize a fresh VLAN entry */ 1491 memset(entry, 0, sizeof(*entry)); 1492 entry->valid = true; 1493 entry->vid = vid; 1494 1495 /* Exclude all ports */ 1496 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1497 entry->member[i] = 1498 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1499 1500 return mv88e6xxx_atu_new(chip, &entry->fid); 1501 } 1502 1503 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1504 return -EOPNOTSUPP; 1505 } 1506 1507 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1508 u16 vid_begin, u16 vid_end) 1509 { 1510 struct mv88e6xxx_chip *chip = ds->priv; 1511 struct mv88e6xxx_vtu_entry vlan = { 1512 .vid = vid_begin - 1, 1513 }; 1514 int i, err; 1515 1516 /* DSA and CPU ports have to be members of multiple vlans */ 1517 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1518 return 0; 1519 1520 if (!vid_begin) 1521 return -EOPNOTSUPP; 1522 1523 mutex_lock(&chip->reg_lock); 1524 1525 do { 1526 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1527 if (err) 1528 goto unlock; 1529 1530 if (!vlan.valid) 1531 break; 1532 1533 if (vlan.vid > vid_end) 1534 break; 1535 1536 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1537 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1538 continue; 1539 1540 if (!ds->ports[i].slave) 1541 continue; 1542 1543 if (vlan.member[i] == 1544 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1545 continue; 1546 1547 if (dsa_to_port(ds, i)->bridge_dev == 1548 ds->ports[port].bridge_dev) 1549 break; /* same bridge, check next VLAN */ 1550 1551 if (!dsa_to_port(ds, i)->bridge_dev) 1552 continue; 1553 1554 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1555 port, vlan.vid, i, 1556 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1557 err = -EOPNOTSUPP; 1558 goto unlock; 1559 } 1560 } while (vlan.vid < vid_end); 1561 1562 unlock: 1563 mutex_unlock(&chip->reg_lock); 1564 1565 return err; 1566 } 1567 1568 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1569 bool vlan_filtering) 1570 { 1571 struct mv88e6xxx_chip *chip = ds->priv; 1572 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1573 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1574 int err; 1575 1576 if (!chip->info->max_vid) 1577 return -EOPNOTSUPP; 1578 1579 mutex_lock(&chip->reg_lock); 1580 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1581 mutex_unlock(&chip->reg_lock); 1582 1583 return err; 1584 } 1585 1586 static int 1587 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1588 const struct switchdev_obj_port_vlan *vlan) 1589 { 1590 struct mv88e6xxx_chip *chip = ds->priv; 1591 int err; 1592 1593 if (!chip->info->max_vid) 1594 return -EOPNOTSUPP; 1595 1596 /* If the requested port doesn't belong to the same bridge as the VLAN 1597 * members, do not support it (yet) and fallback to software VLAN. 1598 */ 1599 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1600 vlan->vid_end); 1601 if (err) 1602 return err; 1603 1604 /* We don't need any dynamic resource from the kernel (yet), 1605 * so skip the prepare phase. 1606 */ 1607 return 0; 1608 } 1609 1610 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1611 const unsigned char *addr, u16 vid, 1612 u8 state) 1613 { 1614 struct mv88e6xxx_vtu_entry vlan; 1615 struct mv88e6xxx_atu_entry entry; 1616 int err; 1617 1618 /* Null VLAN ID corresponds to the port private database */ 1619 if (vid == 0) 1620 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1621 else 1622 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1623 if (err) 1624 return err; 1625 1626 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1627 ether_addr_copy(entry.mac, addr); 1628 eth_addr_dec(entry.mac); 1629 1630 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1631 if (err) 1632 return err; 1633 1634 /* Initialize a fresh ATU entry if it isn't found */ 1635 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1636 !ether_addr_equal(entry.mac, addr)) { 1637 memset(&entry, 0, sizeof(entry)); 1638 ether_addr_copy(entry.mac, addr); 1639 } 1640 1641 /* Purge the ATU entry only if no port is using it anymore */ 1642 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1643 entry.portvec &= ~BIT(port); 1644 if (!entry.portvec) 1645 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1646 } else { 1647 entry.portvec |= BIT(port); 1648 entry.state = state; 1649 } 1650 1651 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1652 } 1653 1654 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1655 u16 vid) 1656 { 1657 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1658 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1659 1660 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1661 } 1662 1663 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1664 { 1665 int port; 1666 int err; 1667 1668 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1669 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1670 if (err) 1671 return err; 1672 } 1673 1674 return 0; 1675 } 1676 1677 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1678 u16 vid, u8 member) 1679 { 1680 struct mv88e6xxx_vtu_entry vlan; 1681 int err; 1682 1683 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1684 if (err) 1685 return err; 1686 1687 vlan.member[port] = member; 1688 1689 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1690 if (err) 1691 return err; 1692 1693 return mv88e6xxx_broadcast_setup(chip, vid); 1694 } 1695 1696 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1697 const struct switchdev_obj_port_vlan *vlan) 1698 { 1699 struct mv88e6xxx_chip *chip = ds->priv; 1700 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1701 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1702 u8 member; 1703 u16 vid; 1704 1705 if (!chip->info->max_vid) 1706 return; 1707 1708 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1709 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1710 else if (untagged) 1711 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1712 else 1713 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1714 1715 mutex_lock(&chip->reg_lock); 1716 1717 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1718 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1719 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1720 vid, untagged ? 'u' : 't'); 1721 1722 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1723 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1724 vlan->vid_end); 1725 1726 mutex_unlock(&chip->reg_lock); 1727 } 1728 1729 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1730 int port, u16 vid) 1731 { 1732 struct mv88e6xxx_vtu_entry vlan; 1733 int i, err; 1734 1735 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1736 if (err) 1737 return err; 1738 1739 /* Tell switchdev if this VLAN is handled in software */ 1740 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1741 return -EOPNOTSUPP; 1742 1743 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1744 1745 /* keep the VLAN unless all ports are excluded */ 1746 vlan.valid = false; 1747 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1748 if (vlan.member[i] != 1749 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1750 vlan.valid = true; 1751 break; 1752 } 1753 } 1754 1755 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1756 if (err) 1757 return err; 1758 1759 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1760 } 1761 1762 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1763 const struct switchdev_obj_port_vlan *vlan) 1764 { 1765 struct mv88e6xxx_chip *chip = ds->priv; 1766 u16 pvid, vid; 1767 int err = 0; 1768 1769 if (!chip->info->max_vid) 1770 return -EOPNOTSUPP; 1771 1772 mutex_lock(&chip->reg_lock); 1773 1774 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1775 if (err) 1776 goto unlock; 1777 1778 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1779 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1780 if (err) 1781 goto unlock; 1782 1783 if (vid == pvid) { 1784 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1785 if (err) 1786 goto unlock; 1787 } 1788 } 1789 1790 unlock: 1791 mutex_unlock(&chip->reg_lock); 1792 1793 return err; 1794 } 1795 1796 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1797 const unsigned char *addr, u16 vid) 1798 { 1799 struct mv88e6xxx_chip *chip = ds->priv; 1800 int err; 1801 1802 mutex_lock(&chip->reg_lock); 1803 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1804 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1805 mutex_unlock(&chip->reg_lock); 1806 1807 return err; 1808 } 1809 1810 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1811 const unsigned char *addr, u16 vid) 1812 { 1813 struct mv88e6xxx_chip *chip = ds->priv; 1814 int err; 1815 1816 mutex_lock(&chip->reg_lock); 1817 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1818 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1819 mutex_unlock(&chip->reg_lock); 1820 1821 return err; 1822 } 1823 1824 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1825 u16 fid, u16 vid, int port, 1826 dsa_fdb_dump_cb_t *cb, void *data) 1827 { 1828 struct mv88e6xxx_atu_entry addr; 1829 bool is_static; 1830 int err; 1831 1832 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1833 eth_broadcast_addr(addr.mac); 1834 1835 do { 1836 mutex_lock(&chip->reg_lock); 1837 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1838 mutex_unlock(&chip->reg_lock); 1839 if (err) 1840 return err; 1841 1842 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1843 break; 1844 1845 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1846 continue; 1847 1848 if (!is_unicast_ether_addr(addr.mac)) 1849 continue; 1850 1851 is_static = (addr.state == 1852 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1853 err = cb(addr.mac, vid, is_static, data); 1854 if (err) 1855 return err; 1856 } while (!is_broadcast_ether_addr(addr.mac)); 1857 1858 return err; 1859 } 1860 1861 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1862 dsa_fdb_dump_cb_t *cb, void *data) 1863 { 1864 struct mv88e6xxx_vtu_entry vlan = { 1865 .vid = chip->info->max_vid, 1866 }; 1867 u16 fid; 1868 int err; 1869 1870 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1871 mutex_lock(&chip->reg_lock); 1872 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1873 mutex_unlock(&chip->reg_lock); 1874 1875 if (err) 1876 return err; 1877 1878 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1879 if (err) 1880 return err; 1881 1882 /* Dump VLANs' Filtering Information Databases */ 1883 do { 1884 mutex_lock(&chip->reg_lock); 1885 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1886 mutex_unlock(&chip->reg_lock); 1887 if (err) 1888 return err; 1889 1890 if (!vlan.valid) 1891 break; 1892 1893 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1894 cb, data); 1895 if (err) 1896 return err; 1897 } while (vlan.vid < chip->info->max_vid); 1898 1899 return err; 1900 } 1901 1902 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1903 dsa_fdb_dump_cb_t *cb, void *data) 1904 { 1905 struct mv88e6xxx_chip *chip = ds->priv; 1906 1907 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1908 } 1909 1910 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1911 struct net_device *br) 1912 { 1913 struct dsa_switch *ds; 1914 int port; 1915 int dev; 1916 int err; 1917 1918 /* Remap the Port VLAN of each local bridge group member */ 1919 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1920 if (chip->ds->ports[port].bridge_dev == br) { 1921 err = mv88e6xxx_port_vlan_map(chip, port); 1922 if (err) 1923 return err; 1924 } 1925 } 1926 1927 if (!mv88e6xxx_has_pvt(chip)) 1928 return 0; 1929 1930 /* Remap the Port VLAN of each cross-chip bridge group member */ 1931 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1932 ds = chip->ds->dst->ds[dev]; 1933 if (!ds) 1934 break; 1935 1936 for (port = 0; port < ds->num_ports; ++port) { 1937 if (ds->ports[port].bridge_dev == br) { 1938 err = mv88e6xxx_pvt_map(chip, dev, port); 1939 if (err) 1940 return err; 1941 } 1942 } 1943 } 1944 1945 return 0; 1946 } 1947 1948 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1949 struct net_device *br) 1950 { 1951 struct mv88e6xxx_chip *chip = ds->priv; 1952 int err; 1953 1954 mutex_lock(&chip->reg_lock); 1955 err = mv88e6xxx_bridge_map(chip, br); 1956 mutex_unlock(&chip->reg_lock); 1957 1958 return err; 1959 } 1960 1961 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1962 struct net_device *br) 1963 { 1964 struct mv88e6xxx_chip *chip = ds->priv; 1965 1966 mutex_lock(&chip->reg_lock); 1967 if (mv88e6xxx_bridge_map(chip, br) || 1968 mv88e6xxx_port_vlan_map(chip, port)) 1969 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1970 mutex_unlock(&chip->reg_lock); 1971 } 1972 1973 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1974 int port, struct net_device *br) 1975 { 1976 struct mv88e6xxx_chip *chip = ds->priv; 1977 int err; 1978 1979 if (!mv88e6xxx_has_pvt(chip)) 1980 return 0; 1981 1982 mutex_lock(&chip->reg_lock); 1983 err = mv88e6xxx_pvt_map(chip, dev, port); 1984 mutex_unlock(&chip->reg_lock); 1985 1986 return err; 1987 } 1988 1989 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1990 int port, struct net_device *br) 1991 { 1992 struct mv88e6xxx_chip *chip = ds->priv; 1993 1994 if (!mv88e6xxx_has_pvt(chip)) 1995 return; 1996 1997 mutex_lock(&chip->reg_lock); 1998 if (mv88e6xxx_pvt_map(chip, dev, port)) 1999 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2000 mutex_unlock(&chip->reg_lock); 2001 } 2002 2003 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2004 { 2005 if (chip->info->ops->reset) 2006 return chip->info->ops->reset(chip); 2007 2008 return 0; 2009 } 2010 2011 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2012 { 2013 struct gpio_desc *gpiod = chip->reset; 2014 2015 /* If there is a GPIO connected to the reset pin, toggle it */ 2016 if (gpiod) { 2017 gpiod_set_value_cansleep(gpiod, 1); 2018 usleep_range(10000, 20000); 2019 gpiod_set_value_cansleep(gpiod, 0); 2020 usleep_range(10000, 20000); 2021 } 2022 } 2023 2024 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2025 { 2026 int i, err; 2027 2028 /* Set all ports to the Disabled state */ 2029 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2030 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2031 if (err) 2032 return err; 2033 } 2034 2035 /* Wait for transmit queues to drain, 2036 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2037 */ 2038 usleep_range(2000, 4000); 2039 2040 return 0; 2041 } 2042 2043 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2044 { 2045 int err; 2046 2047 err = mv88e6xxx_disable_ports(chip); 2048 if (err) 2049 return err; 2050 2051 mv88e6xxx_hardware_reset(chip); 2052 2053 return mv88e6xxx_software_reset(chip); 2054 } 2055 2056 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2057 enum mv88e6xxx_frame_mode frame, 2058 enum mv88e6xxx_egress_mode egress, u16 etype) 2059 { 2060 int err; 2061 2062 if (!chip->info->ops->port_set_frame_mode) 2063 return -EOPNOTSUPP; 2064 2065 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2066 if (err) 2067 return err; 2068 2069 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2070 if (err) 2071 return err; 2072 2073 if (chip->info->ops->port_set_ether_type) 2074 return chip->info->ops->port_set_ether_type(chip, port, etype); 2075 2076 return 0; 2077 } 2078 2079 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2080 { 2081 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2082 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2083 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2084 } 2085 2086 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2087 { 2088 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2089 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2090 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2091 } 2092 2093 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2094 { 2095 return mv88e6xxx_set_port_mode(chip, port, 2096 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2097 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2098 ETH_P_EDSA); 2099 } 2100 2101 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2102 { 2103 if (dsa_is_dsa_port(chip->ds, port)) 2104 return mv88e6xxx_set_port_mode_dsa(chip, port); 2105 2106 if (dsa_is_user_port(chip->ds, port)) 2107 return mv88e6xxx_set_port_mode_normal(chip, port); 2108 2109 /* Setup CPU port mode depending on its supported tag format */ 2110 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2111 return mv88e6xxx_set_port_mode_dsa(chip, port); 2112 2113 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2114 return mv88e6xxx_set_port_mode_edsa(chip, port); 2115 2116 return -EINVAL; 2117 } 2118 2119 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2120 { 2121 bool message = dsa_is_dsa_port(chip->ds, port); 2122 2123 return mv88e6xxx_port_set_message_port(chip, port, message); 2124 } 2125 2126 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2127 { 2128 struct dsa_switch *ds = chip->ds; 2129 bool flood; 2130 2131 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2132 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2133 if (chip->info->ops->port_set_egress_floods) 2134 return chip->info->ops->port_set_egress_floods(chip, port, 2135 flood, flood); 2136 2137 return 0; 2138 } 2139 2140 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2141 bool on) 2142 { 2143 if (chip->info->ops->serdes_power) 2144 return chip->info->ops->serdes_power(chip, port, on); 2145 2146 return 0; 2147 } 2148 2149 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2150 { 2151 struct dsa_switch *ds = chip->ds; 2152 int upstream_port; 2153 int err; 2154 2155 upstream_port = dsa_upstream_port(ds, port); 2156 if (chip->info->ops->port_set_upstream_port) { 2157 err = chip->info->ops->port_set_upstream_port(chip, port, 2158 upstream_port); 2159 if (err) 2160 return err; 2161 } 2162 2163 if (port == upstream_port) { 2164 if (chip->info->ops->set_cpu_port) { 2165 err = chip->info->ops->set_cpu_port(chip, 2166 upstream_port); 2167 if (err) 2168 return err; 2169 } 2170 2171 if (chip->info->ops->set_egress_port) { 2172 err = chip->info->ops->set_egress_port(chip, 2173 upstream_port); 2174 if (err) 2175 return err; 2176 } 2177 } 2178 2179 return 0; 2180 } 2181 2182 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2183 { 2184 struct dsa_switch *ds = chip->ds; 2185 int err; 2186 u16 reg; 2187 2188 chip->ports[port].chip = chip; 2189 chip->ports[port].port = port; 2190 2191 /* MAC Forcing register: don't force link, speed, duplex or flow control 2192 * state to any particular values on physical ports, but force the CPU 2193 * port and all DSA ports to their maximum bandwidth and full duplex. 2194 */ 2195 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2196 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2197 SPEED_MAX, DUPLEX_FULL, 2198 PAUSE_OFF, 2199 PHY_INTERFACE_MODE_NA); 2200 else 2201 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2202 SPEED_UNFORCED, DUPLEX_UNFORCED, 2203 PAUSE_ON, 2204 PHY_INTERFACE_MODE_NA); 2205 if (err) 2206 return err; 2207 2208 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2209 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2210 * tunneling, determine priority by looking at 802.1p and IP 2211 * priority fields (IP prio has precedence), and set STP state 2212 * to Forwarding. 2213 * 2214 * If this is the CPU link, use DSA or EDSA tagging depending 2215 * on which tagging mode was configured. 2216 * 2217 * If this is a link to another switch, use DSA tagging mode. 2218 * 2219 * If this is the upstream port for this switch, enable 2220 * forwarding of unknown unicasts and multicasts. 2221 */ 2222 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2223 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2224 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2225 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2226 if (err) 2227 return err; 2228 2229 err = mv88e6xxx_setup_port_mode(chip, port); 2230 if (err) 2231 return err; 2232 2233 err = mv88e6xxx_setup_egress_floods(chip, port); 2234 if (err) 2235 return err; 2236 2237 /* Enable the SERDES interface for DSA and CPU ports. Normal 2238 * ports SERDES are enabled when the port is enabled, thus 2239 * saving a bit of power. 2240 */ 2241 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2242 err = mv88e6xxx_serdes_power(chip, port, true); 2243 if (err) 2244 return err; 2245 } 2246 2247 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2248 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2249 * untagged frames on this port, do a destination address lookup on all 2250 * received packets as usual, disable ARP mirroring and don't send a 2251 * copy of all transmitted/received frames on this port to the CPU. 2252 */ 2253 err = mv88e6xxx_port_set_map_da(chip, port); 2254 if (err) 2255 return err; 2256 2257 err = mv88e6xxx_setup_upstream_port(chip, port); 2258 if (err) 2259 return err; 2260 2261 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2262 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2263 if (err) 2264 return err; 2265 2266 if (chip->info->ops->port_set_jumbo_size) { 2267 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2268 if (err) 2269 return err; 2270 } 2271 2272 /* Port Association Vector: when learning source addresses 2273 * of packets, add the address to the address database using 2274 * a port bitmap that has only the bit for this port set and 2275 * the other bits clear. 2276 */ 2277 reg = 1 << port; 2278 /* Disable learning for CPU port */ 2279 if (dsa_is_cpu_port(ds, port)) 2280 reg = 0; 2281 2282 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2283 reg); 2284 if (err) 2285 return err; 2286 2287 /* Egress rate control 2: disable egress rate control. */ 2288 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2289 0x0000); 2290 if (err) 2291 return err; 2292 2293 if (chip->info->ops->port_pause_limit) { 2294 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2295 if (err) 2296 return err; 2297 } 2298 2299 if (chip->info->ops->port_disable_learn_limit) { 2300 err = chip->info->ops->port_disable_learn_limit(chip, port); 2301 if (err) 2302 return err; 2303 } 2304 2305 if (chip->info->ops->port_disable_pri_override) { 2306 err = chip->info->ops->port_disable_pri_override(chip, port); 2307 if (err) 2308 return err; 2309 } 2310 2311 if (chip->info->ops->port_tag_remap) { 2312 err = chip->info->ops->port_tag_remap(chip, port); 2313 if (err) 2314 return err; 2315 } 2316 2317 if (chip->info->ops->port_egress_rate_limiting) { 2318 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2319 if (err) 2320 return err; 2321 } 2322 2323 err = mv88e6xxx_setup_message_port(chip, port); 2324 if (err) 2325 return err; 2326 2327 /* Port based VLAN map: give each port the same default address 2328 * database, and allow bidirectional communication between the 2329 * CPU and DSA port(s), and the other ports. 2330 */ 2331 err = mv88e6xxx_port_set_fid(chip, port, 0); 2332 if (err) 2333 return err; 2334 2335 err = mv88e6xxx_port_vlan_map(chip, port); 2336 if (err) 2337 return err; 2338 2339 /* Default VLAN ID and priority: don't set a default VLAN 2340 * ID, and set the default packet priority to zero. 2341 */ 2342 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2343 } 2344 2345 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2346 struct phy_device *phydev) 2347 { 2348 struct mv88e6xxx_chip *chip = ds->priv; 2349 int err; 2350 2351 mutex_lock(&chip->reg_lock); 2352 2353 err = mv88e6xxx_serdes_power(chip, port, true); 2354 2355 if (!err && chip->info->ops->serdes_irq_setup) 2356 err = chip->info->ops->serdes_irq_setup(chip, port); 2357 2358 mutex_unlock(&chip->reg_lock); 2359 2360 return err; 2361 } 2362 2363 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 2364 struct phy_device *phydev) 2365 { 2366 struct mv88e6xxx_chip *chip = ds->priv; 2367 2368 mutex_lock(&chip->reg_lock); 2369 2370 if (chip->info->ops->serdes_irq_free) 2371 chip->info->ops->serdes_irq_free(chip, port); 2372 2373 if (mv88e6xxx_serdes_power(chip, port, false)) 2374 dev_err(chip->dev, "failed to power off SERDES\n"); 2375 2376 mutex_unlock(&chip->reg_lock); 2377 } 2378 2379 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2380 unsigned int ageing_time) 2381 { 2382 struct mv88e6xxx_chip *chip = ds->priv; 2383 int err; 2384 2385 mutex_lock(&chip->reg_lock); 2386 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2387 mutex_unlock(&chip->reg_lock); 2388 2389 return err; 2390 } 2391 2392 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2393 { 2394 int err; 2395 2396 /* Initialize the statistics unit */ 2397 if (chip->info->ops->stats_set_histogram) { 2398 err = chip->info->ops->stats_set_histogram(chip); 2399 if (err) 2400 return err; 2401 } 2402 2403 return mv88e6xxx_g1_stats_clear(chip); 2404 } 2405 2406 static int mv88e6xxx_setup(struct dsa_switch *ds) 2407 { 2408 struct mv88e6xxx_chip *chip = ds->priv; 2409 u8 cmode; 2410 int err; 2411 int i; 2412 2413 chip->ds = ds; 2414 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2415 2416 mutex_lock(&chip->reg_lock); 2417 2418 /* Cache the cmode of each port. */ 2419 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2420 if (chip->info->ops->port_get_cmode) { 2421 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2422 if (err) 2423 goto unlock; 2424 2425 chip->ports[i].cmode = cmode; 2426 } 2427 } 2428 2429 /* Setup Switch Port Registers */ 2430 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2431 if (dsa_is_unused_port(ds, i)) 2432 continue; 2433 2434 err = mv88e6xxx_setup_port(chip, i); 2435 if (err) 2436 goto unlock; 2437 } 2438 2439 err = mv88e6xxx_irl_setup(chip); 2440 if (err) 2441 goto unlock; 2442 2443 err = mv88e6xxx_mac_setup(chip); 2444 if (err) 2445 goto unlock; 2446 2447 err = mv88e6xxx_phy_setup(chip); 2448 if (err) 2449 goto unlock; 2450 2451 err = mv88e6xxx_vtu_setup(chip); 2452 if (err) 2453 goto unlock; 2454 2455 err = mv88e6xxx_pvt_setup(chip); 2456 if (err) 2457 goto unlock; 2458 2459 err = mv88e6xxx_atu_setup(chip); 2460 if (err) 2461 goto unlock; 2462 2463 err = mv88e6xxx_broadcast_setup(chip, 0); 2464 if (err) 2465 goto unlock; 2466 2467 err = mv88e6xxx_pot_setup(chip); 2468 if (err) 2469 goto unlock; 2470 2471 err = mv88e6xxx_rmu_setup(chip); 2472 if (err) 2473 goto unlock; 2474 2475 err = mv88e6xxx_rsvd2cpu_setup(chip); 2476 if (err) 2477 goto unlock; 2478 2479 err = mv88e6xxx_trunk_setup(chip); 2480 if (err) 2481 goto unlock; 2482 2483 err = mv88e6xxx_devmap_setup(chip); 2484 if (err) 2485 goto unlock; 2486 2487 err = mv88e6xxx_pri_setup(chip); 2488 if (err) 2489 goto unlock; 2490 2491 /* Setup PTP Hardware Clock and timestamping */ 2492 if (chip->info->ptp_support) { 2493 err = mv88e6xxx_ptp_setup(chip); 2494 if (err) 2495 goto unlock; 2496 2497 err = mv88e6xxx_hwtstamp_setup(chip); 2498 if (err) 2499 goto unlock; 2500 } 2501 2502 err = mv88e6xxx_stats_setup(chip); 2503 if (err) 2504 goto unlock; 2505 2506 unlock: 2507 mutex_unlock(&chip->reg_lock); 2508 2509 return err; 2510 } 2511 2512 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2513 { 2514 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2515 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2516 u16 val; 2517 int err; 2518 2519 if (!chip->info->ops->phy_read) 2520 return -EOPNOTSUPP; 2521 2522 mutex_lock(&chip->reg_lock); 2523 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2524 mutex_unlock(&chip->reg_lock); 2525 2526 if (reg == MII_PHYSID2) { 2527 /* Some internal PHYs don't have a model number. */ 2528 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2529 /* Then there is the 6165 family. It gets is 2530 * PHYs correct. But it can also have two 2531 * SERDES interfaces in the PHY address 2532 * space. And these don't have a model 2533 * number. But they are not PHYs, so we don't 2534 * want to give them something a PHY driver 2535 * will recognise. 2536 * 2537 * Use the mv88e6390 family model number 2538 * instead, for anything which really could be 2539 * a PHY, 2540 */ 2541 if (!(val & 0x3f0)) 2542 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2543 } 2544 2545 return err ? err : val; 2546 } 2547 2548 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2549 { 2550 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2551 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2552 int err; 2553 2554 if (!chip->info->ops->phy_write) 2555 return -EOPNOTSUPP; 2556 2557 mutex_lock(&chip->reg_lock); 2558 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2559 mutex_unlock(&chip->reg_lock); 2560 2561 return err; 2562 } 2563 2564 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2565 struct device_node *np, 2566 bool external) 2567 { 2568 static int index; 2569 struct mv88e6xxx_mdio_bus *mdio_bus; 2570 struct mii_bus *bus; 2571 int err; 2572 2573 if (external) { 2574 mutex_lock(&chip->reg_lock); 2575 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2576 mutex_unlock(&chip->reg_lock); 2577 2578 if (err) 2579 return err; 2580 } 2581 2582 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2583 if (!bus) 2584 return -ENOMEM; 2585 2586 mdio_bus = bus->priv; 2587 mdio_bus->bus = bus; 2588 mdio_bus->chip = chip; 2589 INIT_LIST_HEAD(&mdio_bus->list); 2590 mdio_bus->external = external; 2591 2592 if (np) { 2593 bus->name = np->full_name; 2594 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2595 } else { 2596 bus->name = "mv88e6xxx SMI"; 2597 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2598 } 2599 2600 bus->read = mv88e6xxx_mdio_read; 2601 bus->write = mv88e6xxx_mdio_write; 2602 bus->parent = chip->dev; 2603 2604 if (!external) { 2605 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2606 if (err) 2607 return err; 2608 } 2609 2610 err = of_mdiobus_register(bus, np); 2611 if (err) { 2612 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2613 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2614 return err; 2615 } 2616 2617 if (external) 2618 list_add_tail(&mdio_bus->list, &chip->mdios); 2619 else 2620 list_add(&mdio_bus->list, &chip->mdios); 2621 2622 return 0; 2623 } 2624 2625 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2626 { .compatible = "marvell,mv88e6xxx-mdio-external", 2627 .data = (void *)true }, 2628 { }, 2629 }; 2630 2631 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2632 2633 { 2634 struct mv88e6xxx_mdio_bus *mdio_bus; 2635 struct mii_bus *bus; 2636 2637 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2638 bus = mdio_bus->bus; 2639 2640 if (!mdio_bus->external) 2641 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2642 2643 mdiobus_unregister(bus); 2644 } 2645 } 2646 2647 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2648 struct device_node *np) 2649 { 2650 const struct of_device_id *match; 2651 struct device_node *child; 2652 int err; 2653 2654 /* Always register one mdio bus for the internal/default mdio 2655 * bus. This maybe represented in the device tree, but is 2656 * optional. 2657 */ 2658 child = of_get_child_by_name(np, "mdio"); 2659 err = mv88e6xxx_mdio_register(chip, child, false); 2660 if (err) 2661 return err; 2662 2663 /* Walk the device tree, and see if there are any other nodes 2664 * which say they are compatible with the external mdio 2665 * bus. 2666 */ 2667 for_each_available_child_of_node(np, child) { 2668 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2669 if (match) { 2670 err = mv88e6xxx_mdio_register(chip, child, true); 2671 if (err) { 2672 mv88e6xxx_mdios_unregister(chip); 2673 return err; 2674 } 2675 } 2676 } 2677 2678 return 0; 2679 } 2680 2681 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2682 { 2683 struct mv88e6xxx_chip *chip = ds->priv; 2684 2685 return chip->eeprom_len; 2686 } 2687 2688 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2689 struct ethtool_eeprom *eeprom, u8 *data) 2690 { 2691 struct mv88e6xxx_chip *chip = ds->priv; 2692 int err; 2693 2694 if (!chip->info->ops->get_eeprom) 2695 return -EOPNOTSUPP; 2696 2697 mutex_lock(&chip->reg_lock); 2698 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2699 mutex_unlock(&chip->reg_lock); 2700 2701 if (err) 2702 return err; 2703 2704 eeprom->magic = 0xc3ec4951; 2705 2706 return 0; 2707 } 2708 2709 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2710 struct ethtool_eeprom *eeprom, u8 *data) 2711 { 2712 struct mv88e6xxx_chip *chip = ds->priv; 2713 int err; 2714 2715 if (!chip->info->ops->set_eeprom) 2716 return -EOPNOTSUPP; 2717 2718 if (eeprom->magic != 0xc3ec4951) 2719 return -EINVAL; 2720 2721 mutex_lock(&chip->reg_lock); 2722 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2723 mutex_unlock(&chip->reg_lock); 2724 2725 return err; 2726 } 2727 2728 static const struct mv88e6xxx_ops mv88e6085_ops = { 2729 /* MV88E6XXX_FAMILY_6097 */ 2730 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2731 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2732 .irl_init_all = mv88e6352_g2_irl_init_all, 2733 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2734 .phy_read = mv88e6185_phy_ppu_read, 2735 .phy_write = mv88e6185_phy_ppu_write, 2736 .port_set_link = mv88e6xxx_port_set_link, 2737 .port_set_duplex = mv88e6xxx_port_set_duplex, 2738 .port_set_speed = mv88e6185_port_set_speed, 2739 .port_tag_remap = mv88e6095_port_tag_remap, 2740 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2741 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2742 .port_set_ether_type = mv88e6351_port_set_ether_type, 2743 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2744 .port_pause_limit = mv88e6097_port_pause_limit, 2745 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2746 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2747 .port_link_state = mv88e6352_port_link_state, 2748 .port_get_cmode = mv88e6185_port_get_cmode, 2749 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2750 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2751 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2752 .stats_get_strings = mv88e6095_stats_get_strings, 2753 .stats_get_stats = mv88e6095_stats_get_stats, 2754 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2755 .set_egress_port = mv88e6095_g1_set_egress_port, 2756 .watchdog_ops = &mv88e6097_watchdog_ops, 2757 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2758 .pot_clear = mv88e6xxx_g2_pot_clear, 2759 .ppu_enable = mv88e6185_g1_ppu_enable, 2760 .ppu_disable = mv88e6185_g1_ppu_disable, 2761 .reset = mv88e6185_g1_reset, 2762 .rmu_disable = mv88e6085_g1_rmu_disable, 2763 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2764 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2765 .phylink_validate = mv88e6185_phylink_validate, 2766 }; 2767 2768 static const struct mv88e6xxx_ops mv88e6095_ops = { 2769 /* MV88E6XXX_FAMILY_6095 */ 2770 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2771 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2772 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2773 .phy_read = mv88e6185_phy_ppu_read, 2774 .phy_write = mv88e6185_phy_ppu_write, 2775 .port_set_link = mv88e6xxx_port_set_link, 2776 .port_set_duplex = mv88e6xxx_port_set_duplex, 2777 .port_set_speed = mv88e6185_port_set_speed, 2778 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2779 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2780 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2781 .port_link_state = mv88e6185_port_link_state, 2782 .port_get_cmode = mv88e6185_port_get_cmode, 2783 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2784 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2785 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2786 .stats_get_strings = mv88e6095_stats_get_strings, 2787 .stats_get_stats = mv88e6095_stats_get_stats, 2788 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2789 .ppu_enable = mv88e6185_g1_ppu_enable, 2790 .ppu_disable = mv88e6185_g1_ppu_disable, 2791 .reset = mv88e6185_g1_reset, 2792 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2793 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2794 .phylink_validate = mv88e6185_phylink_validate, 2795 }; 2796 2797 static const struct mv88e6xxx_ops mv88e6097_ops = { 2798 /* MV88E6XXX_FAMILY_6097 */ 2799 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2800 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2801 .irl_init_all = mv88e6352_g2_irl_init_all, 2802 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2803 .phy_read = mv88e6xxx_g2_smi_phy_read, 2804 .phy_write = mv88e6xxx_g2_smi_phy_write, 2805 .port_set_link = mv88e6xxx_port_set_link, 2806 .port_set_duplex = mv88e6xxx_port_set_duplex, 2807 .port_set_speed = mv88e6185_port_set_speed, 2808 .port_tag_remap = mv88e6095_port_tag_remap, 2809 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2810 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2811 .port_set_ether_type = mv88e6351_port_set_ether_type, 2812 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2813 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2814 .port_pause_limit = mv88e6097_port_pause_limit, 2815 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2816 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2817 .port_link_state = mv88e6352_port_link_state, 2818 .port_get_cmode = mv88e6185_port_get_cmode, 2819 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2820 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2821 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2822 .stats_get_strings = mv88e6095_stats_get_strings, 2823 .stats_get_stats = mv88e6095_stats_get_stats, 2824 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2825 .set_egress_port = mv88e6095_g1_set_egress_port, 2826 .watchdog_ops = &mv88e6097_watchdog_ops, 2827 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2828 .pot_clear = mv88e6xxx_g2_pot_clear, 2829 .reset = mv88e6352_g1_reset, 2830 .rmu_disable = mv88e6085_g1_rmu_disable, 2831 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2832 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2833 .phylink_validate = mv88e6185_phylink_validate, 2834 }; 2835 2836 static const struct mv88e6xxx_ops mv88e6123_ops = { 2837 /* MV88E6XXX_FAMILY_6165 */ 2838 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2839 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2840 .irl_init_all = mv88e6352_g2_irl_init_all, 2841 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2842 .phy_read = mv88e6xxx_g2_smi_phy_read, 2843 .phy_write = mv88e6xxx_g2_smi_phy_write, 2844 .port_set_link = mv88e6xxx_port_set_link, 2845 .port_set_duplex = mv88e6xxx_port_set_duplex, 2846 .port_set_speed = mv88e6185_port_set_speed, 2847 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2848 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2849 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2850 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2851 .port_link_state = mv88e6352_port_link_state, 2852 .port_get_cmode = mv88e6185_port_get_cmode, 2853 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2854 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2855 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2856 .stats_get_strings = mv88e6095_stats_get_strings, 2857 .stats_get_stats = mv88e6095_stats_get_stats, 2858 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2859 .set_egress_port = mv88e6095_g1_set_egress_port, 2860 .watchdog_ops = &mv88e6097_watchdog_ops, 2861 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2862 .pot_clear = mv88e6xxx_g2_pot_clear, 2863 .reset = mv88e6352_g1_reset, 2864 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2865 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2866 .phylink_validate = mv88e6185_phylink_validate, 2867 }; 2868 2869 static const struct mv88e6xxx_ops mv88e6131_ops = { 2870 /* MV88E6XXX_FAMILY_6185 */ 2871 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2872 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2873 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2874 .phy_read = mv88e6185_phy_ppu_read, 2875 .phy_write = mv88e6185_phy_ppu_write, 2876 .port_set_link = mv88e6xxx_port_set_link, 2877 .port_set_duplex = mv88e6xxx_port_set_duplex, 2878 .port_set_speed = mv88e6185_port_set_speed, 2879 .port_tag_remap = mv88e6095_port_tag_remap, 2880 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2881 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2882 .port_set_ether_type = mv88e6351_port_set_ether_type, 2883 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2884 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2885 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2886 .port_pause_limit = mv88e6097_port_pause_limit, 2887 .port_set_pause = mv88e6185_port_set_pause, 2888 .port_link_state = mv88e6352_port_link_state, 2889 .port_get_cmode = mv88e6185_port_get_cmode, 2890 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2891 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2892 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2893 .stats_get_strings = mv88e6095_stats_get_strings, 2894 .stats_get_stats = mv88e6095_stats_get_stats, 2895 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2896 .set_egress_port = mv88e6095_g1_set_egress_port, 2897 .watchdog_ops = &mv88e6097_watchdog_ops, 2898 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2899 .ppu_enable = mv88e6185_g1_ppu_enable, 2900 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2901 .ppu_disable = mv88e6185_g1_ppu_disable, 2902 .reset = mv88e6185_g1_reset, 2903 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2904 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2905 .phylink_validate = mv88e6185_phylink_validate, 2906 }; 2907 2908 static const struct mv88e6xxx_ops mv88e6141_ops = { 2909 /* MV88E6XXX_FAMILY_6341 */ 2910 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2911 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2912 .irl_init_all = mv88e6352_g2_irl_init_all, 2913 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2914 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2915 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2916 .phy_read = mv88e6xxx_g2_smi_phy_read, 2917 .phy_write = mv88e6xxx_g2_smi_phy_write, 2918 .port_set_link = mv88e6xxx_port_set_link, 2919 .port_set_duplex = mv88e6xxx_port_set_duplex, 2920 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2921 .port_set_speed = mv88e6341_port_set_speed, 2922 .port_tag_remap = mv88e6095_port_tag_remap, 2923 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2924 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2925 .port_set_ether_type = mv88e6351_port_set_ether_type, 2926 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2927 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2928 .port_pause_limit = mv88e6097_port_pause_limit, 2929 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2930 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2931 .port_link_state = mv88e6352_port_link_state, 2932 .port_get_cmode = mv88e6352_port_get_cmode, 2933 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2934 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2935 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2936 .stats_get_strings = mv88e6320_stats_get_strings, 2937 .stats_get_stats = mv88e6390_stats_get_stats, 2938 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2939 .set_egress_port = mv88e6390_g1_set_egress_port, 2940 .watchdog_ops = &mv88e6390_watchdog_ops, 2941 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2942 .pot_clear = mv88e6xxx_g2_pot_clear, 2943 .reset = mv88e6352_g1_reset, 2944 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2945 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2946 .serdes_power = mv88e6341_serdes_power, 2947 .gpio_ops = &mv88e6352_gpio_ops, 2948 .phylink_validate = mv88e6390_phylink_validate, 2949 }; 2950 2951 static const struct mv88e6xxx_ops mv88e6161_ops = { 2952 /* MV88E6XXX_FAMILY_6165 */ 2953 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2954 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2955 .irl_init_all = mv88e6352_g2_irl_init_all, 2956 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2957 .phy_read = mv88e6xxx_g2_smi_phy_read, 2958 .phy_write = mv88e6xxx_g2_smi_phy_write, 2959 .port_set_link = mv88e6xxx_port_set_link, 2960 .port_set_duplex = mv88e6xxx_port_set_duplex, 2961 .port_set_speed = mv88e6185_port_set_speed, 2962 .port_tag_remap = mv88e6095_port_tag_remap, 2963 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2964 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2965 .port_set_ether_type = mv88e6351_port_set_ether_type, 2966 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2967 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2968 .port_pause_limit = mv88e6097_port_pause_limit, 2969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2971 .port_link_state = mv88e6352_port_link_state, 2972 .port_get_cmode = mv88e6185_port_get_cmode, 2973 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2974 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2975 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2976 .stats_get_strings = mv88e6095_stats_get_strings, 2977 .stats_get_stats = mv88e6095_stats_get_stats, 2978 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2979 .set_egress_port = mv88e6095_g1_set_egress_port, 2980 .watchdog_ops = &mv88e6097_watchdog_ops, 2981 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2982 .pot_clear = mv88e6xxx_g2_pot_clear, 2983 .reset = mv88e6352_g1_reset, 2984 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2985 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2986 .avb_ops = &mv88e6165_avb_ops, 2987 .ptp_ops = &mv88e6165_ptp_ops, 2988 .phylink_validate = mv88e6185_phylink_validate, 2989 }; 2990 2991 static const struct mv88e6xxx_ops mv88e6165_ops = { 2992 /* MV88E6XXX_FAMILY_6165 */ 2993 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2994 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2995 .irl_init_all = mv88e6352_g2_irl_init_all, 2996 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2997 .phy_read = mv88e6165_phy_read, 2998 .phy_write = mv88e6165_phy_write, 2999 .port_set_link = mv88e6xxx_port_set_link, 3000 .port_set_duplex = mv88e6xxx_port_set_duplex, 3001 .port_set_speed = mv88e6185_port_set_speed, 3002 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3003 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3004 .port_link_state = mv88e6352_port_link_state, 3005 .port_get_cmode = mv88e6185_port_get_cmode, 3006 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3007 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3008 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3009 .stats_get_strings = mv88e6095_stats_get_strings, 3010 .stats_get_stats = mv88e6095_stats_get_stats, 3011 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3012 .set_egress_port = mv88e6095_g1_set_egress_port, 3013 .watchdog_ops = &mv88e6097_watchdog_ops, 3014 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3015 .pot_clear = mv88e6xxx_g2_pot_clear, 3016 .reset = mv88e6352_g1_reset, 3017 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3018 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3019 .avb_ops = &mv88e6165_avb_ops, 3020 .ptp_ops = &mv88e6165_ptp_ops, 3021 .phylink_validate = mv88e6185_phylink_validate, 3022 }; 3023 3024 static const struct mv88e6xxx_ops mv88e6171_ops = { 3025 /* MV88E6XXX_FAMILY_6351 */ 3026 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3027 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3028 .irl_init_all = mv88e6352_g2_irl_init_all, 3029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3030 .phy_read = mv88e6xxx_g2_smi_phy_read, 3031 .phy_write = mv88e6xxx_g2_smi_phy_write, 3032 .port_set_link = mv88e6xxx_port_set_link, 3033 .port_set_duplex = mv88e6xxx_port_set_duplex, 3034 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3035 .port_set_speed = mv88e6185_port_set_speed, 3036 .port_tag_remap = mv88e6095_port_tag_remap, 3037 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3038 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3039 .port_set_ether_type = mv88e6351_port_set_ether_type, 3040 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3041 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3042 .port_pause_limit = mv88e6097_port_pause_limit, 3043 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3044 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3045 .port_link_state = mv88e6352_port_link_state, 3046 .port_get_cmode = mv88e6352_port_get_cmode, 3047 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3048 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3049 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3050 .stats_get_strings = mv88e6095_stats_get_strings, 3051 .stats_get_stats = mv88e6095_stats_get_stats, 3052 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3053 .set_egress_port = mv88e6095_g1_set_egress_port, 3054 .watchdog_ops = &mv88e6097_watchdog_ops, 3055 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3056 .pot_clear = mv88e6xxx_g2_pot_clear, 3057 .reset = mv88e6352_g1_reset, 3058 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3059 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3060 .phylink_validate = mv88e6185_phylink_validate, 3061 }; 3062 3063 static const struct mv88e6xxx_ops mv88e6172_ops = { 3064 /* MV88E6XXX_FAMILY_6352 */ 3065 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3066 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3067 .irl_init_all = mv88e6352_g2_irl_init_all, 3068 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3069 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3070 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3071 .phy_read = mv88e6xxx_g2_smi_phy_read, 3072 .phy_write = mv88e6xxx_g2_smi_phy_write, 3073 .port_set_link = mv88e6xxx_port_set_link, 3074 .port_set_duplex = mv88e6xxx_port_set_duplex, 3075 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3076 .port_set_speed = mv88e6352_port_set_speed, 3077 .port_tag_remap = mv88e6095_port_tag_remap, 3078 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3079 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3080 .port_set_ether_type = mv88e6351_port_set_ether_type, 3081 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3082 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3083 .port_pause_limit = mv88e6097_port_pause_limit, 3084 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3085 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3086 .port_link_state = mv88e6352_port_link_state, 3087 .port_get_cmode = mv88e6352_port_get_cmode, 3088 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3089 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3090 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3091 .stats_get_strings = mv88e6095_stats_get_strings, 3092 .stats_get_stats = mv88e6095_stats_get_stats, 3093 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3094 .set_egress_port = mv88e6095_g1_set_egress_port, 3095 .watchdog_ops = &mv88e6097_watchdog_ops, 3096 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3097 .pot_clear = mv88e6xxx_g2_pot_clear, 3098 .reset = mv88e6352_g1_reset, 3099 .rmu_disable = mv88e6352_g1_rmu_disable, 3100 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3101 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3102 .serdes_power = mv88e6352_serdes_power, 3103 .gpio_ops = &mv88e6352_gpio_ops, 3104 .phylink_validate = mv88e6352_phylink_validate, 3105 }; 3106 3107 static const struct mv88e6xxx_ops mv88e6175_ops = { 3108 /* MV88E6XXX_FAMILY_6351 */ 3109 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3110 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3111 .irl_init_all = mv88e6352_g2_irl_init_all, 3112 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3113 .phy_read = mv88e6xxx_g2_smi_phy_read, 3114 .phy_write = mv88e6xxx_g2_smi_phy_write, 3115 .port_set_link = mv88e6xxx_port_set_link, 3116 .port_set_duplex = mv88e6xxx_port_set_duplex, 3117 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3118 .port_set_speed = mv88e6185_port_set_speed, 3119 .port_tag_remap = mv88e6095_port_tag_remap, 3120 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3121 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3122 .port_set_ether_type = mv88e6351_port_set_ether_type, 3123 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3124 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3125 .port_pause_limit = mv88e6097_port_pause_limit, 3126 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3127 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3128 .port_link_state = mv88e6352_port_link_state, 3129 .port_get_cmode = mv88e6352_port_get_cmode, 3130 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3131 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3132 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3133 .stats_get_strings = mv88e6095_stats_get_strings, 3134 .stats_get_stats = mv88e6095_stats_get_stats, 3135 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3136 .set_egress_port = mv88e6095_g1_set_egress_port, 3137 .watchdog_ops = &mv88e6097_watchdog_ops, 3138 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3139 .pot_clear = mv88e6xxx_g2_pot_clear, 3140 .reset = mv88e6352_g1_reset, 3141 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3142 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3143 .phylink_validate = mv88e6185_phylink_validate, 3144 }; 3145 3146 static const struct mv88e6xxx_ops mv88e6176_ops = { 3147 /* MV88E6XXX_FAMILY_6352 */ 3148 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3149 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3150 .irl_init_all = mv88e6352_g2_irl_init_all, 3151 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3152 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3153 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3154 .phy_read = mv88e6xxx_g2_smi_phy_read, 3155 .phy_write = mv88e6xxx_g2_smi_phy_write, 3156 .port_set_link = mv88e6xxx_port_set_link, 3157 .port_set_duplex = mv88e6xxx_port_set_duplex, 3158 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3159 .port_set_speed = mv88e6352_port_set_speed, 3160 .port_tag_remap = mv88e6095_port_tag_remap, 3161 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3162 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3163 .port_set_ether_type = mv88e6351_port_set_ether_type, 3164 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3165 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3166 .port_pause_limit = mv88e6097_port_pause_limit, 3167 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3168 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3169 .port_link_state = mv88e6352_port_link_state, 3170 .port_get_cmode = mv88e6352_port_get_cmode, 3171 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3172 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3173 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3174 .stats_get_strings = mv88e6095_stats_get_strings, 3175 .stats_get_stats = mv88e6095_stats_get_stats, 3176 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3177 .set_egress_port = mv88e6095_g1_set_egress_port, 3178 .watchdog_ops = &mv88e6097_watchdog_ops, 3179 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3180 .pot_clear = mv88e6xxx_g2_pot_clear, 3181 .reset = mv88e6352_g1_reset, 3182 .rmu_disable = mv88e6352_g1_rmu_disable, 3183 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3184 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3185 .serdes_power = mv88e6352_serdes_power, 3186 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3187 .serdes_irq_free = mv88e6352_serdes_irq_free, 3188 .gpio_ops = &mv88e6352_gpio_ops, 3189 .phylink_validate = mv88e6352_phylink_validate, 3190 }; 3191 3192 static const struct mv88e6xxx_ops mv88e6185_ops = { 3193 /* MV88E6XXX_FAMILY_6185 */ 3194 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3195 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3196 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3197 .phy_read = mv88e6185_phy_ppu_read, 3198 .phy_write = mv88e6185_phy_ppu_write, 3199 .port_set_link = mv88e6xxx_port_set_link, 3200 .port_set_duplex = mv88e6xxx_port_set_duplex, 3201 .port_set_speed = mv88e6185_port_set_speed, 3202 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3203 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3204 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3205 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3206 .port_set_pause = mv88e6185_port_set_pause, 3207 .port_link_state = mv88e6185_port_link_state, 3208 .port_get_cmode = mv88e6185_port_get_cmode, 3209 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3210 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3211 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3212 .stats_get_strings = mv88e6095_stats_get_strings, 3213 .stats_get_stats = mv88e6095_stats_get_stats, 3214 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3215 .set_egress_port = mv88e6095_g1_set_egress_port, 3216 .watchdog_ops = &mv88e6097_watchdog_ops, 3217 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3218 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3219 .ppu_enable = mv88e6185_g1_ppu_enable, 3220 .ppu_disable = mv88e6185_g1_ppu_disable, 3221 .reset = mv88e6185_g1_reset, 3222 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3223 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3224 .phylink_validate = mv88e6185_phylink_validate, 3225 }; 3226 3227 static const struct mv88e6xxx_ops mv88e6190_ops = { 3228 /* MV88E6XXX_FAMILY_6390 */ 3229 .irl_init_all = mv88e6390_g2_irl_init_all, 3230 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3231 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3232 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3233 .phy_read = mv88e6xxx_g2_smi_phy_read, 3234 .phy_write = mv88e6xxx_g2_smi_phy_write, 3235 .port_set_link = mv88e6xxx_port_set_link, 3236 .port_set_duplex = mv88e6xxx_port_set_duplex, 3237 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3238 .port_set_speed = mv88e6390_port_set_speed, 3239 .port_tag_remap = mv88e6390_port_tag_remap, 3240 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3241 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3242 .port_set_ether_type = mv88e6351_port_set_ether_type, 3243 .port_pause_limit = mv88e6390_port_pause_limit, 3244 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3245 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3246 .port_link_state = mv88e6352_port_link_state, 3247 .port_get_cmode = mv88e6352_port_get_cmode, 3248 .port_set_cmode = mv88e6390_port_set_cmode, 3249 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3250 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3251 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3252 .stats_get_strings = mv88e6320_stats_get_strings, 3253 .stats_get_stats = mv88e6390_stats_get_stats, 3254 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3255 .set_egress_port = mv88e6390_g1_set_egress_port, 3256 .watchdog_ops = &mv88e6390_watchdog_ops, 3257 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3258 .pot_clear = mv88e6xxx_g2_pot_clear, 3259 .reset = mv88e6352_g1_reset, 3260 .rmu_disable = mv88e6390_g1_rmu_disable, 3261 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3262 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3263 .serdes_power = mv88e6390_serdes_power, 3264 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3265 .serdes_irq_free = mv88e6390_serdes_irq_free, 3266 .gpio_ops = &mv88e6352_gpio_ops, 3267 .phylink_validate = mv88e6390_phylink_validate, 3268 }; 3269 3270 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3271 /* MV88E6XXX_FAMILY_6390 */ 3272 .irl_init_all = mv88e6390_g2_irl_init_all, 3273 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3274 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3275 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3276 .phy_read = mv88e6xxx_g2_smi_phy_read, 3277 .phy_write = mv88e6xxx_g2_smi_phy_write, 3278 .port_set_link = mv88e6xxx_port_set_link, 3279 .port_set_duplex = mv88e6xxx_port_set_duplex, 3280 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3281 .port_set_speed = mv88e6390x_port_set_speed, 3282 .port_tag_remap = mv88e6390_port_tag_remap, 3283 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3284 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3285 .port_set_ether_type = mv88e6351_port_set_ether_type, 3286 .port_pause_limit = mv88e6390_port_pause_limit, 3287 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3288 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3289 .port_link_state = mv88e6352_port_link_state, 3290 .port_get_cmode = mv88e6352_port_get_cmode, 3291 .port_set_cmode = mv88e6390x_port_set_cmode, 3292 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3293 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3294 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3295 .stats_get_strings = mv88e6320_stats_get_strings, 3296 .stats_get_stats = mv88e6390_stats_get_stats, 3297 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3298 .set_egress_port = mv88e6390_g1_set_egress_port, 3299 .watchdog_ops = &mv88e6390_watchdog_ops, 3300 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3301 .pot_clear = mv88e6xxx_g2_pot_clear, 3302 .reset = mv88e6352_g1_reset, 3303 .rmu_disable = mv88e6390_g1_rmu_disable, 3304 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3305 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3306 .serdes_power = mv88e6390x_serdes_power, 3307 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3308 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3309 .gpio_ops = &mv88e6352_gpio_ops, 3310 .phylink_validate = mv88e6390x_phylink_validate, 3311 }; 3312 3313 static const struct mv88e6xxx_ops mv88e6191_ops = { 3314 /* MV88E6XXX_FAMILY_6390 */ 3315 .irl_init_all = mv88e6390_g2_irl_init_all, 3316 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3317 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3319 .phy_read = mv88e6xxx_g2_smi_phy_read, 3320 .phy_write = mv88e6xxx_g2_smi_phy_write, 3321 .port_set_link = mv88e6xxx_port_set_link, 3322 .port_set_duplex = mv88e6xxx_port_set_duplex, 3323 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3324 .port_set_speed = mv88e6390_port_set_speed, 3325 .port_tag_remap = mv88e6390_port_tag_remap, 3326 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3327 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3328 .port_set_ether_type = mv88e6351_port_set_ether_type, 3329 .port_pause_limit = mv88e6390_port_pause_limit, 3330 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3331 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3332 .port_link_state = mv88e6352_port_link_state, 3333 .port_get_cmode = mv88e6352_port_get_cmode, 3334 .port_set_cmode = mv88e6390_port_set_cmode, 3335 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3336 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3337 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3338 .stats_get_strings = mv88e6320_stats_get_strings, 3339 .stats_get_stats = mv88e6390_stats_get_stats, 3340 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3341 .set_egress_port = mv88e6390_g1_set_egress_port, 3342 .watchdog_ops = &mv88e6390_watchdog_ops, 3343 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3344 .pot_clear = mv88e6xxx_g2_pot_clear, 3345 .reset = mv88e6352_g1_reset, 3346 .rmu_disable = mv88e6390_g1_rmu_disable, 3347 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3348 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3349 .serdes_power = mv88e6390_serdes_power, 3350 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3351 .serdes_irq_free = mv88e6390_serdes_irq_free, 3352 .avb_ops = &mv88e6390_avb_ops, 3353 .ptp_ops = &mv88e6352_ptp_ops, 3354 .phylink_validate = mv88e6390_phylink_validate, 3355 }; 3356 3357 static const struct mv88e6xxx_ops mv88e6240_ops = { 3358 /* MV88E6XXX_FAMILY_6352 */ 3359 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3360 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3361 .irl_init_all = mv88e6352_g2_irl_init_all, 3362 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3363 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3364 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3365 .phy_read = mv88e6xxx_g2_smi_phy_read, 3366 .phy_write = mv88e6xxx_g2_smi_phy_write, 3367 .port_set_link = mv88e6xxx_port_set_link, 3368 .port_set_duplex = mv88e6xxx_port_set_duplex, 3369 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3370 .port_set_speed = mv88e6352_port_set_speed, 3371 .port_tag_remap = mv88e6095_port_tag_remap, 3372 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3373 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3374 .port_set_ether_type = mv88e6351_port_set_ether_type, 3375 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3376 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3377 .port_pause_limit = mv88e6097_port_pause_limit, 3378 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3379 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3380 .port_link_state = mv88e6352_port_link_state, 3381 .port_get_cmode = mv88e6352_port_get_cmode, 3382 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3383 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3384 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3385 .stats_get_strings = mv88e6095_stats_get_strings, 3386 .stats_get_stats = mv88e6095_stats_get_stats, 3387 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3388 .set_egress_port = mv88e6095_g1_set_egress_port, 3389 .watchdog_ops = &mv88e6097_watchdog_ops, 3390 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3391 .pot_clear = mv88e6xxx_g2_pot_clear, 3392 .reset = mv88e6352_g1_reset, 3393 .rmu_disable = mv88e6352_g1_rmu_disable, 3394 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3395 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3396 .serdes_power = mv88e6352_serdes_power, 3397 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3398 .serdes_irq_free = mv88e6352_serdes_irq_free, 3399 .gpio_ops = &mv88e6352_gpio_ops, 3400 .avb_ops = &mv88e6352_avb_ops, 3401 .ptp_ops = &mv88e6352_ptp_ops, 3402 .phylink_validate = mv88e6352_phylink_validate, 3403 }; 3404 3405 static const struct mv88e6xxx_ops mv88e6290_ops = { 3406 /* MV88E6XXX_FAMILY_6390 */ 3407 .irl_init_all = mv88e6390_g2_irl_init_all, 3408 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3409 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3410 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3411 .phy_read = mv88e6xxx_g2_smi_phy_read, 3412 .phy_write = mv88e6xxx_g2_smi_phy_write, 3413 .port_set_link = mv88e6xxx_port_set_link, 3414 .port_set_duplex = mv88e6xxx_port_set_duplex, 3415 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3416 .port_set_speed = mv88e6390_port_set_speed, 3417 .port_tag_remap = mv88e6390_port_tag_remap, 3418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3419 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3420 .port_set_ether_type = mv88e6351_port_set_ether_type, 3421 .port_pause_limit = mv88e6390_port_pause_limit, 3422 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3423 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3424 .port_link_state = mv88e6352_port_link_state, 3425 .port_get_cmode = mv88e6352_port_get_cmode, 3426 .port_set_cmode = mv88e6390_port_set_cmode, 3427 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3428 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3429 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3430 .stats_get_strings = mv88e6320_stats_get_strings, 3431 .stats_get_stats = mv88e6390_stats_get_stats, 3432 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3433 .set_egress_port = mv88e6390_g1_set_egress_port, 3434 .watchdog_ops = &mv88e6390_watchdog_ops, 3435 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3436 .pot_clear = mv88e6xxx_g2_pot_clear, 3437 .reset = mv88e6352_g1_reset, 3438 .rmu_disable = mv88e6390_g1_rmu_disable, 3439 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3440 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3441 .serdes_power = mv88e6390_serdes_power, 3442 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3443 .serdes_irq_free = mv88e6390_serdes_irq_free, 3444 .gpio_ops = &mv88e6352_gpio_ops, 3445 .avb_ops = &mv88e6390_avb_ops, 3446 .ptp_ops = &mv88e6352_ptp_ops, 3447 .phylink_validate = mv88e6390_phylink_validate, 3448 }; 3449 3450 static const struct mv88e6xxx_ops mv88e6320_ops = { 3451 /* MV88E6XXX_FAMILY_6320 */ 3452 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3453 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3454 .irl_init_all = mv88e6352_g2_irl_init_all, 3455 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3456 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3457 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3458 .phy_read = mv88e6xxx_g2_smi_phy_read, 3459 .phy_write = mv88e6xxx_g2_smi_phy_write, 3460 .port_set_link = mv88e6xxx_port_set_link, 3461 .port_set_duplex = mv88e6xxx_port_set_duplex, 3462 .port_set_speed = mv88e6185_port_set_speed, 3463 .port_tag_remap = mv88e6095_port_tag_remap, 3464 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3465 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3466 .port_set_ether_type = mv88e6351_port_set_ether_type, 3467 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3468 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3469 .port_pause_limit = mv88e6097_port_pause_limit, 3470 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3471 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3472 .port_link_state = mv88e6352_port_link_state, 3473 .port_get_cmode = mv88e6352_port_get_cmode, 3474 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3475 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3476 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3477 .stats_get_strings = mv88e6320_stats_get_strings, 3478 .stats_get_stats = mv88e6320_stats_get_stats, 3479 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3480 .set_egress_port = mv88e6095_g1_set_egress_port, 3481 .watchdog_ops = &mv88e6390_watchdog_ops, 3482 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3483 .pot_clear = mv88e6xxx_g2_pot_clear, 3484 .reset = mv88e6352_g1_reset, 3485 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3486 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3487 .gpio_ops = &mv88e6352_gpio_ops, 3488 .avb_ops = &mv88e6352_avb_ops, 3489 .ptp_ops = &mv88e6352_ptp_ops, 3490 .phylink_validate = mv88e6185_phylink_validate, 3491 }; 3492 3493 static const struct mv88e6xxx_ops mv88e6321_ops = { 3494 /* MV88E6XXX_FAMILY_6320 */ 3495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3496 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3497 .irl_init_all = mv88e6352_g2_irl_init_all, 3498 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3499 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3500 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3501 .phy_read = mv88e6xxx_g2_smi_phy_read, 3502 .phy_write = mv88e6xxx_g2_smi_phy_write, 3503 .port_set_link = mv88e6xxx_port_set_link, 3504 .port_set_duplex = mv88e6xxx_port_set_duplex, 3505 .port_set_speed = mv88e6185_port_set_speed, 3506 .port_tag_remap = mv88e6095_port_tag_remap, 3507 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3508 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3509 .port_set_ether_type = mv88e6351_port_set_ether_type, 3510 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3511 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3512 .port_pause_limit = mv88e6097_port_pause_limit, 3513 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3514 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3515 .port_link_state = mv88e6352_port_link_state, 3516 .port_get_cmode = mv88e6352_port_get_cmode, 3517 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3518 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3519 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3520 .stats_get_strings = mv88e6320_stats_get_strings, 3521 .stats_get_stats = mv88e6320_stats_get_stats, 3522 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3523 .set_egress_port = mv88e6095_g1_set_egress_port, 3524 .watchdog_ops = &mv88e6390_watchdog_ops, 3525 .reset = mv88e6352_g1_reset, 3526 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3527 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3528 .gpio_ops = &mv88e6352_gpio_ops, 3529 .avb_ops = &mv88e6352_avb_ops, 3530 .ptp_ops = &mv88e6352_ptp_ops, 3531 .phylink_validate = mv88e6185_phylink_validate, 3532 }; 3533 3534 static const struct mv88e6xxx_ops mv88e6341_ops = { 3535 /* MV88E6XXX_FAMILY_6341 */ 3536 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3537 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3538 .irl_init_all = mv88e6352_g2_irl_init_all, 3539 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3540 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3541 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3542 .phy_read = mv88e6xxx_g2_smi_phy_read, 3543 .phy_write = mv88e6xxx_g2_smi_phy_write, 3544 .port_set_link = mv88e6xxx_port_set_link, 3545 .port_set_duplex = mv88e6xxx_port_set_duplex, 3546 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3547 .port_set_speed = mv88e6341_port_set_speed, 3548 .port_tag_remap = mv88e6095_port_tag_remap, 3549 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3550 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3551 .port_set_ether_type = mv88e6351_port_set_ether_type, 3552 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3553 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3554 .port_pause_limit = mv88e6097_port_pause_limit, 3555 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3556 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3557 .port_link_state = mv88e6352_port_link_state, 3558 .port_get_cmode = mv88e6352_port_get_cmode, 3559 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3560 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3561 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3562 .stats_get_strings = mv88e6320_stats_get_strings, 3563 .stats_get_stats = mv88e6390_stats_get_stats, 3564 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3565 .set_egress_port = mv88e6390_g1_set_egress_port, 3566 .watchdog_ops = &mv88e6390_watchdog_ops, 3567 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3568 .pot_clear = mv88e6xxx_g2_pot_clear, 3569 .reset = mv88e6352_g1_reset, 3570 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3571 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3572 .serdes_power = mv88e6341_serdes_power, 3573 .gpio_ops = &mv88e6352_gpio_ops, 3574 .avb_ops = &mv88e6390_avb_ops, 3575 .ptp_ops = &mv88e6352_ptp_ops, 3576 .phylink_validate = mv88e6390_phylink_validate, 3577 }; 3578 3579 static const struct mv88e6xxx_ops mv88e6350_ops = { 3580 /* MV88E6XXX_FAMILY_6351 */ 3581 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3582 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3583 .irl_init_all = mv88e6352_g2_irl_init_all, 3584 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3585 .phy_read = mv88e6xxx_g2_smi_phy_read, 3586 .phy_write = mv88e6xxx_g2_smi_phy_write, 3587 .port_set_link = mv88e6xxx_port_set_link, 3588 .port_set_duplex = mv88e6xxx_port_set_duplex, 3589 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3590 .port_set_speed = mv88e6185_port_set_speed, 3591 .port_tag_remap = mv88e6095_port_tag_remap, 3592 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3593 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3594 .port_set_ether_type = mv88e6351_port_set_ether_type, 3595 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3596 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3597 .port_pause_limit = mv88e6097_port_pause_limit, 3598 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3599 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3600 .port_link_state = mv88e6352_port_link_state, 3601 .port_get_cmode = mv88e6352_port_get_cmode, 3602 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3603 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3604 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3605 .stats_get_strings = mv88e6095_stats_get_strings, 3606 .stats_get_stats = mv88e6095_stats_get_stats, 3607 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3608 .set_egress_port = mv88e6095_g1_set_egress_port, 3609 .watchdog_ops = &mv88e6097_watchdog_ops, 3610 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3611 .pot_clear = mv88e6xxx_g2_pot_clear, 3612 .reset = mv88e6352_g1_reset, 3613 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3614 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3615 .phylink_validate = mv88e6185_phylink_validate, 3616 }; 3617 3618 static const struct mv88e6xxx_ops mv88e6351_ops = { 3619 /* MV88E6XXX_FAMILY_6351 */ 3620 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3621 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3622 .irl_init_all = mv88e6352_g2_irl_init_all, 3623 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3624 .phy_read = mv88e6xxx_g2_smi_phy_read, 3625 .phy_write = mv88e6xxx_g2_smi_phy_write, 3626 .port_set_link = mv88e6xxx_port_set_link, 3627 .port_set_duplex = mv88e6xxx_port_set_duplex, 3628 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3629 .port_set_speed = mv88e6185_port_set_speed, 3630 .port_tag_remap = mv88e6095_port_tag_remap, 3631 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3632 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3633 .port_set_ether_type = mv88e6351_port_set_ether_type, 3634 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3635 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3636 .port_pause_limit = mv88e6097_port_pause_limit, 3637 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3638 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3639 .port_link_state = mv88e6352_port_link_state, 3640 .port_get_cmode = mv88e6352_port_get_cmode, 3641 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3642 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3643 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3644 .stats_get_strings = mv88e6095_stats_get_strings, 3645 .stats_get_stats = mv88e6095_stats_get_stats, 3646 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3647 .set_egress_port = mv88e6095_g1_set_egress_port, 3648 .watchdog_ops = &mv88e6097_watchdog_ops, 3649 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3650 .pot_clear = mv88e6xxx_g2_pot_clear, 3651 .reset = mv88e6352_g1_reset, 3652 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3653 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3654 .avb_ops = &mv88e6352_avb_ops, 3655 .ptp_ops = &mv88e6352_ptp_ops, 3656 .phylink_validate = mv88e6185_phylink_validate, 3657 }; 3658 3659 static const struct mv88e6xxx_ops mv88e6352_ops = { 3660 /* MV88E6XXX_FAMILY_6352 */ 3661 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3662 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3663 .irl_init_all = mv88e6352_g2_irl_init_all, 3664 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3665 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3666 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3667 .phy_read = mv88e6xxx_g2_smi_phy_read, 3668 .phy_write = mv88e6xxx_g2_smi_phy_write, 3669 .port_set_link = mv88e6xxx_port_set_link, 3670 .port_set_duplex = mv88e6xxx_port_set_duplex, 3671 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3672 .port_set_speed = mv88e6352_port_set_speed, 3673 .port_tag_remap = mv88e6095_port_tag_remap, 3674 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3675 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3676 .port_set_ether_type = mv88e6351_port_set_ether_type, 3677 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3678 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3679 .port_pause_limit = mv88e6097_port_pause_limit, 3680 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3681 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3682 .port_link_state = mv88e6352_port_link_state, 3683 .port_get_cmode = mv88e6352_port_get_cmode, 3684 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3685 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3686 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3687 .stats_get_strings = mv88e6095_stats_get_strings, 3688 .stats_get_stats = mv88e6095_stats_get_stats, 3689 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3690 .set_egress_port = mv88e6095_g1_set_egress_port, 3691 .watchdog_ops = &mv88e6097_watchdog_ops, 3692 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3693 .pot_clear = mv88e6xxx_g2_pot_clear, 3694 .reset = mv88e6352_g1_reset, 3695 .rmu_disable = mv88e6352_g1_rmu_disable, 3696 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3697 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3698 .serdes_power = mv88e6352_serdes_power, 3699 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3700 .serdes_irq_free = mv88e6352_serdes_irq_free, 3701 .gpio_ops = &mv88e6352_gpio_ops, 3702 .avb_ops = &mv88e6352_avb_ops, 3703 .ptp_ops = &mv88e6352_ptp_ops, 3704 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3705 .serdes_get_strings = mv88e6352_serdes_get_strings, 3706 .serdes_get_stats = mv88e6352_serdes_get_stats, 3707 .phylink_validate = mv88e6352_phylink_validate, 3708 }; 3709 3710 static const struct mv88e6xxx_ops mv88e6390_ops = { 3711 /* MV88E6XXX_FAMILY_6390 */ 3712 .irl_init_all = mv88e6390_g2_irl_init_all, 3713 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3714 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3715 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3716 .phy_read = mv88e6xxx_g2_smi_phy_read, 3717 .phy_write = mv88e6xxx_g2_smi_phy_write, 3718 .port_set_link = mv88e6xxx_port_set_link, 3719 .port_set_duplex = mv88e6xxx_port_set_duplex, 3720 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3721 .port_set_speed = mv88e6390_port_set_speed, 3722 .port_tag_remap = mv88e6390_port_tag_remap, 3723 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3724 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3725 .port_set_ether_type = mv88e6351_port_set_ether_type, 3726 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3727 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3728 .port_pause_limit = mv88e6390_port_pause_limit, 3729 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3730 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3731 .port_link_state = mv88e6352_port_link_state, 3732 .port_get_cmode = mv88e6352_port_get_cmode, 3733 .port_set_cmode = mv88e6390_port_set_cmode, 3734 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3735 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3736 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3737 .stats_get_strings = mv88e6320_stats_get_strings, 3738 .stats_get_stats = mv88e6390_stats_get_stats, 3739 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3740 .set_egress_port = mv88e6390_g1_set_egress_port, 3741 .watchdog_ops = &mv88e6390_watchdog_ops, 3742 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3743 .pot_clear = mv88e6xxx_g2_pot_clear, 3744 .reset = mv88e6352_g1_reset, 3745 .rmu_disable = mv88e6390_g1_rmu_disable, 3746 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3747 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3748 .serdes_power = mv88e6390_serdes_power, 3749 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3750 .serdes_irq_free = mv88e6390_serdes_irq_free, 3751 .gpio_ops = &mv88e6352_gpio_ops, 3752 .avb_ops = &mv88e6390_avb_ops, 3753 .ptp_ops = &mv88e6352_ptp_ops, 3754 .phylink_validate = mv88e6390_phylink_validate, 3755 }; 3756 3757 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3758 /* MV88E6XXX_FAMILY_6390 */ 3759 .irl_init_all = mv88e6390_g2_irl_init_all, 3760 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3761 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3762 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3763 .phy_read = mv88e6xxx_g2_smi_phy_read, 3764 .phy_write = mv88e6xxx_g2_smi_phy_write, 3765 .port_set_link = mv88e6xxx_port_set_link, 3766 .port_set_duplex = mv88e6xxx_port_set_duplex, 3767 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3768 .port_set_speed = mv88e6390x_port_set_speed, 3769 .port_tag_remap = mv88e6390_port_tag_remap, 3770 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3771 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3772 .port_set_ether_type = mv88e6351_port_set_ether_type, 3773 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3774 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3775 .port_pause_limit = mv88e6390_port_pause_limit, 3776 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3777 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3778 .port_link_state = mv88e6352_port_link_state, 3779 .port_get_cmode = mv88e6352_port_get_cmode, 3780 .port_set_cmode = mv88e6390x_port_set_cmode, 3781 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3782 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3783 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3784 .stats_get_strings = mv88e6320_stats_get_strings, 3785 .stats_get_stats = mv88e6390_stats_get_stats, 3786 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3787 .set_egress_port = mv88e6390_g1_set_egress_port, 3788 .watchdog_ops = &mv88e6390_watchdog_ops, 3789 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3790 .pot_clear = mv88e6xxx_g2_pot_clear, 3791 .reset = mv88e6352_g1_reset, 3792 .rmu_disable = mv88e6390_g1_rmu_disable, 3793 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3794 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3795 .serdes_power = mv88e6390x_serdes_power, 3796 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3797 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3798 .gpio_ops = &mv88e6352_gpio_ops, 3799 .avb_ops = &mv88e6390_avb_ops, 3800 .ptp_ops = &mv88e6352_ptp_ops, 3801 .phylink_validate = mv88e6390x_phylink_validate, 3802 }; 3803 3804 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3805 [MV88E6085] = { 3806 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3807 .family = MV88E6XXX_FAMILY_6097, 3808 .name = "Marvell 88E6085", 3809 .num_databases = 4096, 3810 .num_ports = 10, 3811 .num_internal_phys = 5, 3812 .max_vid = 4095, 3813 .port_base_addr = 0x10, 3814 .phy_base_addr = 0x0, 3815 .global1_addr = 0x1b, 3816 .global2_addr = 0x1c, 3817 .age_time_coeff = 15000, 3818 .g1_irqs = 8, 3819 .g2_irqs = 10, 3820 .atu_move_port_mask = 0xf, 3821 .pvt = true, 3822 .multi_chip = true, 3823 .tag_protocol = DSA_TAG_PROTO_DSA, 3824 .ops = &mv88e6085_ops, 3825 }, 3826 3827 [MV88E6095] = { 3828 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3829 .family = MV88E6XXX_FAMILY_6095, 3830 .name = "Marvell 88E6095/88E6095F", 3831 .num_databases = 256, 3832 .num_ports = 11, 3833 .num_internal_phys = 0, 3834 .max_vid = 4095, 3835 .port_base_addr = 0x10, 3836 .phy_base_addr = 0x0, 3837 .global1_addr = 0x1b, 3838 .global2_addr = 0x1c, 3839 .age_time_coeff = 15000, 3840 .g1_irqs = 8, 3841 .atu_move_port_mask = 0xf, 3842 .multi_chip = true, 3843 .tag_protocol = DSA_TAG_PROTO_DSA, 3844 .ops = &mv88e6095_ops, 3845 }, 3846 3847 [MV88E6097] = { 3848 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3849 .family = MV88E6XXX_FAMILY_6097, 3850 .name = "Marvell 88E6097/88E6097F", 3851 .num_databases = 4096, 3852 .num_ports = 11, 3853 .num_internal_phys = 8, 3854 .max_vid = 4095, 3855 .port_base_addr = 0x10, 3856 .phy_base_addr = 0x0, 3857 .global1_addr = 0x1b, 3858 .global2_addr = 0x1c, 3859 .age_time_coeff = 15000, 3860 .g1_irqs = 8, 3861 .g2_irqs = 10, 3862 .atu_move_port_mask = 0xf, 3863 .pvt = true, 3864 .multi_chip = true, 3865 .tag_protocol = DSA_TAG_PROTO_EDSA, 3866 .ops = &mv88e6097_ops, 3867 }, 3868 3869 [MV88E6123] = { 3870 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3871 .family = MV88E6XXX_FAMILY_6165, 3872 .name = "Marvell 88E6123", 3873 .num_databases = 4096, 3874 .num_ports = 3, 3875 .num_internal_phys = 5, 3876 .max_vid = 4095, 3877 .port_base_addr = 0x10, 3878 .phy_base_addr = 0x0, 3879 .global1_addr = 0x1b, 3880 .global2_addr = 0x1c, 3881 .age_time_coeff = 15000, 3882 .g1_irqs = 9, 3883 .g2_irqs = 10, 3884 .atu_move_port_mask = 0xf, 3885 .pvt = true, 3886 .multi_chip = true, 3887 .tag_protocol = DSA_TAG_PROTO_EDSA, 3888 .ops = &mv88e6123_ops, 3889 }, 3890 3891 [MV88E6131] = { 3892 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3893 .family = MV88E6XXX_FAMILY_6185, 3894 .name = "Marvell 88E6131", 3895 .num_databases = 256, 3896 .num_ports = 8, 3897 .num_internal_phys = 0, 3898 .max_vid = 4095, 3899 .port_base_addr = 0x10, 3900 .phy_base_addr = 0x0, 3901 .global1_addr = 0x1b, 3902 .global2_addr = 0x1c, 3903 .age_time_coeff = 15000, 3904 .g1_irqs = 9, 3905 .atu_move_port_mask = 0xf, 3906 .multi_chip = true, 3907 .tag_protocol = DSA_TAG_PROTO_DSA, 3908 .ops = &mv88e6131_ops, 3909 }, 3910 3911 [MV88E6141] = { 3912 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3913 .family = MV88E6XXX_FAMILY_6341, 3914 .name = "Marvell 88E6141", 3915 .num_databases = 4096, 3916 .num_ports = 6, 3917 .num_internal_phys = 5, 3918 .num_gpio = 11, 3919 .max_vid = 4095, 3920 .port_base_addr = 0x10, 3921 .phy_base_addr = 0x10, 3922 .global1_addr = 0x1b, 3923 .global2_addr = 0x1c, 3924 .age_time_coeff = 3750, 3925 .atu_move_port_mask = 0x1f, 3926 .g1_irqs = 9, 3927 .g2_irqs = 10, 3928 .pvt = true, 3929 .multi_chip = true, 3930 .tag_protocol = DSA_TAG_PROTO_EDSA, 3931 .ops = &mv88e6141_ops, 3932 }, 3933 3934 [MV88E6161] = { 3935 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3936 .family = MV88E6XXX_FAMILY_6165, 3937 .name = "Marvell 88E6161", 3938 .num_databases = 4096, 3939 .num_ports = 6, 3940 .num_internal_phys = 5, 3941 .max_vid = 4095, 3942 .port_base_addr = 0x10, 3943 .phy_base_addr = 0x0, 3944 .global1_addr = 0x1b, 3945 .global2_addr = 0x1c, 3946 .age_time_coeff = 15000, 3947 .g1_irqs = 9, 3948 .g2_irqs = 10, 3949 .atu_move_port_mask = 0xf, 3950 .pvt = true, 3951 .multi_chip = true, 3952 .tag_protocol = DSA_TAG_PROTO_EDSA, 3953 .ptp_support = true, 3954 .ops = &mv88e6161_ops, 3955 }, 3956 3957 [MV88E6165] = { 3958 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3959 .family = MV88E6XXX_FAMILY_6165, 3960 .name = "Marvell 88E6165", 3961 .num_databases = 4096, 3962 .num_ports = 6, 3963 .num_internal_phys = 0, 3964 .max_vid = 4095, 3965 .port_base_addr = 0x10, 3966 .phy_base_addr = 0x0, 3967 .global1_addr = 0x1b, 3968 .global2_addr = 0x1c, 3969 .age_time_coeff = 15000, 3970 .g1_irqs = 9, 3971 .g2_irqs = 10, 3972 .atu_move_port_mask = 0xf, 3973 .pvt = true, 3974 .multi_chip = true, 3975 .tag_protocol = DSA_TAG_PROTO_DSA, 3976 .ptp_support = true, 3977 .ops = &mv88e6165_ops, 3978 }, 3979 3980 [MV88E6171] = { 3981 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3982 .family = MV88E6XXX_FAMILY_6351, 3983 .name = "Marvell 88E6171", 3984 .num_databases = 4096, 3985 .num_ports = 7, 3986 .num_internal_phys = 5, 3987 .max_vid = 4095, 3988 .port_base_addr = 0x10, 3989 .phy_base_addr = 0x0, 3990 .global1_addr = 0x1b, 3991 .global2_addr = 0x1c, 3992 .age_time_coeff = 15000, 3993 .g1_irqs = 9, 3994 .g2_irqs = 10, 3995 .atu_move_port_mask = 0xf, 3996 .pvt = true, 3997 .multi_chip = true, 3998 .tag_protocol = DSA_TAG_PROTO_EDSA, 3999 .ops = &mv88e6171_ops, 4000 }, 4001 4002 [MV88E6172] = { 4003 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4004 .family = MV88E6XXX_FAMILY_6352, 4005 .name = "Marvell 88E6172", 4006 .num_databases = 4096, 4007 .num_ports = 7, 4008 .num_internal_phys = 5, 4009 .num_gpio = 15, 4010 .max_vid = 4095, 4011 .port_base_addr = 0x10, 4012 .phy_base_addr = 0x0, 4013 .global1_addr = 0x1b, 4014 .global2_addr = 0x1c, 4015 .age_time_coeff = 15000, 4016 .g1_irqs = 9, 4017 .g2_irqs = 10, 4018 .atu_move_port_mask = 0xf, 4019 .pvt = true, 4020 .multi_chip = true, 4021 .tag_protocol = DSA_TAG_PROTO_EDSA, 4022 .ops = &mv88e6172_ops, 4023 }, 4024 4025 [MV88E6175] = { 4026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4027 .family = MV88E6XXX_FAMILY_6351, 4028 .name = "Marvell 88E6175", 4029 .num_databases = 4096, 4030 .num_ports = 7, 4031 .num_internal_phys = 5, 4032 .max_vid = 4095, 4033 .port_base_addr = 0x10, 4034 .phy_base_addr = 0x0, 4035 .global1_addr = 0x1b, 4036 .global2_addr = 0x1c, 4037 .age_time_coeff = 15000, 4038 .g1_irqs = 9, 4039 .g2_irqs = 10, 4040 .atu_move_port_mask = 0xf, 4041 .pvt = true, 4042 .multi_chip = true, 4043 .tag_protocol = DSA_TAG_PROTO_EDSA, 4044 .ops = &mv88e6175_ops, 4045 }, 4046 4047 [MV88E6176] = { 4048 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4049 .family = MV88E6XXX_FAMILY_6352, 4050 .name = "Marvell 88E6176", 4051 .num_databases = 4096, 4052 .num_ports = 7, 4053 .num_internal_phys = 5, 4054 .num_gpio = 15, 4055 .max_vid = 4095, 4056 .port_base_addr = 0x10, 4057 .phy_base_addr = 0x0, 4058 .global1_addr = 0x1b, 4059 .global2_addr = 0x1c, 4060 .age_time_coeff = 15000, 4061 .g1_irqs = 9, 4062 .g2_irqs = 10, 4063 .atu_move_port_mask = 0xf, 4064 .pvt = true, 4065 .multi_chip = true, 4066 .tag_protocol = DSA_TAG_PROTO_EDSA, 4067 .ops = &mv88e6176_ops, 4068 }, 4069 4070 [MV88E6185] = { 4071 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4072 .family = MV88E6XXX_FAMILY_6185, 4073 .name = "Marvell 88E6185", 4074 .num_databases = 256, 4075 .num_ports = 10, 4076 .num_internal_phys = 0, 4077 .max_vid = 4095, 4078 .port_base_addr = 0x10, 4079 .phy_base_addr = 0x0, 4080 .global1_addr = 0x1b, 4081 .global2_addr = 0x1c, 4082 .age_time_coeff = 15000, 4083 .g1_irqs = 8, 4084 .atu_move_port_mask = 0xf, 4085 .multi_chip = true, 4086 .tag_protocol = DSA_TAG_PROTO_EDSA, 4087 .ops = &mv88e6185_ops, 4088 }, 4089 4090 [MV88E6190] = { 4091 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4092 .family = MV88E6XXX_FAMILY_6390, 4093 .name = "Marvell 88E6190", 4094 .num_databases = 4096, 4095 .num_ports = 11, /* 10 + Z80 */ 4096 .num_internal_phys = 11, 4097 .num_gpio = 16, 4098 .max_vid = 8191, 4099 .port_base_addr = 0x0, 4100 .phy_base_addr = 0x0, 4101 .global1_addr = 0x1b, 4102 .global2_addr = 0x1c, 4103 .tag_protocol = DSA_TAG_PROTO_DSA, 4104 .age_time_coeff = 3750, 4105 .g1_irqs = 9, 4106 .g2_irqs = 14, 4107 .pvt = true, 4108 .multi_chip = true, 4109 .atu_move_port_mask = 0x1f, 4110 .ops = &mv88e6190_ops, 4111 }, 4112 4113 [MV88E6190X] = { 4114 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4115 .family = MV88E6XXX_FAMILY_6390, 4116 .name = "Marvell 88E6190X", 4117 .num_databases = 4096, 4118 .num_ports = 11, /* 10 + Z80 */ 4119 .num_internal_phys = 11, 4120 .num_gpio = 16, 4121 .max_vid = 8191, 4122 .port_base_addr = 0x0, 4123 .phy_base_addr = 0x0, 4124 .global1_addr = 0x1b, 4125 .global2_addr = 0x1c, 4126 .age_time_coeff = 3750, 4127 .g1_irqs = 9, 4128 .g2_irqs = 14, 4129 .atu_move_port_mask = 0x1f, 4130 .pvt = true, 4131 .multi_chip = true, 4132 .tag_protocol = DSA_TAG_PROTO_DSA, 4133 .ops = &mv88e6190x_ops, 4134 }, 4135 4136 [MV88E6191] = { 4137 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4138 .family = MV88E6XXX_FAMILY_6390, 4139 .name = "Marvell 88E6191", 4140 .num_databases = 4096, 4141 .num_ports = 11, /* 10 + Z80 */ 4142 .num_internal_phys = 11, 4143 .max_vid = 8191, 4144 .port_base_addr = 0x0, 4145 .phy_base_addr = 0x0, 4146 .global1_addr = 0x1b, 4147 .global2_addr = 0x1c, 4148 .age_time_coeff = 3750, 4149 .g1_irqs = 9, 4150 .g2_irqs = 14, 4151 .atu_move_port_mask = 0x1f, 4152 .pvt = true, 4153 .multi_chip = true, 4154 .tag_protocol = DSA_TAG_PROTO_DSA, 4155 .ptp_support = true, 4156 .ops = &mv88e6191_ops, 4157 }, 4158 4159 [MV88E6240] = { 4160 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4161 .family = MV88E6XXX_FAMILY_6352, 4162 .name = "Marvell 88E6240", 4163 .num_databases = 4096, 4164 .num_ports = 7, 4165 .num_internal_phys = 5, 4166 .num_gpio = 15, 4167 .max_vid = 4095, 4168 .port_base_addr = 0x10, 4169 .phy_base_addr = 0x0, 4170 .global1_addr = 0x1b, 4171 .global2_addr = 0x1c, 4172 .age_time_coeff = 15000, 4173 .g1_irqs = 9, 4174 .g2_irqs = 10, 4175 .atu_move_port_mask = 0xf, 4176 .pvt = true, 4177 .multi_chip = true, 4178 .tag_protocol = DSA_TAG_PROTO_EDSA, 4179 .ptp_support = true, 4180 .ops = &mv88e6240_ops, 4181 }, 4182 4183 [MV88E6290] = { 4184 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4185 .family = MV88E6XXX_FAMILY_6390, 4186 .name = "Marvell 88E6290", 4187 .num_databases = 4096, 4188 .num_ports = 11, /* 10 + Z80 */ 4189 .num_internal_phys = 11, 4190 .num_gpio = 16, 4191 .max_vid = 8191, 4192 .port_base_addr = 0x0, 4193 .phy_base_addr = 0x0, 4194 .global1_addr = 0x1b, 4195 .global2_addr = 0x1c, 4196 .age_time_coeff = 3750, 4197 .g1_irqs = 9, 4198 .g2_irqs = 14, 4199 .atu_move_port_mask = 0x1f, 4200 .pvt = true, 4201 .multi_chip = true, 4202 .tag_protocol = DSA_TAG_PROTO_DSA, 4203 .ptp_support = true, 4204 .ops = &mv88e6290_ops, 4205 }, 4206 4207 [MV88E6320] = { 4208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4209 .family = MV88E6XXX_FAMILY_6320, 4210 .name = "Marvell 88E6320", 4211 .num_databases = 4096, 4212 .num_ports = 7, 4213 .num_internal_phys = 5, 4214 .num_gpio = 15, 4215 .max_vid = 4095, 4216 .port_base_addr = 0x10, 4217 .phy_base_addr = 0x0, 4218 .global1_addr = 0x1b, 4219 .global2_addr = 0x1c, 4220 .age_time_coeff = 15000, 4221 .g1_irqs = 8, 4222 .g2_irqs = 10, 4223 .atu_move_port_mask = 0xf, 4224 .pvt = true, 4225 .multi_chip = true, 4226 .tag_protocol = DSA_TAG_PROTO_EDSA, 4227 .ptp_support = true, 4228 .ops = &mv88e6320_ops, 4229 }, 4230 4231 [MV88E6321] = { 4232 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4233 .family = MV88E6XXX_FAMILY_6320, 4234 .name = "Marvell 88E6321", 4235 .num_databases = 4096, 4236 .num_ports = 7, 4237 .num_internal_phys = 5, 4238 .num_gpio = 15, 4239 .max_vid = 4095, 4240 .port_base_addr = 0x10, 4241 .phy_base_addr = 0x0, 4242 .global1_addr = 0x1b, 4243 .global2_addr = 0x1c, 4244 .age_time_coeff = 15000, 4245 .g1_irqs = 8, 4246 .g2_irqs = 10, 4247 .atu_move_port_mask = 0xf, 4248 .multi_chip = true, 4249 .tag_protocol = DSA_TAG_PROTO_EDSA, 4250 .ptp_support = true, 4251 .ops = &mv88e6321_ops, 4252 }, 4253 4254 [MV88E6341] = { 4255 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4256 .family = MV88E6XXX_FAMILY_6341, 4257 .name = "Marvell 88E6341", 4258 .num_databases = 4096, 4259 .num_internal_phys = 5, 4260 .num_ports = 6, 4261 .num_gpio = 11, 4262 .max_vid = 4095, 4263 .port_base_addr = 0x10, 4264 .phy_base_addr = 0x10, 4265 .global1_addr = 0x1b, 4266 .global2_addr = 0x1c, 4267 .age_time_coeff = 3750, 4268 .atu_move_port_mask = 0x1f, 4269 .g1_irqs = 9, 4270 .g2_irqs = 10, 4271 .pvt = true, 4272 .multi_chip = true, 4273 .tag_protocol = DSA_TAG_PROTO_EDSA, 4274 .ptp_support = true, 4275 .ops = &mv88e6341_ops, 4276 }, 4277 4278 [MV88E6350] = { 4279 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4280 .family = MV88E6XXX_FAMILY_6351, 4281 .name = "Marvell 88E6350", 4282 .num_databases = 4096, 4283 .num_ports = 7, 4284 .num_internal_phys = 5, 4285 .max_vid = 4095, 4286 .port_base_addr = 0x10, 4287 .phy_base_addr = 0x0, 4288 .global1_addr = 0x1b, 4289 .global2_addr = 0x1c, 4290 .age_time_coeff = 15000, 4291 .g1_irqs = 9, 4292 .g2_irqs = 10, 4293 .atu_move_port_mask = 0xf, 4294 .pvt = true, 4295 .multi_chip = true, 4296 .tag_protocol = DSA_TAG_PROTO_EDSA, 4297 .ops = &mv88e6350_ops, 4298 }, 4299 4300 [MV88E6351] = { 4301 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4302 .family = MV88E6XXX_FAMILY_6351, 4303 .name = "Marvell 88E6351", 4304 .num_databases = 4096, 4305 .num_ports = 7, 4306 .num_internal_phys = 5, 4307 .max_vid = 4095, 4308 .port_base_addr = 0x10, 4309 .phy_base_addr = 0x0, 4310 .global1_addr = 0x1b, 4311 .global2_addr = 0x1c, 4312 .age_time_coeff = 15000, 4313 .g1_irqs = 9, 4314 .g2_irqs = 10, 4315 .atu_move_port_mask = 0xf, 4316 .pvt = true, 4317 .multi_chip = true, 4318 .tag_protocol = DSA_TAG_PROTO_EDSA, 4319 .ops = &mv88e6351_ops, 4320 }, 4321 4322 [MV88E6352] = { 4323 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4324 .family = MV88E6XXX_FAMILY_6352, 4325 .name = "Marvell 88E6352", 4326 .num_databases = 4096, 4327 .num_ports = 7, 4328 .num_internal_phys = 5, 4329 .num_gpio = 15, 4330 .max_vid = 4095, 4331 .port_base_addr = 0x10, 4332 .phy_base_addr = 0x0, 4333 .global1_addr = 0x1b, 4334 .global2_addr = 0x1c, 4335 .age_time_coeff = 15000, 4336 .g1_irqs = 9, 4337 .g2_irqs = 10, 4338 .atu_move_port_mask = 0xf, 4339 .pvt = true, 4340 .multi_chip = true, 4341 .tag_protocol = DSA_TAG_PROTO_EDSA, 4342 .ptp_support = true, 4343 .ops = &mv88e6352_ops, 4344 }, 4345 [MV88E6390] = { 4346 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4347 .family = MV88E6XXX_FAMILY_6390, 4348 .name = "Marvell 88E6390", 4349 .num_databases = 4096, 4350 .num_ports = 11, /* 10 + Z80 */ 4351 .num_internal_phys = 11, 4352 .num_gpio = 16, 4353 .max_vid = 8191, 4354 .port_base_addr = 0x0, 4355 .phy_base_addr = 0x0, 4356 .global1_addr = 0x1b, 4357 .global2_addr = 0x1c, 4358 .age_time_coeff = 3750, 4359 .g1_irqs = 9, 4360 .g2_irqs = 14, 4361 .atu_move_port_mask = 0x1f, 4362 .pvt = true, 4363 .multi_chip = true, 4364 .tag_protocol = DSA_TAG_PROTO_DSA, 4365 .ptp_support = true, 4366 .ops = &mv88e6390_ops, 4367 }, 4368 [MV88E6390X] = { 4369 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4370 .family = MV88E6XXX_FAMILY_6390, 4371 .name = "Marvell 88E6390X", 4372 .num_databases = 4096, 4373 .num_ports = 11, /* 10 + Z80 */ 4374 .num_internal_phys = 11, 4375 .num_gpio = 16, 4376 .max_vid = 8191, 4377 .port_base_addr = 0x0, 4378 .phy_base_addr = 0x0, 4379 .global1_addr = 0x1b, 4380 .global2_addr = 0x1c, 4381 .age_time_coeff = 3750, 4382 .g1_irqs = 9, 4383 .g2_irqs = 14, 4384 .atu_move_port_mask = 0x1f, 4385 .pvt = true, 4386 .multi_chip = true, 4387 .tag_protocol = DSA_TAG_PROTO_DSA, 4388 .ptp_support = true, 4389 .ops = &mv88e6390x_ops, 4390 }, 4391 }; 4392 4393 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4394 { 4395 int i; 4396 4397 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4398 if (mv88e6xxx_table[i].prod_num == prod_num) 4399 return &mv88e6xxx_table[i]; 4400 4401 return NULL; 4402 } 4403 4404 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4405 { 4406 const struct mv88e6xxx_info *info; 4407 unsigned int prod_num, rev; 4408 u16 id; 4409 int err; 4410 4411 mutex_lock(&chip->reg_lock); 4412 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4413 mutex_unlock(&chip->reg_lock); 4414 if (err) 4415 return err; 4416 4417 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4418 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4419 4420 info = mv88e6xxx_lookup_info(prod_num); 4421 if (!info) 4422 return -ENODEV; 4423 4424 /* Update the compatible info with the probed one */ 4425 chip->info = info; 4426 4427 err = mv88e6xxx_g2_require(chip); 4428 if (err) 4429 return err; 4430 4431 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4432 chip->info->prod_num, chip->info->name, rev); 4433 4434 return 0; 4435 } 4436 4437 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4438 { 4439 struct mv88e6xxx_chip *chip; 4440 4441 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4442 if (!chip) 4443 return NULL; 4444 4445 chip->dev = dev; 4446 4447 mutex_init(&chip->reg_lock); 4448 INIT_LIST_HEAD(&chip->mdios); 4449 4450 return chip; 4451 } 4452 4453 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4454 struct mii_bus *bus, int sw_addr) 4455 { 4456 if (sw_addr == 0) 4457 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4458 else if (chip->info->multi_chip) 4459 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4460 else 4461 return -EINVAL; 4462 4463 chip->bus = bus; 4464 chip->sw_addr = sw_addr; 4465 4466 return 0; 4467 } 4468 4469 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4470 int port) 4471 { 4472 struct mv88e6xxx_chip *chip = ds->priv; 4473 4474 return chip->info->tag_protocol; 4475 } 4476 4477 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4478 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4479 struct device *host_dev, int sw_addr, 4480 void **priv) 4481 { 4482 struct mv88e6xxx_chip *chip; 4483 struct mii_bus *bus; 4484 int err; 4485 4486 bus = dsa_host_dev_to_mii_bus(host_dev); 4487 if (!bus) 4488 return NULL; 4489 4490 chip = mv88e6xxx_alloc_chip(dsa_dev); 4491 if (!chip) 4492 return NULL; 4493 4494 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4495 chip->info = &mv88e6xxx_table[MV88E6085]; 4496 4497 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4498 if (err) 4499 goto free; 4500 4501 err = mv88e6xxx_detect(chip); 4502 if (err) 4503 goto free; 4504 4505 mutex_lock(&chip->reg_lock); 4506 err = mv88e6xxx_switch_reset(chip); 4507 mutex_unlock(&chip->reg_lock); 4508 if (err) 4509 goto free; 4510 4511 mv88e6xxx_phy_init(chip); 4512 4513 err = mv88e6xxx_mdios_register(chip, NULL); 4514 if (err) 4515 goto free; 4516 4517 *priv = chip; 4518 4519 return chip->info->name; 4520 free: 4521 devm_kfree(dsa_dev, chip); 4522 4523 return NULL; 4524 } 4525 #endif 4526 4527 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4528 const struct switchdev_obj_port_mdb *mdb) 4529 { 4530 /* We don't need any dynamic resource from the kernel (yet), 4531 * so skip the prepare phase. 4532 */ 4533 4534 return 0; 4535 } 4536 4537 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4538 const struct switchdev_obj_port_mdb *mdb) 4539 { 4540 struct mv88e6xxx_chip *chip = ds->priv; 4541 4542 mutex_lock(&chip->reg_lock); 4543 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4544 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4545 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4546 port); 4547 mutex_unlock(&chip->reg_lock); 4548 } 4549 4550 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4551 const struct switchdev_obj_port_mdb *mdb) 4552 { 4553 struct mv88e6xxx_chip *chip = ds->priv; 4554 int err; 4555 4556 mutex_lock(&chip->reg_lock); 4557 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4558 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4559 mutex_unlock(&chip->reg_lock); 4560 4561 return err; 4562 } 4563 4564 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4565 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4566 .probe = mv88e6xxx_drv_probe, 4567 #endif 4568 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4569 .setup = mv88e6xxx_setup, 4570 .adjust_link = mv88e6xxx_adjust_link, 4571 .phylink_validate = mv88e6xxx_validate, 4572 .phylink_mac_link_state = mv88e6xxx_link_state, 4573 .phylink_mac_config = mv88e6xxx_mac_config, 4574 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4575 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4576 .get_strings = mv88e6xxx_get_strings, 4577 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4578 .get_sset_count = mv88e6xxx_get_sset_count, 4579 .port_enable = mv88e6xxx_port_enable, 4580 .port_disable = mv88e6xxx_port_disable, 4581 .get_mac_eee = mv88e6xxx_get_mac_eee, 4582 .set_mac_eee = mv88e6xxx_set_mac_eee, 4583 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4584 .get_eeprom = mv88e6xxx_get_eeprom, 4585 .set_eeprom = mv88e6xxx_set_eeprom, 4586 .get_regs_len = mv88e6xxx_get_regs_len, 4587 .get_regs = mv88e6xxx_get_regs, 4588 .set_ageing_time = mv88e6xxx_set_ageing_time, 4589 .port_bridge_join = mv88e6xxx_port_bridge_join, 4590 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4591 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4592 .port_fast_age = mv88e6xxx_port_fast_age, 4593 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4594 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4595 .port_vlan_add = mv88e6xxx_port_vlan_add, 4596 .port_vlan_del = mv88e6xxx_port_vlan_del, 4597 .port_fdb_add = mv88e6xxx_port_fdb_add, 4598 .port_fdb_del = mv88e6xxx_port_fdb_del, 4599 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4600 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4601 .port_mdb_add = mv88e6xxx_port_mdb_add, 4602 .port_mdb_del = mv88e6xxx_port_mdb_del, 4603 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4604 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4605 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4606 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4607 .port_txtstamp = mv88e6xxx_port_txtstamp, 4608 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4609 .get_ts_info = mv88e6xxx_get_ts_info, 4610 }; 4611 4612 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4613 .ops = &mv88e6xxx_switch_ops, 4614 }; 4615 4616 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4617 { 4618 struct device *dev = chip->dev; 4619 struct dsa_switch *ds; 4620 4621 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4622 if (!ds) 4623 return -ENOMEM; 4624 4625 ds->priv = chip; 4626 ds->dev = dev; 4627 ds->ops = &mv88e6xxx_switch_ops; 4628 ds->ageing_time_min = chip->info->age_time_coeff; 4629 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4630 4631 dev_set_drvdata(dev, ds); 4632 4633 return dsa_register_switch(ds); 4634 } 4635 4636 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4637 { 4638 dsa_unregister_switch(chip->ds); 4639 } 4640 4641 static const void *pdata_device_get_match_data(struct device *dev) 4642 { 4643 const struct of_device_id *matches = dev->driver->of_match_table; 4644 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4645 4646 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4647 matches++) { 4648 if (!strcmp(pdata->compatible, matches->compatible)) 4649 return matches->data; 4650 } 4651 return NULL; 4652 } 4653 4654 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4655 { 4656 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4657 const struct mv88e6xxx_info *compat_info = NULL; 4658 struct device *dev = &mdiodev->dev; 4659 struct device_node *np = dev->of_node; 4660 struct mv88e6xxx_chip *chip; 4661 int port; 4662 int err; 4663 4664 if (!np && !pdata) 4665 return -EINVAL; 4666 4667 if (np) 4668 compat_info = of_device_get_match_data(dev); 4669 4670 if (pdata) { 4671 compat_info = pdata_device_get_match_data(dev); 4672 4673 if (!pdata->netdev) 4674 return -EINVAL; 4675 4676 for (port = 0; port < DSA_MAX_PORTS; port++) { 4677 if (!(pdata->enabled_ports & (1 << port))) 4678 continue; 4679 if (strcmp(pdata->cd.port_names[port], "cpu")) 4680 continue; 4681 pdata->cd.netdev[port] = &pdata->netdev->dev; 4682 break; 4683 } 4684 } 4685 4686 if (!compat_info) 4687 return -EINVAL; 4688 4689 chip = mv88e6xxx_alloc_chip(dev); 4690 if (!chip) { 4691 err = -ENOMEM; 4692 goto out; 4693 } 4694 4695 chip->info = compat_info; 4696 4697 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4698 if (err) 4699 goto out; 4700 4701 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4702 if (IS_ERR(chip->reset)) { 4703 err = PTR_ERR(chip->reset); 4704 goto out; 4705 } 4706 4707 err = mv88e6xxx_detect(chip); 4708 if (err) 4709 goto out; 4710 4711 mv88e6xxx_phy_init(chip); 4712 4713 if (chip->info->ops->get_eeprom) { 4714 if (np) 4715 of_property_read_u32(np, "eeprom-length", 4716 &chip->eeprom_len); 4717 else 4718 chip->eeprom_len = pdata->eeprom_len; 4719 } 4720 4721 mutex_lock(&chip->reg_lock); 4722 err = mv88e6xxx_switch_reset(chip); 4723 mutex_unlock(&chip->reg_lock); 4724 if (err) 4725 goto out; 4726 4727 chip->irq = of_irq_get(np, 0); 4728 if (chip->irq == -EPROBE_DEFER) { 4729 err = chip->irq; 4730 goto out; 4731 } 4732 4733 /* Has to be performed before the MDIO bus is created, because 4734 * the PHYs will link their interrupts to these interrupt 4735 * controllers 4736 */ 4737 mutex_lock(&chip->reg_lock); 4738 if (chip->irq > 0) 4739 err = mv88e6xxx_g1_irq_setup(chip); 4740 else 4741 err = mv88e6xxx_irq_poll_setup(chip); 4742 mutex_unlock(&chip->reg_lock); 4743 4744 if (err) 4745 goto out; 4746 4747 if (chip->info->g2_irqs > 0) { 4748 err = mv88e6xxx_g2_irq_setup(chip); 4749 if (err) 4750 goto out_g1_irq; 4751 } 4752 4753 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4754 if (err) 4755 goto out_g2_irq; 4756 4757 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4758 if (err) 4759 goto out_g1_atu_prob_irq; 4760 4761 err = mv88e6xxx_mdios_register(chip, np); 4762 if (err) 4763 goto out_g1_vtu_prob_irq; 4764 4765 err = mv88e6xxx_register_switch(chip); 4766 if (err) 4767 goto out_mdio; 4768 4769 return 0; 4770 4771 out_mdio: 4772 mv88e6xxx_mdios_unregister(chip); 4773 out_g1_vtu_prob_irq: 4774 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4775 out_g1_atu_prob_irq: 4776 mv88e6xxx_g1_atu_prob_irq_free(chip); 4777 out_g2_irq: 4778 if (chip->info->g2_irqs > 0) 4779 mv88e6xxx_g2_irq_free(chip); 4780 out_g1_irq: 4781 if (chip->irq > 0) 4782 mv88e6xxx_g1_irq_free(chip); 4783 else 4784 mv88e6xxx_irq_poll_free(chip); 4785 out: 4786 if (pdata) 4787 dev_put(pdata->netdev); 4788 4789 return err; 4790 } 4791 4792 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4793 { 4794 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4795 struct mv88e6xxx_chip *chip = ds->priv; 4796 4797 if (chip->info->ptp_support) { 4798 mv88e6xxx_hwtstamp_free(chip); 4799 mv88e6xxx_ptp_free(chip); 4800 } 4801 4802 mv88e6xxx_phy_destroy(chip); 4803 mv88e6xxx_unregister_switch(chip); 4804 mv88e6xxx_mdios_unregister(chip); 4805 4806 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4807 mv88e6xxx_g1_atu_prob_irq_free(chip); 4808 4809 if (chip->info->g2_irqs > 0) 4810 mv88e6xxx_g2_irq_free(chip); 4811 4812 if (chip->irq > 0) 4813 mv88e6xxx_g1_irq_free(chip); 4814 else 4815 mv88e6xxx_irq_poll_free(chip); 4816 } 4817 4818 static const struct of_device_id mv88e6xxx_of_match[] = { 4819 { 4820 .compatible = "marvell,mv88e6085", 4821 .data = &mv88e6xxx_table[MV88E6085], 4822 }, 4823 { 4824 .compatible = "marvell,mv88e6190", 4825 .data = &mv88e6xxx_table[MV88E6190], 4826 }, 4827 { /* sentinel */ }, 4828 }; 4829 4830 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4831 4832 static struct mdio_driver mv88e6xxx_driver = { 4833 .probe = mv88e6xxx_probe, 4834 .remove = mv88e6xxx_remove, 4835 .mdiodrv.driver = { 4836 .name = "mv88e6085", 4837 .of_match_table = mv88e6xxx_of_match, 4838 }, 4839 }; 4840 4841 static int __init mv88e6xxx_init(void) 4842 { 4843 register_switch_driver(&mv88e6xxx_switch_drv); 4844 return mdio_driver_register(&mv88e6xxx_driver); 4845 } 4846 module_init(mv88e6xxx_init); 4847 4848 static void __exit mv88e6xxx_cleanup(void) 4849 { 4850 mdio_driver_unregister(&mv88e6xxx_driver); 4851 unregister_switch_driver(&mv88e6xxx_switch_drv); 4852 } 4853 module_exit(mv88e6xxx_cleanup); 4854 4855 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4856 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4857 MODULE_LICENSE("GPL"); 4858