1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121 } 122 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125 { 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128 } 129 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131 { 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140 } 141 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143 { 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148 } 149 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151 { 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159 { 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189 unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196 out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198 } 199 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201 { 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212 } 213 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215 { 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232 out: 233 mv88e6xxx_reg_unlock(chip); 234 } 235 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242 }; 243 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247 { 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255 } 256 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260 }; 261 262 /* To be called with reg_lock held */ 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264 { 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278 } 279 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281 { 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291 } 292 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294 { 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328 out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332 out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341 } 342 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344 { 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372 } 373 374 static void mv88e6xxx_irq_poll(struct kthread_work *work) 375 { 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 } 384 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386 { 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404 } 405 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407 { 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414 } 415 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418 { 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436 } 437 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441 { 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466 restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471 } 472 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474 { 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478 } 479 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481 { 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500 } 501 502 static const u8 mv88e6185_phy_interface_modes[] = { 503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 510 }; 511 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 513 struct phylink_config *config) 514 { 515 u8 cmode = chip->ports[port].cmode; 516 517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 518 519 if (mv88e6xxx_phy_is_internal(chip, port)) { 520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 521 } else { 522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 523 mv88e6185_phy_interface_modes[cmode]) 524 __set_bit(mv88e6185_phy_interface_modes[cmode], 525 config->supported_interfaces); 526 527 config->mac_capabilities |= MAC_1000FD; 528 } 529 } 530 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 532 struct phylink_config *config) 533 { 534 u8 cmode = chip->ports[port].cmode; 535 536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 537 mv88e6185_phy_interface_modes[cmode]) 538 __set_bit(mv88e6185_phy_interface_modes[cmode], 539 config->supported_interfaces); 540 541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 542 MAC_1000FD; 543 } 544 545 static const u8 mv88e6xxx_phy_interface_modes[] = { 546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 554 /* higher interface modes are not needed here, since ports supporting 555 * them are writable, and so the supported interfaces are filled in the 556 * corresponding .phylink_set_interfaces() implementation below 557 */ 558 }; 559 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 561 { 562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 563 mv88e6xxx_phy_interface_modes[cmode]) 564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 566 phy_interface_set_rgmii(supported); 567 } 568 569 static void 570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 571 struct phylink_config *config) 572 { 573 unsigned long *supported = config->supported_interfaces; 574 int err; 575 u16 reg; 576 577 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 578 if (err) { 579 dev_err(chip->dev, "p%d: failed to read port status\n", port); 580 return; 581 } 582 583 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 584 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 585 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 588 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 589 break; 590 591 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 592 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 593 __set_bit(PHY_INTERFACE_MODE_MII, supported); 594 break; 595 596 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 597 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 600 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 601 break; 602 603 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 604 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 605 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 606 break; 607 608 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 609 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 610 break; 611 612 default: 613 dev_err(chip->dev, 614 "p%d: invalid port mode in status register: %04x\n", 615 port, reg); 616 } 617 } 618 619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 620 struct phylink_config *config) 621 { 622 if (!mv88e6xxx_phy_is_internal(chip, port)) 623 mv88e6250_setup_supported_interfaces(chip, port, config); 624 625 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 626 } 627 628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 629 struct phylink_config *config) 630 { 631 unsigned long *supported = config->supported_interfaces; 632 633 /* Translate the default cmode */ 634 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 635 636 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 637 MAC_1000FD; 638 } 639 640 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 641 { 642 u16 reg, val; 643 int err; 644 645 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 646 if (err) 647 return err; 648 649 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 650 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 651 return 0xf; 652 653 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 654 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 655 if (err) 656 return err; 657 658 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 659 if (err) 660 return err; 661 662 /* Restore PHY_DETECT value */ 663 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 664 if (err) 665 return err; 666 667 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 668 } 669 670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 671 struct phylink_config *config) 672 { 673 unsigned long *supported = config->supported_interfaces; 674 int err, cmode; 675 676 /* Translate the default cmode */ 677 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 678 679 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 680 MAC_1000FD; 681 682 /* Port 4 supports automedia if the serdes is associated with it. */ 683 if (port == 4) { 684 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 685 if (err < 0) 686 dev_err(chip->dev, "p%d: failed to read scratch\n", 687 port); 688 if (err <= 0) 689 return; 690 691 cmode = mv88e6352_get_port4_serdes_cmode(chip); 692 if (cmode < 0) 693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 694 port); 695 else 696 mv88e6xxx_translate_cmode(cmode, supported); 697 } 698 } 699 700 static void mv88e632x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 701 struct phylink_config *config) 702 { 703 unsigned long *supported = config->supported_interfaces; 704 705 /* Translate the default cmode */ 706 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 707 708 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 709 MAC_1000FD; 710 } 711 712 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 713 struct phylink_config *config) 714 { 715 unsigned long *supported = config->supported_interfaces; 716 717 /* Translate the default cmode */ 718 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 719 720 /* No ethtool bits for 200Mbps */ 721 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 722 MAC_1000FD; 723 724 /* The C_Mode field is programmable on port 5 */ 725 if (port == 5) { 726 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 727 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 728 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 729 730 config->mac_capabilities |= MAC_2500FD; 731 } 732 } 733 734 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 735 struct phylink_config *config) 736 { 737 unsigned long *supported = config->supported_interfaces; 738 739 /* Translate the default cmode */ 740 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 741 742 /* No ethtool bits for 200Mbps */ 743 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 744 MAC_1000FD; 745 746 /* The C_Mode field is programmable on ports 9 and 10 */ 747 if (port == 9 || port == 10) { 748 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 749 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 750 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 751 752 config->mac_capabilities |= MAC_2500FD; 753 } 754 } 755 756 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 757 struct phylink_config *config) 758 { 759 unsigned long *supported = config->supported_interfaces; 760 761 mv88e6390_phylink_get_caps(chip, port, config); 762 763 /* For the 6x90X, ports 2-7 can be in automedia mode. 764 * (Note that 6x90 doesn't support RXAUI nor XAUI). 765 * 766 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 767 * configured for 1000BASE-X, SGMII or 2500BASE-X. 768 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 769 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 770 * 771 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 772 * configured for 1000BASE-X, SGMII or 2500BASE-X. 773 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 774 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 775 * 776 * For now, be permissive (as the old code was) and allow 1000BASE-X 777 * on ports 2..7. 778 */ 779 if (port >= 2 && port <= 7) 780 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 781 782 /* The C_Mode field can also be programmed for 10G speeds */ 783 if (port == 9 || port == 10) { 784 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 785 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 786 787 config->mac_capabilities |= MAC_10000FD; 788 } 789 } 790 791 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 792 struct phylink_config *config) 793 { 794 unsigned long *supported = config->supported_interfaces; 795 bool is_6191x = 796 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 797 bool is_6361 = 798 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 799 800 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 801 802 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 803 MAC_1000FD; 804 805 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 806 if (port == 0 || port == 9 || port == 10) { 807 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 808 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 809 810 /* 6191X supports >1G modes only on port 10 */ 811 if (!is_6191x || port == 10) { 812 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 813 config->mac_capabilities |= MAC_2500FD; 814 815 /* 6361 only supports up to 2500BaseX */ 816 if (!is_6361) { 817 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 818 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 819 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 820 config->mac_capabilities |= MAC_5000FD | 821 MAC_10000FD; 822 } 823 } 824 } 825 826 if (port == 0) { 827 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 828 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 829 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 830 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 831 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 832 } 833 } 834 835 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 836 struct phylink_config *config) 837 { 838 struct mv88e6xxx_chip *chip = ds->priv; 839 840 mv88e6xxx_reg_lock(chip); 841 chip->info->ops->phylink_get_caps(chip, port, config); 842 mv88e6xxx_reg_unlock(chip); 843 844 if (mv88e6xxx_phy_is_internal(chip, port)) { 845 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 846 config->supported_interfaces); 847 /* Internal ports with no phy-mode need GMII for PHYLIB */ 848 __set_bit(PHY_INTERFACE_MODE_GMII, 849 config->supported_interfaces); 850 } 851 } 852 853 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds, 854 int port, 855 phy_interface_t interface) 856 { 857 struct mv88e6xxx_chip *chip = ds->priv; 858 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); 859 860 if (chip->info->ops->pcs_ops) 861 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port, 862 interface); 863 864 return pcs; 865 } 866 867 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 868 unsigned int mode, phy_interface_t interface) 869 { 870 struct mv88e6xxx_chip *chip = ds->priv; 871 int err = 0; 872 873 /* In inband mode, the link may come up at any time while the link 874 * is not forced down. Force the link down while we reconfigure the 875 * interface mode. 876 */ 877 if (mode == MLO_AN_INBAND && 878 chip->ports[port].interface != interface && 879 chip->info->ops->port_set_link) { 880 mv88e6xxx_reg_lock(chip); 881 err = chip->info->ops->port_set_link(chip, port, 882 LINK_FORCED_DOWN); 883 mv88e6xxx_reg_unlock(chip); 884 } 885 886 return err; 887 } 888 889 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 890 unsigned int mode, 891 const struct phylink_link_state *state) 892 { 893 struct mv88e6xxx_chip *chip = ds->priv; 894 int err = 0; 895 896 mv88e6xxx_reg_lock(chip); 897 898 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 899 err = mv88e6xxx_port_config_interface(chip, port, 900 state->interface); 901 if (err && err != -EOPNOTSUPP) 902 goto err_unlock; 903 } 904 905 err_unlock: 906 mv88e6xxx_reg_unlock(chip); 907 908 if (err && err != -EOPNOTSUPP) 909 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 910 } 911 912 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 913 unsigned int mode, phy_interface_t interface) 914 { 915 struct mv88e6xxx_chip *chip = ds->priv; 916 int err = 0; 917 918 /* Undo the forced down state above after completing configuration 919 * irrespective of its state on entry, which allows the link to come 920 * up in the in-band case where there is no separate SERDES. Also 921 * ensure that the link can come up if the PPU is in use and we are 922 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 923 */ 924 mv88e6xxx_reg_lock(chip); 925 926 if (chip->info->ops->port_set_link && 927 ((mode == MLO_AN_INBAND && 928 chip->ports[port].interface != interface) || 929 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 930 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 931 932 mv88e6xxx_reg_unlock(chip); 933 934 chip->ports[port].interface = interface; 935 936 return err; 937 } 938 939 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 940 unsigned int mode, 941 phy_interface_t interface) 942 { 943 struct mv88e6xxx_chip *chip = ds->priv; 944 const struct mv88e6xxx_ops *ops; 945 int err = 0; 946 947 ops = chip->info->ops; 948 949 mv88e6xxx_reg_lock(chip); 950 /* Force the link down if we know the port may not be automatically 951 * updated by the switch or if we are using fixed-link mode. 952 */ 953 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 954 mode == MLO_AN_FIXED) && ops->port_sync_link) 955 err = ops->port_sync_link(chip, port, mode, false); 956 957 if (!err && ops->port_set_speed_duplex) 958 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 959 DUPLEX_UNFORCED); 960 mv88e6xxx_reg_unlock(chip); 961 962 if (err) 963 dev_err(chip->dev, 964 "p%d: failed to force MAC link down\n", port); 965 } 966 967 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 968 unsigned int mode, phy_interface_t interface, 969 struct phy_device *phydev, 970 int speed, int duplex, 971 bool tx_pause, bool rx_pause) 972 { 973 struct mv88e6xxx_chip *chip = ds->priv; 974 const struct mv88e6xxx_ops *ops; 975 int err = 0; 976 977 ops = chip->info->ops; 978 979 mv88e6xxx_reg_lock(chip); 980 /* Configure and force the link up if we know that the port may not 981 * automatically updated by the switch or if we are using fixed-link 982 * mode. 983 */ 984 if (!mv88e6xxx_port_ppu_updates(chip, port) || 985 mode == MLO_AN_FIXED) { 986 if (ops->port_set_speed_duplex) { 987 err = ops->port_set_speed_duplex(chip, port, 988 speed, duplex); 989 if (err && err != -EOPNOTSUPP) 990 goto error; 991 } 992 993 if (ops->port_sync_link) 994 err = ops->port_sync_link(chip, port, mode, true); 995 } 996 error: 997 mv88e6xxx_reg_unlock(chip); 998 999 if (err && err != -EOPNOTSUPP) 1000 dev_err(ds->dev, 1001 "p%d: failed to configure MAC link up\n", port); 1002 } 1003 1004 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1005 { 1006 if (!chip->info->ops->stats_snapshot) 1007 return -EOPNOTSUPP; 1008 1009 return chip->info->ops->stats_snapshot(chip, port); 1010 } 1011 1012 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1013 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 1014 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 1015 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 1016 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 1017 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 1018 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 1019 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 1020 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 1021 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 1022 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 1023 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 1024 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1025 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1026 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1027 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1028 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1029 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1030 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1031 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1032 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1033 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1034 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1035 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1036 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1037 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1038 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1039 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1040 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1041 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1042 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1043 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1044 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1045 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1046 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1047 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1048 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1049 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1050 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1051 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1052 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1053 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1054 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1055 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1056 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1057 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1058 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1059 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1060 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1061 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1062 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1063 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1064 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1065 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1066 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1067 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1068 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1069 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1070 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1071 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1072 }; 1073 1074 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1075 struct mv88e6xxx_hw_stat *s, 1076 int port, u16 bank1_select, 1077 u16 histogram) 1078 { 1079 u32 low; 1080 u32 high = 0; 1081 u16 reg = 0; 1082 int err; 1083 u64 value; 1084 1085 switch (s->type) { 1086 case STATS_TYPE_PORT: 1087 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1088 if (err) 1089 return U64_MAX; 1090 1091 low = reg; 1092 if (s->size == 4) { 1093 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1094 if (err) 1095 return U64_MAX; 1096 low |= ((u32)reg) << 16; 1097 } 1098 break; 1099 case STATS_TYPE_BANK1: 1100 reg = bank1_select; 1101 fallthrough; 1102 case STATS_TYPE_BANK0: 1103 reg |= s->reg | histogram; 1104 mv88e6xxx_g1_stats_read(chip, reg, &low); 1105 if (s->size == 8) 1106 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1107 break; 1108 default: 1109 return U64_MAX; 1110 } 1111 value = (((u64)high) << 32) | low; 1112 return value; 1113 } 1114 1115 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1116 uint8_t *data, int types) 1117 { 1118 struct mv88e6xxx_hw_stat *stat; 1119 int i, j; 1120 1121 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1122 stat = &mv88e6xxx_hw_stats[i]; 1123 if (stat->type & types) { 1124 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1125 ETH_GSTRING_LEN); 1126 j++; 1127 } 1128 } 1129 1130 return j; 1131 } 1132 1133 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1134 uint8_t *data) 1135 { 1136 return mv88e6xxx_stats_get_strings(chip, data, 1137 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1138 } 1139 1140 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1141 uint8_t *data) 1142 { 1143 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1144 } 1145 1146 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1147 uint8_t *data) 1148 { 1149 return mv88e6xxx_stats_get_strings(chip, data, 1150 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1151 } 1152 1153 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1154 "atu_member_violation", 1155 "atu_miss_violation", 1156 "atu_full_violation", 1157 "vtu_member_violation", 1158 "vtu_miss_violation", 1159 }; 1160 1161 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1162 { 1163 unsigned int i; 1164 1165 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1166 strscpy(data + i * ETH_GSTRING_LEN, 1167 mv88e6xxx_atu_vtu_stats_strings[i], 1168 ETH_GSTRING_LEN); 1169 } 1170 1171 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1172 u32 stringset, uint8_t *data) 1173 { 1174 struct mv88e6xxx_chip *chip = ds->priv; 1175 int count = 0; 1176 1177 if (stringset != ETH_SS_STATS) 1178 return; 1179 1180 mv88e6xxx_reg_lock(chip); 1181 1182 if (chip->info->ops->stats_get_strings) 1183 count = chip->info->ops->stats_get_strings(chip, data); 1184 1185 if (chip->info->ops->serdes_get_strings) { 1186 data += count * ETH_GSTRING_LEN; 1187 count = chip->info->ops->serdes_get_strings(chip, port, data); 1188 } 1189 1190 data += count * ETH_GSTRING_LEN; 1191 mv88e6xxx_atu_vtu_get_strings(data); 1192 1193 mv88e6xxx_reg_unlock(chip); 1194 } 1195 1196 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1197 int types) 1198 { 1199 struct mv88e6xxx_hw_stat *stat; 1200 int i, j; 1201 1202 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1203 stat = &mv88e6xxx_hw_stats[i]; 1204 if (stat->type & types) 1205 j++; 1206 } 1207 return j; 1208 } 1209 1210 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1211 { 1212 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1213 STATS_TYPE_PORT); 1214 } 1215 1216 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1217 { 1218 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1219 } 1220 1221 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1222 { 1223 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1224 STATS_TYPE_BANK1); 1225 } 1226 1227 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1228 { 1229 struct mv88e6xxx_chip *chip = ds->priv; 1230 int serdes_count = 0; 1231 int count = 0; 1232 1233 if (sset != ETH_SS_STATS) 1234 return 0; 1235 1236 mv88e6xxx_reg_lock(chip); 1237 if (chip->info->ops->stats_get_sset_count) 1238 count = chip->info->ops->stats_get_sset_count(chip); 1239 if (count < 0) 1240 goto out; 1241 1242 if (chip->info->ops->serdes_get_sset_count) 1243 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1244 port); 1245 if (serdes_count < 0) { 1246 count = serdes_count; 1247 goto out; 1248 } 1249 count += serdes_count; 1250 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1251 1252 out: 1253 mv88e6xxx_reg_unlock(chip); 1254 1255 return count; 1256 } 1257 1258 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1259 uint64_t *data, int types, 1260 u16 bank1_select, u16 histogram) 1261 { 1262 struct mv88e6xxx_hw_stat *stat; 1263 int i, j; 1264 1265 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1266 stat = &mv88e6xxx_hw_stats[i]; 1267 if (stat->type & types) { 1268 mv88e6xxx_reg_lock(chip); 1269 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1270 bank1_select, 1271 histogram); 1272 mv88e6xxx_reg_unlock(chip); 1273 1274 j++; 1275 } 1276 } 1277 return j; 1278 } 1279 1280 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1281 uint64_t *data) 1282 { 1283 return mv88e6xxx_stats_get_stats(chip, port, data, 1284 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1285 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1286 } 1287 1288 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1289 uint64_t *data) 1290 { 1291 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1292 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1293 } 1294 1295 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1296 uint64_t *data) 1297 { 1298 return mv88e6xxx_stats_get_stats(chip, port, data, 1299 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1300 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1301 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1302 } 1303 1304 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1305 uint64_t *data) 1306 { 1307 return mv88e6xxx_stats_get_stats(chip, port, data, 1308 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1309 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1310 0); 1311 } 1312 1313 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1314 uint64_t *data) 1315 { 1316 *data++ = chip->ports[port].atu_member_violation; 1317 *data++ = chip->ports[port].atu_miss_violation; 1318 *data++ = chip->ports[port].atu_full_violation; 1319 *data++ = chip->ports[port].vtu_member_violation; 1320 *data++ = chip->ports[port].vtu_miss_violation; 1321 } 1322 1323 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1324 uint64_t *data) 1325 { 1326 int count = 0; 1327 1328 if (chip->info->ops->stats_get_stats) 1329 count = chip->info->ops->stats_get_stats(chip, port, data); 1330 1331 mv88e6xxx_reg_lock(chip); 1332 if (chip->info->ops->serdes_get_stats) { 1333 data += count; 1334 count = chip->info->ops->serdes_get_stats(chip, port, data); 1335 } 1336 data += count; 1337 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1338 mv88e6xxx_reg_unlock(chip); 1339 } 1340 1341 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1342 uint64_t *data) 1343 { 1344 struct mv88e6xxx_chip *chip = ds->priv; 1345 int ret; 1346 1347 mv88e6xxx_reg_lock(chip); 1348 1349 ret = mv88e6xxx_stats_snapshot(chip, port); 1350 mv88e6xxx_reg_unlock(chip); 1351 1352 if (ret < 0) 1353 return; 1354 1355 mv88e6xxx_get_stats(chip, port, data); 1356 1357 } 1358 1359 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1360 { 1361 struct mv88e6xxx_chip *chip = ds->priv; 1362 int len; 1363 1364 len = 32 * sizeof(u16); 1365 if (chip->info->ops->serdes_get_regs_len) 1366 len += chip->info->ops->serdes_get_regs_len(chip, port); 1367 1368 return len; 1369 } 1370 1371 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1372 struct ethtool_regs *regs, void *_p) 1373 { 1374 struct mv88e6xxx_chip *chip = ds->priv; 1375 int err; 1376 u16 reg; 1377 u16 *p = _p; 1378 int i; 1379 1380 regs->version = chip->info->prod_num; 1381 1382 memset(p, 0xff, 32 * sizeof(u16)); 1383 1384 mv88e6xxx_reg_lock(chip); 1385 1386 for (i = 0; i < 32; i++) { 1387 1388 err = mv88e6xxx_port_read(chip, port, i, ®); 1389 if (!err) 1390 p[i] = reg; 1391 } 1392 1393 if (chip->info->ops->serdes_get_regs) 1394 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1395 1396 mv88e6xxx_reg_unlock(chip); 1397 } 1398 1399 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1400 struct ethtool_eee *e) 1401 { 1402 /* Nothing to do on the port's MAC */ 1403 return 0; 1404 } 1405 1406 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1407 struct ethtool_eee *e) 1408 { 1409 /* Nothing to do on the port's MAC */ 1410 return 0; 1411 } 1412 1413 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1414 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1415 { 1416 struct dsa_switch *ds = chip->ds; 1417 struct dsa_switch_tree *dst = ds->dst; 1418 struct dsa_port *dp, *other_dp; 1419 bool found = false; 1420 u16 pvlan; 1421 1422 /* dev is a physical switch */ 1423 if (dev <= dst->last_switch) { 1424 list_for_each_entry(dp, &dst->ports, list) { 1425 if (dp->ds->index == dev && dp->index == port) { 1426 /* dp might be a DSA link or a user port, so it 1427 * might or might not have a bridge. 1428 * Use the "found" variable for both cases. 1429 */ 1430 found = true; 1431 break; 1432 } 1433 } 1434 /* dev is a virtual bridge */ 1435 } else { 1436 list_for_each_entry(dp, &dst->ports, list) { 1437 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1438 1439 if (!bridge_num) 1440 continue; 1441 1442 if (bridge_num + dst->last_switch != dev) 1443 continue; 1444 1445 found = true; 1446 break; 1447 } 1448 } 1449 1450 /* Prevent frames from unknown switch or virtual bridge */ 1451 if (!found) 1452 return 0; 1453 1454 /* Frames from DSA links and CPU ports can egress any local port */ 1455 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1456 return mv88e6xxx_port_mask(chip); 1457 1458 pvlan = 0; 1459 1460 /* Frames from standalone user ports can only egress on the 1461 * upstream port. 1462 */ 1463 if (!dsa_port_bridge_dev_get(dp)) 1464 return BIT(dsa_switch_upstream_port(ds)); 1465 1466 /* Frames from bridged user ports can egress any local DSA 1467 * links and CPU ports, as well as any local member of their 1468 * bridge group. 1469 */ 1470 dsa_switch_for_each_port(other_dp, ds) 1471 if (other_dp->type == DSA_PORT_TYPE_CPU || 1472 other_dp->type == DSA_PORT_TYPE_DSA || 1473 dsa_port_bridge_same(dp, other_dp)) 1474 pvlan |= BIT(other_dp->index); 1475 1476 return pvlan; 1477 } 1478 1479 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1480 { 1481 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1482 1483 /* prevent frames from going back out of the port they came in on */ 1484 output_ports &= ~BIT(port); 1485 1486 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1487 } 1488 1489 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1490 u8 state) 1491 { 1492 struct mv88e6xxx_chip *chip = ds->priv; 1493 int err; 1494 1495 mv88e6xxx_reg_lock(chip); 1496 err = mv88e6xxx_port_set_state(chip, port, state); 1497 mv88e6xxx_reg_unlock(chip); 1498 1499 if (err) 1500 dev_err(ds->dev, "p%d: failed to update state\n", port); 1501 } 1502 1503 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1504 { 1505 int err; 1506 1507 if (chip->info->ops->ieee_pri_map) { 1508 err = chip->info->ops->ieee_pri_map(chip); 1509 if (err) 1510 return err; 1511 } 1512 1513 if (chip->info->ops->ip_pri_map) { 1514 err = chip->info->ops->ip_pri_map(chip); 1515 if (err) 1516 return err; 1517 } 1518 1519 return 0; 1520 } 1521 1522 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1523 { 1524 struct dsa_switch *ds = chip->ds; 1525 int target, port; 1526 int err; 1527 1528 if (!chip->info->global2_addr) 1529 return 0; 1530 1531 /* Initialize the routing port to the 32 possible target devices */ 1532 for (target = 0; target < 32; target++) { 1533 port = dsa_routing_port(ds, target); 1534 if (port == ds->num_ports) 1535 port = 0x1f; 1536 1537 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1538 if (err) 1539 return err; 1540 } 1541 1542 if (chip->info->ops->set_cascade_port) { 1543 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1544 err = chip->info->ops->set_cascade_port(chip, port); 1545 if (err) 1546 return err; 1547 } 1548 1549 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1550 if (err) 1551 return err; 1552 1553 return 0; 1554 } 1555 1556 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1557 { 1558 /* Clear all trunk masks and mapping */ 1559 if (chip->info->global2_addr) 1560 return mv88e6xxx_g2_trunk_clear(chip); 1561 1562 return 0; 1563 } 1564 1565 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1566 { 1567 if (chip->info->ops->rmu_disable) 1568 return chip->info->ops->rmu_disable(chip); 1569 1570 return 0; 1571 } 1572 1573 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1574 { 1575 if (chip->info->ops->pot_clear) 1576 return chip->info->ops->pot_clear(chip); 1577 1578 return 0; 1579 } 1580 1581 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1582 { 1583 if (chip->info->ops->mgmt_rsvd2cpu) 1584 return chip->info->ops->mgmt_rsvd2cpu(chip); 1585 1586 return 0; 1587 } 1588 1589 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1590 { 1591 int err; 1592 1593 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1594 if (err) 1595 return err; 1596 1597 /* The chips that have a "learn2all" bit in Global1, ATU 1598 * Control are precisely those whose port registers have a 1599 * Message Port bit in Port Control 1 and hence implement 1600 * ->port_setup_message_port. 1601 */ 1602 if (chip->info->ops->port_setup_message_port) { 1603 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1604 if (err) 1605 return err; 1606 } 1607 1608 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1609 } 1610 1611 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1612 { 1613 int port; 1614 int err; 1615 1616 if (!chip->info->ops->irl_init_all) 1617 return 0; 1618 1619 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1620 /* Disable ingress rate limiting by resetting all per port 1621 * ingress rate limit resources to their initial state. 1622 */ 1623 err = chip->info->ops->irl_init_all(chip, port); 1624 if (err) 1625 return err; 1626 } 1627 1628 return 0; 1629 } 1630 1631 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1632 { 1633 if (chip->info->ops->set_switch_mac) { 1634 u8 addr[ETH_ALEN]; 1635 1636 eth_random_addr(addr); 1637 1638 return chip->info->ops->set_switch_mac(chip, addr); 1639 } 1640 1641 return 0; 1642 } 1643 1644 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1645 { 1646 struct dsa_switch_tree *dst = chip->ds->dst; 1647 struct dsa_switch *ds; 1648 struct dsa_port *dp; 1649 u16 pvlan = 0; 1650 1651 if (!mv88e6xxx_has_pvt(chip)) 1652 return 0; 1653 1654 /* Skip the local source device, which uses in-chip port VLAN */ 1655 if (dev != chip->ds->index) { 1656 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1657 1658 ds = dsa_switch_find(dst->index, dev); 1659 dp = ds ? dsa_to_port(ds, port) : NULL; 1660 if (dp && dp->lag) { 1661 /* As the PVT is used to limit flooding of 1662 * FORWARD frames, which use the LAG ID as the 1663 * source port, we must translate dev/port to 1664 * the special "LAG device" in the PVT, using 1665 * the LAG ID (one-based) as the port number 1666 * (zero-based). 1667 */ 1668 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1669 port = dsa_port_lag_id_get(dp) - 1; 1670 } 1671 } 1672 1673 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1674 } 1675 1676 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1677 { 1678 int dev, port; 1679 int err; 1680 1681 if (!mv88e6xxx_has_pvt(chip)) 1682 return 0; 1683 1684 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1685 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1686 */ 1687 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1688 if (err) 1689 return err; 1690 1691 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1692 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1693 err = mv88e6xxx_pvt_map(chip, dev, port); 1694 if (err) 1695 return err; 1696 } 1697 } 1698 1699 return 0; 1700 } 1701 1702 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1703 u16 fid) 1704 { 1705 if (dsa_to_port(chip->ds, port)->lag) 1706 /* Hardware is incapable of fast-aging a LAG through a 1707 * regular ATU move operation. Until we have something 1708 * more fancy in place this is a no-op. 1709 */ 1710 return -EOPNOTSUPP; 1711 1712 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1713 } 1714 1715 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1716 { 1717 struct mv88e6xxx_chip *chip = ds->priv; 1718 int err; 1719 1720 mv88e6xxx_reg_lock(chip); 1721 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1722 mv88e6xxx_reg_unlock(chip); 1723 1724 if (err) 1725 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1726 port, err); 1727 } 1728 1729 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1730 { 1731 if (!mv88e6xxx_max_vid(chip)) 1732 return 0; 1733 1734 return mv88e6xxx_g1_vtu_flush(chip); 1735 } 1736 1737 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1738 struct mv88e6xxx_vtu_entry *entry) 1739 { 1740 int err; 1741 1742 if (!chip->info->ops->vtu_getnext) 1743 return -EOPNOTSUPP; 1744 1745 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1746 entry->valid = false; 1747 1748 err = chip->info->ops->vtu_getnext(chip, entry); 1749 1750 if (entry->vid != vid) 1751 entry->valid = false; 1752 1753 return err; 1754 } 1755 1756 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1757 int (*cb)(struct mv88e6xxx_chip *chip, 1758 const struct mv88e6xxx_vtu_entry *entry, 1759 void *priv), 1760 void *priv) 1761 { 1762 struct mv88e6xxx_vtu_entry entry = { 1763 .vid = mv88e6xxx_max_vid(chip), 1764 .valid = false, 1765 }; 1766 int err; 1767 1768 if (!chip->info->ops->vtu_getnext) 1769 return -EOPNOTSUPP; 1770 1771 do { 1772 err = chip->info->ops->vtu_getnext(chip, &entry); 1773 if (err) 1774 return err; 1775 1776 if (!entry.valid) 1777 break; 1778 1779 err = cb(chip, &entry, priv); 1780 if (err) 1781 return err; 1782 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1783 1784 return 0; 1785 } 1786 1787 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1788 struct mv88e6xxx_vtu_entry *entry) 1789 { 1790 if (!chip->info->ops->vtu_loadpurge) 1791 return -EOPNOTSUPP; 1792 1793 return chip->info->ops->vtu_loadpurge(chip, entry); 1794 } 1795 1796 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1797 const struct mv88e6xxx_vtu_entry *entry, 1798 void *_fid_bitmap) 1799 { 1800 unsigned long *fid_bitmap = _fid_bitmap; 1801 1802 set_bit(entry->fid, fid_bitmap); 1803 return 0; 1804 } 1805 1806 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1807 { 1808 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1809 1810 /* Every FID has an associated VID, so walking the VTU 1811 * will discover the full set of FIDs in use. 1812 */ 1813 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1814 } 1815 1816 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1817 { 1818 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1819 int err; 1820 1821 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1822 if (err) 1823 return err; 1824 1825 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1826 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1827 return -ENOSPC; 1828 1829 /* Clear the database */ 1830 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1831 } 1832 1833 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1834 struct mv88e6xxx_stu_entry *entry) 1835 { 1836 if (!chip->info->ops->stu_loadpurge) 1837 return -EOPNOTSUPP; 1838 1839 return chip->info->ops->stu_loadpurge(chip, entry); 1840 } 1841 1842 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1843 { 1844 struct mv88e6xxx_stu_entry stu = { 1845 .valid = true, 1846 .sid = 0 1847 }; 1848 1849 if (!mv88e6xxx_has_stu(chip)) 1850 return 0; 1851 1852 /* Make sure that SID 0 is always valid. This is used by VTU 1853 * entries that do not make use of the STU, e.g. when creating 1854 * a VLAN upper on a port that is also part of a VLAN 1855 * filtering bridge. 1856 */ 1857 return mv88e6xxx_stu_loadpurge(chip, &stu); 1858 } 1859 1860 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1861 { 1862 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1863 struct mv88e6xxx_mst *mst; 1864 1865 __set_bit(0, busy); 1866 1867 list_for_each_entry(mst, &chip->msts, node) 1868 __set_bit(mst->stu.sid, busy); 1869 1870 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1871 1872 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1873 } 1874 1875 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1876 { 1877 struct mv88e6xxx_mst *mst, *tmp; 1878 int err; 1879 1880 if (!sid) 1881 return 0; 1882 1883 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1884 if (mst->stu.sid != sid) 1885 continue; 1886 1887 if (!refcount_dec_and_test(&mst->refcnt)) 1888 return 0; 1889 1890 mst->stu.valid = false; 1891 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1892 if (err) { 1893 refcount_set(&mst->refcnt, 1); 1894 return err; 1895 } 1896 1897 list_del(&mst->node); 1898 kfree(mst); 1899 return 0; 1900 } 1901 1902 return -ENOENT; 1903 } 1904 1905 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1906 u16 msti, u8 *sid) 1907 { 1908 struct mv88e6xxx_mst *mst; 1909 int err, i; 1910 1911 if (!mv88e6xxx_has_stu(chip)) { 1912 err = -EOPNOTSUPP; 1913 goto err; 1914 } 1915 1916 if (!msti) { 1917 *sid = 0; 1918 return 0; 1919 } 1920 1921 list_for_each_entry(mst, &chip->msts, node) { 1922 if (mst->br == br && mst->msti == msti) { 1923 refcount_inc(&mst->refcnt); 1924 *sid = mst->stu.sid; 1925 return 0; 1926 } 1927 } 1928 1929 err = mv88e6xxx_sid_get(chip, sid); 1930 if (err) 1931 goto err; 1932 1933 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1934 if (!mst) { 1935 err = -ENOMEM; 1936 goto err; 1937 } 1938 1939 INIT_LIST_HEAD(&mst->node); 1940 refcount_set(&mst->refcnt, 1); 1941 mst->br = br; 1942 mst->msti = msti; 1943 mst->stu.valid = true; 1944 mst->stu.sid = *sid; 1945 1946 /* The bridge starts out all ports in the disabled state. But 1947 * a STU state of disabled means to go by the port-global 1948 * state. So we set all user port's initial state to blocking, 1949 * to match the bridge's behavior. 1950 */ 1951 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1952 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1953 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1954 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1955 1956 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1957 if (err) 1958 goto err_free; 1959 1960 list_add_tail(&mst->node, &chip->msts); 1961 return 0; 1962 1963 err_free: 1964 kfree(mst); 1965 err: 1966 return err; 1967 } 1968 1969 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1970 const struct switchdev_mst_state *st) 1971 { 1972 struct dsa_port *dp = dsa_to_port(ds, port); 1973 struct mv88e6xxx_chip *chip = ds->priv; 1974 struct mv88e6xxx_mst *mst; 1975 u8 state; 1976 int err; 1977 1978 if (!mv88e6xxx_has_stu(chip)) 1979 return -EOPNOTSUPP; 1980 1981 switch (st->state) { 1982 case BR_STATE_DISABLED: 1983 case BR_STATE_BLOCKING: 1984 case BR_STATE_LISTENING: 1985 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1986 break; 1987 case BR_STATE_LEARNING: 1988 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1989 break; 1990 case BR_STATE_FORWARDING: 1991 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1992 break; 1993 default: 1994 return -EINVAL; 1995 } 1996 1997 list_for_each_entry(mst, &chip->msts, node) { 1998 if (mst->br == dsa_port_bridge_dev_get(dp) && 1999 mst->msti == st->msti) { 2000 if (mst->stu.state[port] == state) 2001 return 0; 2002 2003 mst->stu.state[port] = state; 2004 mv88e6xxx_reg_lock(chip); 2005 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2006 mv88e6xxx_reg_unlock(chip); 2007 return err; 2008 } 2009 } 2010 2011 return -ENOENT; 2012 } 2013 2014 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2015 u16 vid) 2016 { 2017 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2018 struct mv88e6xxx_chip *chip = ds->priv; 2019 struct mv88e6xxx_vtu_entry vlan; 2020 int err; 2021 2022 /* DSA and CPU ports have to be members of multiple vlans */ 2023 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2024 return 0; 2025 2026 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2027 if (err) 2028 return err; 2029 2030 if (!vlan.valid) 2031 return 0; 2032 2033 dsa_switch_for_each_user_port(other_dp, ds) { 2034 struct net_device *other_br; 2035 2036 if (vlan.member[other_dp->index] == 2037 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2038 continue; 2039 2040 if (dsa_port_bridge_same(dp, other_dp)) 2041 break; /* same bridge, check next VLAN */ 2042 2043 other_br = dsa_port_bridge_dev_get(other_dp); 2044 if (!other_br) 2045 continue; 2046 2047 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2048 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2049 return -EOPNOTSUPP; 2050 } 2051 2052 return 0; 2053 } 2054 2055 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2056 { 2057 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2058 struct net_device *br = dsa_port_bridge_dev_get(dp); 2059 struct mv88e6xxx_port *p = &chip->ports[port]; 2060 u16 pvid = MV88E6XXX_VID_STANDALONE; 2061 bool drop_untagged = false; 2062 int err; 2063 2064 if (br) { 2065 if (br_vlan_enabled(br)) { 2066 pvid = p->bridge_pvid.vid; 2067 drop_untagged = !p->bridge_pvid.valid; 2068 } else { 2069 pvid = MV88E6XXX_VID_BRIDGED; 2070 } 2071 } 2072 2073 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2074 if (err) 2075 return err; 2076 2077 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2078 } 2079 2080 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2081 bool vlan_filtering, 2082 struct netlink_ext_ack *extack) 2083 { 2084 struct mv88e6xxx_chip *chip = ds->priv; 2085 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2086 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2087 int err; 2088 2089 if (!mv88e6xxx_max_vid(chip)) 2090 return -EOPNOTSUPP; 2091 2092 mv88e6xxx_reg_lock(chip); 2093 2094 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2095 if (err) 2096 goto unlock; 2097 2098 err = mv88e6xxx_port_commit_pvid(chip, port); 2099 if (err) 2100 goto unlock; 2101 2102 unlock: 2103 mv88e6xxx_reg_unlock(chip); 2104 2105 return err; 2106 } 2107 2108 static int 2109 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2110 const struct switchdev_obj_port_vlan *vlan) 2111 { 2112 struct mv88e6xxx_chip *chip = ds->priv; 2113 int err; 2114 2115 if (!mv88e6xxx_max_vid(chip)) 2116 return -EOPNOTSUPP; 2117 2118 /* If the requested port doesn't belong to the same bridge as the VLAN 2119 * members, do not support it (yet) and fallback to software VLAN. 2120 */ 2121 mv88e6xxx_reg_lock(chip); 2122 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2123 mv88e6xxx_reg_unlock(chip); 2124 2125 return err; 2126 } 2127 2128 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2129 const unsigned char *addr, u16 vid, 2130 u8 state) 2131 { 2132 struct mv88e6xxx_atu_entry entry; 2133 struct mv88e6xxx_vtu_entry vlan; 2134 u16 fid; 2135 int err; 2136 2137 /* Ports have two private address databases: one for when the port is 2138 * standalone and one for when the port is under a bridge and the 2139 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2140 * address database to remain 100% empty, so we never load an ATU entry 2141 * into a standalone port's database. Therefore, translate the null 2142 * VLAN ID into the port's database used for VLAN-unaware bridging. 2143 */ 2144 if (vid == 0) { 2145 fid = MV88E6XXX_FID_BRIDGED; 2146 } else { 2147 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2148 if (err) 2149 return err; 2150 2151 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2152 if (!vlan.valid) 2153 return -EOPNOTSUPP; 2154 2155 fid = vlan.fid; 2156 } 2157 2158 entry.state = 0; 2159 ether_addr_copy(entry.mac, addr); 2160 eth_addr_dec(entry.mac); 2161 2162 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2163 if (err) 2164 return err; 2165 2166 /* Initialize a fresh ATU entry if it isn't found */ 2167 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2168 memset(&entry, 0, sizeof(entry)); 2169 ether_addr_copy(entry.mac, addr); 2170 } 2171 2172 /* Purge the ATU entry only if no port is using it anymore */ 2173 if (!state) { 2174 entry.portvec &= ~BIT(port); 2175 if (!entry.portvec) 2176 entry.state = 0; 2177 } else { 2178 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2179 entry.portvec = BIT(port); 2180 else 2181 entry.portvec |= BIT(port); 2182 2183 entry.state = state; 2184 } 2185 2186 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2187 } 2188 2189 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2190 const struct mv88e6xxx_policy *policy) 2191 { 2192 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2193 enum mv88e6xxx_policy_action action = policy->action; 2194 const u8 *addr = policy->addr; 2195 u16 vid = policy->vid; 2196 u8 state; 2197 int err; 2198 int id; 2199 2200 if (!chip->info->ops->port_set_policy) 2201 return -EOPNOTSUPP; 2202 2203 switch (mapping) { 2204 case MV88E6XXX_POLICY_MAPPING_DA: 2205 case MV88E6XXX_POLICY_MAPPING_SA: 2206 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2207 state = 0; /* Dissociate the port and address */ 2208 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2209 is_multicast_ether_addr(addr)) 2210 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2211 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2212 is_unicast_ether_addr(addr)) 2213 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2214 else 2215 return -EOPNOTSUPP; 2216 2217 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2218 state); 2219 if (err) 2220 return err; 2221 break; 2222 default: 2223 return -EOPNOTSUPP; 2224 } 2225 2226 /* Skip the port's policy clearing if the mapping is still in use */ 2227 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2228 idr_for_each_entry(&chip->policies, policy, id) 2229 if (policy->port == port && 2230 policy->mapping == mapping && 2231 policy->action != action) 2232 return 0; 2233 2234 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2235 } 2236 2237 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2238 struct ethtool_rx_flow_spec *fs) 2239 { 2240 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2241 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2242 enum mv88e6xxx_policy_mapping mapping; 2243 enum mv88e6xxx_policy_action action; 2244 struct mv88e6xxx_policy *policy; 2245 u16 vid = 0; 2246 u8 *addr; 2247 int err; 2248 int id; 2249 2250 if (fs->location != RX_CLS_LOC_ANY) 2251 return -EINVAL; 2252 2253 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2254 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2255 else 2256 return -EOPNOTSUPP; 2257 2258 switch (fs->flow_type & ~FLOW_EXT) { 2259 case ETHER_FLOW: 2260 if (!is_zero_ether_addr(mac_mask->h_dest) && 2261 is_zero_ether_addr(mac_mask->h_source)) { 2262 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2263 addr = mac_entry->h_dest; 2264 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2265 !is_zero_ether_addr(mac_mask->h_source)) { 2266 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2267 addr = mac_entry->h_source; 2268 } else { 2269 /* Cannot support DA and SA mapping in the same rule */ 2270 return -EOPNOTSUPP; 2271 } 2272 break; 2273 default: 2274 return -EOPNOTSUPP; 2275 } 2276 2277 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2278 if (fs->m_ext.vlan_tci != htons(0xffff)) 2279 return -EOPNOTSUPP; 2280 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2281 } 2282 2283 idr_for_each_entry(&chip->policies, policy, id) { 2284 if (policy->port == port && policy->mapping == mapping && 2285 policy->action == action && policy->vid == vid && 2286 ether_addr_equal(policy->addr, addr)) 2287 return -EEXIST; 2288 } 2289 2290 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2291 if (!policy) 2292 return -ENOMEM; 2293 2294 fs->location = 0; 2295 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2296 GFP_KERNEL); 2297 if (err) { 2298 devm_kfree(chip->dev, policy); 2299 return err; 2300 } 2301 2302 memcpy(&policy->fs, fs, sizeof(*fs)); 2303 ether_addr_copy(policy->addr, addr); 2304 policy->mapping = mapping; 2305 policy->action = action; 2306 policy->port = port; 2307 policy->vid = vid; 2308 2309 err = mv88e6xxx_policy_apply(chip, port, policy); 2310 if (err) { 2311 idr_remove(&chip->policies, fs->location); 2312 devm_kfree(chip->dev, policy); 2313 return err; 2314 } 2315 2316 return 0; 2317 } 2318 2319 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2320 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2321 { 2322 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2323 struct mv88e6xxx_chip *chip = ds->priv; 2324 struct mv88e6xxx_policy *policy; 2325 int err; 2326 int id; 2327 2328 mv88e6xxx_reg_lock(chip); 2329 2330 switch (rxnfc->cmd) { 2331 case ETHTOOL_GRXCLSRLCNT: 2332 rxnfc->data = 0; 2333 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2334 rxnfc->rule_cnt = 0; 2335 idr_for_each_entry(&chip->policies, policy, id) 2336 if (policy->port == port) 2337 rxnfc->rule_cnt++; 2338 err = 0; 2339 break; 2340 case ETHTOOL_GRXCLSRULE: 2341 err = -ENOENT; 2342 policy = idr_find(&chip->policies, fs->location); 2343 if (policy) { 2344 memcpy(fs, &policy->fs, sizeof(*fs)); 2345 err = 0; 2346 } 2347 break; 2348 case ETHTOOL_GRXCLSRLALL: 2349 rxnfc->data = 0; 2350 rxnfc->rule_cnt = 0; 2351 idr_for_each_entry(&chip->policies, policy, id) 2352 if (policy->port == port) 2353 rule_locs[rxnfc->rule_cnt++] = id; 2354 err = 0; 2355 break; 2356 default: 2357 err = -EOPNOTSUPP; 2358 break; 2359 } 2360 2361 mv88e6xxx_reg_unlock(chip); 2362 2363 return err; 2364 } 2365 2366 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2367 struct ethtool_rxnfc *rxnfc) 2368 { 2369 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2370 struct mv88e6xxx_chip *chip = ds->priv; 2371 struct mv88e6xxx_policy *policy; 2372 int err; 2373 2374 mv88e6xxx_reg_lock(chip); 2375 2376 switch (rxnfc->cmd) { 2377 case ETHTOOL_SRXCLSRLINS: 2378 err = mv88e6xxx_policy_insert(chip, port, fs); 2379 break; 2380 case ETHTOOL_SRXCLSRLDEL: 2381 err = -ENOENT; 2382 policy = idr_remove(&chip->policies, fs->location); 2383 if (policy) { 2384 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2385 err = mv88e6xxx_policy_apply(chip, port, policy); 2386 devm_kfree(chip->dev, policy); 2387 } 2388 break; 2389 default: 2390 err = -EOPNOTSUPP; 2391 break; 2392 } 2393 2394 mv88e6xxx_reg_unlock(chip); 2395 2396 return err; 2397 } 2398 2399 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2400 u16 vid) 2401 { 2402 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2403 u8 broadcast[ETH_ALEN]; 2404 2405 eth_broadcast_addr(broadcast); 2406 2407 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2408 } 2409 2410 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2411 { 2412 int port; 2413 int err; 2414 2415 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2416 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2417 struct net_device *brport; 2418 2419 if (dsa_is_unused_port(chip->ds, port)) 2420 continue; 2421 2422 brport = dsa_port_to_bridge_port(dp); 2423 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2424 /* Skip bridged user ports where broadcast 2425 * flooding is disabled. 2426 */ 2427 continue; 2428 2429 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2430 if (err) 2431 return err; 2432 } 2433 2434 return 0; 2435 } 2436 2437 struct mv88e6xxx_port_broadcast_sync_ctx { 2438 int port; 2439 bool flood; 2440 }; 2441 2442 static int 2443 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2444 const struct mv88e6xxx_vtu_entry *vlan, 2445 void *_ctx) 2446 { 2447 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2448 u8 broadcast[ETH_ALEN]; 2449 u8 state; 2450 2451 if (ctx->flood) 2452 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2453 else 2454 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2455 2456 eth_broadcast_addr(broadcast); 2457 2458 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2459 vlan->vid, state); 2460 } 2461 2462 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2463 bool flood) 2464 { 2465 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2466 .port = port, 2467 .flood = flood, 2468 }; 2469 struct mv88e6xxx_vtu_entry vid0 = { 2470 .vid = 0, 2471 }; 2472 int err; 2473 2474 /* Update the port's private database... */ 2475 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2476 if (err) 2477 return err; 2478 2479 /* ...and the database for all VLANs. */ 2480 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2481 &ctx); 2482 } 2483 2484 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2485 u16 vid, u8 member, bool warn) 2486 { 2487 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2488 struct mv88e6xxx_vtu_entry vlan; 2489 int i, err; 2490 2491 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2492 if (err) 2493 return err; 2494 2495 if (!vlan.valid) { 2496 memset(&vlan, 0, sizeof(vlan)); 2497 2498 if (vid == MV88E6XXX_VID_STANDALONE) 2499 vlan.policy = true; 2500 2501 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2502 if (err) 2503 return err; 2504 2505 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2506 if (i == port) 2507 vlan.member[i] = member; 2508 else 2509 vlan.member[i] = non_member; 2510 2511 vlan.vid = vid; 2512 vlan.valid = true; 2513 2514 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2515 if (err) 2516 return err; 2517 2518 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2519 if (err) 2520 return err; 2521 } else if (vlan.member[port] != member) { 2522 vlan.member[port] = member; 2523 2524 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2525 if (err) 2526 return err; 2527 } else if (warn) { 2528 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2529 port, vid); 2530 } 2531 2532 return 0; 2533 } 2534 2535 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2536 const struct switchdev_obj_port_vlan *vlan, 2537 struct netlink_ext_ack *extack) 2538 { 2539 struct mv88e6xxx_chip *chip = ds->priv; 2540 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2541 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2542 struct mv88e6xxx_port *p = &chip->ports[port]; 2543 bool warn; 2544 u8 member; 2545 int err; 2546 2547 if (!vlan->vid) 2548 return 0; 2549 2550 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2551 if (err) 2552 return err; 2553 2554 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2555 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2556 else if (untagged) 2557 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2558 else 2559 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2560 2561 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2562 * and then the CPU port. Do not warn for duplicates for the CPU port. 2563 */ 2564 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2565 2566 mv88e6xxx_reg_lock(chip); 2567 2568 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2569 if (err) { 2570 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2571 vlan->vid, untagged ? 'u' : 't'); 2572 goto out; 2573 } 2574 2575 if (pvid) { 2576 p->bridge_pvid.vid = vlan->vid; 2577 p->bridge_pvid.valid = true; 2578 2579 err = mv88e6xxx_port_commit_pvid(chip, port); 2580 if (err) 2581 goto out; 2582 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2583 /* The old pvid was reinstalled as a non-pvid VLAN */ 2584 p->bridge_pvid.valid = false; 2585 2586 err = mv88e6xxx_port_commit_pvid(chip, port); 2587 if (err) 2588 goto out; 2589 } 2590 2591 out: 2592 mv88e6xxx_reg_unlock(chip); 2593 2594 return err; 2595 } 2596 2597 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2598 int port, u16 vid) 2599 { 2600 struct mv88e6xxx_vtu_entry vlan; 2601 int i, err; 2602 2603 if (!vid) 2604 return 0; 2605 2606 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2607 if (err) 2608 return err; 2609 2610 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2611 * tell switchdev that this VLAN is likely handled in software. 2612 */ 2613 if (!vlan.valid || 2614 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2615 return -EOPNOTSUPP; 2616 2617 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2618 2619 /* keep the VLAN unless all ports are excluded */ 2620 vlan.valid = false; 2621 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2622 if (vlan.member[i] != 2623 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2624 vlan.valid = true; 2625 break; 2626 } 2627 } 2628 2629 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2630 if (err) 2631 return err; 2632 2633 if (!vlan.valid) { 2634 err = mv88e6xxx_mst_put(chip, vlan.sid); 2635 if (err) 2636 return err; 2637 } 2638 2639 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2640 } 2641 2642 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2643 const struct switchdev_obj_port_vlan *vlan) 2644 { 2645 struct mv88e6xxx_chip *chip = ds->priv; 2646 struct mv88e6xxx_port *p = &chip->ports[port]; 2647 int err = 0; 2648 u16 pvid; 2649 2650 if (!mv88e6xxx_max_vid(chip)) 2651 return -EOPNOTSUPP; 2652 2653 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2654 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2655 * switchdev workqueue to ensure that all FDB entries are deleted 2656 * before we remove the VLAN. 2657 */ 2658 dsa_flush_workqueue(); 2659 2660 mv88e6xxx_reg_lock(chip); 2661 2662 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2663 if (err) 2664 goto unlock; 2665 2666 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2667 if (err) 2668 goto unlock; 2669 2670 if (vlan->vid == pvid) { 2671 p->bridge_pvid.valid = false; 2672 2673 err = mv88e6xxx_port_commit_pvid(chip, port); 2674 if (err) 2675 goto unlock; 2676 } 2677 2678 unlock: 2679 mv88e6xxx_reg_unlock(chip); 2680 2681 return err; 2682 } 2683 2684 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2685 { 2686 struct mv88e6xxx_chip *chip = ds->priv; 2687 struct mv88e6xxx_vtu_entry vlan; 2688 int err; 2689 2690 mv88e6xxx_reg_lock(chip); 2691 2692 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2693 if (err) 2694 goto unlock; 2695 2696 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2697 2698 unlock: 2699 mv88e6xxx_reg_unlock(chip); 2700 2701 return err; 2702 } 2703 2704 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2705 struct dsa_bridge bridge, 2706 const struct switchdev_vlan_msti *msti) 2707 { 2708 struct mv88e6xxx_chip *chip = ds->priv; 2709 struct mv88e6xxx_vtu_entry vlan; 2710 u8 old_sid, new_sid; 2711 int err; 2712 2713 if (!mv88e6xxx_has_stu(chip)) 2714 return -EOPNOTSUPP; 2715 2716 mv88e6xxx_reg_lock(chip); 2717 2718 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2719 if (err) 2720 goto unlock; 2721 2722 if (!vlan.valid) { 2723 err = -EINVAL; 2724 goto unlock; 2725 } 2726 2727 old_sid = vlan.sid; 2728 2729 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2730 if (err) 2731 goto unlock; 2732 2733 if (new_sid != old_sid) { 2734 vlan.sid = new_sid; 2735 2736 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2737 if (err) { 2738 mv88e6xxx_mst_put(chip, new_sid); 2739 goto unlock; 2740 } 2741 } 2742 2743 err = mv88e6xxx_mst_put(chip, old_sid); 2744 2745 unlock: 2746 mv88e6xxx_reg_unlock(chip); 2747 return err; 2748 } 2749 2750 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2751 const unsigned char *addr, u16 vid, 2752 struct dsa_db db) 2753 { 2754 struct mv88e6xxx_chip *chip = ds->priv; 2755 int err; 2756 2757 mv88e6xxx_reg_lock(chip); 2758 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2759 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2760 mv88e6xxx_reg_unlock(chip); 2761 2762 return err; 2763 } 2764 2765 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2766 const unsigned char *addr, u16 vid, 2767 struct dsa_db db) 2768 { 2769 struct mv88e6xxx_chip *chip = ds->priv; 2770 int err; 2771 2772 mv88e6xxx_reg_lock(chip); 2773 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2774 mv88e6xxx_reg_unlock(chip); 2775 2776 return err; 2777 } 2778 2779 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2780 u16 fid, u16 vid, int port, 2781 dsa_fdb_dump_cb_t *cb, void *data) 2782 { 2783 struct mv88e6xxx_atu_entry addr; 2784 bool is_static; 2785 int err; 2786 2787 addr.state = 0; 2788 eth_broadcast_addr(addr.mac); 2789 2790 do { 2791 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2792 if (err) 2793 return err; 2794 2795 if (!addr.state) 2796 break; 2797 2798 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2799 continue; 2800 2801 if (!is_unicast_ether_addr(addr.mac)) 2802 continue; 2803 2804 is_static = (addr.state == 2805 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2806 err = cb(addr.mac, vid, is_static, data); 2807 if (err) 2808 return err; 2809 } while (!is_broadcast_ether_addr(addr.mac)); 2810 2811 return err; 2812 } 2813 2814 struct mv88e6xxx_port_db_dump_vlan_ctx { 2815 int port; 2816 dsa_fdb_dump_cb_t *cb; 2817 void *data; 2818 }; 2819 2820 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2821 const struct mv88e6xxx_vtu_entry *entry, 2822 void *_data) 2823 { 2824 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2825 2826 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2827 ctx->port, ctx->cb, ctx->data); 2828 } 2829 2830 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2831 dsa_fdb_dump_cb_t *cb, void *data) 2832 { 2833 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2834 .port = port, 2835 .cb = cb, 2836 .data = data, 2837 }; 2838 u16 fid; 2839 int err; 2840 2841 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2842 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2843 if (err) 2844 return err; 2845 2846 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2847 if (err) 2848 return err; 2849 2850 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2851 } 2852 2853 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2854 dsa_fdb_dump_cb_t *cb, void *data) 2855 { 2856 struct mv88e6xxx_chip *chip = ds->priv; 2857 int err; 2858 2859 mv88e6xxx_reg_lock(chip); 2860 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2861 mv88e6xxx_reg_unlock(chip); 2862 2863 return err; 2864 } 2865 2866 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2867 struct dsa_bridge bridge) 2868 { 2869 struct dsa_switch *ds = chip->ds; 2870 struct dsa_switch_tree *dst = ds->dst; 2871 struct dsa_port *dp; 2872 int err; 2873 2874 list_for_each_entry(dp, &dst->ports, list) { 2875 if (dsa_port_offloads_bridge(dp, &bridge)) { 2876 if (dp->ds == ds) { 2877 /* This is a local bridge group member, 2878 * remap its Port VLAN Map. 2879 */ 2880 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2881 if (err) 2882 return err; 2883 } else { 2884 /* This is an external bridge group member, 2885 * remap its cross-chip Port VLAN Table entry. 2886 */ 2887 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2888 dp->index); 2889 if (err) 2890 return err; 2891 } 2892 } 2893 } 2894 2895 return 0; 2896 } 2897 2898 /* Treat the software bridge as a virtual single-port switch behind the 2899 * CPU and map in the PVT. First dst->last_switch elements are taken by 2900 * physical switches, so start from beyond that range. 2901 */ 2902 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2903 unsigned int bridge_num) 2904 { 2905 u8 dev = bridge_num + ds->dst->last_switch; 2906 struct mv88e6xxx_chip *chip = ds->priv; 2907 2908 return mv88e6xxx_pvt_map(chip, dev, 0); 2909 } 2910 2911 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2912 struct dsa_bridge bridge, 2913 bool *tx_fwd_offload, 2914 struct netlink_ext_ack *extack) 2915 { 2916 struct mv88e6xxx_chip *chip = ds->priv; 2917 int err; 2918 2919 mv88e6xxx_reg_lock(chip); 2920 2921 err = mv88e6xxx_bridge_map(chip, bridge); 2922 if (err) 2923 goto unlock; 2924 2925 err = mv88e6xxx_port_set_map_da(chip, port, true); 2926 if (err) 2927 goto unlock; 2928 2929 err = mv88e6xxx_port_commit_pvid(chip, port); 2930 if (err) 2931 goto unlock; 2932 2933 if (mv88e6xxx_has_pvt(chip)) { 2934 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2935 if (err) 2936 goto unlock; 2937 2938 *tx_fwd_offload = true; 2939 } 2940 2941 unlock: 2942 mv88e6xxx_reg_unlock(chip); 2943 2944 return err; 2945 } 2946 2947 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2948 struct dsa_bridge bridge) 2949 { 2950 struct mv88e6xxx_chip *chip = ds->priv; 2951 int err; 2952 2953 mv88e6xxx_reg_lock(chip); 2954 2955 if (bridge.tx_fwd_offload && 2956 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2957 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2958 2959 if (mv88e6xxx_bridge_map(chip, bridge) || 2960 mv88e6xxx_port_vlan_map(chip, port)) 2961 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2962 2963 err = mv88e6xxx_port_set_map_da(chip, port, false); 2964 if (err) 2965 dev_err(ds->dev, 2966 "port %d failed to restore map-DA: %pe\n", 2967 port, ERR_PTR(err)); 2968 2969 err = mv88e6xxx_port_commit_pvid(chip, port); 2970 if (err) 2971 dev_err(ds->dev, 2972 "port %d failed to restore standalone pvid: %pe\n", 2973 port, ERR_PTR(err)); 2974 2975 mv88e6xxx_reg_unlock(chip); 2976 } 2977 2978 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2979 int tree_index, int sw_index, 2980 int port, struct dsa_bridge bridge, 2981 struct netlink_ext_ack *extack) 2982 { 2983 struct mv88e6xxx_chip *chip = ds->priv; 2984 int err; 2985 2986 if (tree_index != ds->dst->index) 2987 return 0; 2988 2989 mv88e6xxx_reg_lock(chip); 2990 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2991 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2992 mv88e6xxx_reg_unlock(chip); 2993 2994 return err; 2995 } 2996 2997 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2998 int tree_index, int sw_index, 2999 int port, struct dsa_bridge bridge) 3000 { 3001 struct mv88e6xxx_chip *chip = ds->priv; 3002 3003 if (tree_index != ds->dst->index) 3004 return; 3005 3006 mv88e6xxx_reg_lock(chip); 3007 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3008 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3009 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3010 mv88e6xxx_reg_unlock(chip); 3011 } 3012 3013 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3014 { 3015 if (chip->info->ops->reset) 3016 return chip->info->ops->reset(chip); 3017 3018 return 0; 3019 } 3020 3021 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3022 { 3023 struct gpio_desc *gpiod = chip->reset; 3024 3025 /* If there is a GPIO connected to the reset pin, toggle it */ 3026 if (gpiod) { 3027 /* If the switch has just been reset and not yet completed 3028 * loading EEPROM, the reset may interrupt the I2C transaction 3029 * mid-byte, causing the first EEPROM read after the reset 3030 * from the wrong location resulting in the switch booting 3031 * to wrong mode and inoperable. 3032 */ 3033 if (chip->info->ops->get_eeprom) 3034 mv88e6xxx_g2_eeprom_wait(chip); 3035 3036 gpiod_set_value_cansleep(gpiod, 1); 3037 usleep_range(10000, 20000); 3038 gpiod_set_value_cansleep(gpiod, 0); 3039 usleep_range(10000, 20000); 3040 3041 if (chip->info->ops->get_eeprom) 3042 mv88e6xxx_g2_eeprom_wait(chip); 3043 } 3044 } 3045 3046 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3047 { 3048 int i, err; 3049 3050 /* Set all ports to the Disabled state */ 3051 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3052 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3053 if (err) 3054 return err; 3055 } 3056 3057 /* Wait for transmit queues to drain, 3058 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3059 */ 3060 usleep_range(2000, 4000); 3061 3062 return 0; 3063 } 3064 3065 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3066 { 3067 int err; 3068 3069 err = mv88e6xxx_disable_ports(chip); 3070 if (err) 3071 return err; 3072 3073 mv88e6xxx_hardware_reset(chip); 3074 3075 return mv88e6xxx_software_reset(chip); 3076 } 3077 3078 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3079 enum mv88e6xxx_frame_mode frame, 3080 enum mv88e6xxx_egress_mode egress, u16 etype) 3081 { 3082 int err; 3083 3084 if (!chip->info->ops->port_set_frame_mode) 3085 return -EOPNOTSUPP; 3086 3087 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3088 if (err) 3089 return err; 3090 3091 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3092 if (err) 3093 return err; 3094 3095 if (chip->info->ops->port_set_ether_type) 3096 return chip->info->ops->port_set_ether_type(chip, port, etype); 3097 3098 return 0; 3099 } 3100 3101 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3102 { 3103 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3104 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3105 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3106 } 3107 3108 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3109 { 3110 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3111 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3112 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3113 } 3114 3115 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3116 { 3117 return mv88e6xxx_set_port_mode(chip, port, 3118 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3119 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3120 ETH_P_EDSA); 3121 } 3122 3123 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3124 { 3125 if (dsa_is_dsa_port(chip->ds, port)) 3126 return mv88e6xxx_set_port_mode_dsa(chip, port); 3127 3128 if (dsa_is_user_port(chip->ds, port)) 3129 return mv88e6xxx_set_port_mode_normal(chip, port); 3130 3131 /* Setup CPU port mode depending on its supported tag format */ 3132 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3133 return mv88e6xxx_set_port_mode_dsa(chip, port); 3134 3135 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3136 return mv88e6xxx_set_port_mode_edsa(chip, port); 3137 3138 return -EINVAL; 3139 } 3140 3141 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3142 { 3143 bool message = dsa_is_dsa_port(chip->ds, port); 3144 3145 return mv88e6xxx_port_set_message_port(chip, port, message); 3146 } 3147 3148 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3149 { 3150 int err; 3151 3152 if (chip->info->ops->port_set_ucast_flood) { 3153 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3154 if (err) 3155 return err; 3156 } 3157 if (chip->info->ops->port_set_mcast_flood) { 3158 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3159 if (err) 3160 return err; 3161 } 3162 3163 return 0; 3164 } 3165 3166 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3167 enum mv88e6xxx_egress_direction direction, 3168 int port) 3169 { 3170 int err; 3171 3172 if (!chip->info->ops->set_egress_port) 3173 return -EOPNOTSUPP; 3174 3175 err = chip->info->ops->set_egress_port(chip, direction, port); 3176 if (err) 3177 return err; 3178 3179 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3180 chip->ingress_dest_port = port; 3181 else 3182 chip->egress_dest_port = port; 3183 3184 return 0; 3185 } 3186 3187 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3188 { 3189 struct dsa_switch *ds = chip->ds; 3190 int upstream_port; 3191 int err; 3192 3193 upstream_port = dsa_upstream_port(ds, port); 3194 if (chip->info->ops->port_set_upstream_port) { 3195 err = chip->info->ops->port_set_upstream_port(chip, port, 3196 upstream_port); 3197 if (err) 3198 return err; 3199 } 3200 3201 if (port == upstream_port) { 3202 if (chip->info->ops->set_cpu_port) { 3203 err = chip->info->ops->set_cpu_port(chip, 3204 upstream_port); 3205 if (err) 3206 return err; 3207 } 3208 3209 err = mv88e6xxx_set_egress_port(chip, 3210 MV88E6XXX_EGRESS_DIR_INGRESS, 3211 upstream_port); 3212 if (err && err != -EOPNOTSUPP) 3213 return err; 3214 3215 err = mv88e6xxx_set_egress_port(chip, 3216 MV88E6XXX_EGRESS_DIR_EGRESS, 3217 upstream_port); 3218 if (err && err != -EOPNOTSUPP) 3219 return err; 3220 } 3221 3222 return 0; 3223 } 3224 3225 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3226 { 3227 struct device_node *phy_handle = NULL; 3228 struct dsa_switch *ds = chip->ds; 3229 struct dsa_port *dp; 3230 int tx_amp; 3231 int err; 3232 u16 reg; 3233 3234 chip->ports[port].chip = chip; 3235 chip->ports[port].port = port; 3236 3237 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3238 SPEED_UNFORCED, DUPLEX_UNFORCED, 3239 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3240 if (err) 3241 return err; 3242 3243 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3244 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3245 * tunneling, determine priority by looking at 802.1p and IP 3246 * priority fields (IP prio has precedence), and set STP state 3247 * to Forwarding. 3248 * 3249 * If this is the CPU link, use DSA or EDSA tagging depending 3250 * on which tagging mode was configured. 3251 * 3252 * If this is a link to another switch, use DSA tagging mode. 3253 * 3254 * If this is the upstream port for this switch, enable 3255 * forwarding of unknown unicasts and multicasts. 3256 */ 3257 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3258 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3259 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3260 * by a USER port to the CPU port to allow snooping. 3261 */ 3262 if (dsa_is_user_port(ds, port)) 3263 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3264 3265 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3266 if (err) 3267 return err; 3268 3269 err = mv88e6xxx_setup_port_mode(chip, port); 3270 if (err) 3271 return err; 3272 3273 err = mv88e6xxx_setup_egress_floods(chip, port); 3274 if (err) 3275 return err; 3276 3277 /* Port Control 2: don't force a good FCS, set the MTU size to 3278 * 10222 bytes, disable 802.1q tags checking, don't discard 3279 * tagged or untagged frames on this port, skip destination 3280 * address lookup on user ports, disable ARP mirroring and don't 3281 * send a copy of all transmitted/received frames on this port 3282 * to the CPU. 3283 */ 3284 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3285 if (err) 3286 return err; 3287 3288 err = mv88e6xxx_setup_upstream_port(chip, port); 3289 if (err) 3290 return err; 3291 3292 /* On chips that support it, set all downstream DSA ports' 3293 * VLAN policy to TRAP. In combination with loading 3294 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3295 * provides a better isolation barrier between standalone 3296 * ports, as the ATU is bypassed on any intermediate switches 3297 * between the incoming port and the CPU. 3298 */ 3299 if (dsa_is_downstream_port(ds, port) && 3300 chip->info->ops->port_set_policy) { 3301 err = chip->info->ops->port_set_policy(chip, port, 3302 MV88E6XXX_POLICY_MAPPING_VTU, 3303 MV88E6XXX_POLICY_ACTION_TRAP); 3304 if (err) 3305 return err; 3306 } 3307 3308 /* User ports start out in standalone mode and 802.1Q is 3309 * therefore disabled. On DSA ports, all valid VIDs are always 3310 * loaded in the VTU - therefore, enable 802.1Q in order to take 3311 * advantage of VLAN policy on chips that supports it. 3312 */ 3313 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3314 dsa_is_user_port(ds, port) ? 3315 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3316 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3317 if (err) 3318 return err; 3319 3320 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3321 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3322 * the first free FID. This will be used as the private PVID for 3323 * unbridged ports. Shared (DSA and CPU) ports must also be 3324 * members of this VID, in order to trap all frames assigned to 3325 * it to the CPU. 3326 */ 3327 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3328 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3329 false); 3330 if (err) 3331 return err; 3332 3333 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3334 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3335 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3336 * as the private PVID on ports under a VLAN-unaware bridge. 3337 * Shared (DSA and CPU) ports must also be members of it, to translate 3338 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3339 * relying on their port default FID. 3340 */ 3341 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3342 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3343 false); 3344 if (err) 3345 return err; 3346 3347 if (chip->info->ops->port_set_jumbo_size) { 3348 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3349 if (err) 3350 return err; 3351 } 3352 3353 /* Port Association Vector: disable automatic address learning 3354 * on all user ports since they start out in standalone 3355 * mode. When joining a bridge, learning will be configured to 3356 * match the bridge port settings. Enable learning on all 3357 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3358 * learning process. 3359 * 3360 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3361 * and RefreshLocked. I.e. setup standard automatic learning. 3362 */ 3363 if (dsa_is_user_port(ds, port)) 3364 reg = 0; 3365 else 3366 reg = 1 << port; 3367 3368 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3369 reg); 3370 if (err) 3371 return err; 3372 3373 /* Egress rate control 2: disable egress rate control. */ 3374 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3375 0x0000); 3376 if (err) 3377 return err; 3378 3379 if (chip->info->ops->port_pause_limit) { 3380 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3381 if (err) 3382 return err; 3383 } 3384 3385 if (chip->info->ops->port_disable_learn_limit) { 3386 err = chip->info->ops->port_disable_learn_limit(chip, port); 3387 if (err) 3388 return err; 3389 } 3390 3391 if (chip->info->ops->port_disable_pri_override) { 3392 err = chip->info->ops->port_disable_pri_override(chip, port); 3393 if (err) 3394 return err; 3395 } 3396 3397 if (chip->info->ops->port_tag_remap) { 3398 err = chip->info->ops->port_tag_remap(chip, port); 3399 if (err) 3400 return err; 3401 } 3402 3403 if (chip->info->ops->port_egress_rate_limiting) { 3404 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3405 if (err) 3406 return err; 3407 } 3408 3409 if (chip->info->ops->port_setup_message_port) { 3410 err = chip->info->ops->port_setup_message_port(chip, port); 3411 if (err) 3412 return err; 3413 } 3414 3415 if (chip->info->ops->serdes_set_tx_amplitude) { 3416 dp = dsa_to_port(ds, port); 3417 if (dp) 3418 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3419 3420 if (phy_handle && !of_property_read_u32(phy_handle, 3421 "tx-p2p-microvolt", 3422 &tx_amp)) 3423 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3424 port, tx_amp); 3425 if (phy_handle) { 3426 of_node_put(phy_handle); 3427 if (err) 3428 return err; 3429 } 3430 } 3431 3432 /* Port based VLAN map: give each port the same default address 3433 * database, and allow bidirectional communication between the 3434 * CPU and DSA port(s), and the other ports. 3435 */ 3436 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3437 if (err) 3438 return err; 3439 3440 err = mv88e6xxx_port_vlan_map(chip, port); 3441 if (err) 3442 return err; 3443 3444 /* Default VLAN ID and priority: don't set a default VLAN 3445 * ID, and set the default packet priority to zero. 3446 */ 3447 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3448 } 3449 3450 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3451 { 3452 struct mv88e6xxx_chip *chip = ds->priv; 3453 3454 if (chip->info->ops->port_set_jumbo_size) 3455 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3456 else if (chip->info->ops->set_max_frame_size) 3457 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3458 return ETH_DATA_LEN; 3459 } 3460 3461 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3462 { 3463 struct mv88e6xxx_chip *chip = ds->priv; 3464 int ret = 0; 3465 3466 /* For families where we don't know how to alter the MTU, 3467 * just accept any value up to ETH_DATA_LEN 3468 */ 3469 if (!chip->info->ops->port_set_jumbo_size && 3470 !chip->info->ops->set_max_frame_size) { 3471 if (new_mtu > ETH_DATA_LEN) 3472 return -EINVAL; 3473 3474 return 0; 3475 } 3476 3477 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3478 new_mtu += EDSA_HLEN; 3479 3480 mv88e6xxx_reg_lock(chip); 3481 if (chip->info->ops->port_set_jumbo_size) 3482 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3483 else if (chip->info->ops->set_max_frame_size) 3484 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3485 mv88e6xxx_reg_unlock(chip); 3486 3487 return ret; 3488 } 3489 3490 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3491 unsigned int ageing_time) 3492 { 3493 struct mv88e6xxx_chip *chip = ds->priv; 3494 int err; 3495 3496 mv88e6xxx_reg_lock(chip); 3497 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3498 mv88e6xxx_reg_unlock(chip); 3499 3500 return err; 3501 } 3502 3503 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3504 { 3505 int err; 3506 3507 /* Initialize the statistics unit */ 3508 if (chip->info->ops->stats_set_histogram) { 3509 err = chip->info->ops->stats_set_histogram(chip); 3510 if (err) 3511 return err; 3512 } 3513 3514 return mv88e6xxx_g1_stats_clear(chip); 3515 } 3516 3517 /* Check if the errata has already been applied. */ 3518 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3519 { 3520 int port; 3521 int err; 3522 u16 val; 3523 3524 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3525 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3526 if (err) { 3527 dev_err(chip->dev, 3528 "Error reading hidden register: %d\n", err); 3529 return false; 3530 } 3531 if (val != 0x01c0) 3532 return false; 3533 } 3534 3535 return true; 3536 } 3537 3538 /* The 6390 copper ports have an errata which require poking magic 3539 * values into undocumented hidden registers and then performing a 3540 * software reset. 3541 */ 3542 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3543 { 3544 int port; 3545 int err; 3546 3547 if (mv88e6390_setup_errata_applied(chip)) 3548 return 0; 3549 3550 /* Set the ports into blocking mode */ 3551 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3552 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3553 if (err) 3554 return err; 3555 } 3556 3557 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3558 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3559 if (err) 3560 return err; 3561 } 3562 3563 return mv88e6xxx_software_reset(chip); 3564 } 3565 3566 /* prod_id for switch families which do not have a PHY model number */ 3567 static const u16 family_prod_id_table[] = { 3568 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3569 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3570 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3571 }; 3572 3573 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3574 { 3575 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3576 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3577 u16 prod_id; 3578 u16 val; 3579 int err; 3580 3581 if (!chip->info->ops->phy_read) 3582 return -EOPNOTSUPP; 3583 3584 mv88e6xxx_reg_lock(chip); 3585 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3586 mv88e6xxx_reg_unlock(chip); 3587 3588 /* Some internal PHYs don't have a model number. */ 3589 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3590 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3591 prod_id = family_prod_id_table[chip->info->family]; 3592 if (prod_id) 3593 val |= prod_id >> 4; 3594 } 3595 3596 return err ? err : val; 3597 } 3598 3599 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3600 int reg) 3601 { 3602 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3603 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3604 u16 val; 3605 int err; 3606 3607 if (!chip->info->ops->phy_read_c45) 3608 return 0xffff; 3609 3610 mv88e6xxx_reg_lock(chip); 3611 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3612 mv88e6xxx_reg_unlock(chip); 3613 3614 return err ? err : val; 3615 } 3616 3617 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3618 { 3619 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3620 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3621 int err; 3622 3623 if (!chip->info->ops->phy_write) 3624 return -EOPNOTSUPP; 3625 3626 mv88e6xxx_reg_lock(chip); 3627 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3628 mv88e6xxx_reg_unlock(chip); 3629 3630 return err; 3631 } 3632 3633 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3634 int reg, u16 val) 3635 { 3636 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3637 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3638 int err; 3639 3640 if (!chip->info->ops->phy_write_c45) 3641 return -EOPNOTSUPP; 3642 3643 mv88e6xxx_reg_lock(chip); 3644 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3645 mv88e6xxx_reg_unlock(chip); 3646 3647 return err; 3648 } 3649 3650 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3651 struct device_node *np, 3652 bool external) 3653 { 3654 static int index; 3655 struct mv88e6xxx_mdio_bus *mdio_bus; 3656 struct mii_bus *bus; 3657 int err; 3658 3659 if (external) { 3660 mv88e6xxx_reg_lock(chip); 3661 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3662 mv88e6xxx_reg_unlock(chip); 3663 3664 if (err) 3665 return err; 3666 } 3667 3668 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3669 if (!bus) 3670 return -ENOMEM; 3671 3672 mdio_bus = bus->priv; 3673 mdio_bus->bus = bus; 3674 mdio_bus->chip = chip; 3675 INIT_LIST_HEAD(&mdio_bus->list); 3676 mdio_bus->external = external; 3677 3678 if (np) { 3679 bus->name = np->full_name; 3680 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3681 } else { 3682 bus->name = "mv88e6xxx SMI"; 3683 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3684 } 3685 3686 bus->read = mv88e6xxx_mdio_read; 3687 bus->write = mv88e6xxx_mdio_write; 3688 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3689 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3690 bus->parent = chip->dev; 3691 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3692 mv88e6xxx_num_ports(chip) - 1, 3693 chip->info->phy_base_addr); 3694 3695 if (!external) { 3696 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3697 if (err) 3698 goto out; 3699 } 3700 3701 err = of_mdiobus_register(bus, np); 3702 if (err) { 3703 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3704 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3705 goto out; 3706 } 3707 3708 if (external) 3709 list_add_tail(&mdio_bus->list, &chip->mdios); 3710 else 3711 list_add(&mdio_bus->list, &chip->mdios); 3712 3713 return 0; 3714 3715 out: 3716 mdiobus_free(bus); 3717 return err; 3718 } 3719 3720 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3721 3722 { 3723 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3724 struct mii_bus *bus; 3725 3726 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3727 bus = mdio_bus->bus; 3728 3729 if (!mdio_bus->external) 3730 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3731 3732 mdiobus_unregister(bus); 3733 mdiobus_free(bus); 3734 } 3735 } 3736 3737 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3738 { 3739 struct device_node *np = chip->dev->of_node; 3740 struct device_node *child; 3741 int err; 3742 3743 /* Always register one mdio bus for the internal/default mdio 3744 * bus. This maybe represented in the device tree, but is 3745 * optional. 3746 */ 3747 child = of_get_child_by_name(np, "mdio"); 3748 err = mv88e6xxx_mdio_register(chip, child, false); 3749 of_node_put(child); 3750 if (err) 3751 return err; 3752 3753 /* Walk the device tree, and see if there are any other nodes 3754 * which say they are compatible with the external mdio 3755 * bus. 3756 */ 3757 for_each_available_child_of_node(np, child) { 3758 if (of_device_is_compatible( 3759 child, "marvell,mv88e6xxx-mdio-external")) { 3760 err = mv88e6xxx_mdio_register(chip, child, true); 3761 if (err) { 3762 mv88e6xxx_mdios_unregister(chip); 3763 of_node_put(child); 3764 return err; 3765 } 3766 } 3767 } 3768 3769 return 0; 3770 } 3771 3772 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3773 { 3774 struct mv88e6xxx_chip *chip = ds->priv; 3775 3776 mv88e6xxx_teardown_devlink_params(ds); 3777 dsa_devlink_resources_unregister(ds); 3778 mv88e6xxx_teardown_devlink_regions_global(ds); 3779 mv88e6xxx_mdios_unregister(chip); 3780 } 3781 3782 static int mv88e6xxx_setup(struct dsa_switch *ds) 3783 { 3784 struct mv88e6xxx_chip *chip = ds->priv; 3785 u8 cmode; 3786 int err; 3787 int i; 3788 3789 err = mv88e6xxx_mdios_register(chip); 3790 if (err) 3791 return err; 3792 3793 chip->ds = ds; 3794 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3795 3796 /* Since virtual bridges are mapped in the PVT, the number we support 3797 * depends on the physical switch topology. We need to let DSA figure 3798 * that out and therefore we cannot set this at dsa_register_switch() 3799 * time. 3800 */ 3801 if (mv88e6xxx_has_pvt(chip)) 3802 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3803 ds->dst->last_switch - 1; 3804 3805 mv88e6xxx_reg_lock(chip); 3806 3807 if (chip->info->ops->setup_errata) { 3808 err = chip->info->ops->setup_errata(chip); 3809 if (err) 3810 goto unlock; 3811 } 3812 3813 /* Cache the cmode of each port. */ 3814 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3815 if (chip->info->ops->port_get_cmode) { 3816 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3817 if (err) 3818 goto unlock; 3819 3820 chip->ports[i].cmode = cmode; 3821 } 3822 } 3823 3824 err = mv88e6xxx_vtu_setup(chip); 3825 if (err) 3826 goto unlock; 3827 3828 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3829 * VTU, thereby also flushing the STU). 3830 */ 3831 err = mv88e6xxx_stu_setup(chip); 3832 if (err) 3833 goto unlock; 3834 3835 /* Setup Switch Port Registers */ 3836 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3837 if (dsa_is_unused_port(ds, i)) 3838 continue; 3839 3840 /* Prevent the use of an invalid port. */ 3841 if (mv88e6xxx_is_invalid_port(chip, i)) { 3842 dev_err(chip->dev, "port %d is invalid\n", i); 3843 err = -EINVAL; 3844 goto unlock; 3845 } 3846 3847 err = mv88e6xxx_setup_port(chip, i); 3848 if (err) 3849 goto unlock; 3850 } 3851 3852 err = mv88e6xxx_irl_setup(chip); 3853 if (err) 3854 goto unlock; 3855 3856 err = mv88e6xxx_mac_setup(chip); 3857 if (err) 3858 goto unlock; 3859 3860 err = mv88e6xxx_phy_setup(chip); 3861 if (err) 3862 goto unlock; 3863 3864 err = mv88e6xxx_pvt_setup(chip); 3865 if (err) 3866 goto unlock; 3867 3868 err = mv88e6xxx_atu_setup(chip); 3869 if (err) 3870 goto unlock; 3871 3872 err = mv88e6xxx_broadcast_setup(chip, 0); 3873 if (err) 3874 goto unlock; 3875 3876 err = mv88e6xxx_pot_setup(chip); 3877 if (err) 3878 goto unlock; 3879 3880 err = mv88e6xxx_rmu_setup(chip); 3881 if (err) 3882 goto unlock; 3883 3884 err = mv88e6xxx_rsvd2cpu_setup(chip); 3885 if (err) 3886 goto unlock; 3887 3888 err = mv88e6xxx_trunk_setup(chip); 3889 if (err) 3890 goto unlock; 3891 3892 err = mv88e6xxx_devmap_setup(chip); 3893 if (err) 3894 goto unlock; 3895 3896 err = mv88e6xxx_pri_setup(chip); 3897 if (err) 3898 goto unlock; 3899 3900 /* Setup PTP Hardware Clock and timestamping */ 3901 if (chip->info->ptp_support) { 3902 err = mv88e6xxx_ptp_setup(chip); 3903 if (err) 3904 goto unlock; 3905 3906 err = mv88e6xxx_hwtstamp_setup(chip); 3907 if (err) 3908 goto unlock; 3909 } 3910 3911 err = mv88e6xxx_stats_setup(chip); 3912 if (err) 3913 goto unlock; 3914 3915 unlock: 3916 mv88e6xxx_reg_unlock(chip); 3917 3918 if (err) 3919 goto out_mdios; 3920 3921 /* Have to be called without holding the register lock, since 3922 * they take the devlink lock, and we later take the locks in 3923 * the reverse order when getting/setting parameters or 3924 * resource occupancy. 3925 */ 3926 err = mv88e6xxx_setup_devlink_resources(ds); 3927 if (err) 3928 goto out_mdios; 3929 3930 err = mv88e6xxx_setup_devlink_params(ds); 3931 if (err) 3932 goto out_resources; 3933 3934 err = mv88e6xxx_setup_devlink_regions_global(ds); 3935 if (err) 3936 goto out_params; 3937 3938 return 0; 3939 3940 out_params: 3941 mv88e6xxx_teardown_devlink_params(ds); 3942 out_resources: 3943 dsa_devlink_resources_unregister(ds); 3944 out_mdios: 3945 mv88e6xxx_mdios_unregister(chip); 3946 3947 return err; 3948 } 3949 3950 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3951 { 3952 struct mv88e6xxx_chip *chip = ds->priv; 3953 int err; 3954 3955 if (chip->info->ops->pcs_ops && 3956 chip->info->ops->pcs_ops->pcs_init) { 3957 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 3958 if (err) 3959 return err; 3960 } 3961 3962 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3963 } 3964 3965 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3966 { 3967 struct mv88e6xxx_chip *chip = ds->priv; 3968 3969 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3970 3971 if (chip->info->ops->pcs_ops && 3972 chip->info->ops->pcs_ops->pcs_teardown) 3973 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 3974 } 3975 3976 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3977 { 3978 struct mv88e6xxx_chip *chip = ds->priv; 3979 3980 return chip->eeprom_len; 3981 } 3982 3983 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3984 struct ethtool_eeprom *eeprom, u8 *data) 3985 { 3986 struct mv88e6xxx_chip *chip = ds->priv; 3987 int err; 3988 3989 if (!chip->info->ops->get_eeprom) 3990 return -EOPNOTSUPP; 3991 3992 mv88e6xxx_reg_lock(chip); 3993 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3994 mv88e6xxx_reg_unlock(chip); 3995 3996 if (err) 3997 return err; 3998 3999 eeprom->magic = 0xc3ec4951; 4000 4001 return 0; 4002 } 4003 4004 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4005 struct ethtool_eeprom *eeprom, u8 *data) 4006 { 4007 struct mv88e6xxx_chip *chip = ds->priv; 4008 int err; 4009 4010 if (!chip->info->ops->set_eeprom) 4011 return -EOPNOTSUPP; 4012 4013 if (eeprom->magic != 0xc3ec4951) 4014 return -EINVAL; 4015 4016 mv88e6xxx_reg_lock(chip); 4017 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4018 mv88e6xxx_reg_unlock(chip); 4019 4020 return err; 4021 } 4022 4023 static const struct mv88e6xxx_ops mv88e6085_ops = { 4024 /* MV88E6XXX_FAMILY_6097 */ 4025 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4026 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4027 .irl_init_all = mv88e6352_g2_irl_init_all, 4028 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4029 .phy_read = mv88e6185_phy_ppu_read, 4030 .phy_write = mv88e6185_phy_ppu_write, 4031 .port_set_link = mv88e6xxx_port_set_link, 4032 .port_sync_link = mv88e6xxx_port_sync_link, 4033 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4034 .port_tag_remap = mv88e6095_port_tag_remap, 4035 .port_set_policy = mv88e6352_port_set_policy, 4036 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4037 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4038 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4039 .port_set_ether_type = mv88e6351_port_set_ether_type, 4040 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4041 .port_pause_limit = mv88e6097_port_pause_limit, 4042 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4043 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4044 .port_get_cmode = mv88e6185_port_get_cmode, 4045 .port_setup_message_port = mv88e6xxx_setup_message_port, 4046 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4047 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4048 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4049 .stats_get_strings = mv88e6095_stats_get_strings, 4050 .stats_get_stats = mv88e6095_stats_get_stats, 4051 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4052 .set_egress_port = mv88e6095_g1_set_egress_port, 4053 .watchdog_ops = &mv88e6097_watchdog_ops, 4054 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4055 .pot_clear = mv88e6xxx_g2_pot_clear, 4056 .ppu_enable = mv88e6185_g1_ppu_enable, 4057 .ppu_disable = mv88e6185_g1_ppu_disable, 4058 .reset = mv88e6185_g1_reset, 4059 .rmu_disable = mv88e6085_g1_rmu_disable, 4060 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4061 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4062 .stu_getnext = mv88e6352_g1_stu_getnext, 4063 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4064 .phylink_get_caps = mv88e6185_phylink_get_caps, 4065 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4066 }; 4067 4068 static const struct mv88e6xxx_ops mv88e6095_ops = { 4069 /* MV88E6XXX_FAMILY_6095 */ 4070 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4071 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4072 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4073 .phy_read = mv88e6185_phy_ppu_read, 4074 .phy_write = mv88e6185_phy_ppu_write, 4075 .port_set_link = mv88e6xxx_port_set_link, 4076 .port_sync_link = mv88e6185_port_sync_link, 4077 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4078 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4079 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4080 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4081 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4082 .port_get_cmode = mv88e6185_port_get_cmode, 4083 .port_setup_message_port = mv88e6xxx_setup_message_port, 4084 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4085 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4086 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4087 .stats_get_strings = mv88e6095_stats_get_strings, 4088 .stats_get_stats = mv88e6095_stats_get_stats, 4089 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4090 .ppu_enable = mv88e6185_g1_ppu_enable, 4091 .ppu_disable = mv88e6185_g1_ppu_disable, 4092 .reset = mv88e6185_g1_reset, 4093 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4094 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4095 .phylink_get_caps = mv88e6095_phylink_get_caps, 4096 .pcs_ops = &mv88e6185_pcs_ops, 4097 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4098 }; 4099 4100 static const struct mv88e6xxx_ops mv88e6097_ops = { 4101 /* MV88E6XXX_FAMILY_6097 */ 4102 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4103 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4104 .irl_init_all = mv88e6352_g2_irl_init_all, 4105 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4106 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4107 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4108 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4109 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4110 .port_set_link = mv88e6xxx_port_set_link, 4111 .port_sync_link = mv88e6185_port_sync_link, 4112 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4113 .port_tag_remap = mv88e6095_port_tag_remap, 4114 .port_set_policy = mv88e6352_port_set_policy, 4115 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4116 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4117 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4118 .port_set_ether_type = mv88e6351_port_set_ether_type, 4119 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4120 .port_pause_limit = mv88e6097_port_pause_limit, 4121 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4122 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4123 .port_get_cmode = mv88e6185_port_get_cmode, 4124 .port_setup_message_port = mv88e6xxx_setup_message_port, 4125 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4126 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4127 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4128 .stats_get_strings = mv88e6095_stats_get_strings, 4129 .stats_get_stats = mv88e6095_stats_get_stats, 4130 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4131 .set_egress_port = mv88e6095_g1_set_egress_port, 4132 .watchdog_ops = &mv88e6097_watchdog_ops, 4133 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4134 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4135 .pot_clear = mv88e6xxx_g2_pot_clear, 4136 .reset = mv88e6352_g1_reset, 4137 .rmu_disable = mv88e6085_g1_rmu_disable, 4138 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4139 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4140 .phylink_get_caps = mv88e6095_phylink_get_caps, 4141 .pcs_ops = &mv88e6185_pcs_ops, 4142 .stu_getnext = mv88e6352_g1_stu_getnext, 4143 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4144 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4145 }; 4146 4147 static const struct mv88e6xxx_ops mv88e6123_ops = { 4148 /* MV88E6XXX_FAMILY_6165 */ 4149 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4150 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4151 .irl_init_all = mv88e6352_g2_irl_init_all, 4152 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4153 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4154 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4155 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4156 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4157 .port_set_link = mv88e6xxx_port_set_link, 4158 .port_sync_link = mv88e6xxx_port_sync_link, 4159 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4160 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4161 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4162 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4163 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4164 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4165 .port_get_cmode = mv88e6185_port_get_cmode, 4166 .port_setup_message_port = mv88e6xxx_setup_message_port, 4167 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4168 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4169 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4170 .stats_get_strings = mv88e6095_stats_get_strings, 4171 .stats_get_stats = mv88e6095_stats_get_stats, 4172 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4173 .set_egress_port = mv88e6095_g1_set_egress_port, 4174 .watchdog_ops = &mv88e6097_watchdog_ops, 4175 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4176 .pot_clear = mv88e6xxx_g2_pot_clear, 4177 .reset = mv88e6352_g1_reset, 4178 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4179 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4180 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4181 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4182 .stu_getnext = mv88e6352_g1_stu_getnext, 4183 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4184 .phylink_get_caps = mv88e6185_phylink_get_caps, 4185 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4186 }; 4187 4188 static const struct mv88e6xxx_ops mv88e6131_ops = { 4189 /* MV88E6XXX_FAMILY_6185 */ 4190 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4191 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4192 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4193 .phy_read = mv88e6185_phy_ppu_read, 4194 .phy_write = mv88e6185_phy_ppu_write, 4195 .port_set_link = mv88e6xxx_port_set_link, 4196 .port_sync_link = mv88e6xxx_port_sync_link, 4197 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4198 .port_tag_remap = mv88e6095_port_tag_remap, 4199 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4200 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4201 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4202 .port_set_ether_type = mv88e6351_port_set_ether_type, 4203 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4204 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4205 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4206 .port_pause_limit = mv88e6097_port_pause_limit, 4207 .port_set_pause = mv88e6185_port_set_pause, 4208 .port_get_cmode = mv88e6185_port_get_cmode, 4209 .port_setup_message_port = mv88e6xxx_setup_message_port, 4210 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4211 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4212 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4213 .stats_get_strings = mv88e6095_stats_get_strings, 4214 .stats_get_stats = mv88e6095_stats_get_stats, 4215 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4216 .set_egress_port = mv88e6095_g1_set_egress_port, 4217 .watchdog_ops = &mv88e6097_watchdog_ops, 4218 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4219 .ppu_enable = mv88e6185_g1_ppu_enable, 4220 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4221 .ppu_disable = mv88e6185_g1_ppu_disable, 4222 .reset = mv88e6185_g1_reset, 4223 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4224 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4225 .phylink_get_caps = mv88e6185_phylink_get_caps, 4226 }; 4227 4228 static const struct mv88e6xxx_ops mv88e6141_ops = { 4229 /* MV88E6XXX_FAMILY_6341 */ 4230 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4231 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4232 .irl_init_all = mv88e6352_g2_irl_init_all, 4233 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4234 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4235 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4236 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4237 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4238 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4239 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4240 .port_set_link = mv88e6xxx_port_set_link, 4241 .port_sync_link = mv88e6xxx_port_sync_link, 4242 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4243 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4244 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4245 .port_tag_remap = mv88e6095_port_tag_remap, 4246 .port_set_policy = mv88e6352_port_set_policy, 4247 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4248 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4249 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4250 .port_set_ether_type = mv88e6351_port_set_ether_type, 4251 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4252 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4253 .port_pause_limit = mv88e6097_port_pause_limit, 4254 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4255 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4256 .port_get_cmode = mv88e6352_port_get_cmode, 4257 .port_set_cmode = mv88e6341_port_set_cmode, 4258 .port_setup_message_port = mv88e6xxx_setup_message_port, 4259 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4260 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4261 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4262 .stats_get_strings = mv88e6320_stats_get_strings, 4263 .stats_get_stats = mv88e6390_stats_get_stats, 4264 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4265 .set_egress_port = mv88e6390_g1_set_egress_port, 4266 .watchdog_ops = &mv88e6390_watchdog_ops, 4267 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4268 .pot_clear = mv88e6xxx_g2_pot_clear, 4269 .reset = mv88e6352_g1_reset, 4270 .rmu_disable = mv88e6390_g1_rmu_disable, 4271 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4272 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4273 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4274 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4275 .stu_getnext = mv88e6352_g1_stu_getnext, 4276 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4277 .serdes_get_lane = mv88e6341_serdes_get_lane, 4278 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4279 .gpio_ops = &mv88e6352_gpio_ops, 4280 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4281 .serdes_get_strings = mv88e6390_serdes_get_strings, 4282 .serdes_get_stats = mv88e6390_serdes_get_stats, 4283 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4284 .serdes_get_regs = mv88e6390_serdes_get_regs, 4285 .phylink_get_caps = mv88e6341_phylink_get_caps, 4286 .pcs_ops = &mv88e6390_pcs_ops, 4287 }; 4288 4289 static const struct mv88e6xxx_ops mv88e6161_ops = { 4290 /* MV88E6XXX_FAMILY_6165 */ 4291 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4292 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4293 .irl_init_all = mv88e6352_g2_irl_init_all, 4294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4295 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4296 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4297 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4298 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4299 .port_set_link = mv88e6xxx_port_set_link, 4300 .port_sync_link = mv88e6xxx_port_sync_link, 4301 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4302 .port_tag_remap = mv88e6095_port_tag_remap, 4303 .port_set_policy = mv88e6352_port_set_policy, 4304 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4305 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4306 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4307 .port_set_ether_type = mv88e6351_port_set_ether_type, 4308 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4309 .port_pause_limit = mv88e6097_port_pause_limit, 4310 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4311 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4312 .port_get_cmode = mv88e6185_port_get_cmode, 4313 .port_setup_message_port = mv88e6xxx_setup_message_port, 4314 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4315 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4316 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4317 .stats_get_strings = mv88e6095_stats_get_strings, 4318 .stats_get_stats = mv88e6095_stats_get_stats, 4319 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4320 .set_egress_port = mv88e6095_g1_set_egress_port, 4321 .watchdog_ops = &mv88e6097_watchdog_ops, 4322 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4323 .pot_clear = mv88e6xxx_g2_pot_clear, 4324 .reset = mv88e6352_g1_reset, 4325 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4326 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4327 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4328 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4329 .stu_getnext = mv88e6352_g1_stu_getnext, 4330 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4331 .avb_ops = &mv88e6165_avb_ops, 4332 .ptp_ops = &mv88e6165_ptp_ops, 4333 .phylink_get_caps = mv88e6185_phylink_get_caps, 4334 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4335 }; 4336 4337 static const struct mv88e6xxx_ops mv88e6165_ops = { 4338 /* MV88E6XXX_FAMILY_6165 */ 4339 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4340 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4341 .irl_init_all = mv88e6352_g2_irl_init_all, 4342 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4343 .phy_read = mv88e6165_phy_read, 4344 .phy_write = mv88e6165_phy_write, 4345 .port_set_link = mv88e6xxx_port_set_link, 4346 .port_sync_link = mv88e6xxx_port_sync_link, 4347 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4348 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4349 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4350 .port_get_cmode = mv88e6185_port_get_cmode, 4351 .port_setup_message_port = mv88e6xxx_setup_message_port, 4352 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4353 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4354 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4355 .stats_get_strings = mv88e6095_stats_get_strings, 4356 .stats_get_stats = mv88e6095_stats_get_stats, 4357 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4358 .set_egress_port = mv88e6095_g1_set_egress_port, 4359 .watchdog_ops = &mv88e6097_watchdog_ops, 4360 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4361 .pot_clear = mv88e6xxx_g2_pot_clear, 4362 .reset = mv88e6352_g1_reset, 4363 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4364 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4365 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4366 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4367 .stu_getnext = mv88e6352_g1_stu_getnext, 4368 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4369 .avb_ops = &mv88e6165_avb_ops, 4370 .ptp_ops = &mv88e6165_ptp_ops, 4371 .phylink_get_caps = mv88e6185_phylink_get_caps, 4372 }; 4373 4374 static const struct mv88e6xxx_ops mv88e6171_ops = { 4375 /* MV88E6XXX_FAMILY_6351 */ 4376 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4377 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4378 .irl_init_all = mv88e6352_g2_irl_init_all, 4379 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4380 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4381 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4382 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4383 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4384 .port_set_link = mv88e6xxx_port_set_link, 4385 .port_sync_link = mv88e6xxx_port_sync_link, 4386 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4387 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4388 .port_tag_remap = mv88e6095_port_tag_remap, 4389 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4390 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4391 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4392 .port_set_ether_type = mv88e6351_port_set_ether_type, 4393 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4394 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4395 .port_pause_limit = mv88e6097_port_pause_limit, 4396 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4397 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4398 .port_get_cmode = mv88e6352_port_get_cmode, 4399 .port_setup_message_port = mv88e6xxx_setup_message_port, 4400 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4401 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4402 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4403 .stats_get_strings = mv88e6095_stats_get_strings, 4404 .stats_get_stats = mv88e6095_stats_get_stats, 4405 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4406 .set_egress_port = mv88e6095_g1_set_egress_port, 4407 .watchdog_ops = &mv88e6097_watchdog_ops, 4408 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4409 .pot_clear = mv88e6xxx_g2_pot_clear, 4410 .reset = mv88e6352_g1_reset, 4411 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4412 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4413 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4414 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4415 .stu_getnext = mv88e6352_g1_stu_getnext, 4416 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4417 .phylink_get_caps = mv88e6351_phylink_get_caps, 4418 }; 4419 4420 static const struct mv88e6xxx_ops mv88e6172_ops = { 4421 /* MV88E6XXX_FAMILY_6352 */ 4422 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4423 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4424 .irl_init_all = mv88e6352_g2_irl_init_all, 4425 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4426 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4427 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4428 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4429 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4430 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4431 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4432 .port_set_link = mv88e6xxx_port_set_link, 4433 .port_sync_link = mv88e6xxx_port_sync_link, 4434 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4435 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4436 .port_tag_remap = mv88e6095_port_tag_remap, 4437 .port_set_policy = mv88e6352_port_set_policy, 4438 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4439 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4440 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4441 .port_set_ether_type = mv88e6351_port_set_ether_type, 4442 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4443 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4444 .port_pause_limit = mv88e6097_port_pause_limit, 4445 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4446 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4447 .port_get_cmode = mv88e6352_port_get_cmode, 4448 .port_setup_message_port = mv88e6xxx_setup_message_port, 4449 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4450 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4451 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4452 .stats_get_strings = mv88e6095_stats_get_strings, 4453 .stats_get_stats = mv88e6095_stats_get_stats, 4454 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4455 .set_egress_port = mv88e6095_g1_set_egress_port, 4456 .watchdog_ops = &mv88e6097_watchdog_ops, 4457 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4458 .pot_clear = mv88e6xxx_g2_pot_clear, 4459 .reset = mv88e6352_g1_reset, 4460 .rmu_disable = mv88e6352_g1_rmu_disable, 4461 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4462 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4463 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4464 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4465 .stu_getnext = mv88e6352_g1_stu_getnext, 4466 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4467 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4468 .serdes_get_regs = mv88e6352_serdes_get_regs, 4469 .gpio_ops = &mv88e6352_gpio_ops, 4470 .phylink_get_caps = mv88e6352_phylink_get_caps, 4471 .pcs_ops = &mv88e6352_pcs_ops, 4472 }; 4473 4474 static const struct mv88e6xxx_ops mv88e6175_ops = { 4475 /* MV88E6XXX_FAMILY_6351 */ 4476 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4477 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4478 .irl_init_all = mv88e6352_g2_irl_init_all, 4479 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4480 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4481 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4482 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4483 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4484 .port_set_link = mv88e6xxx_port_set_link, 4485 .port_sync_link = mv88e6xxx_port_sync_link, 4486 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4487 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4488 .port_tag_remap = mv88e6095_port_tag_remap, 4489 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4490 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4491 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4492 .port_set_ether_type = mv88e6351_port_set_ether_type, 4493 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4494 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4495 .port_pause_limit = mv88e6097_port_pause_limit, 4496 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4497 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4498 .port_get_cmode = mv88e6352_port_get_cmode, 4499 .port_setup_message_port = mv88e6xxx_setup_message_port, 4500 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4501 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4502 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4503 .stats_get_strings = mv88e6095_stats_get_strings, 4504 .stats_get_stats = mv88e6095_stats_get_stats, 4505 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4506 .set_egress_port = mv88e6095_g1_set_egress_port, 4507 .watchdog_ops = &mv88e6097_watchdog_ops, 4508 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4509 .pot_clear = mv88e6xxx_g2_pot_clear, 4510 .reset = mv88e6352_g1_reset, 4511 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4512 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4513 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4514 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4515 .stu_getnext = mv88e6352_g1_stu_getnext, 4516 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4517 .phylink_get_caps = mv88e6351_phylink_get_caps, 4518 }; 4519 4520 static const struct mv88e6xxx_ops mv88e6176_ops = { 4521 /* MV88E6XXX_FAMILY_6352 */ 4522 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4523 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4524 .irl_init_all = mv88e6352_g2_irl_init_all, 4525 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4526 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4527 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4528 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4529 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4530 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4531 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4532 .port_set_link = mv88e6xxx_port_set_link, 4533 .port_sync_link = mv88e6xxx_port_sync_link, 4534 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4535 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4536 .port_tag_remap = mv88e6095_port_tag_remap, 4537 .port_set_policy = mv88e6352_port_set_policy, 4538 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4539 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4540 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4541 .port_set_ether_type = mv88e6351_port_set_ether_type, 4542 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4543 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4544 .port_pause_limit = mv88e6097_port_pause_limit, 4545 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4546 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4547 .port_get_cmode = mv88e6352_port_get_cmode, 4548 .port_setup_message_port = mv88e6xxx_setup_message_port, 4549 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4550 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4551 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4552 .stats_get_strings = mv88e6095_stats_get_strings, 4553 .stats_get_stats = mv88e6095_stats_get_stats, 4554 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4555 .set_egress_port = mv88e6095_g1_set_egress_port, 4556 .watchdog_ops = &mv88e6097_watchdog_ops, 4557 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4558 .pot_clear = mv88e6xxx_g2_pot_clear, 4559 .reset = mv88e6352_g1_reset, 4560 .rmu_disable = mv88e6352_g1_rmu_disable, 4561 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4562 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4563 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4564 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4565 .stu_getnext = mv88e6352_g1_stu_getnext, 4566 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4567 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4568 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4569 .serdes_get_regs = mv88e6352_serdes_get_regs, 4570 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4571 .gpio_ops = &mv88e6352_gpio_ops, 4572 .phylink_get_caps = mv88e6352_phylink_get_caps, 4573 .pcs_ops = &mv88e6352_pcs_ops, 4574 }; 4575 4576 static const struct mv88e6xxx_ops mv88e6185_ops = { 4577 /* MV88E6XXX_FAMILY_6185 */ 4578 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4579 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4580 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4581 .phy_read = mv88e6185_phy_ppu_read, 4582 .phy_write = mv88e6185_phy_ppu_write, 4583 .port_set_link = mv88e6xxx_port_set_link, 4584 .port_sync_link = mv88e6185_port_sync_link, 4585 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4586 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4587 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4588 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4589 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4590 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4591 .port_set_pause = mv88e6185_port_set_pause, 4592 .port_get_cmode = mv88e6185_port_get_cmode, 4593 .port_setup_message_port = mv88e6xxx_setup_message_port, 4594 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4595 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4596 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4597 .stats_get_strings = mv88e6095_stats_get_strings, 4598 .stats_get_stats = mv88e6095_stats_get_stats, 4599 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4600 .set_egress_port = mv88e6095_g1_set_egress_port, 4601 .watchdog_ops = &mv88e6097_watchdog_ops, 4602 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4603 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4604 .ppu_enable = mv88e6185_g1_ppu_enable, 4605 .ppu_disable = mv88e6185_g1_ppu_disable, 4606 .reset = mv88e6185_g1_reset, 4607 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4608 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4609 .phylink_get_caps = mv88e6185_phylink_get_caps, 4610 .pcs_ops = &mv88e6185_pcs_ops, 4611 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4612 }; 4613 4614 static const struct mv88e6xxx_ops mv88e6190_ops = { 4615 /* MV88E6XXX_FAMILY_6390 */ 4616 .setup_errata = mv88e6390_setup_errata, 4617 .irl_init_all = mv88e6390_g2_irl_init_all, 4618 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4619 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4620 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4621 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4622 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4623 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4624 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4625 .port_set_link = mv88e6xxx_port_set_link, 4626 .port_sync_link = mv88e6xxx_port_sync_link, 4627 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4628 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4629 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4630 .port_tag_remap = mv88e6390_port_tag_remap, 4631 .port_set_policy = mv88e6352_port_set_policy, 4632 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4633 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4634 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4635 .port_set_ether_type = mv88e6351_port_set_ether_type, 4636 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4637 .port_pause_limit = mv88e6390_port_pause_limit, 4638 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4639 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4640 .port_get_cmode = mv88e6352_port_get_cmode, 4641 .port_set_cmode = mv88e6390_port_set_cmode, 4642 .port_setup_message_port = mv88e6xxx_setup_message_port, 4643 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4644 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4645 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4646 .stats_get_strings = mv88e6320_stats_get_strings, 4647 .stats_get_stats = mv88e6390_stats_get_stats, 4648 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4649 .set_egress_port = mv88e6390_g1_set_egress_port, 4650 .watchdog_ops = &mv88e6390_watchdog_ops, 4651 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4652 .pot_clear = mv88e6xxx_g2_pot_clear, 4653 .reset = mv88e6352_g1_reset, 4654 .rmu_disable = mv88e6390_g1_rmu_disable, 4655 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4656 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4657 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4658 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4659 .stu_getnext = mv88e6390_g1_stu_getnext, 4660 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4661 .serdes_get_lane = mv88e6390_serdes_get_lane, 4662 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4663 .serdes_get_strings = mv88e6390_serdes_get_strings, 4664 .serdes_get_stats = mv88e6390_serdes_get_stats, 4665 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4666 .serdes_get_regs = mv88e6390_serdes_get_regs, 4667 .gpio_ops = &mv88e6352_gpio_ops, 4668 .phylink_get_caps = mv88e6390_phylink_get_caps, 4669 .pcs_ops = &mv88e6390_pcs_ops, 4670 }; 4671 4672 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4673 /* MV88E6XXX_FAMILY_6390 */ 4674 .setup_errata = mv88e6390_setup_errata, 4675 .irl_init_all = mv88e6390_g2_irl_init_all, 4676 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4677 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4678 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4679 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4680 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4681 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4682 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4683 .port_set_link = mv88e6xxx_port_set_link, 4684 .port_sync_link = mv88e6xxx_port_sync_link, 4685 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4686 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4687 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4688 .port_tag_remap = mv88e6390_port_tag_remap, 4689 .port_set_policy = mv88e6352_port_set_policy, 4690 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4691 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4692 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4693 .port_set_ether_type = mv88e6351_port_set_ether_type, 4694 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4695 .port_pause_limit = mv88e6390_port_pause_limit, 4696 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4697 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4698 .port_get_cmode = mv88e6352_port_get_cmode, 4699 .port_set_cmode = mv88e6390x_port_set_cmode, 4700 .port_setup_message_port = mv88e6xxx_setup_message_port, 4701 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4702 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4703 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4704 .stats_get_strings = mv88e6320_stats_get_strings, 4705 .stats_get_stats = mv88e6390_stats_get_stats, 4706 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4707 .set_egress_port = mv88e6390_g1_set_egress_port, 4708 .watchdog_ops = &mv88e6390_watchdog_ops, 4709 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4710 .pot_clear = mv88e6xxx_g2_pot_clear, 4711 .reset = mv88e6352_g1_reset, 4712 .rmu_disable = mv88e6390_g1_rmu_disable, 4713 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4714 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4715 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4716 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4717 .stu_getnext = mv88e6390_g1_stu_getnext, 4718 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4719 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4720 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4721 .serdes_get_strings = mv88e6390_serdes_get_strings, 4722 .serdes_get_stats = mv88e6390_serdes_get_stats, 4723 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4724 .serdes_get_regs = mv88e6390_serdes_get_regs, 4725 .gpio_ops = &mv88e6352_gpio_ops, 4726 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4727 .pcs_ops = &mv88e6390_pcs_ops, 4728 }; 4729 4730 static const struct mv88e6xxx_ops mv88e6191_ops = { 4731 /* MV88E6XXX_FAMILY_6390 */ 4732 .setup_errata = mv88e6390_setup_errata, 4733 .irl_init_all = mv88e6390_g2_irl_init_all, 4734 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4735 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4736 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4737 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4738 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4739 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4740 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4741 .port_set_link = mv88e6xxx_port_set_link, 4742 .port_sync_link = mv88e6xxx_port_sync_link, 4743 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4744 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4745 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4746 .port_tag_remap = mv88e6390_port_tag_remap, 4747 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4748 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4749 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4750 .port_set_ether_type = mv88e6351_port_set_ether_type, 4751 .port_pause_limit = mv88e6390_port_pause_limit, 4752 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4753 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4754 .port_get_cmode = mv88e6352_port_get_cmode, 4755 .port_set_cmode = mv88e6390_port_set_cmode, 4756 .port_setup_message_port = mv88e6xxx_setup_message_port, 4757 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4758 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4759 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4760 .stats_get_strings = mv88e6320_stats_get_strings, 4761 .stats_get_stats = mv88e6390_stats_get_stats, 4762 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4763 .set_egress_port = mv88e6390_g1_set_egress_port, 4764 .watchdog_ops = &mv88e6390_watchdog_ops, 4765 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4766 .pot_clear = mv88e6xxx_g2_pot_clear, 4767 .reset = mv88e6352_g1_reset, 4768 .rmu_disable = mv88e6390_g1_rmu_disable, 4769 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4770 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4771 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4772 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4773 .stu_getnext = mv88e6390_g1_stu_getnext, 4774 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4775 .serdes_get_lane = mv88e6390_serdes_get_lane, 4776 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4777 .serdes_get_strings = mv88e6390_serdes_get_strings, 4778 .serdes_get_stats = mv88e6390_serdes_get_stats, 4779 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4780 .serdes_get_regs = mv88e6390_serdes_get_regs, 4781 .avb_ops = &mv88e6390_avb_ops, 4782 .ptp_ops = &mv88e6352_ptp_ops, 4783 .phylink_get_caps = mv88e6390_phylink_get_caps, 4784 .pcs_ops = &mv88e6390_pcs_ops, 4785 }; 4786 4787 static const struct mv88e6xxx_ops mv88e6240_ops = { 4788 /* MV88E6XXX_FAMILY_6352 */ 4789 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4790 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4791 .irl_init_all = mv88e6352_g2_irl_init_all, 4792 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4793 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4794 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4795 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4796 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4797 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4798 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4799 .port_set_link = mv88e6xxx_port_set_link, 4800 .port_sync_link = mv88e6xxx_port_sync_link, 4801 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4802 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4803 .port_tag_remap = mv88e6095_port_tag_remap, 4804 .port_set_policy = mv88e6352_port_set_policy, 4805 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4806 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4807 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4808 .port_set_ether_type = mv88e6351_port_set_ether_type, 4809 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4810 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4811 .port_pause_limit = mv88e6097_port_pause_limit, 4812 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4813 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4814 .port_get_cmode = mv88e6352_port_get_cmode, 4815 .port_setup_message_port = mv88e6xxx_setup_message_port, 4816 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4817 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4818 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4819 .stats_get_strings = mv88e6095_stats_get_strings, 4820 .stats_get_stats = mv88e6095_stats_get_stats, 4821 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4822 .set_egress_port = mv88e6095_g1_set_egress_port, 4823 .watchdog_ops = &mv88e6097_watchdog_ops, 4824 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4825 .pot_clear = mv88e6xxx_g2_pot_clear, 4826 .reset = mv88e6352_g1_reset, 4827 .rmu_disable = mv88e6352_g1_rmu_disable, 4828 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4829 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4830 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4831 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4832 .stu_getnext = mv88e6352_g1_stu_getnext, 4833 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4834 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4835 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4836 .serdes_get_regs = mv88e6352_serdes_get_regs, 4837 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4838 .gpio_ops = &mv88e6352_gpio_ops, 4839 .avb_ops = &mv88e6352_avb_ops, 4840 .ptp_ops = &mv88e6352_ptp_ops, 4841 .phylink_get_caps = mv88e6352_phylink_get_caps, 4842 .pcs_ops = &mv88e6352_pcs_ops, 4843 }; 4844 4845 static const struct mv88e6xxx_ops mv88e6250_ops = { 4846 /* MV88E6XXX_FAMILY_6250 */ 4847 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4848 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4849 .irl_init_all = mv88e6352_g2_irl_init_all, 4850 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4851 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4852 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4853 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4854 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4855 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4856 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4857 .port_set_link = mv88e6xxx_port_set_link, 4858 .port_sync_link = mv88e6xxx_port_sync_link, 4859 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4860 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4861 .port_tag_remap = mv88e6095_port_tag_remap, 4862 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4863 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4864 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4865 .port_set_ether_type = mv88e6351_port_set_ether_type, 4866 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4867 .port_pause_limit = mv88e6097_port_pause_limit, 4868 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4869 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4870 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4871 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4872 .stats_get_strings = mv88e6250_stats_get_strings, 4873 .stats_get_stats = mv88e6250_stats_get_stats, 4874 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4875 .set_egress_port = mv88e6095_g1_set_egress_port, 4876 .watchdog_ops = &mv88e6250_watchdog_ops, 4877 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4878 .pot_clear = mv88e6xxx_g2_pot_clear, 4879 .reset = mv88e6250_g1_reset, 4880 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4881 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4882 .avb_ops = &mv88e6352_avb_ops, 4883 .ptp_ops = &mv88e6250_ptp_ops, 4884 .phylink_get_caps = mv88e6250_phylink_get_caps, 4885 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4886 }; 4887 4888 static const struct mv88e6xxx_ops mv88e6290_ops = { 4889 /* MV88E6XXX_FAMILY_6390 */ 4890 .setup_errata = mv88e6390_setup_errata, 4891 .irl_init_all = mv88e6390_g2_irl_init_all, 4892 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4893 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4894 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4895 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4896 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4897 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4898 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4899 .port_set_link = mv88e6xxx_port_set_link, 4900 .port_sync_link = mv88e6xxx_port_sync_link, 4901 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4902 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4903 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4904 .port_tag_remap = mv88e6390_port_tag_remap, 4905 .port_set_policy = mv88e6352_port_set_policy, 4906 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4907 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4908 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4909 .port_set_ether_type = mv88e6351_port_set_ether_type, 4910 .port_pause_limit = mv88e6390_port_pause_limit, 4911 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4912 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4913 .port_get_cmode = mv88e6352_port_get_cmode, 4914 .port_set_cmode = mv88e6390_port_set_cmode, 4915 .port_setup_message_port = mv88e6xxx_setup_message_port, 4916 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4917 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4918 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4919 .stats_get_strings = mv88e6320_stats_get_strings, 4920 .stats_get_stats = mv88e6390_stats_get_stats, 4921 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4922 .set_egress_port = mv88e6390_g1_set_egress_port, 4923 .watchdog_ops = &mv88e6390_watchdog_ops, 4924 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4925 .pot_clear = mv88e6xxx_g2_pot_clear, 4926 .reset = mv88e6352_g1_reset, 4927 .rmu_disable = mv88e6390_g1_rmu_disable, 4928 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4929 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4930 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4931 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4932 .stu_getnext = mv88e6390_g1_stu_getnext, 4933 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4934 .serdes_get_lane = mv88e6390_serdes_get_lane, 4935 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4936 .serdes_get_strings = mv88e6390_serdes_get_strings, 4937 .serdes_get_stats = mv88e6390_serdes_get_stats, 4938 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4939 .serdes_get_regs = mv88e6390_serdes_get_regs, 4940 .gpio_ops = &mv88e6352_gpio_ops, 4941 .avb_ops = &mv88e6390_avb_ops, 4942 .ptp_ops = &mv88e6390_ptp_ops, 4943 .phylink_get_caps = mv88e6390_phylink_get_caps, 4944 .pcs_ops = &mv88e6390_pcs_ops, 4945 }; 4946 4947 static const struct mv88e6xxx_ops mv88e6320_ops = { 4948 /* MV88E6XXX_FAMILY_6320 */ 4949 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4950 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4951 .irl_init_all = mv88e6352_g2_irl_init_all, 4952 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4953 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4954 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4955 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4956 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4957 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4958 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4959 .port_set_link = mv88e6xxx_port_set_link, 4960 .port_sync_link = mv88e6xxx_port_sync_link, 4961 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 4962 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4963 .port_tag_remap = mv88e6095_port_tag_remap, 4964 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4965 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4966 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4967 .port_set_ether_type = mv88e6351_port_set_ether_type, 4968 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4969 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4970 .port_pause_limit = mv88e6097_port_pause_limit, 4971 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4972 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4973 .port_get_cmode = mv88e6352_port_get_cmode, 4974 .port_setup_message_port = mv88e6xxx_setup_message_port, 4975 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4976 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4977 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4978 .stats_get_strings = mv88e6320_stats_get_strings, 4979 .stats_get_stats = mv88e6320_stats_get_stats, 4980 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4981 .set_egress_port = mv88e6095_g1_set_egress_port, 4982 .watchdog_ops = &mv88e6390_watchdog_ops, 4983 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4984 .pot_clear = mv88e6xxx_g2_pot_clear, 4985 .reset = mv88e6352_g1_reset, 4986 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4987 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4988 .gpio_ops = &mv88e6352_gpio_ops, 4989 .avb_ops = &mv88e6352_avb_ops, 4990 .ptp_ops = &mv88e6352_ptp_ops, 4991 .phylink_get_caps = mv88e632x_phylink_get_caps, 4992 }; 4993 4994 static const struct mv88e6xxx_ops mv88e6321_ops = { 4995 /* MV88E6XXX_FAMILY_6320 */ 4996 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4997 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4998 .irl_init_all = mv88e6352_g2_irl_init_all, 4999 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5000 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5001 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5002 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5003 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5004 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5005 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5006 .port_set_link = mv88e6xxx_port_set_link, 5007 .port_sync_link = mv88e6xxx_port_sync_link, 5008 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5009 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5010 .port_tag_remap = mv88e6095_port_tag_remap, 5011 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5012 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5013 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5014 .port_set_ether_type = mv88e6351_port_set_ether_type, 5015 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5016 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5017 .port_pause_limit = mv88e6097_port_pause_limit, 5018 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5019 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5020 .port_get_cmode = mv88e6352_port_get_cmode, 5021 .port_setup_message_port = mv88e6xxx_setup_message_port, 5022 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5023 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5024 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5025 .stats_get_strings = mv88e6320_stats_get_strings, 5026 .stats_get_stats = mv88e6320_stats_get_stats, 5027 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5028 .set_egress_port = mv88e6095_g1_set_egress_port, 5029 .watchdog_ops = &mv88e6390_watchdog_ops, 5030 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5031 .reset = mv88e6352_g1_reset, 5032 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5033 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5034 .gpio_ops = &mv88e6352_gpio_ops, 5035 .avb_ops = &mv88e6352_avb_ops, 5036 .ptp_ops = &mv88e6352_ptp_ops, 5037 .phylink_get_caps = mv88e632x_phylink_get_caps, 5038 }; 5039 5040 static const struct mv88e6xxx_ops mv88e6341_ops = { 5041 /* MV88E6XXX_FAMILY_6341 */ 5042 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5043 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5044 .irl_init_all = mv88e6352_g2_irl_init_all, 5045 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5046 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5047 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5048 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5049 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5050 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5051 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5052 .port_set_link = mv88e6xxx_port_set_link, 5053 .port_sync_link = mv88e6xxx_port_sync_link, 5054 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5055 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5056 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5057 .port_tag_remap = mv88e6095_port_tag_remap, 5058 .port_set_policy = mv88e6352_port_set_policy, 5059 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5060 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5061 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5062 .port_set_ether_type = mv88e6351_port_set_ether_type, 5063 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5064 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5065 .port_pause_limit = mv88e6097_port_pause_limit, 5066 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5067 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5068 .port_get_cmode = mv88e6352_port_get_cmode, 5069 .port_set_cmode = mv88e6341_port_set_cmode, 5070 .port_setup_message_port = mv88e6xxx_setup_message_port, 5071 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5072 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5073 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5074 .stats_get_strings = mv88e6320_stats_get_strings, 5075 .stats_get_stats = mv88e6390_stats_get_stats, 5076 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5077 .set_egress_port = mv88e6390_g1_set_egress_port, 5078 .watchdog_ops = &mv88e6390_watchdog_ops, 5079 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5080 .pot_clear = mv88e6xxx_g2_pot_clear, 5081 .reset = mv88e6352_g1_reset, 5082 .rmu_disable = mv88e6390_g1_rmu_disable, 5083 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5084 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5085 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5086 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5087 .stu_getnext = mv88e6352_g1_stu_getnext, 5088 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5089 .serdes_get_lane = mv88e6341_serdes_get_lane, 5090 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5091 .gpio_ops = &mv88e6352_gpio_ops, 5092 .avb_ops = &mv88e6390_avb_ops, 5093 .ptp_ops = &mv88e6352_ptp_ops, 5094 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5095 .serdes_get_strings = mv88e6390_serdes_get_strings, 5096 .serdes_get_stats = mv88e6390_serdes_get_stats, 5097 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5098 .serdes_get_regs = mv88e6390_serdes_get_regs, 5099 .phylink_get_caps = mv88e6341_phylink_get_caps, 5100 .pcs_ops = &mv88e6390_pcs_ops, 5101 }; 5102 5103 static const struct mv88e6xxx_ops mv88e6350_ops = { 5104 /* MV88E6XXX_FAMILY_6351 */ 5105 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5106 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5107 .irl_init_all = mv88e6352_g2_irl_init_all, 5108 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5109 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5110 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5111 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5112 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5113 .port_set_link = mv88e6xxx_port_set_link, 5114 .port_sync_link = mv88e6xxx_port_sync_link, 5115 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5116 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5117 .port_tag_remap = mv88e6095_port_tag_remap, 5118 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5119 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5120 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5121 .port_set_ether_type = mv88e6351_port_set_ether_type, 5122 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5123 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5124 .port_pause_limit = mv88e6097_port_pause_limit, 5125 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5126 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5127 .port_get_cmode = mv88e6352_port_get_cmode, 5128 .port_setup_message_port = mv88e6xxx_setup_message_port, 5129 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5130 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5131 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5132 .stats_get_strings = mv88e6095_stats_get_strings, 5133 .stats_get_stats = mv88e6095_stats_get_stats, 5134 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5135 .set_egress_port = mv88e6095_g1_set_egress_port, 5136 .watchdog_ops = &mv88e6097_watchdog_ops, 5137 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5138 .pot_clear = mv88e6xxx_g2_pot_clear, 5139 .reset = mv88e6352_g1_reset, 5140 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5141 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5142 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5143 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5144 .stu_getnext = mv88e6352_g1_stu_getnext, 5145 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5146 .phylink_get_caps = mv88e6351_phylink_get_caps, 5147 }; 5148 5149 static const struct mv88e6xxx_ops mv88e6351_ops = { 5150 /* MV88E6XXX_FAMILY_6351 */ 5151 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5152 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5153 .irl_init_all = mv88e6352_g2_irl_init_all, 5154 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5155 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5156 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5157 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5158 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5159 .port_set_link = mv88e6xxx_port_set_link, 5160 .port_sync_link = mv88e6xxx_port_sync_link, 5161 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5162 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5163 .port_tag_remap = mv88e6095_port_tag_remap, 5164 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5165 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5166 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5167 .port_set_ether_type = mv88e6351_port_set_ether_type, 5168 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5169 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5170 .port_pause_limit = mv88e6097_port_pause_limit, 5171 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5172 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5173 .port_get_cmode = mv88e6352_port_get_cmode, 5174 .port_setup_message_port = mv88e6xxx_setup_message_port, 5175 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5176 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5177 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5178 .stats_get_strings = mv88e6095_stats_get_strings, 5179 .stats_get_stats = mv88e6095_stats_get_stats, 5180 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5181 .set_egress_port = mv88e6095_g1_set_egress_port, 5182 .watchdog_ops = &mv88e6097_watchdog_ops, 5183 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5184 .pot_clear = mv88e6xxx_g2_pot_clear, 5185 .reset = mv88e6352_g1_reset, 5186 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5187 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5188 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5189 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5190 .stu_getnext = mv88e6352_g1_stu_getnext, 5191 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5192 .avb_ops = &mv88e6352_avb_ops, 5193 .ptp_ops = &mv88e6352_ptp_ops, 5194 .phylink_get_caps = mv88e6351_phylink_get_caps, 5195 }; 5196 5197 static const struct mv88e6xxx_ops mv88e6352_ops = { 5198 /* MV88E6XXX_FAMILY_6352 */ 5199 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5200 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5201 .irl_init_all = mv88e6352_g2_irl_init_all, 5202 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5203 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5204 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5205 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5206 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5207 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5208 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5209 .port_set_link = mv88e6xxx_port_set_link, 5210 .port_sync_link = mv88e6xxx_port_sync_link, 5211 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5212 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5213 .port_tag_remap = mv88e6095_port_tag_remap, 5214 .port_set_policy = mv88e6352_port_set_policy, 5215 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5216 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5217 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5218 .port_set_ether_type = mv88e6351_port_set_ether_type, 5219 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5220 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5221 .port_pause_limit = mv88e6097_port_pause_limit, 5222 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5223 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5224 .port_get_cmode = mv88e6352_port_get_cmode, 5225 .port_setup_message_port = mv88e6xxx_setup_message_port, 5226 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5227 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5228 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5229 .stats_get_strings = mv88e6095_stats_get_strings, 5230 .stats_get_stats = mv88e6095_stats_get_stats, 5231 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5232 .set_egress_port = mv88e6095_g1_set_egress_port, 5233 .watchdog_ops = &mv88e6097_watchdog_ops, 5234 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5235 .pot_clear = mv88e6xxx_g2_pot_clear, 5236 .reset = mv88e6352_g1_reset, 5237 .rmu_disable = mv88e6352_g1_rmu_disable, 5238 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5239 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5240 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5241 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5242 .stu_getnext = mv88e6352_g1_stu_getnext, 5243 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5244 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5245 .gpio_ops = &mv88e6352_gpio_ops, 5246 .avb_ops = &mv88e6352_avb_ops, 5247 .ptp_ops = &mv88e6352_ptp_ops, 5248 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5249 .serdes_get_strings = mv88e6352_serdes_get_strings, 5250 .serdes_get_stats = mv88e6352_serdes_get_stats, 5251 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5252 .serdes_get_regs = mv88e6352_serdes_get_regs, 5253 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5254 .phylink_get_caps = mv88e6352_phylink_get_caps, 5255 .pcs_ops = &mv88e6352_pcs_ops, 5256 }; 5257 5258 static const struct mv88e6xxx_ops mv88e6390_ops = { 5259 /* MV88E6XXX_FAMILY_6390 */ 5260 .setup_errata = mv88e6390_setup_errata, 5261 .irl_init_all = mv88e6390_g2_irl_init_all, 5262 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5263 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5265 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5266 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5267 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5268 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5269 .port_set_link = mv88e6xxx_port_set_link, 5270 .port_sync_link = mv88e6xxx_port_sync_link, 5271 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5272 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5273 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5274 .port_tag_remap = mv88e6390_port_tag_remap, 5275 .port_set_policy = mv88e6352_port_set_policy, 5276 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5277 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5278 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5279 .port_set_ether_type = mv88e6351_port_set_ether_type, 5280 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5281 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5282 .port_pause_limit = mv88e6390_port_pause_limit, 5283 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5284 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5285 .port_get_cmode = mv88e6352_port_get_cmode, 5286 .port_set_cmode = mv88e6390_port_set_cmode, 5287 .port_setup_message_port = mv88e6xxx_setup_message_port, 5288 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5289 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5290 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5291 .stats_get_strings = mv88e6320_stats_get_strings, 5292 .stats_get_stats = mv88e6390_stats_get_stats, 5293 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5294 .set_egress_port = mv88e6390_g1_set_egress_port, 5295 .watchdog_ops = &mv88e6390_watchdog_ops, 5296 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5297 .pot_clear = mv88e6xxx_g2_pot_clear, 5298 .reset = mv88e6352_g1_reset, 5299 .rmu_disable = mv88e6390_g1_rmu_disable, 5300 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5301 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5302 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5303 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5304 .stu_getnext = mv88e6390_g1_stu_getnext, 5305 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5306 .serdes_get_lane = mv88e6390_serdes_get_lane, 5307 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5308 .gpio_ops = &mv88e6352_gpio_ops, 5309 .avb_ops = &mv88e6390_avb_ops, 5310 .ptp_ops = &mv88e6390_ptp_ops, 5311 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5312 .serdes_get_strings = mv88e6390_serdes_get_strings, 5313 .serdes_get_stats = mv88e6390_serdes_get_stats, 5314 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5315 .serdes_get_regs = mv88e6390_serdes_get_regs, 5316 .phylink_get_caps = mv88e6390_phylink_get_caps, 5317 .pcs_ops = &mv88e6390_pcs_ops, 5318 }; 5319 5320 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5321 /* MV88E6XXX_FAMILY_6390 */ 5322 .setup_errata = mv88e6390_setup_errata, 5323 .irl_init_all = mv88e6390_g2_irl_init_all, 5324 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5325 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5326 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5327 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5328 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5329 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5330 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5331 .port_set_link = mv88e6xxx_port_set_link, 5332 .port_sync_link = mv88e6xxx_port_sync_link, 5333 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5334 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5335 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5336 .port_tag_remap = mv88e6390_port_tag_remap, 5337 .port_set_policy = mv88e6352_port_set_policy, 5338 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5339 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5340 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5341 .port_set_ether_type = mv88e6351_port_set_ether_type, 5342 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5343 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5344 .port_pause_limit = mv88e6390_port_pause_limit, 5345 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5346 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5347 .port_get_cmode = mv88e6352_port_get_cmode, 5348 .port_set_cmode = mv88e6390x_port_set_cmode, 5349 .port_setup_message_port = mv88e6xxx_setup_message_port, 5350 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5351 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5352 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5353 .stats_get_strings = mv88e6320_stats_get_strings, 5354 .stats_get_stats = mv88e6390_stats_get_stats, 5355 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5356 .set_egress_port = mv88e6390_g1_set_egress_port, 5357 .watchdog_ops = &mv88e6390_watchdog_ops, 5358 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5359 .pot_clear = mv88e6xxx_g2_pot_clear, 5360 .reset = mv88e6352_g1_reset, 5361 .rmu_disable = mv88e6390_g1_rmu_disable, 5362 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5363 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5364 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5365 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5366 .stu_getnext = mv88e6390_g1_stu_getnext, 5367 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5368 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5369 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5370 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5371 .serdes_get_strings = mv88e6390_serdes_get_strings, 5372 .serdes_get_stats = mv88e6390_serdes_get_stats, 5373 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5374 .serdes_get_regs = mv88e6390_serdes_get_regs, 5375 .gpio_ops = &mv88e6352_gpio_ops, 5376 .avb_ops = &mv88e6390_avb_ops, 5377 .ptp_ops = &mv88e6390_ptp_ops, 5378 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5379 .pcs_ops = &mv88e6390_pcs_ops, 5380 }; 5381 5382 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5383 /* MV88E6XXX_FAMILY_6393 */ 5384 .irl_init_all = mv88e6390_g2_irl_init_all, 5385 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5386 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5387 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5388 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5389 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5390 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5391 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5392 .port_set_link = mv88e6xxx_port_set_link, 5393 .port_sync_link = mv88e6xxx_port_sync_link, 5394 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5395 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5396 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5397 .port_tag_remap = mv88e6390_port_tag_remap, 5398 .port_set_policy = mv88e6393x_port_set_policy, 5399 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5400 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5401 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5402 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5403 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5404 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5405 .port_pause_limit = mv88e6390_port_pause_limit, 5406 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5407 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5408 .port_get_cmode = mv88e6352_port_get_cmode, 5409 .port_set_cmode = mv88e6393x_port_set_cmode, 5410 .port_setup_message_port = mv88e6xxx_setup_message_port, 5411 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5412 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5413 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5414 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5415 .stats_get_strings = mv88e6320_stats_get_strings, 5416 .stats_get_stats = mv88e6390_stats_get_stats, 5417 /* .set_cpu_port is missing because this family does not support a global 5418 * CPU port, only per port CPU port which is set via 5419 * .port_set_upstream_port method. 5420 */ 5421 .set_egress_port = mv88e6393x_set_egress_port, 5422 .watchdog_ops = &mv88e6393x_watchdog_ops, 5423 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5424 .pot_clear = mv88e6xxx_g2_pot_clear, 5425 .reset = mv88e6352_g1_reset, 5426 .rmu_disable = mv88e6390_g1_rmu_disable, 5427 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5428 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5429 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5430 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5431 .stu_getnext = mv88e6390_g1_stu_getnext, 5432 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5433 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5434 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5435 /* TODO: serdes stats */ 5436 .gpio_ops = &mv88e6352_gpio_ops, 5437 .avb_ops = &mv88e6390_avb_ops, 5438 .ptp_ops = &mv88e6352_ptp_ops, 5439 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5440 .pcs_ops = &mv88e6393x_pcs_ops, 5441 }; 5442 5443 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5444 [MV88E6020] = { 5445 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5446 .family = MV88E6XXX_FAMILY_6250, 5447 .name = "Marvell 88E6020", 5448 .num_databases = 64, 5449 /* Ports 2-4 are not routed to pins 5450 * => usable ports 0, 1, 5, 6 5451 */ 5452 .num_ports = 7, 5453 .num_internal_phys = 2, 5454 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5455 .max_vid = 4095, 5456 .port_base_addr = 0x8, 5457 .phy_base_addr = 0x0, 5458 .global1_addr = 0xf, 5459 .global2_addr = 0x7, 5460 .age_time_coeff = 15000, 5461 .g1_irqs = 9, 5462 .g2_irqs = 5, 5463 .atu_move_port_mask = 0xf, 5464 .dual_chip = true, 5465 .ops = &mv88e6250_ops, 5466 }, 5467 5468 [MV88E6071] = { 5469 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5470 .family = MV88E6XXX_FAMILY_6250, 5471 .name = "Marvell 88E6071", 5472 .num_databases = 64, 5473 .num_ports = 7, 5474 .num_internal_phys = 5, 5475 .max_vid = 4095, 5476 .port_base_addr = 0x08, 5477 .phy_base_addr = 0x00, 5478 .global1_addr = 0x0f, 5479 .global2_addr = 0x07, 5480 .age_time_coeff = 15000, 5481 .g1_irqs = 9, 5482 .g2_irqs = 5, 5483 .atu_move_port_mask = 0xf, 5484 .dual_chip = true, 5485 .ops = &mv88e6250_ops, 5486 }, 5487 5488 [MV88E6085] = { 5489 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5490 .family = MV88E6XXX_FAMILY_6097, 5491 .name = "Marvell 88E6085", 5492 .num_databases = 4096, 5493 .num_macs = 8192, 5494 .num_ports = 10, 5495 .num_internal_phys = 5, 5496 .max_vid = 4095, 5497 .max_sid = 63, 5498 .port_base_addr = 0x10, 5499 .phy_base_addr = 0x0, 5500 .global1_addr = 0x1b, 5501 .global2_addr = 0x1c, 5502 .age_time_coeff = 15000, 5503 .g1_irqs = 8, 5504 .g2_irqs = 10, 5505 .atu_move_port_mask = 0xf, 5506 .pvt = true, 5507 .multi_chip = true, 5508 .ops = &mv88e6085_ops, 5509 }, 5510 5511 [MV88E6095] = { 5512 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5513 .family = MV88E6XXX_FAMILY_6095, 5514 .name = "Marvell 88E6095/88E6095F", 5515 .num_databases = 256, 5516 .num_macs = 8192, 5517 .num_ports = 11, 5518 .num_internal_phys = 0, 5519 .max_vid = 4095, 5520 .port_base_addr = 0x10, 5521 .phy_base_addr = 0x0, 5522 .global1_addr = 0x1b, 5523 .global2_addr = 0x1c, 5524 .age_time_coeff = 15000, 5525 .g1_irqs = 8, 5526 .atu_move_port_mask = 0xf, 5527 .multi_chip = true, 5528 .ops = &mv88e6095_ops, 5529 }, 5530 5531 [MV88E6097] = { 5532 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5533 .family = MV88E6XXX_FAMILY_6097, 5534 .name = "Marvell 88E6097/88E6097F", 5535 .num_databases = 4096, 5536 .num_macs = 8192, 5537 .num_ports = 11, 5538 .num_internal_phys = 8, 5539 .max_vid = 4095, 5540 .max_sid = 63, 5541 .port_base_addr = 0x10, 5542 .phy_base_addr = 0x0, 5543 .global1_addr = 0x1b, 5544 .global2_addr = 0x1c, 5545 .age_time_coeff = 15000, 5546 .g1_irqs = 8, 5547 .g2_irqs = 10, 5548 .atu_move_port_mask = 0xf, 5549 .pvt = true, 5550 .multi_chip = true, 5551 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5552 .ops = &mv88e6097_ops, 5553 }, 5554 5555 [MV88E6123] = { 5556 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5557 .family = MV88E6XXX_FAMILY_6165, 5558 .name = "Marvell 88E6123", 5559 .num_databases = 4096, 5560 .num_macs = 1024, 5561 .num_ports = 3, 5562 .num_internal_phys = 5, 5563 .max_vid = 4095, 5564 .max_sid = 63, 5565 .port_base_addr = 0x10, 5566 .phy_base_addr = 0x0, 5567 .global1_addr = 0x1b, 5568 .global2_addr = 0x1c, 5569 .age_time_coeff = 15000, 5570 .g1_irqs = 9, 5571 .g2_irqs = 10, 5572 .atu_move_port_mask = 0xf, 5573 .pvt = true, 5574 .multi_chip = true, 5575 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5576 .ops = &mv88e6123_ops, 5577 }, 5578 5579 [MV88E6131] = { 5580 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5581 .family = MV88E6XXX_FAMILY_6185, 5582 .name = "Marvell 88E6131", 5583 .num_databases = 256, 5584 .num_macs = 8192, 5585 .num_ports = 8, 5586 .num_internal_phys = 0, 5587 .max_vid = 4095, 5588 .port_base_addr = 0x10, 5589 .phy_base_addr = 0x0, 5590 .global1_addr = 0x1b, 5591 .global2_addr = 0x1c, 5592 .age_time_coeff = 15000, 5593 .g1_irqs = 9, 5594 .atu_move_port_mask = 0xf, 5595 .multi_chip = true, 5596 .ops = &mv88e6131_ops, 5597 }, 5598 5599 [MV88E6141] = { 5600 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5601 .family = MV88E6XXX_FAMILY_6341, 5602 .name = "Marvell 88E6141", 5603 .num_databases = 256, 5604 .num_macs = 2048, 5605 .num_ports = 6, 5606 .num_internal_phys = 5, 5607 .num_gpio = 11, 5608 .max_vid = 4095, 5609 .max_sid = 63, 5610 .port_base_addr = 0x10, 5611 .phy_base_addr = 0x10, 5612 .global1_addr = 0x1b, 5613 .global2_addr = 0x1c, 5614 .age_time_coeff = 3750, 5615 .atu_move_port_mask = 0x1f, 5616 .g1_irqs = 9, 5617 .g2_irqs = 10, 5618 .pvt = true, 5619 .multi_chip = true, 5620 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5621 .ops = &mv88e6141_ops, 5622 }, 5623 5624 [MV88E6161] = { 5625 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5626 .family = MV88E6XXX_FAMILY_6165, 5627 .name = "Marvell 88E6161", 5628 .num_databases = 4096, 5629 .num_macs = 1024, 5630 .num_ports = 6, 5631 .num_internal_phys = 5, 5632 .max_vid = 4095, 5633 .max_sid = 63, 5634 .port_base_addr = 0x10, 5635 .phy_base_addr = 0x0, 5636 .global1_addr = 0x1b, 5637 .global2_addr = 0x1c, 5638 .age_time_coeff = 15000, 5639 .g1_irqs = 9, 5640 .g2_irqs = 10, 5641 .atu_move_port_mask = 0xf, 5642 .pvt = true, 5643 .multi_chip = true, 5644 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5645 .ptp_support = true, 5646 .ops = &mv88e6161_ops, 5647 }, 5648 5649 [MV88E6165] = { 5650 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5651 .family = MV88E6XXX_FAMILY_6165, 5652 .name = "Marvell 88E6165", 5653 .num_databases = 4096, 5654 .num_macs = 8192, 5655 .num_ports = 6, 5656 .num_internal_phys = 0, 5657 .max_vid = 4095, 5658 .max_sid = 63, 5659 .port_base_addr = 0x10, 5660 .phy_base_addr = 0x0, 5661 .global1_addr = 0x1b, 5662 .global2_addr = 0x1c, 5663 .age_time_coeff = 15000, 5664 .g1_irqs = 9, 5665 .g2_irqs = 10, 5666 .atu_move_port_mask = 0xf, 5667 .pvt = true, 5668 .multi_chip = true, 5669 .ptp_support = true, 5670 .ops = &mv88e6165_ops, 5671 }, 5672 5673 [MV88E6171] = { 5674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5675 .family = MV88E6XXX_FAMILY_6351, 5676 .name = "Marvell 88E6171", 5677 .num_databases = 4096, 5678 .num_macs = 8192, 5679 .num_ports = 7, 5680 .num_internal_phys = 5, 5681 .max_vid = 4095, 5682 .max_sid = 63, 5683 .port_base_addr = 0x10, 5684 .phy_base_addr = 0x0, 5685 .global1_addr = 0x1b, 5686 .global2_addr = 0x1c, 5687 .age_time_coeff = 15000, 5688 .g1_irqs = 9, 5689 .g2_irqs = 10, 5690 .atu_move_port_mask = 0xf, 5691 .pvt = true, 5692 .multi_chip = true, 5693 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5694 .ops = &mv88e6171_ops, 5695 }, 5696 5697 [MV88E6172] = { 5698 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5699 .family = MV88E6XXX_FAMILY_6352, 5700 .name = "Marvell 88E6172", 5701 .num_databases = 4096, 5702 .num_macs = 8192, 5703 .num_ports = 7, 5704 .num_internal_phys = 5, 5705 .num_gpio = 15, 5706 .max_vid = 4095, 5707 .max_sid = 63, 5708 .port_base_addr = 0x10, 5709 .phy_base_addr = 0x0, 5710 .global1_addr = 0x1b, 5711 .global2_addr = 0x1c, 5712 .age_time_coeff = 15000, 5713 .g1_irqs = 9, 5714 .g2_irqs = 10, 5715 .atu_move_port_mask = 0xf, 5716 .pvt = true, 5717 .multi_chip = true, 5718 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5719 .ops = &mv88e6172_ops, 5720 }, 5721 5722 [MV88E6175] = { 5723 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5724 .family = MV88E6XXX_FAMILY_6351, 5725 .name = "Marvell 88E6175", 5726 .num_databases = 4096, 5727 .num_macs = 8192, 5728 .num_ports = 7, 5729 .num_internal_phys = 5, 5730 .max_vid = 4095, 5731 .max_sid = 63, 5732 .port_base_addr = 0x10, 5733 .phy_base_addr = 0x0, 5734 .global1_addr = 0x1b, 5735 .global2_addr = 0x1c, 5736 .age_time_coeff = 15000, 5737 .g1_irqs = 9, 5738 .g2_irqs = 10, 5739 .atu_move_port_mask = 0xf, 5740 .pvt = true, 5741 .multi_chip = true, 5742 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5743 .ops = &mv88e6175_ops, 5744 }, 5745 5746 [MV88E6176] = { 5747 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5748 .family = MV88E6XXX_FAMILY_6352, 5749 .name = "Marvell 88E6176", 5750 .num_databases = 4096, 5751 .num_macs = 8192, 5752 .num_ports = 7, 5753 .num_internal_phys = 5, 5754 .num_gpio = 15, 5755 .max_vid = 4095, 5756 .max_sid = 63, 5757 .port_base_addr = 0x10, 5758 .phy_base_addr = 0x0, 5759 .global1_addr = 0x1b, 5760 .global2_addr = 0x1c, 5761 .age_time_coeff = 15000, 5762 .g1_irqs = 9, 5763 .g2_irqs = 10, 5764 .atu_move_port_mask = 0xf, 5765 .pvt = true, 5766 .multi_chip = true, 5767 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5768 .ops = &mv88e6176_ops, 5769 }, 5770 5771 [MV88E6185] = { 5772 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5773 .family = MV88E6XXX_FAMILY_6185, 5774 .name = "Marvell 88E6185", 5775 .num_databases = 256, 5776 .num_macs = 8192, 5777 .num_ports = 10, 5778 .num_internal_phys = 0, 5779 .max_vid = 4095, 5780 .port_base_addr = 0x10, 5781 .phy_base_addr = 0x0, 5782 .global1_addr = 0x1b, 5783 .global2_addr = 0x1c, 5784 .age_time_coeff = 15000, 5785 .g1_irqs = 8, 5786 .atu_move_port_mask = 0xf, 5787 .multi_chip = true, 5788 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5789 .ops = &mv88e6185_ops, 5790 }, 5791 5792 [MV88E6190] = { 5793 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5794 .family = MV88E6XXX_FAMILY_6390, 5795 .name = "Marvell 88E6190", 5796 .num_databases = 4096, 5797 .num_macs = 16384, 5798 .num_ports = 11, /* 10 + Z80 */ 5799 .num_internal_phys = 9, 5800 .num_gpio = 16, 5801 .max_vid = 8191, 5802 .max_sid = 63, 5803 .port_base_addr = 0x0, 5804 .phy_base_addr = 0x0, 5805 .global1_addr = 0x1b, 5806 .global2_addr = 0x1c, 5807 .age_time_coeff = 3750, 5808 .g1_irqs = 9, 5809 .g2_irqs = 14, 5810 .pvt = true, 5811 .multi_chip = true, 5812 .atu_move_port_mask = 0x1f, 5813 .ops = &mv88e6190_ops, 5814 }, 5815 5816 [MV88E6190X] = { 5817 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5818 .family = MV88E6XXX_FAMILY_6390, 5819 .name = "Marvell 88E6190X", 5820 .num_databases = 4096, 5821 .num_macs = 16384, 5822 .num_ports = 11, /* 10 + Z80 */ 5823 .num_internal_phys = 9, 5824 .num_gpio = 16, 5825 .max_vid = 8191, 5826 .max_sid = 63, 5827 .port_base_addr = 0x0, 5828 .phy_base_addr = 0x0, 5829 .global1_addr = 0x1b, 5830 .global2_addr = 0x1c, 5831 .age_time_coeff = 3750, 5832 .g1_irqs = 9, 5833 .g2_irqs = 14, 5834 .atu_move_port_mask = 0x1f, 5835 .pvt = true, 5836 .multi_chip = true, 5837 .ops = &mv88e6190x_ops, 5838 }, 5839 5840 [MV88E6191] = { 5841 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5842 .family = MV88E6XXX_FAMILY_6390, 5843 .name = "Marvell 88E6191", 5844 .num_databases = 4096, 5845 .num_macs = 16384, 5846 .num_ports = 11, /* 10 + Z80 */ 5847 .num_internal_phys = 9, 5848 .max_vid = 8191, 5849 .max_sid = 63, 5850 .port_base_addr = 0x0, 5851 .phy_base_addr = 0x0, 5852 .global1_addr = 0x1b, 5853 .global2_addr = 0x1c, 5854 .age_time_coeff = 3750, 5855 .g1_irqs = 9, 5856 .g2_irqs = 14, 5857 .atu_move_port_mask = 0x1f, 5858 .pvt = true, 5859 .multi_chip = true, 5860 .ptp_support = true, 5861 .ops = &mv88e6191_ops, 5862 }, 5863 5864 [MV88E6191X] = { 5865 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5866 .family = MV88E6XXX_FAMILY_6393, 5867 .name = "Marvell 88E6191X", 5868 .num_databases = 4096, 5869 .num_ports = 11, /* 10 + Z80 */ 5870 .num_internal_phys = 8, 5871 .internal_phys_offset = 1, 5872 .max_vid = 8191, 5873 .max_sid = 63, 5874 .port_base_addr = 0x0, 5875 .phy_base_addr = 0x0, 5876 .global1_addr = 0x1b, 5877 .global2_addr = 0x1c, 5878 .age_time_coeff = 3750, 5879 .g1_irqs = 10, 5880 .g2_irqs = 14, 5881 .atu_move_port_mask = 0x1f, 5882 .pvt = true, 5883 .multi_chip = true, 5884 .ptp_support = true, 5885 .ops = &mv88e6393x_ops, 5886 }, 5887 5888 [MV88E6193X] = { 5889 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5890 .family = MV88E6XXX_FAMILY_6393, 5891 .name = "Marvell 88E6193X", 5892 .num_databases = 4096, 5893 .num_ports = 11, /* 10 + Z80 */ 5894 .num_internal_phys = 8, 5895 .internal_phys_offset = 1, 5896 .max_vid = 8191, 5897 .max_sid = 63, 5898 .port_base_addr = 0x0, 5899 .phy_base_addr = 0x0, 5900 .global1_addr = 0x1b, 5901 .global2_addr = 0x1c, 5902 .age_time_coeff = 3750, 5903 .g1_irqs = 10, 5904 .g2_irqs = 14, 5905 .atu_move_port_mask = 0x1f, 5906 .pvt = true, 5907 .multi_chip = true, 5908 .ptp_support = true, 5909 .ops = &mv88e6393x_ops, 5910 }, 5911 5912 [MV88E6220] = { 5913 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5914 .family = MV88E6XXX_FAMILY_6250, 5915 .name = "Marvell 88E6220", 5916 .num_databases = 64, 5917 5918 /* Ports 2-4 are not routed to pins 5919 * => usable ports 0, 1, 5, 6 5920 */ 5921 .num_ports = 7, 5922 .num_internal_phys = 2, 5923 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5924 .max_vid = 4095, 5925 .port_base_addr = 0x08, 5926 .phy_base_addr = 0x00, 5927 .global1_addr = 0x0f, 5928 .global2_addr = 0x07, 5929 .age_time_coeff = 15000, 5930 .g1_irqs = 9, 5931 .g2_irqs = 10, 5932 .atu_move_port_mask = 0xf, 5933 .dual_chip = true, 5934 .ptp_support = true, 5935 .ops = &mv88e6250_ops, 5936 }, 5937 5938 [MV88E6240] = { 5939 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5940 .family = MV88E6XXX_FAMILY_6352, 5941 .name = "Marvell 88E6240", 5942 .num_databases = 4096, 5943 .num_macs = 8192, 5944 .num_ports = 7, 5945 .num_internal_phys = 5, 5946 .num_gpio = 15, 5947 .max_vid = 4095, 5948 .max_sid = 63, 5949 .port_base_addr = 0x10, 5950 .phy_base_addr = 0x0, 5951 .global1_addr = 0x1b, 5952 .global2_addr = 0x1c, 5953 .age_time_coeff = 15000, 5954 .g1_irqs = 9, 5955 .g2_irqs = 10, 5956 .atu_move_port_mask = 0xf, 5957 .pvt = true, 5958 .multi_chip = true, 5959 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5960 .ptp_support = true, 5961 .ops = &mv88e6240_ops, 5962 }, 5963 5964 [MV88E6250] = { 5965 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5966 .family = MV88E6XXX_FAMILY_6250, 5967 .name = "Marvell 88E6250", 5968 .num_databases = 64, 5969 .num_ports = 7, 5970 .num_internal_phys = 5, 5971 .max_vid = 4095, 5972 .port_base_addr = 0x08, 5973 .phy_base_addr = 0x00, 5974 .global1_addr = 0x0f, 5975 .global2_addr = 0x07, 5976 .age_time_coeff = 15000, 5977 .g1_irqs = 9, 5978 .g2_irqs = 10, 5979 .atu_move_port_mask = 0xf, 5980 .dual_chip = true, 5981 .ptp_support = true, 5982 .ops = &mv88e6250_ops, 5983 }, 5984 5985 [MV88E6290] = { 5986 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5987 .family = MV88E6XXX_FAMILY_6390, 5988 .name = "Marvell 88E6290", 5989 .num_databases = 4096, 5990 .num_ports = 11, /* 10 + Z80 */ 5991 .num_internal_phys = 9, 5992 .num_gpio = 16, 5993 .max_vid = 8191, 5994 .max_sid = 63, 5995 .port_base_addr = 0x0, 5996 .phy_base_addr = 0x0, 5997 .global1_addr = 0x1b, 5998 .global2_addr = 0x1c, 5999 .age_time_coeff = 3750, 6000 .g1_irqs = 9, 6001 .g2_irqs = 14, 6002 .atu_move_port_mask = 0x1f, 6003 .pvt = true, 6004 .multi_chip = true, 6005 .ptp_support = true, 6006 .ops = &mv88e6290_ops, 6007 }, 6008 6009 [MV88E6320] = { 6010 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6011 .family = MV88E6XXX_FAMILY_6320, 6012 .name = "Marvell 88E6320", 6013 .num_databases = 4096, 6014 .num_macs = 8192, 6015 .num_ports = 7, 6016 .num_internal_phys = 5, 6017 .num_gpio = 15, 6018 .max_vid = 4095, 6019 .port_base_addr = 0x10, 6020 .phy_base_addr = 0x0, 6021 .global1_addr = 0x1b, 6022 .global2_addr = 0x1c, 6023 .age_time_coeff = 15000, 6024 .g1_irqs = 8, 6025 .g2_irqs = 10, 6026 .atu_move_port_mask = 0xf, 6027 .pvt = true, 6028 .multi_chip = true, 6029 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6030 .ptp_support = true, 6031 .ops = &mv88e6320_ops, 6032 }, 6033 6034 [MV88E6321] = { 6035 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6036 .family = MV88E6XXX_FAMILY_6320, 6037 .name = "Marvell 88E6321", 6038 .num_databases = 4096, 6039 .num_macs = 8192, 6040 .num_ports = 7, 6041 .num_internal_phys = 5, 6042 .num_gpio = 15, 6043 .max_vid = 4095, 6044 .port_base_addr = 0x10, 6045 .phy_base_addr = 0x0, 6046 .global1_addr = 0x1b, 6047 .global2_addr = 0x1c, 6048 .age_time_coeff = 15000, 6049 .g1_irqs = 8, 6050 .g2_irqs = 10, 6051 .atu_move_port_mask = 0xf, 6052 .multi_chip = true, 6053 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6054 .ptp_support = true, 6055 .ops = &mv88e6321_ops, 6056 }, 6057 6058 [MV88E6341] = { 6059 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6060 .family = MV88E6XXX_FAMILY_6341, 6061 .name = "Marvell 88E6341", 6062 .num_databases = 256, 6063 .num_macs = 2048, 6064 .num_internal_phys = 5, 6065 .num_ports = 6, 6066 .num_gpio = 11, 6067 .max_vid = 4095, 6068 .max_sid = 63, 6069 .port_base_addr = 0x10, 6070 .phy_base_addr = 0x10, 6071 .global1_addr = 0x1b, 6072 .global2_addr = 0x1c, 6073 .age_time_coeff = 3750, 6074 .atu_move_port_mask = 0x1f, 6075 .g1_irqs = 9, 6076 .g2_irqs = 10, 6077 .pvt = true, 6078 .multi_chip = true, 6079 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6080 .ptp_support = true, 6081 .ops = &mv88e6341_ops, 6082 }, 6083 6084 [MV88E6350] = { 6085 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6086 .family = MV88E6XXX_FAMILY_6351, 6087 .name = "Marvell 88E6350", 6088 .num_databases = 4096, 6089 .num_macs = 8192, 6090 .num_ports = 7, 6091 .num_internal_phys = 5, 6092 .max_vid = 4095, 6093 .max_sid = 63, 6094 .port_base_addr = 0x10, 6095 .phy_base_addr = 0x0, 6096 .global1_addr = 0x1b, 6097 .global2_addr = 0x1c, 6098 .age_time_coeff = 15000, 6099 .g1_irqs = 9, 6100 .g2_irqs = 10, 6101 .atu_move_port_mask = 0xf, 6102 .pvt = true, 6103 .multi_chip = true, 6104 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6105 .ops = &mv88e6350_ops, 6106 }, 6107 6108 [MV88E6351] = { 6109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6110 .family = MV88E6XXX_FAMILY_6351, 6111 .name = "Marvell 88E6351", 6112 .num_databases = 4096, 6113 .num_macs = 8192, 6114 .num_ports = 7, 6115 .num_internal_phys = 5, 6116 .max_vid = 4095, 6117 .max_sid = 63, 6118 .port_base_addr = 0x10, 6119 .phy_base_addr = 0x0, 6120 .global1_addr = 0x1b, 6121 .global2_addr = 0x1c, 6122 .age_time_coeff = 15000, 6123 .g1_irqs = 9, 6124 .g2_irqs = 10, 6125 .atu_move_port_mask = 0xf, 6126 .pvt = true, 6127 .multi_chip = true, 6128 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6129 .ops = &mv88e6351_ops, 6130 }, 6131 6132 [MV88E6352] = { 6133 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6134 .family = MV88E6XXX_FAMILY_6352, 6135 .name = "Marvell 88E6352", 6136 .num_databases = 4096, 6137 .num_macs = 8192, 6138 .num_ports = 7, 6139 .num_internal_phys = 5, 6140 .num_gpio = 15, 6141 .max_vid = 4095, 6142 .max_sid = 63, 6143 .port_base_addr = 0x10, 6144 .phy_base_addr = 0x0, 6145 .global1_addr = 0x1b, 6146 .global2_addr = 0x1c, 6147 .age_time_coeff = 15000, 6148 .g1_irqs = 9, 6149 .g2_irqs = 10, 6150 .atu_move_port_mask = 0xf, 6151 .pvt = true, 6152 .multi_chip = true, 6153 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6154 .ptp_support = true, 6155 .ops = &mv88e6352_ops, 6156 }, 6157 [MV88E6361] = { 6158 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6159 .family = MV88E6XXX_FAMILY_6393, 6160 .name = "Marvell 88E6361", 6161 .num_databases = 4096, 6162 .num_macs = 16384, 6163 .num_ports = 11, 6164 /* Ports 1, 2 and 8 are not routed */ 6165 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6166 .num_internal_phys = 5, 6167 .internal_phys_offset = 3, 6168 .max_vid = 4095, 6169 .max_sid = 63, 6170 .port_base_addr = 0x0, 6171 .phy_base_addr = 0x0, 6172 .global1_addr = 0x1b, 6173 .global2_addr = 0x1c, 6174 .age_time_coeff = 3750, 6175 .g1_irqs = 10, 6176 .g2_irqs = 14, 6177 .atu_move_port_mask = 0x1f, 6178 .pvt = true, 6179 .multi_chip = true, 6180 .ptp_support = true, 6181 .ops = &mv88e6393x_ops, 6182 }, 6183 [MV88E6390] = { 6184 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6185 .family = MV88E6XXX_FAMILY_6390, 6186 .name = "Marvell 88E6390", 6187 .num_databases = 4096, 6188 .num_macs = 16384, 6189 .num_ports = 11, /* 10 + Z80 */ 6190 .num_internal_phys = 9, 6191 .num_gpio = 16, 6192 .max_vid = 8191, 6193 .max_sid = 63, 6194 .port_base_addr = 0x0, 6195 .phy_base_addr = 0x0, 6196 .global1_addr = 0x1b, 6197 .global2_addr = 0x1c, 6198 .age_time_coeff = 3750, 6199 .g1_irqs = 9, 6200 .g2_irqs = 14, 6201 .atu_move_port_mask = 0x1f, 6202 .pvt = true, 6203 .multi_chip = true, 6204 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6205 .ptp_support = true, 6206 .ops = &mv88e6390_ops, 6207 }, 6208 [MV88E6390X] = { 6209 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6210 .family = MV88E6XXX_FAMILY_6390, 6211 .name = "Marvell 88E6390X", 6212 .num_databases = 4096, 6213 .num_macs = 16384, 6214 .num_ports = 11, /* 10 + Z80 */ 6215 .num_internal_phys = 9, 6216 .num_gpio = 16, 6217 .max_vid = 8191, 6218 .max_sid = 63, 6219 .port_base_addr = 0x0, 6220 .phy_base_addr = 0x0, 6221 .global1_addr = 0x1b, 6222 .global2_addr = 0x1c, 6223 .age_time_coeff = 3750, 6224 .g1_irqs = 9, 6225 .g2_irqs = 14, 6226 .atu_move_port_mask = 0x1f, 6227 .pvt = true, 6228 .multi_chip = true, 6229 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6230 .ptp_support = true, 6231 .ops = &mv88e6390x_ops, 6232 }, 6233 6234 [MV88E6393X] = { 6235 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6236 .family = MV88E6XXX_FAMILY_6393, 6237 .name = "Marvell 88E6393X", 6238 .num_databases = 4096, 6239 .num_ports = 11, /* 10 + Z80 */ 6240 .num_internal_phys = 8, 6241 .internal_phys_offset = 1, 6242 .max_vid = 8191, 6243 .max_sid = 63, 6244 .port_base_addr = 0x0, 6245 .phy_base_addr = 0x0, 6246 .global1_addr = 0x1b, 6247 .global2_addr = 0x1c, 6248 .age_time_coeff = 3750, 6249 .g1_irqs = 10, 6250 .g2_irqs = 14, 6251 .atu_move_port_mask = 0x1f, 6252 .pvt = true, 6253 .multi_chip = true, 6254 .ptp_support = true, 6255 .ops = &mv88e6393x_ops, 6256 }, 6257 }; 6258 6259 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6260 { 6261 int i; 6262 6263 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6264 if (mv88e6xxx_table[i].prod_num == prod_num) 6265 return &mv88e6xxx_table[i]; 6266 6267 return NULL; 6268 } 6269 6270 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6271 { 6272 const struct mv88e6xxx_info *info; 6273 unsigned int prod_num, rev; 6274 u16 id; 6275 int err; 6276 6277 mv88e6xxx_reg_lock(chip); 6278 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6279 mv88e6xxx_reg_unlock(chip); 6280 if (err) 6281 return err; 6282 6283 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6284 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6285 6286 info = mv88e6xxx_lookup_info(prod_num); 6287 if (!info) 6288 return -ENODEV; 6289 6290 /* Update the compatible info with the probed one */ 6291 chip->info = info; 6292 6293 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6294 chip->info->prod_num, chip->info->name, rev); 6295 6296 return 0; 6297 } 6298 6299 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6300 struct mdio_device *mdiodev) 6301 { 6302 int err; 6303 6304 /* dual_chip takes precedence over single/multi-chip modes */ 6305 if (chip->info->dual_chip) 6306 return -EINVAL; 6307 6308 /* If the mdio addr is 16 indicating the first port address of a switch 6309 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6310 * configured in single chip addressing mode. Setup the smi access as 6311 * single chip addressing mode and attempt to detect the model of the 6312 * switch, if this fails the device is not configured in single chip 6313 * addressing mode. 6314 */ 6315 if (mdiodev->addr != 16) 6316 return -EINVAL; 6317 6318 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6319 if (err) 6320 return err; 6321 6322 return mv88e6xxx_detect(chip); 6323 } 6324 6325 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6326 { 6327 struct mv88e6xxx_chip *chip; 6328 6329 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6330 if (!chip) 6331 return NULL; 6332 6333 chip->dev = dev; 6334 6335 mutex_init(&chip->reg_lock); 6336 INIT_LIST_HEAD(&chip->mdios); 6337 idr_init(&chip->policies); 6338 INIT_LIST_HEAD(&chip->msts); 6339 6340 return chip; 6341 } 6342 6343 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6344 int port, 6345 enum dsa_tag_protocol m) 6346 { 6347 struct mv88e6xxx_chip *chip = ds->priv; 6348 6349 return chip->tag_protocol; 6350 } 6351 6352 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6353 enum dsa_tag_protocol proto) 6354 { 6355 struct mv88e6xxx_chip *chip = ds->priv; 6356 enum dsa_tag_protocol old_protocol; 6357 struct dsa_port *cpu_dp; 6358 int err; 6359 6360 switch (proto) { 6361 case DSA_TAG_PROTO_EDSA: 6362 switch (chip->info->edsa_support) { 6363 case MV88E6XXX_EDSA_UNSUPPORTED: 6364 return -EPROTONOSUPPORT; 6365 case MV88E6XXX_EDSA_UNDOCUMENTED: 6366 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6367 fallthrough; 6368 case MV88E6XXX_EDSA_SUPPORTED: 6369 break; 6370 } 6371 break; 6372 case DSA_TAG_PROTO_DSA: 6373 break; 6374 default: 6375 return -EPROTONOSUPPORT; 6376 } 6377 6378 old_protocol = chip->tag_protocol; 6379 chip->tag_protocol = proto; 6380 6381 mv88e6xxx_reg_lock(chip); 6382 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6383 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6384 if (err) { 6385 mv88e6xxx_reg_unlock(chip); 6386 goto unwind; 6387 } 6388 } 6389 mv88e6xxx_reg_unlock(chip); 6390 6391 return 0; 6392 6393 unwind: 6394 chip->tag_protocol = old_protocol; 6395 6396 mv88e6xxx_reg_lock(chip); 6397 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6398 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6399 mv88e6xxx_reg_unlock(chip); 6400 6401 return err; 6402 } 6403 6404 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6405 const struct switchdev_obj_port_mdb *mdb, 6406 struct dsa_db db) 6407 { 6408 struct mv88e6xxx_chip *chip = ds->priv; 6409 int err; 6410 6411 mv88e6xxx_reg_lock(chip); 6412 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6413 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6414 mv88e6xxx_reg_unlock(chip); 6415 6416 return err; 6417 } 6418 6419 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6420 const struct switchdev_obj_port_mdb *mdb, 6421 struct dsa_db db) 6422 { 6423 struct mv88e6xxx_chip *chip = ds->priv; 6424 int err; 6425 6426 mv88e6xxx_reg_lock(chip); 6427 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6428 mv88e6xxx_reg_unlock(chip); 6429 6430 return err; 6431 } 6432 6433 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6434 struct dsa_mall_mirror_tc_entry *mirror, 6435 bool ingress, 6436 struct netlink_ext_ack *extack) 6437 { 6438 enum mv88e6xxx_egress_direction direction = ingress ? 6439 MV88E6XXX_EGRESS_DIR_INGRESS : 6440 MV88E6XXX_EGRESS_DIR_EGRESS; 6441 struct mv88e6xxx_chip *chip = ds->priv; 6442 bool other_mirrors = false; 6443 int i; 6444 int err; 6445 6446 mutex_lock(&chip->reg_lock); 6447 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6448 mirror->to_local_port) { 6449 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6450 other_mirrors |= ingress ? 6451 chip->ports[i].mirror_ingress : 6452 chip->ports[i].mirror_egress; 6453 6454 /* Can't change egress port when other mirror is active */ 6455 if (other_mirrors) { 6456 err = -EBUSY; 6457 goto out; 6458 } 6459 6460 err = mv88e6xxx_set_egress_port(chip, direction, 6461 mirror->to_local_port); 6462 if (err) 6463 goto out; 6464 } 6465 6466 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6467 out: 6468 mutex_unlock(&chip->reg_lock); 6469 6470 return err; 6471 } 6472 6473 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6474 struct dsa_mall_mirror_tc_entry *mirror) 6475 { 6476 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6477 MV88E6XXX_EGRESS_DIR_INGRESS : 6478 MV88E6XXX_EGRESS_DIR_EGRESS; 6479 struct mv88e6xxx_chip *chip = ds->priv; 6480 bool other_mirrors = false; 6481 int i; 6482 6483 mutex_lock(&chip->reg_lock); 6484 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6485 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6486 6487 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6488 other_mirrors |= mirror->ingress ? 6489 chip->ports[i].mirror_ingress : 6490 chip->ports[i].mirror_egress; 6491 6492 /* Reset egress port when no other mirror is active */ 6493 if (!other_mirrors) { 6494 if (mv88e6xxx_set_egress_port(chip, direction, 6495 dsa_upstream_port(ds, port))) 6496 dev_err(ds->dev, "failed to set egress port\n"); 6497 } 6498 6499 mutex_unlock(&chip->reg_lock); 6500 } 6501 6502 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6503 struct switchdev_brport_flags flags, 6504 struct netlink_ext_ack *extack) 6505 { 6506 struct mv88e6xxx_chip *chip = ds->priv; 6507 const struct mv88e6xxx_ops *ops; 6508 6509 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6510 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6511 return -EINVAL; 6512 6513 ops = chip->info->ops; 6514 6515 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6516 return -EINVAL; 6517 6518 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6519 return -EINVAL; 6520 6521 return 0; 6522 } 6523 6524 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6525 struct switchdev_brport_flags flags, 6526 struct netlink_ext_ack *extack) 6527 { 6528 struct mv88e6xxx_chip *chip = ds->priv; 6529 int err = 0; 6530 6531 mv88e6xxx_reg_lock(chip); 6532 6533 if (flags.mask & BR_LEARNING) { 6534 bool learning = !!(flags.val & BR_LEARNING); 6535 u16 pav = learning ? (1 << port) : 0; 6536 6537 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6538 if (err) 6539 goto out; 6540 } 6541 6542 if (flags.mask & BR_FLOOD) { 6543 bool unicast = !!(flags.val & BR_FLOOD); 6544 6545 err = chip->info->ops->port_set_ucast_flood(chip, port, 6546 unicast); 6547 if (err) 6548 goto out; 6549 } 6550 6551 if (flags.mask & BR_MCAST_FLOOD) { 6552 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6553 6554 err = chip->info->ops->port_set_mcast_flood(chip, port, 6555 multicast); 6556 if (err) 6557 goto out; 6558 } 6559 6560 if (flags.mask & BR_BCAST_FLOOD) { 6561 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6562 6563 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6564 if (err) 6565 goto out; 6566 } 6567 6568 if (flags.mask & BR_PORT_MAB) { 6569 bool mab = !!(flags.val & BR_PORT_MAB); 6570 6571 mv88e6xxx_port_set_mab(chip, port, mab); 6572 } 6573 6574 if (flags.mask & BR_PORT_LOCKED) { 6575 bool locked = !!(flags.val & BR_PORT_LOCKED); 6576 6577 err = mv88e6xxx_port_set_lock(chip, port, locked); 6578 if (err) 6579 goto out; 6580 } 6581 out: 6582 mv88e6xxx_reg_unlock(chip); 6583 6584 return err; 6585 } 6586 6587 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6588 struct dsa_lag lag, 6589 struct netdev_lag_upper_info *info, 6590 struct netlink_ext_ack *extack) 6591 { 6592 struct mv88e6xxx_chip *chip = ds->priv; 6593 struct dsa_port *dp; 6594 int members = 0; 6595 6596 if (!mv88e6xxx_has_lag(chip)) { 6597 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6598 return false; 6599 } 6600 6601 if (!lag.id) 6602 return false; 6603 6604 dsa_lag_foreach_port(dp, ds->dst, &lag) 6605 /* Includes the port joining the LAG */ 6606 members++; 6607 6608 if (members > 8) { 6609 NL_SET_ERR_MSG_MOD(extack, 6610 "Cannot offload more than 8 LAG ports"); 6611 return false; 6612 } 6613 6614 /* We could potentially relax this to include active 6615 * backup in the future. 6616 */ 6617 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6618 NL_SET_ERR_MSG_MOD(extack, 6619 "Can only offload LAG using hash TX type"); 6620 return false; 6621 } 6622 6623 /* Ideally we would also validate that the hash type matches 6624 * the hardware. Alas, this is always set to unknown on team 6625 * interfaces. 6626 */ 6627 return true; 6628 } 6629 6630 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6631 { 6632 struct mv88e6xxx_chip *chip = ds->priv; 6633 struct dsa_port *dp; 6634 u16 map = 0; 6635 int id; 6636 6637 /* DSA LAG IDs are one-based, hardware is zero-based */ 6638 id = lag.id - 1; 6639 6640 /* Build the map of all ports to distribute flows destined for 6641 * this LAG. This can be either a local user port, or a DSA 6642 * port if the LAG port is on a remote chip. 6643 */ 6644 dsa_lag_foreach_port(dp, ds->dst, &lag) 6645 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6646 6647 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6648 } 6649 6650 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6651 /* Row number corresponds to the number of active members in a 6652 * LAG. Each column states which of the eight hash buckets are 6653 * mapped to the column:th port in the LAG. 6654 * 6655 * Example: In a LAG with three active ports, the second port 6656 * ([2][1]) would be selected for traffic mapped to buckets 6657 * 3,4,5 (0x38). 6658 */ 6659 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6660 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6661 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6662 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6663 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6664 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6665 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6666 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6667 }; 6668 6669 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6670 int num_tx, int nth) 6671 { 6672 u8 active = 0; 6673 int i; 6674 6675 num_tx = num_tx <= 8 ? num_tx : 8; 6676 if (nth < num_tx) 6677 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6678 6679 for (i = 0; i < 8; i++) { 6680 if (BIT(i) & active) 6681 mask[i] |= BIT(port); 6682 } 6683 } 6684 6685 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6686 { 6687 struct mv88e6xxx_chip *chip = ds->priv; 6688 unsigned int id, num_tx; 6689 struct dsa_port *dp; 6690 struct dsa_lag *lag; 6691 int i, err, nth; 6692 u16 mask[8]; 6693 u16 ivec; 6694 6695 /* Assume no port is a member of any LAG. */ 6696 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6697 6698 /* Disable all masks for ports that _are_ members of a LAG. */ 6699 dsa_switch_for_each_port(dp, ds) { 6700 if (!dp->lag) 6701 continue; 6702 6703 ivec &= ~BIT(dp->index); 6704 } 6705 6706 for (i = 0; i < 8; i++) 6707 mask[i] = ivec; 6708 6709 /* Enable the correct subset of masks for all LAG ports that 6710 * are in the Tx set. 6711 */ 6712 dsa_lags_foreach_id(id, ds->dst) { 6713 lag = dsa_lag_by_id(ds->dst, id); 6714 if (!lag) 6715 continue; 6716 6717 num_tx = 0; 6718 dsa_lag_foreach_port(dp, ds->dst, lag) { 6719 if (dp->lag_tx_enabled) 6720 num_tx++; 6721 } 6722 6723 if (!num_tx) 6724 continue; 6725 6726 nth = 0; 6727 dsa_lag_foreach_port(dp, ds->dst, lag) { 6728 if (!dp->lag_tx_enabled) 6729 continue; 6730 6731 if (dp->ds == ds) 6732 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6733 num_tx, nth); 6734 6735 nth++; 6736 } 6737 } 6738 6739 for (i = 0; i < 8; i++) { 6740 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6741 if (err) 6742 return err; 6743 } 6744 6745 return 0; 6746 } 6747 6748 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6749 struct dsa_lag lag) 6750 { 6751 int err; 6752 6753 err = mv88e6xxx_lag_sync_masks(ds); 6754 6755 if (!err) 6756 err = mv88e6xxx_lag_sync_map(ds, lag); 6757 6758 return err; 6759 } 6760 6761 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6762 { 6763 struct mv88e6xxx_chip *chip = ds->priv; 6764 int err; 6765 6766 mv88e6xxx_reg_lock(chip); 6767 err = mv88e6xxx_lag_sync_masks(ds); 6768 mv88e6xxx_reg_unlock(chip); 6769 return err; 6770 } 6771 6772 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6773 struct dsa_lag lag, 6774 struct netdev_lag_upper_info *info, 6775 struct netlink_ext_ack *extack) 6776 { 6777 struct mv88e6xxx_chip *chip = ds->priv; 6778 int err, id; 6779 6780 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6781 return -EOPNOTSUPP; 6782 6783 /* DSA LAG IDs are one-based */ 6784 id = lag.id - 1; 6785 6786 mv88e6xxx_reg_lock(chip); 6787 6788 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6789 if (err) 6790 goto err_unlock; 6791 6792 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6793 if (err) 6794 goto err_clear_trunk; 6795 6796 mv88e6xxx_reg_unlock(chip); 6797 return 0; 6798 6799 err_clear_trunk: 6800 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6801 err_unlock: 6802 mv88e6xxx_reg_unlock(chip); 6803 return err; 6804 } 6805 6806 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6807 struct dsa_lag lag) 6808 { 6809 struct mv88e6xxx_chip *chip = ds->priv; 6810 int err_sync, err_trunk; 6811 6812 mv88e6xxx_reg_lock(chip); 6813 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6814 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6815 mv88e6xxx_reg_unlock(chip); 6816 return err_sync ? : err_trunk; 6817 } 6818 6819 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6820 int port) 6821 { 6822 struct mv88e6xxx_chip *chip = ds->priv; 6823 int err; 6824 6825 mv88e6xxx_reg_lock(chip); 6826 err = mv88e6xxx_lag_sync_masks(ds); 6827 mv88e6xxx_reg_unlock(chip); 6828 return err; 6829 } 6830 6831 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6832 int port, struct dsa_lag lag, 6833 struct netdev_lag_upper_info *info, 6834 struct netlink_ext_ack *extack) 6835 { 6836 struct mv88e6xxx_chip *chip = ds->priv; 6837 int err; 6838 6839 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6840 return -EOPNOTSUPP; 6841 6842 mv88e6xxx_reg_lock(chip); 6843 6844 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6845 if (err) 6846 goto unlock; 6847 6848 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6849 6850 unlock: 6851 mv88e6xxx_reg_unlock(chip); 6852 return err; 6853 } 6854 6855 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6856 int port, struct dsa_lag lag) 6857 { 6858 struct mv88e6xxx_chip *chip = ds->priv; 6859 int err_sync, err_pvt; 6860 6861 mv88e6xxx_reg_lock(chip); 6862 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6863 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6864 mv88e6xxx_reg_unlock(chip); 6865 return err_sync ? : err_pvt; 6866 } 6867 6868 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6869 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6870 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6871 .setup = mv88e6xxx_setup, 6872 .teardown = mv88e6xxx_teardown, 6873 .port_setup = mv88e6xxx_port_setup, 6874 .port_teardown = mv88e6xxx_port_teardown, 6875 .phylink_get_caps = mv88e6xxx_get_caps, 6876 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs, 6877 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 6878 .phylink_mac_config = mv88e6xxx_mac_config, 6879 .phylink_mac_finish = mv88e6xxx_mac_finish, 6880 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6881 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6882 .get_strings = mv88e6xxx_get_strings, 6883 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6884 .get_sset_count = mv88e6xxx_get_sset_count, 6885 .port_max_mtu = mv88e6xxx_get_max_mtu, 6886 .port_change_mtu = mv88e6xxx_change_mtu, 6887 .get_mac_eee = mv88e6xxx_get_mac_eee, 6888 .set_mac_eee = mv88e6xxx_set_mac_eee, 6889 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6890 .get_eeprom = mv88e6xxx_get_eeprom, 6891 .set_eeprom = mv88e6xxx_set_eeprom, 6892 .get_regs_len = mv88e6xxx_get_regs_len, 6893 .get_regs = mv88e6xxx_get_regs, 6894 .get_rxnfc = mv88e6xxx_get_rxnfc, 6895 .set_rxnfc = mv88e6xxx_set_rxnfc, 6896 .set_ageing_time = mv88e6xxx_set_ageing_time, 6897 .port_bridge_join = mv88e6xxx_port_bridge_join, 6898 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6899 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6900 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6901 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6902 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6903 .port_fast_age = mv88e6xxx_port_fast_age, 6904 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6905 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6906 .port_vlan_add = mv88e6xxx_port_vlan_add, 6907 .port_vlan_del = mv88e6xxx_port_vlan_del, 6908 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6909 .port_fdb_add = mv88e6xxx_port_fdb_add, 6910 .port_fdb_del = mv88e6xxx_port_fdb_del, 6911 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6912 .port_mdb_add = mv88e6xxx_port_mdb_add, 6913 .port_mdb_del = mv88e6xxx_port_mdb_del, 6914 .port_mirror_add = mv88e6xxx_port_mirror_add, 6915 .port_mirror_del = mv88e6xxx_port_mirror_del, 6916 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6917 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6918 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6919 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6920 .port_txtstamp = mv88e6xxx_port_txtstamp, 6921 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6922 .get_ts_info = mv88e6xxx_get_ts_info, 6923 .devlink_param_get = mv88e6xxx_devlink_param_get, 6924 .devlink_param_set = mv88e6xxx_devlink_param_set, 6925 .devlink_info_get = mv88e6xxx_devlink_info_get, 6926 .port_lag_change = mv88e6xxx_port_lag_change, 6927 .port_lag_join = mv88e6xxx_port_lag_join, 6928 .port_lag_leave = mv88e6xxx_port_lag_leave, 6929 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6930 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6931 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6932 }; 6933 6934 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6935 { 6936 struct device *dev = chip->dev; 6937 struct dsa_switch *ds; 6938 6939 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6940 if (!ds) 6941 return -ENOMEM; 6942 6943 ds->dev = dev; 6944 ds->num_ports = mv88e6xxx_num_ports(chip); 6945 ds->priv = chip; 6946 ds->dev = dev; 6947 ds->ops = &mv88e6xxx_switch_ops; 6948 ds->ageing_time_min = chip->info->age_time_coeff; 6949 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6950 6951 /* Some chips support up to 32, but that requires enabling the 6952 * 5-bit port mode, which we do not support. 640k^W16 ought to 6953 * be enough for anyone. 6954 */ 6955 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6956 6957 dev_set_drvdata(dev, ds); 6958 6959 return dsa_register_switch(ds); 6960 } 6961 6962 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6963 { 6964 dsa_unregister_switch(chip->ds); 6965 } 6966 6967 static const void *pdata_device_get_match_data(struct device *dev) 6968 { 6969 const struct of_device_id *matches = dev->driver->of_match_table; 6970 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6971 6972 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6973 matches++) { 6974 if (!strcmp(pdata->compatible, matches->compatible)) 6975 return matches->data; 6976 } 6977 return NULL; 6978 } 6979 6980 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6981 * would be lost after a power cycle so prevent it to be suspended. 6982 */ 6983 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6984 { 6985 return -EOPNOTSUPP; 6986 } 6987 6988 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6989 { 6990 return 0; 6991 } 6992 6993 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6994 6995 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6996 { 6997 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6998 const struct mv88e6xxx_info *compat_info = NULL; 6999 struct device *dev = &mdiodev->dev; 7000 struct device_node *np = dev->of_node; 7001 struct mv88e6xxx_chip *chip; 7002 int port; 7003 int err; 7004 7005 if (!np && !pdata) 7006 return -EINVAL; 7007 7008 if (np) 7009 compat_info = of_device_get_match_data(dev); 7010 7011 if (pdata) { 7012 compat_info = pdata_device_get_match_data(dev); 7013 7014 if (!pdata->netdev) 7015 return -EINVAL; 7016 7017 for (port = 0; port < DSA_MAX_PORTS; port++) { 7018 if (!(pdata->enabled_ports & (1 << port))) 7019 continue; 7020 if (strcmp(pdata->cd.port_names[port], "cpu")) 7021 continue; 7022 pdata->cd.netdev[port] = &pdata->netdev->dev; 7023 break; 7024 } 7025 } 7026 7027 if (!compat_info) 7028 return -EINVAL; 7029 7030 chip = mv88e6xxx_alloc_chip(dev); 7031 if (!chip) { 7032 err = -ENOMEM; 7033 goto out; 7034 } 7035 7036 chip->info = compat_info; 7037 7038 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7039 if (IS_ERR(chip->reset)) { 7040 err = PTR_ERR(chip->reset); 7041 goto out; 7042 } 7043 if (chip->reset) 7044 usleep_range(10000, 20000); 7045 7046 /* Detect if the device is configured in single chip addressing mode, 7047 * otherwise continue with address specific smi init/detection. 7048 */ 7049 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7050 if (err) { 7051 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7052 if (err) 7053 goto out; 7054 7055 err = mv88e6xxx_detect(chip); 7056 if (err) 7057 goto out; 7058 } 7059 7060 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7061 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7062 else 7063 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7064 7065 mv88e6xxx_phy_init(chip); 7066 7067 if (chip->info->ops->get_eeprom) { 7068 if (np) 7069 of_property_read_u32(np, "eeprom-length", 7070 &chip->eeprom_len); 7071 else 7072 chip->eeprom_len = pdata->eeprom_len; 7073 } 7074 7075 mv88e6xxx_reg_lock(chip); 7076 err = mv88e6xxx_switch_reset(chip); 7077 mv88e6xxx_reg_unlock(chip); 7078 if (err) 7079 goto out; 7080 7081 if (np) { 7082 chip->irq = of_irq_get(np, 0); 7083 if (chip->irq == -EPROBE_DEFER) { 7084 err = chip->irq; 7085 goto out; 7086 } 7087 } 7088 7089 if (pdata) 7090 chip->irq = pdata->irq; 7091 7092 /* Has to be performed before the MDIO bus is created, because 7093 * the PHYs will link their interrupts to these interrupt 7094 * controllers 7095 */ 7096 mv88e6xxx_reg_lock(chip); 7097 if (chip->irq > 0) 7098 err = mv88e6xxx_g1_irq_setup(chip); 7099 else 7100 err = mv88e6xxx_irq_poll_setup(chip); 7101 mv88e6xxx_reg_unlock(chip); 7102 7103 if (err) 7104 goto out; 7105 7106 if (chip->info->g2_irqs > 0) { 7107 err = mv88e6xxx_g2_irq_setup(chip); 7108 if (err) 7109 goto out_g1_irq; 7110 } 7111 7112 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7113 if (err) 7114 goto out_g2_irq; 7115 7116 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7117 if (err) 7118 goto out_g1_atu_prob_irq; 7119 7120 err = mv88e6xxx_register_switch(chip); 7121 if (err) 7122 goto out_g1_vtu_prob_irq; 7123 7124 return 0; 7125 7126 out_g1_vtu_prob_irq: 7127 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7128 out_g1_atu_prob_irq: 7129 mv88e6xxx_g1_atu_prob_irq_free(chip); 7130 out_g2_irq: 7131 if (chip->info->g2_irqs > 0) 7132 mv88e6xxx_g2_irq_free(chip); 7133 out_g1_irq: 7134 if (chip->irq > 0) 7135 mv88e6xxx_g1_irq_free(chip); 7136 else 7137 mv88e6xxx_irq_poll_free(chip); 7138 out: 7139 if (pdata) 7140 dev_put(pdata->netdev); 7141 7142 return err; 7143 } 7144 7145 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7146 { 7147 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7148 struct mv88e6xxx_chip *chip; 7149 7150 if (!ds) 7151 return; 7152 7153 chip = ds->priv; 7154 7155 if (chip->info->ptp_support) { 7156 mv88e6xxx_hwtstamp_free(chip); 7157 mv88e6xxx_ptp_free(chip); 7158 } 7159 7160 mv88e6xxx_phy_destroy(chip); 7161 mv88e6xxx_unregister_switch(chip); 7162 7163 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7164 mv88e6xxx_g1_atu_prob_irq_free(chip); 7165 7166 if (chip->info->g2_irqs > 0) 7167 mv88e6xxx_g2_irq_free(chip); 7168 7169 if (chip->irq > 0) 7170 mv88e6xxx_g1_irq_free(chip); 7171 else 7172 mv88e6xxx_irq_poll_free(chip); 7173 } 7174 7175 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7176 { 7177 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7178 7179 if (!ds) 7180 return; 7181 7182 dsa_switch_shutdown(ds); 7183 7184 dev_set_drvdata(&mdiodev->dev, NULL); 7185 } 7186 7187 static const struct of_device_id mv88e6xxx_of_match[] = { 7188 { 7189 .compatible = "marvell,mv88e6085", 7190 .data = &mv88e6xxx_table[MV88E6085], 7191 }, 7192 { 7193 .compatible = "marvell,mv88e6190", 7194 .data = &mv88e6xxx_table[MV88E6190], 7195 }, 7196 { 7197 .compatible = "marvell,mv88e6250", 7198 .data = &mv88e6xxx_table[MV88E6250], 7199 }, 7200 { /* sentinel */ }, 7201 }; 7202 7203 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7204 7205 static struct mdio_driver mv88e6xxx_driver = { 7206 .probe = mv88e6xxx_probe, 7207 .remove = mv88e6xxx_remove, 7208 .shutdown = mv88e6xxx_shutdown, 7209 .mdiodrv.driver = { 7210 .name = "mv88e6085", 7211 .of_match_table = mv88e6xxx_of_match, 7212 .pm = &mv88e6xxx_pm_ops, 7213 }, 7214 }; 7215 7216 mdio_module_driver(mv88e6xxx_driver); 7217 7218 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7219 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7220 MODULE_LICENSE("GPL"); 7221