1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2015 CMC Electronics, Inc. 7 * Added support for VLAN Table Unit operations 8 * 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 #include <net/switchdev.h> 36 37 #include "mv88e6xxx.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "port.h" 41 42 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 43 { 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 45 dev_err(chip->dev, "Switch registers lock not held!\n"); 46 dump_stack(); 47 } 48 } 49 50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 52 * 53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 54 * is the only device connected to the SMI master. In this mode it responds to 55 * all 32 possible SMI addresses, and thus maps directly the internal devices. 56 * 57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 58 * multiple devices to share the SMI interface. In this mode it responds to only 59 * 2 registers, used to indirectly access the internal SMI devices. 60 */ 61 62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 63 int addr, int reg, u16 *val) 64 { 65 if (!chip->smi_ops) 66 return -EOPNOTSUPP; 67 68 return chip->smi_ops->read(chip, addr, reg, val); 69 } 70 71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 72 int addr, int reg, u16 val) 73 { 74 if (!chip->smi_ops) 75 return -EOPNOTSUPP; 76 77 return chip->smi_ops->write(chip, addr, reg, val); 78 } 79 80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 81 int addr, int reg, u16 *val) 82 { 83 int ret; 84 85 ret = mdiobus_read_nested(chip->bus, addr, reg); 86 if (ret < 0) 87 return ret; 88 89 *val = ret & 0xffff; 90 91 return 0; 92 } 93 94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 95 int addr, int reg, u16 val) 96 { 97 int ret; 98 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 100 if (ret < 0) 101 return ret; 102 103 return 0; 104 } 105 106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 107 .read = mv88e6xxx_smi_single_chip_read, 108 .write = mv88e6xxx_smi_single_chip_write, 109 }; 110 111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 112 { 113 int ret; 114 int i; 115 116 for (i = 0; i < 16; i++) { 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 118 if (ret < 0) 119 return ret; 120 121 if ((ret & SMI_CMD_BUSY) == 0) 122 return 0; 123 } 124 125 return -ETIMEDOUT; 126 } 127 128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 129 int addr, int reg, u16 *val) 130 { 131 int ret; 132 133 /* Wait for the bus to become free. */ 134 ret = mv88e6xxx_smi_multi_chip_wait(chip); 135 if (ret < 0) 136 return ret; 137 138 /* Transmit the read command. */ 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 140 SMI_CMD_OP_22_READ | (addr << 5) | reg); 141 if (ret < 0) 142 return ret; 143 144 /* Wait for the read command to complete. */ 145 ret = mv88e6xxx_smi_multi_chip_wait(chip); 146 if (ret < 0) 147 return ret; 148 149 /* Read the data. */ 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 151 if (ret < 0) 152 return ret; 153 154 *val = ret & 0xffff; 155 156 return 0; 157 } 158 159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 160 int addr, int reg, u16 val) 161 { 162 int ret; 163 164 /* Wait for the bus to become free. */ 165 ret = mv88e6xxx_smi_multi_chip_wait(chip); 166 if (ret < 0) 167 return ret; 168 169 /* Transmit the data to write. */ 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the write command. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 177 if (ret < 0) 178 return ret; 179 180 /* Wait for the write command to complete. */ 181 ret = mv88e6xxx_smi_multi_chip_wait(chip); 182 if (ret < 0) 183 return ret; 184 185 return 0; 186 } 187 188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 189 .read = mv88e6xxx_smi_multi_chip_read, 190 .write = mv88e6xxx_smi_multi_chip_write, 191 }; 192 193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 194 { 195 int err; 196 197 assert_reg_lock(chip); 198 199 err = mv88e6xxx_smi_read(chip, addr, reg, val); 200 if (err) 201 return err; 202 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 204 addr, reg, *val); 205 206 return 0; 207 } 208 209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 210 { 211 int err; 212 213 assert_reg_lock(chip); 214 215 err = mv88e6xxx_smi_write(chip, addr, reg, val); 216 if (err) 217 return err; 218 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 220 addr, reg, val); 221 222 return 0; 223 } 224 225 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, 226 int reg, u16 *val) 227 { 228 int addr = phy; /* PHY devices addresses start at 0x0 */ 229 230 if (!chip->info->ops->phy_read) 231 return -EOPNOTSUPP; 232 233 return chip->info->ops->phy_read(chip, addr, reg, val); 234 } 235 236 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 237 int reg, u16 val) 238 { 239 int addr = phy; /* PHY devices addresses start at 0x0 */ 240 241 if (!chip->info->ops->phy_write) 242 return -EOPNOTSUPP; 243 244 return chip->info->ops->phy_write(chip, addr, reg, val); 245 } 246 247 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) 248 { 249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) 250 return -EOPNOTSUPP; 251 252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 253 } 254 255 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) 256 { 257 int err; 258 259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ 260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); 261 if (unlikely(err)) { 262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", 263 phy, err); 264 } 265 } 266 267 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 268 u8 page, int reg, u16 *val) 269 { 270 int err; 271 272 /* There is no paging for registers 22 */ 273 if (reg == PHY_PAGE) 274 return -EINVAL; 275 276 err = mv88e6xxx_phy_page_get(chip, phy, page); 277 if (!err) { 278 err = mv88e6xxx_phy_read(chip, phy, reg, val); 279 mv88e6xxx_phy_page_put(chip, phy); 280 } 281 282 return err; 283 } 284 285 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, 286 u8 page, int reg, u16 val) 287 { 288 int err; 289 290 /* There is no paging for registers 22 */ 291 if (reg == PHY_PAGE) 292 return -EINVAL; 293 294 err = mv88e6xxx_phy_page_get(chip, phy, page); 295 if (!err) { 296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 297 mv88e6xxx_phy_page_put(chip, phy); 298 } 299 300 return err; 301 } 302 303 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 304 { 305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 306 reg, val); 307 } 308 309 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 310 { 311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 312 reg, val); 313 } 314 315 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 316 { 317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 318 unsigned int n = d->hwirq; 319 320 chip->g1_irq.masked |= (1 << n); 321 } 322 323 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 324 { 325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 326 unsigned int n = d->hwirq; 327 328 chip->g1_irq.masked &= ~(1 << n); 329 } 330 331 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 332 { 333 struct mv88e6xxx_chip *chip = dev_id; 334 unsigned int nhandled = 0; 335 unsigned int sub_irq; 336 unsigned int n; 337 u16 reg; 338 int err; 339 340 mutex_lock(&chip->reg_lock); 341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 342 mutex_unlock(&chip->reg_lock); 343 344 if (err) 345 goto out; 346 347 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 348 if (reg & (1 << n)) { 349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 350 handle_nested_irq(sub_irq); 351 ++nhandled; 352 } 353 } 354 out: 355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 356 } 357 358 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 359 { 360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 361 362 mutex_lock(&chip->reg_lock); 363 } 364 365 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 366 { 367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 369 u16 reg; 370 int err; 371 372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); 373 if (err) 374 goto out; 375 376 reg &= ~mask; 377 reg |= (~chip->g1_irq.masked & mask); 378 379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); 380 if (err) 381 goto out; 382 383 out: 384 mutex_unlock(&chip->reg_lock); 385 } 386 387 static struct irq_chip mv88e6xxx_g1_irq_chip = { 388 .name = "mv88e6xxx-g1", 389 .irq_mask = mv88e6xxx_g1_irq_mask, 390 .irq_unmask = mv88e6xxx_g1_irq_unmask, 391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 393 }; 394 395 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 396 unsigned int irq, 397 irq_hw_number_t hwirq) 398 { 399 struct mv88e6xxx_chip *chip = d->host_data; 400 401 irq_set_chip_data(irq, d->host_data); 402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 403 irq_set_noprobe(irq); 404 405 return 0; 406 } 407 408 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 409 .map = mv88e6xxx_g1_irq_domain_map, 410 .xlate = irq_domain_xlate_twocell, 411 }; 412 413 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 414 { 415 int irq, virq; 416 u16 mask; 417 418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 419 mask |= GENMASK(chip->g1_irq.nirqs, 0); 420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 421 422 free_irq(chip->irq, chip); 423 424 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 425 virq = irq_find_mapping(chip->g1_irq.domain, irq); 426 irq_dispose_mapping(virq); 427 } 428 429 irq_domain_remove(chip->g1_irq.domain); 430 } 431 432 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 433 { 434 int err, irq, virq; 435 u16 reg, mask; 436 437 chip->g1_irq.nirqs = chip->info->g1_irqs; 438 chip->g1_irq.domain = irq_domain_add_simple( 439 NULL, chip->g1_irq.nirqs, 0, 440 &mv88e6xxx_g1_irq_domain_ops, chip); 441 if (!chip->g1_irq.domain) 442 return -ENOMEM; 443 444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 445 irq_create_mapping(chip->g1_irq.domain, irq); 446 447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 448 chip->g1_irq.masked = ~0; 449 450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 451 if (err) 452 goto out_mapping; 453 454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 455 456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 457 if (err) 458 goto out_disable; 459 460 /* Reading the interrupt status clears (most of) them */ 461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 462 if (err) 463 goto out_disable; 464 465 err = request_threaded_irq(chip->irq, NULL, 466 mv88e6xxx_g1_irq_thread_fn, 467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 468 dev_name(chip->dev), chip); 469 if (err) 470 goto out_disable; 471 472 return 0; 473 474 out_disable: 475 mask |= GENMASK(chip->g1_irq.nirqs, 0); 476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 477 478 out_mapping: 479 for (irq = 0; irq < 16; irq++) { 480 virq = irq_find_mapping(chip->g1_irq.domain, irq); 481 irq_dispose_mapping(virq); 482 } 483 484 irq_domain_remove(chip->g1_irq.domain); 485 486 return err; 487 } 488 489 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 490 { 491 int i; 492 493 for (i = 0; i < 16; i++) { 494 u16 val; 495 int err; 496 497 err = mv88e6xxx_read(chip, addr, reg, &val); 498 if (err) 499 return err; 500 501 if (!(val & mask)) 502 return 0; 503 504 usleep_range(1000, 2000); 505 } 506 507 dev_err(chip->dev, "Timeout while waiting for switch\n"); 508 return -ETIMEDOUT; 509 } 510 511 /* Indirect write to single pointer-data register with an Update bit */ 512 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 513 { 514 u16 val; 515 int err; 516 517 /* Wait until the previous operation is completed */ 518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 519 if (err) 520 return err; 521 522 /* Set the Update bit to trigger a write operation */ 523 val = BIT(15) | update; 524 525 return mv88e6xxx_write(chip, addr, reg, val); 526 } 527 528 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) 529 { 530 u16 val; 531 int i, err; 532 533 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); 534 if (err) 535 return err; 536 537 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, 538 val & ~GLOBAL_CONTROL_PPU_ENABLE); 539 if (err) 540 return err; 541 542 for (i = 0; i < 16; i++) { 543 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); 544 if (err) 545 return err; 546 547 usleep_range(1000, 2000); 548 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING) 549 return 0; 550 } 551 552 return -ETIMEDOUT; 553 } 554 555 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) 556 { 557 u16 val; 558 int i, err; 559 560 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); 561 if (err) 562 return err; 563 564 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, 565 val | GLOBAL_CONTROL_PPU_ENABLE); 566 if (err) 567 return err; 568 569 for (i = 0; i < 16; i++) { 570 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); 571 if (err) 572 return err; 573 574 usleep_range(1000, 2000); 575 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING) 576 return 0; 577 } 578 579 return -ETIMEDOUT; 580 } 581 582 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) 583 { 584 struct mv88e6xxx_chip *chip; 585 586 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); 587 588 mutex_lock(&chip->reg_lock); 589 590 if (mutex_trylock(&chip->ppu_mutex)) { 591 if (mv88e6xxx_ppu_enable(chip) == 0) 592 chip->ppu_disabled = 0; 593 mutex_unlock(&chip->ppu_mutex); 594 } 595 596 mutex_unlock(&chip->reg_lock); 597 } 598 599 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) 600 { 601 struct mv88e6xxx_chip *chip = (void *)_ps; 602 603 schedule_work(&chip->ppu_work); 604 } 605 606 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) 607 { 608 int ret; 609 610 mutex_lock(&chip->ppu_mutex); 611 612 /* If the PHY polling unit is enabled, disable it so that 613 * we can access the PHY registers. If it was already 614 * disabled, cancel the timer that is going to re-enable 615 * it. 616 */ 617 if (!chip->ppu_disabled) { 618 ret = mv88e6xxx_ppu_disable(chip); 619 if (ret < 0) { 620 mutex_unlock(&chip->ppu_mutex); 621 return ret; 622 } 623 chip->ppu_disabled = 1; 624 } else { 625 del_timer(&chip->ppu_timer); 626 ret = 0; 627 } 628 629 return ret; 630 } 631 632 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) 633 { 634 /* Schedule a timer to re-enable the PHY polling unit. */ 635 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); 636 mutex_unlock(&chip->ppu_mutex); 637 } 638 639 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) 640 { 641 mutex_init(&chip->ppu_mutex); 642 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); 643 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer, 644 (unsigned long)chip); 645 } 646 647 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) 648 { 649 del_timer_sync(&chip->ppu_timer); 650 } 651 652 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, 653 int reg, u16 *val) 654 { 655 int err; 656 657 err = mv88e6xxx_ppu_access_get(chip); 658 if (!err) { 659 err = mv88e6xxx_read(chip, addr, reg, val); 660 mv88e6xxx_ppu_access_put(chip); 661 } 662 663 return err; 664 } 665 666 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, 667 int reg, u16 val) 668 { 669 int err; 670 671 err = mv88e6xxx_ppu_access_get(chip); 672 if (!err) { 673 err = mv88e6xxx_write(chip, addr, reg, val); 674 mv88e6xxx_ppu_access_put(chip); 675 } 676 677 return err; 678 } 679 680 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) 681 { 682 return chip->info->family == MV88E6XXX_FAMILY_6095; 683 } 684 685 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) 686 { 687 return chip->info->family == MV88E6XXX_FAMILY_6097; 688 } 689 690 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) 691 { 692 return chip->info->family == MV88E6XXX_FAMILY_6165; 693 } 694 695 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) 696 { 697 return chip->info->family == MV88E6XXX_FAMILY_6185; 698 } 699 700 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) 701 { 702 return chip->info->family == MV88E6XXX_FAMILY_6320; 703 } 704 705 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) 706 { 707 return chip->info->family == MV88E6XXX_FAMILY_6351; 708 } 709 710 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) 711 { 712 return chip->info->family == MV88E6XXX_FAMILY_6352; 713 } 714 715 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 716 int link, int speed, int duplex, 717 phy_interface_t mode) 718 { 719 int err; 720 721 if (!chip->info->ops->port_set_link) 722 return 0; 723 724 /* Port's MAC control must not be changed unless the link is down */ 725 err = chip->info->ops->port_set_link(chip, port, 0); 726 if (err) 727 return err; 728 729 if (chip->info->ops->port_set_speed) { 730 err = chip->info->ops->port_set_speed(chip, port, speed); 731 if (err && err != -EOPNOTSUPP) 732 goto restore_link; 733 } 734 735 if (chip->info->ops->port_set_duplex) { 736 err = chip->info->ops->port_set_duplex(chip, port, duplex); 737 if (err && err != -EOPNOTSUPP) 738 goto restore_link; 739 } 740 741 if (chip->info->ops->port_set_rgmii_delay) { 742 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 743 if (err && err != -EOPNOTSUPP) 744 goto restore_link; 745 } 746 747 err = 0; 748 restore_link: 749 if (chip->info->ops->port_set_link(chip, port, link)) 750 netdev_err(chip->ds->ports[port].netdev, 751 "failed to restore MAC's link\n"); 752 753 return err; 754 } 755 756 /* We expect the switch to perform auto negotiation if there is a real 757 * phy. However, in the case of a fixed link phy, we force the port 758 * settings from the fixed link settings. 759 */ 760 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 761 struct phy_device *phydev) 762 { 763 struct mv88e6xxx_chip *chip = ds->priv; 764 int err; 765 766 if (!phy_is_pseudo_fixed_link(phydev)) 767 return; 768 769 mutex_lock(&chip->reg_lock); 770 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 771 phydev->duplex, phydev->interface); 772 mutex_unlock(&chip->reg_lock); 773 774 if (err && err != -EOPNOTSUPP) 775 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n"); 776 } 777 778 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 779 { 780 if (!chip->info->ops->stats_snapshot) 781 return -EOPNOTSUPP; 782 783 return chip->info->ops->stats_snapshot(chip, port); 784 } 785 786 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 787 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 788 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 789 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 790 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 791 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 792 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 793 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 794 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 795 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 796 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 797 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 798 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 799 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 800 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 801 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 802 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 803 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 804 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 805 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 806 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 807 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 808 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 809 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 810 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 811 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 812 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 813 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 814 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 815 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 816 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 817 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 818 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 819 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 820 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 821 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 822 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 823 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 824 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 825 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 826 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 827 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 828 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 829 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 830 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 831 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 832 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 833 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 834 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 835 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 836 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 837 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 838 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 839 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 840 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 841 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 842 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 843 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 844 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 845 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 846 }; 847 848 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 849 struct mv88e6xxx_hw_stat *s, 850 int port, u16 bank1_select, 851 u16 histogram) 852 { 853 u32 low; 854 u32 high = 0; 855 u16 reg = 0; 856 int err; 857 u64 value; 858 859 switch (s->type) { 860 case STATS_TYPE_PORT: 861 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 862 if (err) 863 return UINT64_MAX; 864 865 low = reg; 866 if (s->sizeof_stat == 4) { 867 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 868 if (err) 869 return UINT64_MAX; 870 high = reg; 871 } 872 break; 873 case STATS_TYPE_BANK1: 874 reg = bank1_select; 875 /* fall through */ 876 case STATS_TYPE_BANK0: 877 reg |= s->reg | histogram; 878 mv88e6xxx_g1_stats_read(chip, reg, &low); 879 if (s->sizeof_stat == 8) 880 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 881 } 882 value = (((u64)high) << 16) | low; 883 return value; 884 } 885 886 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 887 uint8_t *data, int types) 888 { 889 struct mv88e6xxx_hw_stat *stat; 890 int i, j; 891 892 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 893 stat = &mv88e6xxx_hw_stats[i]; 894 if (stat->type & types) { 895 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 896 ETH_GSTRING_LEN); 897 j++; 898 } 899 } 900 } 901 902 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 903 uint8_t *data) 904 { 905 mv88e6xxx_stats_get_strings(chip, data, 906 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 907 } 908 909 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 910 uint8_t *data) 911 { 912 mv88e6xxx_stats_get_strings(chip, data, 913 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 914 } 915 916 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 917 uint8_t *data) 918 { 919 struct mv88e6xxx_chip *chip = ds->priv; 920 921 if (chip->info->ops->stats_get_strings) 922 chip->info->ops->stats_get_strings(chip, data); 923 } 924 925 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 926 int types) 927 { 928 struct mv88e6xxx_hw_stat *stat; 929 int i, j; 930 931 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 932 stat = &mv88e6xxx_hw_stats[i]; 933 if (stat->type & types) 934 j++; 935 } 936 return j; 937 } 938 939 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 940 { 941 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 942 STATS_TYPE_PORT); 943 } 944 945 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 946 { 947 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 948 STATS_TYPE_BANK1); 949 } 950 951 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 952 { 953 struct mv88e6xxx_chip *chip = ds->priv; 954 955 if (chip->info->ops->stats_get_sset_count) 956 return chip->info->ops->stats_get_sset_count(chip); 957 958 return 0; 959 } 960 961 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 962 uint64_t *data, int types, 963 u16 bank1_select, u16 histogram) 964 { 965 struct mv88e6xxx_hw_stat *stat; 966 int i, j; 967 968 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 969 stat = &mv88e6xxx_hw_stats[i]; 970 if (stat->type & types) { 971 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 972 bank1_select, 973 histogram); 974 j++; 975 } 976 } 977 } 978 979 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 980 uint64_t *data) 981 { 982 return mv88e6xxx_stats_get_stats(chip, port, data, 983 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 984 0, GLOBAL_STATS_OP_HIST_RX_TX); 985 } 986 987 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 988 uint64_t *data) 989 { 990 return mv88e6xxx_stats_get_stats(chip, port, data, 991 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 992 GLOBAL_STATS_OP_BANK_1_BIT_9, 993 GLOBAL_STATS_OP_HIST_RX_TX); 994 } 995 996 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 997 uint64_t *data) 998 { 999 return mv88e6xxx_stats_get_stats(chip, port, data, 1000 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1001 GLOBAL_STATS_OP_BANK_1_BIT_10, 0); 1002 } 1003 1004 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1005 uint64_t *data) 1006 { 1007 if (chip->info->ops->stats_get_stats) 1008 chip->info->ops->stats_get_stats(chip, port, data); 1009 } 1010 1011 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1012 uint64_t *data) 1013 { 1014 struct mv88e6xxx_chip *chip = ds->priv; 1015 int ret; 1016 1017 mutex_lock(&chip->reg_lock); 1018 1019 ret = mv88e6xxx_stats_snapshot(chip, port); 1020 if (ret < 0) { 1021 mutex_unlock(&chip->reg_lock); 1022 return; 1023 } 1024 1025 mv88e6xxx_get_stats(chip, port, data); 1026 1027 mutex_unlock(&chip->reg_lock); 1028 } 1029 1030 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 1031 { 1032 if (chip->info->ops->stats_set_histogram) 1033 return chip->info->ops->stats_set_histogram(chip); 1034 1035 return 0; 1036 } 1037 1038 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1039 { 1040 return 32 * sizeof(u16); 1041 } 1042 1043 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1044 struct ethtool_regs *regs, void *_p) 1045 { 1046 struct mv88e6xxx_chip *chip = ds->priv; 1047 int err; 1048 u16 reg; 1049 u16 *p = _p; 1050 int i; 1051 1052 regs->version = 0; 1053 1054 memset(p, 0xff, 32 * sizeof(u16)); 1055 1056 mutex_lock(&chip->reg_lock); 1057 1058 for (i = 0; i < 32; i++) { 1059 1060 err = mv88e6xxx_port_read(chip, port, i, ®); 1061 if (!err) 1062 p[i] = reg; 1063 } 1064 1065 mutex_unlock(&chip->reg_lock); 1066 } 1067 1068 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) 1069 { 1070 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); 1071 } 1072 1073 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 1074 struct ethtool_eee *e) 1075 { 1076 struct mv88e6xxx_chip *chip = ds->priv; 1077 u16 reg; 1078 int err; 1079 1080 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1081 return -EOPNOTSUPP; 1082 1083 mutex_lock(&chip->reg_lock); 1084 1085 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1086 if (err) 1087 goto out; 1088 1089 e->eee_enabled = !!(reg & 0x0200); 1090 e->tx_lpi_enabled = !!(reg & 0x0100); 1091 1092 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 1093 if (err) 1094 goto out; 1095 1096 e->eee_active = !!(reg & PORT_STATUS_EEE); 1097 out: 1098 mutex_unlock(&chip->reg_lock); 1099 1100 return err; 1101 } 1102 1103 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 1104 struct phy_device *phydev, struct ethtool_eee *e) 1105 { 1106 struct mv88e6xxx_chip *chip = ds->priv; 1107 u16 reg; 1108 int err; 1109 1110 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1111 return -EOPNOTSUPP; 1112 1113 mutex_lock(&chip->reg_lock); 1114 1115 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1116 if (err) 1117 goto out; 1118 1119 reg &= ~0x0300; 1120 if (e->eee_enabled) 1121 reg |= 0x0200; 1122 if (e->tx_lpi_enabled) 1123 reg |= 0x0100; 1124 1125 err = mv88e6xxx_phy_write(chip, port, 16, reg); 1126 out: 1127 mutex_unlock(&chip->reg_lock); 1128 1129 return err; 1130 } 1131 1132 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) 1133 { 1134 u16 val; 1135 int err; 1136 1137 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { 1138 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); 1139 if (err) 1140 return err; 1141 } else if (mv88e6xxx_num_databases(chip) == 256) { 1142 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 1143 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 1144 if (err) 1145 return err; 1146 1147 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 1148 (val & 0xfff) | ((fid << 8) & 0xf000)); 1149 if (err) 1150 return err; 1151 1152 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1153 cmd |= fid & 0xf; 1154 } 1155 1156 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); 1157 if (err) 1158 return err; 1159 1160 return _mv88e6xxx_atu_wait(chip); 1161 } 1162 1163 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, 1164 struct mv88e6xxx_atu_entry *entry) 1165 { 1166 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; 1167 1168 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { 1169 unsigned int mask, shift; 1170 1171 if (entry->trunk) { 1172 data |= GLOBAL_ATU_DATA_TRUNK; 1173 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 1174 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 1175 } else { 1176 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 1177 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 1178 } 1179 1180 data |= (entry->portv_trunkid << shift) & mask; 1181 } 1182 1183 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); 1184 } 1185 1186 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, 1187 struct mv88e6xxx_atu_entry *entry, 1188 bool static_too) 1189 { 1190 int op; 1191 int err; 1192 1193 err = _mv88e6xxx_atu_wait(chip); 1194 if (err) 1195 return err; 1196 1197 err = _mv88e6xxx_atu_data_write(chip, entry); 1198 if (err) 1199 return err; 1200 1201 if (entry->fid) { 1202 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : 1203 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 1204 } else { 1205 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : 1206 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; 1207 } 1208 1209 return _mv88e6xxx_atu_cmd(chip, entry->fid, op); 1210 } 1211 1212 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, 1213 u16 fid, bool static_too) 1214 { 1215 struct mv88e6xxx_atu_entry entry = { 1216 .fid = fid, 1217 .state = 0, /* EntryState bits must be 0 */ 1218 }; 1219 1220 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1221 } 1222 1223 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 1224 int from_port, int to_port, bool static_too) 1225 { 1226 struct mv88e6xxx_atu_entry entry = { 1227 .trunk = false, 1228 .fid = fid, 1229 }; 1230 1231 /* EntryState bits must be 0xF */ 1232 entry.state = GLOBAL_ATU_DATA_STATE_MASK; 1233 1234 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ 1235 entry.portv_trunkid = (to_port & 0x0f) << 4; 1236 entry.portv_trunkid |= from_port & 0x0f; 1237 1238 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1239 } 1240 1241 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, 1242 int port, bool static_too) 1243 { 1244 /* Destination port 0xF means remove the entries */ 1245 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); 1246 } 1247 1248 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) 1249 { 1250 struct net_device *bridge = chip->ports[port].bridge_dev; 1251 struct dsa_switch *ds = chip->ds; 1252 u16 output_ports = 0; 1253 int i; 1254 1255 /* allow CPU port or DSA link(s) to send frames to every port */ 1256 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 1257 output_ports = ~0; 1258 } else { 1259 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1260 /* allow sending frames to every group member */ 1261 if (bridge && chip->ports[i].bridge_dev == bridge) 1262 output_ports |= BIT(i); 1263 1264 /* allow sending frames to CPU port and DSA link(s) */ 1265 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1266 output_ports |= BIT(i); 1267 } 1268 } 1269 1270 /* prevent frames from going back out of the port they came in on */ 1271 output_ports &= ~BIT(port); 1272 1273 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1274 } 1275 1276 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1277 u8 state) 1278 { 1279 struct mv88e6xxx_chip *chip = ds->priv; 1280 int stp_state; 1281 int err; 1282 1283 switch (state) { 1284 case BR_STATE_DISABLED: 1285 stp_state = PORT_CONTROL_STATE_DISABLED; 1286 break; 1287 case BR_STATE_BLOCKING: 1288 case BR_STATE_LISTENING: 1289 stp_state = PORT_CONTROL_STATE_BLOCKING; 1290 break; 1291 case BR_STATE_LEARNING: 1292 stp_state = PORT_CONTROL_STATE_LEARNING; 1293 break; 1294 case BR_STATE_FORWARDING: 1295 default: 1296 stp_state = PORT_CONTROL_STATE_FORWARDING; 1297 break; 1298 } 1299 1300 mutex_lock(&chip->reg_lock); 1301 err = mv88e6xxx_port_set_state(chip, port, stp_state); 1302 mutex_unlock(&chip->reg_lock); 1303 1304 if (err) 1305 netdev_err(ds->ports[port].netdev, "failed to update state\n"); 1306 } 1307 1308 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1309 { 1310 struct mv88e6xxx_chip *chip = ds->priv; 1311 int err; 1312 1313 mutex_lock(&chip->reg_lock); 1314 err = _mv88e6xxx_atu_remove(chip, 0, port, false); 1315 mutex_unlock(&chip->reg_lock); 1316 1317 if (err) 1318 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); 1319 } 1320 1321 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) 1322 { 1323 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); 1324 } 1325 1326 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) 1327 { 1328 int err; 1329 1330 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); 1331 if (err) 1332 return err; 1333 1334 return _mv88e6xxx_vtu_wait(chip); 1335 } 1336 1337 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) 1338 { 1339 int ret; 1340 1341 ret = _mv88e6xxx_vtu_wait(chip); 1342 if (ret < 0) 1343 return ret; 1344 1345 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); 1346 } 1347 1348 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, 1349 struct mv88e6xxx_vtu_entry *entry, 1350 unsigned int nibble_offset) 1351 { 1352 u16 regs[3]; 1353 int i, err; 1354 1355 for (i = 0; i < 3; ++i) { 1356 u16 *reg = ®s[i]; 1357 1358 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1359 if (err) 1360 return err; 1361 } 1362 1363 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1364 unsigned int shift = (i % 4) * 4 + nibble_offset; 1365 u16 reg = regs[i / 4]; 1366 1367 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, 1374 struct mv88e6xxx_vtu_entry *entry) 1375 { 1376 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); 1377 } 1378 1379 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, 1380 struct mv88e6xxx_vtu_entry *entry) 1381 { 1382 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); 1383 } 1384 1385 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, 1386 struct mv88e6xxx_vtu_entry *entry, 1387 unsigned int nibble_offset) 1388 { 1389 u16 regs[3] = { 0 }; 1390 int i, err; 1391 1392 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1393 unsigned int shift = (i % 4) * 4 + nibble_offset; 1394 u8 data = entry->data[i]; 1395 1396 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; 1397 } 1398 1399 for (i = 0; i < 3; ++i) { 1400 u16 reg = regs[i]; 1401 1402 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1403 if (err) 1404 return err; 1405 } 1406 1407 return 0; 1408 } 1409 1410 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, 1411 struct mv88e6xxx_vtu_entry *entry) 1412 { 1413 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); 1414 } 1415 1416 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, 1417 struct mv88e6xxx_vtu_entry *entry) 1418 { 1419 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); 1420 } 1421 1422 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) 1423 { 1424 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, 1425 vid & GLOBAL_VTU_VID_MASK); 1426 } 1427 1428 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1429 struct mv88e6xxx_vtu_entry *entry) 1430 { 1431 struct mv88e6xxx_vtu_entry next = { 0 }; 1432 u16 val; 1433 int err; 1434 1435 err = _mv88e6xxx_vtu_wait(chip); 1436 if (err) 1437 return err; 1438 1439 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); 1440 if (err) 1441 return err; 1442 1443 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1444 if (err) 1445 return err; 1446 1447 next.vid = val & GLOBAL_VTU_VID_MASK; 1448 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1449 1450 if (next.valid) { 1451 err = mv88e6xxx_vtu_data_read(chip, &next); 1452 if (err) 1453 return err; 1454 1455 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1456 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); 1457 if (err) 1458 return err; 1459 1460 next.fid = val & GLOBAL_VTU_FID_MASK; 1461 } else if (mv88e6xxx_num_databases(chip) == 256) { 1462 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1463 * VTU DBNum[3:0] are located in VTU Operation 3:0 1464 */ 1465 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); 1466 if (err) 1467 return err; 1468 1469 next.fid = (val & 0xf00) >> 4; 1470 next.fid |= val & 0xf; 1471 } 1472 1473 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1474 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1475 if (err) 1476 return err; 1477 1478 next.sid = val & GLOBAL_VTU_SID_MASK; 1479 } 1480 } 1481 1482 *entry = next; 1483 return 0; 1484 } 1485 1486 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, 1487 struct switchdev_obj_port_vlan *vlan, 1488 int (*cb)(struct switchdev_obj *obj)) 1489 { 1490 struct mv88e6xxx_chip *chip = ds->priv; 1491 struct mv88e6xxx_vtu_entry next; 1492 u16 pvid; 1493 int err; 1494 1495 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1496 return -EOPNOTSUPP; 1497 1498 mutex_lock(&chip->reg_lock); 1499 1500 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1501 if (err) 1502 goto unlock; 1503 1504 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1505 if (err) 1506 goto unlock; 1507 1508 do { 1509 err = _mv88e6xxx_vtu_getnext(chip, &next); 1510 if (err) 1511 break; 1512 1513 if (!next.valid) 1514 break; 1515 1516 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1517 continue; 1518 1519 /* reinit and dump this VLAN obj */ 1520 vlan->vid_begin = next.vid; 1521 vlan->vid_end = next.vid; 1522 vlan->flags = 0; 1523 1524 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) 1525 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1526 1527 if (next.vid == pvid) 1528 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1529 1530 err = cb(&vlan->obj); 1531 if (err) 1532 break; 1533 } while (next.vid < GLOBAL_VTU_VID_MASK); 1534 1535 unlock: 1536 mutex_unlock(&chip->reg_lock); 1537 1538 return err; 1539 } 1540 1541 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1542 struct mv88e6xxx_vtu_entry *entry) 1543 { 1544 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; 1545 u16 reg = 0; 1546 int err; 1547 1548 err = _mv88e6xxx_vtu_wait(chip); 1549 if (err) 1550 return err; 1551 1552 if (!entry->valid) 1553 goto loadpurge; 1554 1555 /* Write port member tags */ 1556 err = mv88e6xxx_vtu_data_write(chip, entry); 1557 if (err) 1558 return err; 1559 1560 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1561 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1562 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1563 if (err) 1564 return err; 1565 } 1566 1567 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1568 reg = entry->fid & GLOBAL_VTU_FID_MASK; 1569 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); 1570 if (err) 1571 return err; 1572 } else if (mv88e6xxx_num_databases(chip) == 256) { 1573 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1574 * VTU DBNum[3:0] are located in VTU Operation 3:0 1575 */ 1576 op |= (entry->fid & 0xf0) << 8; 1577 op |= entry->fid & 0xf; 1578 } 1579 1580 reg = GLOBAL_VTU_VID_VALID; 1581 loadpurge: 1582 reg |= entry->vid & GLOBAL_VTU_VID_MASK; 1583 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1584 if (err) 1585 return err; 1586 1587 return _mv88e6xxx_vtu_cmd(chip, op); 1588 } 1589 1590 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, 1591 struct mv88e6xxx_vtu_entry *entry) 1592 { 1593 struct mv88e6xxx_vtu_entry next = { 0 }; 1594 u16 val; 1595 int err; 1596 1597 err = _mv88e6xxx_vtu_wait(chip); 1598 if (err) 1599 return err; 1600 1601 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, 1602 sid & GLOBAL_VTU_SID_MASK); 1603 if (err) 1604 return err; 1605 1606 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); 1607 if (err) 1608 return err; 1609 1610 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1611 if (err) 1612 return err; 1613 1614 next.sid = val & GLOBAL_VTU_SID_MASK; 1615 1616 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1617 if (err) 1618 return err; 1619 1620 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1621 1622 if (next.valid) { 1623 err = mv88e6xxx_stu_data_read(chip, &next); 1624 if (err) 1625 return err; 1626 } 1627 1628 *entry = next; 1629 return 0; 1630 } 1631 1632 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1633 struct mv88e6xxx_vtu_entry *entry) 1634 { 1635 u16 reg = 0; 1636 int err; 1637 1638 err = _mv88e6xxx_vtu_wait(chip); 1639 if (err) 1640 return err; 1641 1642 if (!entry->valid) 1643 goto loadpurge; 1644 1645 /* Write port states */ 1646 err = mv88e6xxx_stu_data_write(chip, entry); 1647 if (err) 1648 return err; 1649 1650 reg = GLOBAL_VTU_VID_VALID; 1651 loadpurge: 1652 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1653 if (err) 1654 return err; 1655 1656 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1657 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1658 if (err) 1659 return err; 1660 1661 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); 1662 } 1663 1664 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) 1665 { 1666 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1667 struct mv88e6xxx_vtu_entry vlan; 1668 int i, err; 1669 1670 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1671 1672 /* Set every FID bit used by the (un)bridged ports */ 1673 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1674 err = mv88e6xxx_port_get_fid(chip, i, fid); 1675 if (err) 1676 return err; 1677 1678 set_bit(*fid, fid_bitmap); 1679 } 1680 1681 /* Set every FID bit used by the VLAN entries */ 1682 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1683 if (err) 1684 return err; 1685 1686 do { 1687 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1688 if (err) 1689 return err; 1690 1691 if (!vlan.valid) 1692 break; 1693 1694 set_bit(vlan.fid, fid_bitmap); 1695 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 1696 1697 /* The reset value 0x000 is used to indicate that multiple address 1698 * databases are not needed. Return the next positive available. 1699 */ 1700 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1701 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1702 return -ENOSPC; 1703 1704 /* Clear the database */ 1705 return _mv88e6xxx_atu_flush(chip, *fid, true); 1706 } 1707 1708 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, 1709 struct mv88e6xxx_vtu_entry *entry) 1710 { 1711 struct dsa_switch *ds = chip->ds; 1712 struct mv88e6xxx_vtu_entry vlan = { 1713 .valid = true, 1714 .vid = vid, 1715 }; 1716 int i, err; 1717 1718 err = _mv88e6xxx_fid_new(chip, &vlan.fid); 1719 if (err) 1720 return err; 1721 1722 /* exclude all ports except the CPU and DSA ports */ 1723 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1724 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) 1725 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 1726 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1727 1728 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || 1729 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { 1730 struct mv88e6xxx_vtu_entry vstp; 1731 1732 /* Adding a VTU entry requires a valid STU entry. As VSTP is not 1733 * implemented, only one STU entry is needed to cover all VTU 1734 * entries. Thus, validate the SID 0. 1735 */ 1736 vlan.sid = 0; 1737 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); 1738 if (err) 1739 return err; 1740 1741 if (vstp.sid != vlan.sid || !vstp.valid) { 1742 memset(&vstp, 0, sizeof(vstp)); 1743 vstp.valid = true; 1744 vstp.sid = vlan.sid; 1745 1746 err = _mv88e6xxx_stu_loadpurge(chip, &vstp); 1747 if (err) 1748 return err; 1749 } 1750 } 1751 1752 *entry = vlan; 1753 return 0; 1754 } 1755 1756 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1757 struct mv88e6xxx_vtu_entry *entry, bool creat) 1758 { 1759 int err; 1760 1761 if (!vid) 1762 return -EINVAL; 1763 1764 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); 1765 if (err) 1766 return err; 1767 1768 err = _mv88e6xxx_vtu_getnext(chip, entry); 1769 if (err) 1770 return err; 1771 1772 if (entry->vid != vid || !entry->valid) { 1773 if (!creat) 1774 return -EOPNOTSUPP; 1775 /* -ENOENT would've been more appropriate, but switchdev expects 1776 * -EOPNOTSUPP to inform bridge about an eventual software VLAN. 1777 */ 1778 1779 err = _mv88e6xxx_vtu_new(chip, vid, entry); 1780 } 1781 1782 return err; 1783 } 1784 1785 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1786 u16 vid_begin, u16 vid_end) 1787 { 1788 struct mv88e6xxx_chip *chip = ds->priv; 1789 struct mv88e6xxx_vtu_entry vlan; 1790 int i, err; 1791 1792 if (!vid_begin) 1793 return -EOPNOTSUPP; 1794 1795 mutex_lock(&chip->reg_lock); 1796 1797 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); 1798 if (err) 1799 goto unlock; 1800 1801 do { 1802 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1803 if (err) 1804 goto unlock; 1805 1806 if (!vlan.valid) 1807 break; 1808 1809 if (vlan.vid > vid_end) 1810 break; 1811 1812 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1813 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1814 continue; 1815 1816 if (vlan.data[i] == 1817 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1818 continue; 1819 1820 if (chip->ports[i].bridge_dev == 1821 chip->ports[port].bridge_dev) 1822 break; /* same bridge, check next VLAN */ 1823 1824 netdev_warn(ds->ports[port].netdev, 1825 "hardware VLAN %d already used by %s\n", 1826 vlan.vid, 1827 netdev_name(chip->ports[i].bridge_dev)); 1828 err = -EOPNOTSUPP; 1829 goto unlock; 1830 } 1831 } while (vlan.vid < vid_end); 1832 1833 unlock: 1834 mutex_unlock(&chip->reg_lock); 1835 1836 return err; 1837 } 1838 1839 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1840 bool vlan_filtering) 1841 { 1842 struct mv88e6xxx_chip *chip = ds->priv; 1843 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : 1844 PORT_CONTROL_2_8021Q_DISABLED; 1845 int err; 1846 1847 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1848 return -EOPNOTSUPP; 1849 1850 mutex_lock(&chip->reg_lock); 1851 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1852 mutex_unlock(&chip->reg_lock); 1853 1854 return err; 1855 } 1856 1857 static int 1858 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1859 const struct switchdev_obj_port_vlan *vlan, 1860 struct switchdev_trans *trans) 1861 { 1862 struct mv88e6xxx_chip *chip = ds->priv; 1863 int err; 1864 1865 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1866 return -EOPNOTSUPP; 1867 1868 /* If the requested port doesn't belong to the same bridge as the VLAN 1869 * members, do not support it (yet) and fallback to software VLAN. 1870 */ 1871 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1872 vlan->vid_end); 1873 if (err) 1874 return err; 1875 1876 /* We don't need any dynamic resource from the kernel (yet), 1877 * so skip the prepare phase. 1878 */ 1879 return 0; 1880 } 1881 1882 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1883 u16 vid, bool untagged) 1884 { 1885 struct mv88e6xxx_vtu_entry vlan; 1886 int err; 1887 1888 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1889 if (err) 1890 return err; 1891 1892 vlan.data[port] = untagged ? 1893 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : 1894 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; 1895 1896 return _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1897 } 1898 1899 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1900 const struct switchdev_obj_port_vlan *vlan, 1901 struct switchdev_trans *trans) 1902 { 1903 struct mv88e6xxx_chip *chip = ds->priv; 1904 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1905 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1906 u16 vid; 1907 1908 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1909 return; 1910 1911 mutex_lock(&chip->reg_lock); 1912 1913 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1914 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) 1915 netdev_err(ds->ports[port].netdev, 1916 "failed to add VLAN %d%c\n", 1917 vid, untagged ? 'u' : 't'); 1918 1919 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1920 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", 1921 vlan->vid_end); 1922 1923 mutex_unlock(&chip->reg_lock); 1924 } 1925 1926 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1927 int port, u16 vid) 1928 { 1929 struct dsa_switch *ds = chip->ds; 1930 struct mv88e6xxx_vtu_entry vlan; 1931 int i, err; 1932 1933 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1934 if (err) 1935 return err; 1936 1937 /* Tell switchdev if this VLAN is handled in software */ 1938 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1939 return -EOPNOTSUPP; 1940 1941 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1942 1943 /* keep the VLAN unless all ports are excluded */ 1944 vlan.valid = false; 1945 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1946 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1947 continue; 1948 1949 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1950 vlan.valid = true; 1951 break; 1952 } 1953 } 1954 1955 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1956 if (err) 1957 return err; 1958 1959 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); 1960 } 1961 1962 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1963 const struct switchdev_obj_port_vlan *vlan) 1964 { 1965 struct mv88e6xxx_chip *chip = ds->priv; 1966 u16 pvid, vid; 1967 int err = 0; 1968 1969 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1970 return -EOPNOTSUPP; 1971 1972 mutex_lock(&chip->reg_lock); 1973 1974 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1975 if (err) 1976 goto unlock; 1977 1978 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1979 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1980 if (err) 1981 goto unlock; 1982 1983 if (vid == pvid) { 1984 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1985 if (err) 1986 goto unlock; 1987 } 1988 } 1989 1990 unlock: 1991 mutex_unlock(&chip->reg_lock); 1992 1993 return err; 1994 } 1995 1996 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, 1997 const unsigned char *addr) 1998 { 1999 int i, err; 2000 2001 for (i = 0; i < 3; i++) { 2002 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, 2003 (addr[i * 2] << 8) | addr[i * 2 + 1]); 2004 if (err) 2005 return err; 2006 } 2007 2008 return 0; 2009 } 2010 2011 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, 2012 unsigned char *addr) 2013 { 2014 u16 val; 2015 int i, err; 2016 2017 for (i = 0; i < 3; i++) { 2018 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); 2019 if (err) 2020 return err; 2021 2022 addr[i * 2] = val >> 8; 2023 addr[i * 2 + 1] = val & 0xff; 2024 } 2025 2026 return 0; 2027 } 2028 2029 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, 2030 struct mv88e6xxx_atu_entry *entry) 2031 { 2032 int ret; 2033 2034 ret = _mv88e6xxx_atu_wait(chip); 2035 if (ret < 0) 2036 return ret; 2037 2038 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); 2039 if (ret < 0) 2040 return ret; 2041 2042 ret = _mv88e6xxx_atu_data_write(chip, entry); 2043 if (ret < 0) 2044 return ret; 2045 2046 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); 2047 } 2048 2049 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2050 struct mv88e6xxx_atu_entry *entry); 2051 2052 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, 2053 const u8 *addr, struct mv88e6xxx_atu_entry *entry) 2054 { 2055 struct mv88e6xxx_atu_entry next; 2056 int err; 2057 2058 eth_broadcast_addr(next.mac); 2059 2060 err = _mv88e6xxx_atu_mac_write(chip, next.mac); 2061 if (err) 2062 return err; 2063 2064 do { 2065 err = _mv88e6xxx_atu_getnext(chip, fid, &next); 2066 if (err) 2067 return err; 2068 2069 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2070 break; 2071 2072 if (ether_addr_equal(next.mac, addr)) { 2073 *entry = next; 2074 return 0; 2075 } 2076 } while (!is_broadcast_ether_addr(next.mac)); 2077 2078 memset(entry, 0, sizeof(*entry)); 2079 entry->fid = fid; 2080 ether_addr_copy(entry->mac, addr); 2081 2082 return 0; 2083 } 2084 2085 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2086 const unsigned char *addr, u16 vid, 2087 u8 state) 2088 { 2089 struct mv88e6xxx_vtu_entry vlan; 2090 struct mv88e6xxx_atu_entry entry; 2091 int err; 2092 2093 /* Null VLAN ID corresponds to the port private database */ 2094 if (vid == 0) 2095 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 2096 else 2097 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 2098 if (err) 2099 return err; 2100 2101 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); 2102 if (err) 2103 return err; 2104 2105 /* Purge the ATU entry only if no port is using it anymore */ 2106 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { 2107 entry.portv_trunkid &= ~BIT(port); 2108 if (!entry.portv_trunkid) 2109 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; 2110 } else { 2111 entry.portv_trunkid |= BIT(port); 2112 entry.state = state; 2113 } 2114 2115 return _mv88e6xxx_atu_load(chip, &entry); 2116 } 2117 2118 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 2119 const struct switchdev_obj_port_fdb *fdb, 2120 struct switchdev_trans *trans) 2121 { 2122 /* We don't need any dynamic resource from the kernel (yet), 2123 * so skip the prepare phase. 2124 */ 2125 return 0; 2126 } 2127 2128 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2129 const struct switchdev_obj_port_fdb *fdb, 2130 struct switchdev_trans *trans) 2131 { 2132 struct mv88e6xxx_chip *chip = ds->priv; 2133 2134 mutex_lock(&chip->reg_lock); 2135 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2136 GLOBAL_ATU_DATA_STATE_UC_STATIC)) 2137 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); 2138 mutex_unlock(&chip->reg_lock); 2139 } 2140 2141 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2142 const struct switchdev_obj_port_fdb *fdb) 2143 { 2144 struct mv88e6xxx_chip *chip = ds->priv; 2145 int err; 2146 2147 mutex_lock(&chip->reg_lock); 2148 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2149 GLOBAL_ATU_DATA_STATE_UNUSED); 2150 mutex_unlock(&chip->reg_lock); 2151 2152 return err; 2153 } 2154 2155 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2156 struct mv88e6xxx_atu_entry *entry) 2157 { 2158 struct mv88e6xxx_atu_entry next = { 0 }; 2159 u16 val; 2160 int err; 2161 2162 next.fid = fid; 2163 2164 err = _mv88e6xxx_atu_wait(chip); 2165 if (err) 2166 return err; 2167 2168 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); 2169 if (err) 2170 return err; 2171 2172 err = _mv88e6xxx_atu_mac_read(chip, next.mac); 2173 if (err) 2174 return err; 2175 2176 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); 2177 if (err) 2178 return err; 2179 2180 next.state = val & GLOBAL_ATU_DATA_STATE_MASK; 2181 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { 2182 unsigned int mask, shift; 2183 2184 if (val & GLOBAL_ATU_DATA_TRUNK) { 2185 next.trunk = true; 2186 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 2187 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 2188 } else { 2189 next.trunk = false; 2190 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 2191 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 2192 } 2193 2194 next.portv_trunkid = (val & mask) >> shift; 2195 } 2196 2197 *entry = next; 2198 return 0; 2199 } 2200 2201 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2202 u16 fid, u16 vid, int port, 2203 struct switchdev_obj *obj, 2204 int (*cb)(struct switchdev_obj *obj)) 2205 { 2206 struct mv88e6xxx_atu_entry addr = { 2207 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 2208 }; 2209 int err; 2210 2211 err = _mv88e6xxx_atu_mac_write(chip, addr.mac); 2212 if (err) 2213 return err; 2214 2215 do { 2216 err = _mv88e6xxx_atu_getnext(chip, fid, &addr); 2217 if (err) 2218 return err; 2219 2220 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2221 break; 2222 2223 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) 2224 continue; 2225 2226 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { 2227 struct switchdev_obj_port_fdb *fdb; 2228 2229 if (!is_unicast_ether_addr(addr.mac)) 2230 continue; 2231 2232 fdb = SWITCHDEV_OBJ_PORT_FDB(obj); 2233 fdb->vid = vid; 2234 ether_addr_copy(fdb->addr, addr.mac); 2235 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) 2236 fdb->ndm_state = NUD_NOARP; 2237 else 2238 fdb->ndm_state = NUD_REACHABLE; 2239 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { 2240 struct switchdev_obj_port_mdb *mdb; 2241 2242 if (!is_multicast_ether_addr(addr.mac)) 2243 continue; 2244 2245 mdb = SWITCHDEV_OBJ_PORT_MDB(obj); 2246 mdb->vid = vid; 2247 ether_addr_copy(mdb->addr, addr.mac); 2248 } else { 2249 return -EOPNOTSUPP; 2250 } 2251 2252 err = cb(obj); 2253 if (err) 2254 return err; 2255 } while (!is_broadcast_ether_addr(addr.mac)); 2256 2257 return err; 2258 } 2259 2260 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2261 struct switchdev_obj *obj, 2262 int (*cb)(struct switchdev_obj *obj)) 2263 { 2264 struct mv88e6xxx_vtu_entry vlan = { 2265 .vid = GLOBAL_VTU_VID_MASK, /* all ones */ 2266 }; 2267 u16 fid; 2268 int err; 2269 2270 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2271 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2272 if (err) 2273 return err; 2274 2275 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); 2276 if (err) 2277 return err; 2278 2279 /* Dump VLANs' Filtering Information Databases */ 2280 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); 2281 if (err) 2282 return err; 2283 2284 do { 2285 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 2286 if (err) 2287 return err; 2288 2289 if (!vlan.valid) 2290 break; 2291 2292 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2293 obj, cb); 2294 if (err) 2295 return err; 2296 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 2297 2298 return err; 2299 } 2300 2301 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2302 struct switchdev_obj_port_fdb *fdb, 2303 int (*cb)(struct switchdev_obj *obj)) 2304 { 2305 struct mv88e6xxx_chip *chip = ds->priv; 2306 int err; 2307 2308 mutex_lock(&chip->reg_lock); 2309 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); 2310 mutex_unlock(&chip->reg_lock); 2311 2312 return err; 2313 } 2314 2315 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2316 struct net_device *bridge) 2317 { 2318 struct mv88e6xxx_chip *chip = ds->priv; 2319 int i, err = 0; 2320 2321 mutex_lock(&chip->reg_lock); 2322 2323 /* Assign the bridge and remap each port's VLANTable */ 2324 chip->ports[port].bridge_dev = bridge; 2325 2326 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2327 if (chip->ports[i].bridge_dev == bridge) { 2328 err = _mv88e6xxx_port_based_vlan_map(chip, i); 2329 if (err) 2330 break; 2331 } 2332 } 2333 2334 mutex_unlock(&chip->reg_lock); 2335 2336 return err; 2337 } 2338 2339 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) 2340 { 2341 struct mv88e6xxx_chip *chip = ds->priv; 2342 struct net_device *bridge = chip->ports[port].bridge_dev; 2343 int i; 2344 2345 mutex_lock(&chip->reg_lock); 2346 2347 /* Unassign the bridge and remap each port's VLANTable */ 2348 chip->ports[port].bridge_dev = NULL; 2349 2350 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2351 if (i == port || chip->ports[i].bridge_dev == bridge) 2352 if (_mv88e6xxx_port_based_vlan_map(chip, i)) 2353 netdev_warn(ds->ports[i].netdev, 2354 "failed to remap\n"); 2355 2356 mutex_unlock(&chip->reg_lock); 2357 } 2358 2359 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2360 { 2361 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE); 2362 u16 is_reset = (ppu_active ? 0x8800 : 0xc800); 2363 struct gpio_desc *gpiod = chip->reset; 2364 unsigned long timeout; 2365 u16 reg; 2366 int err; 2367 int i; 2368 2369 /* Set all ports to the disabled state. */ 2370 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2371 err = mv88e6xxx_port_set_state(chip, i, 2372 PORT_CONTROL_STATE_DISABLED); 2373 if (err) 2374 return err; 2375 } 2376 2377 /* Wait for transmit queues to drain. */ 2378 usleep_range(2000, 4000); 2379 2380 /* If there is a gpio connected to the reset pin, toggle it */ 2381 if (gpiod) { 2382 gpiod_set_value_cansleep(gpiod, 1); 2383 usleep_range(10000, 20000); 2384 gpiod_set_value_cansleep(gpiod, 0); 2385 usleep_range(10000, 20000); 2386 } 2387 2388 /* Reset the switch. Keep the PPU active if requested. The PPU 2389 * needs to be active to support indirect phy register access 2390 * through global registers 0x18 and 0x19. 2391 */ 2392 if (ppu_active) 2393 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000); 2394 else 2395 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400); 2396 if (err) 2397 return err; 2398 2399 /* Wait up to one second for reset to complete. */ 2400 timeout = jiffies + 1 * HZ; 2401 while (time_before(jiffies, timeout)) { 2402 err = mv88e6xxx_g1_read(chip, 0x00, ®); 2403 if (err) 2404 return err; 2405 2406 if ((reg & is_reset) == is_reset) 2407 break; 2408 usleep_range(1000, 2000); 2409 } 2410 if (time_after(jiffies, timeout)) 2411 err = -ETIMEDOUT; 2412 else 2413 err = 0; 2414 2415 return err; 2416 } 2417 2418 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) 2419 { 2420 u16 val; 2421 int err; 2422 2423 /* Clear Power Down bit */ 2424 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); 2425 if (err) 2426 return err; 2427 2428 if (val & BMCR_PDOWN) { 2429 val &= ~BMCR_PDOWN; 2430 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); 2431 } 2432 2433 return err; 2434 } 2435 2436 static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port, 2437 int upstream_port) 2438 { 2439 int err; 2440 2441 err = chip->info->ops->port_set_frame_mode( 2442 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2443 if (err) 2444 return err; 2445 2446 return chip->info->ops->port_set_egress_unknowns( 2447 chip, port, port == upstream_port); 2448 } 2449 2450 static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port) 2451 { 2452 int err; 2453 2454 switch (chip->info->tag_protocol) { 2455 case DSA_TAG_PROTO_EDSA: 2456 err = chip->info->ops->port_set_frame_mode( 2457 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE); 2458 if (err) 2459 return err; 2460 2461 err = mv88e6xxx_port_set_egress_mode( 2462 chip, port, PORT_CONTROL_EGRESS_ADD_TAG); 2463 if (err) 2464 return err; 2465 2466 if (chip->info->ops->port_set_ether_type) 2467 err = chip->info->ops->port_set_ether_type( 2468 chip, port, ETH_P_EDSA); 2469 break; 2470 2471 case DSA_TAG_PROTO_DSA: 2472 err = chip->info->ops->port_set_frame_mode( 2473 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2474 if (err) 2475 return err; 2476 2477 err = mv88e6xxx_port_set_egress_mode( 2478 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED); 2479 break; 2480 default: 2481 err = -EINVAL; 2482 } 2483 2484 if (err) 2485 return err; 2486 2487 return chip->info->ops->port_set_egress_unknowns(chip, port, true); 2488 } 2489 2490 static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port) 2491 { 2492 int err; 2493 2494 err = chip->info->ops->port_set_frame_mode( 2495 chip, port, MV88E6XXX_FRAME_MODE_NORMAL); 2496 if (err) 2497 return err; 2498 2499 return chip->info->ops->port_set_egress_unknowns(chip, port, false); 2500 } 2501 2502 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2503 { 2504 struct dsa_switch *ds = chip->ds; 2505 int err; 2506 u16 reg; 2507 2508 /* MAC Forcing register: don't force link, speed, duplex or flow control 2509 * state to any particular values on physical ports, but force the CPU 2510 * port and all DSA ports to their maximum bandwidth and full duplex. 2511 */ 2512 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2513 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2514 SPEED_MAX, DUPLEX_FULL, 2515 PHY_INTERFACE_MODE_NA); 2516 else 2517 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2518 SPEED_UNFORCED, DUPLEX_UNFORCED, 2519 PHY_INTERFACE_MODE_NA); 2520 if (err) 2521 return err; 2522 2523 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2524 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2525 * tunneling, determine priority by looking at 802.1p and IP 2526 * priority fields (IP prio has precedence), and set STP state 2527 * to Forwarding. 2528 * 2529 * If this is the CPU link, use DSA or EDSA tagging depending 2530 * on which tagging mode was configured. 2531 * 2532 * If this is a link to another switch, use DSA tagging mode. 2533 * 2534 * If this is the upstream port for this switch, enable 2535 * forwarding of unknown unicasts and multicasts. 2536 */ 2537 reg = PORT_CONTROL_IGMP_MLD_SNOOP | 2538 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | 2539 PORT_CONTROL_STATE_FORWARDING; 2540 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 2541 if (err) 2542 return err; 2543 2544 if (dsa_is_cpu_port(ds, port)) { 2545 err = mv88e6xxx_setup_port_cpu(chip, port); 2546 } else if (dsa_is_dsa_port(ds, port)) { 2547 err = mv88e6xxx_setup_port_dsa(chip, port, 2548 dsa_upstream_port(ds)); 2549 } else { 2550 err = mv88e6xxx_setup_port_normal(chip, port); 2551 } 2552 if (err) 2553 return err; 2554 2555 /* If this port is connected to a SerDes, make sure the SerDes is not 2556 * powered down. 2557 */ 2558 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { 2559 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 2560 if (err) 2561 return err; 2562 reg &= PORT_STATUS_CMODE_MASK; 2563 if ((reg == PORT_STATUS_CMODE_100BASE_X) || 2564 (reg == PORT_STATUS_CMODE_1000BASE_X) || 2565 (reg == PORT_STATUS_CMODE_SGMII)) { 2566 err = mv88e6xxx_serdes_power_on(chip); 2567 if (err < 0) 2568 return err; 2569 } 2570 } 2571 2572 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2573 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2574 * untagged frames on this port, do a destination address lookup on all 2575 * received packets as usual, disable ARP mirroring and don't send a 2576 * copy of all transmitted/received frames on this port to the CPU. 2577 */ 2578 reg = 0; 2579 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2580 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2581 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || 2582 mv88e6xxx_6185_family(chip)) 2583 reg = PORT_CONTROL_2_MAP_DA; 2584 2585 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { 2586 /* Set the upstream port this port should use */ 2587 reg |= dsa_upstream_port(ds); 2588 /* enable forwarding of unknown multicast addresses to 2589 * the upstream port 2590 */ 2591 if (port == dsa_upstream_port(ds)) 2592 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; 2593 } 2594 2595 reg |= PORT_CONTROL_2_8021Q_DISABLED; 2596 2597 if (reg) { 2598 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); 2599 if (err) 2600 return err; 2601 } 2602 2603 if (chip->info->ops->port_jumbo_config) { 2604 err = chip->info->ops->port_jumbo_config(chip, port); 2605 if (err) 2606 return err; 2607 } 2608 2609 /* Port Association Vector: when learning source addresses 2610 * of packets, add the address to the address database using 2611 * a port bitmap that has only the bit for this port set and 2612 * the other bits clear. 2613 */ 2614 reg = 1 << port; 2615 /* Disable learning for CPU port */ 2616 if (dsa_is_cpu_port(ds, port)) 2617 reg = 0; 2618 2619 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); 2620 if (err) 2621 return err; 2622 2623 /* Egress rate control 2: disable egress rate control. */ 2624 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); 2625 if (err) 2626 return err; 2627 2628 if (chip->info->ops->port_pause_config) { 2629 err = chip->info->ops->port_pause_config(chip, port); 2630 if (err) 2631 return err; 2632 } 2633 2634 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2635 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2636 mv88e6xxx_6320_family(chip)) { 2637 /* Port ATU control: disable limiting the number of 2638 * address database entries that this port is allowed 2639 * to use. 2640 */ 2641 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 2642 0x0000); 2643 /* Priority Override: disable DA, SA and VTU priority 2644 * override. 2645 */ 2646 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 2647 0x0000); 2648 if (err) 2649 return err; 2650 } 2651 2652 if (chip->info->ops->port_tag_remap) { 2653 err = chip->info->ops->port_tag_remap(chip, port); 2654 if (err) 2655 return err; 2656 } 2657 2658 if (chip->info->ops->port_egress_rate_limiting) { 2659 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2660 if (err) 2661 return err; 2662 } 2663 2664 /* Port Control 1: disable trunking, disable sending 2665 * learning messages to this port. 2666 */ 2667 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); 2668 if (err) 2669 return err; 2670 2671 /* Port based VLAN map: give each port the same default address 2672 * database, and allow bidirectional communication between the 2673 * CPU and DSA port(s), and the other ports. 2674 */ 2675 err = mv88e6xxx_port_set_fid(chip, port, 0); 2676 if (err) 2677 return err; 2678 2679 err = _mv88e6xxx_port_based_vlan_map(chip, port); 2680 if (err) 2681 return err; 2682 2683 /* Default VLAN ID and priority: don't set a default VLAN 2684 * ID, and set the default packet priority to zero. 2685 */ 2686 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); 2687 } 2688 2689 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 2690 { 2691 int err; 2692 2693 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); 2694 if (err) 2695 return err; 2696 2697 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); 2698 if (err) 2699 return err; 2700 2701 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); 2702 if (err) 2703 return err; 2704 2705 return 0; 2706 } 2707 2708 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, 2709 unsigned int msecs) 2710 { 2711 const unsigned int coeff = chip->info->age_time_coeff; 2712 const unsigned int min = 0x01 * coeff; 2713 const unsigned int max = 0xff * coeff; 2714 u8 age_time; 2715 u16 val; 2716 int err; 2717 2718 if (msecs < min || msecs > max) 2719 return -ERANGE; 2720 2721 /* Round to nearest multiple of coeff */ 2722 age_time = (msecs + coeff / 2) / coeff; 2723 2724 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 2725 if (err) 2726 return err; 2727 2728 /* AgeTime is 11:4 bits */ 2729 val &= ~0xff0; 2730 val |= age_time << 4; 2731 2732 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); 2733 } 2734 2735 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2736 unsigned int ageing_time) 2737 { 2738 struct mv88e6xxx_chip *chip = ds->priv; 2739 int err; 2740 2741 mutex_lock(&chip->reg_lock); 2742 err = mv88e6xxx_g1_set_age_time(chip, ageing_time); 2743 mutex_unlock(&chip->reg_lock); 2744 2745 return err; 2746 } 2747 2748 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2749 { 2750 struct dsa_switch *ds = chip->ds; 2751 u32 upstream_port = dsa_upstream_port(ds); 2752 u16 reg; 2753 int err; 2754 2755 /* Enable the PHY Polling Unit if present, don't discard any packets, 2756 * and mask all interrupt sources. 2757 */ 2758 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); 2759 if (err < 0) 2760 return err; 2761 2762 reg &= ~GLOBAL_CONTROL_PPU_ENABLE; 2763 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || 2764 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) 2765 reg |= GLOBAL_CONTROL_PPU_ENABLE; 2766 2767 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); 2768 if (err) 2769 return err; 2770 2771 if (chip->info->ops->g1_set_cpu_port) { 2772 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port); 2773 if (err) 2774 return err; 2775 } 2776 2777 if (chip->info->ops->g1_set_egress_port) { 2778 err = chip->info->ops->g1_set_egress_port(chip, upstream_port); 2779 if (err) 2780 return err; 2781 } 2782 2783 /* Disable remote management, and set the switch's DSA device number. */ 2784 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, 2785 GLOBAL_CONTROL_2_MULTIPLE_CASCADE | 2786 (ds->index & 0x1f)); 2787 if (err) 2788 return err; 2789 2790 /* Clear all the VTU and STU entries */ 2791 err = _mv88e6xxx_vtu_stu_flush(chip); 2792 if (err < 0) 2793 return err; 2794 2795 /* Set the default address aging time to 5 minutes, and 2796 * enable address learn messages to be sent to all message 2797 * ports. 2798 */ 2799 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 2800 GLOBAL_ATU_CONTROL_LEARN2ALL); 2801 if (err) 2802 return err; 2803 2804 err = mv88e6xxx_g1_set_age_time(chip, 300000); 2805 if (err) 2806 return err; 2807 2808 /* Clear all ATU entries */ 2809 err = _mv88e6xxx_atu_flush(chip, 0, true); 2810 if (err) 2811 return err; 2812 2813 /* Configure the IP ToS mapping registers. */ 2814 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); 2815 if (err) 2816 return err; 2817 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); 2818 if (err) 2819 return err; 2820 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); 2821 if (err) 2822 return err; 2823 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); 2824 if (err) 2825 return err; 2826 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); 2827 if (err) 2828 return err; 2829 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); 2830 if (err) 2831 return err; 2832 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); 2833 if (err) 2834 return err; 2835 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); 2836 if (err) 2837 return err; 2838 2839 /* Configure the IEEE 802.1p priority mapping register. */ 2840 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); 2841 if (err) 2842 return err; 2843 2844 /* Initialize the statistics unit */ 2845 err = mv88e6xxx_stats_set_histogram(chip); 2846 if (err) 2847 return err; 2848 2849 /* Clear the statistics counters for all ports */ 2850 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 2851 GLOBAL_STATS_OP_FLUSH_ALL); 2852 if (err) 2853 return err; 2854 2855 /* Wait for the flush to complete. */ 2856 err = mv88e6xxx_g1_stats_wait(chip); 2857 if (err) 2858 return err; 2859 2860 return 0; 2861 } 2862 2863 static int mv88e6xxx_setup(struct dsa_switch *ds) 2864 { 2865 struct mv88e6xxx_chip *chip = ds->priv; 2866 int err; 2867 int i; 2868 2869 chip->ds = ds; 2870 ds->slave_mii_bus = chip->mdio_bus; 2871 2872 mutex_lock(&chip->reg_lock); 2873 2874 /* Setup Switch Port Registers */ 2875 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2876 err = mv88e6xxx_setup_port(chip, i); 2877 if (err) 2878 goto unlock; 2879 } 2880 2881 /* Setup Switch Global 1 Registers */ 2882 err = mv88e6xxx_g1_setup(chip); 2883 if (err) 2884 goto unlock; 2885 2886 /* Setup Switch Global 2 Registers */ 2887 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 2888 err = mv88e6xxx_g2_setup(chip); 2889 if (err) 2890 goto unlock; 2891 } 2892 2893 /* Some generations have the configuration of sending reserved 2894 * management frames to the CPU in global2, others in 2895 * global1. Hence it does not fit the two setup functions 2896 * above. 2897 */ 2898 if (chip->info->ops->mgmt_rsvd2cpu) { 2899 err = chip->info->ops->mgmt_rsvd2cpu(chip); 2900 if (err) 2901 goto unlock; 2902 } 2903 2904 unlock: 2905 mutex_unlock(&chip->reg_lock); 2906 2907 return err; 2908 } 2909 2910 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2911 { 2912 struct mv88e6xxx_chip *chip = ds->priv; 2913 int err; 2914 2915 if (!chip->info->ops->set_switch_mac) 2916 return -EOPNOTSUPP; 2917 2918 mutex_lock(&chip->reg_lock); 2919 err = chip->info->ops->set_switch_mac(chip, addr); 2920 mutex_unlock(&chip->reg_lock); 2921 2922 return err; 2923 } 2924 2925 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2926 { 2927 struct mv88e6xxx_chip *chip = bus->priv; 2928 u16 val; 2929 int err; 2930 2931 if (phy >= mv88e6xxx_num_ports(chip)) 2932 return 0xffff; 2933 2934 mutex_lock(&chip->reg_lock); 2935 err = mv88e6xxx_phy_read(chip, phy, reg, &val); 2936 mutex_unlock(&chip->reg_lock); 2937 2938 return err ? err : val; 2939 } 2940 2941 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2942 { 2943 struct mv88e6xxx_chip *chip = bus->priv; 2944 int err; 2945 2946 if (phy >= mv88e6xxx_num_ports(chip)) 2947 return 0xffff; 2948 2949 mutex_lock(&chip->reg_lock); 2950 err = mv88e6xxx_phy_write(chip, phy, reg, val); 2951 mutex_unlock(&chip->reg_lock); 2952 2953 return err; 2954 } 2955 2956 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2957 struct device_node *np) 2958 { 2959 static int index; 2960 struct mii_bus *bus; 2961 int err; 2962 2963 if (np) 2964 chip->mdio_np = of_get_child_by_name(np, "mdio"); 2965 2966 bus = devm_mdiobus_alloc(chip->dev); 2967 if (!bus) 2968 return -ENOMEM; 2969 2970 bus->priv = (void *)chip; 2971 if (np) { 2972 bus->name = np->full_name; 2973 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 2974 } else { 2975 bus->name = "mv88e6xxx SMI"; 2976 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2977 } 2978 2979 bus->read = mv88e6xxx_mdio_read; 2980 bus->write = mv88e6xxx_mdio_write; 2981 bus->parent = chip->dev; 2982 2983 if (chip->mdio_np) 2984 err = of_mdiobus_register(bus, chip->mdio_np); 2985 else 2986 err = mdiobus_register(bus); 2987 if (err) { 2988 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2989 goto out; 2990 } 2991 chip->mdio_bus = bus; 2992 2993 return 0; 2994 2995 out: 2996 if (chip->mdio_np) 2997 of_node_put(chip->mdio_np); 2998 2999 return err; 3000 } 3001 3002 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) 3003 3004 { 3005 struct mii_bus *bus = chip->mdio_bus; 3006 3007 mdiobus_unregister(bus); 3008 3009 if (chip->mdio_np) 3010 of_node_put(chip->mdio_np); 3011 } 3012 3013 #ifdef CONFIG_NET_DSA_HWMON 3014 3015 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) 3016 { 3017 struct mv88e6xxx_chip *chip = ds->priv; 3018 u16 val; 3019 int ret; 3020 3021 *temp = 0; 3022 3023 mutex_lock(&chip->reg_lock); 3024 3025 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); 3026 if (ret < 0) 3027 goto error; 3028 3029 /* Enable temperature sensor */ 3030 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 3031 if (ret < 0) 3032 goto error; 3033 3034 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); 3035 if (ret < 0) 3036 goto error; 3037 3038 /* Wait for temperature to stabilize */ 3039 usleep_range(10000, 12000); 3040 3041 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 3042 if (ret < 0) 3043 goto error; 3044 3045 /* Disable temperature sensor */ 3046 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); 3047 if (ret < 0) 3048 goto error; 3049 3050 *temp = ((val & 0x1f) - 5) * 5; 3051 3052 error: 3053 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); 3054 mutex_unlock(&chip->reg_lock); 3055 return ret; 3056 } 3057 3058 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) 3059 { 3060 struct mv88e6xxx_chip *chip = ds->priv; 3061 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3062 u16 val; 3063 int ret; 3064 3065 *temp = 0; 3066 3067 mutex_lock(&chip->reg_lock); 3068 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); 3069 mutex_unlock(&chip->reg_lock); 3070 if (ret < 0) 3071 return ret; 3072 3073 *temp = (val & 0xff) - 25; 3074 3075 return 0; 3076 } 3077 3078 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) 3079 { 3080 struct mv88e6xxx_chip *chip = ds->priv; 3081 3082 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) 3083 return -EOPNOTSUPP; 3084 3085 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) 3086 return mv88e63xx_get_temp(ds, temp); 3087 3088 return mv88e61xx_get_temp(ds, temp); 3089 } 3090 3091 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) 3092 { 3093 struct mv88e6xxx_chip *chip = ds->priv; 3094 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3095 u16 val; 3096 int ret; 3097 3098 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3099 return -EOPNOTSUPP; 3100 3101 *temp = 0; 3102 3103 mutex_lock(&chip->reg_lock); 3104 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3105 mutex_unlock(&chip->reg_lock); 3106 if (ret < 0) 3107 return ret; 3108 3109 *temp = (((val >> 8) & 0x1f) * 5) - 25; 3110 3111 return 0; 3112 } 3113 3114 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) 3115 { 3116 struct mv88e6xxx_chip *chip = ds->priv; 3117 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3118 u16 val; 3119 int err; 3120 3121 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3122 return -EOPNOTSUPP; 3123 3124 mutex_lock(&chip->reg_lock); 3125 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3126 if (err) 3127 goto unlock; 3128 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); 3129 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, 3130 (val & 0xe0ff) | (temp << 8)); 3131 unlock: 3132 mutex_unlock(&chip->reg_lock); 3133 3134 return err; 3135 } 3136 3137 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) 3138 { 3139 struct mv88e6xxx_chip *chip = ds->priv; 3140 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3141 u16 val; 3142 int ret; 3143 3144 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3145 return -EOPNOTSUPP; 3146 3147 *alarm = false; 3148 3149 mutex_lock(&chip->reg_lock); 3150 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3151 mutex_unlock(&chip->reg_lock); 3152 if (ret < 0) 3153 return ret; 3154 3155 *alarm = !!(val & 0x40); 3156 3157 return 0; 3158 } 3159 #endif /* CONFIG_NET_DSA_HWMON */ 3160 3161 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3162 { 3163 struct mv88e6xxx_chip *chip = ds->priv; 3164 3165 return chip->eeprom_len; 3166 } 3167 3168 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3169 struct ethtool_eeprom *eeprom, u8 *data) 3170 { 3171 struct mv88e6xxx_chip *chip = ds->priv; 3172 int err; 3173 3174 if (!chip->info->ops->get_eeprom) 3175 return -EOPNOTSUPP; 3176 3177 mutex_lock(&chip->reg_lock); 3178 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3179 mutex_unlock(&chip->reg_lock); 3180 3181 if (err) 3182 return err; 3183 3184 eeprom->magic = 0xc3ec4951; 3185 3186 return 0; 3187 } 3188 3189 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3190 struct ethtool_eeprom *eeprom, u8 *data) 3191 { 3192 struct mv88e6xxx_chip *chip = ds->priv; 3193 int err; 3194 3195 if (!chip->info->ops->set_eeprom) 3196 return -EOPNOTSUPP; 3197 3198 if (eeprom->magic != 0xc3ec4951) 3199 return -EINVAL; 3200 3201 mutex_lock(&chip->reg_lock); 3202 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3203 mutex_unlock(&chip->reg_lock); 3204 3205 return err; 3206 } 3207 3208 static const struct mv88e6xxx_ops mv88e6085_ops = { 3209 /* MV88E6XXX_FAMILY_6097 */ 3210 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3211 .phy_read = mv88e6xxx_phy_ppu_read, 3212 .phy_write = mv88e6xxx_phy_ppu_write, 3213 .port_set_link = mv88e6xxx_port_set_link, 3214 .port_set_duplex = mv88e6xxx_port_set_duplex, 3215 .port_set_speed = mv88e6185_port_set_speed, 3216 .port_tag_remap = mv88e6095_port_tag_remap, 3217 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3218 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3219 .port_set_ether_type = mv88e6351_port_set_ether_type, 3220 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3221 .port_pause_config = mv88e6097_port_pause_config, 3222 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3223 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3224 .stats_get_strings = mv88e6095_stats_get_strings, 3225 .stats_get_stats = mv88e6095_stats_get_stats, 3226 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3227 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3228 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3229 }; 3230 3231 static const struct mv88e6xxx_ops mv88e6095_ops = { 3232 /* MV88E6XXX_FAMILY_6095 */ 3233 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3234 .phy_read = mv88e6xxx_phy_ppu_read, 3235 .phy_write = mv88e6xxx_phy_ppu_write, 3236 .port_set_link = mv88e6xxx_port_set_link, 3237 .port_set_duplex = mv88e6xxx_port_set_duplex, 3238 .port_set_speed = mv88e6185_port_set_speed, 3239 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3240 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3241 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3242 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3243 .stats_get_strings = mv88e6095_stats_get_strings, 3244 .stats_get_stats = mv88e6095_stats_get_stats, 3245 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3246 }; 3247 3248 static const struct mv88e6xxx_ops mv88e6097_ops = { 3249 /* MV88E6XXX_FAMILY_6097 */ 3250 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3251 .phy_read = mv88e6xxx_g2_smi_phy_read, 3252 .phy_write = mv88e6xxx_g2_smi_phy_write, 3253 .port_set_link = mv88e6xxx_port_set_link, 3254 .port_set_duplex = mv88e6xxx_port_set_duplex, 3255 .port_set_speed = mv88e6185_port_set_speed, 3256 .port_tag_remap = mv88e6095_port_tag_remap, 3257 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3258 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3259 .port_set_ether_type = mv88e6351_port_set_ether_type, 3260 .port_jumbo_config = mv88e6165_port_jumbo_config, 3261 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3262 .port_pause_config = mv88e6097_port_pause_config, 3263 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3264 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3265 .stats_get_strings = mv88e6095_stats_get_strings, 3266 .stats_get_stats = mv88e6095_stats_get_stats, 3267 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3268 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3269 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3270 }; 3271 3272 static const struct mv88e6xxx_ops mv88e6123_ops = { 3273 /* MV88E6XXX_FAMILY_6165 */ 3274 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3275 .phy_read = mv88e6xxx_read, 3276 .phy_write = mv88e6xxx_write, 3277 .port_set_link = mv88e6xxx_port_set_link, 3278 .port_set_duplex = mv88e6xxx_port_set_duplex, 3279 .port_set_speed = mv88e6185_port_set_speed, 3280 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3281 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3282 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3283 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3284 .stats_get_strings = mv88e6095_stats_get_strings, 3285 .stats_get_stats = mv88e6095_stats_get_stats, 3286 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3287 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3288 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3289 }; 3290 3291 static const struct mv88e6xxx_ops mv88e6131_ops = { 3292 /* MV88E6XXX_FAMILY_6185 */ 3293 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3294 .phy_read = mv88e6xxx_phy_ppu_read, 3295 .phy_write = mv88e6xxx_phy_ppu_write, 3296 .port_set_link = mv88e6xxx_port_set_link, 3297 .port_set_duplex = mv88e6xxx_port_set_duplex, 3298 .port_set_speed = mv88e6185_port_set_speed, 3299 .port_tag_remap = mv88e6095_port_tag_remap, 3300 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3301 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3302 .port_set_ether_type = mv88e6351_port_set_ether_type, 3303 .port_jumbo_config = mv88e6165_port_jumbo_config, 3304 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3305 .port_pause_config = mv88e6097_port_pause_config, 3306 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3307 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3308 .stats_get_strings = mv88e6095_stats_get_strings, 3309 .stats_get_stats = mv88e6095_stats_get_stats, 3310 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3311 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3312 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3313 }; 3314 3315 static const struct mv88e6xxx_ops mv88e6161_ops = { 3316 /* MV88E6XXX_FAMILY_6165 */ 3317 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3318 .phy_read = mv88e6xxx_read, 3319 .phy_write = mv88e6xxx_write, 3320 .port_set_link = mv88e6xxx_port_set_link, 3321 .port_set_duplex = mv88e6xxx_port_set_duplex, 3322 .port_set_speed = mv88e6185_port_set_speed, 3323 .port_tag_remap = mv88e6095_port_tag_remap, 3324 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3325 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3326 .port_set_ether_type = mv88e6351_port_set_ether_type, 3327 .port_jumbo_config = mv88e6165_port_jumbo_config, 3328 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3329 .port_pause_config = mv88e6097_port_pause_config, 3330 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3331 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3332 .stats_get_strings = mv88e6095_stats_get_strings, 3333 .stats_get_stats = mv88e6095_stats_get_stats, 3334 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3335 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3336 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3337 }; 3338 3339 static const struct mv88e6xxx_ops mv88e6165_ops = { 3340 /* MV88E6XXX_FAMILY_6165 */ 3341 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3342 .phy_read = mv88e6xxx_read, 3343 .phy_write = mv88e6xxx_write, 3344 .port_set_link = mv88e6xxx_port_set_link, 3345 .port_set_duplex = mv88e6xxx_port_set_duplex, 3346 .port_set_speed = mv88e6185_port_set_speed, 3347 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3348 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3349 .stats_get_strings = mv88e6095_stats_get_strings, 3350 .stats_get_stats = mv88e6095_stats_get_stats, 3351 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3352 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3353 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3354 }; 3355 3356 static const struct mv88e6xxx_ops mv88e6171_ops = { 3357 /* MV88E6XXX_FAMILY_6351 */ 3358 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3359 .phy_read = mv88e6xxx_g2_smi_phy_read, 3360 .phy_write = mv88e6xxx_g2_smi_phy_write, 3361 .port_set_link = mv88e6xxx_port_set_link, 3362 .port_set_duplex = mv88e6xxx_port_set_duplex, 3363 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3364 .port_set_speed = mv88e6185_port_set_speed, 3365 .port_tag_remap = mv88e6095_port_tag_remap, 3366 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3367 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3368 .port_set_ether_type = mv88e6351_port_set_ether_type, 3369 .port_jumbo_config = mv88e6165_port_jumbo_config, 3370 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3371 .port_pause_config = mv88e6097_port_pause_config, 3372 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3373 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3374 .stats_get_strings = mv88e6095_stats_get_strings, 3375 .stats_get_stats = mv88e6095_stats_get_stats, 3376 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3377 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3378 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3379 }; 3380 3381 static const struct mv88e6xxx_ops mv88e6172_ops = { 3382 /* MV88E6XXX_FAMILY_6352 */ 3383 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3384 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3385 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3386 .phy_read = mv88e6xxx_g2_smi_phy_read, 3387 .phy_write = mv88e6xxx_g2_smi_phy_write, 3388 .port_set_link = mv88e6xxx_port_set_link, 3389 .port_set_duplex = mv88e6xxx_port_set_duplex, 3390 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3391 .port_set_speed = mv88e6352_port_set_speed, 3392 .port_tag_remap = mv88e6095_port_tag_remap, 3393 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3394 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3395 .port_set_ether_type = mv88e6351_port_set_ether_type, 3396 .port_jumbo_config = mv88e6165_port_jumbo_config, 3397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3398 .port_pause_config = mv88e6097_port_pause_config, 3399 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3400 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3401 .stats_get_strings = mv88e6095_stats_get_strings, 3402 .stats_get_stats = mv88e6095_stats_get_stats, 3403 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3404 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3405 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3406 }; 3407 3408 static const struct mv88e6xxx_ops mv88e6175_ops = { 3409 /* MV88E6XXX_FAMILY_6351 */ 3410 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3411 .phy_read = mv88e6xxx_g2_smi_phy_read, 3412 .phy_write = mv88e6xxx_g2_smi_phy_write, 3413 .port_set_link = mv88e6xxx_port_set_link, 3414 .port_set_duplex = mv88e6xxx_port_set_duplex, 3415 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3416 .port_set_speed = mv88e6185_port_set_speed, 3417 .port_tag_remap = mv88e6095_port_tag_remap, 3418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3419 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3420 .port_set_ether_type = mv88e6351_port_set_ether_type, 3421 .port_jumbo_config = mv88e6165_port_jumbo_config, 3422 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3423 .port_pause_config = mv88e6097_port_pause_config, 3424 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3425 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3426 .stats_get_strings = mv88e6095_stats_get_strings, 3427 .stats_get_stats = mv88e6095_stats_get_stats, 3428 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3429 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3430 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3431 }; 3432 3433 static const struct mv88e6xxx_ops mv88e6176_ops = { 3434 /* MV88E6XXX_FAMILY_6352 */ 3435 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3436 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3437 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3438 .phy_read = mv88e6xxx_g2_smi_phy_read, 3439 .phy_write = mv88e6xxx_g2_smi_phy_write, 3440 .port_set_link = mv88e6xxx_port_set_link, 3441 .port_set_duplex = mv88e6xxx_port_set_duplex, 3442 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3443 .port_set_speed = mv88e6352_port_set_speed, 3444 .port_tag_remap = mv88e6095_port_tag_remap, 3445 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3446 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3447 .port_set_ether_type = mv88e6351_port_set_ether_type, 3448 .port_jumbo_config = mv88e6165_port_jumbo_config, 3449 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3450 .port_pause_config = mv88e6097_port_pause_config, 3451 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3452 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3453 .stats_get_strings = mv88e6095_stats_get_strings, 3454 .stats_get_stats = mv88e6095_stats_get_stats, 3455 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3456 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3457 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3458 }; 3459 3460 static const struct mv88e6xxx_ops mv88e6185_ops = { 3461 /* MV88E6XXX_FAMILY_6185 */ 3462 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3463 .phy_read = mv88e6xxx_phy_ppu_read, 3464 .phy_write = mv88e6xxx_phy_ppu_write, 3465 .port_set_link = mv88e6xxx_port_set_link, 3466 .port_set_duplex = mv88e6xxx_port_set_duplex, 3467 .port_set_speed = mv88e6185_port_set_speed, 3468 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3469 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3470 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3471 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3472 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3473 .stats_get_strings = mv88e6095_stats_get_strings, 3474 .stats_get_stats = mv88e6095_stats_get_stats, 3475 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3476 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3477 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3478 }; 3479 3480 static const struct mv88e6xxx_ops mv88e6190_ops = { 3481 /* MV88E6XXX_FAMILY_6390 */ 3482 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3483 .phy_read = mv88e6xxx_g2_smi_phy_read, 3484 .phy_write = mv88e6xxx_g2_smi_phy_write, 3485 .port_set_link = mv88e6xxx_port_set_link, 3486 .port_set_duplex = mv88e6xxx_port_set_duplex, 3487 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3488 .port_set_speed = mv88e6390_port_set_speed, 3489 .port_tag_remap = mv88e6390_port_tag_remap, 3490 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3491 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3492 .port_set_ether_type = mv88e6351_port_set_ether_type, 3493 .port_pause_config = mv88e6390_port_pause_config, 3494 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3495 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3496 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3497 .stats_get_strings = mv88e6320_stats_get_strings, 3498 .stats_get_stats = mv88e6390_stats_get_stats, 3499 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3500 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3501 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3502 }; 3503 3504 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3505 /* MV88E6XXX_FAMILY_6390 */ 3506 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3507 .phy_read = mv88e6xxx_g2_smi_phy_read, 3508 .phy_write = mv88e6xxx_g2_smi_phy_write, 3509 .port_set_link = mv88e6xxx_port_set_link, 3510 .port_set_duplex = mv88e6xxx_port_set_duplex, 3511 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3512 .port_set_speed = mv88e6390x_port_set_speed, 3513 .port_tag_remap = mv88e6390_port_tag_remap, 3514 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3515 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3516 .port_set_ether_type = mv88e6351_port_set_ether_type, 3517 .port_pause_config = mv88e6390_port_pause_config, 3518 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3519 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3520 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3521 .stats_get_strings = mv88e6320_stats_get_strings, 3522 .stats_get_stats = mv88e6390_stats_get_stats, 3523 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3524 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3525 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3526 }; 3527 3528 static const struct mv88e6xxx_ops mv88e6191_ops = { 3529 /* MV88E6XXX_FAMILY_6390 */ 3530 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3531 .phy_read = mv88e6xxx_g2_smi_phy_read, 3532 .phy_write = mv88e6xxx_g2_smi_phy_write, 3533 .port_set_link = mv88e6xxx_port_set_link, 3534 .port_set_duplex = mv88e6xxx_port_set_duplex, 3535 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3536 .port_set_speed = mv88e6390_port_set_speed, 3537 .port_tag_remap = mv88e6390_port_tag_remap, 3538 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3539 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3540 .port_set_ether_type = mv88e6351_port_set_ether_type, 3541 .port_pause_config = mv88e6390_port_pause_config, 3542 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3543 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3544 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3545 .stats_get_strings = mv88e6320_stats_get_strings, 3546 .stats_get_stats = mv88e6390_stats_get_stats, 3547 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3548 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3549 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3550 }; 3551 3552 static const struct mv88e6xxx_ops mv88e6240_ops = { 3553 /* MV88E6XXX_FAMILY_6352 */ 3554 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3555 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3556 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3557 .phy_read = mv88e6xxx_g2_smi_phy_read, 3558 .phy_write = mv88e6xxx_g2_smi_phy_write, 3559 .port_set_link = mv88e6xxx_port_set_link, 3560 .port_set_duplex = mv88e6xxx_port_set_duplex, 3561 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3562 .port_set_speed = mv88e6352_port_set_speed, 3563 .port_tag_remap = mv88e6095_port_tag_remap, 3564 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3565 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3566 .port_set_ether_type = mv88e6351_port_set_ether_type, 3567 .port_jumbo_config = mv88e6165_port_jumbo_config, 3568 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3569 .port_pause_config = mv88e6097_port_pause_config, 3570 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3571 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3572 .stats_get_strings = mv88e6095_stats_get_strings, 3573 .stats_get_stats = mv88e6095_stats_get_stats, 3574 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3575 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3576 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3577 }; 3578 3579 static const struct mv88e6xxx_ops mv88e6290_ops = { 3580 /* MV88E6XXX_FAMILY_6390 */ 3581 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3582 .phy_read = mv88e6xxx_g2_smi_phy_read, 3583 .phy_write = mv88e6xxx_g2_smi_phy_write, 3584 .port_set_link = mv88e6xxx_port_set_link, 3585 .port_set_duplex = mv88e6xxx_port_set_duplex, 3586 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3587 .port_set_speed = mv88e6390_port_set_speed, 3588 .port_tag_remap = mv88e6390_port_tag_remap, 3589 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3590 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3591 .port_set_ether_type = mv88e6351_port_set_ether_type, 3592 .port_pause_config = mv88e6390_port_pause_config, 3593 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3594 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3595 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3596 .stats_get_strings = mv88e6320_stats_get_strings, 3597 .stats_get_stats = mv88e6390_stats_get_stats, 3598 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3599 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3600 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3601 }; 3602 3603 static const struct mv88e6xxx_ops mv88e6320_ops = { 3604 /* MV88E6XXX_FAMILY_6320 */ 3605 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3606 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3607 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3608 .phy_read = mv88e6xxx_g2_smi_phy_read, 3609 .phy_write = mv88e6xxx_g2_smi_phy_write, 3610 .port_set_link = mv88e6xxx_port_set_link, 3611 .port_set_duplex = mv88e6xxx_port_set_duplex, 3612 .port_set_speed = mv88e6185_port_set_speed, 3613 .port_tag_remap = mv88e6095_port_tag_remap, 3614 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3615 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3616 .port_set_ether_type = mv88e6351_port_set_ether_type, 3617 .port_jumbo_config = mv88e6165_port_jumbo_config, 3618 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3619 .port_pause_config = mv88e6097_port_pause_config, 3620 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3621 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3622 .stats_get_strings = mv88e6320_stats_get_strings, 3623 .stats_get_stats = mv88e6320_stats_get_stats, 3624 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3625 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3626 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3627 }; 3628 3629 static const struct mv88e6xxx_ops mv88e6321_ops = { 3630 /* MV88E6XXX_FAMILY_6321 */ 3631 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3632 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3634 .phy_read = mv88e6xxx_g2_smi_phy_read, 3635 .phy_write = mv88e6xxx_g2_smi_phy_write, 3636 .port_set_link = mv88e6xxx_port_set_link, 3637 .port_set_duplex = mv88e6xxx_port_set_duplex, 3638 .port_set_speed = mv88e6185_port_set_speed, 3639 .port_tag_remap = mv88e6095_port_tag_remap, 3640 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3641 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3642 .port_set_ether_type = mv88e6351_port_set_ether_type, 3643 .port_jumbo_config = mv88e6165_port_jumbo_config, 3644 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3645 .port_pause_config = mv88e6097_port_pause_config, 3646 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3647 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3648 .stats_get_strings = mv88e6320_stats_get_strings, 3649 .stats_get_stats = mv88e6320_stats_get_stats, 3650 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3651 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3652 }; 3653 3654 static const struct mv88e6xxx_ops mv88e6350_ops = { 3655 /* MV88E6XXX_FAMILY_6351 */ 3656 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3657 .phy_read = mv88e6xxx_g2_smi_phy_read, 3658 .phy_write = mv88e6xxx_g2_smi_phy_write, 3659 .port_set_link = mv88e6xxx_port_set_link, 3660 .port_set_duplex = mv88e6xxx_port_set_duplex, 3661 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3662 .port_set_speed = mv88e6185_port_set_speed, 3663 .port_tag_remap = mv88e6095_port_tag_remap, 3664 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3665 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3666 .port_set_ether_type = mv88e6351_port_set_ether_type, 3667 .port_jumbo_config = mv88e6165_port_jumbo_config, 3668 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3669 .port_pause_config = mv88e6097_port_pause_config, 3670 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3671 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3672 .stats_get_strings = mv88e6095_stats_get_strings, 3673 .stats_get_stats = mv88e6095_stats_get_stats, 3674 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3675 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3676 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3677 }; 3678 3679 static const struct mv88e6xxx_ops mv88e6351_ops = { 3680 /* MV88E6XXX_FAMILY_6351 */ 3681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3682 .phy_read = mv88e6xxx_g2_smi_phy_read, 3683 .phy_write = mv88e6xxx_g2_smi_phy_write, 3684 .port_set_link = mv88e6xxx_port_set_link, 3685 .port_set_duplex = mv88e6xxx_port_set_duplex, 3686 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3687 .port_set_speed = mv88e6185_port_set_speed, 3688 .port_tag_remap = mv88e6095_port_tag_remap, 3689 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3690 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3691 .port_set_ether_type = mv88e6351_port_set_ether_type, 3692 .port_jumbo_config = mv88e6165_port_jumbo_config, 3693 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3694 .port_pause_config = mv88e6097_port_pause_config, 3695 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3696 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3697 .stats_get_strings = mv88e6095_stats_get_strings, 3698 .stats_get_stats = mv88e6095_stats_get_stats, 3699 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3700 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3701 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3702 }; 3703 3704 static const struct mv88e6xxx_ops mv88e6352_ops = { 3705 /* MV88E6XXX_FAMILY_6352 */ 3706 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3707 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3708 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3709 .phy_read = mv88e6xxx_g2_smi_phy_read, 3710 .phy_write = mv88e6xxx_g2_smi_phy_write, 3711 .port_set_link = mv88e6xxx_port_set_link, 3712 .port_set_duplex = mv88e6xxx_port_set_duplex, 3713 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3714 .port_set_speed = mv88e6352_port_set_speed, 3715 .port_tag_remap = mv88e6095_port_tag_remap, 3716 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3717 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3718 .port_set_ether_type = mv88e6351_port_set_ether_type, 3719 .port_jumbo_config = mv88e6165_port_jumbo_config, 3720 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3721 .port_pause_config = mv88e6097_port_pause_config, 3722 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3723 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3724 .stats_get_strings = mv88e6095_stats_get_strings, 3725 .stats_get_stats = mv88e6095_stats_get_stats, 3726 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3727 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3728 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3729 }; 3730 3731 static const struct mv88e6xxx_ops mv88e6390_ops = { 3732 /* MV88E6XXX_FAMILY_6390 */ 3733 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3734 .phy_read = mv88e6xxx_g2_smi_phy_read, 3735 .phy_write = mv88e6xxx_g2_smi_phy_write, 3736 .port_set_link = mv88e6xxx_port_set_link, 3737 .port_set_duplex = mv88e6xxx_port_set_duplex, 3738 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3739 .port_set_speed = mv88e6390_port_set_speed, 3740 .port_tag_remap = mv88e6390_port_tag_remap, 3741 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3742 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3743 .port_set_ether_type = mv88e6351_port_set_ether_type, 3744 .port_jumbo_config = mv88e6165_port_jumbo_config, 3745 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3746 .port_pause_config = mv88e6390_port_pause_config, 3747 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3748 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3749 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3750 .stats_get_strings = mv88e6320_stats_get_strings, 3751 .stats_get_stats = mv88e6390_stats_get_stats, 3752 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3753 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3754 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3755 }; 3756 3757 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3758 /* MV88E6XXX_FAMILY_6390 */ 3759 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3760 .phy_read = mv88e6xxx_g2_smi_phy_read, 3761 .phy_write = mv88e6xxx_g2_smi_phy_write, 3762 .port_set_link = mv88e6xxx_port_set_link, 3763 .port_set_duplex = mv88e6xxx_port_set_duplex, 3764 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3765 .port_set_speed = mv88e6390x_port_set_speed, 3766 .port_tag_remap = mv88e6390_port_tag_remap, 3767 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3768 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3769 .port_set_ether_type = mv88e6351_port_set_ether_type, 3770 .port_jumbo_config = mv88e6165_port_jumbo_config, 3771 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3772 .port_pause_config = mv88e6390_port_pause_config, 3773 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3774 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3775 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3776 .stats_get_strings = mv88e6320_stats_get_strings, 3777 .stats_get_stats = mv88e6390_stats_get_stats, 3778 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3779 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3780 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3781 }; 3782 3783 static const struct mv88e6xxx_ops mv88e6391_ops = { 3784 /* MV88E6XXX_FAMILY_6390 */ 3785 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3786 .phy_read = mv88e6xxx_g2_smi_phy_read, 3787 .phy_write = mv88e6xxx_g2_smi_phy_write, 3788 .port_set_link = mv88e6xxx_port_set_link, 3789 .port_set_duplex = mv88e6xxx_port_set_duplex, 3790 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3791 .port_set_speed = mv88e6390_port_set_speed, 3792 .port_tag_remap = mv88e6390_port_tag_remap, 3793 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3794 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3795 .port_set_ether_type = mv88e6351_port_set_ether_type, 3796 .port_pause_config = mv88e6390_port_pause_config, 3797 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3798 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3799 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3800 .stats_get_strings = mv88e6320_stats_get_strings, 3801 .stats_get_stats = mv88e6390_stats_get_stats, 3802 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3803 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3804 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3805 }; 3806 3807 static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip, 3808 const struct mv88e6xxx_ops *ops) 3809 { 3810 if (!ops->port_set_frame_mode) { 3811 dev_err(chip->dev, "Missing port_set_frame_mode"); 3812 return -EINVAL; 3813 } 3814 3815 if (!ops->port_set_egress_unknowns) { 3816 dev_err(chip->dev, "Missing port_set_egress_mode"); 3817 return -EINVAL; 3818 } 3819 3820 return 0; 3821 } 3822 3823 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3824 [MV88E6085] = { 3825 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, 3826 .family = MV88E6XXX_FAMILY_6097, 3827 .name = "Marvell 88E6085", 3828 .num_databases = 4096, 3829 .num_ports = 10, 3830 .port_base_addr = 0x10, 3831 .global1_addr = 0x1b, 3832 .age_time_coeff = 15000, 3833 .g1_irqs = 8, 3834 .tag_protocol = DSA_TAG_PROTO_DSA, 3835 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3836 .ops = &mv88e6085_ops, 3837 }, 3838 3839 [MV88E6095] = { 3840 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, 3841 .family = MV88E6XXX_FAMILY_6095, 3842 .name = "Marvell 88E6095/88E6095F", 3843 .num_databases = 256, 3844 .num_ports = 11, 3845 .port_base_addr = 0x10, 3846 .global1_addr = 0x1b, 3847 .age_time_coeff = 15000, 3848 .g1_irqs = 8, 3849 .tag_protocol = DSA_TAG_PROTO_DSA, 3850 .flags = MV88E6XXX_FLAGS_FAMILY_6095, 3851 .ops = &mv88e6095_ops, 3852 }, 3853 3854 [MV88E6097] = { 3855 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097, 3856 .family = MV88E6XXX_FAMILY_6097, 3857 .name = "Marvell 88E6097/88E6097F", 3858 .num_databases = 4096, 3859 .num_ports = 11, 3860 .port_base_addr = 0x10, 3861 .global1_addr = 0x1b, 3862 .age_time_coeff = 15000, 3863 .g1_irqs = 8, 3864 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3865 .ops = &mv88e6097_ops, 3866 }, 3867 3868 [MV88E6123] = { 3869 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, 3870 .family = MV88E6XXX_FAMILY_6165, 3871 .name = "Marvell 88E6123", 3872 .num_databases = 4096, 3873 .num_ports = 3, 3874 .port_base_addr = 0x10, 3875 .global1_addr = 0x1b, 3876 .age_time_coeff = 15000, 3877 .g1_irqs = 9, 3878 .tag_protocol = DSA_TAG_PROTO_DSA, 3879 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3880 .ops = &mv88e6123_ops, 3881 }, 3882 3883 [MV88E6131] = { 3884 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, 3885 .family = MV88E6XXX_FAMILY_6185, 3886 .name = "Marvell 88E6131", 3887 .num_databases = 256, 3888 .num_ports = 8, 3889 .port_base_addr = 0x10, 3890 .global1_addr = 0x1b, 3891 .age_time_coeff = 15000, 3892 .g1_irqs = 9, 3893 .tag_protocol = DSA_TAG_PROTO_DSA, 3894 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3895 .ops = &mv88e6131_ops, 3896 }, 3897 3898 [MV88E6161] = { 3899 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, 3900 .family = MV88E6XXX_FAMILY_6165, 3901 .name = "Marvell 88E6161", 3902 .num_databases = 4096, 3903 .num_ports = 6, 3904 .port_base_addr = 0x10, 3905 .global1_addr = 0x1b, 3906 .age_time_coeff = 15000, 3907 .g1_irqs = 9, 3908 .tag_protocol = DSA_TAG_PROTO_DSA, 3909 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3910 .ops = &mv88e6161_ops, 3911 }, 3912 3913 [MV88E6165] = { 3914 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, 3915 .family = MV88E6XXX_FAMILY_6165, 3916 .name = "Marvell 88E6165", 3917 .num_databases = 4096, 3918 .num_ports = 6, 3919 .port_base_addr = 0x10, 3920 .global1_addr = 0x1b, 3921 .age_time_coeff = 15000, 3922 .g1_irqs = 9, 3923 .tag_protocol = DSA_TAG_PROTO_DSA, 3924 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3925 .ops = &mv88e6165_ops, 3926 }, 3927 3928 [MV88E6171] = { 3929 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, 3930 .family = MV88E6XXX_FAMILY_6351, 3931 .name = "Marvell 88E6171", 3932 .num_databases = 4096, 3933 .num_ports = 7, 3934 .port_base_addr = 0x10, 3935 .global1_addr = 0x1b, 3936 .age_time_coeff = 15000, 3937 .g1_irqs = 9, 3938 .tag_protocol = DSA_TAG_PROTO_EDSA, 3939 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3940 .ops = &mv88e6171_ops, 3941 }, 3942 3943 [MV88E6172] = { 3944 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, 3945 .family = MV88E6XXX_FAMILY_6352, 3946 .name = "Marvell 88E6172", 3947 .num_databases = 4096, 3948 .num_ports = 7, 3949 .port_base_addr = 0x10, 3950 .global1_addr = 0x1b, 3951 .age_time_coeff = 15000, 3952 .g1_irqs = 9, 3953 .tag_protocol = DSA_TAG_PROTO_EDSA, 3954 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3955 .ops = &mv88e6172_ops, 3956 }, 3957 3958 [MV88E6175] = { 3959 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, 3960 .family = MV88E6XXX_FAMILY_6351, 3961 .name = "Marvell 88E6175", 3962 .num_databases = 4096, 3963 .num_ports = 7, 3964 .port_base_addr = 0x10, 3965 .global1_addr = 0x1b, 3966 .age_time_coeff = 15000, 3967 .g1_irqs = 9, 3968 .tag_protocol = DSA_TAG_PROTO_EDSA, 3969 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3970 .ops = &mv88e6175_ops, 3971 }, 3972 3973 [MV88E6176] = { 3974 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, 3975 .family = MV88E6XXX_FAMILY_6352, 3976 .name = "Marvell 88E6176", 3977 .num_databases = 4096, 3978 .num_ports = 7, 3979 .port_base_addr = 0x10, 3980 .global1_addr = 0x1b, 3981 .age_time_coeff = 15000, 3982 .g1_irqs = 9, 3983 .tag_protocol = DSA_TAG_PROTO_EDSA, 3984 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3985 .ops = &mv88e6176_ops, 3986 }, 3987 3988 [MV88E6185] = { 3989 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, 3990 .family = MV88E6XXX_FAMILY_6185, 3991 .name = "Marvell 88E6185", 3992 .num_databases = 256, 3993 .num_ports = 10, 3994 .port_base_addr = 0x10, 3995 .global1_addr = 0x1b, 3996 .age_time_coeff = 15000, 3997 .g1_irqs = 8, 3998 .tag_protocol = DSA_TAG_PROTO_EDSA, 3999 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 4000 .ops = &mv88e6185_ops, 4001 }, 4002 4003 [MV88E6190] = { 4004 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190, 4005 .family = MV88E6XXX_FAMILY_6390, 4006 .name = "Marvell 88E6190", 4007 .num_databases = 4096, 4008 .num_ports = 11, /* 10 + Z80 */ 4009 .port_base_addr = 0x0, 4010 .global1_addr = 0x1b, 4011 .tag_protocol = DSA_TAG_PROTO_DSA, 4012 .age_time_coeff = 15000, 4013 .g1_irqs = 9, 4014 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4015 .ops = &mv88e6190_ops, 4016 }, 4017 4018 [MV88E6190X] = { 4019 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X, 4020 .family = MV88E6XXX_FAMILY_6390, 4021 .name = "Marvell 88E6190X", 4022 .num_databases = 4096, 4023 .num_ports = 11, /* 10 + Z80 */ 4024 .port_base_addr = 0x0, 4025 .global1_addr = 0x1b, 4026 .age_time_coeff = 15000, 4027 .g1_irqs = 9, 4028 .tag_protocol = DSA_TAG_PROTO_DSA, 4029 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4030 .ops = &mv88e6190x_ops, 4031 }, 4032 4033 [MV88E6191] = { 4034 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191, 4035 .family = MV88E6XXX_FAMILY_6390, 4036 .name = "Marvell 88E6191", 4037 .num_databases = 4096, 4038 .num_ports = 11, /* 10 + Z80 */ 4039 .port_base_addr = 0x0, 4040 .global1_addr = 0x1b, 4041 .age_time_coeff = 15000, 4042 .g1_irqs = 9, 4043 .tag_protocol = DSA_TAG_PROTO_DSA, 4044 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4045 .ops = &mv88e6391_ops, 4046 }, 4047 4048 [MV88E6240] = { 4049 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, 4050 .family = MV88E6XXX_FAMILY_6352, 4051 .name = "Marvell 88E6240", 4052 .num_databases = 4096, 4053 .num_ports = 7, 4054 .port_base_addr = 0x10, 4055 .global1_addr = 0x1b, 4056 .age_time_coeff = 15000, 4057 .g1_irqs = 9, 4058 .tag_protocol = DSA_TAG_PROTO_EDSA, 4059 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4060 .ops = &mv88e6240_ops, 4061 }, 4062 4063 [MV88E6290] = { 4064 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290, 4065 .family = MV88E6XXX_FAMILY_6390, 4066 .name = "Marvell 88E6290", 4067 .num_databases = 4096, 4068 .num_ports = 11, /* 10 + Z80 */ 4069 .port_base_addr = 0x0, 4070 .global1_addr = 0x1b, 4071 .age_time_coeff = 15000, 4072 .g1_irqs = 9, 4073 .tag_protocol = DSA_TAG_PROTO_DSA, 4074 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4075 .ops = &mv88e6290_ops, 4076 }, 4077 4078 [MV88E6320] = { 4079 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, 4080 .family = MV88E6XXX_FAMILY_6320, 4081 .name = "Marvell 88E6320", 4082 .num_databases = 4096, 4083 .num_ports = 7, 4084 .port_base_addr = 0x10, 4085 .global1_addr = 0x1b, 4086 .age_time_coeff = 15000, 4087 .g1_irqs = 8, 4088 .tag_protocol = DSA_TAG_PROTO_EDSA, 4089 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4090 .ops = &mv88e6320_ops, 4091 }, 4092 4093 [MV88E6321] = { 4094 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, 4095 .family = MV88E6XXX_FAMILY_6320, 4096 .name = "Marvell 88E6321", 4097 .num_databases = 4096, 4098 .num_ports = 7, 4099 .port_base_addr = 0x10, 4100 .global1_addr = 0x1b, 4101 .age_time_coeff = 15000, 4102 .g1_irqs = 8, 4103 .tag_protocol = DSA_TAG_PROTO_EDSA, 4104 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4105 .ops = &mv88e6321_ops, 4106 }, 4107 4108 [MV88E6350] = { 4109 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, 4110 .family = MV88E6XXX_FAMILY_6351, 4111 .name = "Marvell 88E6350", 4112 .num_databases = 4096, 4113 .num_ports = 7, 4114 .port_base_addr = 0x10, 4115 .global1_addr = 0x1b, 4116 .age_time_coeff = 15000, 4117 .g1_irqs = 9, 4118 .tag_protocol = DSA_TAG_PROTO_EDSA, 4119 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4120 .ops = &mv88e6350_ops, 4121 }, 4122 4123 [MV88E6351] = { 4124 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, 4125 .family = MV88E6XXX_FAMILY_6351, 4126 .name = "Marvell 88E6351", 4127 .num_databases = 4096, 4128 .num_ports = 7, 4129 .port_base_addr = 0x10, 4130 .global1_addr = 0x1b, 4131 .age_time_coeff = 15000, 4132 .g1_irqs = 9, 4133 .tag_protocol = DSA_TAG_PROTO_EDSA, 4134 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4135 .ops = &mv88e6351_ops, 4136 }, 4137 4138 [MV88E6352] = { 4139 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, 4140 .family = MV88E6XXX_FAMILY_6352, 4141 .name = "Marvell 88E6352", 4142 .num_databases = 4096, 4143 .num_ports = 7, 4144 .port_base_addr = 0x10, 4145 .global1_addr = 0x1b, 4146 .age_time_coeff = 15000, 4147 .g1_irqs = 9, 4148 .tag_protocol = DSA_TAG_PROTO_EDSA, 4149 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4150 .ops = &mv88e6352_ops, 4151 }, 4152 [MV88E6390] = { 4153 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390, 4154 .family = MV88E6XXX_FAMILY_6390, 4155 .name = "Marvell 88E6390", 4156 .num_databases = 4096, 4157 .num_ports = 11, /* 10 + Z80 */ 4158 .port_base_addr = 0x0, 4159 .global1_addr = 0x1b, 4160 .age_time_coeff = 15000, 4161 .g1_irqs = 9, 4162 .tag_protocol = DSA_TAG_PROTO_DSA, 4163 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4164 .ops = &mv88e6390_ops, 4165 }, 4166 [MV88E6390X] = { 4167 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X, 4168 .family = MV88E6XXX_FAMILY_6390, 4169 .name = "Marvell 88E6390X", 4170 .num_databases = 4096, 4171 .num_ports = 11, /* 10 + Z80 */ 4172 .port_base_addr = 0x0, 4173 .global1_addr = 0x1b, 4174 .age_time_coeff = 15000, 4175 .g1_irqs = 9, 4176 .tag_protocol = DSA_TAG_PROTO_DSA, 4177 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4178 .ops = &mv88e6390x_ops, 4179 }, 4180 }; 4181 4182 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4183 { 4184 int i; 4185 4186 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4187 if (mv88e6xxx_table[i].prod_num == prod_num) 4188 return &mv88e6xxx_table[i]; 4189 4190 return NULL; 4191 } 4192 4193 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4194 { 4195 const struct mv88e6xxx_info *info; 4196 unsigned int prod_num, rev; 4197 u16 id; 4198 int err; 4199 4200 mutex_lock(&chip->reg_lock); 4201 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); 4202 mutex_unlock(&chip->reg_lock); 4203 if (err) 4204 return err; 4205 4206 prod_num = (id & 0xfff0) >> 4; 4207 rev = id & 0x000f; 4208 4209 info = mv88e6xxx_lookup_info(prod_num); 4210 if (!info) 4211 return -ENODEV; 4212 4213 /* Update the compatible info with the probed one */ 4214 chip->info = info; 4215 4216 err = mv88e6xxx_g2_require(chip); 4217 if (err) 4218 return err; 4219 4220 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4221 chip->info->prod_num, chip->info->name, rev); 4222 4223 return 0; 4224 } 4225 4226 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4227 { 4228 struct mv88e6xxx_chip *chip; 4229 4230 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4231 if (!chip) 4232 return NULL; 4233 4234 chip->dev = dev; 4235 4236 mutex_init(&chip->reg_lock); 4237 4238 return chip; 4239 } 4240 4241 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) 4242 { 4243 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) 4244 mv88e6xxx_ppu_state_init(chip); 4245 } 4246 4247 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) 4248 { 4249 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) 4250 mv88e6xxx_ppu_state_destroy(chip); 4251 } 4252 4253 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4254 struct mii_bus *bus, int sw_addr) 4255 { 4256 /* ADDR[0] pin is unavailable externally and considered zero */ 4257 if (sw_addr & 0x1) 4258 return -EINVAL; 4259 4260 if (sw_addr == 0) 4261 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4262 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) 4263 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4264 else 4265 return -EINVAL; 4266 4267 chip->bus = bus; 4268 chip->sw_addr = sw_addr; 4269 4270 return 0; 4271 } 4272 4273 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 4274 { 4275 struct mv88e6xxx_chip *chip = ds->priv; 4276 4277 return chip->info->tag_protocol; 4278 } 4279 4280 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4281 struct device *host_dev, int sw_addr, 4282 void **priv) 4283 { 4284 struct mv88e6xxx_chip *chip; 4285 struct mii_bus *bus; 4286 int err; 4287 4288 bus = dsa_host_dev_to_mii_bus(host_dev); 4289 if (!bus) 4290 return NULL; 4291 4292 chip = mv88e6xxx_alloc_chip(dsa_dev); 4293 if (!chip) 4294 return NULL; 4295 4296 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4297 chip->info = &mv88e6xxx_table[MV88E6085]; 4298 4299 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4300 if (err) 4301 goto free; 4302 4303 err = mv88e6xxx_detect(chip); 4304 if (err) 4305 goto free; 4306 4307 mutex_lock(&chip->reg_lock); 4308 err = mv88e6xxx_switch_reset(chip); 4309 mutex_unlock(&chip->reg_lock); 4310 if (err) 4311 goto free; 4312 4313 mv88e6xxx_phy_init(chip); 4314 4315 err = mv88e6xxx_mdio_register(chip, NULL); 4316 if (err) 4317 goto free; 4318 4319 *priv = chip; 4320 4321 return chip->info->name; 4322 free: 4323 devm_kfree(dsa_dev, chip); 4324 4325 return NULL; 4326 } 4327 4328 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4329 const struct switchdev_obj_port_mdb *mdb, 4330 struct switchdev_trans *trans) 4331 { 4332 /* We don't need any dynamic resource from the kernel (yet), 4333 * so skip the prepare phase. 4334 */ 4335 4336 return 0; 4337 } 4338 4339 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4340 const struct switchdev_obj_port_mdb *mdb, 4341 struct switchdev_trans *trans) 4342 { 4343 struct mv88e6xxx_chip *chip = ds->priv; 4344 4345 mutex_lock(&chip->reg_lock); 4346 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4347 GLOBAL_ATU_DATA_STATE_MC_STATIC)) 4348 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); 4349 mutex_unlock(&chip->reg_lock); 4350 } 4351 4352 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4353 const struct switchdev_obj_port_mdb *mdb) 4354 { 4355 struct mv88e6xxx_chip *chip = ds->priv; 4356 int err; 4357 4358 mutex_lock(&chip->reg_lock); 4359 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4360 GLOBAL_ATU_DATA_STATE_UNUSED); 4361 mutex_unlock(&chip->reg_lock); 4362 4363 return err; 4364 } 4365 4366 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, 4367 struct switchdev_obj_port_mdb *mdb, 4368 int (*cb)(struct switchdev_obj *obj)) 4369 { 4370 struct mv88e6xxx_chip *chip = ds->priv; 4371 int err; 4372 4373 mutex_lock(&chip->reg_lock); 4374 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); 4375 mutex_unlock(&chip->reg_lock); 4376 4377 return err; 4378 } 4379 4380 static struct dsa_switch_ops mv88e6xxx_switch_ops = { 4381 .probe = mv88e6xxx_drv_probe, 4382 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4383 .setup = mv88e6xxx_setup, 4384 .set_addr = mv88e6xxx_set_addr, 4385 .adjust_link = mv88e6xxx_adjust_link, 4386 .get_strings = mv88e6xxx_get_strings, 4387 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4388 .get_sset_count = mv88e6xxx_get_sset_count, 4389 .set_eee = mv88e6xxx_set_eee, 4390 .get_eee = mv88e6xxx_get_eee, 4391 #ifdef CONFIG_NET_DSA_HWMON 4392 .get_temp = mv88e6xxx_get_temp, 4393 .get_temp_limit = mv88e6xxx_get_temp_limit, 4394 .set_temp_limit = mv88e6xxx_set_temp_limit, 4395 .get_temp_alarm = mv88e6xxx_get_temp_alarm, 4396 #endif 4397 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4398 .get_eeprom = mv88e6xxx_get_eeprom, 4399 .set_eeprom = mv88e6xxx_set_eeprom, 4400 .get_regs_len = mv88e6xxx_get_regs_len, 4401 .get_regs = mv88e6xxx_get_regs, 4402 .set_ageing_time = mv88e6xxx_set_ageing_time, 4403 .port_bridge_join = mv88e6xxx_port_bridge_join, 4404 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4405 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4406 .port_fast_age = mv88e6xxx_port_fast_age, 4407 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4408 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4409 .port_vlan_add = mv88e6xxx_port_vlan_add, 4410 .port_vlan_del = mv88e6xxx_port_vlan_del, 4411 .port_vlan_dump = mv88e6xxx_port_vlan_dump, 4412 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, 4413 .port_fdb_add = mv88e6xxx_port_fdb_add, 4414 .port_fdb_del = mv88e6xxx_port_fdb_del, 4415 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4416 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4417 .port_mdb_add = mv88e6xxx_port_mdb_add, 4418 .port_mdb_del = mv88e6xxx_port_mdb_del, 4419 .port_mdb_dump = mv88e6xxx_port_mdb_dump, 4420 }; 4421 4422 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, 4423 struct device_node *np) 4424 { 4425 struct device *dev = chip->dev; 4426 struct dsa_switch *ds; 4427 4428 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 4429 if (!ds) 4430 return -ENOMEM; 4431 4432 ds->dev = dev; 4433 ds->priv = chip; 4434 ds->ops = &mv88e6xxx_switch_ops; 4435 4436 dev_set_drvdata(dev, ds); 4437 4438 return dsa_register_switch(ds, np); 4439 } 4440 4441 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4442 { 4443 dsa_unregister_switch(chip->ds); 4444 } 4445 4446 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4447 { 4448 struct device *dev = &mdiodev->dev; 4449 struct device_node *np = dev->of_node; 4450 const struct mv88e6xxx_info *compat_info; 4451 struct mv88e6xxx_chip *chip; 4452 u32 eeprom_len; 4453 int err; 4454 4455 compat_info = of_device_get_match_data(dev); 4456 if (!compat_info) 4457 return -EINVAL; 4458 4459 chip = mv88e6xxx_alloc_chip(dev); 4460 if (!chip) 4461 return -ENOMEM; 4462 4463 chip->info = compat_info; 4464 4465 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops); 4466 if (err) 4467 return err; 4468 4469 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4470 if (err) 4471 return err; 4472 4473 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4474 if (IS_ERR(chip->reset)) 4475 return PTR_ERR(chip->reset); 4476 4477 err = mv88e6xxx_detect(chip); 4478 if (err) 4479 return err; 4480 4481 mv88e6xxx_phy_init(chip); 4482 4483 if (chip->info->ops->get_eeprom && 4484 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 4485 chip->eeprom_len = eeprom_len; 4486 4487 mutex_lock(&chip->reg_lock); 4488 err = mv88e6xxx_switch_reset(chip); 4489 mutex_unlock(&chip->reg_lock); 4490 if (err) 4491 goto out; 4492 4493 chip->irq = of_irq_get(np, 0); 4494 if (chip->irq == -EPROBE_DEFER) { 4495 err = chip->irq; 4496 goto out; 4497 } 4498 4499 if (chip->irq > 0) { 4500 /* Has to be performed before the MDIO bus is created, 4501 * because the PHYs will link there interrupts to these 4502 * interrupt controllers 4503 */ 4504 mutex_lock(&chip->reg_lock); 4505 err = mv88e6xxx_g1_irq_setup(chip); 4506 mutex_unlock(&chip->reg_lock); 4507 4508 if (err) 4509 goto out; 4510 4511 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { 4512 err = mv88e6xxx_g2_irq_setup(chip); 4513 if (err) 4514 goto out_g1_irq; 4515 } 4516 } 4517 4518 err = mv88e6xxx_mdio_register(chip, np); 4519 if (err) 4520 goto out_g2_irq; 4521 4522 err = mv88e6xxx_register_switch(chip, np); 4523 if (err) 4524 goto out_mdio; 4525 4526 return 0; 4527 4528 out_mdio: 4529 mv88e6xxx_mdio_unregister(chip); 4530 out_g2_irq: 4531 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) 4532 mv88e6xxx_g2_irq_free(chip); 4533 out_g1_irq: 4534 if (chip->irq > 0) { 4535 mutex_lock(&chip->reg_lock); 4536 mv88e6xxx_g1_irq_free(chip); 4537 mutex_unlock(&chip->reg_lock); 4538 } 4539 out: 4540 return err; 4541 } 4542 4543 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4544 { 4545 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4546 struct mv88e6xxx_chip *chip = ds->priv; 4547 4548 mv88e6xxx_phy_destroy(chip); 4549 mv88e6xxx_unregister_switch(chip); 4550 mv88e6xxx_mdio_unregister(chip); 4551 4552 if (chip->irq > 0) { 4553 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) 4554 mv88e6xxx_g2_irq_free(chip); 4555 mv88e6xxx_g1_irq_free(chip); 4556 } 4557 } 4558 4559 static const struct of_device_id mv88e6xxx_of_match[] = { 4560 { 4561 .compatible = "marvell,mv88e6085", 4562 .data = &mv88e6xxx_table[MV88E6085], 4563 }, 4564 { 4565 .compatible = "marvell,mv88e6190", 4566 .data = &mv88e6xxx_table[MV88E6190], 4567 }, 4568 { /* sentinel */ }, 4569 }; 4570 4571 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4572 4573 static struct mdio_driver mv88e6xxx_driver = { 4574 .probe = mv88e6xxx_probe, 4575 .remove = mv88e6xxx_remove, 4576 .mdiodrv.driver = { 4577 .name = "mv88e6085", 4578 .of_match_table = mv88e6xxx_of_match, 4579 }, 4580 }; 4581 4582 static int __init mv88e6xxx_init(void) 4583 { 4584 register_switch_driver(&mv88e6xxx_switch_ops); 4585 return mdio_driver_register(&mv88e6xxx_driver); 4586 } 4587 module_init(mv88e6xxx_init); 4588 4589 static void __exit mv88e6xxx_cleanup(void) 4590 { 4591 mdio_driver_unregister(&mv88e6xxx_driver); 4592 unregister_switch_driver(&mv88e6xxx_switch_ops); 4593 } 4594 module_exit(mv88e6xxx_cleanup); 4595 4596 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4597 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4598 MODULE_LICENSE("GPL"); 4599