1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 475 if (err) { 476 dev_err(chip->dev, 477 "p%d: %s: failed to read port status\n", 478 port, __func__); 479 return err; 480 } 481 482 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 483 } 484 485 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 486 struct phylink_link_state *state) 487 { 488 struct mv88e6xxx_chip *chip = ds->priv; 489 int lane; 490 int err; 491 492 mv88e6xxx_reg_lock(chip); 493 lane = mv88e6xxx_serdes_get_lane(chip, port); 494 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 495 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 496 state); 497 else 498 err = -EOPNOTSUPP; 499 mv88e6xxx_reg_unlock(chip); 500 501 return err; 502 } 503 504 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 505 unsigned int mode, 506 phy_interface_t interface, 507 const unsigned long *advertise) 508 { 509 const struct mv88e6xxx_ops *ops = chip->info->ops; 510 int lane; 511 512 if (ops->serdes_pcs_config) { 513 lane = mv88e6xxx_serdes_get_lane(chip, port); 514 if (lane >= 0) 515 return ops->serdes_pcs_config(chip, port, lane, mode, 516 interface, advertise); 517 } 518 519 return 0; 520 } 521 522 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 523 { 524 struct mv88e6xxx_chip *chip = ds->priv; 525 const struct mv88e6xxx_ops *ops; 526 int err = 0; 527 int lane; 528 529 ops = chip->info->ops; 530 531 if (ops->serdes_pcs_an_restart) { 532 mv88e6xxx_reg_lock(chip); 533 lane = mv88e6xxx_serdes_get_lane(chip, port); 534 if (lane >= 0) 535 err = ops->serdes_pcs_an_restart(chip, port, lane); 536 mv88e6xxx_reg_unlock(chip); 537 538 if (err) 539 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 540 } 541 } 542 543 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 544 unsigned int mode, 545 int speed, int duplex) 546 { 547 const struct mv88e6xxx_ops *ops = chip->info->ops; 548 int lane; 549 550 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 551 lane = mv88e6xxx_serdes_get_lane(chip, port); 552 if (lane >= 0) 553 return ops->serdes_pcs_link_up(chip, port, lane, 554 speed, duplex); 555 } 556 557 return 0; 558 } 559 560 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 561 unsigned long *mask, 562 struct phylink_link_state *state) 563 { 564 if (!phy_interface_mode_is_8023z(state->interface)) { 565 /* 10M and 100M are only supported in non-802.3z mode */ 566 phylink_set(mask, 10baseT_Half); 567 phylink_set(mask, 10baseT_Full); 568 phylink_set(mask, 100baseT_Half); 569 phylink_set(mask, 100baseT_Full); 570 } 571 } 572 573 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 574 unsigned long *mask, 575 struct phylink_link_state *state) 576 { 577 /* FIXME: if the port is in 1000Base-X mode, then it only supports 578 * 1000M FD speeds. In this case, CMODE will indicate 5. 579 */ 580 phylink_set(mask, 1000baseT_Full); 581 phylink_set(mask, 1000baseX_Full); 582 583 mv88e6065_phylink_validate(chip, port, mask, state); 584 } 585 586 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 587 unsigned long *mask, 588 struct phylink_link_state *state) 589 { 590 if (port >= 5) 591 phylink_set(mask, 2500baseX_Full); 592 593 /* No ethtool bits for 200Mbps */ 594 phylink_set(mask, 1000baseT_Full); 595 phylink_set(mask, 1000baseX_Full); 596 597 mv88e6065_phylink_validate(chip, port, mask, state); 598 } 599 600 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 601 unsigned long *mask, 602 struct phylink_link_state *state) 603 { 604 /* No ethtool bits for 200Mbps */ 605 phylink_set(mask, 1000baseT_Full); 606 phylink_set(mask, 1000baseX_Full); 607 608 mv88e6065_phylink_validate(chip, port, mask, state); 609 } 610 611 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 612 unsigned long *mask, 613 struct phylink_link_state *state) 614 { 615 if (port >= 9) { 616 phylink_set(mask, 2500baseX_Full); 617 phylink_set(mask, 2500baseT_Full); 618 } 619 620 /* No ethtool bits for 200Mbps */ 621 phylink_set(mask, 1000baseT_Full); 622 phylink_set(mask, 1000baseX_Full); 623 624 mv88e6065_phylink_validate(chip, port, mask, state); 625 } 626 627 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 628 unsigned long *mask, 629 struct phylink_link_state *state) 630 { 631 if (port >= 9) { 632 phylink_set(mask, 10000baseT_Full); 633 phylink_set(mask, 10000baseKR_Full); 634 } 635 636 mv88e6390_phylink_validate(chip, port, mask, state); 637 } 638 639 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 640 unsigned long *mask, 641 struct phylink_link_state *state) 642 { 643 if (port == 0 || port == 9 || port == 10) { 644 phylink_set(mask, 10000baseT_Full); 645 phylink_set(mask, 10000baseKR_Full); 646 phylink_set(mask, 10000baseCR_Full); 647 phylink_set(mask, 10000baseSR_Full); 648 phylink_set(mask, 10000baseLR_Full); 649 phylink_set(mask, 10000baseLRM_Full); 650 phylink_set(mask, 10000baseER_Full); 651 phylink_set(mask, 5000baseT_Full); 652 phylink_set(mask, 2500baseX_Full); 653 phylink_set(mask, 2500baseT_Full); 654 } 655 656 phylink_set(mask, 1000baseT_Full); 657 phylink_set(mask, 1000baseX_Full); 658 659 mv88e6065_phylink_validate(chip, port, mask, state); 660 } 661 662 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 663 unsigned long *supported, 664 struct phylink_link_state *state) 665 { 666 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 667 struct mv88e6xxx_chip *chip = ds->priv; 668 669 /* Allow all the expected bits */ 670 phylink_set(mask, Autoneg); 671 phylink_set(mask, Pause); 672 phylink_set_port_modes(mask); 673 674 if (chip->info->ops->phylink_validate) 675 chip->info->ops->phylink_validate(chip, port, mask, state); 676 677 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 678 bitmap_and(state->advertising, state->advertising, mask, 679 __ETHTOOL_LINK_MODE_MASK_NBITS); 680 681 /* We can only operate at 2500BaseX or 1000BaseX. If requested 682 * to advertise both, only report advertising at 2500BaseX. 683 */ 684 phylink_helper_basex_speed(state); 685 } 686 687 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 688 unsigned int mode, 689 const struct phylink_link_state *state) 690 { 691 struct mv88e6xxx_chip *chip = ds->priv; 692 struct mv88e6xxx_port *p; 693 int err; 694 695 p = &chip->ports[port]; 696 697 /* FIXME: is this the correct test? If we're in fixed mode on an 698 * internal port, why should we process this any different from 699 * PHY mode? On the other hand, the port may be automedia between 700 * an internal PHY and the serdes... 701 */ 702 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 703 return; 704 705 mv88e6xxx_reg_lock(chip); 706 /* In inband mode, the link may come up at any time while the link 707 * is not forced down. Force the link down while we reconfigure the 708 * interface mode. 709 */ 710 if (mode == MLO_AN_INBAND && p->interface != state->interface && 711 chip->info->ops->port_set_link) 712 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 713 714 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 715 if (err && err != -EOPNOTSUPP) 716 goto err_unlock; 717 718 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 719 state->advertising); 720 /* FIXME: we should restart negotiation if something changed - which 721 * is something we get if we convert to using phylinks PCS operations. 722 */ 723 if (err > 0) 724 err = 0; 725 726 /* Undo the forced down state above after completing configuration 727 * irrespective of its state on entry, which allows the link to come up. 728 */ 729 if (mode == MLO_AN_INBAND && p->interface != state->interface && 730 chip->info->ops->port_set_link) 731 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 732 733 p->interface = state->interface; 734 735 err_unlock: 736 mv88e6xxx_reg_unlock(chip); 737 738 if (err && err != -EOPNOTSUPP) 739 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 740 } 741 742 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 743 unsigned int mode, 744 phy_interface_t interface) 745 { 746 struct mv88e6xxx_chip *chip = ds->priv; 747 const struct mv88e6xxx_ops *ops; 748 int err = 0; 749 750 ops = chip->info->ops; 751 752 mv88e6xxx_reg_lock(chip); 753 /* Internal PHYs propagate their configuration directly to the MAC. 754 * External PHYs depend on whether the PPU is enabled for this port. 755 */ 756 if (((!mv88e6xxx_phy_is_internal(ds, port) && 757 !mv88e6xxx_port_ppu_updates(chip, port)) || 758 mode == MLO_AN_FIXED) && ops->port_sync_link) 759 err = ops->port_sync_link(chip, port, mode, false); 760 mv88e6xxx_reg_unlock(chip); 761 762 if (err) 763 dev_err(chip->dev, 764 "p%d: failed to force MAC link down\n", port); 765 } 766 767 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 768 unsigned int mode, phy_interface_t interface, 769 struct phy_device *phydev, 770 int speed, int duplex, 771 bool tx_pause, bool rx_pause) 772 { 773 struct mv88e6xxx_chip *chip = ds->priv; 774 const struct mv88e6xxx_ops *ops; 775 int err = 0; 776 777 ops = chip->info->ops; 778 779 mv88e6xxx_reg_lock(chip); 780 /* Internal PHYs propagate their configuration directly to the MAC. 781 * External PHYs depend on whether the PPU is enabled for this port. 782 */ 783 if ((!mv88e6xxx_phy_is_internal(ds, port) && 784 !mv88e6xxx_port_ppu_updates(chip, port)) || 785 mode == MLO_AN_FIXED) { 786 /* FIXME: for an automedia port, should we force the link 787 * down here - what if the link comes up due to "other" media 788 * while we're bringing the port up, how is the exclusivity 789 * handled in the Marvell hardware? E.g. port 2 on 88E6390 790 * shared between internal PHY and Serdes. 791 */ 792 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 793 duplex); 794 if (err) 795 goto error; 796 797 if (ops->port_set_speed_duplex) { 798 err = ops->port_set_speed_duplex(chip, port, 799 speed, duplex); 800 if (err && err != -EOPNOTSUPP) 801 goto error; 802 } 803 804 if (ops->port_sync_link) 805 err = ops->port_sync_link(chip, port, mode, true); 806 } 807 error: 808 mv88e6xxx_reg_unlock(chip); 809 810 if (err && err != -EOPNOTSUPP) 811 dev_err(ds->dev, 812 "p%d: failed to configure MAC link up\n", port); 813 } 814 815 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 816 { 817 if (!chip->info->ops->stats_snapshot) 818 return -EOPNOTSUPP; 819 820 return chip->info->ops->stats_snapshot(chip, port); 821 } 822 823 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 824 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 825 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 826 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 827 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 828 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 829 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 830 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 831 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 832 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 833 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 834 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 835 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 836 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 837 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 838 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 839 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 840 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 841 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 842 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 843 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 844 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 845 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 846 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 847 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 848 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 849 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 850 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 851 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 852 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 853 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 854 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 855 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 856 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 857 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 858 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 859 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 860 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 861 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 862 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 863 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 864 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 865 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 866 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 867 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 868 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 869 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 870 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 871 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 872 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 873 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 874 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 875 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 876 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 877 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 878 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 879 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 880 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 881 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 882 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 883 }; 884 885 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 886 struct mv88e6xxx_hw_stat *s, 887 int port, u16 bank1_select, 888 u16 histogram) 889 { 890 u32 low; 891 u32 high = 0; 892 u16 reg = 0; 893 int err; 894 u64 value; 895 896 switch (s->type) { 897 case STATS_TYPE_PORT: 898 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 899 if (err) 900 return U64_MAX; 901 902 low = reg; 903 if (s->size == 4) { 904 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 905 if (err) 906 return U64_MAX; 907 low |= ((u32)reg) << 16; 908 } 909 break; 910 case STATS_TYPE_BANK1: 911 reg = bank1_select; 912 fallthrough; 913 case STATS_TYPE_BANK0: 914 reg |= s->reg | histogram; 915 mv88e6xxx_g1_stats_read(chip, reg, &low); 916 if (s->size == 8) 917 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 918 break; 919 default: 920 return U64_MAX; 921 } 922 value = (((u64)high) << 32) | low; 923 return value; 924 } 925 926 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 927 uint8_t *data, int types) 928 { 929 struct mv88e6xxx_hw_stat *stat; 930 int i, j; 931 932 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 933 stat = &mv88e6xxx_hw_stats[i]; 934 if (stat->type & types) { 935 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 936 ETH_GSTRING_LEN); 937 j++; 938 } 939 } 940 941 return j; 942 } 943 944 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 945 uint8_t *data) 946 { 947 return mv88e6xxx_stats_get_strings(chip, data, 948 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 949 } 950 951 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 952 uint8_t *data) 953 { 954 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 955 } 956 957 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 958 uint8_t *data) 959 { 960 return mv88e6xxx_stats_get_strings(chip, data, 961 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 962 } 963 964 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 965 "atu_member_violation", 966 "atu_miss_violation", 967 "atu_full_violation", 968 "vtu_member_violation", 969 "vtu_miss_violation", 970 }; 971 972 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 973 { 974 unsigned int i; 975 976 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 977 strlcpy(data + i * ETH_GSTRING_LEN, 978 mv88e6xxx_atu_vtu_stats_strings[i], 979 ETH_GSTRING_LEN); 980 } 981 982 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 983 u32 stringset, uint8_t *data) 984 { 985 struct mv88e6xxx_chip *chip = ds->priv; 986 int count = 0; 987 988 if (stringset != ETH_SS_STATS) 989 return; 990 991 mv88e6xxx_reg_lock(chip); 992 993 if (chip->info->ops->stats_get_strings) 994 count = chip->info->ops->stats_get_strings(chip, data); 995 996 if (chip->info->ops->serdes_get_strings) { 997 data += count * ETH_GSTRING_LEN; 998 count = chip->info->ops->serdes_get_strings(chip, port, data); 999 } 1000 1001 data += count * ETH_GSTRING_LEN; 1002 mv88e6xxx_atu_vtu_get_strings(data); 1003 1004 mv88e6xxx_reg_unlock(chip); 1005 } 1006 1007 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1008 int types) 1009 { 1010 struct mv88e6xxx_hw_stat *stat; 1011 int i, j; 1012 1013 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1014 stat = &mv88e6xxx_hw_stats[i]; 1015 if (stat->type & types) 1016 j++; 1017 } 1018 return j; 1019 } 1020 1021 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1022 { 1023 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1024 STATS_TYPE_PORT); 1025 } 1026 1027 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1028 { 1029 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1030 } 1031 1032 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1033 { 1034 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1035 STATS_TYPE_BANK1); 1036 } 1037 1038 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1039 { 1040 struct mv88e6xxx_chip *chip = ds->priv; 1041 int serdes_count = 0; 1042 int count = 0; 1043 1044 if (sset != ETH_SS_STATS) 1045 return 0; 1046 1047 mv88e6xxx_reg_lock(chip); 1048 if (chip->info->ops->stats_get_sset_count) 1049 count = chip->info->ops->stats_get_sset_count(chip); 1050 if (count < 0) 1051 goto out; 1052 1053 if (chip->info->ops->serdes_get_sset_count) 1054 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1055 port); 1056 if (serdes_count < 0) { 1057 count = serdes_count; 1058 goto out; 1059 } 1060 count += serdes_count; 1061 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1062 1063 out: 1064 mv88e6xxx_reg_unlock(chip); 1065 1066 return count; 1067 } 1068 1069 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1070 uint64_t *data, int types, 1071 u16 bank1_select, u16 histogram) 1072 { 1073 struct mv88e6xxx_hw_stat *stat; 1074 int i, j; 1075 1076 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1077 stat = &mv88e6xxx_hw_stats[i]; 1078 if (stat->type & types) { 1079 mv88e6xxx_reg_lock(chip); 1080 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1081 bank1_select, 1082 histogram); 1083 mv88e6xxx_reg_unlock(chip); 1084 1085 j++; 1086 } 1087 } 1088 return j; 1089 } 1090 1091 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1092 uint64_t *data) 1093 { 1094 return mv88e6xxx_stats_get_stats(chip, port, data, 1095 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1096 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1097 } 1098 1099 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1100 uint64_t *data) 1101 { 1102 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1103 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1104 } 1105 1106 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1107 uint64_t *data) 1108 { 1109 return mv88e6xxx_stats_get_stats(chip, port, data, 1110 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1111 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1112 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1113 } 1114 1115 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1116 uint64_t *data) 1117 { 1118 return mv88e6xxx_stats_get_stats(chip, port, data, 1119 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1120 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1121 0); 1122 } 1123 1124 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1125 uint64_t *data) 1126 { 1127 *data++ = chip->ports[port].atu_member_violation; 1128 *data++ = chip->ports[port].atu_miss_violation; 1129 *data++ = chip->ports[port].atu_full_violation; 1130 *data++ = chip->ports[port].vtu_member_violation; 1131 *data++ = chip->ports[port].vtu_miss_violation; 1132 } 1133 1134 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1135 uint64_t *data) 1136 { 1137 int count = 0; 1138 1139 if (chip->info->ops->stats_get_stats) 1140 count = chip->info->ops->stats_get_stats(chip, port, data); 1141 1142 mv88e6xxx_reg_lock(chip); 1143 if (chip->info->ops->serdes_get_stats) { 1144 data += count; 1145 count = chip->info->ops->serdes_get_stats(chip, port, data); 1146 } 1147 data += count; 1148 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1149 mv88e6xxx_reg_unlock(chip); 1150 } 1151 1152 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1153 uint64_t *data) 1154 { 1155 struct mv88e6xxx_chip *chip = ds->priv; 1156 int ret; 1157 1158 mv88e6xxx_reg_lock(chip); 1159 1160 ret = mv88e6xxx_stats_snapshot(chip, port); 1161 mv88e6xxx_reg_unlock(chip); 1162 1163 if (ret < 0) 1164 return; 1165 1166 mv88e6xxx_get_stats(chip, port, data); 1167 1168 } 1169 1170 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1171 { 1172 struct mv88e6xxx_chip *chip = ds->priv; 1173 int len; 1174 1175 len = 32 * sizeof(u16); 1176 if (chip->info->ops->serdes_get_regs_len) 1177 len += chip->info->ops->serdes_get_regs_len(chip, port); 1178 1179 return len; 1180 } 1181 1182 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1183 struct ethtool_regs *regs, void *_p) 1184 { 1185 struct mv88e6xxx_chip *chip = ds->priv; 1186 int err; 1187 u16 reg; 1188 u16 *p = _p; 1189 int i; 1190 1191 regs->version = chip->info->prod_num; 1192 1193 memset(p, 0xff, 32 * sizeof(u16)); 1194 1195 mv88e6xxx_reg_lock(chip); 1196 1197 for (i = 0; i < 32; i++) { 1198 1199 err = mv88e6xxx_port_read(chip, port, i, ®); 1200 if (!err) 1201 p[i] = reg; 1202 } 1203 1204 if (chip->info->ops->serdes_get_regs) 1205 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1206 1207 mv88e6xxx_reg_unlock(chip); 1208 } 1209 1210 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1211 struct ethtool_eee *e) 1212 { 1213 /* Nothing to do on the port's MAC */ 1214 return 0; 1215 } 1216 1217 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1218 struct ethtool_eee *e) 1219 { 1220 /* Nothing to do on the port's MAC */ 1221 return 0; 1222 } 1223 1224 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1225 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1226 { 1227 struct dsa_switch *ds = chip->ds; 1228 struct dsa_switch_tree *dst = ds->dst; 1229 struct net_device *br; 1230 struct dsa_port *dp; 1231 bool found = false; 1232 u16 pvlan; 1233 1234 /* dev is a physical switch */ 1235 if (dev <= dst->last_switch) { 1236 list_for_each_entry(dp, &dst->ports, list) { 1237 if (dp->ds->index == dev && dp->index == port) { 1238 /* dp might be a DSA link or a user port, so it 1239 * might or might not have a bridge_dev 1240 * pointer. Use the "found" variable for both 1241 * cases. 1242 */ 1243 br = dp->bridge_dev; 1244 found = true; 1245 break; 1246 } 1247 } 1248 /* dev is a virtual bridge */ 1249 } else { 1250 list_for_each_entry(dp, &dst->ports, list) { 1251 if (dp->bridge_num < 0) 1252 continue; 1253 1254 if (dp->bridge_num + 1 + dst->last_switch != dev) 1255 continue; 1256 1257 br = dp->bridge_dev; 1258 found = true; 1259 break; 1260 } 1261 } 1262 1263 /* Prevent frames from unknown switch or virtual bridge */ 1264 if (!found) 1265 return 0; 1266 1267 /* Frames from DSA links and CPU ports can egress any local port */ 1268 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1269 return mv88e6xxx_port_mask(chip); 1270 1271 pvlan = 0; 1272 1273 /* Frames from user ports can egress any local DSA links and CPU ports, 1274 * as well as any local member of their bridge group. 1275 */ 1276 list_for_each_entry(dp, &dst->ports, list) 1277 if (dp->ds == ds && 1278 (dp->type == DSA_PORT_TYPE_CPU || 1279 dp->type == DSA_PORT_TYPE_DSA || 1280 (br && dp->bridge_dev == br))) 1281 pvlan |= BIT(dp->index); 1282 1283 return pvlan; 1284 } 1285 1286 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1287 { 1288 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1289 1290 /* prevent frames from going back out of the port they came in on */ 1291 output_ports &= ~BIT(port); 1292 1293 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1294 } 1295 1296 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1297 u8 state) 1298 { 1299 struct mv88e6xxx_chip *chip = ds->priv; 1300 int err; 1301 1302 mv88e6xxx_reg_lock(chip); 1303 err = mv88e6xxx_port_set_state(chip, port, state); 1304 mv88e6xxx_reg_unlock(chip); 1305 1306 if (err) 1307 dev_err(ds->dev, "p%d: failed to update state\n", port); 1308 } 1309 1310 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1311 { 1312 int err; 1313 1314 if (chip->info->ops->ieee_pri_map) { 1315 err = chip->info->ops->ieee_pri_map(chip); 1316 if (err) 1317 return err; 1318 } 1319 1320 if (chip->info->ops->ip_pri_map) { 1321 err = chip->info->ops->ip_pri_map(chip); 1322 if (err) 1323 return err; 1324 } 1325 1326 return 0; 1327 } 1328 1329 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1330 { 1331 struct dsa_switch *ds = chip->ds; 1332 int target, port; 1333 int err; 1334 1335 if (!chip->info->global2_addr) 1336 return 0; 1337 1338 /* Initialize the routing port to the 32 possible target devices */ 1339 for (target = 0; target < 32; target++) { 1340 port = dsa_routing_port(ds, target); 1341 if (port == ds->num_ports) 1342 port = 0x1f; 1343 1344 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1345 if (err) 1346 return err; 1347 } 1348 1349 if (chip->info->ops->set_cascade_port) { 1350 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1351 err = chip->info->ops->set_cascade_port(chip, port); 1352 if (err) 1353 return err; 1354 } 1355 1356 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1357 if (err) 1358 return err; 1359 1360 return 0; 1361 } 1362 1363 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1364 { 1365 /* Clear all trunk masks and mapping */ 1366 if (chip->info->global2_addr) 1367 return mv88e6xxx_g2_trunk_clear(chip); 1368 1369 return 0; 1370 } 1371 1372 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1373 { 1374 if (chip->info->ops->rmu_disable) 1375 return chip->info->ops->rmu_disable(chip); 1376 1377 return 0; 1378 } 1379 1380 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1381 { 1382 if (chip->info->ops->pot_clear) 1383 return chip->info->ops->pot_clear(chip); 1384 1385 return 0; 1386 } 1387 1388 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1389 { 1390 if (chip->info->ops->mgmt_rsvd2cpu) 1391 return chip->info->ops->mgmt_rsvd2cpu(chip); 1392 1393 return 0; 1394 } 1395 1396 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1397 { 1398 int err; 1399 1400 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1401 if (err) 1402 return err; 1403 1404 /* The chips that have a "learn2all" bit in Global1, ATU 1405 * Control are precisely those whose port registers have a 1406 * Message Port bit in Port Control 1 and hence implement 1407 * ->port_setup_message_port. 1408 */ 1409 if (chip->info->ops->port_setup_message_port) { 1410 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1411 if (err) 1412 return err; 1413 } 1414 1415 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1416 } 1417 1418 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1419 { 1420 int port; 1421 int err; 1422 1423 if (!chip->info->ops->irl_init_all) 1424 return 0; 1425 1426 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1427 /* Disable ingress rate limiting by resetting all per port 1428 * ingress rate limit resources to their initial state. 1429 */ 1430 err = chip->info->ops->irl_init_all(chip, port); 1431 if (err) 1432 return err; 1433 } 1434 1435 return 0; 1436 } 1437 1438 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1439 { 1440 if (chip->info->ops->set_switch_mac) { 1441 u8 addr[ETH_ALEN]; 1442 1443 eth_random_addr(addr); 1444 1445 return chip->info->ops->set_switch_mac(chip, addr); 1446 } 1447 1448 return 0; 1449 } 1450 1451 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1452 { 1453 struct dsa_switch_tree *dst = chip->ds->dst; 1454 struct dsa_switch *ds; 1455 struct dsa_port *dp; 1456 u16 pvlan = 0; 1457 1458 if (!mv88e6xxx_has_pvt(chip)) 1459 return 0; 1460 1461 /* Skip the local source device, which uses in-chip port VLAN */ 1462 if (dev != chip->ds->index) { 1463 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1464 1465 ds = dsa_switch_find(dst->index, dev); 1466 dp = ds ? dsa_to_port(ds, port) : NULL; 1467 if (dp && dp->lag_dev) { 1468 /* As the PVT is used to limit flooding of 1469 * FORWARD frames, which use the LAG ID as the 1470 * source port, we must translate dev/port to 1471 * the special "LAG device" in the PVT, using 1472 * the LAG ID as the port number. 1473 */ 1474 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1475 port = dsa_lag_id(dst, dp->lag_dev); 1476 } 1477 } 1478 1479 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1480 } 1481 1482 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1483 { 1484 int dev, port; 1485 int err; 1486 1487 if (!mv88e6xxx_has_pvt(chip)) 1488 return 0; 1489 1490 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1491 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1492 */ 1493 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1494 if (err) 1495 return err; 1496 1497 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1498 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1499 err = mv88e6xxx_pvt_map(chip, dev, port); 1500 if (err) 1501 return err; 1502 } 1503 } 1504 1505 return 0; 1506 } 1507 1508 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1509 { 1510 struct mv88e6xxx_chip *chip = ds->priv; 1511 int err; 1512 1513 if (dsa_to_port(ds, port)->lag_dev) 1514 /* Hardware is incapable of fast-aging a LAG through a 1515 * regular ATU move operation. Until we have something 1516 * more fancy in place this is a no-op. 1517 */ 1518 return; 1519 1520 mv88e6xxx_reg_lock(chip); 1521 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1522 mv88e6xxx_reg_unlock(chip); 1523 1524 if (err) 1525 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1526 } 1527 1528 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1529 { 1530 if (!mv88e6xxx_max_vid(chip)) 1531 return 0; 1532 1533 return mv88e6xxx_g1_vtu_flush(chip); 1534 } 1535 1536 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1537 struct mv88e6xxx_vtu_entry *entry) 1538 { 1539 int err; 1540 1541 if (!chip->info->ops->vtu_getnext) 1542 return -EOPNOTSUPP; 1543 1544 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1545 entry->valid = false; 1546 1547 err = chip->info->ops->vtu_getnext(chip, entry); 1548 1549 if (entry->vid != vid) 1550 entry->valid = false; 1551 1552 return err; 1553 } 1554 1555 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1556 int (*cb)(struct mv88e6xxx_chip *chip, 1557 const struct mv88e6xxx_vtu_entry *entry, 1558 void *priv), 1559 void *priv) 1560 { 1561 struct mv88e6xxx_vtu_entry entry = { 1562 .vid = mv88e6xxx_max_vid(chip), 1563 .valid = false, 1564 }; 1565 int err; 1566 1567 if (!chip->info->ops->vtu_getnext) 1568 return -EOPNOTSUPP; 1569 1570 do { 1571 err = chip->info->ops->vtu_getnext(chip, &entry); 1572 if (err) 1573 return err; 1574 1575 if (!entry.valid) 1576 break; 1577 1578 err = cb(chip, &entry, priv); 1579 if (err) 1580 return err; 1581 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1582 1583 return 0; 1584 } 1585 1586 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1587 struct mv88e6xxx_vtu_entry *entry) 1588 { 1589 if (!chip->info->ops->vtu_loadpurge) 1590 return -EOPNOTSUPP; 1591 1592 return chip->info->ops->vtu_loadpurge(chip, entry); 1593 } 1594 1595 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1596 const struct mv88e6xxx_vtu_entry *entry, 1597 void *_fid_bitmap) 1598 { 1599 unsigned long *fid_bitmap = _fid_bitmap; 1600 1601 set_bit(entry->fid, fid_bitmap); 1602 return 0; 1603 } 1604 1605 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1606 { 1607 int i, err; 1608 u16 fid; 1609 1610 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1611 1612 /* Set every FID bit used by the (un)bridged ports */ 1613 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1614 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1615 if (err) 1616 return err; 1617 1618 set_bit(fid, fid_bitmap); 1619 } 1620 1621 /* Set every FID bit used by the VLAN entries */ 1622 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1623 } 1624 1625 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1626 { 1627 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1628 int err; 1629 1630 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1631 if (err) 1632 return err; 1633 1634 /* The reset value 0x000 is used to indicate that multiple address 1635 * databases are not needed. Return the next positive available. 1636 */ 1637 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1638 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1639 return -ENOSPC; 1640 1641 /* Clear the database */ 1642 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1643 } 1644 1645 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1646 u16 vid) 1647 { 1648 struct mv88e6xxx_chip *chip = ds->priv; 1649 struct mv88e6xxx_vtu_entry vlan; 1650 int i, err; 1651 1652 /* DSA and CPU ports have to be members of multiple vlans */ 1653 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1654 return 0; 1655 1656 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1657 if (err) 1658 return err; 1659 1660 if (!vlan.valid) 1661 return 0; 1662 1663 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1664 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1665 continue; 1666 1667 if (!dsa_to_port(ds, i)->slave) 1668 continue; 1669 1670 if (vlan.member[i] == 1671 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1672 continue; 1673 1674 if (dsa_to_port(ds, i)->bridge_dev == 1675 dsa_to_port(ds, port)->bridge_dev) 1676 break; /* same bridge, check next VLAN */ 1677 1678 if (!dsa_to_port(ds, i)->bridge_dev) 1679 continue; 1680 1681 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1682 port, vlan.vid, i, 1683 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1684 return -EOPNOTSUPP; 1685 } 1686 1687 return 0; 1688 } 1689 1690 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1691 { 1692 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1693 struct mv88e6xxx_port *p = &chip->ports[port]; 1694 u16 pvid = MV88E6XXX_VID_STANDALONE; 1695 bool drop_untagged = false; 1696 int err; 1697 1698 if (dp->bridge_dev) { 1699 if (br_vlan_enabled(dp->bridge_dev)) { 1700 pvid = p->bridge_pvid.vid; 1701 drop_untagged = !p->bridge_pvid.valid; 1702 } else { 1703 pvid = MV88E6XXX_VID_BRIDGED; 1704 } 1705 } 1706 1707 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1708 if (err) 1709 return err; 1710 1711 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1712 } 1713 1714 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1715 bool vlan_filtering, 1716 struct netlink_ext_ack *extack) 1717 { 1718 struct mv88e6xxx_chip *chip = ds->priv; 1719 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1720 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1721 int err; 1722 1723 if (!mv88e6xxx_max_vid(chip)) 1724 return -EOPNOTSUPP; 1725 1726 mv88e6xxx_reg_lock(chip); 1727 1728 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1729 if (err) 1730 goto unlock; 1731 1732 err = mv88e6xxx_port_commit_pvid(chip, port); 1733 if (err) 1734 goto unlock; 1735 1736 unlock: 1737 mv88e6xxx_reg_unlock(chip); 1738 1739 return err; 1740 } 1741 1742 static int 1743 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1744 const struct switchdev_obj_port_vlan *vlan) 1745 { 1746 struct mv88e6xxx_chip *chip = ds->priv; 1747 int err; 1748 1749 if (!mv88e6xxx_max_vid(chip)) 1750 return -EOPNOTSUPP; 1751 1752 /* If the requested port doesn't belong to the same bridge as the VLAN 1753 * members, do not support it (yet) and fallback to software VLAN. 1754 */ 1755 mv88e6xxx_reg_lock(chip); 1756 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1757 mv88e6xxx_reg_unlock(chip); 1758 1759 return err; 1760 } 1761 1762 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1763 const unsigned char *addr, u16 vid, 1764 u8 state) 1765 { 1766 struct mv88e6xxx_atu_entry entry; 1767 struct mv88e6xxx_vtu_entry vlan; 1768 u16 fid; 1769 int err; 1770 1771 /* Ports have two private address databases: one for when the port is 1772 * standalone and one for when the port is under a bridge and the 1773 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1774 * address database to remain 100% empty, so we never load an ATU entry 1775 * into a standalone port's database. Therefore, translate the null 1776 * VLAN ID into the port's database used for VLAN-unaware bridging. 1777 */ 1778 if (vid == 0) { 1779 fid = MV88E6XXX_FID_BRIDGED; 1780 } else { 1781 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1782 if (err) 1783 return err; 1784 1785 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1786 if (!vlan.valid) 1787 return -EOPNOTSUPP; 1788 1789 fid = vlan.fid; 1790 } 1791 1792 entry.state = 0; 1793 ether_addr_copy(entry.mac, addr); 1794 eth_addr_dec(entry.mac); 1795 1796 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1797 if (err) 1798 return err; 1799 1800 /* Initialize a fresh ATU entry if it isn't found */ 1801 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1802 memset(&entry, 0, sizeof(entry)); 1803 ether_addr_copy(entry.mac, addr); 1804 } 1805 1806 /* Purge the ATU entry only if no port is using it anymore */ 1807 if (!state) { 1808 entry.portvec &= ~BIT(port); 1809 if (!entry.portvec) 1810 entry.state = 0; 1811 } else { 1812 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1813 entry.portvec = BIT(port); 1814 else 1815 entry.portvec |= BIT(port); 1816 1817 entry.state = state; 1818 } 1819 1820 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1821 } 1822 1823 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1824 const struct mv88e6xxx_policy *policy) 1825 { 1826 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1827 enum mv88e6xxx_policy_action action = policy->action; 1828 const u8 *addr = policy->addr; 1829 u16 vid = policy->vid; 1830 u8 state; 1831 int err; 1832 int id; 1833 1834 if (!chip->info->ops->port_set_policy) 1835 return -EOPNOTSUPP; 1836 1837 switch (mapping) { 1838 case MV88E6XXX_POLICY_MAPPING_DA: 1839 case MV88E6XXX_POLICY_MAPPING_SA: 1840 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1841 state = 0; /* Dissociate the port and address */ 1842 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1843 is_multicast_ether_addr(addr)) 1844 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1845 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1846 is_unicast_ether_addr(addr)) 1847 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1848 else 1849 return -EOPNOTSUPP; 1850 1851 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1852 state); 1853 if (err) 1854 return err; 1855 break; 1856 default: 1857 return -EOPNOTSUPP; 1858 } 1859 1860 /* Skip the port's policy clearing if the mapping is still in use */ 1861 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1862 idr_for_each_entry(&chip->policies, policy, id) 1863 if (policy->port == port && 1864 policy->mapping == mapping && 1865 policy->action != action) 1866 return 0; 1867 1868 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1869 } 1870 1871 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1872 struct ethtool_rx_flow_spec *fs) 1873 { 1874 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1875 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1876 enum mv88e6xxx_policy_mapping mapping; 1877 enum mv88e6xxx_policy_action action; 1878 struct mv88e6xxx_policy *policy; 1879 u16 vid = 0; 1880 u8 *addr; 1881 int err; 1882 int id; 1883 1884 if (fs->location != RX_CLS_LOC_ANY) 1885 return -EINVAL; 1886 1887 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1888 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1889 else 1890 return -EOPNOTSUPP; 1891 1892 switch (fs->flow_type & ~FLOW_EXT) { 1893 case ETHER_FLOW: 1894 if (!is_zero_ether_addr(mac_mask->h_dest) && 1895 is_zero_ether_addr(mac_mask->h_source)) { 1896 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1897 addr = mac_entry->h_dest; 1898 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1899 !is_zero_ether_addr(mac_mask->h_source)) { 1900 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1901 addr = mac_entry->h_source; 1902 } else { 1903 /* Cannot support DA and SA mapping in the same rule */ 1904 return -EOPNOTSUPP; 1905 } 1906 break; 1907 default: 1908 return -EOPNOTSUPP; 1909 } 1910 1911 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1912 if (fs->m_ext.vlan_tci != htons(0xffff)) 1913 return -EOPNOTSUPP; 1914 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1915 } 1916 1917 idr_for_each_entry(&chip->policies, policy, id) { 1918 if (policy->port == port && policy->mapping == mapping && 1919 policy->action == action && policy->vid == vid && 1920 ether_addr_equal(policy->addr, addr)) 1921 return -EEXIST; 1922 } 1923 1924 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1925 if (!policy) 1926 return -ENOMEM; 1927 1928 fs->location = 0; 1929 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1930 GFP_KERNEL); 1931 if (err) { 1932 devm_kfree(chip->dev, policy); 1933 return err; 1934 } 1935 1936 memcpy(&policy->fs, fs, sizeof(*fs)); 1937 ether_addr_copy(policy->addr, addr); 1938 policy->mapping = mapping; 1939 policy->action = action; 1940 policy->port = port; 1941 policy->vid = vid; 1942 1943 err = mv88e6xxx_policy_apply(chip, port, policy); 1944 if (err) { 1945 idr_remove(&chip->policies, fs->location); 1946 devm_kfree(chip->dev, policy); 1947 return err; 1948 } 1949 1950 return 0; 1951 } 1952 1953 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1954 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1955 { 1956 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1957 struct mv88e6xxx_chip *chip = ds->priv; 1958 struct mv88e6xxx_policy *policy; 1959 int err; 1960 int id; 1961 1962 mv88e6xxx_reg_lock(chip); 1963 1964 switch (rxnfc->cmd) { 1965 case ETHTOOL_GRXCLSRLCNT: 1966 rxnfc->data = 0; 1967 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1968 rxnfc->rule_cnt = 0; 1969 idr_for_each_entry(&chip->policies, policy, id) 1970 if (policy->port == port) 1971 rxnfc->rule_cnt++; 1972 err = 0; 1973 break; 1974 case ETHTOOL_GRXCLSRULE: 1975 err = -ENOENT; 1976 policy = idr_find(&chip->policies, fs->location); 1977 if (policy) { 1978 memcpy(fs, &policy->fs, sizeof(*fs)); 1979 err = 0; 1980 } 1981 break; 1982 case ETHTOOL_GRXCLSRLALL: 1983 rxnfc->data = 0; 1984 rxnfc->rule_cnt = 0; 1985 idr_for_each_entry(&chip->policies, policy, id) 1986 if (policy->port == port) 1987 rule_locs[rxnfc->rule_cnt++] = id; 1988 err = 0; 1989 break; 1990 default: 1991 err = -EOPNOTSUPP; 1992 break; 1993 } 1994 1995 mv88e6xxx_reg_unlock(chip); 1996 1997 return err; 1998 } 1999 2000 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2001 struct ethtool_rxnfc *rxnfc) 2002 { 2003 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2004 struct mv88e6xxx_chip *chip = ds->priv; 2005 struct mv88e6xxx_policy *policy; 2006 int err; 2007 2008 mv88e6xxx_reg_lock(chip); 2009 2010 switch (rxnfc->cmd) { 2011 case ETHTOOL_SRXCLSRLINS: 2012 err = mv88e6xxx_policy_insert(chip, port, fs); 2013 break; 2014 case ETHTOOL_SRXCLSRLDEL: 2015 err = -ENOENT; 2016 policy = idr_remove(&chip->policies, fs->location); 2017 if (policy) { 2018 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2019 err = mv88e6xxx_policy_apply(chip, port, policy); 2020 devm_kfree(chip->dev, policy); 2021 } 2022 break; 2023 default: 2024 err = -EOPNOTSUPP; 2025 break; 2026 } 2027 2028 mv88e6xxx_reg_unlock(chip); 2029 2030 return err; 2031 } 2032 2033 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2034 u16 vid) 2035 { 2036 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2037 u8 broadcast[ETH_ALEN]; 2038 2039 eth_broadcast_addr(broadcast); 2040 2041 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2042 } 2043 2044 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2045 { 2046 int port; 2047 int err; 2048 2049 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2050 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2051 struct net_device *brport; 2052 2053 if (dsa_is_unused_port(chip->ds, port)) 2054 continue; 2055 2056 brport = dsa_port_to_bridge_port(dp); 2057 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2058 /* Skip bridged user ports where broadcast 2059 * flooding is disabled. 2060 */ 2061 continue; 2062 2063 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2064 if (err) 2065 return err; 2066 } 2067 2068 return 0; 2069 } 2070 2071 struct mv88e6xxx_port_broadcast_sync_ctx { 2072 int port; 2073 bool flood; 2074 }; 2075 2076 static int 2077 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2078 const struct mv88e6xxx_vtu_entry *vlan, 2079 void *_ctx) 2080 { 2081 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2082 u8 broadcast[ETH_ALEN]; 2083 u8 state; 2084 2085 if (ctx->flood) 2086 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2087 else 2088 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2089 2090 eth_broadcast_addr(broadcast); 2091 2092 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2093 vlan->vid, state); 2094 } 2095 2096 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2097 bool flood) 2098 { 2099 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2100 .port = port, 2101 .flood = flood, 2102 }; 2103 struct mv88e6xxx_vtu_entry vid0 = { 2104 .vid = 0, 2105 }; 2106 int err; 2107 2108 /* Update the port's private database... */ 2109 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2110 if (err) 2111 return err; 2112 2113 /* ...and the database for all VLANs. */ 2114 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2115 &ctx); 2116 } 2117 2118 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2119 u16 vid, u8 member, bool warn) 2120 { 2121 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2122 struct mv88e6xxx_vtu_entry vlan; 2123 int i, err; 2124 2125 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2126 if (err) 2127 return err; 2128 2129 if (!vlan.valid) { 2130 memset(&vlan, 0, sizeof(vlan)); 2131 2132 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2133 if (err) 2134 return err; 2135 2136 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2137 if (i == port) 2138 vlan.member[i] = member; 2139 else 2140 vlan.member[i] = non_member; 2141 2142 vlan.vid = vid; 2143 vlan.valid = true; 2144 2145 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2146 if (err) 2147 return err; 2148 2149 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2150 if (err) 2151 return err; 2152 } else if (vlan.member[port] != member) { 2153 vlan.member[port] = member; 2154 2155 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2156 if (err) 2157 return err; 2158 } else if (warn) { 2159 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2160 port, vid); 2161 } 2162 2163 return 0; 2164 } 2165 2166 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2167 const struct switchdev_obj_port_vlan *vlan, 2168 struct netlink_ext_ack *extack) 2169 { 2170 struct mv88e6xxx_chip *chip = ds->priv; 2171 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2172 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2173 struct mv88e6xxx_port *p = &chip->ports[port]; 2174 bool warn; 2175 u8 member; 2176 int err; 2177 2178 if (!vlan->vid) 2179 return 0; 2180 2181 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2182 if (err) 2183 return err; 2184 2185 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2186 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2187 else if (untagged) 2188 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2189 else 2190 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2191 2192 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2193 * and then the CPU port. Do not warn for duplicates for the CPU port. 2194 */ 2195 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2196 2197 mv88e6xxx_reg_lock(chip); 2198 2199 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2200 if (err) { 2201 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2202 vlan->vid, untagged ? 'u' : 't'); 2203 goto out; 2204 } 2205 2206 if (pvid) { 2207 p->bridge_pvid.vid = vlan->vid; 2208 p->bridge_pvid.valid = true; 2209 2210 err = mv88e6xxx_port_commit_pvid(chip, port); 2211 if (err) 2212 goto out; 2213 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2214 /* The old pvid was reinstalled as a non-pvid VLAN */ 2215 p->bridge_pvid.valid = false; 2216 2217 err = mv88e6xxx_port_commit_pvid(chip, port); 2218 if (err) 2219 goto out; 2220 } 2221 2222 out: 2223 mv88e6xxx_reg_unlock(chip); 2224 2225 return err; 2226 } 2227 2228 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2229 int port, u16 vid) 2230 { 2231 struct mv88e6xxx_vtu_entry vlan; 2232 int i, err; 2233 2234 if (!vid) 2235 return 0; 2236 2237 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2238 if (err) 2239 return err; 2240 2241 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2242 * tell switchdev that this VLAN is likely handled in software. 2243 */ 2244 if (!vlan.valid || 2245 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2246 return -EOPNOTSUPP; 2247 2248 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2249 2250 /* keep the VLAN unless all ports are excluded */ 2251 vlan.valid = false; 2252 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2253 if (vlan.member[i] != 2254 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2255 vlan.valid = true; 2256 break; 2257 } 2258 } 2259 2260 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2261 if (err) 2262 return err; 2263 2264 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2265 } 2266 2267 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2268 const struct switchdev_obj_port_vlan *vlan) 2269 { 2270 struct mv88e6xxx_chip *chip = ds->priv; 2271 struct mv88e6xxx_port *p = &chip->ports[port]; 2272 int err = 0; 2273 u16 pvid; 2274 2275 if (!mv88e6xxx_max_vid(chip)) 2276 return -EOPNOTSUPP; 2277 2278 mv88e6xxx_reg_lock(chip); 2279 2280 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2281 if (err) 2282 goto unlock; 2283 2284 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2285 if (err) 2286 goto unlock; 2287 2288 if (vlan->vid == pvid) { 2289 p->bridge_pvid.valid = false; 2290 2291 err = mv88e6xxx_port_commit_pvid(chip, port); 2292 if (err) 2293 goto unlock; 2294 } 2295 2296 unlock: 2297 mv88e6xxx_reg_unlock(chip); 2298 2299 return err; 2300 } 2301 2302 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2303 const unsigned char *addr, u16 vid) 2304 { 2305 struct mv88e6xxx_chip *chip = ds->priv; 2306 int err; 2307 2308 mv88e6xxx_reg_lock(chip); 2309 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2310 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2311 mv88e6xxx_reg_unlock(chip); 2312 2313 return err; 2314 } 2315 2316 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2317 const unsigned char *addr, u16 vid) 2318 { 2319 struct mv88e6xxx_chip *chip = ds->priv; 2320 int err; 2321 2322 mv88e6xxx_reg_lock(chip); 2323 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2324 mv88e6xxx_reg_unlock(chip); 2325 2326 return err; 2327 } 2328 2329 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2330 u16 fid, u16 vid, int port, 2331 dsa_fdb_dump_cb_t *cb, void *data) 2332 { 2333 struct mv88e6xxx_atu_entry addr; 2334 bool is_static; 2335 int err; 2336 2337 addr.state = 0; 2338 eth_broadcast_addr(addr.mac); 2339 2340 do { 2341 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2342 if (err) 2343 return err; 2344 2345 if (!addr.state) 2346 break; 2347 2348 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2349 continue; 2350 2351 if (!is_unicast_ether_addr(addr.mac)) 2352 continue; 2353 2354 is_static = (addr.state == 2355 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2356 err = cb(addr.mac, vid, is_static, data); 2357 if (err) 2358 return err; 2359 } while (!is_broadcast_ether_addr(addr.mac)); 2360 2361 return err; 2362 } 2363 2364 struct mv88e6xxx_port_db_dump_vlan_ctx { 2365 int port; 2366 dsa_fdb_dump_cb_t *cb; 2367 void *data; 2368 }; 2369 2370 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2371 const struct mv88e6xxx_vtu_entry *entry, 2372 void *_data) 2373 { 2374 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2375 2376 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2377 ctx->port, ctx->cb, ctx->data); 2378 } 2379 2380 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2381 dsa_fdb_dump_cb_t *cb, void *data) 2382 { 2383 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2384 .port = port, 2385 .cb = cb, 2386 .data = data, 2387 }; 2388 u16 fid; 2389 int err; 2390 2391 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2392 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2393 if (err) 2394 return err; 2395 2396 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2397 if (err) 2398 return err; 2399 2400 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2401 } 2402 2403 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2404 dsa_fdb_dump_cb_t *cb, void *data) 2405 { 2406 struct mv88e6xxx_chip *chip = ds->priv; 2407 int err; 2408 2409 mv88e6xxx_reg_lock(chip); 2410 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2411 mv88e6xxx_reg_unlock(chip); 2412 2413 return err; 2414 } 2415 2416 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2417 struct net_device *br) 2418 { 2419 struct dsa_switch *ds = chip->ds; 2420 struct dsa_switch_tree *dst = ds->dst; 2421 struct dsa_port *dp; 2422 int err; 2423 2424 list_for_each_entry(dp, &dst->ports, list) { 2425 if (dp->bridge_dev == br) { 2426 if (dp->ds == ds) { 2427 /* This is a local bridge group member, 2428 * remap its Port VLAN Map. 2429 */ 2430 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2431 if (err) 2432 return err; 2433 } else { 2434 /* This is an external bridge group member, 2435 * remap its cross-chip Port VLAN Table entry. 2436 */ 2437 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2438 dp->index); 2439 if (err) 2440 return err; 2441 } 2442 } 2443 } 2444 2445 return 0; 2446 } 2447 2448 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2449 struct net_device *br) 2450 { 2451 struct mv88e6xxx_chip *chip = ds->priv; 2452 int err; 2453 2454 mv88e6xxx_reg_lock(chip); 2455 2456 err = mv88e6xxx_bridge_map(chip, br); 2457 if (err) 2458 goto unlock; 2459 2460 err = mv88e6xxx_port_commit_pvid(chip, port); 2461 if (err) 2462 goto unlock; 2463 2464 unlock: 2465 mv88e6xxx_reg_unlock(chip); 2466 2467 return err; 2468 } 2469 2470 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2471 struct net_device *br) 2472 { 2473 struct mv88e6xxx_chip *chip = ds->priv; 2474 int err; 2475 2476 mv88e6xxx_reg_lock(chip); 2477 2478 if (mv88e6xxx_bridge_map(chip, br) || 2479 mv88e6xxx_port_vlan_map(chip, port)) 2480 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2481 2482 err = mv88e6xxx_port_commit_pvid(chip, port); 2483 if (err) 2484 dev_err(ds->dev, 2485 "port %d failed to restore standalone pvid: %pe\n", 2486 port, ERR_PTR(err)); 2487 2488 mv88e6xxx_reg_unlock(chip); 2489 } 2490 2491 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2492 int tree_index, int sw_index, 2493 int port, struct net_device *br) 2494 { 2495 struct mv88e6xxx_chip *chip = ds->priv; 2496 int err; 2497 2498 if (tree_index != ds->dst->index) 2499 return 0; 2500 2501 mv88e6xxx_reg_lock(chip); 2502 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2503 mv88e6xxx_reg_unlock(chip); 2504 2505 return err; 2506 } 2507 2508 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2509 int tree_index, int sw_index, 2510 int port, struct net_device *br) 2511 { 2512 struct mv88e6xxx_chip *chip = ds->priv; 2513 2514 if (tree_index != ds->dst->index) 2515 return; 2516 2517 mv88e6xxx_reg_lock(chip); 2518 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2519 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2520 mv88e6xxx_reg_unlock(chip); 2521 } 2522 2523 /* Treat the software bridge as a virtual single-port switch behind the 2524 * CPU and map in the PVT. First dst->last_switch elements are taken by 2525 * physical switches, so start from beyond that range. 2526 */ 2527 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2528 int bridge_num) 2529 { 2530 u8 dev = bridge_num + ds->dst->last_switch + 1; 2531 struct mv88e6xxx_chip *chip = ds->priv; 2532 int err; 2533 2534 mv88e6xxx_reg_lock(chip); 2535 err = mv88e6xxx_pvt_map(chip, dev, 0); 2536 mv88e6xxx_reg_unlock(chip); 2537 2538 return err; 2539 } 2540 2541 static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port, 2542 struct net_device *br, 2543 int bridge_num) 2544 { 2545 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2546 } 2547 2548 static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port, 2549 struct net_device *br, 2550 int bridge_num) 2551 { 2552 int err; 2553 2554 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2555 if (err) { 2556 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n", 2557 ERR_PTR(err)); 2558 } 2559 } 2560 2561 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2562 { 2563 if (chip->info->ops->reset) 2564 return chip->info->ops->reset(chip); 2565 2566 return 0; 2567 } 2568 2569 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2570 { 2571 struct gpio_desc *gpiod = chip->reset; 2572 2573 /* If there is a GPIO connected to the reset pin, toggle it */ 2574 if (gpiod) { 2575 gpiod_set_value_cansleep(gpiod, 1); 2576 usleep_range(10000, 20000); 2577 gpiod_set_value_cansleep(gpiod, 0); 2578 usleep_range(10000, 20000); 2579 2580 mv88e6xxx_g1_wait_eeprom_done(chip); 2581 } 2582 } 2583 2584 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2585 { 2586 int i, err; 2587 2588 /* Set all ports to the Disabled state */ 2589 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2590 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2591 if (err) 2592 return err; 2593 } 2594 2595 /* Wait for transmit queues to drain, 2596 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2597 */ 2598 usleep_range(2000, 4000); 2599 2600 return 0; 2601 } 2602 2603 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2604 { 2605 int err; 2606 2607 err = mv88e6xxx_disable_ports(chip); 2608 if (err) 2609 return err; 2610 2611 mv88e6xxx_hardware_reset(chip); 2612 2613 return mv88e6xxx_software_reset(chip); 2614 } 2615 2616 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2617 enum mv88e6xxx_frame_mode frame, 2618 enum mv88e6xxx_egress_mode egress, u16 etype) 2619 { 2620 int err; 2621 2622 if (!chip->info->ops->port_set_frame_mode) 2623 return -EOPNOTSUPP; 2624 2625 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2626 if (err) 2627 return err; 2628 2629 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2630 if (err) 2631 return err; 2632 2633 if (chip->info->ops->port_set_ether_type) 2634 return chip->info->ops->port_set_ether_type(chip, port, etype); 2635 2636 return 0; 2637 } 2638 2639 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2640 { 2641 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2642 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2643 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2644 } 2645 2646 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2647 { 2648 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2649 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2650 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2651 } 2652 2653 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2654 { 2655 return mv88e6xxx_set_port_mode(chip, port, 2656 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2657 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2658 ETH_P_EDSA); 2659 } 2660 2661 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2662 { 2663 if (dsa_is_dsa_port(chip->ds, port)) 2664 return mv88e6xxx_set_port_mode_dsa(chip, port); 2665 2666 if (dsa_is_user_port(chip->ds, port)) 2667 return mv88e6xxx_set_port_mode_normal(chip, port); 2668 2669 /* Setup CPU port mode depending on its supported tag format */ 2670 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2671 return mv88e6xxx_set_port_mode_dsa(chip, port); 2672 2673 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2674 return mv88e6xxx_set_port_mode_edsa(chip, port); 2675 2676 return -EINVAL; 2677 } 2678 2679 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2680 { 2681 bool message = dsa_is_dsa_port(chip->ds, port); 2682 2683 return mv88e6xxx_port_set_message_port(chip, port, message); 2684 } 2685 2686 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2687 { 2688 int err; 2689 2690 if (chip->info->ops->port_set_ucast_flood) { 2691 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2692 if (err) 2693 return err; 2694 } 2695 if (chip->info->ops->port_set_mcast_flood) { 2696 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2697 if (err) 2698 return err; 2699 } 2700 2701 return 0; 2702 } 2703 2704 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2705 { 2706 struct mv88e6xxx_port *mvp = dev_id; 2707 struct mv88e6xxx_chip *chip = mvp->chip; 2708 irqreturn_t ret = IRQ_NONE; 2709 int port = mvp->port; 2710 int lane; 2711 2712 mv88e6xxx_reg_lock(chip); 2713 lane = mv88e6xxx_serdes_get_lane(chip, port); 2714 if (lane >= 0) 2715 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2716 mv88e6xxx_reg_unlock(chip); 2717 2718 return ret; 2719 } 2720 2721 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2722 int lane) 2723 { 2724 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2725 unsigned int irq; 2726 int err; 2727 2728 /* Nothing to request if this SERDES port has no IRQ */ 2729 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2730 if (!irq) 2731 return 0; 2732 2733 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2734 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2735 2736 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2737 mv88e6xxx_reg_unlock(chip); 2738 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2739 IRQF_ONESHOT, dev_id->serdes_irq_name, 2740 dev_id); 2741 mv88e6xxx_reg_lock(chip); 2742 if (err) 2743 return err; 2744 2745 dev_id->serdes_irq = irq; 2746 2747 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2748 } 2749 2750 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2751 int lane) 2752 { 2753 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2754 unsigned int irq = dev_id->serdes_irq; 2755 int err; 2756 2757 /* Nothing to free if no IRQ has been requested */ 2758 if (!irq) 2759 return 0; 2760 2761 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2762 2763 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2764 mv88e6xxx_reg_unlock(chip); 2765 free_irq(irq, dev_id); 2766 mv88e6xxx_reg_lock(chip); 2767 2768 dev_id->serdes_irq = 0; 2769 2770 return err; 2771 } 2772 2773 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2774 bool on) 2775 { 2776 int lane; 2777 int err; 2778 2779 lane = mv88e6xxx_serdes_get_lane(chip, port); 2780 if (lane < 0) 2781 return 0; 2782 2783 if (on) { 2784 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2785 if (err) 2786 return err; 2787 2788 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2789 } else { 2790 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2791 if (err) 2792 return err; 2793 2794 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2795 } 2796 2797 return err; 2798 } 2799 2800 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2801 enum mv88e6xxx_egress_direction direction, 2802 int port) 2803 { 2804 int err; 2805 2806 if (!chip->info->ops->set_egress_port) 2807 return -EOPNOTSUPP; 2808 2809 err = chip->info->ops->set_egress_port(chip, direction, port); 2810 if (err) 2811 return err; 2812 2813 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2814 chip->ingress_dest_port = port; 2815 else 2816 chip->egress_dest_port = port; 2817 2818 return 0; 2819 } 2820 2821 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2822 { 2823 struct dsa_switch *ds = chip->ds; 2824 int upstream_port; 2825 int err; 2826 2827 upstream_port = dsa_upstream_port(ds, port); 2828 if (chip->info->ops->port_set_upstream_port) { 2829 err = chip->info->ops->port_set_upstream_port(chip, port, 2830 upstream_port); 2831 if (err) 2832 return err; 2833 } 2834 2835 if (port == upstream_port) { 2836 if (chip->info->ops->set_cpu_port) { 2837 err = chip->info->ops->set_cpu_port(chip, 2838 upstream_port); 2839 if (err) 2840 return err; 2841 } 2842 2843 err = mv88e6xxx_set_egress_port(chip, 2844 MV88E6XXX_EGRESS_DIR_INGRESS, 2845 upstream_port); 2846 if (err && err != -EOPNOTSUPP) 2847 return err; 2848 2849 err = mv88e6xxx_set_egress_port(chip, 2850 MV88E6XXX_EGRESS_DIR_EGRESS, 2851 upstream_port); 2852 if (err && err != -EOPNOTSUPP) 2853 return err; 2854 } 2855 2856 return 0; 2857 } 2858 2859 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2860 { 2861 struct dsa_switch *ds = chip->ds; 2862 int err; 2863 u16 reg; 2864 2865 chip->ports[port].chip = chip; 2866 chip->ports[port].port = port; 2867 2868 /* MAC Forcing register: don't force link, speed, duplex or flow control 2869 * state to any particular values on physical ports, but force the CPU 2870 * port and all DSA ports to their maximum bandwidth and full duplex. 2871 */ 2872 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2873 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2874 SPEED_MAX, DUPLEX_FULL, 2875 PAUSE_OFF, 2876 PHY_INTERFACE_MODE_NA); 2877 else 2878 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2879 SPEED_UNFORCED, DUPLEX_UNFORCED, 2880 PAUSE_ON, 2881 PHY_INTERFACE_MODE_NA); 2882 if (err) 2883 return err; 2884 2885 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2886 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2887 * tunneling, determine priority by looking at 802.1p and IP 2888 * priority fields (IP prio has precedence), and set STP state 2889 * to Forwarding. 2890 * 2891 * If this is the CPU link, use DSA or EDSA tagging depending 2892 * on which tagging mode was configured. 2893 * 2894 * If this is a link to another switch, use DSA tagging mode. 2895 * 2896 * If this is the upstream port for this switch, enable 2897 * forwarding of unknown unicasts and multicasts. 2898 */ 2899 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2900 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2901 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2902 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2903 if (err) 2904 return err; 2905 2906 err = mv88e6xxx_setup_port_mode(chip, port); 2907 if (err) 2908 return err; 2909 2910 err = mv88e6xxx_setup_egress_floods(chip, port); 2911 if (err) 2912 return err; 2913 2914 /* Port Control 2: don't force a good FCS, set the MTU size to 2915 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2916 * untagged frames on this port, do a destination address lookup on all 2917 * received packets as usual, disable ARP mirroring and don't send a 2918 * copy of all transmitted/received frames on this port to the CPU. 2919 */ 2920 err = mv88e6xxx_port_set_map_da(chip, port); 2921 if (err) 2922 return err; 2923 2924 err = mv88e6xxx_setup_upstream_port(chip, port); 2925 if (err) 2926 return err; 2927 2928 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2929 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2930 if (err) 2931 return err; 2932 2933 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2934 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2935 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2936 * as the private PVID on ports under a VLAN-unaware bridge. 2937 * Shared (DSA and CPU) ports must also be members of it, to translate 2938 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2939 * relying on their port default FID. 2940 */ 2941 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2942 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2943 false); 2944 if (err) 2945 return err; 2946 2947 if (chip->info->ops->port_set_jumbo_size) { 2948 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2949 if (err) 2950 return err; 2951 } 2952 2953 /* Port Association Vector: disable automatic address learning 2954 * on all user ports since they start out in standalone 2955 * mode. When joining a bridge, learning will be configured to 2956 * match the bridge port settings. Enable learning on all 2957 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2958 * learning process. 2959 * 2960 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2961 * and RefreshLocked. I.e. setup standard automatic learning. 2962 */ 2963 if (dsa_is_user_port(ds, port)) 2964 reg = 0; 2965 else 2966 reg = 1 << port; 2967 2968 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2969 reg); 2970 if (err) 2971 return err; 2972 2973 /* Egress rate control 2: disable egress rate control. */ 2974 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2975 0x0000); 2976 if (err) 2977 return err; 2978 2979 if (chip->info->ops->port_pause_limit) { 2980 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2981 if (err) 2982 return err; 2983 } 2984 2985 if (chip->info->ops->port_disable_learn_limit) { 2986 err = chip->info->ops->port_disable_learn_limit(chip, port); 2987 if (err) 2988 return err; 2989 } 2990 2991 if (chip->info->ops->port_disable_pri_override) { 2992 err = chip->info->ops->port_disable_pri_override(chip, port); 2993 if (err) 2994 return err; 2995 } 2996 2997 if (chip->info->ops->port_tag_remap) { 2998 err = chip->info->ops->port_tag_remap(chip, port); 2999 if (err) 3000 return err; 3001 } 3002 3003 if (chip->info->ops->port_egress_rate_limiting) { 3004 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3005 if (err) 3006 return err; 3007 } 3008 3009 if (chip->info->ops->port_setup_message_port) { 3010 err = chip->info->ops->port_setup_message_port(chip, port); 3011 if (err) 3012 return err; 3013 } 3014 3015 /* Port based VLAN map: give each port the same default address 3016 * database, and allow bidirectional communication between the 3017 * CPU and DSA port(s), and the other ports. 3018 */ 3019 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3020 if (err) 3021 return err; 3022 3023 err = mv88e6xxx_port_vlan_map(chip, port); 3024 if (err) 3025 return err; 3026 3027 /* Default VLAN ID and priority: don't set a default VLAN 3028 * ID, and set the default packet priority to zero. 3029 */ 3030 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3031 } 3032 3033 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3034 { 3035 struct mv88e6xxx_chip *chip = ds->priv; 3036 3037 if (chip->info->ops->port_set_jumbo_size) 3038 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3039 else if (chip->info->ops->set_max_frame_size) 3040 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3041 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3042 } 3043 3044 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3045 { 3046 struct mv88e6xxx_chip *chip = ds->priv; 3047 int ret = 0; 3048 3049 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3050 new_mtu += EDSA_HLEN; 3051 3052 mv88e6xxx_reg_lock(chip); 3053 if (chip->info->ops->port_set_jumbo_size) 3054 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3055 else if (chip->info->ops->set_max_frame_size) 3056 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3057 else 3058 if (new_mtu > 1522) 3059 ret = -EINVAL; 3060 mv88e6xxx_reg_unlock(chip); 3061 3062 return ret; 3063 } 3064 3065 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3066 struct phy_device *phydev) 3067 { 3068 struct mv88e6xxx_chip *chip = ds->priv; 3069 int err; 3070 3071 mv88e6xxx_reg_lock(chip); 3072 err = mv88e6xxx_serdes_power(chip, port, true); 3073 mv88e6xxx_reg_unlock(chip); 3074 3075 return err; 3076 } 3077 3078 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3079 { 3080 struct mv88e6xxx_chip *chip = ds->priv; 3081 3082 mv88e6xxx_reg_lock(chip); 3083 if (mv88e6xxx_serdes_power(chip, port, false)) 3084 dev_err(chip->dev, "failed to power off SERDES\n"); 3085 mv88e6xxx_reg_unlock(chip); 3086 } 3087 3088 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3089 unsigned int ageing_time) 3090 { 3091 struct mv88e6xxx_chip *chip = ds->priv; 3092 int err; 3093 3094 mv88e6xxx_reg_lock(chip); 3095 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3096 mv88e6xxx_reg_unlock(chip); 3097 3098 return err; 3099 } 3100 3101 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3102 { 3103 int err; 3104 3105 /* Initialize the statistics unit */ 3106 if (chip->info->ops->stats_set_histogram) { 3107 err = chip->info->ops->stats_set_histogram(chip); 3108 if (err) 3109 return err; 3110 } 3111 3112 return mv88e6xxx_g1_stats_clear(chip); 3113 } 3114 3115 /* Check if the errata has already been applied. */ 3116 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3117 { 3118 int port; 3119 int err; 3120 u16 val; 3121 3122 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3123 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3124 if (err) { 3125 dev_err(chip->dev, 3126 "Error reading hidden register: %d\n", err); 3127 return false; 3128 } 3129 if (val != 0x01c0) 3130 return false; 3131 } 3132 3133 return true; 3134 } 3135 3136 /* The 6390 copper ports have an errata which require poking magic 3137 * values into undocumented hidden registers and then performing a 3138 * software reset. 3139 */ 3140 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3141 { 3142 int port; 3143 int err; 3144 3145 if (mv88e6390_setup_errata_applied(chip)) 3146 return 0; 3147 3148 /* Set the ports into blocking mode */ 3149 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3150 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3151 if (err) 3152 return err; 3153 } 3154 3155 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3156 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3157 if (err) 3158 return err; 3159 } 3160 3161 return mv88e6xxx_software_reset(chip); 3162 } 3163 3164 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3165 { 3166 mv88e6xxx_teardown_devlink_params(ds); 3167 dsa_devlink_resources_unregister(ds); 3168 mv88e6xxx_teardown_devlink_regions_global(ds); 3169 } 3170 3171 static int mv88e6xxx_setup(struct dsa_switch *ds) 3172 { 3173 struct mv88e6xxx_chip *chip = ds->priv; 3174 u8 cmode; 3175 int err; 3176 int i; 3177 3178 chip->ds = ds; 3179 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3180 3181 /* Since virtual bridges are mapped in the PVT, the number we support 3182 * depends on the physical switch topology. We need to let DSA figure 3183 * that out and therefore we cannot set this at dsa_register_switch() 3184 * time. 3185 */ 3186 if (mv88e6xxx_has_pvt(chip)) 3187 ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3188 ds->dst->last_switch - 1; 3189 3190 mv88e6xxx_reg_lock(chip); 3191 3192 if (chip->info->ops->setup_errata) { 3193 err = chip->info->ops->setup_errata(chip); 3194 if (err) 3195 goto unlock; 3196 } 3197 3198 /* Cache the cmode of each port. */ 3199 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3200 if (chip->info->ops->port_get_cmode) { 3201 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3202 if (err) 3203 goto unlock; 3204 3205 chip->ports[i].cmode = cmode; 3206 } 3207 } 3208 3209 err = mv88e6xxx_vtu_setup(chip); 3210 if (err) 3211 goto unlock; 3212 3213 /* Setup Switch Port Registers */ 3214 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3215 if (dsa_is_unused_port(ds, i)) 3216 continue; 3217 3218 /* Prevent the use of an invalid port. */ 3219 if (mv88e6xxx_is_invalid_port(chip, i)) { 3220 dev_err(chip->dev, "port %d is invalid\n", i); 3221 err = -EINVAL; 3222 goto unlock; 3223 } 3224 3225 err = mv88e6xxx_setup_port(chip, i); 3226 if (err) 3227 goto unlock; 3228 } 3229 3230 err = mv88e6xxx_irl_setup(chip); 3231 if (err) 3232 goto unlock; 3233 3234 err = mv88e6xxx_mac_setup(chip); 3235 if (err) 3236 goto unlock; 3237 3238 err = mv88e6xxx_phy_setup(chip); 3239 if (err) 3240 goto unlock; 3241 3242 err = mv88e6xxx_pvt_setup(chip); 3243 if (err) 3244 goto unlock; 3245 3246 err = mv88e6xxx_atu_setup(chip); 3247 if (err) 3248 goto unlock; 3249 3250 err = mv88e6xxx_broadcast_setup(chip, 0); 3251 if (err) 3252 goto unlock; 3253 3254 err = mv88e6xxx_pot_setup(chip); 3255 if (err) 3256 goto unlock; 3257 3258 err = mv88e6xxx_rmu_setup(chip); 3259 if (err) 3260 goto unlock; 3261 3262 err = mv88e6xxx_rsvd2cpu_setup(chip); 3263 if (err) 3264 goto unlock; 3265 3266 err = mv88e6xxx_trunk_setup(chip); 3267 if (err) 3268 goto unlock; 3269 3270 err = mv88e6xxx_devmap_setup(chip); 3271 if (err) 3272 goto unlock; 3273 3274 err = mv88e6xxx_pri_setup(chip); 3275 if (err) 3276 goto unlock; 3277 3278 /* Setup PTP Hardware Clock and timestamping */ 3279 if (chip->info->ptp_support) { 3280 err = mv88e6xxx_ptp_setup(chip); 3281 if (err) 3282 goto unlock; 3283 3284 err = mv88e6xxx_hwtstamp_setup(chip); 3285 if (err) 3286 goto unlock; 3287 } 3288 3289 err = mv88e6xxx_stats_setup(chip); 3290 if (err) 3291 goto unlock; 3292 3293 unlock: 3294 mv88e6xxx_reg_unlock(chip); 3295 3296 if (err) 3297 return err; 3298 3299 /* Have to be called without holding the register lock, since 3300 * they take the devlink lock, and we later take the locks in 3301 * the reverse order when getting/setting parameters or 3302 * resource occupancy. 3303 */ 3304 err = mv88e6xxx_setup_devlink_resources(ds); 3305 if (err) 3306 return err; 3307 3308 err = mv88e6xxx_setup_devlink_params(ds); 3309 if (err) 3310 goto out_resources; 3311 3312 err = mv88e6xxx_setup_devlink_regions_global(ds); 3313 if (err) 3314 goto out_params; 3315 3316 return 0; 3317 3318 out_params: 3319 mv88e6xxx_teardown_devlink_params(ds); 3320 out_resources: 3321 dsa_devlink_resources_unregister(ds); 3322 3323 return err; 3324 } 3325 3326 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3327 { 3328 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3329 } 3330 3331 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3332 { 3333 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3334 } 3335 3336 /* prod_id for switch families which do not have a PHY model number */ 3337 static const u16 family_prod_id_table[] = { 3338 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3339 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3340 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3341 }; 3342 3343 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3344 { 3345 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3346 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3347 u16 prod_id; 3348 u16 val; 3349 int err; 3350 3351 if (!chip->info->ops->phy_read) 3352 return -EOPNOTSUPP; 3353 3354 mv88e6xxx_reg_lock(chip); 3355 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3356 mv88e6xxx_reg_unlock(chip); 3357 3358 /* Some internal PHYs don't have a model number. */ 3359 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3360 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3361 prod_id = family_prod_id_table[chip->info->family]; 3362 if (prod_id) 3363 val |= prod_id >> 4; 3364 } 3365 3366 return err ? err : val; 3367 } 3368 3369 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3370 { 3371 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3372 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3373 int err; 3374 3375 if (!chip->info->ops->phy_write) 3376 return -EOPNOTSUPP; 3377 3378 mv88e6xxx_reg_lock(chip); 3379 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3380 mv88e6xxx_reg_unlock(chip); 3381 3382 return err; 3383 } 3384 3385 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3386 struct device_node *np, 3387 bool external) 3388 { 3389 static int index; 3390 struct mv88e6xxx_mdio_bus *mdio_bus; 3391 struct mii_bus *bus; 3392 int err; 3393 3394 if (external) { 3395 mv88e6xxx_reg_lock(chip); 3396 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3397 mv88e6xxx_reg_unlock(chip); 3398 3399 if (err) 3400 return err; 3401 } 3402 3403 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3404 if (!bus) 3405 return -ENOMEM; 3406 3407 mdio_bus = bus->priv; 3408 mdio_bus->bus = bus; 3409 mdio_bus->chip = chip; 3410 INIT_LIST_HEAD(&mdio_bus->list); 3411 mdio_bus->external = external; 3412 3413 if (np) { 3414 bus->name = np->full_name; 3415 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3416 } else { 3417 bus->name = "mv88e6xxx SMI"; 3418 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3419 } 3420 3421 bus->read = mv88e6xxx_mdio_read; 3422 bus->write = mv88e6xxx_mdio_write; 3423 bus->parent = chip->dev; 3424 3425 if (!external) { 3426 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3427 if (err) 3428 return err; 3429 } 3430 3431 err = of_mdiobus_register(bus, np); 3432 if (err) { 3433 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3434 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3435 return err; 3436 } 3437 3438 if (external) 3439 list_add_tail(&mdio_bus->list, &chip->mdios); 3440 else 3441 list_add(&mdio_bus->list, &chip->mdios); 3442 3443 return 0; 3444 } 3445 3446 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3447 3448 { 3449 struct mv88e6xxx_mdio_bus *mdio_bus; 3450 struct mii_bus *bus; 3451 3452 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3453 bus = mdio_bus->bus; 3454 3455 if (!mdio_bus->external) 3456 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3457 3458 mdiobus_unregister(bus); 3459 } 3460 } 3461 3462 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3463 struct device_node *np) 3464 { 3465 struct device_node *child; 3466 int err; 3467 3468 /* Always register one mdio bus for the internal/default mdio 3469 * bus. This maybe represented in the device tree, but is 3470 * optional. 3471 */ 3472 child = of_get_child_by_name(np, "mdio"); 3473 err = mv88e6xxx_mdio_register(chip, child, false); 3474 if (err) 3475 return err; 3476 3477 /* Walk the device tree, and see if there are any other nodes 3478 * which say they are compatible with the external mdio 3479 * bus. 3480 */ 3481 for_each_available_child_of_node(np, child) { 3482 if (of_device_is_compatible( 3483 child, "marvell,mv88e6xxx-mdio-external")) { 3484 err = mv88e6xxx_mdio_register(chip, child, true); 3485 if (err) { 3486 mv88e6xxx_mdios_unregister(chip); 3487 of_node_put(child); 3488 return err; 3489 } 3490 } 3491 } 3492 3493 return 0; 3494 } 3495 3496 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3497 { 3498 struct mv88e6xxx_chip *chip = ds->priv; 3499 3500 return chip->eeprom_len; 3501 } 3502 3503 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3504 struct ethtool_eeprom *eeprom, u8 *data) 3505 { 3506 struct mv88e6xxx_chip *chip = ds->priv; 3507 int err; 3508 3509 if (!chip->info->ops->get_eeprom) 3510 return -EOPNOTSUPP; 3511 3512 mv88e6xxx_reg_lock(chip); 3513 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3514 mv88e6xxx_reg_unlock(chip); 3515 3516 if (err) 3517 return err; 3518 3519 eeprom->magic = 0xc3ec4951; 3520 3521 return 0; 3522 } 3523 3524 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3525 struct ethtool_eeprom *eeprom, u8 *data) 3526 { 3527 struct mv88e6xxx_chip *chip = ds->priv; 3528 int err; 3529 3530 if (!chip->info->ops->set_eeprom) 3531 return -EOPNOTSUPP; 3532 3533 if (eeprom->magic != 0xc3ec4951) 3534 return -EINVAL; 3535 3536 mv88e6xxx_reg_lock(chip); 3537 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3538 mv88e6xxx_reg_unlock(chip); 3539 3540 return err; 3541 } 3542 3543 static const struct mv88e6xxx_ops mv88e6085_ops = { 3544 /* MV88E6XXX_FAMILY_6097 */ 3545 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3546 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3547 .irl_init_all = mv88e6352_g2_irl_init_all, 3548 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3549 .phy_read = mv88e6185_phy_ppu_read, 3550 .phy_write = mv88e6185_phy_ppu_write, 3551 .port_set_link = mv88e6xxx_port_set_link, 3552 .port_sync_link = mv88e6xxx_port_sync_link, 3553 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3554 .port_tag_remap = mv88e6095_port_tag_remap, 3555 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3556 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3557 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3558 .port_set_ether_type = mv88e6351_port_set_ether_type, 3559 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3560 .port_pause_limit = mv88e6097_port_pause_limit, 3561 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3562 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3563 .port_get_cmode = mv88e6185_port_get_cmode, 3564 .port_setup_message_port = mv88e6xxx_setup_message_port, 3565 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3566 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3567 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3568 .stats_get_strings = mv88e6095_stats_get_strings, 3569 .stats_get_stats = mv88e6095_stats_get_stats, 3570 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3571 .set_egress_port = mv88e6095_g1_set_egress_port, 3572 .watchdog_ops = &mv88e6097_watchdog_ops, 3573 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3574 .pot_clear = mv88e6xxx_g2_pot_clear, 3575 .ppu_enable = mv88e6185_g1_ppu_enable, 3576 .ppu_disable = mv88e6185_g1_ppu_disable, 3577 .reset = mv88e6185_g1_reset, 3578 .rmu_disable = mv88e6085_g1_rmu_disable, 3579 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3580 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3581 .phylink_validate = mv88e6185_phylink_validate, 3582 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3583 }; 3584 3585 static const struct mv88e6xxx_ops mv88e6095_ops = { 3586 /* MV88E6XXX_FAMILY_6095 */ 3587 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3588 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3589 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3590 .phy_read = mv88e6185_phy_ppu_read, 3591 .phy_write = mv88e6185_phy_ppu_write, 3592 .port_set_link = mv88e6xxx_port_set_link, 3593 .port_sync_link = mv88e6185_port_sync_link, 3594 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3595 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3596 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3597 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3598 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3599 .port_get_cmode = mv88e6185_port_get_cmode, 3600 .port_setup_message_port = mv88e6xxx_setup_message_port, 3601 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3602 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3603 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3604 .stats_get_strings = mv88e6095_stats_get_strings, 3605 .stats_get_stats = mv88e6095_stats_get_stats, 3606 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3607 .serdes_power = mv88e6185_serdes_power, 3608 .serdes_get_lane = mv88e6185_serdes_get_lane, 3609 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3610 .ppu_enable = mv88e6185_g1_ppu_enable, 3611 .ppu_disable = mv88e6185_g1_ppu_disable, 3612 .reset = mv88e6185_g1_reset, 3613 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3614 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3615 .phylink_validate = mv88e6185_phylink_validate, 3616 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3617 }; 3618 3619 static const struct mv88e6xxx_ops mv88e6097_ops = { 3620 /* MV88E6XXX_FAMILY_6097 */ 3621 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3622 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3623 .irl_init_all = mv88e6352_g2_irl_init_all, 3624 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3625 .phy_read = mv88e6xxx_g2_smi_phy_read, 3626 .phy_write = mv88e6xxx_g2_smi_phy_write, 3627 .port_set_link = mv88e6xxx_port_set_link, 3628 .port_sync_link = mv88e6185_port_sync_link, 3629 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3630 .port_tag_remap = mv88e6095_port_tag_remap, 3631 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3632 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3633 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3634 .port_set_ether_type = mv88e6351_port_set_ether_type, 3635 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3636 .port_pause_limit = mv88e6097_port_pause_limit, 3637 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3638 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3639 .port_get_cmode = mv88e6185_port_get_cmode, 3640 .port_setup_message_port = mv88e6xxx_setup_message_port, 3641 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3642 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3643 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3644 .stats_get_strings = mv88e6095_stats_get_strings, 3645 .stats_get_stats = mv88e6095_stats_get_stats, 3646 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3647 .set_egress_port = mv88e6095_g1_set_egress_port, 3648 .watchdog_ops = &mv88e6097_watchdog_ops, 3649 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3650 .serdes_power = mv88e6185_serdes_power, 3651 .serdes_get_lane = mv88e6185_serdes_get_lane, 3652 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3653 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3654 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3655 .serdes_irq_status = mv88e6097_serdes_irq_status, 3656 .pot_clear = mv88e6xxx_g2_pot_clear, 3657 .reset = mv88e6352_g1_reset, 3658 .rmu_disable = mv88e6085_g1_rmu_disable, 3659 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3660 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3661 .phylink_validate = mv88e6185_phylink_validate, 3662 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3663 }; 3664 3665 static const struct mv88e6xxx_ops mv88e6123_ops = { 3666 /* MV88E6XXX_FAMILY_6165 */ 3667 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3668 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3669 .irl_init_all = mv88e6352_g2_irl_init_all, 3670 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3671 .phy_read = mv88e6xxx_g2_smi_phy_read, 3672 .phy_write = mv88e6xxx_g2_smi_phy_write, 3673 .port_set_link = mv88e6xxx_port_set_link, 3674 .port_sync_link = mv88e6xxx_port_sync_link, 3675 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3676 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3677 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3678 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3679 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3680 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3681 .port_get_cmode = mv88e6185_port_get_cmode, 3682 .port_setup_message_port = mv88e6xxx_setup_message_port, 3683 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3684 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3685 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3686 .stats_get_strings = mv88e6095_stats_get_strings, 3687 .stats_get_stats = mv88e6095_stats_get_stats, 3688 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3689 .set_egress_port = mv88e6095_g1_set_egress_port, 3690 .watchdog_ops = &mv88e6097_watchdog_ops, 3691 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3692 .pot_clear = mv88e6xxx_g2_pot_clear, 3693 .reset = mv88e6352_g1_reset, 3694 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3695 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3696 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3697 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3698 .phylink_validate = mv88e6185_phylink_validate, 3699 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3700 }; 3701 3702 static const struct mv88e6xxx_ops mv88e6131_ops = { 3703 /* MV88E6XXX_FAMILY_6185 */ 3704 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3705 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3706 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3707 .phy_read = mv88e6185_phy_ppu_read, 3708 .phy_write = mv88e6185_phy_ppu_write, 3709 .port_set_link = mv88e6xxx_port_set_link, 3710 .port_sync_link = mv88e6xxx_port_sync_link, 3711 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3712 .port_tag_remap = mv88e6095_port_tag_remap, 3713 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3714 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3715 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3716 .port_set_ether_type = mv88e6351_port_set_ether_type, 3717 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3718 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3719 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3720 .port_pause_limit = mv88e6097_port_pause_limit, 3721 .port_set_pause = mv88e6185_port_set_pause, 3722 .port_get_cmode = mv88e6185_port_get_cmode, 3723 .port_setup_message_port = mv88e6xxx_setup_message_port, 3724 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3725 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3726 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3727 .stats_get_strings = mv88e6095_stats_get_strings, 3728 .stats_get_stats = mv88e6095_stats_get_stats, 3729 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3730 .set_egress_port = mv88e6095_g1_set_egress_port, 3731 .watchdog_ops = &mv88e6097_watchdog_ops, 3732 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3733 .ppu_enable = mv88e6185_g1_ppu_enable, 3734 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3735 .ppu_disable = mv88e6185_g1_ppu_disable, 3736 .reset = mv88e6185_g1_reset, 3737 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3738 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3739 .phylink_validate = mv88e6185_phylink_validate, 3740 }; 3741 3742 static const struct mv88e6xxx_ops mv88e6141_ops = { 3743 /* MV88E6XXX_FAMILY_6341 */ 3744 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3745 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3746 .irl_init_all = mv88e6352_g2_irl_init_all, 3747 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3748 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3749 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3750 .phy_read = mv88e6xxx_g2_smi_phy_read, 3751 .phy_write = mv88e6xxx_g2_smi_phy_write, 3752 .port_set_link = mv88e6xxx_port_set_link, 3753 .port_sync_link = mv88e6xxx_port_sync_link, 3754 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3755 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3756 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3757 .port_tag_remap = mv88e6095_port_tag_remap, 3758 .port_set_policy = mv88e6352_port_set_policy, 3759 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3760 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3761 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3762 .port_set_ether_type = mv88e6351_port_set_ether_type, 3763 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3764 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3765 .port_pause_limit = mv88e6097_port_pause_limit, 3766 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3767 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3768 .port_get_cmode = mv88e6352_port_get_cmode, 3769 .port_set_cmode = mv88e6341_port_set_cmode, 3770 .port_setup_message_port = mv88e6xxx_setup_message_port, 3771 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3772 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3773 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3774 .stats_get_strings = mv88e6320_stats_get_strings, 3775 .stats_get_stats = mv88e6390_stats_get_stats, 3776 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3777 .set_egress_port = mv88e6390_g1_set_egress_port, 3778 .watchdog_ops = &mv88e6390_watchdog_ops, 3779 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3780 .pot_clear = mv88e6xxx_g2_pot_clear, 3781 .reset = mv88e6352_g1_reset, 3782 .rmu_disable = mv88e6390_g1_rmu_disable, 3783 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3784 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3785 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3786 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3787 .serdes_power = mv88e6390_serdes_power, 3788 .serdes_get_lane = mv88e6341_serdes_get_lane, 3789 /* Check status register pause & lpa register */ 3790 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3791 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3792 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3793 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3794 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3795 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3796 .serdes_irq_status = mv88e6390_serdes_irq_status, 3797 .gpio_ops = &mv88e6352_gpio_ops, 3798 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3799 .serdes_get_strings = mv88e6390_serdes_get_strings, 3800 .serdes_get_stats = mv88e6390_serdes_get_stats, 3801 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3802 .serdes_get_regs = mv88e6390_serdes_get_regs, 3803 .phylink_validate = mv88e6341_phylink_validate, 3804 }; 3805 3806 static const struct mv88e6xxx_ops mv88e6161_ops = { 3807 /* MV88E6XXX_FAMILY_6165 */ 3808 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3809 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3810 .irl_init_all = mv88e6352_g2_irl_init_all, 3811 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3812 .phy_read = mv88e6xxx_g2_smi_phy_read, 3813 .phy_write = mv88e6xxx_g2_smi_phy_write, 3814 .port_set_link = mv88e6xxx_port_set_link, 3815 .port_sync_link = mv88e6xxx_port_sync_link, 3816 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3817 .port_tag_remap = mv88e6095_port_tag_remap, 3818 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3819 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3820 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3821 .port_set_ether_type = mv88e6351_port_set_ether_type, 3822 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3823 .port_pause_limit = mv88e6097_port_pause_limit, 3824 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3825 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3826 .port_get_cmode = mv88e6185_port_get_cmode, 3827 .port_setup_message_port = mv88e6xxx_setup_message_port, 3828 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3829 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3830 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3831 .stats_get_strings = mv88e6095_stats_get_strings, 3832 .stats_get_stats = mv88e6095_stats_get_stats, 3833 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3834 .set_egress_port = mv88e6095_g1_set_egress_port, 3835 .watchdog_ops = &mv88e6097_watchdog_ops, 3836 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3837 .pot_clear = mv88e6xxx_g2_pot_clear, 3838 .reset = mv88e6352_g1_reset, 3839 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3840 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3841 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3842 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3843 .avb_ops = &mv88e6165_avb_ops, 3844 .ptp_ops = &mv88e6165_ptp_ops, 3845 .phylink_validate = mv88e6185_phylink_validate, 3846 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3847 }; 3848 3849 static const struct mv88e6xxx_ops mv88e6165_ops = { 3850 /* MV88E6XXX_FAMILY_6165 */ 3851 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3852 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3853 .irl_init_all = mv88e6352_g2_irl_init_all, 3854 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3855 .phy_read = mv88e6165_phy_read, 3856 .phy_write = mv88e6165_phy_write, 3857 .port_set_link = mv88e6xxx_port_set_link, 3858 .port_sync_link = mv88e6xxx_port_sync_link, 3859 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3860 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3861 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3862 .port_get_cmode = mv88e6185_port_get_cmode, 3863 .port_setup_message_port = mv88e6xxx_setup_message_port, 3864 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3865 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3866 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3867 .stats_get_strings = mv88e6095_stats_get_strings, 3868 .stats_get_stats = mv88e6095_stats_get_stats, 3869 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3870 .set_egress_port = mv88e6095_g1_set_egress_port, 3871 .watchdog_ops = &mv88e6097_watchdog_ops, 3872 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3873 .pot_clear = mv88e6xxx_g2_pot_clear, 3874 .reset = mv88e6352_g1_reset, 3875 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3876 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3877 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3878 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3879 .avb_ops = &mv88e6165_avb_ops, 3880 .ptp_ops = &mv88e6165_ptp_ops, 3881 .phylink_validate = mv88e6185_phylink_validate, 3882 }; 3883 3884 static const struct mv88e6xxx_ops mv88e6171_ops = { 3885 /* MV88E6XXX_FAMILY_6351 */ 3886 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3887 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3888 .irl_init_all = mv88e6352_g2_irl_init_all, 3889 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3890 .phy_read = mv88e6xxx_g2_smi_phy_read, 3891 .phy_write = mv88e6xxx_g2_smi_phy_write, 3892 .port_set_link = mv88e6xxx_port_set_link, 3893 .port_sync_link = mv88e6xxx_port_sync_link, 3894 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3895 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3896 .port_tag_remap = mv88e6095_port_tag_remap, 3897 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3898 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3899 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3900 .port_set_ether_type = mv88e6351_port_set_ether_type, 3901 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3902 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3903 .port_pause_limit = mv88e6097_port_pause_limit, 3904 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3905 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3906 .port_get_cmode = mv88e6352_port_get_cmode, 3907 .port_setup_message_port = mv88e6xxx_setup_message_port, 3908 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3909 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3910 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3911 .stats_get_strings = mv88e6095_stats_get_strings, 3912 .stats_get_stats = mv88e6095_stats_get_stats, 3913 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3914 .set_egress_port = mv88e6095_g1_set_egress_port, 3915 .watchdog_ops = &mv88e6097_watchdog_ops, 3916 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3917 .pot_clear = mv88e6xxx_g2_pot_clear, 3918 .reset = mv88e6352_g1_reset, 3919 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3920 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3921 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3922 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3923 .phylink_validate = mv88e6185_phylink_validate, 3924 }; 3925 3926 static const struct mv88e6xxx_ops mv88e6172_ops = { 3927 /* MV88E6XXX_FAMILY_6352 */ 3928 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3929 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3930 .irl_init_all = mv88e6352_g2_irl_init_all, 3931 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3932 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3933 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3934 .phy_read = mv88e6xxx_g2_smi_phy_read, 3935 .phy_write = mv88e6xxx_g2_smi_phy_write, 3936 .port_set_link = mv88e6xxx_port_set_link, 3937 .port_sync_link = mv88e6xxx_port_sync_link, 3938 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3939 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3940 .port_tag_remap = mv88e6095_port_tag_remap, 3941 .port_set_policy = mv88e6352_port_set_policy, 3942 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3943 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3944 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3945 .port_set_ether_type = mv88e6351_port_set_ether_type, 3946 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3947 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3948 .port_pause_limit = mv88e6097_port_pause_limit, 3949 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3950 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3951 .port_get_cmode = mv88e6352_port_get_cmode, 3952 .port_setup_message_port = mv88e6xxx_setup_message_port, 3953 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3954 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3955 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3956 .stats_get_strings = mv88e6095_stats_get_strings, 3957 .stats_get_stats = mv88e6095_stats_get_stats, 3958 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3959 .set_egress_port = mv88e6095_g1_set_egress_port, 3960 .watchdog_ops = &mv88e6097_watchdog_ops, 3961 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3962 .pot_clear = mv88e6xxx_g2_pot_clear, 3963 .reset = mv88e6352_g1_reset, 3964 .rmu_disable = mv88e6352_g1_rmu_disable, 3965 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3966 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3967 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3968 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3969 .serdes_get_lane = mv88e6352_serdes_get_lane, 3970 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3971 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3972 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3973 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3974 .serdes_power = mv88e6352_serdes_power, 3975 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3976 .serdes_get_regs = mv88e6352_serdes_get_regs, 3977 .gpio_ops = &mv88e6352_gpio_ops, 3978 .phylink_validate = mv88e6352_phylink_validate, 3979 }; 3980 3981 static const struct mv88e6xxx_ops mv88e6175_ops = { 3982 /* MV88E6XXX_FAMILY_6351 */ 3983 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3984 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3985 .irl_init_all = mv88e6352_g2_irl_init_all, 3986 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3987 .phy_read = mv88e6xxx_g2_smi_phy_read, 3988 .phy_write = mv88e6xxx_g2_smi_phy_write, 3989 .port_set_link = mv88e6xxx_port_set_link, 3990 .port_sync_link = mv88e6xxx_port_sync_link, 3991 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3992 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3993 .port_tag_remap = mv88e6095_port_tag_remap, 3994 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3995 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3996 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3997 .port_set_ether_type = mv88e6351_port_set_ether_type, 3998 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3999 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4000 .port_pause_limit = mv88e6097_port_pause_limit, 4001 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4002 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4003 .port_get_cmode = mv88e6352_port_get_cmode, 4004 .port_setup_message_port = mv88e6xxx_setup_message_port, 4005 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4006 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4007 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4008 .stats_get_strings = mv88e6095_stats_get_strings, 4009 .stats_get_stats = mv88e6095_stats_get_stats, 4010 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4011 .set_egress_port = mv88e6095_g1_set_egress_port, 4012 .watchdog_ops = &mv88e6097_watchdog_ops, 4013 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4014 .pot_clear = mv88e6xxx_g2_pot_clear, 4015 .reset = mv88e6352_g1_reset, 4016 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4017 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4018 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4019 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4020 .phylink_validate = mv88e6185_phylink_validate, 4021 }; 4022 4023 static const struct mv88e6xxx_ops mv88e6176_ops = { 4024 /* MV88E6XXX_FAMILY_6352 */ 4025 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4026 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4027 .irl_init_all = mv88e6352_g2_irl_init_all, 4028 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4029 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4030 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4031 .phy_read = mv88e6xxx_g2_smi_phy_read, 4032 .phy_write = mv88e6xxx_g2_smi_phy_write, 4033 .port_set_link = mv88e6xxx_port_set_link, 4034 .port_sync_link = mv88e6xxx_port_sync_link, 4035 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4036 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4037 .port_tag_remap = mv88e6095_port_tag_remap, 4038 .port_set_policy = mv88e6352_port_set_policy, 4039 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4040 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4041 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4042 .port_set_ether_type = mv88e6351_port_set_ether_type, 4043 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4044 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4045 .port_pause_limit = mv88e6097_port_pause_limit, 4046 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4047 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4048 .port_get_cmode = mv88e6352_port_get_cmode, 4049 .port_setup_message_port = mv88e6xxx_setup_message_port, 4050 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4051 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4052 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4053 .stats_get_strings = mv88e6095_stats_get_strings, 4054 .stats_get_stats = mv88e6095_stats_get_stats, 4055 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4056 .set_egress_port = mv88e6095_g1_set_egress_port, 4057 .watchdog_ops = &mv88e6097_watchdog_ops, 4058 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4059 .pot_clear = mv88e6xxx_g2_pot_clear, 4060 .reset = mv88e6352_g1_reset, 4061 .rmu_disable = mv88e6352_g1_rmu_disable, 4062 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4063 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4064 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4065 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4066 .serdes_get_lane = mv88e6352_serdes_get_lane, 4067 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4068 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4069 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4070 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4071 .serdes_power = mv88e6352_serdes_power, 4072 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4073 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4074 .serdes_irq_status = mv88e6352_serdes_irq_status, 4075 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4076 .serdes_get_regs = mv88e6352_serdes_get_regs, 4077 .gpio_ops = &mv88e6352_gpio_ops, 4078 .phylink_validate = mv88e6352_phylink_validate, 4079 }; 4080 4081 static const struct mv88e6xxx_ops mv88e6185_ops = { 4082 /* MV88E6XXX_FAMILY_6185 */ 4083 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4084 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4085 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4086 .phy_read = mv88e6185_phy_ppu_read, 4087 .phy_write = mv88e6185_phy_ppu_write, 4088 .port_set_link = mv88e6xxx_port_set_link, 4089 .port_sync_link = mv88e6185_port_sync_link, 4090 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4091 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4092 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4093 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4094 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4095 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4096 .port_set_pause = mv88e6185_port_set_pause, 4097 .port_get_cmode = mv88e6185_port_get_cmode, 4098 .port_setup_message_port = mv88e6xxx_setup_message_port, 4099 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4100 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4101 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4102 .stats_get_strings = mv88e6095_stats_get_strings, 4103 .stats_get_stats = mv88e6095_stats_get_stats, 4104 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4105 .set_egress_port = mv88e6095_g1_set_egress_port, 4106 .watchdog_ops = &mv88e6097_watchdog_ops, 4107 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4108 .serdes_power = mv88e6185_serdes_power, 4109 .serdes_get_lane = mv88e6185_serdes_get_lane, 4110 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4111 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4112 .ppu_enable = mv88e6185_g1_ppu_enable, 4113 .ppu_disable = mv88e6185_g1_ppu_disable, 4114 .reset = mv88e6185_g1_reset, 4115 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4116 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4117 .phylink_validate = mv88e6185_phylink_validate, 4118 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4119 }; 4120 4121 static const struct mv88e6xxx_ops mv88e6190_ops = { 4122 /* MV88E6XXX_FAMILY_6390 */ 4123 .setup_errata = mv88e6390_setup_errata, 4124 .irl_init_all = mv88e6390_g2_irl_init_all, 4125 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4126 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4127 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4128 .phy_read = mv88e6xxx_g2_smi_phy_read, 4129 .phy_write = mv88e6xxx_g2_smi_phy_write, 4130 .port_set_link = mv88e6xxx_port_set_link, 4131 .port_sync_link = mv88e6xxx_port_sync_link, 4132 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4133 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4134 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4135 .port_tag_remap = mv88e6390_port_tag_remap, 4136 .port_set_policy = mv88e6352_port_set_policy, 4137 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4138 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4139 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4140 .port_set_ether_type = mv88e6351_port_set_ether_type, 4141 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4142 .port_pause_limit = mv88e6390_port_pause_limit, 4143 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4144 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4145 .port_get_cmode = mv88e6352_port_get_cmode, 4146 .port_set_cmode = mv88e6390_port_set_cmode, 4147 .port_setup_message_port = mv88e6xxx_setup_message_port, 4148 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4149 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4150 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4151 .stats_get_strings = mv88e6320_stats_get_strings, 4152 .stats_get_stats = mv88e6390_stats_get_stats, 4153 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4154 .set_egress_port = mv88e6390_g1_set_egress_port, 4155 .watchdog_ops = &mv88e6390_watchdog_ops, 4156 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4157 .pot_clear = mv88e6xxx_g2_pot_clear, 4158 .reset = mv88e6352_g1_reset, 4159 .rmu_disable = mv88e6390_g1_rmu_disable, 4160 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4161 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4162 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4163 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4164 .serdes_power = mv88e6390_serdes_power, 4165 .serdes_get_lane = mv88e6390_serdes_get_lane, 4166 /* Check status register pause & lpa register */ 4167 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4168 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4169 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4170 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4171 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4172 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4173 .serdes_irq_status = mv88e6390_serdes_irq_status, 4174 .serdes_get_strings = mv88e6390_serdes_get_strings, 4175 .serdes_get_stats = mv88e6390_serdes_get_stats, 4176 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4177 .serdes_get_regs = mv88e6390_serdes_get_regs, 4178 .gpio_ops = &mv88e6352_gpio_ops, 4179 .phylink_validate = mv88e6390_phylink_validate, 4180 }; 4181 4182 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4183 /* MV88E6XXX_FAMILY_6390 */ 4184 .setup_errata = mv88e6390_setup_errata, 4185 .irl_init_all = mv88e6390_g2_irl_init_all, 4186 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4187 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4188 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4189 .phy_read = mv88e6xxx_g2_smi_phy_read, 4190 .phy_write = mv88e6xxx_g2_smi_phy_write, 4191 .port_set_link = mv88e6xxx_port_set_link, 4192 .port_sync_link = mv88e6xxx_port_sync_link, 4193 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4194 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4195 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4196 .port_tag_remap = mv88e6390_port_tag_remap, 4197 .port_set_policy = mv88e6352_port_set_policy, 4198 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4199 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4200 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4201 .port_set_ether_type = mv88e6351_port_set_ether_type, 4202 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4203 .port_pause_limit = mv88e6390_port_pause_limit, 4204 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4205 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4206 .port_get_cmode = mv88e6352_port_get_cmode, 4207 .port_set_cmode = mv88e6390x_port_set_cmode, 4208 .port_setup_message_port = mv88e6xxx_setup_message_port, 4209 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4210 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4211 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4212 .stats_get_strings = mv88e6320_stats_get_strings, 4213 .stats_get_stats = mv88e6390_stats_get_stats, 4214 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4215 .set_egress_port = mv88e6390_g1_set_egress_port, 4216 .watchdog_ops = &mv88e6390_watchdog_ops, 4217 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4218 .pot_clear = mv88e6xxx_g2_pot_clear, 4219 .reset = mv88e6352_g1_reset, 4220 .rmu_disable = mv88e6390_g1_rmu_disable, 4221 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4222 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4223 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4224 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4225 .serdes_power = mv88e6390_serdes_power, 4226 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4227 /* Check status register pause & lpa register */ 4228 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4229 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4230 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4231 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4232 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4233 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4234 .serdes_irq_status = mv88e6390_serdes_irq_status, 4235 .serdes_get_strings = mv88e6390_serdes_get_strings, 4236 .serdes_get_stats = mv88e6390_serdes_get_stats, 4237 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4238 .serdes_get_regs = mv88e6390_serdes_get_regs, 4239 .gpio_ops = &mv88e6352_gpio_ops, 4240 .phylink_validate = mv88e6390x_phylink_validate, 4241 }; 4242 4243 static const struct mv88e6xxx_ops mv88e6191_ops = { 4244 /* MV88E6XXX_FAMILY_6390 */ 4245 .setup_errata = mv88e6390_setup_errata, 4246 .irl_init_all = mv88e6390_g2_irl_init_all, 4247 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4248 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4249 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4250 .phy_read = mv88e6xxx_g2_smi_phy_read, 4251 .phy_write = mv88e6xxx_g2_smi_phy_write, 4252 .port_set_link = mv88e6xxx_port_set_link, 4253 .port_sync_link = mv88e6xxx_port_sync_link, 4254 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4255 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4256 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4257 .port_tag_remap = mv88e6390_port_tag_remap, 4258 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4259 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4260 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4261 .port_set_ether_type = mv88e6351_port_set_ether_type, 4262 .port_pause_limit = mv88e6390_port_pause_limit, 4263 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4264 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4265 .port_get_cmode = mv88e6352_port_get_cmode, 4266 .port_set_cmode = mv88e6390_port_set_cmode, 4267 .port_setup_message_port = mv88e6xxx_setup_message_port, 4268 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4269 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4270 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4271 .stats_get_strings = mv88e6320_stats_get_strings, 4272 .stats_get_stats = mv88e6390_stats_get_stats, 4273 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4274 .set_egress_port = mv88e6390_g1_set_egress_port, 4275 .watchdog_ops = &mv88e6390_watchdog_ops, 4276 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4277 .pot_clear = mv88e6xxx_g2_pot_clear, 4278 .reset = mv88e6352_g1_reset, 4279 .rmu_disable = mv88e6390_g1_rmu_disable, 4280 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4281 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4282 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4283 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4284 .serdes_power = mv88e6390_serdes_power, 4285 .serdes_get_lane = mv88e6390_serdes_get_lane, 4286 /* Check status register pause & lpa register */ 4287 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4288 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4289 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4290 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4291 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4292 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4293 .serdes_irq_status = mv88e6390_serdes_irq_status, 4294 .serdes_get_strings = mv88e6390_serdes_get_strings, 4295 .serdes_get_stats = mv88e6390_serdes_get_stats, 4296 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4297 .serdes_get_regs = mv88e6390_serdes_get_regs, 4298 .avb_ops = &mv88e6390_avb_ops, 4299 .ptp_ops = &mv88e6352_ptp_ops, 4300 .phylink_validate = mv88e6390_phylink_validate, 4301 }; 4302 4303 static const struct mv88e6xxx_ops mv88e6240_ops = { 4304 /* MV88E6XXX_FAMILY_6352 */ 4305 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4306 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4307 .irl_init_all = mv88e6352_g2_irl_init_all, 4308 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4309 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4310 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4311 .phy_read = mv88e6xxx_g2_smi_phy_read, 4312 .phy_write = mv88e6xxx_g2_smi_phy_write, 4313 .port_set_link = mv88e6xxx_port_set_link, 4314 .port_sync_link = mv88e6xxx_port_sync_link, 4315 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4316 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4317 .port_tag_remap = mv88e6095_port_tag_remap, 4318 .port_set_policy = mv88e6352_port_set_policy, 4319 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4320 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4321 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4322 .port_set_ether_type = mv88e6351_port_set_ether_type, 4323 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4324 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4325 .port_pause_limit = mv88e6097_port_pause_limit, 4326 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4327 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4328 .port_get_cmode = mv88e6352_port_get_cmode, 4329 .port_setup_message_port = mv88e6xxx_setup_message_port, 4330 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4331 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4332 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4333 .stats_get_strings = mv88e6095_stats_get_strings, 4334 .stats_get_stats = mv88e6095_stats_get_stats, 4335 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4336 .set_egress_port = mv88e6095_g1_set_egress_port, 4337 .watchdog_ops = &mv88e6097_watchdog_ops, 4338 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4339 .pot_clear = mv88e6xxx_g2_pot_clear, 4340 .reset = mv88e6352_g1_reset, 4341 .rmu_disable = mv88e6352_g1_rmu_disable, 4342 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4343 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4344 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4345 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4346 .serdes_get_lane = mv88e6352_serdes_get_lane, 4347 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4348 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4349 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4350 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4351 .serdes_power = mv88e6352_serdes_power, 4352 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4353 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4354 .serdes_irq_status = mv88e6352_serdes_irq_status, 4355 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4356 .serdes_get_regs = mv88e6352_serdes_get_regs, 4357 .gpio_ops = &mv88e6352_gpio_ops, 4358 .avb_ops = &mv88e6352_avb_ops, 4359 .ptp_ops = &mv88e6352_ptp_ops, 4360 .phylink_validate = mv88e6352_phylink_validate, 4361 }; 4362 4363 static const struct mv88e6xxx_ops mv88e6250_ops = { 4364 /* MV88E6XXX_FAMILY_6250 */ 4365 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4366 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4367 .irl_init_all = mv88e6352_g2_irl_init_all, 4368 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4369 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4370 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4371 .phy_read = mv88e6xxx_g2_smi_phy_read, 4372 .phy_write = mv88e6xxx_g2_smi_phy_write, 4373 .port_set_link = mv88e6xxx_port_set_link, 4374 .port_sync_link = mv88e6xxx_port_sync_link, 4375 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4376 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4377 .port_tag_remap = mv88e6095_port_tag_remap, 4378 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4379 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4380 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4381 .port_set_ether_type = mv88e6351_port_set_ether_type, 4382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4383 .port_pause_limit = mv88e6097_port_pause_limit, 4384 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4385 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4386 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4387 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4388 .stats_get_strings = mv88e6250_stats_get_strings, 4389 .stats_get_stats = mv88e6250_stats_get_stats, 4390 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4391 .set_egress_port = mv88e6095_g1_set_egress_port, 4392 .watchdog_ops = &mv88e6250_watchdog_ops, 4393 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4394 .pot_clear = mv88e6xxx_g2_pot_clear, 4395 .reset = mv88e6250_g1_reset, 4396 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4397 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4398 .avb_ops = &mv88e6352_avb_ops, 4399 .ptp_ops = &mv88e6250_ptp_ops, 4400 .phylink_validate = mv88e6065_phylink_validate, 4401 }; 4402 4403 static const struct mv88e6xxx_ops mv88e6290_ops = { 4404 /* MV88E6XXX_FAMILY_6390 */ 4405 .setup_errata = mv88e6390_setup_errata, 4406 .irl_init_all = mv88e6390_g2_irl_init_all, 4407 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4408 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4409 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4410 .phy_read = mv88e6xxx_g2_smi_phy_read, 4411 .phy_write = mv88e6xxx_g2_smi_phy_write, 4412 .port_set_link = mv88e6xxx_port_set_link, 4413 .port_sync_link = mv88e6xxx_port_sync_link, 4414 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4415 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4416 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4417 .port_tag_remap = mv88e6390_port_tag_remap, 4418 .port_set_policy = mv88e6352_port_set_policy, 4419 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4420 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4421 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4422 .port_set_ether_type = mv88e6351_port_set_ether_type, 4423 .port_pause_limit = mv88e6390_port_pause_limit, 4424 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4425 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4426 .port_get_cmode = mv88e6352_port_get_cmode, 4427 .port_set_cmode = mv88e6390_port_set_cmode, 4428 .port_setup_message_port = mv88e6xxx_setup_message_port, 4429 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4430 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4431 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4432 .stats_get_strings = mv88e6320_stats_get_strings, 4433 .stats_get_stats = mv88e6390_stats_get_stats, 4434 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4435 .set_egress_port = mv88e6390_g1_set_egress_port, 4436 .watchdog_ops = &mv88e6390_watchdog_ops, 4437 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4438 .pot_clear = mv88e6xxx_g2_pot_clear, 4439 .reset = mv88e6352_g1_reset, 4440 .rmu_disable = mv88e6390_g1_rmu_disable, 4441 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4442 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4443 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4444 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4445 .serdes_power = mv88e6390_serdes_power, 4446 .serdes_get_lane = mv88e6390_serdes_get_lane, 4447 /* Check status register pause & lpa register */ 4448 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4449 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4450 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4451 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4452 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4453 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4454 .serdes_irq_status = mv88e6390_serdes_irq_status, 4455 .serdes_get_strings = mv88e6390_serdes_get_strings, 4456 .serdes_get_stats = mv88e6390_serdes_get_stats, 4457 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4458 .serdes_get_regs = mv88e6390_serdes_get_regs, 4459 .gpio_ops = &mv88e6352_gpio_ops, 4460 .avb_ops = &mv88e6390_avb_ops, 4461 .ptp_ops = &mv88e6352_ptp_ops, 4462 .phylink_validate = mv88e6390_phylink_validate, 4463 }; 4464 4465 static const struct mv88e6xxx_ops mv88e6320_ops = { 4466 /* MV88E6XXX_FAMILY_6320 */ 4467 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4468 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4469 .irl_init_all = mv88e6352_g2_irl_init_all, 4470 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4471 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4472 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4473 .phy_read = mv88e6xxx_g2_smi_phy_read, 4474 .phy_write = mv88e6xxx_g2_smi_phy_write, 4475 .port_set_link = mv88e6xxx_port_set_link, 4476 .port_sync_link = mv88e6xxx_port_sync_link, 4477 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4478 .port_tag_remap = mv88e6095_port_tag_remap, 4479 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4480 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4481 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4482 .port_set_ether_type = mv88e6351_port_set_ether_type, 4483 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4484 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4485 .port_pause_limit = mv88e6097_port_pause_limit, 4486 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4487 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4488 .port_get_cmode = mv88e6352_port_get_cmode, 4489 .port_setup_message_port = mv88e6xxx_setup_message_port, 4490 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4491 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4492 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4493 .stats_get_strings = mv88e6320_stats_get_strings, 4494 .stats_get_stats = mv88e6320_stats_get_stats, 4495 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4496 .set_egress_port = mv88e6095_g1_set_egress_port, 4497 .watchdog_ops = &mv88e6390_watchdog_ops, 4498 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4499 .pot_clear = mv88e6xxx_g2_pot_clear, 4500 .reset = mv88e6352_g1_reset, 4501 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4502 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4503 .gpio_ops = &mv88e6352_gpio_ops, 4504 .avb_ops = &mv88e6352_avb_ops, 4505 .ptp_ops = &mv88e6352_ptp_ops, 4506 .phylink_validate = mv88e6185_phylink_validate, 4507 }; 4508 4509 static const struct mv88e6xxx_ops mv88e6321_ops = { 4510 /* MV88E6XXX_FAMILY_6320 */ 4511 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4512 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4513 .irl_init_all = mv88e6352_g2_irl_init_all, 4514 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4515 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4516 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4517 .phy_read = mv88e6xxx_g2_smi_phy_read, 4518 .phy_write = mv88e6xxx_g2_smi_phy_write, 4519 .port_set_link = mv88e6xxx_port_set_link, 4520 .port_sync_link = mv88e6xxx_port_sync_link, 4521 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4522 .port_tag_remap = mv88e6095_port_tag_remap, 4523 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4524 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4525 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4526 .port_set_ether_type = mv88e6351_port_set_ether_type, 4527 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4528 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4529 .port_pause_limit = mv88e6097_port_pause_limit, 4530 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4531 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4532 .port_get_cmode = mv88e6352_port_get_cmode, 4533 .port_setup_message_port = mv88e6xxx_setup_message_port, 4534 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4535 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4536 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4537 .stats_get_strings = mv88e6320_stats_get_strings, 4538 .stats_get_stats = mv88e6320_stats_get_stats, 4539 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4540 .set_egress_port = mv88e6095_g1_set_egress_port, 4541 .watchdog_ops = &mv88e6390_watchdog_ops, 4542 .reset = mv88e6352_g1_reset, 4543 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4544 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4545 .gpio_ops = &mv88e6352_gpio_ops, 4546 .avb_ops = &mv88e6352_avb_ops, 4547 .ptp_ops = &mv88e6352_ptp_ops, 4548 .phylink_validate = mv88e6185_phylink_validate, 4549 }; 4550 4551 static const struct mv88e6xxx_ops mv88e6341_ops = { 4552 /* MV88E6XXX_FAMILY_6341 */ 4553 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4554 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4555 .irl_init_all = mv88e6352_g2_irl_init_all, 4556 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4557 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4558 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4559 .phy_read = mv88e6xxx_g2_smi_phy_read, 4560 .phy_write = mv88e6xxx_g2_smi_phy_write, 4561 .port_set_link = mv88e6xxx_port_set_link, 4562 .port_sync_link = mv88e6xxx_port_sync_link, 4563 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4564 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4565 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4566 .port_tag_remap = mv88e6095_port_tag_remap, 4567 .port_set_policy = mv88e6352_port_set_policy, 4568 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4569 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4570 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4571 .port_set_ether_type = mv88e6351_port_set_ether_type, 4572 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4573 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4574 .port_pause_limit = mv88e6097_port_pause_limit, 4575 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4576 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4577 .port_get_cmode = mv88e6352_port_get_cmode, 4578 .port_set_cmode = mv88e6341_port_set_cmode, 4579 .port_setup_message_port = mv88e6xxx_setup_message_port, 4580 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4581 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4582 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4583 .stats_get_strings = mv88e6320_stats_get_strings, 4584 .stats_get_stats = mv88e6390_stats_get_stats, 4585 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4586 .set_egress_port = mv88e6390_g1_set_egress_port, 4587 .watchdog_ops = &mv88e6390_watchdog_ops, 4588 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4589 .pot_clear = mv88e6xxx_g2_pot_clear, 4590 .reset = mv88e6352_g1_reset, 4591 .rmu_disable = mv88e6390_g1_rmu_disable, 4592 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4593 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4594 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4595 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4596 .serdes_power = mv88e6390_serdes_power, 4597 .serdes_get_lane = mv88e6341_serdes_get_lane, 4598 /* Check status register pause & lpa register */ 4599 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4600 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4601 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4602 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4603 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4604 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4605 .serdes_irq_status = mv88e6390_serdes_irq_status, 4606 .gpio_ops = &mv88e6352_gpio_ops, 4607 .avb_ops = &mv88e6390_avb_ops, 4608 .ptp_ops = &mv88e6352_ptp_ops, 4609 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4610 .serdes_get_strings = mv88e6390_serdes_get_strings, 4611 .serdes_get_stats = mv88e6390_serdes_get_stats, 4612 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4613 .serdes_get_regs = mv88e6390_serdes_get_regs, 4614 .phylink_validate = mv88e6341_phylink_validate, 4615 }; 4616 4617 static const struct mv88e6xxx_ops mv88e6350_ops = { 4618 /* MV88E6XXX_FAMILY_6351 */ 4619 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4620 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4621 .irl_init_all = mv88e6352_g2_irl_init_all, 4622 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4623 .phy_read = mv88e6xxx_g2_smi_phy_read, 4624 .phy_write = mv88e6xxx_g2_smi_phy_write, 4625 .port_set_link = mv88e6xxx_port_set_link, 4626 .port_sync_link = mv88e6xxx_port_sync_link, 4627 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4628 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4629 .port_tag_remap = mv88e6095_port_tag_remap, 4630 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4631 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4632 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4633 .port_set_ether_type = mv88e6351_port_set_ether_type, 4634 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4635 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4636 .port_pause_limit = mv88e6097_port_pause_limit, 4637 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4638 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4639 .port_get_cmode = mv88e6352_port_get_cmode, 4640 .port_setup_message_port = mv88e6xxx_setup_message_port, 4641 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4642 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4643 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4644 .stats_get_strings = mv88e6095_stats_get_strings, 4645 .stats_get_stats = mv88e6095_stats_get_stats, 4646 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4647 .set_egress_port = mv88e6095_g1_set_egress_port, 4648 .watchdog_ops = &mv88e6097_watchdog_ops, 4649 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4650 .pot_clear = mv88e6xxx_g2_pot_clear, 4651 .reset = mv88e6352_g1_reset, 4652 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4653 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4654 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4655 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4656 .phylink_validate = mv88e6185_phylink_validate, 4657 }; 4658 4659 static const struct mv88e6xxx_ops mv88e6351_ops = { 4660 /* MV88E6XXX_FAMILY_6351 */ 4661 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4662 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4663 .irl_init_all = mv88e6352_g2_irl_init_all, 4664 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4665 .phy_read = mv88e6xxx_g2_smi_phy_read, 4666 .phy_write = mv88e6xxx_g2_smi_phy_write, 4667 .port_set_link = mv88e6xxx_port_set_link, 4668 .port_sync_link = mv88e6xxx_port_sync_link, 4669 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4670 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4671 .port_tag_remap = mv88e6095_port_tag_remap, 4672 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4673 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4674 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4675 .port_set_ether_type = mv88e6351_port_set_ether_type, 4676 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4677 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4678 .port_pause_limit = mv88e6097_port_pause_limit, 4679 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4680 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4681 .port_get_cmode = mv88e6352_port_get_cmode, 4682 .port_setup_message_port = mv88e6xxx_setup_message_port, 4683 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4684 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4685 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4686 .stats_get_strings = mv88e6095_stats_get_strings, 4687 .stats_get_stats = mv88e6095_stats_get_stats, 4688 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4689 .set_egress_port = mv88e6095_g1_set_egress_port, 4690 .watchdog_ops = &mv88e6097_watchdog_ops, 4691 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4692 .pot_clear = mv88e6xxx_g2_pot_clear, 4693 .reset = mv88e6352_g1_reset, 4694 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4695 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4696 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4697 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4698 .avb_ops = &mv88e6352_avb_ops, 4699 .ptp_ops = &mv88e6352_ptp_ops, 4700 .phylink_validate = mv88e6185_phylink_validate, 4701 }; 4702 4703 static const struct mv88e6xxx_ops mv88e6352_ops = { 4704 /* MV88E6XXX_FAMILY_6352 */ 4705 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4706 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4707 .irl_init_all = mv88e6352_g2_irl_init_all, 4708 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4709 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4710 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4711 .phy_read = mv88e6xxx_g2_smi_phy_read, 4712 .phy_write = mv88e6xxx_g2_smi_phy_write, 4713 .port_set_link = mv88e6xxx_port_set_link, 4714 .port_sync_link = mv88e6xxx_port_sync_link, 4715 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4716 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4717 .port_tag_remap = mv88e6095_port_tag_remap, 4718 .port_set_policy = mv88e6352_port_set_policy, 4719 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4720 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4721 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4722 .port_set_ether_type = mv88e6351_port_set_ether_type, 4723 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4724 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4725 .port_pause_limit = mv88e6097_port_pause_limit, 4726 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4727 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4728 .port_get_cmode = mv88e6352_port_get_cmode, 4729 .port_setup_message_port = mv88e6xxx_setup_message_port, 4730 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4731 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4732 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4733 .stats_get_strings = mv88e6095_stats_get_strings, 4734 .stats_get_stats = mv88e6095_stats_get_stats, 4735 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4736 .set_egress_port = mv88e6095_g1_set_egress_port, 4737 .watchdog_ops = &mv88e6097_watchdog_ops, 4738 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4739 .pot_clear = mv88e6xxx_g2_pot_clear, 4740 .reset = mv88e6352_g1_reset, 4741 .rmu_disable = mv88e6352_g1_rmu_disable, 4742 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4743 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4744 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4745 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4746 .serdes_get_lane = mv88e6352_serdes_get_lane, 4747 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4748 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4749 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4750 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4751 .serdes_power = mv88e6352_serdes_power, 4752 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4753 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4754 .serdes_irq_status = mv88e6352_serdes_irq_status, 4755 .gpio_ops = &mv88e6352_gpio_ops, 4756 .avb_ops = &mv88e6352_avb_ops, 4757 .ptp_ops = &mv88e6352_ptp_ops, 4758 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4759 .serdes_get_strings = mv88e6352_serdes_get_strings, 4760 .serdes_get_stats = mv88e6352_serdes_get_stats, 4761 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4762 .serdes_get_regs = mv88e6352_serdes_get_regs, 4763 .phylink_validate = mv88e6352_phylink_validate, 4764 }; 4765 4766 static const struct mv88e6xxx_ops mv88e6390_ops = { 4767 /* MV88E6XXX_FAMILY_6390 */ 4768 .setup_errata = mv88e6390_setup_errata, 4769 .irl_init_all = mv88e6390_g2_irl_init_all, 4770 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4771 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4772 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4773 .phy_read = mv88e6xxx_g2_smi_phy_read, 4774 .phy_write = mv88e6xxx_g2_smi_phy_write, 4775 .port_set_link = mv88e6xxx_port_set_link, 4776 .port_sync_link = mv88e6xxx_port_sync_link, 4777 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4778 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4779 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4780 .port_tag_remap = mv88e6390_port_tag_remap, 4781 .port_set_policy = mv88e6352_port_set_policy, 4782 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4783 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4784 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4785 .port_set_ether_type = mv88e6351_port_set_ether_type, 4786 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4787 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4788 .port_pause_limit = mv88e6390_port_pause_limit, 4789 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4790 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4791 .port_get_cmode = mv88e6352_port_get_cmode, 4792 .port_set_cmode = mv88e6390_port_set_cmode, 4793 .port_setup_message_port = mv88e6xxx_setup_message_port, 4794 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4795 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4796 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4797 .stats_get_strings = mv88e6320_stats_get_strings, 4798 .stats_get_stats = mv88e6390_stats_get_stats, 4799 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4800 .set_egress_port = mv88e6390_g1_set_egress_port, 4801 .watchdog_ops = &mv88e6390_watchdog_ops, 4802 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4803 .pot_clear = mv88e6xxx_g2_pot_clear, 4804 .reset = mv88e6352_g1_reset, 4805 .rmu_disable = mv88e6390_g1_rmu_disable, 4806 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4807 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4808 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4809 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4810 .serdes_power = mv88e6390_serdes_power, 4811 .serdes_get_lane = mv88e6390_serdes_get_lane, 4812 /* Check status register pause & lpa register */ 4813 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4814 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4815 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4816 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4817 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4818 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4819 .serdes_irq_status = mv88e6390_serdes_irq_status, 4820 .gpio_ops = &mv88e6352_gpio_ops, 4821 .avb_ops = &mv88e6390_avb_ops, 4822 .ptp_ops = &mv88e6352_ptp_ops, 4823 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4824 .serdes_get_strings = mv88e6390_serdes_get_strings, 4825 .serdes_get_stats = mv88e6390_serdes_get_stats, 4826 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4827 .serdes_get_regs = mv88e6390_serdes_get_regs, 4828 .phylink_validate = mv88e6390_phylink_validate, 4829 }; 4830 4831 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4832 /* MV88E6XXX_FAMILY_6390 */ 4833 .setup_errata = mv88e6390_setup_errata, 4834 .irl_init_all = mv88e6390_g2_irl_init_all, 4835 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4836 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4837 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4838 .phy_read = mv88e6xxx_g2_smi_phy_read, 4839 .phy_write = mv88e6xxx_g2_smi_phy_write, 4840 .port_set_link = mv88e6xxx_port_set_link, 4841 .port_sync_link = mv88e6xxx_port_sync_link, 4842 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4843 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4844 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4845 .port_tag_remap = mv88e6390_port_tag_remap, 4846 .port_set_policy = mv88e6352_port_set_policy, 4847 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4848 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4849 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4850 .port_set_ether_type = mv88e6351_port_set_ether_type, 4851 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4852 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4853 .port_pause_limit = mv88e6390_port_pause_limit, 4854 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4855 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4856 .port_get_cmode = mv88e6352_port_get_cmode, 4857 .port_set_cmode = mv88e6390x_port_set_cmode, 4858 .port_setup_message_port = mv88e6xxx_setup_message_port, 4859 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4860 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4861 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4862 .stats_get_strings = mv88e6320_stats_get_strings, 4863 .stats_get_stats = mv88e6390_stats_get_stats, 4864 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4865 .set_egress_port = mv88e6390_g1_set_egress_port, 4866 .watchdog_ops = &mv88e6390_watchdog_ops, 4867 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4868 .pot_clear = mv88e6xxx_g2_pot_clear, 4869 .reset = mv88e6352_g1_reset, 4870 .rmu_disable = mv88e6390_g1_rmu_disable, 4871 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4872 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4873 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4874 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4875 .serdes_power = mv88e6390_serdes_power, 4876 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4877 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4878 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4879 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4880 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4881 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4882 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4883 .serdes_irq_status = mv88e6390_serdes_irq_status, 4884 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4885 .serdes_get_strings = mv88e6390_serdes_get_strings, 4886 .serdes_get_stats = mv88e6390_serdes_get_stats, 4887 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4888 .serdes_get_regs = mv88e6390_serdes_get_regs, 4889 .gpio_ops = &mv88e6352_gpio_ops, 4890 .avb_ops = &mv88e6390_avb_ops, 4891 .ptp_ops = &mv88e6352_ptp_ops, 4892 .phylink_validate = mv88e6390x_phylink_validate, 4893 }; 4894 4895 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4896 /* MV88E6XXX_FAMILY_6393 */ 4897 .setup_errata = mv88e6393x_serdes_setup_errata, 4898 .irl_init_all = mv88e6390_g2_irl_init_all, 4899 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4900 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4901 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4902 .phy_read = mv88e6xxx_g2_smi_phy_read, 4903 .phy_write = mv88e6xxx_g2_smi_phy_write, 4904 .port_set_link = mv88e6xxx_port_set_link, 4905 .port_sync_link = mv88e6xxx_port_sync_link, 4906 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4907 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4908 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4909 .port_tag_remap = mv88e6390_port_tag_remap, 4910 .port_set_policy = mv88e6393x_port_set_policy, 4911 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4912 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4913 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4914 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4915 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4916 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4917 .port_pause_limit = mv88e6390_port_pause_limit, 4918 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4919 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4920 .port_get_cmode = mv88e6352_port_get_cmode, 4921 .port_set_cmode = mv88e6393x_port_set_cmode, 4922 .port_setup_message_port = mv88e6xxx_setup_message_port, 4923 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4924 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4925 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4926 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4927 .stats_get_strings = mv88e6320_stats_get_strings, 4928 .stats_get_stats = mv88e6390_stats_get_stats, 4929 /* .set_cpu_port is missing because this family does not support a global 4930 * CPU port, only per port CPU port which is set via 4931 * .port_set_upstream_port method. 4932 */ 4933 .set_egress_port = mv88e6393x_set_egress_port, 4934 .watchdog_ops = &mv88e6390_watchdog_ops, 4935 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4936 .pot_clear = mv88e6xxx_g2_pot_clear, 4937 .reset = mv88e6352_g1_reset, 4938 .rmu_disable = mv88e6390_g1_rmu_disable, 4939 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4940 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4941 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4942 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4943 .serdes_power = mv88e6393x_serdes_power, 4944 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4945 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4946 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4947 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4948 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4949 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4950 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4951 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4952 /* TODO: serdes stats */ 4953 .gpio_ops = &mv88e6352_gpio_ops, 4954 .avb_ops = &mv88e6390_avb_ops, 4955 .ptp_ops = &mv88e6352_ptp_ops, 4956 .phylink_validate = mv88e6393x_phylink_validate, 4957 }; 4958 4959 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4960 [MV88E6085] = { 4961 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4962 .family = MV88E6XXX_FAMILY_6097, 4963 .name = "Marvell 88E6085", 4964 .num_databases = 4096, 4965 .num_macs = 8192, 4966 .num_ports = 10, 4967 .num_internal_phys = 5, 4968 .max_vid = 4095, 4969 .port_base_addr = 0x10, 4970 .phy_base_addr = 0x0, 4971 .global1_addr = 0x1b, 4972 .global2_addr = 0x1c, 4973 .age_time_coeff = 15000, 4974 .g1_irqs = 8, 4975 .g2_irqs = 10, 4976 .atu_move_port_mask = 0xf, 4977 .pvt = true, 4978 .multi_chip = true, 4979 .ops = &mv88e6085_ops, 4980 }, 4981 4982 [MV88E6095] = { 4983 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4984 .family = MV88E6XXX_FAMILY_6095, 4985 .name = "Marvell 88E6095/88E6095F", 4986 .num_databases = 256, 4987 .num_macs = 8192, 4988 .num_ports = 11, 4989 .num_internal_phys = 0, 4990 .max_vid = 4095, 4991 .port_base_addr = 0x10, 4992 .phy_base_addr = 0x0, 4993 .global1_addr = 0x1b, 4994 .global2_addr = 0x1c, 4995 .age_time_coeff = 15000, 4996 .g1_irqs = 8, 4997 .atu_move_port_mask = 0xf, 4998 .multi_chip = true, 4999 .ops = &mv88e6095_ops, 5000 }, 5001 5002 [MV88E6097] = { 5003 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5004 .family = MV88E6XXX_FAMILY_6097, 5005 .name = "Marvell 88E6097/88E6097F", 5006 .num_databases = 4096, 5007 .num_macs = 8192, 5008 .num_ports = 11, 5009 .num_internal_phys = 8, 5010 .max_vid = 4095, 5011 .port_base_addr = 0x10, 5012 .phy_base_addr = 0x0, 5013 .global1_addr = 0x1b, 5014 .global2_addr = 0x1c, 5015 .age_time_coeff = 15000, 5016 .g1_irqs = 8, 5017 .g2_irqs = 10, 5018 .atu_move_port_mask = 0xf, 5019 .pvt = true, 5020 .multi_chip = true, 5021 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5022 .ops = &mv88e6097_ops, 5023 }, 5024 5025 [MV88E6123] = { 5026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5027 .family = MV88E6XXX_FAMILY_6165, 5028 .name = "Marvell 88E6123", 5029 .num_databases = 4096, 5030 .num_macs = 1024, 5031 .num_ports = 3, 5032 .num_internal_phys = 5, 5033 .max_vid = 4095, 5034 .port_base_addr = 0x10, 5035 .phy_base_addr = 0x0, 5036 .global1_addr = 0x1b, 5037 .global2_addr = 0x1c, 5038 .age_time_coeff = 15000, 5039 .g1_irqs = 9, 5040 .g2_irqs = 10, 5041 .atu_move_port_mask = 0xf, 5042 .pvt = true, 5043 .multi_chip = true, 5044 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5045 .ops = &mv88e6123_ops, 5046 }, 5047 5048 [MV88E6131] = { 5049 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5050 .family = MV88E6XXX_FAMILY_6185, 5051 .name = "Marvell 88E6131", 5052 .num_databases = 256, 5053 .num_macs = 8192, 5054 .num_ports = 8, 5055 .num_internal_phys = 0, 5056 .max_vid = 4095, 5057 .port_base_addr = 0x10, 5058 .phy_base_addr = 0x0, 5059 .global1_addr = 0x1b, 5060 .global2_addr = 0x1c, 5061 .age_time_coeff = 15000, 5062 .g1_irqs = 9, 5063 .atu_move_port_mask = 0xf, 5064 .multi_chip = true, 5065 .ops = &mv88e6131_ops, 5066 }, 5067 5068 [MV88E6141] = { 5069 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5070 .family = MV88E6XXX_FAMILY_6341, 5071 .name = "Marvell 88E6141", 5072 .num_databases = 4096, 5073 .num_macs = 2048, 5074 .num_ports = 6, 5075 .num_internal_phys = 5, 5076 .num_gpio = 11, 5077 .max_vid = 4095, 5078 .port_base_addr = 0x10, 5079 .phy_base_addr = 0x10, 5080 .global1_addr = 0x1b, 5081 .global2_addr = 0x1c, 5082 .age_time_coeff = 3750, 5083 .atu_move_port_mask = 0x1f, 5084 .g1_irqs = 9, 5085 .g2_irqs = 10, 5086 .pvt = true, 5087 .multi_chip = true, 5088 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5089 .ops = &mv88e6141_ops, 5090 }, 5091 5092 [MV88E6161] = { 5093 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5094 .family = MV88E6XXX_FAMILY_6165, 5095 .name = "Marvell 88E6161", 5096 .num_databases = 4096, 5097 .num_macs = 1024, 5098 .num_ports = 6, 5099 .num_internal_phys = 5, 5100 .max_vid = 4095, 5101 .port_base_addr = 0x10, 5102 .phy_base_addr = 0x0, 5103 .global1_addr = 0x1b, 5104 .global2_addr = 0x1c, 5105 .age_time_coeff = 15000, 5106 .g1_irqs = 9, 5107 .g2_irqs = 10, 5108 .atu_move_port_mask = 0xf, 5109 .pvt = true, 5110 .multi_chip = true, 5111 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5112 .ptp_support = true, 5113 .ops = &mv88e6161_ops, 5114 }, 5115 5116 [MV88E6165] = { 5117 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5118 .family = MV88E6XXX_FAMILY_6165, 5119 .name = "Marvell 88E6165", 5120 .num_databases = 4096, 5121 .num_macs = 8192, 5122 .num_ports = 6, 5123 .num_internal_phys = 0, 5124 .max_vid = 4095, 5125 .port_base_addr = 0x10, 5126 .phy_base_addr = 0x0, 5127 .global1_addr = 0x1b, 5128 .global2_addr = 0x1c, 5129 .age_time_coeff = 15000, 5130 .g1_irqs = 9, 5131 .g2_irqs = 10, 5132 .atu_move_port_mask = 0xf, 5133 .pvt = true, 5134 .multi_chip = true, 5135 .ptp_support = true, 5136 .ops = &mv88e6165_ops, 5137 }, 5138 5139 [MV88E6171] = { 5140 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5141 .family = MV88E6XXX_FAMILY_6351, 5142 .name = "Marvell 88E6171", 5143 .num_databases = 4096, 5144 .num_macs = 8192, 5145 .num_ports = 7, 5146 .num_internal_phys = 5, 5147 .max_vid = 4095, 5148 .port_base_addr = 0x10, 5149 .phy_base_addr = 0x0, 5150 .global1_addr = 0x1b, 5151 .global2_addr = 0x1c, 5152 .age_time_coeff = 15000, 5153 .g1_irqs = 9, 5154 .g2_irqs = 10, 5155 .atu_move_port_mask = 0xf, 5156 .pvt = true, 5157 .multi_chip = true, 5158 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5159 .ops = &mv88e6171_ops, 5160 }, 5161 5162 [MV88E6172] = { 5163 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5164 .family = MV88E6XXX_FAMILY_6352, 5165 .name = "Marvell 88E6172", 5166 .num_databases = 4096, 5167 .num_macs = 8192, 5168 .num_ports = 7, 5169 .num_internal_phys = 5, 5170 .num_gpio = 15, 5171 .max_vid = 4095, 5172 .port_base_addr = 0x10, 5173 .phy_base_addr = 0x0, 5174 .global1_addr = 0x1b, 5175 .global2_addr = 0x1c, 5176 .age_time_coeff = 15000, 5177 .g1_irqs = 9, 5178 .g2_irqs = 10, 5179 .atu_move_port_mask = 0xf, 5180 .pvt = true, 5181 .multi_chip = true, 5182 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5183 .ops = &mv88e6172_ops, 5184 }, 5185 5186 [MV88E6175] = { 5187 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5188 .family = MV88E6XXX_FAMILY_6351, 5189 .name = "Marvell 88E6175", 5190 .num_databases = 4096, 5191 .num_macs = 8192, 5192 .num_ports = 7, 5193 .num_internal_phys = 5, 5194 .max_vid = 4095, 5195 .port_base_addr = 0x10, 5196 .phy_base_addr = 0x0, 5197 .global1_addr = 0x1b, 5198 .global2_addr = 0x1c, 5199 .age_time_coeff = 15000, 5200 .g1_irqs = 9, 5201 .g2_irqs = 10, 5202 .atu_move_port_mask = 0xf, 5203 .pvt = true, 5204 .multi_chip = true, 5205 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5206 .ops = &mv88e6175_ops, 5207 }, 5208 5209 [MV88E6176] = { 5210 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5211 .family = MV88E6XXX_FAMILY_6352, 5212 .name = "Marvell 88E6176", 5213 .num_databases = 4096, 5214 .num_macs = 8192, 5215 .num_ports = 7, 5216 .num_internal_phys = 5, 5217 .num_gpio = 15, 5218 .max_vid = 4095, 5219 .port_base_addr = 0x10, 5220 .phy_base_addr = 0x0, 5221 .global1_addr = 0x1b, 5222 .global2_addr = 0x1c, 5223 .age_time_coeff = 15000, 5224 .g1_irqs = 9, 5225 .g2_irqs = 10, 5226 .atu_move_port_mask = 0xf, 5227 .pvt = true, 5228 .multi_chip = true, 5229 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5230 .ops = &mv88e6176_ops, 5231 }, 5232 5233 [MV88E6185] = { 5234 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5235 .family = MV88E6XXX_FAMILY_6185, 5236 .name = "Marvell 88E6185", 5237 .num_databases = 256, 5238 .num_macs = 8192, 5239 .num_ports = 10, 5240 .num_internal_phys = 0, 5241 .max_vid = 4095, 5242 .port_base_addr = 0x10, 5243 .phy_base_addr = 0x0, 5244 .global1_addr = 0x1b, 5245 .global2_addr = 0x1c, 5246 .age_time_coeff = 15000, 5247 .g1_irqs = 8, 5248 .atu_move_port_mask = 0xf, 5249 .multi_chip = true, 5250 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5251 .ops = &mv88e6185_ops, 5252 }, 5253 5254 [MV88E6190] = { 5255 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5256 .family = MV88E6XXX_FAMILY_6390, 5257 .name = "Marvell 88E6190", 5258 .num_databases = 4096, 5259 .num_macs = 16384, 5260 .num_ports = 11, /* 10 + Z80 */ 5261 .num_internal_phys = 9, 5262 .num_gpio = 16, 5263 .max_vid = 8191, 5264 .port_base_addr = 0x0, 5265 .phy_base_addr = 0x0, 5266 .global1_addr = 0x1b, 5267 .global2_addr = 0x1c, 5268 .age_time_coeff = 3750, 5269 .g1_irqs = 9, 5270 .g2_irqs = 14, 5271 .pvt = true, 5272 .multi_chip = true, 5273 .atu_move_port_mask = 0x1f, 5274 .ops = &mv88e6190_ops, 5275 }, 5276 5277 [MV88E6190X] = { 5278 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5279 .family = MV88E6XXX_FAMILY_6390, 5280 .name = "Marvell 88E6190X", 5281 .num_databases = 4096, 5282 .num_macs = 16384, 5283 .num_ports = 11, /* 10 + Z80 */ 5284 .num_internal_phys = 9, 5285 .num_gpio = 16, 5286 .max_vid = 8191, 5287 .port_base_addr = 0x0, 5288 .phy_base_addr = 0x0, 5289 .global1_addr = 0x1b, 5290 .global2_addr = 0x1c, 5291 .age_time_coeff = 3750, 5292 .g1_irqs = 9, 5293 .g2_irqs = 14, 5294 .atu_move_port_mask = 0x1f, 5295 .pvt = true, 5296 .multi_chip = true, 5297 .ops = &mv88e6190x_ops, 5298 }, 5299 5300 [MV88E6191] = { 5301 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5302 .family = MV88E6XXX_FAMILY_6390, 5303 .name = "Marvell 88E6191", 5304 .num_databases = 4096, 5305 .num_macs = 16384, 5306 .num_ports = 11, /* 10 + Z80 */ 5307 .num_internal_phys = 9, 5308 .max_vid = 8191, 5309 .port_base_addr = 0x0, 5310 .phy_base_addr = 0x0, 5311 .global1_addr = 0x1b, 5312 .global2_addr = 0x1c, 5313 .age_time_coeff = 3750, 5314 .g1_irqs = 9, 5315 .g2_irqs = 14, 5316 .atu_move_port_mask = 0x1f, 5317 .pvt = true, 5318 .multi_chip = true, 5319 .ptp_support = true, 5320 .ops = &mv88e6191_ops, 5321 }, 5322 5323 [MV88E6191X] = { 5324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5325 .family = MV88E6XXX_FAMILY_6393, 5326 .name = "Marvell 88E6191X", 5327 .num_databases = 4096, 5328 .num_ports = 11, /* 10 + Z80 */ 5329 .num_internal_phys = 9, 5330 .max_vid = 8191, 5331 .port_base_addr = 0x0, 5332 .phy_base_addr = 0x0, 5333 .global1_addr = 0x1b, 5334 .global2_addr = 0x1c, 5335 .age_time_coeff = 3750, 5336 .g1_irqs = 10, 5337 .g2_irqs = 14, 5338 .atu_move_port_mask = 0x1f, 5339 .pvt = true, 5340 .multi_chip = true, 5341 .ptp_support = true, 5342 .ops = &mv88e6393x_ops, 5343 }, 5344 5345 [MV88E6193X] = { 5346 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5347 .family = MV88E6XXX_FAMILY_6393, 5348 .name = "Marvell 88E6193X", 5349 .num_databases = 4096, 5350 .num_ports = 11, /* 10 + Z80 */ 5351 .num_internal_phys = 9, 5352 .max_vid = 8191, 5353 .port_base_addr = 0x0, 5354 .phy_base_addr = 0x0, 5355 .global1_addr = 0x1b, 5356 .global2_addr = 0x1c, 5357 .age_time_coeff = 3750, 5358 .g1_irqs = 10, 5359 .g2_irqs = 14, 5360 .atu_move_port_mask = 0x1f, 5361 .pvt = true, 5362 .multi_chip = true, 5363 .ptp_support = true, 5364 .ops = &mv88e6393x_ops, 5365 }, 5366 5367 [MV88E6220] = { 5368 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5369 .family = MV88E6XXX_FAMILY_6250, 5370 .name = "Marvell 88E6220", 5371 .num_databases = 64, 5372 5373 /* Ports 2-4 are not routed to pins 5374 * => usable ports 0, 1, 5, 6 5375 */ 5376 .num_ports = 7, 5377 .num_internal_phys = 2, 5378 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5379 .max_vid = 4095, 5380 .port_base_addr = 0x08, 5381 .phy_base_addr = 0x00, 5382 .global1_addr = 0x0f, 5383 .global2_addr = 0x07, 5384 .age_time_coeff = 15000, 5385 .g1_irqs = 9, 5386 .g2_irqs = 10, 5387 .atu_move_port_mask = 0xf, 5388 .dual_chip = true, 5389 .ptp_support = true, 5390 .ops = &mv88e6250_ops, 5391 }, 5392 5393 [MV88E6240] = { 5394 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5395 .family = MV88E6XXX_FAMILY_6352, 5396 .name = "Marvell 88E6240", 5397 .num_databases = 4096, 5398 .num_macs = 8192, 5399 .num_ports = 7, 5400 .num_internal_phys = 5, 5401 .num_gpio = 15, 5402 .max_vid = 4095, 5403 .port_base_addr = 0x10, 5404 .phy_base_addr = 0x0, 5405 .global1_addr = 0x1b, 5406 .global2_addr = 0x1c, 5407 .age_time_coeff = 15000, 5408 .g1_irqs = 9, 5409 .g2_irqs = 10, 5410 .atu_move_port_mask = 0xf, 5411 .pvt = true, 5412 .multi_chip = true, 5413 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5414 .ptp_support = true, 5415 .ops = &mv88e6240_ops, 5416 }, 5417 5418 [MV88E6250] = { 5419 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5420 .family = MV88E6XXX_FAMILY_6250, 5421 .name = "Marvell 88E6250", 5422 .num_databases = 64, 5423 .num_ports = 7, 5424 .num_internal_phys = 5, 5425 .max_vid = 4095, 5426 .port_base_addr = 0x08, 5427 .phy_base_addr = 0x00, 5428 .global1_addr = 0x0f, 5429 .global2_addr = 0x07, 5430 .age_time_coeff = 15000, 5431 .g1_irqs = 9, 5432 .g2_irqs = 10, 5433 .atu_move_port_mask = 0xf, 5434 .dual_chip = true, 5435 .ptp_support = true, 5436 .ops = &mv88e6250_ops, 5437 }, 5438 5439 [MV88E6290] = { 5440 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5441 .family = MV88E6XXX_FAMILY_6390, 5442 .name = "Marvell 88E6290", 5443 .num_databases = 4096, 5444 .num_ports = 11, /* 10 + Z80 */ 5445 .num_internal_phys = 9, 5446 .num_gpio = 16, 5447 .max_vid = 8191, 5448 .port_base_addr = 0x0, 5449 .phy_base_addr = 0x0, 5450 .global1_addr = 0x1b, 5451 .global2_addr = 0x1c, 5452 .age_time_coeff = 3750, 5453 .g1_irqs = 9, 5454 .g2_irqs = 14, 5455 .atu_move_port_mask = 0x1f, 5456 .pvt = true, 5457 .multi_chip = true, 5458 .ptp_support = true, 5459 .ops = &mv88e6290_ops, 5460 }, 5461 5462 [MV88E6320] = { 5463 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5464 .family = MV88E6XXX_FAMILY_6320, 5465 .name = "Marvell 88E6320", 5466 .num_databases = 4096, 5467 .num_macs = 8192, 5468 .num_ports = 7, 5469 .num_internal_phys = 5, 5470 .num_gpio = 15, 5471 .max_vid = 4095, 5472 .port_base_addr = 0x10, 5473 .phy_base_addr = 0x0, 5474 .global1_addr = 0x1b, 5475 .global2_addr = 0x1c, 5476 .age_time_coeff = 15000, 5477 .g1_irqs = 8, 5478 .g2_irqs = 10, 5479 .atu_move_port_mask = 0xf, 5480 .pvt = true, 5481 .multi_chip = true, 5482 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5483 .ptp_support = true, 5484 .ops = &mv88e6320_ops, 5485 }, 5486 5487 [MV88E6321] = { 5488 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5489 .family = MV88E6XXX_FAMILY_6320, 5490 .name = "Marvell 88E6321", 5491 .num_databases = 4096, 5492 .num_macs = 8192, 5493 .num_ports = 7, 5494 .num_internal_phys = 5, 5495 .num_gpio = 15, 5496 .max_vid = 4095, 5497 .port_base_addr = 0x10, 5498 .phy_base_addr = 0x0, 5499 .global1_addr = 0x1b, 5500 .global2_addr = 0x1c, 5501 .age_time_coeff = 15000, 5502 .g1_irqs = 8, 5503 .g2_irqs = 10, 5504 .atu_move_port_mask = 0xf, 5505 .multi_chip = true, 5506 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5507 .ptp_support = true, 5508 .ops = &mv88e6321_ops, 5509 }, 5510 5511 [MV88E6341] = { 5512 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5513 .family = MV88E6XXX_FAMILY_6341, 5514 .name = "Marvell 88E6341", 5515 .num_databases = 4096, 5516 .num_macs = 2048, 5517 .num_internal_phys = 5, 5518 .num_ports = 6, 5519 .num_gpio = 11, 5520 .max_vid = 4095, 5521 .port_base_addr = 0x10, 5522 .phy_base_addr = 0x10, 5523 .global1_addr = 0x1b, 5524 .global2_addr = 0x1c, 5525 .age_time_coeff = 3750, 5526 .atu_move_port_mask = 0x1f, 5527 .g1_irqs = 9, 5528 .g2_irqs = 10, 5529 .pvt = true, 5530 .multi_chip = true, 5531 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5532 .ptp_support = true, 5533 .ops = &mv88e6341_ops, 5534 }, 5535 5536 [MV88E6350] = { 5537 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5538 .family = MV88E6XXX_FAMILY_6351, 5539 .name = "Marvell 88E6350", 5540 .num_databases = 4096, 5541 .num_macs = 8192, 5542 .num_ports = 7, 5543 .num_internal_phys = 5, 5544 .max_vid = 4095, 5545 .port_base_addr = 0x10, 5546 .phy_base_addr = 0x0, 5547 .global1_addr = 0x1b, 5548 .global2_addr = 0x1c, 5549 .age_time_coeff = 15000, 5550 .g1_irqs = 9, 5551 .g2_irqs = 10, 5552 .atu_move_port_mask = 0xf, 5553 .pvt = true, 5554 .multi_chip = true, 5555 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5556 .ops = &mv88e6350_ops, 5557 }, 5558 5559 [MV88E6351] = { 5560 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5561 .family = MV88E6XXX_FAMILY_6351, 5562 .name = "Marvell 88E6351", 5563 .num_databases = 4096, 5564 .num_macs = 8192, 5565 .num_ports = 7, 5566 .num_internal_phys = 5, 5567 .max_vid = 4095, 5568 .port_base_addr = 0x10, 5569 .phy_base_addr = 0x0, 5570 .global1_addr = 0x1b, 5571 .global2_addr = 0x1c, 5572 .age_time_coeff = 15000, 5573 .g1_irqs = 9, 5574 .g2_irqs = 10, 5575 .atu_move_port_mask = 0xf, 5576 .pvt = true, 5577 .multi_chip = true, 5578 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5579 .ops = &mv88e6351_ops, 5580 }, 5581 5582 [MV88E6352] = { 5583 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5584 .family = MV88E6XXX_FAMILY_6352, 5585 .name = "Marvell 88E6352", 5586 .num_databases = 4096, 5587 .num_macs = 8192, 5588 .num_ports = 7, 5589 .num_internal_phys = 5, 5590 .num_gpio = 15, 5591 .max_vid = 4095, 5592 .port_base_addr = 0x10, 5593 .phy_base_addr = 0x0, 5594 .global1_addr = 0x1b, 5595 .global2_addr = 0x1c, 5596 .age_time_coeff = 15000, 5597 .g1_irqs = 9, 5598 .g2_irqs = 10, 5599 .atu_move_port_mask = 0xf, 5600 .pvt = true, 5601 .multi_chip = true, 5602 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5603 .ptp_support = true, 5604 .ops = &mv88e6352_ops, 5605 }, 5606 [MV88E6390] = { 5607 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5608 .family = MV88E6XXX_FAMILY_6390, 5609 .name = "Marvell 88E6390", 5610 .num_databases = 4096, 5611 .num_macs = 16384, 5612 .num_ports = 11, /* 10 + Z80 */ 5613 .num_internal_phys = 9, 5614 .num_gpio = 16, 5615 .max_vid = 8191, 5616 .port_base_addr = 0x0, 5617 .phy_base_addr = 0x0, 5618 .global1_addr = 0x1b, 5619 .global2_addr = 0x1c, 5620 .age_time_coeff = 3750, 5621 .g1_irqs = 9, 5622 .g2_irqs = 14, 5623 .atu_move_port_mask = 0x1f, 5624 .pvt = true, 5625 .multi_chip = true, 5626 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5627 .ptp_support = true, 5628 .ops = &mv88e6390_ops, 5629 }, 5630 [MV88E6390X] = { 5631 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5632 .family = MV88E6XXX_FAMILY_6390, 5633 .name = "Marvell 88E6390X", 5634 .num_databases = 4096, 5635 .num_macs = 16384, 5636 .num_ports = 11, /* 10 + Z80 */ 5637 .num_internal_phys = 9, 5638 .num_gpio = 16, 5639 .max_vid = 8191, 5640 .port_base_addr = 0x0, 5641 .phy_base_addr = 0x0, 5642 .global1_addr = 0x1b, 5643 .global2_addr = 0x1c, 5644 .age_time_coeff = 3750, 5645 .g1_irqs = 9, 5646 .g2_irqs = 14, 5647 .atu_move_port_mask = 0x1f, 5648 .pvt = true, 5649 .multi_chip = true, 5650 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5651 .ptp_support = true, 5652 .ops = &mv88e6390x_ops, 5653 }, 5654 5655 [MV88E6393X] = { 5656 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5657 .family = MV88E6XXX_FAMILY_6393, 5658 .name = "Marvell 88E6393X", 5659 .num_databases = 4096, 5660 .num_ports = 11, /* 10 + Z80 */ 5661 .num_internal_phys = 9, 5662 .max_vid = 8191, 5663 .port_base_addr = 0x0, 5664 .phy_base_addr = 0x0, 5665 .global1_addr = 0x1b, 5666 .global2_addr = 0x1c, 5667 .age_time_coeff = 3750, 5668 .g1_irqs = 10, 5669 .g2_irqs = 14, 5670 .atu_move_port_mask = 0x1f, 5671 .pvt = true, 5672 .multi_chip = true, 5673 .ptp_support = true, 5674 .ops = &mv88e6393x_ops, 5675 }, 5676 }; 5677 5678 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5679 { 5680 int i; 5681 5682 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5683 if (mv88e6xxx_table[i].prod_num == prod_num) 5684 return &mv88e6xxx_table[i]; 5685 5686 return NULL; 5687 } 5688 5689 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5690 { 5691 const struct mv88e6xxx_info *info; 5692 unsigned int prod_num, rev; 5693 u16 id; 5694 int err; 5695 5696 mv88e6xxx_reg_lock(chip); 5697 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5698 mv88e6xxx_reg_unlock(chip); 5699 if (err) 5700 return err; 5701 5702 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5703 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5704 5705 info = mv88e6xxx_lookup_info(prod_num); 5706 if (!info) 5707 return -ENODEV; 5708 5709 /* Update the compatible info with the probed one */ 5710 chip->info = info; 5711 5712 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5713 chip->info->prod_num, chip->info->name, rev); 5714 5715 return 0; 5716 } 5717 5718 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5719 { 5720 struct mv88e6xxx_chip *chip; 5721 5722 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5723 if (!chip) 5724 return NULL; 5725 5726 chip->dev = dev; 5727 5728 mutex_init(&chip->reg_lock); 5729 INIT_LIST_HEAD(&chip->mdios); 5730 idr_init(&chip->policies); 5731 5732 return chip; 5733 } 5734 5735 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5736 int port, 5737 enum dsa_tag_protocol m) 5738 { 5739 struct mv88e6xxx_chip *chip = ds->priv; 5740 5741 return chip->tag_protocol; 5742 } 5743 5744 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5745 enum dsa_tag_protocol proto) 5746 { 5747 struct mv88e6xxx_chip *chip = ds->priv; 5748 enum dsa_tag_protocol old_protocol; 5749 int err; 5750 5751 switch (proto) { 5752 case DSA_TAG_PROTO_EDSA: 5753 switch (chip->info->edsa_support) { 5754 case MV88E6XXX_EDSA_UNSUPPORTED: 5755 return -EPROTONOSUPPORT; 5756 case MV88E6XXX_EDSA_UNDOCUMENTED: 5757 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5758 fallthrough; 5759 case MV88E6XXX_EDSA_SUPPORTED: 5760 break; 5761 } 5762 break; 5763 case DSA_TAG_PROTO_DSA: 5764 break; 5765 default: 5766 return -EPROTONOSUPPORT; 5767 } 5768 5769 old_protocol = chip->tag_protocol; 5770 chip->tag_protocol = proto; 5771 5772 mv88e6xxx_reg_lock(chip); 5773 err = mv88e6xxx_setup_port_mode(chip, port); 5774 mv88e6xxx_reg_unlock(chip); 5775 5776 if (err) 5777 chip->tag_protocol = old_protocol; 5778 5779 return err; 5780 } 5781 5782 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5783 const struct switchdev_obj_port_mdb *mdb) 5784 { 5785 struct mv88e6xxx_chip *chip = ds->priv; 5786 int err; 5787 5788 mv88e6xxx_reg_lock(chip); 5789 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5790 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5791 mv88e6xxx_reg_unlock(chip); 5792 5793 return err; 5794 } 5795 5796 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5797 const struct switchdev_obj_port_mdb *mdb) 5798 { 5799 struct mv88e6xxx_chip *chip = ds->priv; 5800 int err; 5801 5802 mv88e6xxx_reg_lock(chip); 5803 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5804 mv88e6xxx_reg_unlock(chip); 5805 5806 return err; 5807 } 5808 5809 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5810 struct dsa_mall_mirror_tc_entry *mirror, 5811 bool ingress) 5812 { 5813 enum mv88e6xxx_egress_direction direction = ingress ? 5814 MV88E6XXX_EGRESS_DIR_INGRESS : 5815 MV88E6XXX_EGRESS_DIR_EGRESS; 5816 struct mv88e6xxx_chip *chip = ds->priv; 5817 bool other_mirrors = false; 5818 int i; 5819 int err; 5820 5821 mutex_lock(&chip->reg_lock); 5822 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5823 mirror->to_local_port) { 5824 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5825 other_mirrors |= ingress ? 5826 chip->ports[i].mirror_ingress : 5827 chip->ports[i].mirror_egress; 5828 5829 /* Can't change egress port when other mirror is active */ 5830 if (other_mirrors) { 5831 err = -EBUSY; 5832 goto out; 5833 } 5834 5835 err = mv88e6xxx_set_egress_port(chip, direction, 5836 mirror->to_local_port); 5837 if (err) 5838 goto out; 5839 } 5840 5841 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5842 out: 5843 mutex_unlock(&chip->reg_lock); 5844 5845 return err; 5846 } 5847 5848 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5849 struct dsa_mall_mirror_tc_entry *mirror) 5850 { 5851 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5852 MV88E6XXX_EGRESS_DIR_INGRESS : 5853 MV88E6XXX_EGRESS_DIR_EGRESS; 5854 struct mv88e6xxx_chip *chip = ds->priv; 5855 bool other_mirrors = false; 5856 int i; 5857 5858 mutex_lock(&chip->reg_lock); 5859 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5860 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5861 5862 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5863 other_mirrors |= mirror->ingress ? 5864 chip->ports[i].mirror_ingress : 5865 chip->ports[i].mirror_egress; 5866 5867 /* Reset egress port when no other mirror is active */ 5868 if (!other_mirrors) { 5869 if (mv88e6xxx_set_egress_port(chip, direction, 5870 dsa_upstream_port(ds, port))) 5871 dev_err(ds->dev, "failed to set egress port\n"); 5872 } 5873 5874 mutex_unlock(&chip->reg_lock); 5875 } 5876 5877 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5878 struct switchdev_brport_flags flags, 5879 struct netlink_ext_ack *extack) 5880 { 5881 struct mv88e6xxx_chip *chip = ds->priv; 5882 const struct mv88e6xxx_ops *ops; 5883 5884 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5885 BR_BCAST_FLOOD)) 5886 return -EINVAL; 5887 5888 ops = chip->info->ops; 5889 5890 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5891 return -EINVAL; 5892 5893 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5894 return -EINVAL; 5895 5896 return 0; 5897 } 5898 5899 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5900 struct switchdev_brport_flags flags, 5901 struct netlink_ext_ack *extack) 5902 { 5903 struct mv88e6xxx_chip *chip = ds->priv; 5904 int err = -EOPNOTSUPP; 5905 5906 mv88e6xxx_reg_lock(chip); 5907 5908 if (flags.mask & BR_LEARNING) { 5909 bool learning = !!(flags.val & BR_LEARNING); 5910 u16 pav = learning ? (1 << port) : 0; 5911 5912 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5913 if (err) 5914 goto out; 5915 } 5916 5917 if (flags.mask & BR_FLOOD) { 5918 bool unicast = !!(flags.val & BR_FLOOD); 5919 5920 err = chip->info->ops->port_set_ucast_flood(chip, port, 5921 unicast); 5922 if (err) 5923 goto out; 5924 } 5925 5926 if (flags.mask & BR_MCAST_FLOOD) { 5927 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5928 5929 err = chip->info->ops->port_set_mcast_flood(chip, port, 5930 multicast); 5931 if (err) 5932 goto out; 5933 } 5934 5935 if (flags.mask & BR_BCAST_FLOOD) { 5936 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5937 5938 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5939 if (err) 5940 goto out; 5941 } 5942 5943 out: 5944 mv88e6xxx_reg_unlock(chip); 5945 5946 return err; 5947 } 5948 5949 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5950 struct net_device *lag, 5951 struct netdev_lag_upper_info *info) 5952 { 5953 struct mv88e6xxx_chip *chip = ds->priv; 5954 struct dsa_port *dp; 5955 int id, members = 0; 5956 5957 if (!mv88e6xxx_has_lag(chip)) 5958 return false; 5959 5960 id = dsa_lag_id(ds->dst, lag); 5961 if (id < 0 || id >= ds->num_lag_ids) 5962 return false; 5963 5964 dsa_lag_foreach_port(dp, ds->dst, lag) 5965 /* Includes the port joining the LAG */ 5966 members++; 5967 5968 if (members > 8) 5969 return false; 5970 5971 /* We could potentially relax this to include active 5972 * backup in the future. 5973 */ 5974 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5975 return false; 5976 5977 /* Ideally we would also validate that the hash type matches 5978 * the hardware. Alas, this is always set to unknown on team 5979 * interfaces. 5980 */ 5981 return true; 5982 } 5983 5984 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5985 { 5986 struct mv88e6xxx_chip *chip = ds->priv; 5987 struct dsa_port *dp; 5988 u16 map = 0; 5989 int id; 5990 5991 id = dsa_lag_id(ds->dst, lag); 5992 5993 /* Build the map of all ports to distribute flows destined for 5994 * this LAG. This can be either a local user port, or a DSA 5995 * port if the LAG port is on a remote chip. 5996 */ 5997 dsa_lag_foreach_port(dp, ds->dst, lag) 5998 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5999 6000 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6001 } 6002 6003 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6004 /* Row number corresponds to the number of active members in a 6005 * LAG. Each column states which of the eight hash buckets are 6006 * mapped to the column:th port in the LAG. 6007 * 6008 * Example: In a LAG with three active ports, the second port 6009 * ([2][1]) would be selected for traffic mapped to buckets 6010 * 3,4,5 (0x38). 6011 */ 6012 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6013 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6014 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6015 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6016 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6017 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6018 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6019 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6020 }; 6021 6022 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6023 int num_tx, int nth) 6024 { 6025 u8 active = 0; 6026 int i; 6027 6028 num_tx = num_tx <= 8 ? num_tx : 8; 6029 if (nth < num_tx) 6030 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6031 6032 for (i = 0; i < 8; i++) { 6033 if (BIT(i) & active) 6034 mask[i] |= BIT(port); 6035 } 6036 } 6037 6038 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6039 { 6040 struct mv88e6xxx_chip *chip = ds->priv; 6041 unsigned int id, num_tx; 6042 struct net_device *lag; 6043 struct dsa_port *dp; 6044 int i, err, nth; 6045 u16 mask[8]; 6046 u16 ivec; 6047 6048 /* Assume no port is a member of any LAG. */ 6049 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6050 6051 /* Disable all masks for ports that _are_ members of a LAG. */ 6052 list_for_each_entry(dp, &ds->dst->ports, list) { 6053 if (!dp->lag_dev || dp->ds != ds) 6054 continue; 6055 6056 ivec &= ~BIT(dp->index); 6057 } 6058 6059 for (i = 0; i < 8; i++) 6060 mask[i] = ivec; 6061 6062 /* Enable the correct subset of masks for all LAG ports that 6063 * are in the Tx set. 6064 */ 6065 dsa_lags_foreach_id(id, ds->dst) { 6066 lag = dsa_lag_dev(ds->dst, id); 6067 if (!lag) 6068 continue; 6069 6070 num_tx = 0; 6071 dsa_lag_foreach_port(dp, ds->dst, lag) { 6072 if (dp->lag_tx_enabled) 6073 num_tx++; 6074 } 6075 6076 if (!num_tx) 6077 continue; 6078 6079 nth = 0; 6080 dsa_lag_foreach_port(dp, ds->dst, lag) { 6081 if (!dp->lag_tx_enabled) 6082 continue; 6083 6084 if (dp->ds == ds) 6085 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6086 num_tx, nth); 6087 6088 nth++; 6089 } 6090 } 6091 6092 for (i = 0; i < 8; i++) { 6093 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6094 if (err) 6095 return err; 6096 } 6097 6098 return 0; 6099 } 6100 6101 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6102 struct net_device *lag) 6103 { 6104 int err; 6105 6106 err = mv88e6xxx_lag_sync_masks(ds); 6107 6108 if (!err) 6109 err = mv88e6xxx_lag_sync_map(ds, lag); 6110 6111 return err; 6112 } 6113 6114 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6115 { 6116 struct mv88e6xxx_chip *chip = ds->priv; 6117 int err; 6118 6119 mv88e6xxx_reg_lock(chip); 6120 err = mv88e6xxx_lag_sync_masks(ds); 6121 mv88e6xxx_reg_unlock(chip); 6122 return err; 6123 } 6124 6125 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6126 struct net_device *lag, 6127 struct netdev_lag_upper_info *info) 6128 { 6129 struct mv88e6xxx_chip *chip = ds->priv; 6130 int err, id; 6131 6132 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6133 return -EOPNOTSUPP; 6134 6135 id = dsa_lag_id(ds->dst, lag); 6136 6137 mv88e6xxx_reg_lock(chip); 6138 6139 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6140 if (err) 6141 goto err_unlock; 6142 6143 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6144 if (err) 6145 goto err_clear_trunk; 6146 6147 mv88e6xxx_reg_unlock(chip); 6148 return 0; 6149 6150 err_clear_trunk: 6151 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6152 err_unlock: 6153 mv88e6xxx_reg_unlock(chip); 6154 return err; 6155 } 6156 6157 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6158 struct net_device *lag) 6159 { 6160 struct mv88e6xxx_chip *chip = ds->priv; 6161 int err_sync, err_trunk; 6162 6163 mv88e6xxx_reg_lock(chip); 6164 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6165 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6166 mv88e6xxx_reg_unlock(chip); 6167 return err_sync ? : err_trunk; 6168 } 6169 6170 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6171 int port) 6172 { 6173 struct mv88e6xxx_chip *chip = ds->priv; 6174 int err; 6175 6176 mv88e6xxx_reg_lock(chip); 6177 err = mv88e6xxx_lag_sync_masks(ds); 6178 mv88e6xxx_reg_unlock(chip); 6179 return err; 6180 } 6181 6182 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6183 int port, struct net_device *lag, 6184 struct netdev_lag_upper_info *info) 6185 { 6186 struct mv88e6xxx_chip *chip = ds->priv; 6187 int err; 6188 6189 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6190 return -EOPNOTSUPP; 6191 6192 mv88e6xxx_reg_lock(chip); 6193 6194 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6195 if (err) 6196 goto unlock; 6197 6198 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6199 6200 unlock: 6201 mv88e6xxx_reg_unlock(chip); 6202 return err; 6203 } 6204 6205 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6206 int port, struct net_device *lag) 6207 { 6208 struct mv88e6xxx_chip *chip = ds->priv; 6209 int err_sync, err_pvt; 6210 6211 mv88e6xxx_reg_lock(chip); 6212 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6213 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6214 mv88e6xxx_reg_unlock(chip); 6215 return err_sync ? : err_pvt; 6216 } 6217 6218 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6219 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6220 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6221 .setup = mv88e6xxx_setup, 6222 .teardown = mv88e6xxx_teardown, 6223 .port_setup = mv88e6xxx_port_setup, 6224 .port_teardown = mv88e6xxx_port_teardown, 6225 .phylink_validate = mv88e6xxx_validate, 6226 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6227 .phylink_mac_config = mv88e6xxx_mac_config, 6228 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6229 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6230 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6231 .get_strings = mv88e6xxx_get_strings, 6232 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6233 .get_sset_count = mv88e6xxx_get_sset_count, 6234 .port_enable = mv88e6xxx_port_enable, 6235 .port_disable = mv88e6xxx_port_disable, 6236 .port_max_mtu = mv88e6xxx_get_max_mtu, 6237 .port_change_mtu = mv88e6xxx_change_mtu, 6238 .get_mac_eee = mv88e6xxx_get_mac_eee, 6239 .set_mac_eee = mv88e6xxx_set_mac_eee, 6240 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6241 .get_eeprom = mv88e6xxx_get_eeprom, 6242 .set_eeprom = mv88e6xxx_set_eeprom, 6243 .get_regs_len = mv88e6xxx_get_regs_len, 6244 .get_regs = mv88e6xxx_get_regs, 6245 .get_rxnfc = mv88e6xxx_get_rxnfc, 6246 .set_rxnfc = mv88e6xxx_set_rxnfc, 6247 .set_ageing_time = mv88e6xxx_set_ageing_time, 6248 .port_bridge_join = mv88e6xxx_port_bridge_join, 6249 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6250 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6251 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6252 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6253 .port_fast_age = mv88e6xxx_port_fast_age, 6254 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6255 .port_vlan_add = mv88e6xxx_port_vlan_add, 6256 .port_vlan_del = mv88e6xxx_port_vlan_del, 6257 .port_fdb_add = mv88e6xxx_port_fdb_add, 6258 .port_fdb_del = mv88e6xxx_port_fdb_del, 6259 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6260 .port_mdb_add = mv88e6xxx_port_mdb_add, 6261 .port_mdb_del = mv88e6xxx_port_mdb_del, 6262 .port_mirror_add = mv88e6xxx_port_mirror_add, 6263 .port_mirror_del = mv88e6xxx_port_mirror_del, 6264 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6265 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6266 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6267 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6268 .port_txtstamp = mv88e6xxx_port_txtstamp, 6269 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6270 .get_ts_info = mv88e6xxx_get_ts_info, 6271 .devlink_param_get = mv88e6xxx_devlink_param_get, 6272 .devlink_param_set = mv88e6xxx_devlink_param_set, 6273 .devlink_info_get = mv88e6xxx_devlink_info_get, 6274 .port_lag_change = mv88e6xxx_port_lag_change, 6275 .port_lag_join = mv88e6xxx_port_lag_join, 6276 .port_lag_leave = mv88e6xxx_port_lag_leave, 6277 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6278 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6279 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6280 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload, 6281 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload, 6282 }; 6283 6284 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6285 { 6286 struct device *dev = chip->dev; 6287 struct dsa_switch *ds; 6288 6289 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6290 if (!ds) 6291 return -ENOMEM; 6292 6293 ds->dev = dev; 6294 ds->num_ports = mv88e6xxx_num_ports(chip); 6295 ds->priv = chip; 6296 ds->dev = dev; 6297 ds->ops = &mv88e6xxx_switch_ops; 6298 ds->ageing_time_min = chip->info->age_time_coeff; 6299 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6300 6301 /* Some chips support up to 32, but that requires enabling the 6302 * 5-bit port mode, which we do not support. 640k^W16 ought to 6303 * be enough for anyone. 6304 */ 6305 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6306 6307 dev_set_drvdata(dev, ds); 6308 6309 return dsa_register_switch(ds); 6310 } 6311 6312 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6313 { 6314 dsa_unregister_switch(chip->ds); 6315 } 6316 6317 static const void *pdata_device_get_match_data(struct device *dev) 6318 { 6319 const struct of_device_id *matches = dev->driver->of_match_table; 6320 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6321 6322 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6323 matches++) { 6324 if (!strcmp(pdata->compatible, matches->compatible)) 6325 return matches->data; 6326 } 6327 return NULL; 6328 } 6329 6330 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6331 * would be lost after a power cycle so prevent it to be suspended. 6332 */ 6333 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6334 { 6335 return -EOPNOTSUPP; 6336 } 6337 6338 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6339 { 6340 return 0; 6341 } 6342 6343 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6344 6345 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6346 { 6347 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6348 const struct mv88e6xxx_info *compat_info = NULL; 6349 struct device *dev = &mdiodev->dev; 6350 struct device_node *np = dev->of_node; 6351 struct mv88e6xxx_chip *chip; 6352 int port; 6353 int err; 6354 6355 if (!np && !pdata) 6356 return -EINVAL; 6357 6358 if (np) 6359 compat_info = of_device_get_match_data(dev); 6360 6361 if (pdata) { 6362 compat_info = pdata_device_get_match_data(dev); 6363 6364 if (!pdata->netdev) 6365 return -EINVAL; 6366 6367 for (port = 0; port < DSA_MAX_PORTS; port++) { 6368 if (!(pdata->enabled_ports & (1 << port))) 6369 continue; 6370 if (strcmp(pdata->cd.port_names[port], "cpu")) 6371 continue; 6372 pdata->cd.netdev[port] = &pdata->netdev->dev; 6373 break; 6374 } 6375 } 6376 6377 if (!compat_info) 6378 return -EINVAL; 6379 6380 chip = mv88e6xxx_alloc_chip(dev); 6381 if (!chip) { 6382 err = -ENOMEM; 6383 goto out; 6384 } 6385 6386 chip->info = compat_info; 6387 6388 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6389 if (err) 6390 goto out; 6391 6392 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6393 if (IS_ERR(chip->reset)) { 6394 err = PTR_ERR(chip->reset); 6395 goto out; 6396 } 6397 if (chip->reset) 6398 usleep_range(1000, 2000); 6399 6400 err = mv88e6xxx_detect(chip); 6401 if (err) 6402 goto out; 6403 6404 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6405 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6406 else 6407 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6408 6409 mv88e6xxx_phy_init(chip); 6410 6411 if (chip->info->ops->get_eeprom) { 6412 if (np) 6413 of_property_read_u32(np, "eeprom-length", 6414 &chip->eeprom_len); 6415 else 6416 chip->eeprom_len = pdata->eeprom_len; 6417 } 6418 6419 mv88e6xxx_reg_lock(chip); 6420 err = mv88e6xxx_switch_reset(chip); 6421 mv88e6xxx_reg_unlock(chip); 6422 if (err) 6423 goto out; 6424 6425 if (np) { 6426 chip->irq = of_irq_get(np, 0); 6427 if (chip->irq == -EPROBE_DEFER) { 6428 err = chip->irq; 6429 goto out; 6430 } 6431 } 6432 6433 if (pdata) 6434 chip->irq = pdata->irq; 6435 6436 /* Has to be performed before the MDIO bus is created, because 6437 * the PHYs will link their interrupts to these interrupt 6438 * controllers 6439 */ 6440 mv88e6xxx_reg_lock(chip); 6441 if (chip->irq > 0) 6442 err = mv88e6xxx_g1_irq_setup(chip); 6443 else 6444 err = mv88e6xxx_irq_poll_setup(chip); 6445 mv88e6xxx_reg_unlock(chip); 6446 6447 if (err) 6448 goto out; 6449 6450 if (chip->info->g2_irqs > 0) { 6451 err = mv88e6xxx_g2_irq_setup(chip); 6452 if (err) 6453 goto out_g1_irq; 6454 } 6455 6456 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6457 if (err) 6458 goto out_g2_irq; 6459 6460 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6461 if (err) 6462 goto out_g1_atu_prob_irq; 6463 6464 err = mv88e6xxx_mdios_register(chip, np); 6465 if (err) 6466 goto out_g1_vtu_prob_irq; 6467 6468 err = mv88e6xxx_register_switch(chip); 6469 if (err) 6470 goto out_mdio; 6471 6472 return 0; 6473 6474 out_mdio: 6475 mv88e6xxx_mdios_unregister(chip); 6476 out_g1_vtu_prob_irq: 6477 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6478 out_g1_atu_prob_irq: 6479 mv88e6xxx_g1_atu_prob_irq_free(chip); 6480 out_g2_irq: 6481 if (chip->info->g2_irqs > 0) 6482 mv88e6xxx_g2_irq_free(chip); 6483 out_g1_irq: 6484 if (chip->irq > 0) 6485 mv88e6xxx_g1_irq_free(chip); 6486 else 6487 mv88e6xxx_irq_poll_free(chip); 6488 out: 6489 if (pdata) 6490 dev_put(pdata->netdev); 6491 6492 return err; 6493 } 6494 6495 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6496 { 6497 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6498 struct mv88e6xxx_chip *chip; 6499 6500 if (!ds) 6501 return; 6502 6503 chip = ds->priv; 6504 6505 if (chip->info->ptp_support) { 6506 mv88e6xxx_hwtstamp_free(chip); 6507 mv88e6xxx_ptp_free(chip); 6508 } 6509 6510 mv88e6xxx_phy_destroy(chip); 6511 mv88e6xxx_unregister_switch(chip); 6512 mv88e6xxx_mdios_unregister(chip); 6513 6514 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6515 mv88e6xxx_g1_atu_prob_irq_free(chip); 6516 6517 if (chip->info->g2_irqs > 0) 6518 mv88e6xxx_g2_irq_free(chip); 6519 6520 if (chip->irq > 0) 6521 mv88e6xxx_g1_irq_free(chip); 6522 else 6523 mv88e6xxx_irq_poll_free(chip); 6524 6525 dev_set_drvdata(&mdiodev->dev, NULL); 6526 } 6527 6528 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6529 { 6530 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6531 6532 if (!ds) 6533 return; 6534 6535 dsa_switch_shutdown(ds); 6536 6537 dev_set_drvdata(&mdiodev->dev, NULL); 6538 } 6539 6540 static const struct of_device_id mv88e6xxx_of_match[] = { 6541 { 6542 .compatible = "marvell,mv88e6085", 6543 .data = &mv88e6xxx_table[MV88E6085], 6544 }, 6545 { 6546 .compatible = "marvell,mv88e6190", 6547 .data = &mv88e6xxx_table[MV88E6190], 6548 }, 6549 { 6550 .compatible = "marvell,mv88e6250", 6551 .data = &mv88e6xxx_table[MV88E6250], 6552 }, 6553 { /* sentinel */ }, 6554 }; 6555 6556 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6557 6558 static struct mdio_driver mv88e6xxx_driver = { 6559 .probe = mv88e6xxx_probe, 6560 .remove = mv88e6xxx_remove, 6561 .shutdown = mv88e6xxx_shutdown, 6562 .mdiodrv.driver = { 6563 .name = "mv88e6085", 6564 .of_match_table = mv88e6xxx_of_match, 6565 .pm = &mv88e6xxx_pm_ops, 6566 }, 6567 }; 6568 6569 mdio_module_driver(mv88e6xxx_driver); 6570 6571 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6572 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6573 MODULE_LICENSE("GPL"); 6574