1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "devlink.h" 36 #include "global1.h" 37 #include "global2.h" 38 #include "hwtstamp.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "ptp.h" 42 #include "serdes.h" 43 #include "smi.h" 44 45 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 46 { 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 48 dev_err(chip->dev, "Switch registers lock not held!\n"); 49 dump_stack(); 50 } 51 } 52 53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 54 { 55 int err; 56 57 assert_reg_lock(chip); 58 59 err = mv88e6xxx_smi_read(chip, addr, reg, val); 60 if (err) 61 return err; 62 63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 64 addr, reg, *val); 65 66 return 0; 67 } 68 69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 70 { 71 int err; 72 73 assert_reg_lock(chip); 74 75 err = mv88e6xxx_smi_write(chip, addr, reg, val); 76 if (err) 77 return err; 78 79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 80 addr, reg, val); 81 82 return 0; 83 } 84 85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 86 u16 mask, u16 val) 87 { 88 u16 data; 89 int err; 90 int i; 91 92 /* There's no bus specific operation to wait for a mask */ 93 for (i = 0; i < 16; i++) { 94 err = mv88e6xxx_read(chip, addr, reg, &data); 95 if (err) 96 return err; 97 98 if ((data & mask) == val) 99 return 0; 100 101 usleep_range(1000, 2000); 102 } 103 104 dev_err(chip->dev, "Timeout while waiting for switch\n"); 105 return -ETIMEDOUT; 106 } 107 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 109 int bit, int val) 110 { 111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 112 val ? BIT(bit) : 0x0000); 113 } 114 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 116 { 117 struct mv88e6xxx_mdio_bus *mdio_bus; 118 119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 120 list); 121 if (!mdio_bus) 122 return NULL; 123 124 return mdio_bus->bus; 125 } 126 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 128 { 129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 130 unsigned int n = d->hwirq; 131 132 chip->g1_irq.masked |= (1 << n); 133 } 134 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked &= ~(1 << n); 141 } 142 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 144 { 145 unsigned int nhandled = 0; 146 unsigned int sub_irq; 147 unsigned int n; 148 u16 reg; 149 u16 ctl1; 150 int err; 151 152 mv88e6xxx_reg_lock(chip); 153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 154 mv88e6xxx_reg_unlock(chip); 155 156 if (err) 157 goto out; 158 159 do { 160 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 161 if (reg & (1 << n)) { 162 sub_irq = irq_find_mapping(chip->g1_irq.domain, 163 n); 164 handle_nested_irq(sub_irq); 165 ++nhandled; 166 } 167 } 168 169 mv88e6xxx_reg_lock(chip); 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 171 if (err) 172 goto unlock; 173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 174 unlock: 175 mv88e6xxx_reg_unlock(chip); 176 if (err) 177 goto out; 178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 179 } while (reg & ctl1); 180 181 out: 182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 183 } 184 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 186 { 187 struct mv88e6xxx_chip *chip = dev_id; 188 189 return mv88e6xxx_g1_irq_thread_work(chip); 190 } 191 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 193 { 194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 195 196 mv88e6xxx_reg_lock(chip); 197 } 198 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 200 { 201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 203 u16 reg; 204 int err; 205 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 207 if (err) 208 goto out; 209 210 reg &= ~mask; 211 reg |= (~chip->g1_irq.masked & mask); 212 213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 214 if (err) 215 goto out; 216 217 out: 218 mv88e6xxx_reg_unlock(chip); 219 } 220 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 222 .name = "mv88e6xxx-g1", 223 .irq_mask = mv88e6xxx_g1_irq_mask, 224 .irq_unmask = mv88e6xxx_g1_irq_unmask, 225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 227 }; 228 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 230 unsigned int irq, 231 irq_hw_number_t hwirq) 232 { 233 struct mv88e6xxx_chip *chip = d->host_data; 234 235 irq_set_chip_data(irq, d->host_data); 236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 237 irq_set_noprobe(irq); 238 239 return 0; 240 } 241 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 243 .map = mv88e6xxx_g1_irq_domain_map, 244 .xlate = irq_domain_xlate_twocell, 245 }; 246 247 /* To be called with reg_lock held */ 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 249 { 250 int irq, virq; 251 u16 mask; 252 253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 256 257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 258 virq = irq_find_mapping(chip->g1_irq.domain, irq); 259 irq_dispose_mapping(virq); 260 } 261 262 irq_domain_remove(chip->g1_irq.domain); 263 } 264 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 266 { 267 /* 268 * free_irq must be called without reg_lock taken because the irq 269 * handler takes this lock, too. 270 */ 271 free_irq(chip->irq, chip); 272 273 mv88e6xxx_reg_lock(chip); 274 mv88e6xxx_g1_irq_free_common(chip); 275 mv88e6xxx_reg_unlock(chip); 276 } 277 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 279 { 280 int err, irq, virq; 281 u16 reg, mask; 282 283 chip->g1_irq.nirqs = chip->info->g1_irqs; 284 chip->g1_irq.domain = irq_domain_add_simple( 285 NULL, chip->g1_irq.nirqs, 0, 286 &mv88e6xxx_g1_irq_domain_ops, chip); 287 if (!chip->g1_irq.domain) 288 return -ENOMEM; 289 290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 291 irq_create_mapping(chip->g1_irq.domain, irq); 292 293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 294 chip->g1_irq.masked = ~0; 295 296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 297 if (err) 298 goto out_mapping; 299 300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 303 if (err) 304 goto out_disable; 305 306 /* Reading the interrupt status clears (most of) them */ 307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 308 if (err) 309 goto out_disable; 310 311 return 0; 312 313 out_disable: 314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 316 317 out_mapping: 318 for (irq = 0; irq < 16; irq++) { 319 virq = irq_find_mapping(chip->g1_irq.domain, irq); 320 irq_dispose_mapping(virq); 321 } 322 323 irq_domain_remove(chip->g1_irq.domain); 324 325 return err; 326 } 327 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 329 { 330 static struct lock_class_key lock_key; 331 static struct lock_class_key request_key; 332 int err; 333 334 err = mv88e6xxx_g1_irq_setup_common(chip); 335 if (err) 336 return err; 337 338 /* These lock classes tells lockdep that global 1 irqs are in 339 * a different category than their parent GPIO, so it won't 340 * report false recursion. 341 */ 342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 343 344 snprintf(chip->irq_name, sizeof(chip->irq_name), 345 "mv88e6xxx-%s", dev_name(chip->dev)); 346 347 mv88e6xxx_reg_unlock(chip); 348 err = request_threaded_irq(chip->irq, NULL, 349 mv88e6xxx_g1_irq_thread_fn, 350 IRQF_ONESHOT | IRQF_SHARED, 351 chip->irq_name, chip); 352 mv88e6xxx_reg_lock(chip); 353 if (err) 354 mv88e6xxx_g1_irq_free_common(chip); 355 356 return err; 357 } 358 359 static void mv88e6xxx_irq_poll(struct kthread_work *work) 360 { 361 struct mv88e6xxx_chip *chip = container_of(work, 362 struct mv88e6xxx_chip, 363 irq_poll_work.work); 364 mv88e6xxx_g1_irq_thread_work(chip); 365 366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 367 msecs_to_jiffies(100)); 368 } 369 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 371 { 372 int err; 373 374 err = mv88e6xxx_g1_irq_setup_common(chip); 375 if (err) 376 return err; 377 378 kthread_init_delayed_work(&chip->irq_poll_work, 379 mv88e6xxx_irq_poll); 380 381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 382 if (IS_ERR(chip->kworker)) 383 return PTR_ERR(chip->kworker); 384 385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 386 msecs_to_jiffies(100)); 387 388 return 0; 389 } 390 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 392 { 393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 394 kthread_destroy_worker(chip->kworker); 395 396 mv88e6xxx_reg_lock(chip); 397 mv88e6xxx_g1_irq_free_common(chip); 398 mv88e6xxx_reg_unlock(chip); 399 } 400 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 402 int port, phy_interface_t interface) 403 { 404 int err; 405 406 if (chip->info->ops->port_set_rgmii_delay) { 407 err = chip->info->ops->port_set_rgmii_delay(chip, port, 408 interface); 409 if (err && err != -EOPNOTSUPP) 410 return err; 411 } 412 413 if (chip->info->ops->port_set_cmode) { 414 err = chip->info->ops->port_set_cmode(chip, port, 415 interface); 416 if (err && err != -EOPNOTSUPP) 417 return err; 418 } 419 420 return 0; 421 } 422 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 424 int link, int speed, int duplex, int pause, 425 phy_interface_t mode) 426 { 427 int err; 428 429 if (!chip->info->ops->port_set_link) 430 return 0; 431 432 /* Port's MAC control must not be changed unless the link is down */ 433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 434 if (err) 435 return err; 436 437 if (chip->info->ops->port_set_speed_duplex) { 438 err = chip->info->ops->port_set_speed_duplex(chip, port, 439 speed, duplex); 440 if (err && err != -EOPNOTSUPP) 441 goto restore_link; 442 } 443 444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 445 mode = chip->info->ops->port_max_speed_mode(port); 446 447 if (chip->info->ops->port_set_pause) { 448 err = chip->info->ops->port_set_pause(chip, port, pause); 449 if (err) 450 goto restore_link; 451 } 452 453 err = mv88e6xxx_port_config_interface(chip, port, mode); 454 restore_link: 455 if (chip->info->ops->port_set_link(chip, port, link)) 456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 457 458 return err; 459 } 460 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 462 { 463 struct mv88e6xxx_chip *chip = ds->priv; 464 465 return port < chip->info->num_internal_phys; 466 } 467 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 469 { 470 u16 reg; 471 int err; 472 473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 474 if (err) { 475 dev_err(chip->dev, 476 "p%d: %s: failed to read port status\n", 477 port, __func__); 478 return err; 479 } 480 481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 482 } 483 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 485 struct phylink_link_state *state) 486 { 487 struct mv88e6xxx_chip *chip = ds->priv; 488 u8 lane; 489 int err; 490 491 mv88e6xxx_reg_lock(chip); 492 lane = mv88e6xxx_serdes_get_lane(chip, port); 493 if (lane && chip->info->ops->serdes_pcs_get_state) 494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 495 state); 496 else 497 err = -EOPNOTSUPP; 498 mv88e6xxx_reg_unlock(chip); 499 500 return err; 501 } 502 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 504 unsigned int mode, 505 phy_interface_t interface, 506 const unsigned long *advertise) 507 { 508 const struct mv88e6xxx_ops *ops = chip->info->ops; 509 u8 lane; 510 511 if (ops->serdes_pcs_config) { 512 lane = mv88e6xxx_serdes_get_lane(chip, port); 513 if (lane) 514 return ops->serdes_pcs_config(chip, port, lane, mode, 515 interface, advertise); 516 } 517 518 return 0; 519 } 520 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 522 { 523 struct mv88e6xxx_chip *chip = ds->priv; 524 const struct mv88e6xxx_ops *ops; 525 int err = 0; 526 u8 lane; 527 528 ops = chip->info->ops; 529 530 if (ops->serdes_pcs_an_restart) { 531 mv88e6xxx_reg_lock(chip); 532 lane = mv88e6xxx_serdes_get_lane(chip, port); 533 if (lane) 534 err = ops->serdes_pcs_an_restart(chip, port, lane); 535 mv88e6xxx_reg_unlock(chip); 536 537 if (err) 538 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 539 } 540 } 541 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 543 unsigned int mode, 544 int speed, int duplex) 545 { 546 const struct mv88e6xxx_ops *ops = chip->info->ops; 547 u8 lane; 548 549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane) 552 return ops->serdes_pcs_link_up(chip, port, lane, 553 speed, duplex); 554 } 555 556 return 0; 557 } 558 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 560 unsigned long *mask, 561 struct phylink_link_state *state) 562 { 563 if (!phy_interface_mode_is_8023z(state->interface)) { 564 /* 10M and 100M are only supported in non-802.3z mode */ 565 phylink_set(mask, 10baseT_Half); 566 phylink_set(mask, 10baseT_Full); 567 phylink_set(mask, 100baseT_Half); 568 phylink_set(mask, 100baseT_Full); 569 } 570 } 571 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 573 unsigned long *mask, 574 struct phylink_link_state *state) 575 { 576 /* FIXME: if the port is in 1000Base-X mode, then it only supports 577 * 1000M FD speeds. In this case, CMODE will indicate 5. 578 */ 579 phylink_set(mask, 1000baseT_Full); 580 phylink_set(mask, 1000baseX_Full); 581 582 mv88e6065_phylink_validate(chip, port, mask, state); 583 } 584 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 586 unsigned long *mask, 587 struct phylink_link_state *state) 588 { 589 if (port >= 5) 590 phylink_set(mask, 2500baseX_Full); 591 592 /* No ethtool bits for 200Mbps */ 593 phylink_set(mask, 1000baseT_Full); 594 phylink_set(mask, 1000baseX_Full); 595 596 mv88e6065_phylink_validate(chip, port, mask, state); 597 } 598 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 600 unsigned long *mask, 601 struct phylink_link_state *state) 602 { 603 /* No ethtool bits for 200Mbps */ 604 phylink_set(mask, 1000baseT_Full); 605 phylink_set(mask, 1000baseX_Full); 606 607 mv88e6065_phylink_validate(chip, port, mask, state); 608 } 609 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 611 unsigned long *mask, 612 struct phylink_link_state *state) 613 { 614 if (port >= 9) { 615 phylink_set(mask, 2500baseX_Full); 616 phylink_set(mask, 2500baseT_Full); 617 } 618 619 /* No ethtool bits for 200Mbps */ 620 phylink_set(mask, 1000baseT_Full); 621 phylink_set(mask, 1000baseX_Full); 622 623 mv88e6065_phylink_validate(chip, port, mask, state); 624 } 625 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 627 unsigned long *mask, 628 struct phylink_link_state *state) 629 { 630 if (port >= 9) { 631 phylink_set(mask, 10000baseT_Full); 632 phylink_set(mask, 10000baseKR_Full); 633 } 634 635 mv88e6390_phylink_validate(chip, port, mask, state); 636 } 637 638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 639 unsigned long *supported, 640 struct phylink_link_state *state) 641 { 642 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 643 struct mv88e6xxx_chip *chip = ds->priv; 644 645 /* Allow all the expected bits */ 646 phylink_set(mask, Autoneg); 647 phylink_set(mask, Pause); 648 phylink_set_port_modes(mask); 649 650 if (chip->info->ops->phylink_validate) 651 chip->info->ops->phylink_validate(chip, port, mask, state); 652 653 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 654 bitmap_and(state->advertising, state->advertising, mask, 655 __ETHTOOL_LINK_MODE_MASK_NBITS); 656 657 /* We can only operate at 2500BaseX or 1000BaseX. If requested 658 * to advertise both, only report advertising at 2500BaseX. 659 */ 660 phylink_helper_basex_speed(state); 661 } 662 663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 664 unsigned int mode, 665 const struct phylink_link_state *state) 666 { 667 struct mv88e6xxx_chip *chip = ds->priv; 668 struct mv88e6xxx_port *p; 669 int err; 670 671 p = &chip->ports[port]; 672 673 /* FIXME: is this the correct test? If we're in fixed mode on an 674 * internal port, why should we process this any different from 675 * PHY mode? On the other hand, the port may be automedia between 676 * an internal PHY and the serdes... 677 */ 678 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 679 return; 680 681 mv88e6xxx_reg_lock(chip); 682 /* In inband mode, the link may come up at any time while the link 683 * is not forced down. Force the link down while we reconfigure the 684 * interface mode. 685 */ 686 if (mode == MLO_AN_INBAND && p->interface != state->interface && 687 chip->info->ops->port_set_link) 688 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 689 690 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 691 if (err && err != -EOPNOTSUPP) 692 goto err_unlock; 693 694 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 695 state->advertising); 696 /* FIXME: we should restart negotiation if something changed - which 697 * is something we get if we convert to using phylinks PCS operations. 698 */ 699 if (err > 0) 700 err = 0; 701 702 /* Undo the forced down state above after completing configuration 703 * irrespective of its state on entry, which allows the link to come up. 704 */ 705 if (mode == MLO_AN_INBAND && p->interface != state->interface && 706 chip->info->ops->port_set_link) 707 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 708 709 p->interface = state->interface; 710 711 err_unlock: 712 mv88e6xxx_reg_unlock(chip); 713 714 if (err && err != -EOPNOTSUPP) 715 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 716 } 717 718 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 719 unsigned int mode, 720 phy_interface_t interface) 721 { 722 struct mv88e6xxx_chip *chip = ds->priv; 723 const struct mv88e6xxx_ops *ops; 724 int err = 0; 725 726 ops = chip->info->ops; 727 728 mv88e6xxx_reg_lock(chip); 729 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 730 mode == MLO_AN_FIXED) && ops->port_sync_link) 731 err = ops->port_sync_link(chip, port, mode, false); 732 mv88e6xxx_reg_unlock(chip); 733 734 if (err) 735 dev_err(chip->dev, 736 "p%d: failed to force MAC link down\n", port); 737 } 738 739 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 740 unsigned int mode, phy_interface_t interface, 741 struct phy_device *phydev, 742 int speed, int duplex, 743 bool tx_pause, bool rx_pause) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 const struct mv88e6xxx_ops *ops; 747 int err = 0; 748 749 ops = chip->info->ops; 750 751 mv88e6xxx_reg_lock(chip); 752 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 753 /* FIXME: for an automedia port, should we force the link 754 * down here - what if the link comes up due to "other" media 755 * while we're bringing the port up, how is the exclusivity 756 * handled in the Marvell hardware? E.g. port 2 on 88E6390 757 * shared between internal PHY and Serdes. 758 */ 759 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 760 duplex); 761 if (err) 762 goto error; 763 764 if (ops->port_set_speed_duplex) { 765 err = ops->port_set_speed_duplex(chip, port, 766 speed, duplex); 767 if (err && err != -EOPNOTSUPP) 768 goto error; 769 } 770 771 if (ops->port_sync_link) 772 err = ops->port_sync_link(chip, port, mode, true); 773 } 774 error: 775 mv88e6xxx_reg_unlock(chip); 776 777 if (err && err != -EOPNOTSUPP) 778 dev_err(ds->dev, 779 "p%d: failed to configure MAC link up\n", port); 780 } 781 782 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 783 { 784 if (!chip->info->ops->stats_snapshot) 785 return -EOPNOTSUPP; 786 787 return chip->info->ops->stats_snapshot(chip, port); 788 } 789 790 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 791 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 792 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 793 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 794 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 795 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 796 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 797 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 798 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 799 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 800 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 801 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 802 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 803 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 804 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 805 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 806 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 807 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 808 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 809 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 810 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 811 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 812 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 813 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 814 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 815 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 816 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 817 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 818 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 819 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 820 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 821 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 822 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 823 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 824 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 825 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 826 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 827 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 828 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 829 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 830 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 831 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 832 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 833 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 834 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 835 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 836 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 837 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 838 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 839 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 840 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 841 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 842 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 843 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 844 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 845 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 846 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 847 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 848 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 849 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 850 }; 851 852 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 853 struct mv88e6xxx_hw_stat *s, 854 int port, u16 bank1_select, 855 u16 histogram) 856 { 857 u32 low; 858 u32 high = 0; 859 u16 reg = 0; 860 int err; 861 u64 value; 862 863 switch (s->type) { 864 case STATS_TYPE_PORT: 865 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 866 if (err) 867 return U64_MAX; 868 869 low = reg; 870 if (s->size == 4) { 871 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 872 if (err) 873 return U64_MAX; 874 low |= ((u32)reg) << 16; 875 } 876 break; 877 case STATS_TYPE_BANK1: 878 reg = bank1_select; 879 fallthrough; 880 case STATS_TYPE_BANK0: 881 reg |= s->reg | histogram; 882 mv88e6xxx_g1_stats_read(chip, reg, &low); 883 if (s->size == 8) 884 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 885 break; 886 default: 887 return U64_MAX; 888 } 889 value = (((u64)high) << 32) | low; 890 return value; 891 } 892 893 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 894 uint8_t *data, int types) 895 { 896 struct mv88e6xxx_hw_stat *stat; 897 int i, j; 898 899 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 900 stat = &mv88e6xxx_hw_stats[i]; 901 if (stat->type & types) { 902 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 903 ETH_GSTRING_LEN); 904 j++; 905 } 906 } 907 908 return j; 909 } 910 911 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 912 uint8_t *data) 913 { 914 return mv88e6xxx_stats_get_strings(chip, data, 915 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 916 } 917 918 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 919 uint8_t *data) 920 { 921 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 922 } 923 924 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 925 uint8_t *data) 926 { 927 return mv88e6xxx_stats_get_strings(chip, data, 928 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 929 } 930 931 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 932 "atu_member_violation", 933 "atu_miss_violation", 934 "atu_full_violation", 935 "vtu_member_violation", 936 "vtu_miss_violation", 937 }; 938 939 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 940 { 941 unsigned int i; 942 943 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 944 strlcpy(data + i * ETH_GSTRING_LEN, 945 mv88e6xxx_atu_vtu_stats_strings[i], 946 ETH_GSTRING_LEN); 947 } 948 949 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 950 u32 stringset, uint8_t *data) 951 { 952 struct mv88e6xxx_chip *chip = ds->priv; 953 int count = 0; 954 955 if (stringset != ETH_SS_STATS) 956 return; 957 958 mv88e6xxx_reg_lock(chip); 959 960 if (chip->info->ops->stats_get_strings) 961 count = chip->info->ops->stats_get_strings(chip, data); 962 963 if (chip->info->ops->serdes_get_strings) { 964 data += count * ETH_GSTRING_LEN; 965 count = chip->info->ops->serdes_get_strings(chip, port, data); 966 } 967 968 data += count * ETH_GSTRING_LEN; 969 mv88e6xxx_atu_vtu_get_strings(data); 970 971 mv88e6xxx_reg_unlock(chip); 972 } 973 974 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 975 int types) 976 { 977 struct mv88e6xxx_hw_stat *stat; 978 int i, j; 979 980 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 981 stat = &mv88e6xxx_hw_stats[i]; 982 if (stat->type & types) 983 j++; 984 } 985 return j; 986 } 987 988 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 989 { 990 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 991 STATS_TYPE_PORT); 992 } 993 994 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 995 { 996 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 997 } 998 999 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1000 { 1001 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1002 STATS_TYPE_BANK1); 1003 } 1004 1005 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1006 { 1007 struct mv88e6xxx_chip *chip = ds->priv; 1008 int serdes_count = 0; 1009 int count = 0; 1010 1011 if (sset != ETH_SS_STATS) 1012 return 0; 1013 1014 mv88e6xxx_reg_lock(chip); 1015 if (chip->info->ops->stats_get_sset_count) 1016 count = chip->info->ops->stats_get_sset_count(chip); 1017 if (count < 0) 1018 goto out; 1019 1020 if (chip->info->ops->serdes_get_sset_count) 1021 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1022 port); 1023 if (serdes_count < 0) { 1024 count = serdes_count; 1025 goto out; 1026 } 1027 count += serdes_count; 1028 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1029 1030 out: 1031 mv88e6xxx_reg_unlock(chip); 1032 1033 return count; 1034 } 1035 1036 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1037 uint64_t *data, int types, 1038 u16 bank1_select, u16 histogram) 1039 { 1040 struct mv88e6xxx_hw_stat *stat; 1041 int i, j; 1042 1043 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1044 stat = &mv88e6xxx_hw_stats[i]; 1045 if (stat->type & types) { 1046 mv88e6xxx_reg_lock(chip); 1047 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1048 bank1_select, 1049 histogram); 1050 mv88e6xxx_reg_unlock(chip); 1051 1052 j++; 1053 } 1054 } 1055 return j; 1056 } 1057 1058 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1059 uint64_t *data) 1060 { 1061 return mv88e6xxx_stats_get_stats(chip, port, data, 1062 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1063 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1064 } 1065 1066 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1067 uint64_t *data) 1068 { 1069 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1070 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1071 } 1072 1073 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1074 uint64_t *data) 1075 { 1076 return mv88e6xxx_stats_get_stats(chip, port, data, 1077 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1078 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1079 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1080 } 1081 1082 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1083 uint64_t *data) 1084 { 1085 return mv88e6xxx_stats_get_stats(chip, port, data, 1086 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1087 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1088 0); 1089 } 1090 1091 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1092 uint64_t *data) 1093 { 1094 *data++ = chip->ports[port].atu_member_violation; 1095 *data++ = chip->ports[port].atu_miss_violation; 1096 *data++ = chip->ports[port].atu_full_violation; 1097 *data++ = chip->ports[port].vtu_member_violation; 1098 *data++ = chip->ports[port].vtu_miss_violation; 1099 } 1100 1101 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1102 uint64_t *data) 1103 { 1104 int count = 0; 1105 1106 if (chip->info->ops->stats_get_stats) 1107 count = chip->info->ops->stats_get_stats(chip, port, data); 1108 1109 mv88e6xxx_reg_lock(chip); 1110 if (chip->info->ops->serdes_get_stats) { 1111 data += count; 1112 count = chip->info->ops->serdes_get_stats(chip, port, data); 1113 } 1114 data += count; 1115 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1116 mv88e6xxx_reg_unlock(chip); 1117 } 1118 1119 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1120 uint64_t *data) 1121 { 1122 struct mv88e6xxx_chip *chip = ds->priv; 1123 int ret; 1124 1125 mv88e6xxx_reg_lock(chip); 1126 1127 ret = mv88e6xxx_stats_snapshot(chip, port); 1128 mv88e6xxx_reg_unlock(chip); 1129 1130 if (ret < 0) 1131 return; 1132 1133 mv88e6xxx_get_stats(chip, port, data); 1134 1135 } 1136 1137 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1138 { 1139 struct mv88e6xxx_chip *chip = ds->priv; 1140 int len; 1141 1142 len = 32 * sizeof(u16); 1143 if (chip->info->ops->serdes_get_regs_len) 1144 len += chip->info->ops->serdes_get_regs_len(chip, port); 1145 1146 return len; 1147 } 1148 1149 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1150 struct ethtool_regs *regs, void *_p) 1151 { 1152 struct mv88e6xxx_chip *chip = ds->priv; 1153 int err; 1154 u16 reg; 1155 u16 *p = _p; 1156 int i; 1157 1158 regs->version = chip->info->prod_num; 1159 1160 memset(p, 0xff, 32 * sizeof(u16)); 1161 1162 mv88e6xxx_reg_lock(chip); 1163 1164 for (i = 0; i < 32; i++) { 1165 1166 err = mv88e6xxx_port_read(chip, port, i, ®); 1167 if (!err) 1168 p[i] = reg; 1169 } 1170 1171 if (chip->info->ops->serdes_get_regs) 1172 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1173 1174 mv88e6xxx_reg_unlock(chip); 1175 } 1176 1177 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1178 struct ethtool_eee *e) 1179 { 1180 /* Nothing to do on the port's MAC */ 1181 return 0; 1182 } 1183 1184 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1185 struct ethtool_eee *e) 1186 { 1187 /* Nothing to do on the port's MAC */ 1188 return 0; 1189 } 1190 1191 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1192 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1193 { 1194 struct dsa_switch *ds = chip->ds; 1195 struct dsa_switch_tree *dst = ds->dst; 1196 struct net_device *br; 1197 struct dsa_port *dp; 1198 bool found = false; 1199 u16 pvlan; 1200 1201 list_for_each_entry(dp, &dst->ports, list) { 1202 if (dp->ds->index == dev && dp->index == port) { 1203 found = true; 1204 break; 1205 } 1206 } 1207 1208 /* Prevent frames from unknown switch or port */ 1209 if (!found) 1210 return 0; 1211 1212 /* Frames from DSA links and CPU ports can egress any local port */ 1213 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1214 return mv88e6xxx_port_mask(chip); 1215 1216 br = dp->bridge_dev; 1217 pvlan = 0; 1218 1219 /* Frames from user ports can egress any local DSA links and CPU ports, 1220 * as well as any local member of their bridge group. 1221 */ 1222 list_for_each_entry(dp, &dst->ports, list) 1223 if (dp->ds == ds && 1224 (dp->type == DSA_PORT_TYPE_CPU || 1225 dp->type == DSA_PORT_TYPE_DSA || 1226 (br && dp->bridge_dev == br))) 1227 pvlan |= BIT(dp->index); 1228 1229 return pvlan; 1230 } 1231 1232 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1233 { 1234 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1235 1236 /* prevent frames from going back out of the port they came in on */ 1237 output_ports &= ~BIT(port); 1238 1239 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1240 } 1241 1242 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1243 u8 state) 1244 { 1245 struct mv88e6xxx_chip *chip = ds->priv; 1246 int err; 1247 1248 mv88e6xxx_reg_lock(chip); 1249 err = mv88e6xxx_port_set_state(chip, port, state); 1250 mv88e6xxx_reg_unlock(chip); 1251 1252 if (err) 1253 dev_err(ds->dev, "p%d: failed to update state\n", port); 1254 } 1255 1256 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1257 { 1258 int err; 1259 1260 if (chip->info->ops->ieee_pri_map) { 1261 err = chip->info->ops->ieee_pri_map(chip); 1262 if (err) 1263 return err; 1264 } 1265 1266 if (chip->info->ops->ip_pri_map) { 1267 err = chip->info->ops->ip_pri_map(chip); 1268 if (err) 1269 return err; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1276 { 1277 struct dsa_switch *ds = chip->ds; 1278 int target, port; 1279 int err; 1280 1281 if (!chip->info->global2_addr) 1282 return 0; 1283 1284 /* Initialize the routing port to the 32 possible target devices */ 1285 for (target = 0; target < 32; target++) { 1286 port = dsa_routing_port(ds, target); 1287 if (port == ds->num_ports) 1288 port = 0x1f; 1289 1290 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1291 if (err) 1292 return err; 1293 } 1294 1295 if (chip->info->ops->set_cascade_port) { 1296 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1297 err = chip->info->ops->set_cascade_port(chip, port); 1298 if (err) 1299 return err; 1300 } 1301 1302 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1303 if (err) 1304 return err; 1305 1306 return 0; 1307 } 1308 1309 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 /* Clear all trunk masks and mapping */ 1312 if (chip->info->global2_addr) 1313 return mv88e6xxx_g2_trunk_clear(chip); 1314 1315 return 0; 1316 } 1317 1318 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1319 { 1320 if (chip->info->ops->rmu_disable) 1321 return chip->info->ops->rmu_disable(chip); 1322 1323 return 0; 1324 } 1325 1326 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1327 { 1328 if (chip->info->ops->pot_clear) 1329 return chip->info->ops->pot_clear(chip); 1330 1331 return 0; 1332 } 1333 1334 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1335 { 1336 if (chip->info->ops->mgmt_rsvd2cpu) 1337 return chip->info->ops->mgmt_rsvd2cpu(chip); 1338 1339 return 0; 1340 } 1341 1342 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1343 { 1344 int err; 1345 1346 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1347 if (err) 1348 return err; 1349 1350 /* The chips that have a "learn2all" bit in Global1, ATU 1351 * Control are precisely those whose port registers have a 1352 * Message Port bit in Port Control 1 and hence implement 1353 * ->port_setup_message_port. 1354 */ 1355 if (chip->info->ops->port_setup_message_port) { 1356 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1357 if (err) 1358 return err; 1359 } 1360 1361 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1362 } 1363 1364 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1365 { 1366 int port; 1367 int err; 1368 1369 if (!chip->info->ops->irl_init_all) 1370 return 0; 1371 1372 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1373 /* Disable ingress rate limiting by resetting all per port 1374 * ingress rate limit resources to their initial state. 1375 */ 1376 err = chip->info->ops->irl_init_all(chip, port); 1377 if (err) 1378 return err; 1379 } 1380 1381 return 0; 1382 } 1383 1384 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1385 { 1386 if (chip->info->ops->set_switch_mac) { 1387 u8 addr[ETH_ALEN]; 1388 1389 eth_random_addr(addr); 1390 1391 return chip->info->ops->set_switch_mac(chip, addr); 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1398 { 1399 struct dsa_switch_tree *dst = chip->ds->dst; 1400 struct dsa_switch *ds; 1401 struct dsa_port *dp; 1402 u16 pvlan = 0; 1403 1404 if (!mv88e6xxx_has_pvt(chip)) 1405 return 0; 1406 1407 /* Skip the local source device, which uses in-chip port VLAN */ 1408 if (dev != chip->ds->index) { 1409 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1410 1411 ds = dsa_switch_find(dst->index, dev); 1412 dp = ds ? dsa_to_port(ds, port) : NULL; 1413 if (dp && dp->lag_dev) { 1414 /* As the PVT is used to limit flooding of 1415 * FORWARD frames, which use the LAG ID as the 1416 * source port, we must translate dev/port to 1417 * the special "LAG device" in the PVT, using 1418 * the LAG ID as the port number. 1419 */ 1420 dev = MV88E6XXX_G2_PVT_ADRR_DEV_TRUNK; 1421 port = dsa_lag_id(dst, dp->lag_dev); 1422 } 1423 } 1424 1425 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1426 } 1427 1428 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1429 { 1430 int dev, port; 1431 int err; 1432 1433 if (!mv88e6xxx_has_pvt(chip)) 1434 return 0; 1435 1436 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1437 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1438 */ 1439 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1440 if (err) 1441 return err; 1442 1443 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1444 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1445 err = mv88e6xxx_pvt_map(chip, dev, port); 1446 if (err) 1447 return err; 1448 } 1449 } 1450 1451 return 0; 1452 } 1453 1454 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1455 { 1456 struct mv88e6xxx_chip *chip = ds->priv; 1457 int err; 1458 1459 mv88e6xxx_reg_lock(chip); 1460 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1461 mv88e6xxx_reg_unlock(chip); 1462 1463 if (err) 1464 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1465 } 1466 1467 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1468 { 1469 if (!mv88e6xxx_max_vid(chip)) 1470 return 0; 1471 1472 return mv88e6xxx_g1_vtu_flush(chip); 1473 } 1474 1475 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1476 struct mv88e6xxx_vtu_entry *entry) 1477 { 1478 if (!chip->info->ops->vtu_getnext) 1479 return -EOPNOTSUPP; 1480 1481 return chip->info->ops->vtu_getnext(chip, entry); 1482 } 1483 1484 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1485 struct mv88e6xxx_vtu_entry *entry) 1486 { 1487 if (!chip->info->ops->vtu_loadpurge) 1488 return -EOPNOTSUPP; 1489 1490 return chip->info->ops->vtu_loadpurge(chip, entry); 1491 } 1492 1493 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1494 { 1495 struct mv88e6xxx_vtu_entry vlan; 1496 int i, err; 1497 u16 fid; 1498 1499 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1500 1501 /* Set every FID bit used by the (un)bridged ports */ 1502 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1503 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1504 if (err) 1505 return err; 1506 1507 set_bit(fid, fid_bitmap); 1508 } 1509 1510 /* Set every FID bit used by the VLAN entries */ 1511 vlan.vid = mv88e6xxx_max_vid(chip); 1512 vlan.valid = false; 1513 1514 do { 1515 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1516 if (err) 1517 return err; 1518 1519 if (!vlan.valid) 1520 break; 1521 1522 set_bit(vlan.fid, fid_bitmap); 1523 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 1524 1525 return 0; 1526 } 1527 1528 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1529 { 1530 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1531 int err; 1532 1533 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1534 if (err) 1535 return err; 1536 1537 /* The reset value 0x000 is used to indicate that multiple address 1538 * databases are not needed. Return the next positive available. 1539 */ 1540 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1541 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1542 return -ENOSPC; 1543 1544 /* Clear the database */ 1545 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1546 } 1547 1548 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1549 u16 vid) 1550 { 1551 struct mv88e6xxx_chip *chip = ds->priv; 1552 struct mv88e6xxx_vtu_entry vlan; 1553 int i, err; 1554 1555 if (!vid) 1556 return -EOPNOTSUPP; 1557 1558 /* DSA and CPU ports have to be members of multiple vlans */ 1559 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1560 return 0; 1561 1562 vlan.vid = vid - 1; 1563 vlan.valid = false; 1564 1565 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1566 if (err) 1567 return err; 1568 1569 if (!vlan.valid) 1570 return 0; 1571 1572 if (vlan.vid != vid) 1573 return 0; 1574 1575 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1576 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1577 continue; 1578 1579 if (!dsa_to_port(ds, i)->slave) 1580 continue; 1581 1582 if (vlan.member[i] == 1583 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1584 continue; 1585 1586 if (dsa_to_port(ds, i)->bridge_dev == 1587 dsa_to_port(ds, port)->bridge_dev) 1588 break; /* same bridge, check next VLAN */ 1589 1590 if (!dsa_to_port(ds, i)->bridge_dev) 1591 continue; 1592 1593 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1594 port, vlan.vid, i, 1595 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1596 return -EOPNOTSUPP; 1597 } 1598 1599 return 0; 1600 } 1601 1602 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1603 bool vlan_filtering) 1604 { 1605 struct mv88e6xxx_chip *chip = ds->priv; 1606 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1607 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1608 int err; 1609 1610 if (!mv88e6xxx_max_vid(chip)) 1611 return -EOPNOTSUPP; 1612 1613 mv88e6xxx_reg_lock(chip); 1614 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1615 mv88e6xxx_reg_unlock(chip); 1616 1617 return err; 1618 } 1619 1620 static int 1621 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1622 const struct switchdev_obj_port_vlan *vlan) 1623 { 1624 struct mv88e6xxx_chip *chip = ds->priv; 1625 int err; 1626 1627 if (!mv88e6xxx_max_vid(chip)) 1628 return -EOPNOTSUPP; 1629 1630 /* If the requested port doesn't belong to the same bridge as the VLAN 1631 * members, do not support it (yet) and fallback to software VLAN. 1632 */ 1633 mv88e6xxx_reg_lock(chip); 1634 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1635 mv88e6xxx_reg_unlock(chip); 1636 1637 return err; 1638 } 1639 1640 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1641 const unsigned char *addr, u16 vid, 1642 u8 state) 1643 { 1644 struct mv88e6xxx_atu_entry entry; 1645 struct mv88e6xxx_vtu_entry vlan; 1646 u16 fid; 1647 int err; 1648 1649 /* Null VLAN ID corresponds to the port private database */ 1650 if (vid == 0) { 1651 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1652 if (err) 1653 return err; 1654 } else { 1655 vlan.vid = vid - 1; 1656 vlan.valid = false; 1657 1658 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1659 if (err) 1660 return err; 1661 1662 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1663 if (vlan.vid != vid || !vlan.valid) 1664 return -EOPNOTSUPP; 1665 1666 fid = vlan.fid; 1667 } 1668 1669 entry.state = 0; 1670 ether_addr_copy(entry.mac, addr); 1671 eth_addr_dec(entry.mac); 1672 1673 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1674 if (err) 1675 return err; 1676 1677 /* Initialize a fresh ATU entry if it isn't found */ 1678 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1679 memset(&entry, 0, sizeof(entry)); 1680 ether_addr_copy(entry.mac, addr); 1681 } 1682 1683 /* Purge the ATU entry only if no port is using it anymore */ 1684 if (!state) { 1685 entry.portvec &= ~BIT(port); 1686 if (!entry.portvec) 1687 entry.state = 0; 1688 } else { 1689 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1690 entry.portvec = BIT(port); 1691 else 1692 entry.portvec |= BIT(port); 1693 1694 entry.state = state; 1695 } 1696 1697 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1698 } 1699 1700 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1701 const struct mv88e6xxx_policy *policy) 1702 { 1703 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1704 enum mv88e6xxx_policy_action action = policy->action; 1705 const u8 *addr = policy->addr; 1706 u16 vid = policy->vid; 1707 u8 state; 1708 int err; 1709 int id; 1710 1711 if (!chip->info->ops->port_set_policy) 1712 return -EOPNOTSUPP; 1713 1714 switch (mapping) { 1715 case MV88E6XXX_POLICY_MAPPING_DA: 1716 case MV88E6XXX_POLICY_MAPPING_SA: 1717 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1718 state = 0; /* Dissociate the port and address */ 1719 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1720 is_multicast_ether_addr(addr)) 1721 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1722 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1723 is_unicast_ether_addr(addr)) 1724 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1725 else 1726 return -EOPNOTSUPP; 1727 1728 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1729 state); 1730 if (err) 1731 return err; 1732 break; 1733 default: 1734 return -EOPNOTSUPP; 1735 } 1736 1737 /* Skip the port's policy clearing if the mapping is still in use */ 1738 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1739 idr_for_each_entry(&chip->policies, policy, id) 1740 if (policy->port == port && 1741 policy->mapping == mapping && 1742 policy->action != action) 1743 return 0; 1744 1745 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1746 } 1747 1748 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1749 struct ethtool_rx_flow_spec *fs) 1750 { 1751 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1752 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1753 enum mv88e6xxx_policy_mapping mapping; 1754 enum mv88e6xxx_policy_action action; 1755 struct mv88e6xxx_policy *policy; 1756 u16 vid = 0; 1757 u8 *addr; 1758 int err; 1759 int id; 1760 1761 if (fs->location != RX_CLS_LOC_ANY) 1762 return -EINVAL; 1763 1764 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1765 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1766 else 1767 return -EOPNOTSUPP; 1768 1769 switch (fs->flow_type & ~FLOW_EXT) { 1770 case ETHER_FLOW: 1771 if (!is_zero_ether_addr(mac_mask->h_dest) && 1772 is_zero_ether_addr(mac_mask->h_source)) { 1773 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1774 addr = mac_entry->h_dest; 1775 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1776 !is_zero_ether_addr(mac_mask->h_source)) { 1777 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1778 addr = mac_entry->h_source; 1779 } else { 1780 /* Cannot support DA and SA mapping in the same rule */ 1781 return -EOPNOTSUPP; 1782 } 1783 break; 1784 default: 1785 return -EOPNOTSUPP; 1786 } 1787 1788 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1789 if (fs->m_ext.vlan_tci != htons(0xffff)) 1790 return -EOPNOTSUPP; 1791 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1792 } 1793 1794 idr_for_each_entry(&chip->policies, policy, id) { 1795 if (policy->port == port && policy->mapping == mapping && 1796 policy->action == action && policy->vid == vid && 1797 ether_addr_equal(policy->addr, addr)) 1798 return -EEXIST; 1799 } 1800 1801 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1802 if (!policy) 1803 return -ENOMEM; 1804 1805 fs->location = 0; 1806 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1807 GFP_KERNEL); 1808 if (err) { 1809 devm_kfree(chip->dev, policy); 1810 return err; 1811 } 1812 1813 memcpy(&policy->fs, fs, sizeof(*fs)); 1814 ether_addr_copy(policy->addr, addr); 1815 policy->mapping = mapping; 1816 policy->action = action; 1817 policy->port = port; 1818 policy->vid = vid; 1819 1820 err = mv88e6xxx_policy_apply(chip, port, policy); 1821 if (err) { 1822 idr_remove(&chip->policies, fs->location); 1823 devm_kfree(chip->dev, policy); 1824 return err; 1825 } 1826 1827 return 0; 1828 } 1829 1830 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1831 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1832 { 1833 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1834 struct mv88e6xxx_chip *chip = ds->priv; 1835 struct mv88e6xxx_policy *policy; 1836 int err; 1837 int id; 1838 1839 mv88e6xxx_reg_lock(chip); 1840 1841 switch (rxnfc->cmd) { 1842 case ETHTOOL_GRXCLSRLCNT: 1843 rxnfc->data = 0; 1844 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1845 rxnfc->rule_cnt = 0; 1846 idr_for_each_entry(&chip->policies, policy, id) 1847 if (policy->port == port) 1848 rxnfc->rule_cnt++; 1849 err = 0; 1850 break; 1851 case ETHTOOL_GRXCLSRULE: 1852 err = -ENOENT; 1853 policy = idr_find(&chip->policies, fs->location); 1854 if (policy) { 1855 memcpy(fs, &policy->fs, sizeof(*fs)); 1856 err = 0; 1857 } 1858 break; 1859 case ETHTOOL_GRXCLSRLALL: 1860 rxnfc->data = 0; 1861 rxnfc->rule_cnt = 0; 1862 idr_for_each_entry(&chip->policies, policy, id) 1863 if (policy->port == port) 1864 rule_locs[rxnfc->rule_cnt++] = id; 1865 err = 0; 1866 break; 1867 default: 1868 err = -EOPNOTSUPP; 1869 break; 1870 } 1871 1872 mv88e6xxx_reg_unlock(chip); 1873 1874 return err; 1875 } 1876 1877 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1878 struct ethtool_rxnfc *rxnfc) 1879 { 1880 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1881 struct mv88e6xxx_chip *chip = ds->priv; 1882 struct mv88e6xxx_policy *policy; 1883 int err; 1884 1885 mv88e6xxx_reg_lock(chip); 1886 1887 switch (rxnfc->cmd) { 1888 case ETHTOOL_SRXCLSRLINS: 1889 err = mv88e6xxx_policy_insert(chip, port, fs); 1890 break; 1891 case ETHTOOL_SRXCLSRLDEL: 1892 err = -ENOENT; 1893 policy = idr_remove(&chip->policies, fs->location); 1894 if (policy) { 1895 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1896 err = mv88e6xxx_policy_apply(chip, port, policy); 1897 devm_kfree(chip->dev, policy); 1898 } 1899 break; 1900 default: 1901 err = -EOPNOTSUPP; 1902 break; 1903 } 1904 1905 mv88e6xxx_reg_unlock(chip); 1906 1907 return err; 1908 } 1909 1910 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1911 u16 vid) 1912 { 1913 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1914 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1915 1916 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1917 } 1918 1919 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1920 { 1921 int port; 1922 int err; 1923 1924 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1925 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1926 if (err) 1927 return err; 1928 } 1929 1930 return 0; 1931 } 1932 1933 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1934 u16 vid, u8 member, bool warn) 1935 { 1936 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1937 struct mv88e6xxx_vtu_entry vlan; 1938 int i, err; 1939 1940 vlan.vid = vid - 1; 1941 vlan.valid = false; 1942 1943 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1944 if (err) 1945 return err; 1946 1947 if (vlan.vid != vid || !vlan.valid) { 1948 memset(&vlan, 0, sizeof(vlan)); 1949 1950 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1951 if (err) 1952 return err; 1953 1954 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1955 if (i == port) 1956 vlan.member[i] = member; 1957 else 1958 vlan.member[i] = non_member; 1959 1960 vlan.vid = vid; 1961 vlan.valid = true; 1962 1963 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1964 if (err) 1965 return err; 1966 1967 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1968 if (err) 1969 return err; 1970 } else if (vlan.member[port] != member) { 1971 vlan.member[port] = member; 1972 1973 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1974 if (err) 1975 return err; 1976 } else if (warn) { 1977 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1978 port, vid); 1979 } 1980 1981 return 0; 1982 } 1983 1984 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1985 const struct switchdev_obj_port_vlan *vlan) 1986 { 1987 struct mv88e6xxx_chip *chip = ds->priv; 1988 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1989 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1990 bool warn; 1991 u8 member; 1992 int err; 1993 1994 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 1995 if (err) 1996 return err; 1997 1998 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1999 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2000 else if (untagged) 2001 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2002 else 2003 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2004 2005 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2006 * and then the CPU port. Do not warn for duplicates for the CPU port. 2007 */ 2008 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2009 2010 mv88e6xxx_reg_lock(chip); 2011 2012 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2013 if (err) { 2014 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2015 vlan->vid, untagged ? 'u' : 't'); 2016 goto out; 2017 } 2018 2019 if (pvid) { 2020 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid); 2021 if (err) { 2022 dev_err(ds->dev, "p%d: failed to set PVID %d\n", 2023 port, vlan->vid); 2024 goto out; 2025 } 2026 } 2027 out: 2028 mv88e6xxx_reg_unlock(chip); 2029 2030 return err; 2031 } 2032 2033 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2034 int port, u16 vid) 2035 { 2036 struct mv88e6xxx_vtu_entry vlan; 2037 int i, err; 2038 2039 if (!vid) 2040 return -EOPNOTSUPP; 2041 2042 vlan.vid = vid - 1; 2043 vlan.valid = false; 2044 2045 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2046 if (err) 2047 return err; 2048 2049 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2050 * tell switchdev that this VLAN is likely handled in software. 2051 */ 2052 if (vlan.vid != vid || !vlan.valid || 2053 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2054 return -EOPNOTSUPP; 2055 2056 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2057 2058 /* keep the VLAN unless all ports are excluded */ 2059 vlan.valid = false; 2060 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2061 if (vlan.member[i] != 2062 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2063 vlan.valid = true; 2064 break; 2065 } 2066 } 2067 2068 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2069 if (err) 2070 return err; 2071 2072 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2073 } 2074 2075 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2076 const struct switchdev_obj_port_vlan *vlan) 2077 { 2078 struct mv88e6xxx_chip *chip = ds->priv; 2079 int err = 0; 2080 u16 pvid; 2081 2082 if (!mv88e6xxx_max_vid(chip)) 2083 return -EOPNOTSUPP; 2084 2085 mv88e6xxx_reg_lock(chip); 2086 2087 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2088 if (err) 2089 goto unlock; 2090 2091 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2092 if (err) 2093 goto unlock; 2094 2095 if (vlan->vid == pvid) { 2096 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2097 if (err) 2098 goto unlock; 2099 } 2100 2101 unlock: 2102 mv88e6xxx_reg_unlock(chip); 2103 2104 return err; 2105 } 2106 2107 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2108 const unsigned char *addr, u16 vid) 2109 { 2110 struct mv88e6xxx_chip *chip = ds->priv; 2111 int err; 2112 2113 mv88e6xxx_reg_lock(chip); 2114 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2115 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2116 mv88e6xxx_reg_unlock(chip); 2117 2118 return err; 2119 } 2120 2121 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2122 const unsigned char *addr, u16 vid) 2123 { 2124 struct mv88e6xxx_chip *chip = ds->priv; 2125 int err; 2126 2127 mv88e6xxx_reg_lock(chip); 2128 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2129 mv88e6xxx_reg_unlock(chip); 2130 2131 return err; 2132 } 2133 2134 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2135 u16 fid, u16 vid, int port, 2136 dsa_fdb_dump_cb_t *cb, void *data) 2137 { 2138 struct mv88e6xxx_atu_entry addr; 2139 bool is_static; 2140 int err; 2141 2142 addr.state = 0; 2143 eth_broadcast_addr(addr.mac); 2144 2145 do { 2146 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2147 if (err) 2148 return err; 2149 2150 if (!addr.state) 2151 break; 2152 2153 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2154 continue; 2155 2156 if (!is_unicast_ether_addr(addr.mac)) 2157 continue; 2158 2159 is_static = (addr.state == 2160 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2161 err = cb(addr.mac, vid, is_static, data); 2162 if (err) 2163 return err; 2164 } while (!is_broadcast_ether_addr(addr.mac)); 2165 2166 return err; 2167 } 2168 2169 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2170 dsa_fdb_dump_cb_t *cb, void *data) 2171 { 2172 struct mv88e6xxx_vtu_entry vlan; 2173 u16 fid; 2174 int err; 2175 2176 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2177 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2178 if (err) 2179 return err; 2180 2181 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2182 if (err) 2183 return err; 2184 2185 /* Dump VLANs' Filtering Information Databases */ 2186 vlan.vid = mv88e6xxx_max_vid(chip); 2187 vlan.valid = false; 2188 2189 do { 2190 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2191 if (err) 2192 return err; 2193 2194 if (!vlan.valid) 2195 break; 2196 2197 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2198 cb, data); 2199 if (err) 2200 return err; 2201 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 2202 2203 return err; 2204 } 2205 2206 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2207 dsa_fdb_dump_cb_t *cb, void *data) 2208 { 2209 struct mv88e6xxx_chip *chip = ds->priv; 2210 int err; 2211 2212 mv88e6xxx_reg_lock(chip); 2213 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2214 mv88e6xxx_reg_unlock(chip); 2215 2216 return err; 2217 } 2218 2219 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2220 struct net_device *br) 2221 { 2222 struct dsa_switch *ds = chip->ds; 2223 struct dsa_switch_tree *dst = ds->dst; 2224 struct dsa_port *dp; 2225 int err; 2226 2227 list_for_each_entry(dp, &dst->ports, list) { 2228 if (dp->bridge_dev == br) { 2229 if (dp->ds == ds) { 2230 /* This is a local bridge group member, 2231 * remap its Port VLAN Map. 2232 */ 2233 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2234 if (err) 2235 return err; 2236 } else { 2237 /* This is an external bridge group member, 2238 * remap its cross-chip Port VLAN Table entry. 2239 */ 2240 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2241 dp->index); 2242 if (err) 2243 return err; 2244 } 2245 } 2246 } 2247 2248 return 0; 2249 } 2250 2251 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2252 struct net_device *br) 2253 { 2254 struct mv88e6xxx_chip *chip = ds->priv; 2255 int err; 2256 2257 mv88e6xxx_reg_lock(chip); 2258 err = mv88e6xxx_bridge_map(chip, br); 2259 mv88e6xxx_reg_unlock(chip); 2260 2261 return err; 2262 } 2263 2264 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2265 struct net_device *br) 2266 { 2267 struct mv88e6xxx_chip *chip = ds->priv; 2268 2269 mv88e6xxx_reg_lock(chip); 2270 if (mv88e6xxx_bridge_map(chip, br) || 2271 mv88e6xxx_port_vlan_map(chip, port)) 2272 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2273 mv88e6xxx_reg_unlock(chip); 2274 } 2275 2276 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2277 int tree_index, int sw_index, 2278 int port, struct net_device *br) 2279 { 2280 struct mv88e6xxx_chip *chip = ds->priv; 2281 int err; 2282 2283 if (tree_index != ds->dst->index) 2284 return 0; 2285 2286 mv88e6xxx_reg_lock(chip); 2287 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2288 mv88e6xxx_reg_unlock(chip); 2289 2290 return err; 2291 } 2292 2293 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2294 int tree_index, int sw_index, 2295 int port, struct net_device *br) 2296 { 2297 struct mv88e6xxx_chip *chip = ds->priv; 2298 2299 if (tree_index != ds->dst->index) 2300 return; 2301 2302 mv88e6xxx_reg_lock(chip); 2303 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2304 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2305 mv88e6xxx_reg_unlock(chip); 2306 } 2307 2308 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2309 { 2310 if (chip->info->ops->reset) 2311 return chip->info->ops->reset(chip); 2312 2313 return 0; 2314 } 2315 2316 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2317 { 2318 struct gpio_desc *gpiod = chip->reset; 2319 2320 /* If there is a GPIO connected to the reset pin, toggle it */ 2321 if (gpiod) { 2322 gpiod_set_value_cansleep(gpiod, 1); 2323 usleep_range(10000, 20000); 2324 gpiod_set_value_cansleep(gpiod, 0); 2325 usleep_range(10000, 20000); 2326 2327 mv88e6xxx_g1_wait_eeprom_done(chip); 2328 } 2329 } 2330 2331 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2332 { 2333 int i, err; 2334 2335 /* Set all ports to the Disabled state */ 2336 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2337 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2338 if (err) 2339 return err; 2340 } 2341 2342 /* Wait for transmit queues to drain, 2343 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2344 */ 2345 usleep_range(2000, 4000); 2346 2347 return 0; 2348 } 2349 2350 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2351 { 2352 int err; 2353 2354 err = mv88e6xxx_disable_ports(chip); 2355 if (err) 2356 return err; 2357 2358 mv88e6xxx_hardware_reset(chip); 2359 2360 return mv88e6xxx_software_reset(chip); 2361 } 2362 2363 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2364 enum mv88e6xxx_frame_mode frame, 2365 enum mv88e6xxx_egress_mode egress, u16 etype) 2366 { 2367 int err; 2368 2369 if (!chip->info->ops->port_set_frame_mode) 2370 return -EOPNOTSUPP; 2371 2372 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2373 if (err) 2374 return err; 2375 2376 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2377 if (err) 2378 return err; 2379 2380 if (chip->info->ops->port_set_ether_type) 2381 return chip->info->ops->port_set_ether_type(chip, port, etype); 2382 2383 return 0; 2384 } 2385 2386 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2387 { 2388 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2389 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2390 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2391 } 2392 2393 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2394 { 2395 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2396 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2397 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2398 } 2399 2400 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2401 { 2402 return mv88e6xxx_set_port_mode(chip, port, 2403 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2404 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2405 ETH_P_EDSA); 2406 } 2407 2408 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2409 { 2410 if (dsa_is_dsa_port(chip->ds, port)) 2411 return mv88e6xxx_set_port_mode_dsa(chip, port); 2412 2413 if (dsa_is_user_port(chip->ds, port)) 2414 return mv88e6xxx_set_port_mode_normal(chip, port); 2415 2416 /* Setup CPU port mode depending on its supported tag format */ 2417 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2418 return mv88e6xxx_set_port_mode_dsa(chip, port); 2419 2420 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2421 return mv88e6xxx_set_port_mode_edsa(chip, port); 2422 2423 return -EINVAL; 2424 } 2425 2426 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2427 { 2428 bool message = dsa_is_dsa_port(chip->ds, port); 2429 2430 return mv88e6xxx_port_set_message_port(chip, port, message); 2431 } 2432 2433 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2434 { 2435 struct dsa_switch *ds = chip->ds; 2436 bool flood; 2437 2438 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2439 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2440 if (chip->info->ops->port_set_egress_floods) 2441 return chip->info->ops->port_set_egress_floods(chip, port, 2442 flood, flood); 2443 2444 return 0; 2445 } 2446 2447 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2448 { 2449 struct mv88e6xxx_port *mvp = dev_id; 2450 struct mv88e6xxx_chip *chip = mvp->chip; 2451 irqreturn_t ret = IRQ_NONE; 2452 int port = mvp->port; 2453 u8 lane; 2454 2455 mv88e6xxx_reg_lock(chip); 2456 lane = mv88e6xxx_serdes_get_lane(chip, port); 2457 if (lane) 2458 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2459 mv88e6xxx_reg_unlock(chip); 2460 2461 return ret; 2462 } 2463 2464 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2465 u8 lane) 2466 { 2467 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2468 unsigned int irq; 2469 int err; 2470 2471 /* Nothing to request if this SERDES port has no IRQ */ 2472 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2473 if (!irq) 2474 return 0; 2475 2476 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2477 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2478 2479 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2480 mv88e6xxx_reg_unlock(chip); 2481 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2482 IRQF_ONESHOT, dev_id->serdes_irq_name, 2483 dev_id); 2484 mv88e6xxx_reg_lock(chip); 2485 if (err) 2486 return err; 2487 2488 dev_id->serdes_irq = irq; 2489 2490 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2491 } 2492 2493 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2494 u8 lane) 2495 { 2496 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2497 unsigned int irq = dev_id->serdes_irq; 2498 int err; 2499 2500 /* Nothing to free if no IRQ has been requested */ 2501 if (!irq) 2502 return 0; 2503 2504 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2505 2506 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2507 mv88e6xxx_reg_unlock(chip); 2508 free_irq(irq, dev_id); 2509 mv88e6xxx_reg_lock(chip); 2510 2511 dev_id->serdes_irq = 0; 2512 2513 return err; 2514 } 2515 2516 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2517 bool on) 2518 { 2519 u8 lane; 2520 int err; 2521 2522 lane = mv88e6xxx_serdes_get_lane(chip, port); 2523 if (!lane) 2524 return 0; 2525 2526 if (on) { 2527 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2528 if (err) 2529 return err; 2530 2531 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2532 } else { 2533 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2534 if (err) 2535 return err; 2536 2537 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2538 } 2539 2540 return err; 2541 } 2542 2543 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2544 { 2545 struct dsa_switch *ds = chip->ds; 2546 int upstream_port; 2547 int err; 2548 2549 upstream_port = dsa_upstream_port(ds, port); 2550 if (chip->info->ops->port_set_upstream_port) { 2551 err = chip->info->ops->port_set_upstream_port(chip, port, 2552 upstream_port); 2553 if (err) 2554 return err; 2555 } 2556 2557 if (port == upstream_port) { 2558 if (chip->info->ops->set_cpu_port) { 2559 err = chip->info->ops->set_cpu_port(chip, 2560 upstream_port); 2561 if (err) 2562 return err; 2563 } 2564 2565 if (chip->info->ops->set_egress_port) { 2566 err = chip->info->ops->set_egress_port(chip, 2567 MV88E6XXX_EGRESS_DIR_INGRESS, 2568 upstream_port); 2569 if (err) 2570 return err; 2571 2572 err = chip->info->ops->set_egress_port(chip, 2573 MV88E6XXX_EGRESS_DIR_EGRESS, 2574 upstream_port); 2575 if (err) 2576 return err; 2577 } 2578 } 2579 2580 return 0; 2581 } 2582 2583 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2584 { 2585 struct dsa_switch *ds = chip->ds; 2586 int err; 2587 u16 reg; 2588 2589 chip->ports[port].chip = chip; 2590 chip->ports[port].port = port; 2591 2592 /* MAC Forcing register: don't force link, speed, duplex or flow control 2593 * state to any particular values on physical ports, but force the CPU 2594 * port and all DSA ports to their maximum bandwidth and full duplex. 2595 */ 2596 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2597 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2598 SPEED_MAX, DUPLEX_FULL, 2599 PAUSE_OFF, 2600 PHY_INTERFACE_MODE_NA); 2601 else 2602 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2603 SPEED_UNFORCED, DUPLEX_UNFORCED, 2604 PAUSE_ON, 2605 PHY_INTERFACE_MODE_NA); 2606 if (err) 2607 return err; 2608 2609 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2610 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2611 * tunneling, determine priority by looking at 802.1p and IP 2612 * priority fields (IP prio has precedence), and set STP state 2613 * to Forwarding. 2614 * 2615 * If this is the CPU link, use DSA or EDSA tagging depending 2616 * on which tagging mode was configured. 2617 * 2618 * If this is a link to another switch, use DSA tagging mode. 2619 * 2620 * If this is the upstream port for this switch, enable 2621 * forwarding of unknown unicasts and multicasts. 2622 */ 2623 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2624 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2625 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2626 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2627 if (err) 2628 return err; 2629 2630 err = mv88e6xxx_setup_port_mode(chip, port); 2631 if (err) 2632 return err; 2633 2634 err = mv88e6xxx_setup_egress_floods(chip, port); 2635 if (err) 2636 return err; 2637 2638 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2639 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2640 * untagged frames on this port, do a destination address lookup on all 2641 * received packets as usual, disable ARP mirroring and don't send a 2642 * copy of all transmitted/received frames on this port to the CPU. 2643 */ 2644 err = mv88e6xxx_port_set_map_da(chip, port); 2645 if (err) 2646 return err; 2647 2648 err = mv88e6xxx_setup_upstream_port(chip, port); 2649 if (err) 2650 return err; 2651 2652 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2653 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2654 if (err) 2655 return err; 2656 2657 if (chip->info->ops->port_set_jumbo_size) { 2658 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2659 if (err) 2660 return err; 2661 } 2662 2663 /* Port Association Vector: when learning source addresses 2664 * of packets, add the address to the address database using 2665 * a port bitmap that has only the bit for this port set and 2666 * the other bits clear. 2667 */ 2668 reg = 1 << port; 2669 /* Disable learning for CPU port */ 2670 if (dsa_is_cpu_port(ds, port)) 2671 reg = 0; 2672 2673 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2674 reg); 2675 if (err) 2676 return err; 2677 2678 /* Egress rate control 2: disable egress rate control. */ 2679 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2680 0x0000); 2681 if (err) 2682 return err; 2683 2684 if (chip->info->ops->port_pause_limit) { 2685 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2686 if (err) 2687 return err; 2688 } 2689 2690 if (chip->info->ops->port_disable_learn_limit) { 2691 err = chip->info->ops->port_disable_learn_limit(chip, port); 2692 if (err) 2693 return err; 2694 } 2695 2696 if (chip->info->ops->port_disable_pri_override) { 2697 err = chip->info->ops->port_disable_pri_override(chip, port); 2698 if (err) 2699 return err; 2700 } 2701 2702 if (chip->info->ops->port_tag_remap) { 2703 err = chip->info->ops->port_tag_remap(chip, port); 2704 if (err) 2705 return err; 2706 } 2707 2708 if (chip->info->ops->port_egress_rate_limiting) { 2709 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2710 if (err) 2711 return err; 2712 } 2713 2714 if (chip->info->ops->port_setup_message_port) { 2715 err = chip->info->ops->port_setup_message_port(chip, port); 2716 if (err) 2717 return err; 2718 } 2719 2720 /* Port based VLAN map: give each port the same default address 2721 * database, and allow bidirectional communication between the 2722 * CPU and DSA port(s), and the other ports. 2723 */ 2724 err = mv88e6xxx_port_set_fid(chip, port, 0); 2725 if (err) 2726 return err; 2727 2728 err = mv88e6xxx_port_vlan_map(chip, port); 2729 if (err) 2730 return err; 2731 2732 /* Default VLAN ID and priority: don't set a default VLAN 2733 * ID, and set the default packet priority to zero. 2734 */ 2735 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2736 } 2737 2738 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2739 { 2740 struct mv88e6xxx_chip *chip = ds->priv; 2741 2742 if (chip->info->ops->port_set_jumbo_size) 2743 return 10240; 2744 else if (chip->info->ops->set_max_frame_size) 2745 return 1632; 2746 return 1522; 2747 } 2748 2749 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2750 { 2751 struct mv88e6xxx_chip *chip = ds->priv; 2752 int ret = 0; 2753 2754 mv88e6xxx_reg_lock(chip); 2755 if (chip->info->ops->port_set_jumbo_size) 2756 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2757 else if (chip->info->ops->set_max_frame_size) 2758 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 2759 else 2760 if (new_mtu > 1522) 2761 ret = -EINVAL; 2762 mv88e6xxx_reg_unlock(chip); 2763 2764 return ret; 2765 } 2766 2767 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2768 struct phy_device *phydev) 2769 { 2770 struct mv88e6xxx_chip *chip = ds->priv; 2771 int err; 2772 2773 mv88e6xxx_reg_lock(chip); 2774 err = mv88e6xxx_serdes_power(chip, port, true); 2775 mv88e6xxx_reg_unlock(chip); 2776 2777 return err; 2778 } 2779 2780 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2781 { 2782 struct mv88e6xxx_chip *chip = ds->priv; 2783 2784 mv88e6xxx_reg_lock(chip); 2785 if (mv88e6xxx_serdes_power(chip, port, false)) 2786 dev_err(chip->dev, "failed to power off SERDES\n"); 2787 mv88e6xxx_reg_unlock(chip); 2788 } 2789 2790 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2791 unsigned int ageing_time) 2792 { 2793 struct mv88e6xxx_chip *chip = ds->priv; 2794 int err; 2795 2796 mv88e6xxx_reg_lock(chip); 2797 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2798 mv88e6xxx_reg_unlock(chip); 2799 2800 return err; 2801 } 2802 2803 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2804 { 2805 int err; 2806 2807 /* Initialize the statistics unit */ 2808 if (chip->info->ops->stats_set_histogram) { 2809 err = chip->info->ops->stats_set_histogram(chip); 2810 if (err) 2811 return err; 2812 } 2813 2814 return mv88e6xxx_g1_stats_clear(chip); 2815 } 2816 2817 /* Check if the errata has already been applied. */ 2818 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2819 { 2820 int port; 2821 int err; 2822 u16 val; 2823 2824 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2825 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2826 if (err) { 2827 dev_err(chip->dev, 2828 "Error reading hidden register: %d\n", err); 2829 return false; 2830 } 2831 if (val != 0x01c0) 2832 return false; 2833 } 2834 2835 return true; 2836 } 2837 2838 /* The 6390 copper ports have an errata which require poking magic 2839 * values into undocumented hidden registers and then performing a 2840 * software reset. 2841 */ 2842 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2843 { 2844 int port; 2845 int err; 2846 2847 if (mv88e6390_setup_errata_applied(chip)) 2848 return 0; 2849 2850 /* Set the ports into blocking mode */ 2851 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2852 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2853 if (err) 2854 return err; 2855 } 2856 2857 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2858 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2859 if (err) 2860 return err; 2861 } 2862 2863 return mv88e6xxx_software_reset(chip); 2864 } 2865 2866 static void mv88e6xxx_teardown(struct dsa_switch *ds) 2867 { 2868 mv88e6xxx_teardown_devlink_params(ds); 2869 dsa_devlink_resources_unregister(ds); 2870 mv88e6xxx_teardown_devlink_regions(ds); 2871 } 2872 2873 static int mv88e6xxx_setup(struct dsa_switch *ds) 2874 { 2875 struct mv88e6xxx_chip *chip = ds->priv; 2876 u8 cmode; 2877 int err; 2878 int i; 2879 2880 chip->ds = ds; 2881 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2882 2883 mv88e6xxx_reg_lock(chip); 2884 2885 if (chip->info->ops->setup_errata) { 2886 err = chip->info->ops->setup_errata(chip); 2887 if (err) 2888 goto unlock; 2889 } 2890 2891 /* Cache the cmode of each port. */ 2892 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2893 if (chip->info->ops->port_get_cmode) { 2894 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2895 if (err) 2896 goto unlock; 2897 2898 chip->ports[i].cmode = cmode; 2899 } 2900 } 2901 2902 /* Setup Switch Port Registers */ 2903 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2904 if (dsa_is_unused_port(ds, i)) 2905 continue; 2906 2907 /* Prevent the use of an invalid port. */ 2908 if (mv88e6xxx_is_invalid_port(chip, i)) { 2909 dev_err(chip->dev, "port %d is invalid\n", i); 2910 err = -EINVAL; 2911 goto unlock; 2912 } 2913 2914 err = mv88e6xxx_setup_port(chip, i); 2915 if (err) 2916 goto unlock; 2917 } 2918 2919 err = mv88e6xxx_irl_setup(chip); 2920 if (err) 2921 goto unlock; 2922 2923 err = mv88e6xxx_mac_setup(chip); 2924 if (err) 2925 goto unlock; 2926 2927 err = mv88e6xxx_phy_setup(chip); 2928 if (err) 2929 goto unlock; 2930 2931 err = mv88e6xxx_vtu_setup(chip); 2932 if (err) 2933 goto unlock; 2934 2935 err = mv88e6xxx_pvt_setup(chip); 2936 if (err) 2937 goto unlock; 2938 2939 err = mv88e6xxx_atu_setup(chip); 2940 if (err) 2941 goto unlock; 2942 2943 err = mv88e6xxx_broadcast_setup(chip, 0); 2944 if (err) 2945 goto unlock; 2946 2947 err = mv88e6xxx_pot_setup(chip); 2948 if (err) 2949 goto unlock; 2950 2951 err = mv88e6xxx_rmu_setup(chip); 2952 if (err) 2953 goto unlock; 2954 2955 err = mv88e6xxx_rsvd2cpu_setup(chip); 2956 if (err) 2957 goto unlock; 2958 2959 err = mv88e6xxx_trunk_setup(chip); 2960 if (err) 2961 goto unlock; 2962 2963 err = mv88e6xxx_devmap_setup(chip); 2964 if (err) 2965 goto unlock; 2966 2967 err = mv88e6xxx_pri_setup(chip); 2968 if (err) 2969 goto unlock; 2970 2971 /* Setup PTP Hardware Clock and timestamping */ 2972 if (chip->info->ptp_support) { 2973 err = mv88e6xxx_ptp_setup(chip); 2974 if (err) 2975 goto unlock; 2976 2977 err = mv88e6xxx_hwtstamp_setup(chip); 2978 if (err) 2979 goto unlock; 2980 } 2981 2982 err = mv88e6xxx_stats_setup(chip); 2983 if (err) 2984 goto unlock; 2985 2986 unlock: 2987 mv88e6xxx_reg_unlock(chip); 2988 2989 if (err) 2990 return err; 2991 2992 /* Have to be called without holding the register lock, since 2993 * they take the devlink lock, and we later take the locks in 2994 * the reverse order when getting/setting parameters or 2995 * resource occupancy. 2996 */ 2997 err = mv88e6xxx_setup_devlink_resources(ds); 2998 if (err) 2999 return err; 3000 3001 err = mv88e6xxx_setup_devlink_params(ds); 3002 if (err) 3003 goto out_resources; 3004 3005 err = mv88e6xxx_setup_devlink_regions(ds); 3006 if (err) 3007 goto out_params; 3008 3009 return 0; 3010 3011 out_params: 3012 mv88e6xxx_teardown_devlink_params(ds); 3013 out_resources: 3014 dsa_devlink_resources_unregister(ds); 3015 3016 return err; 3017 } 3018 3019 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3020 { 3021 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3022 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3023 u16 val; 3024 int err; 3025 3026 if (!chip->info->ops->phy_read) 3027 return -EOPNOTSUPP; 3028 3029 mv88e6xxx_reg_lock(chip); 3030 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3031 mv88e6xxx_reg_unlock(chip); 3032 3033 if (reg == MII_PHYSID2) { 3034 /* Some internal PHYs don't have a model number. */ 3035 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3036 /* Then there is the 6165 family. It gets is 3037 * PHYs correct. But it can also have two 3038 * SERDES interfaces in the PHY address 3039 * space. And these don't have a model 3040 * number. But they are not PHYs, so we don't 3041 * want to give them something a PHY driver 3042 * will recognise. 3043 * 3044 * Use the mv88e6390 family model number 3045 * instead, for anything which really could be 3046 * a PHY, 3047 */ 3048 if (!(val & 0x3f0)) 3049 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3050 } 3051 3052 return err ? err : val; 3053 } 3054 3055 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3056 { 3057 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3058 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3059 int err; 3060 3061 if (!chip->info->ops->phy_write) 3062 return -EOPNOTSUPP; 3063 3064 mv88e6xxx_reg_lock(chip); 3065 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3066 mv88e6xxx_reg_unlock(chip); 3067 3068 return err; 3069 } 3070 3071 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3072 struct device_node *np, 3073 bool external) 3074 { 3075 static int index; 3076 struct mv88e6xxx_mdio_bus *mdio_bus; 3077 struct mii_bus *bus; 3078 int err; 3079 3080 if (external) { 3081 mv88e6xxx_reg_lock(chip); 3082 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3083 mv88e6xxx_reg_unlock(chip); 3084 3085 if (err) 3086 return err; 3087 } 3088 3089 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3090 if (!bus) 3091 return -ENOMEM; 3092 3093 mdio_bus = bus->priv; 3094 mdio_bus->bus = bus; 3095 mdio_bus->chip = chip; 3096 INIT_LIST_HEAD(&mdio_bus->list); 3097 mdio_bus->external = external; 3098 3099 if (np) { 3100 bus->name = np->full_name; 3101 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3102 } else { 3103 bus->name = "mv88e6xxx SMI"; 3104 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3105 } 3106 3107 bus->read = mv88e6xxx_mdio_read; 3108 bus->write = mv88e6xxx_mdio_write; 3109 bus->parent = chip->dev; 3110 3111 if (!external) { 3112 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3113 if (err) 3114 return err; 3115 } 3116 3117 err = of_mdiobus_register(bus, np); 3118 if (err) { 3119 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3120 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3121 return err; 3122 } 3123 3124 if (external) 3125 list_add_tail(&mdio_bus->list, &chip->mdios); 3126 else 3127 list_add(&mdio_bus->list, &chip->mdios); 3128 3129 return 0; 3130 } 3131 3132 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3133 3134 { 3135 struct mv88e6xxx_mdio_bus *mdio_bus; 3136 struct mii_bus *bus; 3137 3138 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3139 bus = mdio_bus->bus; 3140 3141 if (!mdio_bus->external) 3142 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3143 3144 mdiobus_unregister(bus); 3145 } 3146 } 3147 3148 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3149 struct device_node *np) 3150 { 3151 struct device_node *child; 3152 int err; 3153 3154 /* Always register one mdio bus for the internal/default mdio 3155 * bus. This maybe represented in the device tree, but is 3156 * optional. 3157 */ 3158 child = of_get_child_by_name(np, "mdio"); 3159 err = mv88e6xxx_mdio_register(chip, child, false); 3160 if (err) 3161 return err; 3162 3163 /* Walk the device tree, and see if there are any other nodes 3164 * which say they are compatible with the external mdio 3165 * bus. 3166 */ 3167 for_each_available_child_of_node(np, child) { 3168 if (of_device_is_compatible( 3169 child, "marvell,mv88e6xxx-mdio-external")) { 3170 err = mv88e6xxx_mdio_register(chip, child, true); 3171 if (err) { 3172 mv88e6xxx_mdios_unregister(chip); 3173 of_node_put(child); 3174 return err; 3175 } 3176 } 3177 } 3178 3179 return 0; 3180 } 3181 3182 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3183 { 3184 struct mv88e6xxx_chip *chip = ds->priv; 3185 3186 return chip->eeprom_len; 3187 } 3188 3189 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3190 struct ethtool_eeprom *eeprom, u8 *data) 3191 { 3192 struct mv88e6xxx_chip *chip = ds->priv; 3193 int err; 3194 3195 if (!chip->info->ops->get_eeprom) 3196 return -EOPNOTSUPP; 3197 3198 mv88e6xxx_reg_lock(chip); 3199 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3200 mv88e6xxx_reg_unlock(chip); 3201 3202 if (err) 3203 return err; 3204 3205 eeprom->magic = 0xc3ec4951; 3206 3207 return 0; 3208 } 3209 3210 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3211 struct ethtool_eeprom *eeprom, u8 *data) 3212 { 3213 struct mv88e6xxx_chip *chip = ds->priv; 3214 int err; 3215 3216 if (!chip->info->ops->set_eeprom) 3217 return -EOPNOTSUPP; 3218 3219 if (eeprom->magic != 0xc3ec4951) 3220 return -EINVAL; 3221 3222 mv88e6xxx_reg_lock(chip); 3223 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3224 mv88e6xxx_reg_unlock(chip); 3225 3226 return err; 3227 } 3228 3229 static const struct mv88e6xxx_ops mv88e6085_ops = { 3230 /* MV88E6XXX_FAMILY_6097 */ 3231 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3232 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3233 .irl_init_all = mv88e6352_g2_irl_init_all, 3234 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3235 .phy_read = mv88e6185_phy_ppu_read, 3236 .phy_write = mv88e6185_phy_ppu_write, 3237 .port_set_link = mv88e6xxx_port_set_link, 3238 .port_sync_link = mv88e6xxx_port_sync_link, 3239 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3240 .port_tag_remap = mv88e6095_port_tag_remap, 3241 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3242 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3243 .port_set_ether_type = mv88e6351_port_set_ether_type, 3244 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3245 .port_pause_limit = mv88e6097_port_pause_limit, 3246 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3247 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3248 .port_get_cmode = mv88e6185_port_get_cmode, 3249 .port_setup_message_port = mv88e6xxx_setup_message_port, 3250 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3251 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3252 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3253 .stats_get_strings = mv88e6095_stats_get_strings, 3254 .stats_get_stats = mv88e6095_stats_get_stats, 3255 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3256 .set_egress_port = mv88e6095_g1_set_egress_port, 3257 .watchdog_ops = &mv88e6097_watchdog_ops, 3258 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3259 .pot_clear = mv88e6xxx_g2_pot_clear, 3260 .ppu_enable = mv88e6185_g1_ppu_enable, 3261 .ppu_disable = mv88e6185_g1_ppu_disable, 3262 .reset = mv88e6185_g1_reset, 3263 .rmu_disable = mv88e6085_g1_rmu_disable, 3264 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3265 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3266 .phylink_validate = mv88e6185_phylink_validate, 3267 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3268 }; 3269 3270 static const struct mv88e6xxx_ops mv88e6095_ops = { 3271 /* MV88E6XXX_FAMILY_6095 */ 3272 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3273 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3274 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3275 .phy_read = mv88e6185_phy_ppu_read, 3276 .phy_write = mv88e6185_phy_ppu_write, 3277 .port_set_link = mv88e6xxx_port_set_link, 3278 .port_sync_link = mv88e6185_port_sync_link, 3279 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3280 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3281 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3282 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3283 .port_get_cmode = mv88e6185_port_get_cmode, 3284 .port_setup_message_port = mv88e6xxx_setup_message_port, 3285 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3286 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3287 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3288 .stats_get_strings = mv88e6095_stats_get_strings, 3289 .stats_get_stats = mv88e6095_stats_get_stats, 3290 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3291 .serdes_power = mv88e6185_serdes_power, 3292 .serdes_get_lane = mv88e6185_serdes_get_lane, 3293 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3294 .ppu_enable = mv88e6185_g1_ppu_enable, 3295 .ppu_disable = mv88e6185_g1_ppu_disable, 3296 .reset = mv88e6185_g1_reset, 3297 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3298 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3299 .phylink_validate = mv88e6185_phylink_validate, 3300 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3301 }; 3302 3303 static const struct mv88e6xxx_ops mv88e6097_ops = { 3304 /* MV88E6XXX_FAMILY_6097 */ 3305 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3306 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3307 .irl_init_all = mv88e6352_g2_irl_init_all, 3308 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3309 .phy_read = mv88e6xxx_g2_smi_phy_read, 3310 .phy_write = mv88e6xxx_g2_smi_phy_write, 3311 .port_set_link = mv88e6xxx_port_set_link, 3312 .port_sync_link = mv88e6185_port_sync_link, 3313 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3314 .port_tag_remap = mv88e6095_port_tag_remap, 3315 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3316 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3317 .port_set_ether_type = mv88e6351_port_set_ether_type, 3318 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3319 .port_pause_limit = mv88e6097_port_pause_limit, 3320 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3321 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3322 .port_get_cmode = mv88e6185_port_get_cmode, 3323 .port_setup_message_port = mv88e6xxx_setup_message_port, 3324 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3325 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3326 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3327 .stats_get_strings = mv88e6095_stats_get_strings, 3328 .stats_get_stats = mv88e6095_stats_get_stats, 3329 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3330 .set_egress_port = mv88e6095_g1_set_egress_port, 3331 .watchdog_ops = &mv88e6097_watchdog_ops, 3332 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3333 .serdes_power = mv88e6185_serdes_power, 3334 .serdes_get_lane = mv88e6185_serdes_get_lane, 3335 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3336 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3337 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3338 .serdes_irq_status = mv88e6097_serdes_irq_status, 3339 .pot_clear = mv88e6xxx_g2_pot_clear, 3340 .reset = mv88e6352_g1_reset, 3341 .rmu_disable = mv88e6085_g1_rmu_disable, 3342 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3343 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3344 .phylink_validate = mv88e6185_phylink_validate, 3345 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3346 }; 3347 3348 static const struct mv88e6xxx_ops mv88e6123_ops = { 3349 /* MV88E6XXX_FAMILY_6165 */ 3350 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3351 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3352 .irl_init_all = mv88e6352_g2_irl_init_all, 3353 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3354 .phy_read = mv88e6xxx_g2_smi_phy_read, 3355 .phy_write = mv88e6xxx_g2_smi_phy_write, 3356 .port_set_link = mv88e6xxx_port_set_link, 3357 .port_sync_link = mv88e6xxx_port_sync_link, 3358 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3359 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3360 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3361 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3362 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3363 .port_get_cmode = mv88e6185_port_get_cmode, 3364 .port_setup_message_port = mv88e6xxx_setup_message_port, 3365 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3366 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3367 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3368 .stats_get_strings = mv88e6095_stats_get_strings, 3369 .stats_get_stats = mv88e6095_stats_get_stats, 3370 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3371 .set_egress_port = mv88e6095_g1_set_egress_port, 3372 .watchdog_ops = &mv88e6097_watchdog_ops, 3373 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3374 .pot_clear = mv88e6xxx_g2_pot_clear, 3375 .reset = mv88e6352_g1_reset, 3376 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3377 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3378 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3379 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3380 .phylink_validate = mv88e6185_phylink_validate, 3381 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3382 }; 3383 3384 static const struct mv88e6xxx_ops mv88e6131_ops = { 3385 /* MV88E6XXX_FAMILY_6185 */ 3386 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3387 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3388 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3389 .phy_read = mv88e6185_phy_ppu_read, 3390 .phy_write = mv88e6185_phy_ppu_write, 3391 .port_set_link = mv88e6xxx_port_set_link, 3392 .port_sync_link = mv88e6xxx_port_sync_link, 3393 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3394 .port_tag_remap = mv88e6095_port_tag_remap, 3395 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3396 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3397 .port_set_ether_type = mv88e6351_port_set_ether_type, 3398 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3399 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3400 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3401 .port_pause_limit = mv88e6097_port_pause_limit, 3402 .port_set_pause = mv88e6185_port_set_pause, 3403 .port_get_cmode = mv88e6185_port_get_cmode, 3404 .port_setup_message_port = mv88e6xxx_setup_message_port, 3405 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3406 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3407 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3408 .stats_get_strings = mv88e6095_stats_get_strings, 3409 .stats_get_stats = mv88e6095_stats_get_stats, 3410 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3411 .set_egress_port = mv88e6095_g1_set_egress_port, 3412 .watchdog_ops = &mv88e6097_watchdog_ops, 3413 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3414 .ppu_enable = mv88e6185_g1_ppu_enable, 3415 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3416 .ppu_disable = mv88e6185_g1_ppu_disable, 3417 .reset = mv88e6185_g1_reset, 3418 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3419 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3420 .phylink_validate = mv88e6185_phylink_validate, 3421 }; 3422 3423 static const struct mv88e6xxx_ops mv88e6141_ops = { 3424 /* MV88E6XXX_FAMILY_6341 */ 3425 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3426 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3427 .irl_init_all = mv88e6352_g2_irl_init_all, 3428 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3429 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3430 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3431 .phy_read = mv88e6xxx_g2_smi_phy_read, 3432 .phy_write = mv88e6xxx_g2_smi_phy_write, 3433 .port_set_link = mv88e6xxx_port_set_link, 3434 .port_sync_link = mv88e6xxx_port_sync_link, 3435 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3436 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3437 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3438 .port_tag_remap = mv88e6095_port_tag_remap, 3439 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3440 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3441 .port_set_ether_type = mv88e6351_port_set_ether_type, 3442 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3443 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3444 .port_pause_limit = mv88e6097_port_pause_limit, 3445 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3446 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3447 .port_get_cmode = mv88e6352_port_get_cmode, 3448 .port_set_cmode = mv88e6341_port_set_cmode, 3449 .port_setup_message_port = mv88e6xxx_setup_message_port, 3450 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3451 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3452 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3453 .stats_get_strings = mv88e6320_stats_get_strings, 3454 .stats_get_stats = mv88e6390_stats_get_stats, 3455 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3456 .set_egress_port = mv88e6390_g1_set_egress_port, 3457 .watchdog_ops = &mv88e6390_watchdog_ops, 3458 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3459 .pot_clear = mv88e6xxx_g2_pot_clear, 3460 .reset = mv88e6352_g1_reset, 3461 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3462 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3463 .serdes_power = mv88e6390_serdes_power, 3464 .serdes_get_lane = mv88e6341_serdes_get_lane, 3465 /* Check status register pause & lpa register */ 3466 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3467 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3468 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3469 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3470 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3471 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3472 .serdes_irq_status = mv88e6390_serdes_irq_status, 3473 .gpio_ops = &mv88e6352_gpio_ops, 3474 .phylink_validate = mv88e6341_phylink_validate, 3475 }; 3476 3477 static const struct mv88e6xxx_ops mv88e6161_ops = { 3478 /* MV88E6XXX_FAMILY_6165 */ 3479 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3480 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3481 .irl_init_all = mv88e6352_g2_irl_init_all, 3482 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3483 .phy_read = mv88e6xxx_g2_smi_phy_read, 3484 .phy_write = mv88e6xxx_g2_smi_phy_write, 3485 .port_set_link = mv88e6xxx_port_set_link, 3486 .port_sync_link = mv88e6xxx_port_sync_link, 3487 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3488 .port_tag_remap = mv88e6095_port_tag_remap, 3489 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3490 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3491 .port_set_ether_type = mv88e6351_port_set_ether_type, 3492 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3493 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3494 .port_pause_limit = mv88e6097_port_pause_limit, 3495 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3496 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3497 .port_get_cmode = mv88e6185_port_get_cmode, 3498 .port_setup_message_port = mv88e6xxx_setup_message_port, 3499 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3500 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3501 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3502 .stats_get_strings = mv88e6095_stats_get_strings, 3503 .stats_get_stats = mv88e6095_stats_get_stats, 3504 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3505 .set_egress_port = mv88e6095_g1_set_egress_port, 3506 .watchdog_ops = &mv88e6097_watchdog_ops, 3507 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3508 .pot_clear = mv88e6xxx_g2_pot_clear, 3509 .reset = mv88e6352_g1_reset, 3510 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3511 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3512 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3513 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3514 .avb_ops = &mv88e6165_avb_ops, 3515 .ptp_ops = &mv88e6165_ptp_ops, 3516 .phylink_validate = mv88e6185_phylink_validate, 3517 }; 3518 3519 static const struct mv88e6xxx_ops mv88e6165_ops = { 3520 /* MV88E6XXX_FAMILY_6165 */ 3521 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3522 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3523 .irl_init_all = mv88e6352_g2_irl_init_all, 3524 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3525 .phy_read = mv88e6165_phy_read, 3526 .phy_write = mv88e6165_phy_write, 3527 .port_set_link = mv88e6xxx_port_set_link, 3528 .port_sync_link = mv88e6xxx_port_sync_link, 3529 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3530 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3531 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3532 .port_get_cmode = mv88e6185_port_get_cmode, 3533 .port_setup_message_port = mv88e6xxx_setup_message_port, 3534 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3535 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3536 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3537 .stats_get_strings = mv88e6095_stats_get_strings, 3538 .stats_get_stats = mv88e6095_stats_get_stats, 3539 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3540 .set_egress_port = mv88e6095_g1_set_egress_port, 3541 .watchdog_ops = &mv88e6097_watchdog_ops, 3542 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3543 .pot_clear = mv88e6xxx_g2_pot_clear, 3544 .reset = mv88e6352_g1_reset, 3545 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3546 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3547 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3548 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3549 .avb_ops = &mv88e6165_avb_ops, 3550 .ptp_ops = &mv88e6165_ptp_ops, 3551 .phylink_validate = mv88e6185_phylink_validate, 3552 }; 3553 3554 static const struct mv88e6xxx_ops mv88e6171_ops = { 3555 /* MV88E6XXX_FAMILY_6351 */ 3556 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3557 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3558 .irl_init_all = mv88e6352_g2_irl_init_all, 3559 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3560 .phy_read = mv88e6xxx_g2_smi_phy_read, 3561 .phy_write = mv88e6xxx_g2_smi_phy_write, 3562 .port_set_link = mv88e6xxx_port_set_link, 3563 .port_sync_link = mv88e6xxx_port_sync_link, 3564 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3565 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3566 .port_tag_remap = mv88e6095_port_tag_remap, 3567 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3568 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3569 .port_set_ether_type = mv88e6351_port_set_ether_type, 3570 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3571 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3572 .port_pause_limit = mv88e6097_port_pause_limit, 3573 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3574 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3575 .port_get_cmode = mv88e6352_port_get_cmode, 3576 .port_setup_message_port = mv88e6xxx_setup_message_port, 3577 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3578 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3579 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3580 .stats_get_strings = mv88e6095_stats_get_strings, 3581 .stats_get_stats = mv88e6095_stats_get_stats, 3582 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3583 .set_egress_port = mv88e6095_g1_set_egress_port, 3584 .watchdog_ops = &mv88e6097_watchdog_ops, 3585 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3586 .pot_clear = mv88e6xxx_g2_pot_clear, 3587 .reset = mv88e6352_g1_reset, 3588 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3589 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3590 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3591 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3592 .phylink_validate = mv88e6185_phylink_validate, 3593 }; 3594 3595 static const struct mv88e6xxx_ops mv88e6172_ops = { 3596 /* MV88E6XXX_FAMILY_6352 */ 3597 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3598 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3599 .irl_init_all = mv88e6352_g2_irl_init_all, 3600 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3601 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3602 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3603 .phy_read = mv88e6xxx_g2_smi_phy_read, 3604 .phy_write = mv88e6xxx_g2_smi_phy_write, 3605 .port_set_link = mv88e6xxx_port_set_link, 3606 .port_sync_link = mv88e6xxx_port_sync_link, 3607 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3608 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3609 .port_tag_remap = mv88e6095_port_tag_remap, 3610 .port_set_policy = mv88e6352_port_set_policy, 3611 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3612 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3613 .port_set_ether_type = mv88e6351_port_set_ether_type, 3614 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3615 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3616 .port_pause_limit = mv88e6097_port_pause_limit, 3617 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3618 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3619 .port_get_cmode = mv88e6352_port_get_cmode, 3620 .port_setup_message_port = mv88e6xxx_setup_message_port, 3621 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3622 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3623 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3624 .stats_get_strings = mv88e6095_stats_get_strings, 3625 .stats_get_stats = mv88e6095_stats_get_stats, 3626 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3627 .set_egress_port = mv88e6095_g1_set_egress_port, 3628 .watchdog_ops = &mv88e6097_watchdog_ops, 3629 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3630 .pot_clear = mv88e6xxx_g2_pot_clear, 3631 .reset = mv88e6352_g1_reset, 3632 .rmu_disable = mv88e6352_g1_rmu_disable, 3633 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3634 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3635 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3636 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3637 .serdes_get_lane = mv88e6352_serdes_get_lane, 3638 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3639 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3640 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3641 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3642 .serdes_power = mv88e6352_serdes_power, 3643 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3644 .serdes_get_regs = mv88e6352_serdes_get_regs, 3645 .gpio_ops = &mv88e6352_gpio_ops, 3646 .phylink_validate = mv88e6352_phylink_validate, 3647 }; 3648 3649 static const struct mv88e6xxx_ops mv88e6175_ops = { 3650 /* MV88E6XXX_FAMILY_6351 */ 3651 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3652 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3653 .irl_init_all = mv88e6352_g2_irl_init_all, 3654 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3655 .phy_read = mv88e6xxx_g2_smi_phy_read, 3656 .phy_write = mv88e6xxx_g2_smi_phy_write, 3657 .port_set_link = mv88e6xxx_port_set_link, 3658 .port_sync_link = mv88e6xxx_port_sync_link, 3659 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3660 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3661 .port_tag_remap = mv88e6095_port_tag_remap, 3662 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3663 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3664 .port_set_ether_type = mv88e6351_port_set_ether_type, 3665 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3666 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3667 .port_pause_limit = mv88e6097_port_pause_limit, 3668 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3669 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3670 .port_get_cmode = mv88e6352_port_get_cmode, 3671 .port_setup_message_port = mv88e6xxx_setup_message_port, 3672 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3673 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3674 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3675 .stats_get_strings = mv88e6095_stats_get_strings, 3676 .stats_get_stats = mv88e6095_stats_get_stats, 3677 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3678 .set_egress_port = mv88e6095_g1_set_egress_port, 3679 .watchdog_ops = &mv88e6097_watchdog_ops, 3680 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3681 .pot_clear = mv88e6xxx_g2_pot_clear, 3682 .reset = mv88e6352_g1_reset, 3683 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3684 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3685 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3686 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3687 .phylink_validate = mv88e6185_phylink_validate, 3688 }; 3689 3690 static const struct mv88e6xxx_ops mv88e6176_ops = { 3691 /* MV88E6XXX_FAMILY_6352 */ 3692 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3693 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3694 .irl_init_all = mv88e6352_g2_irl_init_all, 3695 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3696 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3697 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3698 .phy_read = mv88e6xxx_g2_smi_phy_read, 3699 .phy_write = mv88e6xxx_g2_smi_phy_write, 3700 .port_set_link = mv88e6xxx_port_set_link, 3701 .port_sync_link = mv88e6xxx_port_sync_link, 3702 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3703 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3704 .port_tag_remap = mv88e6095_port_tag_remap, 3705 .port_set_policy = mv88e6352_port_set_policy, 3706 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3707 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3708 .port_set_ether_type = mv88e6351_port_set_ether_type, 3709 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3710 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3711 .port_pause_limit = mv88e6097_port_pause_limit, 3712 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3713 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3714 .port_get_cmode = mv88e6352_port_get_cmode, 3715 .port_setup_message_port = mv88e6xxx_setup_message_port, 3716 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3717 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3718 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3719 .stats_get_strings = mv88e6095_stats_get_strings, 3720 .stats_get_stats = mv88e6095_stats_get_stats, 3721 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3722 .set_egress_port = mv88e6095_g1_set_egress_port, 3723 .watchdog_ops = &mv88e6097_watchdog_ops, 3724 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3725 .pot_clear = mv88e6xxx_g2_pot_clear, 3726 .reset = mv88e6352_g1_reset, 3727 .rmu_disable = mv88e6352_g1_rmu_disable, 3728 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3729 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3730 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3731 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3732 .serdes_get_lane = mv88e6352_serdes_get_lane, 3733 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3734 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3735 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3736 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3737 .serdes_power = mv88e6352_serdes_power, 3738 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3739 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3740 .serdes_irq_status = mv88e6352_serdes_irq_status, 3741 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3742 .serdes_get_regs = mv88e6352_serdes_get_regs, 3743 .gpio_ops = &mv88e6352_gpio_ops, 3744 .phylink_validate = mv88e6352_phylink_validate, 3745 }; 3746 3747 static const struct mv88e6xxx_ops mv88e6185_ops = { 3748 /* MV88E6XXX_FAMILY_6185 */ 3749 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3750 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3751 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3752 .phy_read = mv88e6185_phy_ppu_read, 3753 .phy_write = mv88e6185_phy_ppu_write, 3754 .port_set_link = mv88e6xxx_port_set_link, 3755 .port_sync_link = mv88e6185_port_sync_link, 3756 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3757 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3758 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3759 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3760 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3761 .port_set_pause = mv88e6185_port_set_pause, 3762 .port_get_cmode = mv88e6185_port_get_cmode, 3763 .port_setup_message_port = mv88e6xxx_setup_message_port, 3764 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3765 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3766 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3767 .stats_get_strings = mv88e6095_stats_get_strings, 3768 .stats_get_stats = mv88e6095_stats_get_stats, 3769 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3770 .set_egress_port = mv88e6095_g1_set_egress_port, 3771 .watchdog_ops = &mv88e6097_watchdog_ops, 3772 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3773 .serdes_power = mv88e6185_serdes_power, 3774 .serdes_get_lane = mv88e6185_serdes_get_lane, 3775 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3776 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3777 .ppu_enable = mv88e6185_g1_ppu_enable, 3778 .ppu_disable = mv88e6185_g1_ppu_disable, 3779 .reset = mv88e6185_g1_reset, 3780 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3781 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3782 .phylink_validate = mv88e6185_phylink_validate, 3783 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3784 }; 3785 3786 static const struct mv88e6xxx_ops mv88e6190_ops = { 3787 /* MV88E6XXX_FAMILY_6390 */ 3788 .setup_errata = mv88e6390_setup_errata, 3789 .irl_init_all = mv88e6390_g2_irl_init_all, 3790 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3791 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3792 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3793 .phy_read = mv88e6xxx_g2_smi_phy_read, 3794 .phy_write = mv88e6xxx_g2_smi_phy_write, 3795 .port_set_link = mv88e6xxx_port_set_link, 3796 .port_sync_link = mv88e6xxx_port_sync_link, 3797 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3798 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3799 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3800 .port_tag_remap = mv88e6390_port_tag_remap, 3801 .port_set_policy = mv88e6352_port_set_policy, 3802 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3803 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3804 .port_set_ether_type = mv88e6351_port_set_ether_type, 3805 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3806 .port_pause_limit = mv88e6390_port_pause_limit, 3807 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3808 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3809 .port_get_cmode = mv88e6352_port_get_cmode, 3810 .port_set_cmode = mv88e6390_port_set_cmode, 3811 .port_setup_message_port = mv88e6xxx_setup_message_port, 3812 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3813 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3814 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3815 .stats_get_strings = mv88e6320_stats_get_strings, 3816 .stats_get_stats = mv88e6390_stats_get_stats, 3817 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3818 .set_egress_port = mv88e6390_g1_set_egress_port, 3819 .watchdog_ops = &mv88e6390_watchdog_ops, 3820 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3821 .pot_clear = mv88e6xxx_g2_pot_clear, 3822 .reset = mv88e6352_g1_reset, 3823 .rmu_disable = mv88e6390_g1_rmu_disable, 3824 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3825 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3826 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3827 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3828 .serdes_power = mv88e6390_serdes_power, 3829 .serdes_get_lane = mv88e6390_serdes_get_lane, 3830 /* Check status register pause & lpa register */ 3831 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3832 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3833 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3834 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3835 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3836 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3837 .serdes_irq_status = mv88e6390_serdes_irq_status, 3838 .serdes_get_strings = mv88e6390_serdes_get_strings, 3839 .serdes_get_stats = mv88e6390_serdes_get_stats, 3840 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3841 .serdes_get_regs = mv88e6390_serdes_get_regs, 3842 .gpio_ops = &mv88e6352_gpio_ops, 3843 .phylink_validate = mv88e6390_phylink_validate, 3844 }; 3845 3846 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3847 /* MV88E6XXX_FAMILY_6390 */ 3848 .setup_errata = mv88e6390_setup_errata, 3849 .irl_init_all = mv88e6390_g2_irl_init_all, 3850 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3851 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3852 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3853 .phy_read = mv88e6xxx_g2_smi_phy_read, 3854 .phy_write = mv88e6xxx_g2_smi_phy_write, 3855 .port_set_link = mv88e6xxx_port_set_link, 3856 .port_sync_link = mv88e6xxx_port_sync_link, 3857 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3858 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 3859 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3860 .port_tag_remap = mv88e6390_port_tag_remap, 3861 .port_set_policy = mv88e6352_port_set_policy, 3862 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3863 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3864 .port_set_ether_type = mv88e6351_port_set_ether_type, 3865 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3866 .port_pause_limit = mv88e6390_port_pause_limit, 3867 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3868 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3869 .port_get_cmode = mv88e6352_port_get_cmode, 3870 .port_set_cmode = mv88e6390x_port_set_cmode, 3871 .port_setup_message_port = mv88e6xxx_setup_message_port, 3872 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3873 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3874 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3875 .stats_get_strings = mv88e6320_stats_get_strings, 3876 .stats_get_stats = mv88e6390_stats_get_stats, 3877 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3878 .set_egress_port = mv88e6390_g1_set_egress_port, 3879 .watchdog_ops = &mv88e6390_watchdog_ops, 3880 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3881 .pot_clear = mv88e6xxx_g2_pot_clear, 3882 .reset = mv88e6352_g1_reset, 3883 .rmu_disable = mv88e6390_g1_rmu_disable, 3884 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3885 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3886 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3887 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3888 .serdes_power = mv88e6390_serdes_power, 3889 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3890 /* Check status register pause & lpa register */ 3891 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3892 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3893 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3894 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3895 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3896 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3897 .serdes_irq_status = mv88e6390_serdes_irq_status, 3898 .serdes_get_strings = mv88e6390_serdes_get_strings, 3899 .serdes_get_stats = mv88e6390_serdes_get_stats, 3900 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3901 .serdes_get_regs = mv88e6390_serdes_get_regs, 3902 .gpio_ops = &mv88e6352_gpio_ops, 3903 .phylink_validate = mv88e6390x_phylink_validate, 3904 }; 3905 3906 static const struct mv88e6xxx_ops mv88e6191_ops = { 3907 /* MV88E6XXX_FAMILY_6390 */ 3908 .setup_errata = mv88e6390_setup_errata, 3909 .irl_init_all = mv88e6390_g2_irl_init_all, 3910 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3911 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3912 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3913 .phy_read = mv88e6xxx_g2_smi_phy_read, 3914 .phy_write = mv88e6xxx_g2_smi_phy_write, 3915 .port_set_link = mv88e6xxx_port_set_link, 3916 .port_sync_link = mv88e6xxx_port_sync_link, 3917 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3918 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3919 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3920 .port_tag_remap = mv88e6390_port_tag_remap, 3921 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3922 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3923 .port_set_ether_type = mv88e6351_port_set_ether_type, 3924 .port_pause_limit = mv88e6390_port_pause_limit, 3925 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3926 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3927 .port_get_cmode = mv88e6352_port_get_cmode, 3928 .port_set_cmode = mv88e6390_port_set_cmode, 3929 .port_setup_message_port = mv88e6xxx_setup_message_port, 3930 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3931 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3932 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3933 .stats_get_strings = mv88e6320_stats_get_strings, 3934 .stats_get_stats = mv88e6390_stats_get_stats, 3935 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3936 .set_egress_port = mv88e6390_g1_set_egress_port, 3937 .watchdog_ops = &mv88e6390_watchdog_ops, 3938 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3939 .pot_clear = mv88e6xxx_g2_pot_clear, 3940 .reset = mv88e6352_g1_reset, 3941 .rmu_disable = mv88e6390_g1_rmu_disable, 3942 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3943 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3944 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3945 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3946 .serdes_power = mv88e6390_serdes_power, 3947 .serdes_get_lane = mv88e6390_serdes_get_lane, 3948 /* Check status register pause & lpa register */ 3949 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3950 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3951 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3952 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3953 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3954 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3955 .serdes_irq_status = mv88e6390_serdes_irq_status, 3956 .serdes_get_strings = mv88e6390_serdes_get_strings, 3957 .serdes_get_stats = mv88e6390_serdes_get_stats, 3958 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3959 .serdes_get_regs = mv88e6390_serdes_get_regs, 3960 .avb_ops = &mv88e6390_avb_ops, 3961 .ptp_ops = &mv88e6352_ptp_ops, 3962 .phylink_validate = mv88e6390_phylink_validate, 3963 }; 3964 3965 static const struct mv88e6xxx_ops mv88e6240_ops = { 3966 /* MV88E6XXX_FAMILY_6352 */ 3967 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3968 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3969 .irl_init_all = mv88e6352_g2_irl_init_all, 3970 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3971 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3972 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3973 .phy_read = mv88e6xxx_g2_smi_phy_read, 3974 .phy_write = mv88e6xxx_g2_smi_phy_write, 3975 .port_set_link = mv88e6xxx_port_set_link, 3976 .port_sync_link = mv88e6xxx_port_sync_link, 3977 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3978 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3979 .port_tag_remap = mv88e6095_port_tag_remap, 3980 .port_set_policy = mv88e6352_port_set_policy, 3981 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3982 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3983 .port_set_ether_type = mv88e6351_port_set_ether_type, 3984 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3985 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3986 .port_pause_limit = mv88e6097_port_pause_limit, 3987 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3988 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3989 .port_get_cmode = mv88e6352_port_get_cmode, 3990 .port_setup_message_port = mv88e6xxx_setup_message_port, 3991 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3992 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3993 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3994 .stats_get_strings = mv88e6095_stats_get_strings, 3995 .stats_get_stats = mv88e6095_stats_get_stats, 3996 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3997 .set_egress_port = mv88e6095_g1_set_egress_port, 3998 .watchdog_ops = &mv88e6097_watchdog_ops, 3999 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4000 .pot_clear = mv88e6xxx_g2_pot_clear, 4001 .reset = mv88e6352_g1_reset, 4002 .rmu_disable = mv88e6352_g1_rmu_disable, 4003 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4004 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4005 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4006 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4007 .serdes_get_lane = mv88e6352_serdes_get_lane, 4008 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4009 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4010 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4011 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4012 .serdes_power = mv88e6352_serdes_power, 4013 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4014 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4015 .serdes_irq_status = mv88e6352_serdes_irq_status, 4016 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4017 .serdes_get_regs = mv88e6352_serdes_get_regs, 4018 .gpio_ops = &mv88e6352_gpio_ops, 4019 .avb_ops = &mv88e6352_avb_ops, 4020 .ptp_ops = &mv88e6352_ptp_ops, 4021 .phylink_validate = mv88e6352_phylink_validate, 4022 }; 4023 4024 static const struct mv88e6xxx_ops mv88e6250_ops = { 4025 /* MV88E6XXX_FAMILY_6250 */ 4026 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4027 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4028 .irl_init_all = mv88e6352_g2_irl_init_all, 4029 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4030 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4031 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4032 .phy_read = mv88e6xxx_g2_smi_phy_read, 4033 .phy_write = mv88e6xxx_g2_smi_phy_write, 4034 .port_set_link = mv88e6xxx_port_set_link, 4035 .port_sync_link = mv88e6xxx_port_sync_link, 4036 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4037 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4038 .port_tag_remap = mv88e6095_port_tag_remap, 4039 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4040 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4041 .port_set_ether_type = mv88e6351_port_set_ether_type, 4042 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4043 .port_pause_limit = mv88e6097_port_pause_limit, 4044 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4045 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4046 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4047 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4048 .stats_get_strings = mv88e6250_stats_get_strings, 4049 .stats_get_stats = mv88e6250_stats_get_stats, 4050 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4051 .set_egress_port = mv88e6095_g1_set_egress_port, 4052 .watchdog_ops = &mv88e6250_watchdog_ops, 4053 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4054 .pot_clear = mv88e6xxx_g2_pot_clear, 4055 .reset = mv88e6250_g1_reset, 4056 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4057 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4058 .avb_ops = &mv88e6352_avb_ops, 4059 .ptp_ops = &mv88e6250_ptp_ops, 4060 .phylink_validate = mv88e6065_phylink_validate, 4061 }; 4062 4063 static const struct mv88e6xxx_ops mv88e6290_ops = { 4064 /* MV88E6XXX_FAMILY_6390 */ 4065 .setup_errata = mv88e6390_setup_errata, 4066 .irl_init_all = mv88e6390_g2_irl_init_all, 4067 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4068 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4069 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4070 .phy_read = mv88e6xxx_g2_smi_phy_read, 4071 .phy_write = mv88e6xxx_g2_smi_phy_write, 4072 .port_set_link = mv88e6xxx_port_set_link, 4073 .port_sync_link = mv88e6xxx_port_sync_link, 4074 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4075 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4076 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4077 .port_tag_remap = mv88e6390_port_tag_remap, 4078 .port_set_policy = mv88e6352_port_set_policy, 4079 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4080 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4081 .port_set_ether_type = mv88e6351_port_set_ether_type, 4082 .port_pause_limit = mv88e6390_port_pause_limit, 4083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4085 .port_get_cmode = mv88e6352_port_get_cmode, 4086 .port_set_cmode = mv88e6390_port_set_cmode, 4087 .port_setup_message_port = mv88e6xxx_setup_message_port, 4088 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4089 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4090 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4091 .stats_get_strings = mv88e6320_stats_get_strings, 4092 .stats_get_stats = mv88e6390_stats_get_stats, 4093 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4094 .set_egress_port = mv88e6390_g1_set_egress_port, 4095 .watchdog_ops = &mv88e6390_watchdog_ops, 4096 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4097 .pot_clear = mv88e6xxx_g2_pot_clear, 4098 .reset = mv88e6352_g1_reset, 4099 .rmu_disable = mv88e6390_g1_rmu_disable, 4100 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4101 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4102 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4103 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4104 .serdes_power = mv88e6390_serdes_power, 4105 .serdes_get_lane = mv88e6390_serdes_get_lane, 4106 /* Check status register pause & lpa register */ 4107 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4108 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4109 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4110 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4111 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4112 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4113 .serdes_irq_status = mv88e6390_serdes_irq_status, 4114 .serdes_get_strings = mv88e6390_serdes_get_strings, 4115 .serdes_get_stats = mv88e6390_serdes_get_stats, 4116 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4117 .serdes_get_regs = mv88e6390_serdes_get_regs, 4118 .gpio_ops = &mv88e6352_gpio_ops, 4119 .avb_ops = &mv88e6390_avb_ops, 4120 .ptp_ops = &mv88e6352_ptp_ops, 4121 .phylink_validate = mv88e6390_phylink_validate, 4122 }; 4123 4124 static const struct mv88e6xxx_ops mv88e6320_ops = { 4125 /* MV88E6XXX_FAMILY_6320 */ 4126 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4127 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4128 .irl_init_all = mv88e6352_g2_irl_init_all, 4129 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4130 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4131 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4132 .phy_read = mv88e6xxx_g2_smi_phy_read, 4133 .phy_write = mv88e6xxx_g2_smi_phy_write, 4134 .port_set_link = mv88e6xxx_port_set_link, 4135 .port_sync_link = mv88e6xxx_port_sync_link, 4136 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4137 .port_tag_remap = mv88e6095_port_tag_remap, 4138 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4139 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4140 .port_set_ether_type = mv88e6351_port_set_ether_type, 4141 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4142 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4143 .port_pause_limit = mv88e6097_port_pause_limit, 4144 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4145 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4146 .port_get_cmode = mv88e6352_port_get_cmode, 4147 .port_setup_message_port = mv88e6xxx_setup_message_port, 4148 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4149 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4150 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4151 .stats_get_strings = mv88e6320_stats_get_strings, 4152 .stats_get_stats = mv88e6320_stats_get_stats, 4153 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4154 .set_egress_port = mv88e6095_g1_set_egress_port, 4155 .watchdog_ops = &mv88e6390_watchdog_ops, 4156 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4157 .pot_clear = mv88e6xxx_g2_pot_clear, 4158 .reset = mv88e6352_g1_reset, 4159 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4160 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4161 .gpio_ops = &mv88e6352_gpio_ops, 4162 .avb_ops = &mv88e6352_avb_ops, 4163 .ptp_ops = &mv88e6352_ptp_ops, 4164 .phylink_validate = mv88e6185_phylink_validate, 4165 }; 4166 4167 static const struct mv88e6xxx_ops mv88e6321_ops = { 4168 /* MV88E6XXX_FAMILY_6320 */ 4169 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4170 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4171 .irl_init_all = mv88e6352_g2_irl_init_all, 4172 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4173 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4174 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4175 .phy_read = mv88e6xxx_g2_smi_phy_read, 4176 .phy_write = mv88e6xxx_g2_smi_phy_write, 4177 .port_set_link = mv88e6xxx_port_set_link, 4178 .port_sync_link = mv88e6xxx_port_sync_link, 4179 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4180 .port_tag_remap = mv88e6095_port_tag_remap, 4181 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4182 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4183 .port_set_ether_type = mv88e6351_port_set_ether_type, 4184 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4185 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4186 .port_pause_limit = mv88e6097_port_pause_limit, 4187 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4188 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4189 .port_get_cmode = mv88e6352_port_get_cmode, 4190 .port_setup_message_port = mv88e6xxx_setup_message_port, 4191 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4192 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4193 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4194 .stats_get_strings = mv88e6320_stats_get_strings, 4195 .stats_get_stats = mv88e6320_stats_get_stats, 4196 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4197 .set_egress_port = mv88e6095_g1_set_egress_port, 4198 .watchdog_ops = &mv88e6390_watchdog_ops, 4199 .reset = mv88e6352_g1_reset, 4200 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4201 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4202 .gpio_ops = &mv88e6352_gpio_ops, 4203 .avb_ops = &mv88e6352_avb_ops, 4204 .ptp_ops = &mv88e6352_ptp_ops, 4205 .phylink_validate = mv88e6185_phylink_validate, 4206 }; 4207 4208 static const struct mv88e6xxx_ops mv88e6341_ops = { 4209 /* MV88E6XXX_FAMILY_6341 */ 4210 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4211 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4212 .irl_init_all = mv88e6352_g2_irl_init_all, 4213 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4214 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4215 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4216 .phy_read = mv88e6xxx_g2_smi_phy_read, 4217 .phy_write = mv88e6xxx_g2_smi_phy_write, 4218 .port_set_link = mv88e6xxx_port_set_link, 4219 .port_sync_link = mv88e6xxx_port_sync_link, 4220 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4221 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4222 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4223 .port_tag_remap = mv88e6095_port_tag_remap, 4224 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4225 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4226 .port_set_ether_type = mv88e6351_port_set_ether_type, 4227 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4228 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4229 .port_pause_limit = mv88e6097_port_pause_limit, 4230 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4231 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4232 .port_get_cmode = mv88e6352_port_get_cmode, 4233 .port_set_cmode = mv88e6341_port_set_cmode, 4234 .port_setup_message_port = mv88e6xxx_setup_message_port, 4235 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4236 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4237 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4238 .stats_get_strings = mv88e6320_stats_get_strings, 4239 .stats_get_stats = mv88e6390_stats_get_stats, 4240 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4241 .set_egress_port = mv88e6390_g1_set_egress_port, 4242 .watchdog_ops = &mv88e6390_watchdog_ops, 4243 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4244 .pot_clear = mv88e6xxx_g2_pot_clear, 4245 .reset = mv88e6352_g1_reset, 4246 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4247 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4248 .serdes_power = mv88e6390_serdes_power, 4249 .serdes_get_lane = mv88e6341_serdes_get_lane, 4250 /* Check status register pause & lpa register */ 4251 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4252 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4253 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4254 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4255 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4256 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4257 .serdes_irq_status = mv88e6390_serdes_irq_status, 4258 .gpio_ops = &mv88e6352_gpio_ops, 4259 .avb_ops = &mv88e6390_avb_ops, 4260 .ptp_ops = &mv88e6352_ptp_ops, 4261 .phylink_validate = mv88e6341_phylink_validate, 4262 }; 4263 4264 static const struct mv88e6xxx_ops mv88e6350_ops = { 4265 /* MV88E6XXX_FAMILY_6351 */ 4266 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4267 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4268 .irl_init_all = mv88e6352_g2_irl_init_all, 4269 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4270 .phy_read = mv88e6xxx_g2_smi_phy_read, 4271 .phy_write = mv88e6xxx_g2_smi_phy_write, 4272 .port_set_link = mv88e6xxx_port_set_link, 4273 .port_sync_link = mv88e6xxx_port_sync_link, 4274 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4275 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4276 .port_tag_remap = mv88e6095_port_tag_remap, 4277 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4278 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4279 .port_set_ether_type = mv88e6351_port_set_ether_type, 4280 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4281 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4282 .port_pause_limit = mv88e6097_port_pause_limit, 4283 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4284 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4285 .port_get_cmode = mv88e6352_port_get_cmode, 4286 .port_setup_message_port = mv88e6xxx_setup_message_port, 4287 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4288 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4289 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4290 .stats_get_strings = mv88e6095_stats_get_strings, 4291 .stats_get_stats = mv88e6095_stats_get_stats, 4292 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4293 .set_egress_port = mv88e6095_g1_set_egress_port, 4294 .watchdog_ops = &mv88e6097_watchdog_ops, 4295 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4296 .pot_clear = mv88e6xxx_g2_pot_clear, 4297 .reset = mv88e6352_g1_reset, 4298 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4299 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4300 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4301 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4302 .phylink_validate = mv88e6185_phylink_validate, 4303 }; 4304 4305 static const struct mv88e6xxx_ops mv88e6351_ops = { 4306 /* MV88E6XXX_FAMILY_6351 */ 4307 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4308 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4309 .irl_init_all = mv88e6352_g2_irl_init_all, 4310 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4311 .phy_read = mv88e6xxx_g2_smi_phy_read, 4312 .phy_write = mv88e6xxx_g2_smi_phy_write, 4313 .port_set_link = mv88e6xxx_port_set_link, 4314 .port_sync_link = mv88e6xxx_port_sync_link, 4315 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4316 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4317 .port_tag_remap = mv88e6095_port_tag_remap, 4318 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4319 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4320 .port_set_ether_type = mv88e6351_port_set_ether_type, 4321 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4322 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4323 .port_pause_limit = mv88e6097_port_pause_limit, 4324 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4325 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4326 .port_get_cmode = mv88e6352_port_get_cmode, 4327 .port_setup_message_port = mv88e6xxx_setup_message_port, 4328 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4329 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4330 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4331 .stats_get_strings = mv88e6095_stats_get_strings, 4332 .stats_get_stats = mv88e6095_stats_get_stats, 4333 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4334 .set_egress_port = mv88e6095_g1_set_egress_port, 4335 .watchdog_ops = &mv88e6097_watchdog_ops, 4336 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4337 .pot_clear = mv88e6xxx_g2_pot_clear, 4338 .reset = mv88e6352_g1_reset, 4339 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4340 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4341 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4342 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4343 .avb_ops = &mv88e6352_avb_ops, 4344 .ptp_ops = &mv88e6352_ptp_ops, 4345 .phylink_validate = mv88e6185_phylink_validate, 4346 }; 4347 4348 static const struct mv88e6xxx_ops mv88e6352_ops = { 4349 /* MV88E6XXX_FAMILY_6352 */ 4350 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4351 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4352 .irl_init_all = mv88e6352_g2_irl_init_all, 4353 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4354 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4355 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4356 .phy_read = mv88e6xxx_g2_smi_phy_read, 4357 .phy_write = mv88e6xxx_g2_smi_phy_write, 4358 .port_set_link = mv88e6xxx_port_set_link, 4359 .port_sync_link = mv88e6xxx_port_sync_link, 4360 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4361 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4362 .port_tag_remap = mv88e6095_port_tag_remap, 4363 .port_set_policy = mv88e6352_port_set_policy, 4364 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4365 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4366 .port_set_ether_type = mv88e6351_port_set_ether_type, 4367 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4368 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4369 .port_pause_limit = mv88e6097_port_pause_limit, 4370 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4371 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4372 .port_get_cmode = mv88e6352_port_get_cmode, 4373 .port_setup_message_port = mv88e6xxx_setup_message_port, 4374 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4375 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4376 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4377 .stats_get_strings = mv88e6095_stats_get_strings, 4378 .stats_get_stats = mv88e6095_stats_get_stats, 4379 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4380 .set_egress_port = mv88e6095_g1_set_egress_port, 4381 .watchdog_ops = &mv88e6097_watchdog_ops, 4382 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4383 .pot_clear = mv88e6xxx_g2_pot_clear, 4384 .reset = mv88e6352_g1_reset, 4385 .rmu_disable = mv88e6352_g1_rmu_disable, 4386 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4387 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4388 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4389 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4390 .serdes_get_lane = mv88e6352_serdes_get_lane, 4391 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4392 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4393 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4394 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4395 .serdes_power = mv88e6352_serdes_power, 4396 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4397 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4398 .serdes_irq_status = mv88e6352_serdes_irq_status, 4399 .gpio_ops = &mv88e6352_gpio_ops, 4400 .avb_ops = &mv88e6352_avb_ops, 4401 .ptp_ops = &mv88e6352_ptp_ops, 4402 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4403 .serdes_get_strings = mv88e6352_serdes_get_strings, 4404 .serdes_get_stats = mv88e6352_serdes_get_stats, 4405 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4406 .serdes_get_regs = mv88e6352_serdes_get_regs, 4407 .phylink_validate = mv88e6352_phylink_validate, 4408 }; 4409 4410 static const struct mv88e6xxx_ops mv88e6390_ops = { 4411 /* MV88E6XXX_FAMILY_6390 */ 4412 .setup_errata = mv88e6390_setup_errata, 4413 .irl_init_all = mv88e6390_g2_irl_init_all, 4414 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4415 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4416 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4417 .phy_read = mv88e6xxx_g2_smi_phy_read, 4418 .phy_write = mv88e6xxx_g2_smi_phy_write, 4419 .port_set_link = mv88e6xxx_port_set_link, 4420 .port_sync_link = mv88e6xxx_port_sync_link, 4421 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4422 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4423 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4424 .port_tag_remap = mv88e6390_port_tag_remap, 4425 .port_set_policy = mv88e6352_port_set_policy, 4426 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4427 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4428 .port_set_ether_type = mv88e6351_port_set_ether_type, 4429 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4430 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4431 .port_pause_limit = mv88e6390_port_pause_limit, 4432 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4433 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4434 .port_get_cmode = mv88e6352_port_get_cmode, 4435 .port_set_cmode = mv88e6390_port_set_cmode, 4436 .port_setup_message_port = mv88e6xxx_setup_message_port, 4437 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4438 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4439 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4440 .stats_get_strings = mv88e6320_stats_get_strings, 4441 .stats_get_stats = mv88e6390_stats_get_stats, 4442 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4443 .set_egress_port = mv88e6390_g1_set_egress_port, 4444 .watchdog_ops = &mv88e6390_watchdog_ops, 4445 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4446 .pot_clear = mv88e6xxx_g2_pot_clear, 4447 .reset = mv88e6352_g1_reset, 4448 .rmu_disable = mv88e6390_g1_rmu_disable, 4449 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4450 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4451 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4452 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4453 .serdes_power = mv88e6390_serdes_power, 4454 .serdes_get_lane = mv88e6390_serdes_get_lane, 4455 /* Check status register pause & lpa register */ 4456 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4457 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4458 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4459 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4460 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4461 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4462 .serdes_irq_status = mv88e6390_serdes_irq_status, 4463 .gpio_ops = &mv88e6352_gpio_ops, 4464 .avb_ops = &mv88e6390_avb_ops, 4465 .ptp_ops = &mv88e6352_ptp_ops, 4466 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4467 .serdes_get_strings = mv88e6390_serdes_get_strings, 4468 .serdes_get_stats = mv88e6390_serdes_get_stats, 4469 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4470 .serdes_get_regs = mv88e6390_serdes_get_regs, 4471 .phylink_validate = mv88e6390_phylink_validate, 4472 }; 4473 4474 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4475 /* MV88E6XXX_FAMILY_6390 */ 4476 .setup_errata = mv88e6390_setup_errata, 4477 .irl_init_all = mv88e6390_g2_irl_init_all, 4478 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4479 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4480 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4481 .phy_read = mv88e6xxx_g2_smi_phy_read, 4482 .phy_write = mv88e6xxx_g2_smi_phy_write, 4483 .port_set_link = mv88e6xxx_port_set_link, 4484 .port_sync_link = mv88e6xxx_port_sync_link, 4485 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4486 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4487 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4488 .port_tag_remap = mv88e6390_port_tag_remap, 4489 .port_set_policy = mv88e6352_port_set_policy, 4490 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4491 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4492 .port_set_ether_type = mv88e6351_port_set_ether_type, 4493 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4494 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4495 .port_pause_limit = mv88e6390_port_pause_limit, 4496 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4497 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4498 .port_get_cmode = mv88e6352_port_get_cmode, 4499 .port_set_cmode = mv88e6390x_port_set_cmode, 4500 .port_setup_message_port = mv88e6xxx_setup_message_port, 4501 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4502 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4503 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4504 .stats_get_strings = mv88e6320_stats_get_strings, 4505 .stats_get_stats = mv88e6390_stats_get_stats, 4506 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4507 .set_egress_port = mv88e6390_g1_set_egress_port, 4508 .watchdog_ops = &mv88e6390_watchdog_ops, 4509 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4510 .pot_clear = mv88e6xxx_g2_pot_clear, 4511 .reset = mv88e6352_g1_reset, 4512 .rmu_disable = mv88e6390_g1_rmu_disable, 4513 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4514 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4515 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4516 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4517 .serdes_power = mv88e6390_serdes_power, 4518 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4519 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4520 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4521 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4522 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4523 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4524 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4525 .serdes_irq_status = mv88e6390_serdes_irq_status, 4526 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4527 .serdes_get_strings = mv88e6390_serdes_get_strings, 4528 .serdes_get_stats = mv88e6390_serdes_get_stats, 4529 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4530 .serdes_get_regs = mv88e6390_serdes_get_regs, 4531 .gpio_ops = &mv88e6352_gpio_ops, 4532 .avb_ops = &mv88e6390_avb_ops, 4533 .ptp_ops = &mv88e6352_ptp_ops, 4534 .phylink_validate = mv88e6390x_phylink_validate, 4535 }; 4536 4537 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4538 [MV88E6085] = { 4539 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4540 .family = MV88E6XXX_FAMILY_6097, 4541 .name = "Marvell 88E6085", 4542 .num_databases = 4096, 4543 .num_macs = 8192, 4544 .num_ports = 10, 4545 .num_internal_phys = 5, 4546 .max_vid = 4095, 4547 .port_base_addr = 0x10, 4548 .phy_base_addr = 0x0, 4549 .global1_addr = 0x1b, 4550 .global2_addr = 0x1c, 4551 .age_time_coeff = 15000, 4552 .g1_irqs = 8, 4553 .g2_irqs = 10, 4554 .atu_move_port_mask = 0xf, 4555 .pvt = true, 4556 .multi_chip = true, 4557 .tag_protocol = DSA_TAG_PROTO_DSA, 4558 .ops = &mv88e6085_ops, 4559 }, 4560 4561 [MV88E6095] = { 4562 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4563 .family = MV88E6XXX_FAMILY_6095, 4564 .name = "Marvell 88E6095/88E6095F", 4565 .num_databases = 256, 4566 .num_macs = 8192, 4567 .num_ports = 11, 4568 .num_internal_phys = 0, 4569 .max_vid = 4095, 4570 .port_base_addr = 0x10, 4571 .phy_base_addr = 0x0, 4572 .global1_addr = 0x1b, 4573 .global2_addr = 0x1c, 4574 .age_time_coeff = 15000, 4575 .g1_irqs = 8, 4576 .atu_move_port_mask = 0xf, 4577 .multi_chip = true, 4578 .tag_protocol = DSA_TAG_PROTO_DSA, 4579 .ops = &mv88e6095_ops, 4580 }, 4581 4582 [MV88E6097] = { 4583 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4584 .family = MV88E6XXX_FAMILY_6097, 4585 .name = "Marvell 88E6097/88E6097F", 4586 .num_databases = 4096, 4587 .num_macs = 8192, 4588 .num_ports = 11, 4589 .num_internal_phys = 8, 4590 .max_vid = 4095, 4591 .port_base_addr = 0x10, 4592 .phy_base_addr = 0x0, 4593 .global1_addr = 0x1b, 4594 .global2_addr = 0x1c, 4595 .age_time_coeff = 15000, 4596 .g1_irqs = 8, 4597 .g2_irqs = 10, 4598 .atu_move_port_mask = 0xf, 4599 .pvt = true, 4600 .multi_chip = true, 4601 .tag_protocol = DSA_TAG_PROTO_EDSA, 4602 .ops = &mv88e6097_ops, 4603 }, 4604 4605 [MV88E6123] = { 4606 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4607 .family = MV88E6XXX_FAMILY_6165, 4608 .name = "Marvell 88E6123", 4609 .num_databases = 4096, 4610 .num_macs = 1024, 4611 .num_ports = 3, 4612 .num_internal_phys = 5, 4613 .max_vid = 4095, 4614 .port_base_addr = 0x10, 4615 .phy_base_addr = 0x0, 4616 .global1_addr = 0x1b, 4617 .global2_addr = 0x1c, 4618 .age_time_coeff = 15000, 4619 .g1_irqs = 9, 4620 .g2_irqs = 10, 4621 .atu_move_port_mask = 0xf, 4622 .pvt = true, 4623 .multi_chip = true, 4624 .tag_protocol = DSA_TAG_PROTO_EDSA, 4625 .ops = &mv88e6123_ops, 4626 }, 4627 4628 [MV88E6131] = { 4629 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4630 .family = MV88E6XXX_FAMILY_6185, 4631 .name = "Marvell 88E6131", 4632 .num_databases = 256, 4633 .num_macs = 8192, 4634 .num_ports = 8, 4635 .num_internal_phys = 0, 4636 .max_vid = 4095, 4637 .port_base_addr = 0x10, 4638 .phy_base_addr = 0x0, 4639 .global1_addr = 0x1b, 4640 .global2_addr = 0x1c, 4641 .age_time_coeff = 15000, 4642 .g1_irqs = 9, 4643 .atu_move_port_mask = 0xf, 4644 .multi_chip = true, 4645 .tag_protocol = DSA_TAG_PROTO_DSA, 4646 .ops = &mv88e6131_ops, 4647 }, 4648 4649 [MV88E6141] = { 4650 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4651 .family = MV88E6XXX_FAMILY_6341, 4652 .name = "Marvell 88E6141", 4653 .num_databases = 4096, 4654 .num_macs = 2048, 4655 .num_ports = 6, 4656 .num_internal_phys = 5, 4657 .num_gpio = 11, 4658 .max_vid = 4095, 4659 .port_base_addr = 0x10, 4660 .phy_base_addr = 0x10, 4661 .global1_addr = 0x1b, 4662 .global2_addr = 0x1c, 4663 .age_time_coeff = 3750, 4664 .atu_move_port_mask = 0x1f, 4665 .g1_irqs = 9, 4666 .g2_irqs = 10, 4667 .pvt = true, 4668 .multi_chip = true, 4669 .tag_protocol = DSA_TAG_PROTO_EDSA, 4670 .ops = &mv88e6141_ops, 4671 }, 4672 4673 [MV88E6161] = { 4674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4675 .family = MV88E6XXX_FAMILY_6165, 4676 .name = "Marvell 88E6161", 4677 .num_databases = 4096, 4678 .num_macs = 1024, 4679 .num_ports = 6, 4680 .num_internal_phys = 5, 4681 .max_vid = 4095, 4682 .port_base_addr = 0x10, 4683 .phy_base_addr = 0x0, 4684 .global1_addr = 0x1b, 4685 .global2_addr = 0x1c, 4686 .age_time_coeff = 15000, 4687 .g1_irqs = 9, 4688 .g2_irqs = 10, 4689 .atu_move_port_mask = 0xf, 4690 .pvt = true, 4691 .multi_chip = true, 4692 .tag_protocol = DSA_TAG_PROTO_EDSA, 4693 .ptp_support = true, 4694 .ops = &mv88e6161_ops, 4695 }, 4696 4697 [MV88E6165] = { 4698 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4699 .family = MV88E6XXX_FAMILY_6165, 4700 .name = "Marvell 88E6165", 4701 .num_databases = 4096, 4702 .num_macs = 8192, 4703 .num_ports = 6, 4704 .num_internal_phys = 0, 4705 .max_vid = 4095, 4706 .port_base_addr = 0x10, 4707 .phy_base_addr = 0x0, 4708 .global1_addr = 0x1b, 4709 .global2_addr = 0x1c, 4710 .age_time_coeff = 15000, 4711 .g1_irqs = 9, 4712 .g2_irqs = 10, 4713 .atu_move_port_mask = 0xf, 4714 .pvt = true, 4715 .multi_chip = true, 4716 .tag_protocol = DSA_TAG_PROTO_DSA, 4717 .ptp_support = true, 4718 .ops = &mv88e6165_ops, 4719 }, 4720 4721 [MV88E6171] = { 4722 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4723 .family = MV88E6XXX_FAMILY_6351, 4724 .name = "Marvell 88E6171", 4725 .num_databases = 4096, 4726 .num_macs = 8192, 4727 .num_ports = 7, 4728 .num_internal_phys = 5, 4729 .max_vid = 4095, 4730 .port_base_addr = 0x10, 4731 .phy_base_addr = 0x0, 4732 .global1_addr = 0x1b, 4733 .global2_addr = 0x1c, 4734 .age_time_coeff = 15000, 4735 .g1_irqs = 9, 4736 .g2_irqs = 10, 4737 .atu_move_port_mask = 0xf, 4738 .pvt = true, 4739 .multi_chip = true, 4740 .tag_protocol = DSA_TAG_PROTO_EDSA, 4741 .ops = &mv88e6171_ops, 4742 }, 4743 4744 [MV88E6172] = { 4745 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4746 .family = MV88E6XXX_FAMILY_6352, 4747 .name = "Marvell 88E6172", 4748 .num_databases = 4096, 4749 .num_macs = 8192, 4750 .num_ports = 7, 4751 .num_internal_phys = 5, 4752 .num_gpio = 15, 4753 .max_vid = 4095, 4754 .port_base_addr = 0x10, 4755 .phy_base_addr = 0x0, 4756 .global1_addr = 0x1b, 4757 .global2_addr = 0x1c, 4758 .age_time_coeff = 15000, 4759 .g1_irqs = 9, 4760 .g2_irqs = 10, 4761 .atu_move_port_mask = 0xf, 4762 .pvt = true, 4763 .multi_chip = true, 4764 .tag_protocol = DSA_TAG_PROTO_EDSA, 4765 .ops = &mv88e6172_ops, 4766 }, 4767 4768 [MV88E6175] = { 4769 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4770 .family = MV88E6XXX_FAMILY_6351, 4771 .name = "Marvell 88E6175", 4772 .num_databases = 4096, 4773 .num_macs = 8192, 4774 .num_ports = 7, 4775 .num_internal_phys = 5, 4776 .max_vid = 4095, 4777 .port_base_addr = 0x10, 4778 .phy_base_addr = 0x0, 4779 .global1_addr = 0x1b, 4780 .global2_addr = 0x1c, 4781 .age_time_coeff = 15000, 4782 .g1_irqs = 9, 4783 .g2_irqs = 10, 4784 .atu_move_port_mask = 0xf, 4785 .pvt = true, 4786 .multi_chip = true, 4787 .tag_protocol = DSA_TAG_PROTO_EDSA, 4788 .ops = &mv88e6175_ops, 4789 }, 4790 4791 [MV88E6176] = { 4792 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4793 .family = MV88E6XXX_FAMILY_6352, 4794 .name = "Marvell 88E6176", 4795 .num_databases = 4096, 4796 .num_macs = 8192, 4797 .num_ports = 7, 4798 .num_internal_phys = 5, 4799 .num_gpio = 15, 4800 .max_vid = 4095, 4801 .port_base_addr = 0x10, 4802 .phy_base_addr = 0x0, 4803 .global1_addr = 0x1b, 4804 .global2_addr = 0x1c, 4805 .age_time_coeff = 15000, 4806 .g1_irqs = 9, 4807 .g2_irqs = 10, 4808 .atu_move_port_mask = 0xf, 4809 .pvt = true, 4810 .multi_chip = true, 4811 .tag_protocol = DSA_TAG_PROTO_EDSA, 4812 .ops = &mv88e6176_ops, 4813 }, 4814 4815 [MV88E6185] = { 4816 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4817 .family = MV88E6XXX_FAMILY_6185, 4818 .name = "Marvell 88E6185", 4819 .num_databases = 256, 4820 .num_macs = 8192, 4821 .num_ports = 10, 4822 .num_internal_phys = 0, 4823 .max_vid = 4095, 4824 .port_base_addr = 0x10, 4825 .phy_base_addr = 0x0, 4826 .global1_addr = 0x1b, 4827 .global2_addr = 0x1c, 4828 .age_time_coeff = 15000, 4829 .g1_irqs = 8, 4830 .atu_move_port_mask = 0xf, 4831 .multi_chip = true, 4832 .tag_protocol = DSA_TAG_PROTO_EDSA, 4833 .ops = &mv88e6185_ops, 4834 }, 4835 4836 [MV88E6190] = { 4837 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4838 .family = MV88E6XXX_FAMILY_6390, 4839 .name = "Marvell 88E6190", 4840 .num_databases = 4096, 4841 .num_macs = 16384, 4842 .num_ports = 11, /* 10 + Z80 */ 4843 .num_internal_phys = 9, 4844 .num_gpio = 16, 4845 .max_vid = 8191, 4846 .port_base_addr = 0x0, 4847 .phy_base_addr = 0x0, 4848 .global1_addr = 0x1b, 4849 .global2_addr = 0x1c, 4850 .tag_protocol = DSA_TAG_PROTO_DSA, 4851 .age_time_coeff = 3750, 4852 .g1_irqs = 9, 4853 .g2_irqs = 14, 4854 .pvt = true, 4855 .multi_chip = true, 4856 .atu_move_port_mask = 0x1f, 4857 .ops = &mv88e6190_ops, 4858 }, 4859 4860 [MV88E6190X] = { 4861 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4862 .family = MV88E6XXX_FAMILY_6390, 4863 .name = "Marvell 88E6190X", 4864 .num_databases = 4096, 4865 .num_macs = 16384, 4866 .num_ports = 11, /* 10 + Z80 */ 4867 .num_internal_phys = 9, 4868 .num_gpio = 16, 4869 .max_vid = 8191, 4870 .port_base_addr = 0x0, 4871 .phy_base_addr = 0x0, 4872 .global1_addr = 0x1b, 4873 .global2_addr = 0x1c, 4874 .age_time_coeff = 3750, 4875 .g1_irqs = 9, 4876 .g2_irqs = 14, 4877 .atu_move_port_mask = 0x1f, 4878 .pvt = true, 4879 .multi_chip = true, 4880 .tag_protocol = DSA_TAG_PROTO_DSA, 4881 .ops = &mv88e6190x_ops, 4882 }, 4883 4884 [MV88E6191] = { 4885 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4886 .family = MV88E6XXX_FAMILY_6390, 4887 .name = "Marvell 88E6191", 4888 .num_databases = 4096, 4889 .num_macs = 16384, 4890 .num_ports = 11, /* 10 + Z80 */ 4891 .num_internal_phys = 9, 4892 .max_vid = 8191, 4893 .port_base_addr = 0x0, 4894 .phy_base_addr = 0x0, 4895 .global1_addr = 0x1b, 4896 .global2_addr = 0x1c, 4897 .age_time_coeff = 3750, 4898 .g1_irqs = 9, 4899 .g2_irqs = 14, 4900 .atu_move_port_mask = 0x1f, 4901 .pvt = true, 4902 .multi_chip = true, 4903 .tag_protocol = DSA_TAG_PROTO_DSA, 4904 .ptp_support = true, 4905 .ops = &mv88e6191_ops, 4906 }, 4907 4908 [MV88E6220] = { 4909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4910 .family = MV88E6XXX_FAMILY_6250, 4911 .name = "Marvell 88E6220", 4912 .num_databases = 64, 4913 4914 /* Ports 2-4 are not routed to pins 4915 * => usable ports 0, 1, 5, 6 4916 */ 4917 .num_ports = 7, 4918 .num_internal_phys = 2, 4919 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4920 .max_vid = 4095, 4921 .port_base_addr = 0x08, 4922 .phy_base_addr = 0x00, 4923 .global1_addr = 0x0f, 4924 .global2_addr = 0x07, 4925 .age_time_coeff = 15000, 4926 .g1_irqs = 9, 4927 .g2_irqs = 10, 4928 .atu_move_port_mask = 0xf, 4929 .dual_chip = true, 4930 .tag_protocol = DSA_TAG_PROTO_DSA, 4931 .ptp_support = true, 4932 .ops = &mv88e6250_ops, 4933 }, 4934 4935 [MV88E6240] = { 4936 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4937 .family = MV88E6XXX_FAMILY_6352, 4938 .name = "Marvell 88E6240", 4939 .num_databases = 4096, 4940 .num_macs = 8192, 4941 .num_ports = 7, 4942 .num_internal_phys = 5, 4943 .num_gpio = 15, 4944 .max_vid = 4095, 4945 .port_base_addr = 0x10, 4946 .phy_base_addr = 0x0, 4947 .global1_addr = 0x1b, 4948 .global2_addr = 0x1c, 4949 .age_time_coeff = 15000, 4950 .g1_irqs = 9, 4951 .g2_irqs = 10, 4952 .atu_move_port_mask = 0xf, 4953 .pvt = true, 4954 .multi_chip = true, 4955 .tag_protocol = DSA_TAG_PROTO_EDSA, 4956 .ptp_support = true, 4957 .ops = &mv88e6240_ops, 4958 }, 4959 4960 [MV88E6250] = { 4961 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4962 .family = MV88E6XXX_FAMILY_6250, 4963 .name = "Marvell 88E6250", 4964 .num_databases = 64, 4965 .num_ports = 7, 4966 .num_internal_phys = 5, 4967 .max_vid = 4095, 4968 .port_base_addr = 0x08, 4969 .phy_base_addr = 0x00, 4970 .global1_addr = 0x0f, 4971 .global2_addr = 0x07, 4972 .age_time_coeff = 15000, 4973 .g1_irqs = 9, 4974 .g2_irqs = 10, 4975 .atu_move_port_mask = 0xf, 4976 .dual_chip = true, 4977 .tag_protocol = DSA_TAG_PROTO_DSA, 4978 .ptp_support = true, 4979 .ops = &mv88e6250_ops, 4980 }, 4981 4982 [MV88E6290] = { 4983 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4984 .family = MV88E6XXX_FAMILY_6390, 4985 .name = "Marvell 88E6290", 4986 .num_databases = 4096, 4987 .num_ports = 11, /* 10 + Z80 */ 4988 .num_internal_phys = 9, 4989 .num_gpio = 16, 4990 .max_vid = 8191, 4991 .port_base_addr = 0x0, 4992 .phy_base_addr = 0x0, 4993 .global1_addr = 0x1b, 4994 .global2_addr = 0x1c, 4995 .age_time_coeff = 3750, 4996 .g1_irqs = 9, 4997 .g2_irqs = 14, 4998 .atu_move_port_mask = 0x1f, 4999 .pvt = true, 5000 .multi_chip = true, 5001 .tag_protocol = DSA_TAG_PROTO_DSA, 5002 .ptp_support = true, 5003 .ops = &mv88e6290_ops, 5004 }, 5005 5006 [MV88E6320] = { 5007 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5008 .family = MV88E6XXX_FAMILY_6320, 5009 .name = "Marvell 88E6320", 5010 .num_databases = 4096, 5011 .num_macs = 8192, 5012 .num_ports = 7, 5013 .num_internal_phys = 5, 5014 .num_gpio = 15, 5015 .max_vid = 4095, 5016 .port_base_addr = 0x10, 5017 .phy_base_addr = 0x0, 5018 .global1_addr = 0x1b, 5019 .global2_addr = 0x1c, 5020 .age_time_coeff = 15000, 5021 .g1_irqs = 8, 5022 .g2_irqs = 10, 5023 .atu_move_port_mask = 0xf, 5024 .pvt = true, 5025 .multi_chip = true, 5026 .tag_protocol = DSA_TAG_PROTO_EDSA, 5027 .ptp_support = true, 5028 .ops = &mv88e6320_ops, 5029 }, 5030 5031 [MV88E6321] = { 5032 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5033 .family = MV88E6XXX_FAMILY_6320, 5034 .name = "Marvell 88E6321", 5035 .num_databases = 4096, 5036 .num_macs = 8192, 5037 .num_ports = 7, 5038 .num_internal_phys = 5, 5039 .num_gpio = 15, 5040 .max_vid = 4095, 5041 .port_base_addr = 0x10, 5042 .phy_base_addr = 0x0, 5043 .global1_addr = 0x1b, 5044 .global2_addr = 0x1c, 5045 .age_time_coeff = 15000, 5046 .g1_irqs = 8, 5047 .g2_irqs = 10, 5048 .atu_move_port_mask = 0xf, 5049 .multi_chip = true, 5050 .tag_protocol = DSA_TAG_PROTO_EDSA, 5051 .ptp_support = true, 5052 .ops = &mv88e6321_ops, 5053 }, 5054 5055 [MV88E6341] = { 5056 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5057 .family = MV88E6XXX_FAMILY_6341, 5058 .name = "Marvell 88E6341", 5059 .num_databases = 4096, 5060 .num_macs = 2048, 5061 .num_internal_phys = 5, 5062 .num_ports = 6, 5063 .num_gpio = 11, 5064 .max_vid = 4095, 5065 .port_base_addr = 0x10, 5066 .phy_base_addr = 0x10, 5067 .global1_addr = 0x1b, 5068 .global2_addr = 0x1c, 5069 .age_time_coeff = 3750, 5070 .atu_move_port_mask = 0x1f, 5071 .g1_irqs = 9, 5072 .g2_irqs = 10, 5073 .pvt = true, 5074 .multi_chip = true, 5075 .tag_protocol = DSA_TAG_PROTO_EDSA, 5076 .ptp_support = true, 5077 .ops = &mv88e6341_ops, 5078 }, 5079 5080 [MV88E6350] = { 5081 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5082 .family = MV88E6XXX_FAMILY_6351, 5083 .name = "Marvell 88E6350", 5084 .num_databases = 4096, 5085 .num_macs = 8192, 5086 .num_ports = 7, 5087 .num_internal_phys = 5, 5088 .max_vid = 4095, 5089 .port_base_addr = 0x10, 5090 .phy_base_addr = 0x0, 5091 .global1_addr = 0x1b, 5092 .global2_addr = 0x1c, 5093 .age_time_coeff = 15000, 5094 .g1_irqs = 9, 5095 .g2_irqs = 10, 5096 .atu_move_port_mask = 0xf, 5097 .pvt = true, 5098 .multi_chip = true, 5099 .tag_protocol = DSA_TAG_PROTO_EDSA, 5100 .ops = &mv88e6350_ops, 5101 }, 5102 5103 [MV88E6351] = { 5104 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5105 .family = MV88E6XXX_FAMILY_6351, 5106 .name = "Marvell 88E6351", 5107 .num_databases = 4096, 5108 .num_macs = 8192, 5109 .num_ports = 7, 5110 .num_internal_phys = 5, 5111 .max_vid = 4095, 5112 .port_base_addr = 0x10, 5113 .phy_base_addr = 0x0, 5114 .global1_addr = 0x1b, 5115 .global2_addr = 0x1c, 5116 .age_time_coeff = 15000, 5117 .g1_irqs = 9, 5118 .g2_irqs = 10, 5119 .atu_move_port_mask = 0xf, 5120 .pvt = true, 5121 .multi_chip = true, 5122 .tag_protocol = DSA_TAG_PROTO_EDSA, 5123 .ops = &mv88e6351_ops, 5124 }, 5125 5126 [MV88E6352] = { 5127 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5128 .family = MV88E6XXX_FAMILY_6352, 5129 .name = "Marvell 88E6352", 5130 .num_databases = 4096, 5131 .num_macs = 8192, 5132 .num_ports = 7, 5133 .num_internal_phys = 5, 5134 .num_gpio = 15, 5135 .max_vid = 4095, 5136 .port_base_addr = 0x10, 5137 .phy_base_addr = 0x0, 5138 .global1_addr = 0x1b, 5139 .global2_addr = 0x1c, 5140 .age_time_coeff = 15000, 5141 .g1_irqs = 9, 5142 .g2_irqs = 10, 5143 .atu_move_port_mask = 0xf, 5144 .pvt = true, 5145 .multi_chip = true, 5146 .tag_protocol = DSA_TAG_PROTO_EDSA, 5147 .ptp_support = true, 5148 .ops = &mv88e6352_ops, 5149 }, 5150 [MV88E6390] = { 5151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5152 .family = MV88E6XXX_FAMILY_6390, 5153 .name = "Marvell 88E6390", 5154 .num_databases = 4096, 5155 .num_macs = 16384, 5156 .num_ports = 11, /* 10 + Z80 */ 5157 .num_internal_phys = 9, 5158 .num_gpio = 16, 5159 .max_vid = 8191, 5160 .port_base_addr = 0x0, 5161 .phy_base_addr = 0x0, 5162 .global1_addr = 0x1b, 5163 .global2_addr = 0x1c, 5164 .age_time_coeff = 3750, 5165 .g1_irqs = 9, 5166 .g2_irqs = 14, 5167 .atu_move_port_mask = 0x1f, 5168 .pvt = true, 5169 .multi_chip = true, 5170 .tag_protocol = DSA_TAG_PROTO_DSA, 5171 .ptp_support = true, 5172 .ops = &mv88e6390_ops, 5173 }, 5174 [MV88E6390X] = { 5175 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5176 .family = MV88E6XXX_FAMILY_6390, 5177 .name = "Marvell 88E6390X", 5178 .num_databases = 4096, 5179 .num_macs = 16384, 5180 .num_ports = 11, /* 10 + Z80 */ 5181 .num_internal_phys = 9, 5182 .num_gpio = 16, 5183 .max_vid = 8191, 5184 .port_base_addr = 0x0, 5185 .phy_base_addr = 0x0, 5186 .global1_addr = 0x1b, 5187 .global2_addr = 0x1c, 5188 .age_time_coeff = 3750, 5189 .g1_irqs = 9, 5190 .g2_irqs = 14, 5191 .atu_move_port_mask = 0x1f, 5192 .pvt = true, 5193 .multi_chip = true, 5194 .tag_protocol = DSA_TAG_PROTO_DSA, 5195 .ptp_support = true, 5196 .ops = &mv88e6390x_ops, 5197 }, 5198 }; 5199 5200 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5201 { 5202 int i; 5203 5204 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5205 if (mv88e6xxx_table[i].prod_num == prod_num) 5206 return &mv88e6xxx_table[i]; 5207 5208 return NULL; 5209 } 5210 5211 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5212 { 5213 const struct mv88e6xxx_info *info; 5214 unsigned int prod_num, rev; 5215 u16 id; 5216 int err; 5217 5218 mv88e6xxx_reg_lock(chip); 5219 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5220 mv88e6xxx_reg_unlock(chip); 5221 if (err) 5222 return err; 5223 5224 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5225 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5226 5227 info = mv88e6xxx_lookup_info(prod_num); 5228 if (!info) 5229 return -ENODEV; 5230 5231 /* Update the compatible info with the probed one */ 5232 chip->info = info; 5233 5234 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5235 chip->info->prod_num, chip->info->name, rev); 5236 5237 return 0; 5238 } 5239 5240 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5241 { 5242 struct mv88e6xxx_chip *chip; 5243 5244 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5245 if (!chip) 5246 return NULL; 5247 5248 chip->dev = dev; 5249 5250 mutex_init(&chip->reg_lock); 5251 INIT_LIST_HEAD(&chip->mdios); 5252 idr_init(&chip->policies); 5253 5254 return chip; 5255 } 5256 5257 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5258 int port, 5259 enum dsa_tag_protocol m) 5260 { 5261 struct mv88e6xxx_chip *chip = ds->priv; 5262 5263 return chip->info->tag_protocol; 5264 } 5265 5266 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5267 const struct switchdev_obj_port_mdb *mdb) 5268 { 5269 struct mv88e6xxx_chip *chip = ds->priv; 5270 int err; 5271 5272 mv88e6xxx_reg_lock(chip); 5273 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5274 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5275 mv88e6xxx_reg_unlock(chip); 5276 5277 return err; 5278 } 5279 5280 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5281 const struct switchdev_obj_port_mdb *mdb) 5282 { 5283 struct mv88e6xxx_chip *chip = ds->priv; 5284 int err; 5285 5286 mv88e6xxx_reg_lock(chip); 5287 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5288 mv88e6xxx_reg_unlock(chip); 5289 5290 return err; 5291 } 5292 5293 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5294 struct dsa_mall_mirror_tc_entry *mirror, 5295 bool ingress) 5296 { 5297 enum mv88e6xxx_egress_direction direction = ingress ? 5298 MV88E6XXX_EGRESS_DIR_INGRESS : 5299 MV88E6XXX_EGRESS_DIR_EGRESS; 5300 struct mv88e6xxx_chip *chip = ds->priv; 5301 bool other_mirrors = false; 5302 int i; 5303 int err; 5304 5305 if (!chip->info->ops->set_egress_port) 5306 return -EOPNOTSUPP; 5307 5308 mutex_lock(&chip->reg_lock); 5309 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5310 mirror->to_local_port) { 5311 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5312 other_mirrors |= ingress ? 5313 chip->ports[i].mirror_ingress : 5314 chip->ports[i].mirror_egress; 5315 5316 /* Can't change egress port when other mirror is active */ 5317 if (other_mirrors) { 5318 err = -EBUSY; 5319 goto out; 5320 } 5321 5322 err = chip->info->ops->set_egress_port(chip, 5323 direction, 5324 mirror->to_local_port); 5325 if (err) 5326 goto out; 5327 } 5328 5329 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5330 out: 5331 mutex_unlock(&chip->reg_lock); 5332 5333 return err; 5334 } 5335 5336 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5337 struct dsa_mall_mirror_tc_entry *mirror) 5338 { 5339 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5340 MV88E6XXX_EGRESS_DIR_INGRESS : 5341 MV88E6XXX_EGRESS_DIR_EGRESS; 5342 struct mv88e6xxx_chip *chip = ds->priv; 5343 bool other_mirrors = false; 5344 int i; 5345 5346 mutex_lock(&chip->reg_lock); 5347 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5348 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5349 5350 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5351 other_mirrors |= mirror->ingress ? 5352 chip->ports[i].mirror_ingress : 5353 chip->ports[i].mirror_egress; 5354 5355 /* Reset egress port when no other mirror is active */ 5356 if (!other_mirrors) { 5357 if (chip->info->ops->set_egress_port(chip, 5358 direction, 5359 dsa_upstream_port(ds, 5360 port))) 5361 dev_err(ds->dev, "failed to set egress port\n"); 5362 } 5363 5364 mutex_unlock(&chip->reg_lock); 5365 } 5366 5367 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5368 bool unicast, bool multicast) 5369 { 5370 struct mv88e6xxx_chip *chip = ds->priv; 5371 int err = -EOPNOTSUPP; 5372 5373 mv88e6xxx_reg_lock(chip); 5374 if (chip->info->ops->port_set_egress_floods) 5375 err = chip->info->ops->port_set_egress_floods(chip, port, 5376 unicast, 5377 multicast); 5378 mv88e6xxx_reg_unlock(chip); 5379 5380 return err; 5381 } 5382 5383 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5384 struct net_device *lag, 5385 struct netdev_lag_upper_info *info) 5386 { 5387 struct mv88e6xxx_chip *chip = ds->priv; 5388 struct dsa_port *dp; 5389 int id, members = 0; 5390 5391 if (!mv88e6xxx_has_lag(chip)) 5392 return false; 5393 5394 id = dsa_lag_id(ds->dst, lag); 5395 if (id < 0 || id >= ds->num_lag_ids) 5396 return false; 5397 5398 dsa_lag_foreach_port(dp, ds->dst, lag) 5399 /* Includes the port joining the LAG */ 5400 members++; 5401 5402 if (members > 8) 5403 return false; 5404 5405 /* We could potentially relax this to include active 5406 * backup in the future. 5407 */ 5408 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5409 return false; 5410 5411 /* Ideally we would also validate that the hash type matches 5412 * the hardware. Alas, this is always set to unknown on team 5413 * interfaces. 5414 */ 5415 return true; 5416 } 5417 5418 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5419 { 5420 struct mv88e6xxx_chip *chip = ds->priv; 5421 struct dsa_port *dp; 5422 u16 map = 0; 5423 int id; 5424 5425 id = dsa_lag_id(ds->dst, lag); 5426 5427 /* Build the map of all ports to distribute flows destined for 5428 * this LAG. This can be either a local user port, or a DSA 5429 * port if the LAG port is on a remote chip. 5430 */ 5431 dsa_lag_foreach_port(dp, ds->dst, lag) 5432 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5433 5434 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 5435 } 5436 5437 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 5438 /* Row number corresponds to the number of active members in a 5439 * LAG. Each column states which of the eight hash buckets are 5440 * mapped to the column:th port in the LAG. 5441 * 5442 * Example: In a LAG with three active ports, the second port 5443 * ([2][1]) would be selected for traffic mapped to buckets 5444 * 3,4,5 (0x38). 5445 */ 5446 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 5447 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 5448 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 5449 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 5450 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 5451 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 5452 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 5453 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 5454 }; 5455 5456 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 5457 int num_tx, int nth) 5458 { 5459 u8 active = 0; 5460 int i; 5461 5462 num_tx = num_tx <= 8 ? num_tx : 8; 5463 if (nth < num_tx) 5464 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 5465 5466 for (i = 0; i < 8; i++) { 5467 if (BIT(i) & active) 5468 mask[i] |= BIT(port); 5469 } 5470 } 5471 5472 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 5473 { 5474 struct mv88e6xxx_chip *chip = ds->priv; 5475 unsigned int id, num_tx; 5476 struct net_device *lag; 5477 struct dsa_port *dp; 5478 int i, err, nth; 5479 u16 mask[8]; 5480 u16 ivec; 5481 5482 /* Assume no port is a member of any LAG. */ 5483 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 5484 5485 /* Disable all masks for ports that _are_ members of a LAG. */ 5486 list_for_each_entry(dp, &ds->dst->ports, list) { 5487 if (!dp->lag_dev || dp->ds != ds) 5488 continue; 5489 5490 ivec &= ~BIT(dp->index); 5491 } 5492 5493 for (i = 0; i < 8; i++) 5494 mask[i] = ivec; 5495 5496 /* Enable the correct subset of masks for all LAG ports that 5497 * are in the Tx set. 5498 */ 5499 dsa_lags_foreach_id(id, ds->dst) { 5500 lag = dsa_lag_dev(ds->dst, id); 5501 if (!lag) 5502 continue; 5503 5504 num_tx = 0; 5505 dsa_lag_foreach_port(dp, ds->dst, lag) { 5506 if (dp->lag_tx_enabled) 5507 num_tx++; 5508 } 5509 5510 if (!num_tx) 5511 continue; 5512 5513 nth = 0; 5514 dsa_lag_foreach_port(dp, ds->dst, lag) { 5515 if (!dp->lag_tx_enabled) 5516 continue; 5517 5518 if (dp->ds == ds) 5519 mv88e6xxx_lag_set_port_mask(mask, dp->index, 5520 num_tx, nth); 5521 5522 nth++; 5523 } 5524 } 5525 5526 for (i = 0; i < 8; i++) { 5527 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 5528 if (err) 5529 return err; 5530 } 5531 5532 return 0; 5533 } 5534 5535 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 5536 struct net_device *lag) 5537 { 5538 int err; 5539 5540 err = mv88e6xxx_lag_sync_masks(ds); 5541 5542 if (!err) 5543 err = mv88e6xxx_lag_sync_map(ds, lag); 5544 5545 return err; 5546 } 5547 5548 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 5549 { 5550 struct mv88e6xxx_chip *chip = ds->priv; 5551 int err; 5552 5553 mv88e6xxx_reg_lock(chip); 5554 err = mv88e6xxx_lag_sync_masks(ds); 5555 mv88e6xxx_reg_unlock(chip); 5556 return err; 5557 } 5558 5559 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 5560 struct net_device *lag, 5561 struct netdev_lag_upper_info *info) 5562 { 5563 struct mv88e6xxx_chip *chip = ds->priv; 5564 int err, id; 5565 5566 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 5567 return -EOPNOTSUPP; 5568 5569 id = dsa_lag_id(ds->dst, lag); 5570 5571 mv88e6xxx_reg_lock(chip); 5572 5573 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 5574 if (err) 5575 goto err_unlock; 5576 5577 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 5578 if (err) 5579 goto err_clear_trunk; 5580 5581 mv88e6xxx_reg_unlock(chip); 5582 return 0; 5583 5584 err_clear_trunk: 5585 mv88e6xxx_port_set_trunk(chip, port, false, 0); 5586 err_unlock: 5587 mv88e6xxx_reg_unlock(chip); 5588 return err; 5589 } 5590 5591 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 5592 struct net_device *lag) 5593 { 5594 struct mv88e6xxx_chip *chip = ds->priv; 5595 int err_sync, err_trunk; 5596 5597 mv88e6xxx_reg_lock(chip); 5598 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 5599 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 5600 mv88e6xxx_reg_unlock(chip); 5601 return err_sync ? : err_trunk; 5602 } 5603 5604 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 5605 int port) 5606 { 5607 struct mv88e6xxx_chip *chip = ds->priv; 5608 int err; 5609 5610 mv88e6xxx_reg_lock(chip); 5611 err = mv88e6xxx_lag_sync_masks(ds); 5612 mv88e6xxx_reg_unlock(chip); 5613 return err; 5614 } 5615 5616 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 5617 int port, struct net_device *lag, 5618 struct netdev_lag_upper_info *info) 5619 { 5620 struct mv88e6xxx_chip *chip = ds->priv; 5621 int err; 5622 5623 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 5624 return -EOPNOTSUPP; 5625 5626 mv88e6xxx_reg_lock(chip); 5627 5628 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 5629 if (err) 5630 goto unlock; 5631 5632 err = mv88e6xxx_pvt_map(chip, sw_index, port); 5633 5634 unlock: 5635 mv88e6xxx_reg_unlock(chip); 5636 return err; 5637 } 5638 5639 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 5640 int port, struct net_device *lag) 5641 { 5642 struct mv88e6xxx_chip *chip = ds->priv; 5643 int err_sync, err_pvt; 5644 5645 mv88e6xxx_reg_lock(chip); 5646 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 5647 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 5648 mv88e6xxx_reg_unlock(chip); 5649 return err_sync ? : err_pvt; 5650 } 5651 5652 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5653 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5654 .setup = mv88e6xxx_setup, 5655 .teardown = mv88e6xxx_teardown, 5656 .phylink_validate = mv88e6xxx_validate, 5657 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5658 .phylink_mac_config = mv88e6xxx_mac_config, 5659 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5660 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5661 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5662 .get_strings = mv88e6xxx_get_strings, 5663 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5664 .get_sset_count = mv88e6xxx_get_sset_count, 5665 .port_enable = mv88e6xxx_port_enable, 5666 .port_disable = mv88e6xxx_port_disable, 5667 .port_max_mtu = mv88e6xxx_get_max_mtu, 5668 .port_change_mtu = mv88e6xxx_change_mtu, 5669 .get_mac_eee = mv88e6xxx_get_mac_eee, 5670 .set_mac_eee = mv88e6xxx_set_mac_eee, 5671 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5672 .get_eeprom = mv88e6xxx_get_eeprom, 5673 .set_eeprom = mv88e6xxx_set_eeprom, 5674 .get_regs_len = mv88e6xxx_get_regs_len, 5675 .get_regs = mv88e6xxx_get_regs, 5676 .get_rxnfc = mv88e6xxx_get_rxnfc, 5677 .set_rxnfc = mv88e6xxx_set_rxnfc, 5678 .set_ageing_time = mv88e6xxx_set_ageing_time, 5679 .port_bridge_join = mv88e6xxx_port_bridge_join, 5680 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5681 .port_egress_floods = mv88e6xxx_port_egress_floods, 5682 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5683 .port_fast_age = mv88e6xxx_port_fast_age, 5684 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5685 .port_vlan_add = mv88e6xxx_port_vlan_add, 5686 .port_vlan_del = mv88e6xxx_port_vlan_del, 5687 .port_fdb_add = mv88e6xxx_port_fdb_add, 5688 .port_fdb_del = mv88e6xxx_port_fdb_del, 5689 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5690 .port_mdb_add = mv88e6xxx_port_mdb_add, 5691 .port_mdb_del = mv88e6xxx_port_mdb_del, 5692 .port_mirror_add = mv88e6xxx_port_mirror_add, 5693 .port_mirror_del = mv88e6xxx_port_mirror_del, 5694 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5695 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5696 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5697 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5698 .port_txtstamp = mv88e6xxx_port_txtstamp, 5699 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5700 .get_ts_info = mv88e6xxx_get_ts_info, 5701 .devlink_param_get = mv88e6xxx_devlink_param_get, 5702 .devlink_param_set = mv88e6xxx_devlink_param_set, 5703 .devlink_info_get = mv88e6xxx_devlink_info_get, 5704 .port_lag_change = mv88e6xxx_port_lag_change, 5705 .port_lag_join = mv88e6xxx_port_lag_join, 5706 .port_lag_leave = mv88e6xxx_port_lag_leave, 5707 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 5708 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 5709 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 5710 }; 5711 5712 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5713 { 5714 struct device *dev = chip->dev; 5715 struct dsa_switch *ds; 5716 5717 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5718 if (!ds) 5719 return -ENOMEM; 5720 5721 ds->dev = dev; 5722 ds->num_ports = mv88e6xxx_num_ports(chip); 5723 ds->priv = chip; 5724 ds->dev = dev; 5725 ds->ops = &mv88e6xxx_switch_ops; 5726 ds->ageing_time_min = chip->info->age_time_coeff; 5727 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5728 5729 /* Some chips support up to 32, but that requires enabling the 5730 * 5-bit port mode, which we do not support. 640k^W16 ought to 5731 * be enough for anyone. 5732 */ 5733 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 5734 5735 dev_set_drvdata(dev, ds); 5736 5737 return dsa_register_switch(ds); 5738 } 5739 5740 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5741 { 5742 dsa_unregister_switch(chip->ds); 5743 } 5744 5745 static const void *pdata_device_get_match_data(struct device *dev) 5746 { 5747 const struct of_device_id *matches = dev->driver->of_match_table; 5748 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5749 5750 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5751 matches++) { 5752 if (!strcmp(pdata->compatible, matches->compatible)) 5753 return matches->data; 5754 } 5755 return NULL; 5756 } 5757 5758 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5759 * would be lost after a power cycle so prevent it to be suspended. 5760 */ 5761 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5762 { 5763 return -EOPNOTSUPP; 5764 } 5765 5766 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5767 { 5768 return 0; 5769 } 5770 5771 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5772 5773 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5774 { 5775 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5776 const struct mv88e6xxx_info *compat_info = NULL; 5777 struct device *dev = &mdiodev->dev; 5778 struct device_node *np = dev->of_node; 5779 struct mv88e6xxx_chip *chip; 5780 int port; 5781 int err; 5782 5783 if (!np && !pdata) 5784 return -EINVAL; 5785 5786 if (np) 5787 compat_info = of_device_get_match_data(dev); 5788 5789 if (pdata) { 5790 compat_info = pdata_device_get_match_data(dev); 5791 5792 if (!pdata->netdev) 5793 return -EINVAL; 5794 5795 for (port = 0; port < DSA_MAX_PORTS; port++) { 5796 if (!(pdata->enabled_ports & (1 << port))) 5797 continue; 5798 if (strcmp(pdata->cd.port_names[port], "cpu")) 5799 continue; 5800 pdata->cd.netdev[port] = &pdata->netdev->dev; 5801 break; 5802 } 5803 } 5804 5805 if (!compat_info) 5806 return -EINVAL; 5807 5808 chip = mv88e6xxx_alloc_chip(dev); 5809 if (!chip) { 5810 err = -ENOMEM; 5811 goto out; 5812 } 5813 5814 chip->info = compat_info; 5815 5816 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5817 if (err) 5818 goto out; 5819 5820 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5821 if (IS_ERR(chip->reset)) { 5822 err = PTR_ERR(chip->reset); 5823 goto out; 5824 } 5825 if (chip->reset) 5826 usleep_range(1000, 2000); 5827 5828 err = mv88e6xxx_detect(chip); 5829 if (err) 5830 goto out; 5831 5832 mv88e6xxx_phy_init(chip); 5833 5834 if (chip->info->ops->get_eeprom) { 5835 if (np) 5836 of_property_read_u32(np, "eeprom-length", 5837 &chip->eeprom_len); 5838 else 5839 chip->eeprom_len = pdata->eeprom_len; 5840 } 5841 5842 mv88e6xxx_reg_lock(chip); 5843 err = mv88e6xxx_switch_reset(chip); 5844 mv88e6xxx_reg_unlock(chip); 5845 if (err) 5846 goto out; 5847 5848 if (np) { 5849 chip->irq = of_irq_get(np, 0); 5850 if (chip->irq == -EPROBE_DEFER) { 5851 err = chip->irq; 5852 goto out; 5853 } 5854 } 5855 5856 if (pdata) 5857 chip->irq = pdata->irq; 5858 5859 /* Has to be performed before the MDIO bus is created, because 5860 * the PHYs will link their interrupts to these interrupt 5861 * controllers 5862 */ 5863 mv88e6xxx_reg_lock(chip); 5864 if (chip->irq > 0) 5865 err = mv88e6xxx_g1_irq_setup(chip); 5866 else 5867 err = mv88e6xxx_irq_poll_setup(chip); 5868 mv88e6xxx_reg_unlock(chip); 5869 5870 if (err) 5871 goto out; 5872 5873 if (chip->info->g2_irqs > 0) { 5874 err = mv88e6xxx_g2_irq_setup(chip); 5875 if (err) 5876 goto out_g1_irq; 5877 } 5878 5879 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5880 if (err) 5881 goto out_g2_irq; 5882 5883 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5884 if (err) 5885 goto out_g1_atu_prob_irq; 5886 5887 err = mv88e6xxx_mdios_register(chip, np); 5888 if (err) 5889 goto out_g1_vtu_prob_irq; 5890 5891 err = mv88e6xxx_register_switch(chip); 5892 if (err) 5893 goto out_mdio; 5894 5895 return 0; 5896 5897 out_mdio: 5898 mv88e6xxx_mdios_unregister(chip); 5899 out_g1_vtu_prob_irq: 5900 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5901 out_g1_atu_prob_irq: 5902 mv88e6xxx_g1_atu_prob_irq_free(chip); 5903 out_g2_irq: 5904 if (chip->info->g2_irqs > 0) 5905 mv88e6xxx_g2_irq_free(chip); 5906 out_g1_irq: 5907 if (chip->irq > 0) 5908 mv88e6xxx_g1_irq_free(chip); 5909 else 5910 mv88e6xxx_irq_poll_free(chip); 5911 out: 5912 if (pdata) 5913 dev_put(pdata->netdev); 5914 5915 return err; 5916 } 5917 5918 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5919 { 5920 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5921 struct mv88e6xxx_chip *chip = ds->priv; 5922 5923 if (chip->info->ptp_support) { 5924 mv88e6xxx_hwtstamp_free(chip); 5925 mv88e6xxx_ptp_free(chip); 5926 } 5927 5928 mv88e6xxx_phy_destroy(chip); 5929 mv88e6xxx_unregister_switch(chip); 5930 mv88e6xxx_mdios_unregister(chip); 5931 5932 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5933 mv88e6xxx_g1_atu_prob_irq_free(chip); 5934 5935 if (chip->info->g2_irqs > 0) 5936 mv88e6xxx_g2_irq_free(chip); 5937 5938 if (chip->irq > 0) 5939 mv88e6xxx_g1_irq_free(chip); 5940 else 5941 mv88e6xxx_irq_poll_free(chip); 5942 } 5943 5944 static const struct of_device_id mv88e6xxx_of_match[] = { 5945 { 5946 .compatible = "marvell,mv88e6085", 5947 .data = &mv88e6xxx_table[MV88E6085], 5948 }, 5949 { 5950 .compatible = "marvell,mv88e6190", 5951 .data = &mv88e6xxx_table[MV88E6190], 5952 }, 5953 { 5954 .compatible = "marvell,mv88e6250", 5955 .data = &mv88e6xxx_table[MV88E6250], 5956 }, 5957 { /* sentinel */ }, 5958 }; 5959 5960 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5961 5962 static struct mdio_driver mv88e6xxx_driver = { 5963 .probe = mv88e6xxx_probe, 5964 .remove = mv88e6xxx_remove, 5965 .mdiodrv.driver = { 5966 .name = "mv88e6085", 5967 .of_match_table = mv88e6xxx_of_match, 5968 .pm = &mv88e6xxx_pm_ops, 5969 }, 5970 }; 5971 5972 mdio_module_driver(mv88e6xxx_driver); 5973 5974 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5975 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5976 MODULE_LICENSE("GPL"); 5977