1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 snprintf(chip->irq_name, sizeof(chip->irq_name), 344 "mv88e6xxx-%s", dev_name(chip->dev)); 345 346 mv88e6xxx_reg_unlock(chip); 347 err = request_threaded_irq(chip->irq, NULL, 348 mv88e6xxx_g1_irq_thread_fn, 349 IRQF_ONESHOT | IRQF_SHARED, 350 chip->irq_name, chip); 351 mv88e6xxx_reg_lock(chip); 352 if (err) 353 mv88e6xxx_g1_irq_free_common(chip); 354 355 return err; 356 } 357 358 static void mv88e6xxx_irq_poll(struct kthread_work *work) 359 { 360 struct mv88e6xxx_chip *chip = container_of(work, 361 struct mv88e6xxx_chip, 362 irq_poll_work.work); 363 mv88e6xxx_g1_irq_thread_work(chip); 364 365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 366 msecs_to_jiffies(100)); 367 } 368 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 370 { 371 int err; 372 373 err = mv88e6xxx_g1_irq_setup_common(chip); 374 if (err) 375 return err; 376 377 kthread_init_delayed_work(&chip->irq_poll_work, 378 mv88e6xxx_irq_poll); 379 380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 381 if (IS_ERR(chip->kworker)) 382 return PTR_ERR(chip->kworker); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 387 return 0; 388 } 389 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 391 { 392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 393 kthread_destroy_worker(chip->kworker); 394 395 mv88e6xxx_reg_lock(chip); 396 mv88e6xxx_g1_irq_free_common(chip); 397 mv88e6xxx_reg_unlock(chip); 398 } 399 400 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 401 int port, phy_interface_t interface) 402 { 403 int err; 404 405 if (chip->info->ops->port_set_rgmii_delay) { 406 err = chip->info->ops->port_set_rgmii_delay(chip, port, 407 interface); 408 if (err && err != -EOPNOTSUPP) 409 return err; 410 } 411 412 if (chip->info->ops->port_set_cmode) { 413 err = chip->info->ops->port_set_cmode(chip, port, 414 interface); 415 if (err && err != -EOPNOTSUPP) 416 return err; 417 } 418 419 return 0; 420 } 421 422 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 423 int link, int speed, int duplex, int pause, 424 phy_interface_t mode) 425 { 426 int err; 427 428 if (!chip->info->ops->port_set_link) 429 return 0; 430 431 /* Port's MAC control must not be changed unless the link is down */ 432 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 433 if (err) 434 return err; 435 436 if (chip->info->ops->port_set_speed_duplex) { 437 err = chip->info->ops->port_set_speed_duplex(chip, port, 438 speed, duplex); 439 if (err && err != -EOPNOTSUPP) 440 goto restore_link; 441 } 442 443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 444 mode = chip->info->ops->port_max_speed_mode(port); 445 446 if (chip->info->ops->port_set_pause) { 447 err = chip->info->ops->port_set_pause(chip, port, pause); 448 if (err) 449 goto restore_link; 450 } 451 452 err = mv88e6xxx_port_config_interface(chip, port, mode); 453 restore_link: 454 if (chip->info->ops->port_set_link(chip, port, link)) 455 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 456 457 return err; 458 } 459 460 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 461 { 462 struct mv88e6xxx_chip *chip = ds->priv; 463 464 return port < chip->info->num_internal_phys; 465 } 466 467 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 468 { 469 u16 reg; 470 int err; 471 472 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 473 if (err) { 474 dev_err(chip->dev, 475 "p%d: %s: failed to read port status\n", 476 port, __func__); 477 return err; 478 } 479 480 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 481 } 482 483 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 484 struct phylink_link_state *state) 485 { 486 struct mv88e6xxx_chip *chip = ds->priv; 487 u8 lane; 488 int err; 489 490 mv88e6xxx_reg_lock(chip); 491 lane = mv88e6xxx_serdes_get_lane(chip, port); 492 if (lane && chip->info->ops->serdes_pcs_get_state) 493 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 494 state); 495 else 496 err = -EOPNOTSUPP; 497 mv88e6xxx_reg_unlock(chip); 498 499 return err; 500 } 501 502 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 503 unsigned int mode, 504 phy_interface_t interface, 505 const unsigned long *advertise) 506 { 507 const struct mv88e6xxx_ops *ops = chip->info->ops; 508 u8 lane; 509 510 if (ops->serdes_pcs_config) { 511 lane = mv88e6xxx_serdes_get_lane(chip, port); 512 if (lane) 513 return ops->serdes_pcs_config(chip, port, lane, mode, 514 interface, advertise); 515 } 516 517 return 0; 518 } 519 520 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 521 { 522 struct mv88e6xxx_chip *chip = ds->priv; 523 const struct mv88e6xxx_ops *ops; 524 int err = 0; 525 u8 lane; 526 527 ops = chip->info->ops; 528 529 if (ops->serdes_pcs_an_restart) { 530 mv88e6xxx_reg_lock(chip); 531 lane = mv88e6xxx_serdes_get_lane(chip, port); 532 if (lane) 533 err = ops->serdes_pcs_an_restart(chip, port, lane); 534 mv88e6xxx_reg_unlock(chip); 535 536 if (err) 537 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 538 } 539 } 540 541 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 542 unsigned int mode, 543 int speed, int duplex) 544 { 545 const struct mv88e6xxx_ops *ops = chip->info->ops; 546 u8 lane; 547 548 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 549 lane = mv88e6xxx_serdes_get_lane(chip, port); 550 if (lane) 551 return ops->serdes_pcs_link_up(chip, port, lane, 552 speed, duplex); 553 } 554 555 return 0; 556 } 557 558 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 559 unsigned long *mask, 560 struct phylink_link_state *state) 561 { 562 if (!phy_interface_mode_is_8023z(state->interface)) { 563 /* 10M and 100M are only supported in non-802.3z mode */ 564 phylink_set(mask, 10baseT_Half); 565 phylink_set(mask, 10baseT_Full); 566 phylink_set(mask, 100baseT_Half); 567 phylink_set(mask, 100baseT_Full); 568 } 569 } 570 571 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 572 unsigned long *mask, 573 struct phylink_link_state *state) 574 { 575 /* FIXME: if the port is in 1000Base-X mode, then it only supports 576 * 1000M FD speeds. In this case, CMODE will indicate 5. 577 */ 578 phylink_set(mask, 1000baseT_Full); 579 phylink_set(mask, 1000baseX_Full); 580 581 mv88e6065_phylink_validate(chip, port, mask, state); 582 } 583 584 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 585 unsigned long *mask, 586 struct phylink_link_state *state) 587 { 588 if (port >= 5) 589 phylink_set(mask, 2500baseX_Full); 590 591 /* No ethtool bits for 200Mbps */ 592 phylink_set(mask, 1000baseT_Full); 593 phylink_set(mask, 1000baseX_Full); 594 595 mv88e6065_phylink_validate(chip, port, mask, state); 596 } 597 598 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 599 unsigned long *mask, 600 struct phylink_link_state *state) 601 { 602 /* No ethtool bits for 200Mbps */ 603 phylink_set(mask, 1000baseT_Full); 604 phylink_set(mask, 1000baseX_Full); 605 606 mv88e6065_phylink_validate(chip, port, mask, state); 607 } 608 609 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 610 unsigned long *mask, 611 struct phylink_link_state *state) 612 { 613 if (port >= 9) { 614 phylink_set(mask, 2500baseX_Full); 615 phylink_set(mask, 2500baseT_Full); 616 } 617 618 /* No ethtool bits for 200Mbps */ 619 phylink_set(mask, 1000baseT_Full); 620 phylink_set(mask, 1000baseX_Full); 621 622 mv88e6065_phylink_validate(chip, port, mask, state); 623 } 624 625 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 626 unsigned long *mask, 627 struct phylink_link_state *state) 628 { 629 if (port >= 9) { 630 phylink_set(mask, 10000baseT_Full); 631 phylink_set(mask, 10000baseKR_Full); 632 } 633 634 mv88e6390_phylink_validate(chip, port, mask, state); 635 } 636 637 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 638 unsigned long *supported, 639 struct phylink_link_state *state) 640 { 641 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 642 struct mv88e6xxx_chip *chip = ds->priv; 643 644 /* Allow all the expected bits */ 645 phylink_set(mask, Autoneg); 646 phylink_set(mask, Pause); 647 phylink_set_port_modes(mask); 648 649 if (chip->info->ops->phylink_validate) 650 chip->info->ops->phylink_validate(chip, port, mask, state); 651 652 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 653 bitmap_and(state->advertising, state->advertising, mask, 654 __ETHTOOL_LINK_MODE_MASK_NBITS); 655 656 /* We can only operate at 2500BaseX or 1000BaseX. If requested 657 * to advertise both, only report advertising at 2500BaseX. 658 */ 659 phylink_helper_basex_speed(state); 660 } 661 662 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 663 unsigned int mode, 664 const struct phylink_link_state *state) 665 { 666 struct mv88e6xxx_chip *chip = ds->priv; 667 int err; 668 669 /* FIXME: is this the correct test? If we're in fixed mode on an 670 * internal port, why should we process this any different from 671 * PHY mode? On the other hand, the port may be automedia between 672 * an internal PHY and the serdes... 673 */ 674 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 675 return; 676 677 mv88e6xxx_reg_lock(chip); 678 /* FIXME: should we force the link down here - but if we do, how 679 * do we restore the link force/unforce state? The driver layering 680 * gets in the way. 681 */ 682 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 683 if (err && err != -EOPNOTSUPP) 684 goto err_unlock; 685 686 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 687 state->advertising); 688 /* FIXME: we should restart negotiation if something changed - which 689 * is something we get if we convert to using phylinks PCS operations. 690 */ 691 if (err > 0) 692 err = 0; 693 694 err_unlock: 695 mv88e6xxx_reg_unlock(chip); 696 697 if (err && err != -EOPNOTSUPP) 698 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 699 } 700 701 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 702 unsigned int mode, 703 phy_interface_t interface) 704 { 705 struct mv88e6xxx_chip *chip = ds->priv; 706 const struct mv88e6xxx_ops *ops; 707 int err = 0; 708 709 ops = chip->info->ops; 710 711 mv88e6xxx_reg_lock(chip); 712 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 713 mode == MLO_AN_FIXED) && ops->port_set_link) 714 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN); 715 mv88e6xxx_reg_unlock(chip); 716 717 if (err) 718 dev_err(chip->dev, 719 "p%d: failed to force MAC link down\n", port); 720 } 721 722 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 723 unsigned int mode, phy_interface_t interface, 724 struct phy_device *phydev, 725 int speed, int duplex, 726 bool tx_pause, bool rx_pause) 727 { 728 struct mv88e6xxx_chip *chip = ds->priv; 729 const struct mv88e6xxx_ops *ops; 730 int err = 0; 731 732 ops = chip->info->ops; 733 734 mv88e6xxx_reg_lock(chip); 735 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 736 /* FIXME: for an automedia port, should we force the link 737 * down here - what if the link comes up due to "other" media 738 * while we're bringing the port up, how is the exclusivity 739 * handled in the Marvell hardware? E.g. port 2 on 88E6390 740 * shared between internal PHY and Serdes. 741 */ 742 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 743 duplex); 744 if (err) 745 goto error; 746 747 if (ops->port_set_speed_duplex) { 748 err = ops->port_set_speed_duplex(chip, port, 749 speed, duplex); 750 if (err && err != -EOPNOTSUPP) 751 goto error; 752 } 753 754 if (ops->port_set_link) 755 err = ops->port_set_link(chip, port, LINK_FORCED_UP); 756 } 757 error: 758 mv88e6xxx_reg_unlock(chip); 759 760 if (err && err != -EOPNOTSUPP) 761 dev_err(ds->dev, 762 "p%d: failed to configure MAC link up\n", port); 763 } 764 765 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 766 { 767 if (!chip->info->ops->stats_snapshot) 768 return -EOPNOTSUPP; 769 770 return chip->info->ops->stats_snapshot(chip, port); 771 } 772 773 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 774 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 775 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 776 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 777 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 778 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 779 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 780 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 781 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 782 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 783 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 784 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 785 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 786 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 787 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 788 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 789 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 790 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 791 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 792 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 793 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 794 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 795 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 796 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 797 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 798 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 799 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 800 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 801 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 802 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 803 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 804 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 805 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 806 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 807 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 808 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 809 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 810 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 811 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 812 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 813 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 814 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 815 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 816 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 817 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 818 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 819 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 820 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 821 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 822 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 823 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 824 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 825 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 826 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 827 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 828 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 829 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 830 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 831 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 832 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 833 }; 834 835 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 836 struct mv88e6xxx_hw_stat *s, 837 int port, u16 bank1_select, 838 u16 histogram) 839 { 840 u32 low; 841 u32 high = 0; 842 u16 reg = 0; 843 int err; 844 u64 value; 845 846 switch (s->type) { 847 case STATS_TYPE_PORT: 848 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 849 if (err) 850 return U64_MAX; 851 852 low = reg; 853 if (s->size == 4) { 854 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 855 if (err) 856 return U64_MAX; 857 low |= ((u32)reg) << 16; 858 } 859 break; 860 case STATS_TYPE_BANK1: 861 reg = bank1_select; 862 /* fall through */ 863 case STATS_TYPE_BANK0: 864 reg |= s->reg | histogram; 865 mv88e6xxx_g1_stats_read(chip, reg, &low); 866 if (s->size == 8) 867 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 868 break; 869 default: 870 return U64_MAX; 871 } 872 value = (((u64)high) << 32) | low; 873 return value; 874 } 875 876 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 877 uint8_t *data, int types) 878 { 879 struct mv88e6xxx_hw_stat *stat; 880 int i, j; 881 882 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 883 stat = &mv88e6xxx_hw_stats[i]; 884 if (stat->type & types) { 885 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 886 ETH_GSTRING_LEN); 887 j++; 888 } 889 } 890 891 return j; 892 } 893 894 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 895 uint8_t *data) 896 { 897 return mv88e6xxx_stats_get_strings(chip, data, 898 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 899 } 900 901 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 902 uint8_t *data) 903 { 904 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 905 } 906 907 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 908 uint8_t *data) 909 { 910 return mv88e6xxx_stats_get_strings(chip, data, 911 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 912 } 913 914 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 915 "atu_member_violation", 916 "atu_miss_violation", 917 "atu_full_violation", 918 "vtu_member_violation", 919 "vtu_miss_violation", 920 }; 921 922 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 923 { 924 unsigned int i; 925 926 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 927 strlcpy(data + i * ETH_GSTRING_LEN, 928 mv88e6xxx_atu_vtu_stats_strings[i], 929 ETH_GSTRING_LEN); 930 } 931 932 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 933 u32 stringset, uint8_t *data) 934 { 935 struct mv88e6xxx_chip *chip = ds->priv; 936 int count = 0; 937 938 if (stringset != ETH_SS_STATS) 939 return; 940 941 mv88e6xxx_reg_lock(chip); 942 943 if (chip->info->ops->stats_get_strings) 944 count = chip->info->ops->stats_get_strings(chip, data); 945 946 if (chip->info->ops->serdes_get_strings) { 947 data += count * ETH_GSTRING_LEN; 948 count = chip->info->ops->serdes_get_strings(chip, port, data); 949 } 950 951 data += count * ETH_GSTRING_LEN; 952 mv88e6xxx_atu_vtu_get_strings(data); 953 954 mv88e6xxx_reg_unlock(chip); 955 } 956 957 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 958 int types) 959 { 960 struct mv88e6xxx_hw_stat *stat; 961 int i, j; 962 963 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 964 stat = &mv88e6xxx_hw_stats[i]; 965 if (stat->type & types) 966 j++; 967 } 968 return j; 969 } 970 971 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 972 { 973 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 974 STATS_TYPE_PORT); 975 } 976 977 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 978 { 979 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 980 } 981 982 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 983 { 984 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 985 STATS_TYPE_BANK1); 986 } 987 988 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 989 { 990 struct mv88e6xxx_chip *chip = ds->priv; 991 int serdes_count = 0; 992 int count = 0; 993 994 if (sset != ETH_SS_STATS) 995 return 0; 996 997 mv88e6xxx_reg_lock(chip); 998 if (chip->info->ops->stats_get_sset_count) 999 count = chip->info->ops->stats_get_sset_count(chip); 1000 if (count < 0) 1001 goto out; 1002 1003 if (chip->info->ops->serdes_get_sset_count) 1004 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1005 port); 1006 if (serdes_count < 0) { 1007 count = serdes_count; 1008 goto out; 1009 } 1010 count += serdes_count; 1011 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1012 1013 out: 1014 mv88e6xxx_reg_unlock(chip); 1015 1016 return count; 1017 } 1018 1019 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1020 uint64_t *data, int types, 1021 u16 bank1_select, u16 histogram) 1022 { 1023 struct mv88e6xxx_hw_stat *stat; 1024 int i, j; 1025 1026 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1027 stat = &mv88e6xxx_hw_stats[i]; 1028 if (stat->type & types) { 1029 mv88e6xxx_reg_lock(chip); 1030 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1031 bank1_select, 1032 histogram); 1033 mv88e6xxx_reg_unlock(chip); 1034 1035 j++; 1036 } 1037 } 1038 return j; 1039 } 1040 1041 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1042 uint64_t *data) 1043 { 1044 return mv88e6xxx_stats_get_stats(chip, port, data, 1045 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1046 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1047 } 1048 1049 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1050 uint64_t *data) 1051 { 1052 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1053 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1054 } 1055 1056 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1057 uint64_t *data) 1058 { 1059 return mv88e6xxx_stats_get_stats(chip, port, data, 1060 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1061 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1062 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1063 } 1064 1065 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1066 uint64_t *data) 1067 { 1068 return mv88e6xxx_stats_get_stats(chip, port, data, 1069 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1070 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1071 0); 1072 } 1073 1074 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1075 uint64_t *data) 1076 { 1077 *data++ = chip->ports[port].atu_member_violation; 1078 *data++ = chip->ports[port].atu_miss_violation; 1079 *data++ = chip->ports[port].atu_full_violation; 1080 *data++ = chip->ports[port].vtu_member_violation; 1081 *data++ = chip->ports[port].vtu_miss_violation; 1082 } 1083 1084 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1085 uint64_t *data) 1086 { 1087 int count = 0; 1088 1089 if (chip->info->ops->stats_get_stats) 1090 count = chip->info->ops->stats_get_stats(chip, port, data); 1091 1092 mv88e6xxx_reg_lock(chip); 1093 if (chip->info->ops->serdes_get_stats) { 1094 data += count; 1095 count = chip->info->ops->serdes_get_stats(chip, port, data); 1096 } 1097 data += count; 1098 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1099 mv88e6xxx_reg_unlock(chip); 1100 } 1101 1102 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1103 uint64_t *data) 1104 { 1105 struct mv88e6xxx_chip *chip = ds->priv; 1106 int ret; 1107 1108 mv88e6xxx_reg_lock(chip); 1109 1110 ret = mv88e6xxx_stats_snapshot(chip, port); 1111 mv88e6xxx_reg_unlock(chip); 1112 1113 if (ret < 0) 1114 return; 1115 1116 mv88e6xxx_get_stats(chip, port, data); 1117 1118 } 1119 1120 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1121 { 1122 struct mv88e6xxx_chip *chip = ds->priv; 1123 int len; 1124 1125 len = 32 * sizeof(u16); 1126 if (chip->info->ops->serdes_get_regs_len) 1127 len += chip->info->ops->serdes_get_regs_len(chip, port); 1128 1129 return len; 1130 } 1131 1132 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1133 struct ethtool_regs *regs, void *_p) 1134 { 1135 struct mv88e6xxx_chip *chip = ds->priv; 1136 int err; 1137 u16 reg; 1138 u16 *p = _p; 1139 int i; 1140 1141 regs->version = chip->info->prod_num; 1142 1143 memset(p, 0xff, 32 * sizeof(u16)); 1144 1145 mv88e6xxx_reg_lock(chip); 1146 1147 for (i = 0; i < 32; i++) { 1148 1149 err = mv88e6xxx_port_read(chip, port, i, ®); 1150 if (!err) 1151 p[i] = reg; 1152 } 1153 1154 if (chip->info->ops->serdes_get_regs) 1155 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1156 1157 mv88e6xxx_reg_unlock(chip); 1158 } 1159 1160 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1161 struct ethtool_eee *e) 1162 { 1163 /* Nothing to do on the port's MAC */ 1164 return 0; 1165 } 1166 1167 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1168 struct ethtool_eee *e) 1169 { 1170 /* Nothing to do on the port's MAC */ 1171 return 0; 1172 } 1173 1174 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1175 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1176 { 1177 struct dsa_switch *ds = chip->ds; 1178 struct dsa_switch_tree *dst = ds->dst; 1179 struct net_device *br; 1180 struct dsa_port *dp; 1181 bool found = false; 1182 u16 pvlan; 1183 1184 list_for_each_entry(dp, &dst->ports, list) { 1185 if (dp->ds->index == dev && dp->index == port) { 1186 found = true; 1187 break; 1188 } 1189 } 1190 1191 /* Prevent frames from unknown switch or port */ 1192 if (!found) 1193 return 0; 1194 1195 /* Frames from DSA links and CPU ports can egress any local port */ 1196 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1197 return mv88e6xxx_port_mask(chip); 1198 1199 br = dp->bridge_dev; 1200 pvlan = 0; 1201 1202 /* Frames from user ports can egress any local DSA links and CPU ports, 1203 * as well as any local member of their bridge group. 1204 */ 1205 list_for_each_entry(dp, &dst->ports, list) 1206 if (dp->ds == ds && 1207 (dp->type == DSA_PORT_TYPE_CPU || 1208 dp->type == DSA_PORT_TYPE_DSA || 1209 (br && dp->bridge_dev == br))) 1210 pvlan |= BIT(dp->index); 1211 1212 return pvlan; 1213 } 1214 1215 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1216 { 1217 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1218 1219 /* prevent frames from going back out of the port they came in on */ 1220 output_ports &= ~BIT(port); 1221 1222 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1223 } 1224 1225 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1226 u8 state) 1227 { 1228 struct mv88e6xxx_chip *chip = ds->priv; 1229 int err; 1230 1231 mv88e6xxx_reg_lock(chip); 1232 err = mv88e6xxx_port_set_state(chip, port, state); 1233 mv88e6xxx_reg_unlock(chip); 1234 1235 if (err) 1236 dev_err(ds->dev, "p%d: failed to update state\n", port); 1237 } 1238 1239 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1240 { 1241 int err; 1242 1243 if (chip->info->ops->ieee_pri_map) { 1244 err = chip->info->ops->ieee_pri_map(chip); 1245 if (err) 1246 return err; 1247 } 1248 1249 if (chip->info->ops->ip_pri_map) { 1250 err = chip->info->ops->ip_pri_map(chip); 1251 if (err) 1252 return err; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1259 { 1260 struct dsa_switch *ds = chip->ds; 1261 int target, port; 1262 int err; 1263 1264 if (!chip->info->global2_addr) 1265 return 0; 1266 1267 /* Initialize the routing port to the 32 possible target devices */ 1268 for (target = 0; target < 32; target++) { 1269 port = dsa_routing_port(ds, target); 1270 if (port == ds->num_ports) 1271 port = 0x1f; 1272 1273 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1274 if (err) 1275 return err; 1276 } 1277 1278 if (chip->info->ops->set_cascade_port) { 1279 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1280 err = chip->info->ops->set_cascade_port(chip, port); 1281 if (err) 1282 return err; 1283 } 1284 1285 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1286 if (err) 1287 return err; 1288 1289 return 0; 1290 } 1291 1292 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1293 { 1294 /* Clear all trunk masks and mapping */ 1295 if (chip->info->global2_addr) 1296 return mv88e6xxx_g2_trunk_clear(chip); 1297 1298 return 0; 1299 } 1300 1301 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1302 { 1303 if (chip->info->ops->rmu_disable) 1304 return chip->info->ops->rmu_disable(chip); 1305 1306 return 0; 1307 } 1308 1309 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 if (chip->info->ops->pot_clear) 1312 return chip->info->ops->pot_clear(chip); 1313 1314 return 0; 1315 } 1316 1317 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1318 { 1319 if (chip->info->ops->mgmt_rsvd2cpu) 1320 return chip->info->ops->mgmt_rsvd2cpu(chip); 1321 1322 return 0; 1323 } 1324 1325 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1326 { 1327 int err; 1328 1329 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1330 if (err) 1331 return err; 1332 1333 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1334 if (err) 1335 return err; 1336 1337 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1338 } 1339 1340 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1341 { 1342 int port; 1343 int err; 1344 1345 if (!chip->info->ops->irl_init_all) 1346 return 0; 1347 1348 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1349 /* Disable ingress rate limiting by resetting all per port 1350 * ingress rate limit resources to their initial state. 1351 */ 1352 err = chip->info->ops->irl_init_all(chip, port); 1353 if (err) 1354 return err; 1355 } 1356 1357 return 0; 1358 } 1359 1360 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1361 { 1362 if (chip->info->ops->set_switch_mac) { 1363 u8 addr[ETH_ALEN]; 1364 1365 eth_random_addr(addr); 1366 1367 return chip->info->ops->set_switch_mac(chip, addr); 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1374 { 1375 u16 pvlan = 0; 1376 1377 if (!mv88e6xxx_has_pvt(chip)) 1378 return 0; 1379 1380 /* Skip the local source device, which uses in-chip port VLAN */ 1381 if (dev != chip->ds->index) 1382 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1383 1384 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1385 } 1386 1387 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1388 { 1389 int dev, port; 1390 int err; 1391 1392 if (!mv88e6xxx_has_pvt(chip)) 1393 return 0; 1394 1395 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1396 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1397 */ 1398 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1399 if (err) 1400 return err; 1401 1402 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1403 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1404 err = mv88e6xxx_pvt_map(chip, dev, port); 1405 if (err) 1406 return err; 1407 } 1408 } 1409 1410 return 0; 1411 } 1412 1413 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1414 { 1415 struct mv88e6xxx_chip *chip = ds->priv; 1416 int err; 1417 1418 mv88e6xxx_reg_lock(chip); 1419 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1420 mv88e6xxx_reg_unlock(chip); 1421 1422 if (err) 1423 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1424 } 1425 1426 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1427 { 1428 if (!chip->info->max_vid) 1429 return 0; 1430 1431 return mv88e6xxx_g1_vtu_flush(chip); 1432 } 1433 1434 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1435 struct mv88e6xxx_vtu_entry *entry) 1436 { 1437 if (!chip->info->ops->vtu_getnext) 1438 return -EOPNOTSUPP; 1439 1440 return chip->info->ops->vtu_getnext(chip, entry); 1441 } 1442 1443 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1444 struct mv88e6xxx_vtu_entry *entry) 1445 { 1446 if (!chip->info->ops->vtu_loadpurge) 1447 return -EOPNOTSUPP; 1448 1449 return chip->info->ops->vtu_loadpurge(chip, entry); 1450 } 1451 1452 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1453 { 1454 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1455 struct mv88e6xxx_vtu_entry vlan; 1456 int i, err; 1457 1458 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1459 1460 /* Set every FID bit used by the (un)bridged ports */ 1461 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1462 err = mv88e6xxx_port_get_fid(chip, i, fid); 1463 if (err) 1464 return err; 1465 1466 set_bit(*fid, fid_bitmap); 1467 } 1468 1469 /* Set every FID bit used by the VLAN entries */ 1470 vlan.vid = chip->info->max_vid; 1471 vlan.valid = false; 1472 1473 do { 1474 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1475 if (err) 1476 return err; 1477 1478 if (!vlan.valid) 1479 break; 1480 1481 set_bit(vlan.fid, fid_bitmap); 1482 } while (vlan.vid < chip->info->max_vid); 1483 1484 /* The reset value 0x000 is used to indicate that multiple address 1485 * databases are not needed. Return the next positive available. 1486 */ 1487 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1488 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1489 return -ENOSPC; 1490 1491 /* Clear the database */ 1492 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1493 } 1494 1495 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 1496 { 1497 if (chip->info->ops->atu_get_hash) 1498 return chip->info->ops->atu_get_hash(chip, hash); 1499 1500 return -EOPNOTSUPP; 1501 } 1502 1503 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 1504 { 1505 if (chip->info->ops->atu_set_hash) 1506 return chip->info->ops->atu_set_hash(chip, hash); 1507 1508 return -EOPNOTSUPP; 1509 } 1510 1511 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1512 u16 vid_begin, u16 vid_end) 1513 { 1514 struct mv88e6xxx_chip *chip = ds->priv; 1515 struct mv88e6xxx_vtu_entry vlan; 1516 int i, err; 1517 1518 /* DSA and CPU ports have to be members of multiple vlans */ 1519 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1520 return 0; 1521 1522 if (!vid_begin) 1523 return -EOPNOTSUPP; 1524 1525 vlan.vid = vid_begin - 1; 1526 vlan.valid = false; 1527 1528 do { 1529 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1530 if (err) 1531 return err; 1532 1533 if (!vlan.valid) 1534 break; 1535 1536 if (vlan.vid > vid_end) 1537 break; 1538 1539 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1540 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1541 continue; 1542 1543 if (!dsa_to_port(ds, i)->slave) 1544 continue; 1545 1546 if (vlan.member[i] == 1547 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1548 continue; 1549 1550 if (dsa_to_port(ds, i)->bridge_dev == 1551 dsa_to_port(ds, port)->bridge_dev) 1552 break; /* same bridge, check next VLAN */ 1553 1554 if (!dsa_to_port(ds, i)->bridge_dev) 1555 continue; 1556 1557 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1558 port, vlan.vid, i, 1559 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1560 return -EOPNOTSUPP; 1561 } 1562 } while (vlan.vid < vid_end); 1563 1564 return 0; 1565 } 1566 1567 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1568 bool vlan_filtering) 1569 { 1570 struct mv88e6xxx_chip *chip = ds->priv; 1571 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1572 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1573 int err; 1574 1575 if (!chip->info->max_vid) 1576 return -EOPNOTSUPP; 1577 1578 mv88e6xxx_reg_lock(chip); 1579 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1580 mv88e6xxx_reg_unlock(chip); 1581 1582 return err; 1583 } 1584 1585 static int 1586 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1587 const struct switchdev_obj_port_vlan *vlan) 1588 { 1589 struct mv88e6xxx_chip *chip = ds->priv; 1590 int err; 1591 1592 if (!chip->info->max_vid) 1593 return -EOPNOTSUPP; 1594 1595 /* If the requested port doesn't belong to the same bridge as the VLAN 1596 * members, do not support it (yet) and fallback to software VLAN. 1597 */ 1598 mv88e6xxx_reg_lock(chip); 1599 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1600 vlan->vid_end); 1601 mv88e6xxx_reg_unlock(chip); 1602 1603 /* We don't need any dynamic resource from the kernel (yet), 1604 * so skip the prepare phase. 1605 */ 1606 return err; 1607 } 1608 1609 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1610 const unsigned char *addr, u16 vid, 1611 u8 state) 1612 { 1613 struct mv88e6xxx_atu_entry entry; 1614 struct mv88e6xxx_vtu_entry vlan; 1615 u16 fid; 1616 int err; 1617 1618 /* Null VLAN ID corresponds to the port private database */ 1619 if (vid == 0) { 1620 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1621 if (err) 1622 return err; 1623 } else { 1624 vlan.vid = vid - 1; 1625 vlan.valid = false; 1626 1627 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1628 if (err) 1629 return err; 1630 1631 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1632 if (vlan.vid != vid || !vlan.valid) 1633 return -EOPNOTSUPP; 1634 1635 fid = vlan.fid; 1636 } 1637 1638 entry.state = 0; 1639 ether_addr_copy(entry.mac, addr); 1640 eth_addr_dec(entry.mac); 1641 1642 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1643 if (err) 1644 return err; 1645 1646 /* Initialize a fresh ATU entry if it isn't found */ 1647 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1648 memset(&entry, 0, sizeof(entry)); 1649 ether_addr_copy(entry.mac, addr); 1650 } 1651 1652 /* Purge the ATU entry only if no port is using it anymore */ 1653 if (!state) { 1654 entry.portvec &= ~BIT(port); 1655 if (!entry.portvec) 1656 entry.state = 0; 1657 } else { 1658 entry.portvec |= BIT(port); 1659 entry.state = state; 1660 } 1661 1662 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1663 } 1664 1665 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1666 const struct mv88e6xxx_policy *policy) 1667 { 1668 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1669 enum mv88e6xxx_policy_action action = policy->action; 1670 const u8 *addr = policy->addr; 1671 u16 vid = policy->vid; 1672 u8 state; 1673 int err; 1674 int id; 1675 1676 if (!chip->info->ops->port_set_policy) 1677 return -EOPNOTSUPP; 1678 1679 switch (mapping) { 1680 case MV88E6XXX_POLICY_MAPPING_DA: 1681 case MV88E6XXX_POLICY_MAPPING_SA: 1682 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1683 state = 0; /* Dissociate the port and address */ 1684 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1685 is_multicast_ether_addr(addr)) 1686 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1687 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1688 is_unicast_ether_addr(addr)) 1689 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1690 else 1691 return -EOPNOTSUPP; 1692 1693 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1694 state); 1695 if (err) 1696 return err; 1697 break; 1698 default: 1699 return -EOPNOTSUPP; 1700 } 1701 1702 /* Skip the port's policy clearing if the mapping is still in use */ 1703 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1704 idr_for_each_entry(&chip->policies, policy, id) 1705 if (policy->port == port && 1706 policy->mapping == mapping && 1707 policy->action != action) 1708 return 0; 1709 1710 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1711 } 1712 1713 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1714 struct ethtool_rx_flow_spec *fs) 1715 { 1716 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1717 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1718 enum mv88e6xxx_policy_mapping mapping; 1719 enum mv88e6xxx_policy_action action; 1720 struct mv88e6xxx_policy *policy; 1721 u16 vid = 0; 1722 u8 *addr; 1723 int err; 1724 int id; 1725 1726 if (fs->location != RX_CLS_LOC_ANY) 1727 return -EINVAL; 1728 1729 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1730 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1731 else 1732 return -EOPNOTSUPP; 1733 1734 switch (fs->flow_type & ~FLOW_EXT) { 1735 case ETHER_FLOW: 1736 if (!is_zero_ether_addr(mac_mask->h_dest) && 1737 is_zero_ether_addr(mac_mask->h_source)) { 1738 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1739 addr = mac_entry->h_dest; 1740 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1741 !is_zero_ether_addr(mac_mask->h_source)) { 1742 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1743 addr = mac_entry->h_source; 1744 } else { 1745 /* Cannot support DA and SA mapping in the same rule */ 1746 return -EOPNOTSUPP; 1747 } 1748 break; 1749 default: 1750 return -EOPNOTSUPP; 1751 } 1752 1753 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1754 if (fs->m_ext.vlan_tci != htons(0xffff)) 1755 return -EOPNOTSUPP; 1756 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1757 } 1758 1759 idr_for_each_entry(&chip->policies, policy, id) { 1760 if (policy->port == port && policy->mapping == mapping && 1761 policy->action == action && policy->vid == vid && 1762 ether_addr_equal(policy->addr, addr)) 1763 return -EEXIST; 1764 } 1765 1766 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1767 if (!policy) 1768 return -ENOMEM; 1769 1770 fs->location = 0; 1771 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1772 GFP_KERNEL); 1773 if (err) { 1774 devm_kfree(chip->dev, policy); 1775 return err; 1776 } 1777 1778 memcpy(&policy->fs, fs, sizeof(*fs)); 1779 ether_addr_copy(policy->addr, addr); 1780 policy->mapping = mapping; 1781 policy->action = action; 1782 policy->port = port; 1783 policy->vid = vid; 1784 1785 err = mv88e6xxx_policy_apply(chip, port, policy); 1786 if (err) { 1787 idr_remove(&chip->policies, fs->location); 1788 devm_kfree(chip->dev, policy); 1789 return err; 1790 } 1791 1792 return 0; 1793 } 1794 1795 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1796 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1797 { 1798 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1799 struct mv88e6xxx_chip *chip = ds->priv; 1800 struct mv88e6xxx_policy *policy; 1801 int err; 1802 int id; 1803 1804 mv88e6xxx_reg_lock(chip); 1805 1806 switch (rxnfc->cmd) { 1807 case ETHTOOL_GRXCLSRLCNT: 1808 rxnfc->data = 0; 1809 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1810 rxnfc->rule_cnt = 0; 1811 idr_for_each_entry(&chip->policies, policy, id) 1812 if (policy->port == port) 1813 rxnfc->rule_cnt++; 1814 err = 0; 1815 break; 1816 case ETHTOOL_GRXCLSRULE: 1817 err = -ENOENT; 1818 policy = idr_find(&chip->policies, fs->location); 1819 if (policy) { 1820 memcpy(fs, &policy->fs, sizeof(*fs)); 1821 err = 0; 1822 } 1823 break; 1824 case ETHTOOL_GRXCLSRLALL: 1825 rxnfc->data = 0; 1826 rxnfc->rule_cnt = 0; 1827 idr_for_each_entry(&chip->policies, policy, id) 1828 if (policy->port == port) 1829 rule_locs[rxnfc->rule_cnt++] = id; 1830 err = 0; 1831 break; 1832 default: 1833 err = -EOPNOTSUPP; 1834 break; 1835 } 1836 1837 mv88e6xxx_reg_unlock(chip); 1838 1839 return err; 1840 } 1841 1842 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1843 struct ethtool_rxnfc *rxnfc) 1844 { 1845 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1846 struct mv88e6xxx_chip *chip = ds->priv; 1847 struct mv88e6xxx_policy *policy; 1848 int err; 1849 1850 mv88e6xxx_reg_lock(chip); 1851 1852 switch (rxnfc->cmd) { 1853 case ETHTOOL_SRXCLSRLINS: 1854 err = mv88e6xxx_policy_insert(chip, port, fs); 1855 break; 1856 case ETHTOOL_SRXCLSRLDEL: 1857 err = -ENOENT; 1858 policy = idr_remove(&chip->policies, fs->location); 1859 if (policy) { 1860 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1861 err = mv88e6xxx_policy_apply(chip, port, policy); 1862 devm_kfree(chip->dev, policy); 1863 } 1864 break; 1865 default: 1866 err = -EOPNOTSUPP; 1867 break; 1868 } 1869 1870 mv88e6xxx_reg_unlock(chip); 1871 1872 return err; 1873 } 1874 1875 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1876 u16 vid) 1877 { 1878 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1879 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1880 1881 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1882 } 1883 1884 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1885 { 1886 int port; 1887 int err; 1888 1889 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1890 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1891 if (err) 1892 return err; 1893 } 1894 1895 return 0; 1896 } 1897 1898 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1899 u16 vid, u8 member, bool warn) 1900 { 1901 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1902 struct mv88e6xxx_vtu_entry vlan; 1903 int i, err; 1904 1905 if (!vid) 1906 return -EOPNOTSUPP; 1907 1908 vlan.vid = vid - 1; 1909 vlan.valid = false; 1910 1911 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1912 if (err) 1913 return err; 1914 1915 if (vlan.vid != vid || !vlan.valid) { 1916 memset(&vlan, 0, sizeof(vlan)); 1917 1918 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1919 if (err) 1920 return err; 1921 1922 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1923 if (i == port) 1924 vlan.member[i] = member; 1925 else 1926 vlan.member[i] = non_member; 1927 1928 vlan.vid = vid; 1929 vlan.valid = true; 1930 1931 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1932 if (err) 1933 return err; 1934 1935 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1936 if (err) 1937 return err; 1938 } else if (vlan.member[port] != member) { 1939 vlan.member[port] = member; 1940 1941 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1942 if (err) 1943 return err; 1944 } else if (warn) { 1945 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1946 port, vid); 1947 } 1948 1949 return 0; 1950 } 1951 1952 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1953 const struct switchdev_obj_port_vlan *vlan) 1954 { 1955 struct mv88e6xxx_chip *chip = ds->priv; 1956 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1957 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1958 bool warn; 1959 u8 member; 1960 u16 vid; 1961 1962 if (!chip->info->max_vid) 1963 return; 1964 1965 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1966 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1967 else if (untagged) 1968 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1969 else 1970 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1971 1972 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 1973 * and then the CPU port. Do not warn for duplicates for the CPU port. 1974 */ 1975 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 1976 1977 mv88e6xxx_reg_lock(chip); 1978 1979 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1980 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn)) 1981 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1982 vid, untagged ? 'u' : 't'); 1983 1984 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1985 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1986 vlan->vid_end); 1987 1988 mv88e6xxx_reg_unlock(chip); 1989 } 1990 1991 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1992 int port, u16 vid) 1993 { 1994 struct mv88e6xxx_vtu_entry vlan; 1995 int i, err; 1996 1997 if (!vid) 1998 return -EOPNOTSUPP; 1999 2000 vlan.vid = vid - 1; 2001 vlan.valid = false; 2002 2003 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2004 if (err) 2005 return err; 2006 2007 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2008 * tell switchdev that this VLAN is likely handled in software. 2009 */ 2010 if (vlan.vid != vid || !vlan.valid || 2011 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2012 return -EOPNOTSUPP; 2013 2014 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2015 2016 /* keep the VLAN unless all ports are excluded */ 2017 vlan.valid = false; 2018 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2019 if (vlan.member[i] != 2020 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2021 vlan.valid = true; 2022 break; 2023 } 2024 } 2025 2026 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2027 if (err) 2028 return err; 2029 2030 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2031 } 2032 2033 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2034 const struct switchdev_obj_port_vlan *vlan) 2035 { 2036 struct mv88e6xxx_chip *chip = ds->priv; 2037 u16 pvid, vid; 2038 int err = 0; 2039 2040 if (!chip->info->max_vid) 2041 return -EOPNOTSUPP; 2042 2043 mv88e6xxx_reg_lock(chip); 2044 2045 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2046 if (err) 2047 goto unlock; 2048 2049 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2050 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 2051 if (err) 2052 goto unlock; 2053 2054 if (vid == pvid) { 2055 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2056 if (err) 2057 goto unlock; 2058 } 2059 } 2060 2061 unlock: 2062 mv88e6xxx_reg_unlock(chip); 2063 2064 return err; 2065 } 2066 2067 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2068 const unsigned char *addr, u16 vid) 2069 { 2070 struct mv88e6xxx_chip *chip = ds->priv; 2071 int err; 2072 2073 mv88e6xxx_reg_lock(chip); 2074 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2075 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2076 mv88e6xxx_reg_unlock(chip); 2077 2078 return err; 2079 } 2080 2081 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2082 const unsigned char *addr, u16 vid) 2083 { 2084 struct mv88e6xxx_chip *chip = ds->priv; 2085 int err; 2086 2087 mv88e6xxx_reg_lock(chip); 2088 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2089 mv88e6xxx_reg_unlock(chip); 2090 2091 return err; 2092 } 2093 2094 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2095 u16 fid, u16 vid, int port, 2096 dsa_fdb_dump_cb_t *cb, void *data) 2097 { 2098 struct mv88e6xxx_atu_entry addr; 2099 bool is_static; 2100 int err; 2101 2102 addr.state = 0; 2103 eth_broadcast_addr(addr.mac); 2104 2105 do { 2106 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2107 if (err) 2108 return err; 2109 2110 if (!addr.state) 2111 break; 2112 2113 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2114 continue; 2115 2116 if (!is_unicast_ether_addr(addr.mac)) 2117 continue; 2118 2119 is_static = (addr.state == 2120 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2121 err = cb(addr.mac, vid, is_static, data); 2122 if (err) 2123 return err; 2124 } while (!is_broadcast_ether_addr(addr.mac)); 2125 2126 return err; 2127 } 2128 2129 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2130 dsa_fdb_dump_cb_t *cb, void *data) 2131 { 2132 struct mv88e6xxx_vtu_entry vlan; 2133 u16 fid; 2134 int err; 2135 2136 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2137 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2138 if (err) 2139 return err; 2140 2141 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2142 if (err) 2143 return err; 2144 2145 /* Dump VLANs' Filtering Information Databases */ 2146 vlan.vid = chip->info->max_vid; 2147 vlan.valid = false; 2148 2149 do { 2150 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2151 if (err) 2152 return err; 2153 2154 if (!vlan.valid) 2155 break; 2156 2157 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2158 cb, data); 2159 if (err) 2160 return err; 2161 } while (vlan.vid < chip->info->max_vid); 2162 2163 return err; 2164 } 2165 2166 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2167 dsa_fdb_dump_cb_t *cb, void *data) 2168 { 2169 struct mv88e6xxx_chip *chip = ds->priv; 2170 int err; 2171 2172 mv88e6xxx_reg_lock(chip); 2173 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2174 mv88e6xxx_reg_unlock(chip); 2175 2176 return err; 2177 } 2178 2179 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2180 struct net_device *br) 2181 { 2182 struct dsa_switch *ds = chip->ds; 2183 struct dsa_switch_tree *dst = ds->dst; 2184 struct dsa_port *dp; 2185 int err; 2186 2187 list_for_each_entry(dp, &dst->ports, list) { 2188 if (dp->bridge_dev == br) { 2189 if (dp->ds == ds) { 2190 /* This is a local bridge group member, 2191 * remap its Port VLAN Map. 2192 */ 2193 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2194 if (err) 2195 return err; 2196 } else { 2197 /* This is an external bridge group member, 2198 * remap its cross-chip Port VLAN Table entry. 2199 */ 2200 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2201 dp->index); 2202 if (err) 2203 return err; 2204 } 2205 } 2206 } 2207 2208 return 0; 2209 } 2210 2211 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2212 struct net_device *br) 2213 { 2214 struct mv88e6xxx_chip *chip = ds->priv; 2215 int err; 2216 2217 mv88e6xxx_reg_lock(chip); 2218 err = mv88e6xxx_bridge_map(chip, br); 2219 mv88e6xxx_reg_unlock(chip); 2220 2221 return err; 2222 } 2223 2224 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2225 struct net_device *br) 2226 { 2227 struct mv88e6xxx_chip *chip = ds->priv; 2228 2229 mv88e6xxx_reg_lock(chip); 2230 if (mv88e6xxx_bridge_map(chip, br) || 2231 mv88e6xxx_port_vlan_map(chip, port)) 2232 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2233 mv88e6xxx_reg_unlock(chip); 2234 } 2235 2236 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2237 int tree_index, int sw_index, 2238 int port, struct net_device *br) 2239 { 2240 struct mv88e6xxx_chip *chip = ds->priv; 2241 int err; 2242 2243 if (tree_index != ds->dst->index) 2244 return 0; 2245 2246 mv88e6xxx_reg_lock(chip); 2247 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2248 mv88e6xxx_reg_unlock(chip); 2249 2250 return err; 2251 } 2252 2253 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2254 int tree_index, int sw_index, 2255 int port, struct net_device *br) 2256 { 2257 struct mv88e6xxx_chip *chip = ds->priv; 2258 2259 if (tree_index != ds->dst->index) 2260 return; 2261 2262 mv88e6xxx_reg_lock(chip); 2263 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2264 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2265 mv88e6xxx_reg_unlock(chip); 2266 } 2267 2268 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2269 { 2270 if (chip->info->ops->reset) 2271 return chip->info->ops->reset(chip); 2272 2273 return 0; 2274 } 2275 2276 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2277 { 2278 struct gpio_desc *gpiod = chip->reset; 2279 2280 /* If there is a GPIO connected to the reset pin, toggle it */ 2281 if (gpiod) { 2282 gpiod_set_value_cansleep(gpiod, 1); 2283 usleep_range(10000, 20000); 2284 gpiod_set_value_cansleep(gpiod, 0); 2285 usleep_range(10000, 20000); 2286 } 2287 } 2288 2289 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2290 { 2291 int i, err; 2292 2293 /* Set all ports to the Disabled state */ 2294 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2295 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2296 if (err) 2297 return err; 2298 } 2299 2300 /* Wait for transmit queues to drain, 2301 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2302 */ 2303 usleep_range(2000, 4000); 2304 2305 return 0; 2306 } 2307 2308 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2309 { 2310 int err; 2311 2312 err = mv88e6xxx_disable_ports(chip); 2313 if (err) 2314 return err; 2315 2316 mv88e6xxx_hardware_reset(chip); 2317 2318 return mv88e6xxx_software_reset(chip); 2319 } 2320 2321 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2322 enum mv88e6xxx_frame_mode frame, 2323 enum mv88e6xxx_egress_mode egress, u16 etype) 2324 { 2325 int err; 2326 2327 if (!chip->info->ops->port_set_frame_mode) 2328 return -EOPNOTSUPP; 2329 2330 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2331 if (err) 2332 return err; 2333 2334 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2335 if (err) 2336 return err; 2337 2338 if (chip->info->ops->port_set_ether_type) 2339 return chip->info->ops->port_set_ether_type(chip, port, etype); 2340 2341 return 0; 2342 } 2343 2344 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2345 { 2346 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2347 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2348 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2349 } 2350 2351 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2352 { 2353 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2354 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2355 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2356 } 2357 2358 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2359 { 2360 return mv88e6xxx_set_port_mode(chip, port, 2361 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2362 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2363 ETH_P_EDSA); 2364 } 2365 2366 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2367 { 2368 if (dsa_is_dsa_port(chip->ds, port)) 2369 return mv88e6xxx_set_port_mode_dsa(chip, port); 2370 2371 if (dsa_is_user_port(chip->ds, port)) 2372 return mv88e6xxx_set_port_mode_normal(chip, port); 2373 2374 /* Setup CPU port mode depending on its supported tag format */ 2375 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2376 return mv88e6xxx_set_port_mode_dsa(chip, port); 2377 2378 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2379 return mv88e6xxx_set_port_mode_edsa(chip, port); 2380 2381 return -EINVAL; 2382 } 2383 2384 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2385 { 2386 bool message = dsa_is_dsa_port(chip->ds, port); 2387 2388 return mv88e6xxx_port_set_message_port(chip, port, message); 2389 } 2390 2391 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2392 { 2393 struct dsa_switch *ds = chip->ds; 2394 bool flood; 2395 2396 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2397 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2398 if (chip->info->ops->port_set_egress_floods) 2399 return chip->info->ops->port_set_egress_floods(chip, port, 2400 flood, flood); 2401 2402 return 0; 2403 } 2404 2405 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2406 { 2407 struct mv88e6xxx_port *mvp = dev_id; 2408 struct mv88e6xxx_chip *chip = mvp->chip; 2409 irqreturn_t ret = IRQ_NONE; 2410 int port = mvp->port; 2411 u8 lane; 2412 2413 mv88e6xxx_reg_lock(chip); 2414 lane = mv88e6xxx_serdes_get_lane(chip, port); 2415 if (lane) 2416 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2417 mv88e6xxx_reg_unlock(chip); 2418 2419 return ret; 2420 } 2421 2422 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2423 u8 lane) 2424 { 2425 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2426 unsigned int irq; 2427 int err; 2428 2429 /* Nothing to request if this SERDES port has no IRQ */ 2430 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2431 if (!irq) 2432 return 0; 2433 2434 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2435 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2436 2437 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2438 mv88e6xxx_reg_unlock(chip); 2439 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2440 IRQF_ONESHOT, dev_id->serdes_irq_name, 2441 dev_id); 2442 mv88e6xxx_reg_lock(chip); 2443 if (err) 2444 return err; 2445 2446 dev_id->serdes_irq = irq; 2447 2448 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2449 } 2450 2451 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2452 u8 lane) 2453 { 2454 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2455 unsigned int irq = dev_id->serdes_irq; 2456 int err; 2457 2458 /* Nothing to free if no IRQ has been requested */ 2459 if (!irq) 2460 return 0; 2461 2462 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2463 2464 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2465 mv88e6xxx_reg_unlock(chip); 2466 free_irq(irq, dev_id); 2467 mv88e6xxx_reg_lock(chip); 2468 2469 dev_id->serdes_irq = 0; 2470 2471 return err; 2472 } 2473 2474 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2475 bool on) 2476 { 2477 u8 lane; 2478 int err; 2479 2480 lane = mv88e6xxx_serdes_get_lane(chip, port); 2481 if (!lane) 2482 return 0; 2483 2484 if (on) { 2485 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2486 if (err) 2487 return err; 2488 2489 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2490 } else { 2491 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2492 if (err) 2493 return err; 2494 2495 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2496 } 2497 2498 return err; 2499 } 2500 2501 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2502 { 2503 struct dsa_switch *ds = chip->ds; 2504 int upstream_port; 2505 int err; 2506 2507 upstream_port = dsa_upstream_port(ds, port); 2508 if (chip->info->ops->port_set_upstream_port) { 2509 err = chip->info->ops->port_set_upstream_port(chip, port, 2510 upstream_port); 2511 if (err) 2512 return err; 2513 } 2514 2515 if (port == upstream_port) { 2516 if (chip->info->ops->set_cpu_port) { 2517 err = chip->info->ops->set_cpu_port(chip, 2518 upstream_port); 2519 if (err) 2520 return err; 2521 } 2522 2523 if (chip->info->ops->set_egress_port) { 2524 err = chip->info->ops->set_egress_port(chip, 2525 MV88E6XXX_EGRESS_DIR_INGRESS, 2526 upstream_port); 2527 if (err) 2528 return err; 2529 2530 err = chip->info->ops->set_egress_port(chip, 2531 MV88E6XXX_EGRESS_DIR_EGRESS, 2532 upstream_port); 2533 if (err) 2534 return err; 2535 } 2536 } 2537 2538 return 0; 2539 } 2540 2541 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2542 { 2543 struct dsa_switch *ds = chip->ds; 2544 int err; 2545 u16 reg; 2546 2547 chip->ports[port].chip = chip; 2548 chip->ports[port].port = port; 2549 2550 /* MAC Forcing register: don't force link, speed, duplex or flow control 2551 * state to any particular values on physical ports, but force the CPU 2552 * port and all DSA ports to their maximum bandwidth and full duplex. 2553 */ 2554 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2555 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2556 SPEED_MAX, DUPLEX_FULL, 2557 PAUSE_OFF, 2558 PHY_INTERFACE_MODE_NA); 2559 else 2560 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2561 SPEED_UNFORCED, DUPLEX_UNFORCED, 2562 PAUSE_ON, 2563 PHY_INTERFACE_MODE_NA); 2564 if (err) 2565 return err; 2566 2567 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2568 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2569 * tunneling, determine priority by looking at 802.1p and IP 2570 * priority fields (IP prio has precedence), and set STP state 2571 * to Forwarding. 2572 * 2573 * If this is the CPU link, use DSA or EDSA tagging depending 2574 * on which tagging mode was configured. 2575 * 2576 * If this is a link to another switch, use DSA tagging mode. 2577 * 2578 * If this is the upstream port for this switch, enable 2579 * forwarding of unknown unicasts and multicasts. 2580 */ 2581 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2582 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2583 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2584 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2585 if (err) 2586 return err; 2587 2588 err = mv88e6xxx_setup_port_mode(chip, port); 2589 if (err) 2590 return err; 2591 2592 err = mv88e6xxx_setup_egress_floods(chip, port); 2593 if (err) 2594 return err; 2595 2596 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2597 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2598 * untagged frames on this port, do a destination address lookup on all 2599 * received packets as usual, disable ARP mirroring and don't send a 2600 * copy of all transmitted/received frames on this port to the CPU. 2601 */ 2602 err = mv88e6xxx_port_set_map_da(chip, port); 2603 if (err) 2604 return err; 2605 2606 err = mv88e6xxx_setup_upstream_port(chip, port); 2607 if (err) 2608 return err; 2609 2610 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2611 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2612 if (err) 2613 return err; 2614 2615 if (chip->info->ops->port_set_jumbo_size) { 2616 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2617 if (err) 2618 return err; 2619 } 2620 2621 /* Port Association Vector: when learning source addresses 2622 * of packets, add the address to the address database using 2623 * a port bitmap that has only the bit for this port set and 2624 * the other bits clear. 2625 */ 2626 reg = 1 << port; 2627 /* Disable learning for CPU port */ 2628 if (dsa_is_cpu_port(ds, port)) 2629 reg = 0; 2630 2631 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2632 reg); 2633 if (err) 2634 return err; 2635 2636 /* Egress rate control 2: disable egress rate control. */ 2637 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2638 0x0000); 2639 if (err) 2640 return err; 2641 2642 if (chip->info->ops->port_pause_limit) { 2643 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2644 if (err) 2645 return err; 2646 } 2647 2648 if (chip->info->ops->port_disable_learn_limit) { 2649 err = chip->info->ops->port_disable_learn_limit(chip, port); 2650 if (err) 2651 return err; 2652 } 2653 2654 if (chip->info->ops->port_disable_pri_override) { 2655 err = chip->info->ops->port_disable_pri_override(chip, port); 2656 if (err) 2657 return err; 2658 } 2659 2660 if (chip->info->ops->port_tag_remap) { 2661 err = chip->info->ops->port_tag_remap(chip, port); 2662 if (err) 2663 return err; 2664 } 2665 2666 if (chip->info->ops->port_egress_rate_limiting) { 2667 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2668 if (err) 2669 return err; 2670 } 2671 2672 if (chip->info->ops->port_setup_message_port) { 2673 err = chip->info->ops->port_setup_message_port(chip, port); 2674 if (err) 2675 return err; 2676 } 2677 2678 /* Port based VLAN map: give each port the same default address 2679 * database, and allow bidirectional communication between the 2680 * CPU and DSA port(s), and the other ports. 2681 */ 2682 err = mv88e6xxx_port_set_fid(chip, port, 0); 2683 if (err) 2684 return err; 2685 2686 err = mv88e6xxx_port_vlan_map(chip, port); 2687 if (err) 2688 return err; 2689 2690 /* Default VLAN ID and priority: don't set a default VLAN 2691 * ID, and set the default packet priority to zero. 2692 */ 2693 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2694 } 2695 2696 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2697 { 2698 struct mv88e6xxx_chip *chip = ds->priv; 2699 2700 if (chip->info->ops->port_set_jumbo_size) 2701 return 10240; 2702 return 1522; 2703 } 2704 2705 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2706 { 2707 struct mv88e6xxx_chip *chip = ds->priv; 2708 int ret = 0; 2709 2710 mv88e6xxx_reg_lock(chip); 2711 if (chip->info->ops->port_set_jumbo_size) 2712 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2713 else 2714 if (new_mtu > 1522) 2715 ret = -EINVAL; 2716 mv88e6xxx_reg_unlock(chip); 2717 2718 return ret; 2719 } 2720 2721 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2722 struct phy_device *phydev) 2723 { 2724 struct mv88e6xxx_chip *chip = ds->priv; 2725 int err; 2726 2727 mv88e6xxx_reg_lock(chip); 2728 err = mv88e6xxx_serdes_power(chip, port, true); 2729 mv88e6xxx_reg_unlock(chip); 2730 2731 return err; 2732 } 2733 2734 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2735 { 2736 struct mv88e6xxx_chip *chip = ds->priv; 2737 2738 mv88e6xxx_reg_lock(chip); 2739 if (mv88e6xxx_serdes_power(chip, port, false)) 2740 dev_err(chip->dev, "failed to power off SERDES\n"); 2741 mv88e6xxx_reg_unlock(chip); 2742 } 2743 2744 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2745 unsigned int ageing_time) 2746 { 2747 struct mv88e6xxx_chip *chip = ds->priv; 2748 int err; 2749 2750 mv88e6xxx_reg_lock(chip); 2751 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2752 mv88e6xxx_reg_unlock(chip); 2753 2754 return err; 2755 } 2756 2757 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2758 { 2759 int err; 2760 2761 /* Initialize the statistics unit */ 2762 if (chip->info->ops->stats_set_histogram) { 2763 err = chip->info->ops->stats_set_histogram(chip); 2764 if (err) 2765 return err; 2766 } 2767 2768 return mv88e6xxx_g1_stats_clear(chip); 2769 } 2770 2771 /* Check if the errata has already been applied. */ 2772 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2773 { 2774 int port; 2775 int err; 2776 u16 val; 2777 2778 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2779 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2780 if (err) { 2781 dev_err(chip->dev, 2782 "Error reading hidden register: %d\n", err); 2783 return false; 2784 } 2785 if (val != 0x01c0) 2786 return false; 2787 } 2788 2789 return true; 2790 } 2791 2792 /* The 6390 copper ports have an errata which require poking magic 2793 * values into undocumented hidden registers and then performing a 2794 * software reset. 2795 */ 2796 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2797 { 2798 int port; 2799 int err; 2800 2801 if (mv88e6390_setup_errata_applied(chip)) 2802 return 0; 2803 2804 /* Set the ports into blocking mode */ 2805 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2806 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2807 if (err) 2808 return err; 2809 } 2810 2811 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2812 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2813 if (err) 2814 return err; 2815 } 2816 2817 return mv88e6xxx_software_reset(chip); 2818 } 2819 2820 enum mv88e6xxx_devlink_param_id { 2821 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 2822 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2823 }; 2824 2825 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id, 2826 struct devlink_param_gset_ctx *ctx) 2827 { 2828 struct mv88e6xxx_chip *chip = ds->priv; 2829 int err; 2830 2831 mv88e6xxx_reg_lock(chip); 2832 2833 switch (id) { 2834 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2835 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8); 2836 break; 2837 default: 2838 err = -EOPNOTSUPP; 2839 break; 2840 } 2841 2842 mv88e6xxx_reg_unlock(chip); 2843 2844 return err; 2845 } 2846 2847 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id, 2848 struct devlink_param_gset_ctx *ctx) 2849 { 2850 struct mv88e6xxx_chip *chip = ds->priv; 2851 int err; 2852 2853 mv88e6xxx_reg_lock(chip); 2854 2855 switch (id) { 2856 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2857 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); 2858 break; 2859 default: 2860 err = -EOPNOTSUPP; 2861 break; 2862 } 2863 2864 mv88e6xxx_reg_unlock(chip); 2865 2866 return err; 2867 } 2868 2869 static const struct devlink_param mv88e6xxx_devlink_params[] = { 2870 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2871 "ATU_hash", DEVLINK_PARAM_TYPE_U8, 2872 BIT(DEVLINK_PARAM_CMODE_RUNTIME)), 2873 }; 2874 2875 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds) 2876 { 2877 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params, 2878 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2879 } 2880 2881 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds) 2882 { 2883 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params, 2884 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2885 } 2886 2887 enum mv88e6xxx_devlink_resource_id { 2888 MV88E6XXX_RESOURCE_ID_ATU, 2889 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2890 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2891 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2892 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2893 }; 2894 2895 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, 2896 u16 bin) 2897 { 2898 u16 occupancy = 0; 2899 int err; 2900 2901 mv88e6xxx_reg_lock(chip); 2902 2903 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL, 2904 bin); 2905 if (err) { 2906 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); 2907 goto unlock; 2908 } 2909 2910 err = mv88e6xxx_g1_atu_get_next(chip, 0); 2911 if (err) { 2912 dev_err(chip->dev, "failed to perform ATU get next\n"); 2913 goto unlock; 2914 } 2915 2916 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy); 2917 if (err) { 2918 dev_err(chip->dev, "failed to get ATU stats\n"); 2919 goto unlock; 2920 } 2921 2922 occupancy &= MV88E6XXX_G2_ATU_STATS_MASK; 2923 2924 unlock: 2925 mv88e6xxx_reg_unlock(chip); 2926 2927 return occupancy; 2928 } 2929 2930 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv) 2931 { 2932 struct mv88e6xxx_chip *chip = priv; 2933 2934 return mv88e6xxx_devlink_atu_bin_get(chip, 2935 MV88E6XXX_G2_ATU_STATS_BIN_0); 2936 } 2937 2938 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv) 2939 { 2940 struct mv88e6xxx_chip *chip = priv; 2941 2942 return mv88e6xxx_devlink_atu_bin_get(chip, 2943 MV88E6XXX_G2_ATU_STATS_BIN_1); 2944 } 2945 2946 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv) 2947 { 2948 struct mv88e6xxx_chip *chip = priv; 2949 2950 return mv88e6xxx_devlink_atu_bin_get(chip, 2951 MV88E6XXX_G2_ATU_STATS_BIN_2); 2952 } 2953 2954 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv) 2955 { 2956 struct mv88e6xxx_chip *chip = priv; 2957 2958 return mv88e6xxx_devlink_atu_bin_get(chip, 2959 MV88E6XXX_G2_ATU_STATS_BIN_3); 2960 } 2961 2962 static u64 mv88e6xxx_devlink_atu_get(void *priv) 2963 { 2964 return mv88e6xxx_devlink_atu_bin_0_get(priv) + 2965 mv88e6xxx_devlink_atu_bin_1_get(priv) + 2966 mv88e6xxx_devlink_atu_bin_2_get(priv) + 2967 mv88e6xxx_devlink_atu_bin_3_get(priv); 2968 } 2969 2970 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds) 2971 { 2972 struct devlink_resource_size_params size_params; 2973 struct mv88e6xxx_chip *chip = ds->priv; 2974 int err; 2975 2976 devlink_resource_size_params_init(&size_params, 2977 mv88e6xxx_num_macs(chip), 2978 mv88e6xxx_num_macs(chip), 2979 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2980 2981 err = dsa_devlink_resource_register(ds, "ATU", 2982 mv88e6xxx_num_macs(chip), 2983 MV88E6XXX_RESOURCE_ID_ATU, 2984 DEVLINK_RESOURCE_ID_PARENT_TOP, 2985 &size_params); 2986 if (err) 2987 goto out; 2988 2989 devlink_resource_size_params_init(&size_params, 2990 mv88e6xxx_num_macs(chip) / 4, 2991 mv88e6xxx_num_macs(chip) / 4, 2992 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2993 2994 err = dsa_devlink_resource_register(ds, "ATU_bin_0", 2995 mv88e6xxx_num_macs(chip) / 4, 2996 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2997 MV88E6XXX_RESOURCE_ID_ATU, 2998 &size_params); 2999 if (err) 3000 goto out; 3001 3002 err = dsa_devlink_resource_register(ds, "ATU_bin_1", 3003 mv88e6xxx_num_macs(chip) / 4, 3004 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 3005 MV88E6XXX_RESOURCE_ID_ATU, 3006 &size_params); 3007 if (err) 3008 goto out; 3009 3010 err = dsa_devlink_resource_register(ds, "ATU_bin_2", 3011 mv88e6xxx_num_macs(chip) / 4, 3012 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 3013 MV88E6XXX_RESOURCE_ID_ATU, 3014 &size_params); 3015 if (err) 3016 goto out; 3017 3018 err = dsa_devlink_resource_register(ds, "ATU_bin_3", 3019 mv88e6xxx_num_macs(chip) / 4, 3020 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 3021 MV88E6XXX_RESOURCE_ID_ATU, 3022 &size_params); 3023 if (err) 3024 goto out; 3025 3026 dsa_devlink_resource_occ_get_register(ds, 3027 MV88E6XXX_RESOURCE_ID_ATU, 3028 mv88e6xxx_devlink_atu_get, 3029 chip); 3030 3031 dsa_devlink_resource_occ_get_register(ds, 3032 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 3033 mv88e6xxx_devlink_atu_bin_0_get, 3034 chip); 3035 3036 dsa_devlink_resource_occ_get_register(ds, 3037 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 3038 mv88e6xxx_devlink_atu_bin_1_get, 3039 chip); 3040 3041 dsa_devlink_resource_occ_get_register(ds, 3042 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 3043 mv88e6xxx_devlink_atu_bin_2_get, 3044 chip); 3045 3046 dsa_devlink_resource_occ_get_register(ds, 3047 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 3048 mv88e6xxx_devlink_atu_bin_3_get, 3049 chip); 3050 3051 return 0; 3052 3053 out: 3054 dsa_devlink_resources_unregister(ds); 3055 return err; 3056 } 3057 3058 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3059 { 3060 mv88e6xxx_teardown_devlink_params(ds); 3061 dsa_devlink_resources_unregister(ds); 3062 } 3063 3064 static int mv88e6xxx_setup(struct dsa_switch *ds) 3065 { 3066 struct mv88e6xxx_chip *chip = ds->priv; 3067 u8 cmode; 3068 int err; 3069 int i; 3070 3071 chip->ds = ds; 3072 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3073 3074 mv88e6xxx_reg_lock(chip); 3075 3076 if (chip->info->ops->setup_errata) { 3077 err = chip->info->ops->setup_errata(chip); 3078 if (err) 3079 goto unlock; 3080 } 3081 3082 /* Cache the cmode of each port. */ 3083 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3084 if (chip->info->ops->port_get_cmode) { 3085 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3086 if (err) 3087 goto unlock; 3088 3089 chip->ports[i].cmode = cmode; 3090 } 3091 } 3092 3093 /* Setup Switch Port Registers */ 3094 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3095 if (dsa_is_unused_port(ds, i)) 3096 continue; 3097 3098 /* Prevent the use of an invalid port. */ 3099 if (mv88e6xxx_is_invalid_port(chip, i)) { 3100 dev_err(chip->dev, "port %d is invalid\n", i); 3101 err = -EINVAL; 3102 goto unlock; 3103 } 3104 3105 err = mv88e6xxx_setup_port(chip, i); 3106 if (err) 3107 goto unlock; 3108 } 3109 3110 err = mv88e6xxx_irl_setup(chip); 3111 if (err) 3112 goto unlock; 3113 3114 err = mv88e6xxx_mac_setup(chip); 3115 if (err) 3116 goto unlock; 3117 3118 err = mv88e6xxx_phy_setup(chip); 3119 if (err) 3120 goto unlock; 3121 3122 err = mv88e6xxx_vtu_setup(chip); 3123 if (err) 3124 goto unlock; 3125 3126 err = mv88e6xxx_pvt_setup(chip); 3127 if (err) 3128 goto unlock; 3129 3130 err = mv88e6xxx_atu_setup(chip); 3131 if (err) 3132 goto unlock; 3133 3134 err = mv88e6xxx_broadcast_setup(chip, 0); 3135 if (err) 3136 goto unlock; 3137 3138 err = mv88e6xxx_pot_setup(chip); 3139 if (err) 3140 goto unlock; 3141 3142 err = mv88e6xxx_rmu_setup(chip); 3143 if (err) 3144 goto unlock; 3145 3146 err = mv88e6xxx_rsvd2cpu_setup(chip); 3147 if (err) 3148 goto unlock; 3149 3150 err = mv88e6xxx_trunk_setup(chip); 3151 if (err) 3152 goto unlock; 3153 3154 err = mv88e6xxx_devmap_setup(chip); 3155 if (err) 3156 goto unlock; 3157 3158 err = mv88e6xxx_pri_setup(chip); 3159 if (err) 3160 goto unlock; 3161 3162 /* Setup PTP Hardware Clock and timestamping */ 3163 if (chip->info->ptp_support) { 3164 err = mv88e6xxx_ptp_setup(chip); 3165 if (err) 3166 goto unlock; 3167 3168 err = mv88e6xxx_hwtstamp_setup(chip); 3169 if (err) 3170 goto unlock; 3171 } 3172 3173 err = mv88e6xxx_stats_setup(chip); 3174 if (err) 3175 goto unlock; 3176 3177 unlock: 3178 mv88e6xxx_reg_unlock(chip); 3179 3180 if (err) 3181 return err; 3182 3183 /* Have to be called without holding the register lock, since 3184 * they take the devlink lock, and we later take the locks in 3185 * the reverse order when getting/setting parameters or 3186 * resource occupancy. 3187 */ 3188 err = mv88e6xxx_setup_devlink_resources(ds); 3189 if (err) 3190 return err; 3191 3192 err = mv88e6xxx_setup_devlink_params(ds); 3193 if (err) 3194 dsa_devlink_resources_unregister(ds); 3195 3196 return err; 3197 } 3198 3199 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3200 { 3201 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3202 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3203 u16 val; 3204 int err; 3205 3206 if (!chip->info->ops->phy_read) 3207 return -EOPNOTSUPP; 3208 3209 mv88e6xxx_reg_lock(chip); 3210 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3211 mv88e6xxx_reg_unlock(chip); 3212 3213 if (reg == MII_PHYSID2) { 3214 /* Some internal PHYs don't have a model number. */ 3215 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3216 /* Then there is the 6165 family. It gets is 3217 * PHYs correct. But it can also have two 3218 * SERDES interfaces in the PHY address 3219 * space. And these don't have a model 3220 * number. But they are not PHYs, so we don't 3221 * want to give them something a PHY driver 3222 * will recognise. 3223 * 3224 * Use the mv88e6390 family model number 3225 * instead, for anything which really could be 3226 * a PHY, 3227 */ 3228 if (!(val & 0x3f0)) 3229 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3230 } 3231 3232 return err ? err : val; 3233 } 3234 3235 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3236 { 3237 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3238 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3239 int err; 3240 3241 if (!chip->info->ops->phy_write) 3242 return -EOPNOTSUPP; 3243 3244 mv88e6xxx_reg_lock(chip); 3245 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3246 mv88e6xxx_reg_unlock(chip); 3247 3248 return err; 3249 } 3250 3251 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3252 struct device_node *np, 3253 bool external) 3254 { 3255 static int index; 3256 struct mv88e6xxx_mdio_bus *mdio_bus; 3257 struct mii_bus *bus; 3258 int err; 3259 3260 if (external) { 3261 mv88e6xxx_reg_lock(chip); 3262 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3263 mv88e6xxx_reg_unlock(chip); 3264 3265 if (err) 3266 return err; 3267 } 3268 3269 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3270 if (!bus) 3271 return -ENOMEM; 3272 3273 mdio_bus = bus->priv; 3274 mdio_bus->bus = bus; 3275 mdio_bus->chip = chip; 3276 INIT_LIST_HEAD(&mdio_bus->list); 3277 mdio_bus->external = external; 3278 3279 if (np) { 3280 bus->name = np->full_name; 3281 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3282 } else { 3283 bus->name = "mv88e6xxx SMI"; 3284 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3285 } 3286 3287 bus->read = mv88e6xxx_mdio_read; 3288 bus->write = mv88e6xxx_mdio_write; 3289 bus->parent = chip->dev; 3290 3291 if (!external) { 3292 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3293 if (err) 3294 return err; 3295 } 3296 3297 err = of_mdiobus_register(bus, np); 3298 if (err) { 3299 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3300 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3301 return err; 3302 } 3303 3304 if (external) 3305 list_add_tail(&mdio_bus->list, &chip->mdios); 3306 else 3307 list_add(&mdio_bus->list, &chip->mdios); 3308 3309 return 0; 3310 } 3311 3312 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 3313 { .compatible = "marvell,mv88e6xxx-mdio-external", 3314 .data = (void *)true }, 3315 { }, 3316 }; 3317 3318 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3319 3320 { 3321 struct mv88e6xxx_mdio_bus *mdio_bus; 3322 struct mii_bus *bus; 3323 3324 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3325 bus = mdio_bus->bus; 3326 3327 if (!mdio_bus->external) 3328 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3329 3330 mdiobus_unregister(bus); 3331 } 3332 } 3333 3334 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3335 struct device_node *np) 3336 { 3337 const struct of_device_id *match; 3338 struct device_node *child; 3339 int err; 3340 3341 /* Always register one mdio bus for the internal/default mdio 3342 * bus. This maybe represented in the device tree, but is 3343 * optional. 3344 */ 3345 child = of_get_child_by_name(np, "mdio"); 3346 err = mv88e6xxx_mdio_register(chip, child, false); 3347 if (err) 3348 return err; 3349 3350 /* Walk the device tree, and see if there are any other nodes 3351 * which say they are compatible with the external mdio 3352 * bus. 3353 */ 3354 for_each_available_child_of_node(np, child) { 3355 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3356 if (match) { 3357 err = mv88e6xxx_mdio_register(chip, child, true); 3358 if (err) { 3359 mv88e6xxx_mdios_unregister(chip); 3360 of_node_put(child); 3361 return err; 3362 } 3363 } 3364 } 3365 3366 return 0; 3367 } 3368 3369 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3370 { 3371 struct mv88e6xxx_chip *chip = ds->priv; 3372 3373 return chip->eeprom_len; 3374 } 3375 3376 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3377 struct ethtool_eeprom *eeprom, u8 *data) 3378 { 3379 struct mv88e6xxx_chip *chip = ds->priv; 3380 int err; 3381 3382 if (!chip->info->ops->get_eeprom) 3383 return -EOPNOTSUPP; 3384 3385 mv88e6xxx_reg_lock(chip); 3386 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3387 mv88e6xxx_reg_unlock(chip); 3388 3389 if (err) 3390 return err; 3391 3392 eeprom->magic = 0xc3ec4951; 3393 3394 return 0; 3395 } 3396 3397 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3398 struct ethtool_eeprom *eeprom, u8 *data) 3399 { 3400 struct mv88e6xxx_chip *chip = ds->priv; 3401 int err; 3402 3403 if (!chip->info->ops->set_eeprom) 3404 return -EOPNOTSUPP; 3405 3406 if (eeprom->magic != 0xc3ec4951) 3407 return -EINVAL; 3408 3409 mv88e6xxx_reg_lock(chip); 3410 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3411 mv88e6xxx_reg_unlock(chip); 3412 3413 return err; 3414 } 3415 3416 static const struct mv88e6xxx_ops mv88e6085_ops = { 3417 /* MV88E6XXX_FAMILY_6097 */ 3418 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3419 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3420 .irl_init_all = mv88e6352_g2_irl_init_all, 3421 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3422 .phy_read = mv88e6185_phy_ppu_read, 3423 .phy_write = mv88e6185_phy_ppu_write, 3424 .port_set_link = mv88e6xxx_port_set_link, 3425 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3426 .port_tag_remap = mv88e6095_port_tag_remap, 3427 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3428 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3429 .port_set_ether_type = mv88e6351_port_set_ether_type, 3430 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3431 .port_pause_limit = mv88e6097_port_pause_limit, 3432 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3433 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3434 .port_get_cmode = mv88e6185_port_get_cmode, 3435 .port_setup_message_port = mv88e6xxx_setup_message_port, 3436 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3437 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3438 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3439 .stats_get_strings = mv88e6095_stats_get_strings, 3440 .stats_get_stats = mv88e6095_stats_get_stats, 3441 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3442 .set_egress_port = mv88e6095_g1_set_egress_port, 3443 .watchdog_ops = &mv88e6097_watchdog_ops, 3444 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3445 .pot_clear = mv88e6xxx_g2_pot_clear, 3446 .ppu_enable = mv88e6185_g1_ppu_enable, 3447 .ppu_disable = mv88e6185_g1_ppu_disable, 3448 .reset = mv88e6185_g1_reset, 3449 .rmu_disable = mv88e6085_g1_rmu_disable, 3450 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3451 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3452 .phylink_validate = mv88e6185_phylink_validate, 3453 }; 3454 3455 static const struct mv88e6xxx_ops mv88e6095_ops = { 3456 /* MV88E6XXX_FAMILY_6095 */ 3457 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3458 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3459 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3460 .phy_read = mv88e6185_phy_ppu_read, 3461 .phy_write = mv88e6185_phy_ppu_write, 3462 .port_set_link = mv88e6xxx_port_set_link, 3463 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3464 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3465 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3466 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3467 .port_get_cmode = mv88e6185_port_get_cmode, 3468 .port_setup_message_port = mv88e6xxx_setup_message_port, 3469 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3470 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3471 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3472 .stats_get_strings = mv88e6095_stats_get_strings, 3473 .stats_get_stats = mv88e6095_stats_get_stats, 3474 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3475 .ppu_enable = mv88e6185_g1_ppu_enable, 3476 .ppu_disable = mv88e6185_g1_ppu_disable, 3477 .reset = mv88e6185_g1_reset, 3478 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3479 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3480 .phylink_validate = mv88e6185_phylink_validate, 3481 }; 3482 3483 static const struct mv88e6xxx_ops mv88e6097_ops = { 3484 /* MV88E6XXX_FAMILY_6097 */ 3485 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3486 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3487 .irl_init_all = mv88e6352_g2_irl_init_all, 3488 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3489 .phy_read = mv88e6xxx_g2_smi_phy_read, 3490 .phy_write = mv88e6xxx_g2_smi_phy_write, 3491 .port_set_link = mv88e6xxx_port_set_link, 3492 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3493 .port_tag_remap = mv88e6095_port_tag_remap, 3494 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3495 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3496 .port_set_ether_type = mv88e6351_port_set_ether_type, 3497 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3498 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3499 .port_pause_limit = mv88e6097_port_pause_limit, 3500 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3501 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3502 .port_get_cmode = mv88e6185_port_get_cmode, 3503 .port_setup_message_port = mv88e6xxx_setup_message_port, 3504 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3505 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3506 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3507 .stats_get_strings = mv88e6095_stats_get_strings, 3508 .stats_get_stats = mv88e6095_stats_get_stats, 3509 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3510 .set_egress_port = mv88e6095_g1_set_egress_port, 3511 .watchdog_ops = &mv88e6097_watchdog_ops, 3512 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3513 .pot_clear = mv88e6xxx_g2_pot_clear, 3514 .reset = mv88e6352_g1_reset, 3515 .rmu_disable = mv88e6085_g1_rmu_disable, 3516 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3517 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3518 .phylink_validate = mv88e6185_phylink_validate, 3519 }; 3520 3521 static const struct mv88e6xxx_ops mv88e6123_ops = { 3522 /* MV88E6XXX_FAMILY_6165 */ 3523 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3524 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3525 .irl_init_all = mv88e6352_g2_irl_init_all, 3526 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3527 .phy_read = mv88e6xxx_g2_smi_phy_read, 3528 .phy_write = mv88e6xxx_g2_smi_phy_write, 3529 .port_set_link = mv88e6xxx_port_set_link, 3530 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3531 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3532 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3533 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3534 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3535 .port_get_cmode = mv88e6185_port_get_cmode, 3536 .port_setup_message_port = mv88e6xxx_setup_message_port, 3537 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3538 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3539 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3540 .stats_get_strings = mv88e6095_stats_get_strings, 3541 .stats_get_stats = mv88e6095_stats_get_stats, 3542 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3543 .set_egress_port = mv88e6095_g1_set_egress_port, 3544 .watchdog_ops = &mv88e6097_watchdog_ops, 3545 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3546 .pot_clear = mv88e6xxx_g2_pot_clear, 3547 .reset = mv88e6352_g1_reset, 3548 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3549 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3550 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3551 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3552 .phylink_validate = mv88e6185_phylink_validate, 3553 }; 3554 3555 static const struct mv88e6xxx_ops mv88e6131_ops = { 3556 /* MV88E6XXX_FAMILY_6185 */ 3557 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3558 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3559 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3560 .phy_read = mv88e6185_phy_ppu_read, 3561 .phy_write = mv88e6185_phy_ppu_write, 3562 .port_set_link = mv88e6xxx_port_set_link, 3563 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3564 .port_tag_remap = mv88e6095_port_tag_remap, 3565 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3566 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3567 .port_set_ether_type = mv88e6351_port_set_ether_type, 3568 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3569 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3570 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3571 .port_pause_limit = mv88e6097_port_pause_limit, 3572 .port_set_pause = mv88e6185_port_set_pause, 3573 .port_get_cmode = mv88e6185_port_get_cmode, 3574 .port_setup_message_port = mv88e6xxx_setup_message_port, 3575 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3576 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3577 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3578 .stats_get_strings = mv88e6095_stats_get_strings, 3579 .stats_get_stats = mv88e6095_stats_get_stats, 3580 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3581 .set_egress_port = mv88e6095_g1_set_egress_port, 3582 .watchdog_ops = &mv88e6097_watchdog_ops, 3583 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3584 .ppu_enable = mv88e6185_g1_ppu_enable, 3585 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3586 .ppu_disable = mv88e6185_g1_ppu_disable, 3587 .reset = mv88e6185_g1_reset, 3588 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3589 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3590 .phylink_validate = mv88e6185_phylink_validate, 3591 }; 3592 3593 static const struct mv88e6xxx_ops mv88e6141_ops = { 3594 /* MV88E6XXX_FAMILY_6341 */ 3595 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3596 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3597 .irl_init_all = mv88e6352_g2_irl_init_all, 3598 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3599 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3600 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3601 .phy_read = mv88e6xxx_g2_smi_phy_read, 3602 .phy_write = mv88e6xxx_g2_smi_phy_write, 3603 .port_set_link = mv88e6xxx_port_set_link, 3604 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3605 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3606 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3607 .port_tag_remap = mv88e6095_port_tag_remap, 3608 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3609 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3610 .port_set_ether_type = mv88e6351_port_set_ether_type, 3611 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3612 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3613 .port_pause_limit = mv88e6097_port_pause_limit, 3614 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3615 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3616 .port_get_cmode = mv88e6352_port_get_cmode, 3617 .port_set_cmode = mv88e6341_port_set_cmode, 3618 .port_setup_message_port = mv88e6xxx_setup_message_port, 3619 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3620 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3621 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3622 .stats_get_strings = mv88e6320_stats_get_strings, 3623 .stats_get_stats = mv88e6390_stats_get_stats, 3624 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3625 .set_egress_port = mv88e6390_g1_set_egress_port, 3626 .watchdog_ops = &mv88e6390_watchdog_ops, 3627 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3628 .pot_clear = mv88e6xxx_g2_pot_clear, 3629 .reset = mv88e6352_g1_reset, 3630 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3631 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3632 .serdes_power = mv88e6390_serdes_power, 3633 .serdes_get_lane = mv88e6341_serdes_get_lane, 3634 /* Check status register pause & lpa register */ 3635 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3636 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3637 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3638 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3639 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3640 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3641 .serdes_irq_status = mv88e6390_serdes_irq_status, 3642 .gpio_ops = &mv88e6352_gpio_ops, 3643 .phylink_validate = mv88e6341_phylink_validate, 3644 }; 3645 3646 static const struct mv88e6xxx_ops mv88e6161_ops = { 3647 /* MV88E6XXX_FAMILY_6165 */ 3648 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3649 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3650 .irl_init_all = mv88e6352_g2_irl_init_all, 3651 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3652 .phy_read = mv88e6xxx_g2_smi_phy_read, 3653 .phy_write = mv88e6xxx_g2_smi_phy_write, 3654 .port_set_link = mv88e6xxx_port_set_link, 3655 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3656 .port_tag_remap = mv88e6095_port_tag_remap, 3657 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3658 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3659 .port_set_ether_type = mv88e6351_port_set_ether_type, 3660 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3661 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3662 .port_pause_limit = mv88e6097_port_pause_limit, 3663 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3664 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3665 .port_get_cmode = mv88e6185_port_get_cmode, 3666 .port_setup_message_port = mv88e6xxx_setup_message_port, 3667 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3668 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3669 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3670 .stats_get_strings = mv88e6095_stats_get_strings, 3671 .stats_get_stats = mv88e6095_stats_get_stats, 3672 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3673 .set_egress_port = mv88e6095_g1_set_egress_port, 3674 .watchdog_ops = &mv88e6097_watchdog_ops, 3675 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3676 .pot_clear = mv88e6xxx_g2_pot_clear, 3677 .reset = mv88e6352_g1_reset, 3678 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3679 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3680 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3681 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3682 .avb_ops = &mv88e6165_avb_ops, 3683 .ptp_ops = &mv88e6165_ptp_ops, 3684 .phylink_validate = mv88e6185_phylink_validate, 3685 }; 3686 3687 static const struct mv88e6xxx_ops mv88e6165_ops = { 3688 /* MV88E6XXX_FAMILY_6165 */ 3689 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3690 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3691 .irl_init_all = mv88e6352_g2_irl_init_all, 3692 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3693 .phy_read = mv88e6165_phy_read, 3694 .phy_write = mv88e6165_phy_write, 3695 .port_set_link = mv88e6xxx_port_set_link, 3696 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3697 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3698 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3699 .port_get_cmode = mv88e6185_port_get_cmode, 3700 .port_setup_message_port = mv88e6xxx_setup_message_port, 3701 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3702 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3703 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3704 .stats_get_strings = mv88e6095_stats_get_strings, 3705 .stats_get_stats = mv88e6095_stats_get_stats, 3706 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3707 .set_egress_port = mv88e6095_g1_set_egress_port, 3708 .watchdog_ops = &mv88e6097_watchdog_ops, 3709 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3710 .pot_clear = mv88e6xxx_g2_pot_clear, 3711 .reset = mv88e6352_g1_reset, 3712 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3713 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3714 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3715 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3716 .avb_ops = &mv88e6165_avb_ops, 3717 .ptp_ops = &mv88e6165_ptp_ops, 3718 .phylink_validate = mv88e6185_phylink_validate, 3719 }; 3720 3721 static const struct mv88e6xxx_ops mv88e6171_ops = { 3722 /* MV88E6XXX_FAMILY_6351 */ 3723 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3724 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3725 .irl_init_all = mv88e6352_g2_irl_init_all, 3726 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3727 .phy_read = mv88e6xxx_g2_smi_phy_read, 3728 .phy_write = mv88e6xxx_g2_smi_phy_write, 3729 .port_set_link = mv88e6xxx_port_set_link, 3730 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3731 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3732 .port_tag_remap = mv88e6095_port_tag_remap, 3733 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3734 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3735 .port_set_ether_type = mv88e6351_port_set_ether_type, 3736 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3737 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3738 .port_pause_limit = mv88e6097_port_pause_limit, 3739 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3740 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3741 .port_get_cmode = mv88e6352_port_get_cmode, 3742 .port_setup_message_port = mv88e6xxx_setup_message_port, 3743 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3744 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3745 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3746 .stats_get_strings = mv88e6095_stats_get_strings, 3747 .stats_get_stats = mv88e6095_stats_get_stats, 3748 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3749 .set_egress_port = mv88e6095_g1_set_egress_port, 3750 .watchdog_ops = &mv88e6097_watchdog_ops, 3751 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3752 .pot_clear = mv88e6xxx_g2_pot_clear, 3753 .reset = mv88e6352_g1_reset, 3754 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3755 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3756 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3757 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3758 .phylink_validate = mv88e6185_phylink_validate, 3759 }; 3760 3761 static const struct mv88e6xxx_ops mv88e6172_ops = { 3762 /* MV88E6XXX_FAMILY_6352 */ 3763 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3764 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3765 .irl_init_all = mv88e6352_g2_irl_init_all, 3766 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3767 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3768 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3769 .phy_read = mv88e6xxx_g2_smi_phy_read, 3770 .phy_write = mv88e6xxx_g2_smi_phy_write, 3771 .port_set_link = mv88e6xxx_port_set_link, 3772 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3773 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3774 .port_tag_remap = mv88e6095_port_tag_remap, 3775 .port_set_policy = mv88e6352_port_set_policy, 3776 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3777 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3778 .port_set_ether_type = mv88e6351_port_set_ether_type, 3779 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3780 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3781 .port_pause_limit = mv88e6097_port_pause_limit, 3782 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3783 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3784 .port_get_cmode = mv88e6352_port_get_cmode, 3785 .port_setup_message_port = mv88e6xxx_setup_message_port, 3786 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3787 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3788 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3789 .stats_get_strings = mv88e6095_stats_get_strings, 3790 .stats_get_stats = mv88e6095_stats_get_stats, 3791 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3792 .set_egress_port = mv88e6095_g1_set_egress_port, 3793 .watchdog_ops = &mv88e6097_watchdog_ops, 3794 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3795 .pot_clear = mv88e6xxx_g2_pot_clear, 3796 .reset = mv88e6352_g1_reset, 3797 .rmu_disable = mv88e6352_g1_rmu_disable, 3798 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3799 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3800 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3801 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3802 .serdes_get_lane = mv88e6352_serdes_get_lane, 3803 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3804 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3805 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3806 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3807 .serdes_power = mv88e6352_serdes_power, 3808 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3809 .serdes_get_regs = mv88e6352_serdes_get_regs, 3810 .gpio_ops = &mv88e6352_gpio_ops, 3811 .phylink_validate = mv88e6352_phylink_validate, 3812 }; 3813 3814 static const struct mv88e6xxx_ops mv88e6175_ops = { 3815 /* MV88E6XXX_FAMILY_6351 */ 3816 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3817 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3818 .irl_init_all = mv88e6352_g2_irl_init_all, 3819 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3820 .phy_read = mv88e6xxx_g2_smi_phy_read, 3821 .phy_write = mv88e6xxx_g2_smi_phy_write, 3822 .port_set_link = mv88e6xxx_port_set_link, 3823 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3824 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3825 .port_tag_remap = mv88e6095_port_tag_remap, 3826 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3827 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3828 .port_set_ether_type = mv88e6351_port_set_ether_type, 3829 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3830 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3831 .port_pause_limit = mv88e6097_port_pause_limit, 3832 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3833 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3834 .port_get_cmode = mv88e6352_port_get_cmode, 3835 .port_setup_message_port = mv88e6xxx_setup_message_port, 3836 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3837 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3838 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3839 .stats_get_strings = mv88e6095_stats_get_strings, 3840 .stats_get_stats = mv88e6095_stats_get_stats, 3841 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3842 .set_egress_port = mv88e6095_g1_set_egress_port, 3843 .watchdog_ops = &mv88e6097_watchdog_ops, 3844 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3845 .pot_clear = mv88e6xxx_g2_pot_clear, 3846 .reset = mv88e6352_g1_reset, 3847 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3848 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3849 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3850 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3851 .phylink_validate = mv88e6185_phylink_validate, 3852 }; 3853 3854 static const struct mv88e6xxx_ops mv88e6176_ops = { 3855 /* MV88E6XXX_FAMILY_6352 */ 3856 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3857 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3858 .irl_init_all = mv88e6352_g2_irl_init_all, 3859 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3860 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3861 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3862 .phy_read = mv88e6xxx_g2_smi_phy_read, 3863 .phy_write = mv88e6xxx_g2_smi_phy_write, 3864 .port_set_link = mv88e6xxx_port_set_link, 3865 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3866 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3867 .port_tag_remap = mv88e6095_port_tag_remap, 3868 .port_set_policy = mv88e6352_port_set_policy, 3869 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3870 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3871 .port_set_ether_type = mv88e6351_port_set_ether_type, 3872 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3873 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3874 .port_pause_limit = mv88e6097_port_pause_limit, 3875 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3876 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3877 .port_get_cmode = mv88e6352_port_get_cmode, 3878 .port_setup_message_port = mv88e6xxx_setup_message_port, 3879 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3880 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3881 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3882 .stats_get_strings = mv88e6095_stats_get_strings, 3883 .stats_get_stats = mv88e6095_stats_get_stats, 3884 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3885 .set_egress_port = mv88e6095_g1_set_egress_port, 3886 .watchdog_ops = &mv88e6097_watchdog_ops, 3887 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3888 .pot_clear = mv88e6xxx_g2_pot_clear, 3889 .reset = mv88e6352_g1_reset, 3890 .rmu_disable = mv88e6352_g1_rmu_disable, 3891 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3892 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3893 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3894 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3895 .serdes_get_lane = mv88e6352_serdes_get_lane, 3896 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3897 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3898 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3899 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3900 .serdes_power = mv88e6352_serdes_power, 3901 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3902 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3903 .serdes_irq_status = mv88e6352_serdes_irq_status, 3904 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3905 .serdes_get_regs = mv88e6352_serdes_get_regs, 3906 .gpio_ops = &mv88e6352_gpio_ops, 3907 .phylink_validate = mv88e6352_phylink_validate, 3908 }; 3909 3910 static const struct mv88e6xxx_ops mv88e6185_ops = { 3911 /* MV88E6XXX_FAMILY_6185 */ 3912 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3913 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3914 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3915 .phy_read = mv88e6185_phy_ppu_read, 3916 .phy_write = mv88e6185_phy_ppu_write, 3917 .port_set_link = mv88e6xxx_port_set_link, 3918 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3919 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3920 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3921 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3922 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3923 .port_set_pause = mv88e6185_port_set_pause, 3924 .port_get_cmode = mv88e6185_port_get_cmode, 3925 .port_setup_message_port = mv88e6xxx_setup_message_port, 3926 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3927 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3928 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3929 .stats_get_strings = mv88e6095_stats_get_strings, 3930 .stats_get_stats = mv88e6095_stats_get_stats, 3931 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3932 .set_egress_port = mv88e6095_g1_set_egress_port, 3933 .watchdog_ops = &mv88e6097_watchdog_ops, 3934 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3935 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3936 .ppu_enable = mv88e6185_g1_ppu_enable, 3937 .ppu_disable = mv88e6185_g1_ppu_disable, 3938 .reset = mv88e6185_g1_reset, 3939 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3940 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3941 .phylink_validate = mv88e6185_phylink_validate, 3942 }; 3943 3944 static const struct mv88e6xxx_ops mv88e6190_ops = { 3945 /* MV88E6XXX_FAMILY_6390 */ 3946 .setup_errata = mv88e6390_setup_errata, 3947 .irl_init_all = mv88e6390_g2_irl_init_all, 3948 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3949 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3950 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3951 .phy_read = mv88e6xxx_g2_smi_phy_read, 3952 .phy_write = mv88e6xxx_g2_smi_phy_write, 3953 .port_set_link = mv88e6xxx_port_set_link, 3954 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3955 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3956 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3957 .port_tag_remap = mv88e6390_port_tag_remap, 3958 .port_set_policy = mv88e6352_port_set_policy, 3959 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3960 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3961 .port_set_ether_type = mv88e6351_port_set_ether_type, 3962 .port_pause_limit = mv88e6390_port_pause_limit, 3963 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3964 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3965 .port_get_cmode = mv88e6352_port_get_cmode, 3966 .port_set_cmode = mv88e6390_port_set_cmode, 3967 .port_setup_message_port = mv88e6xxx_setup_message_port, 3968 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3969 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3970 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3971 .stats_get_strings = mv88e6320_stats_get_strings, 3972 .stats_get_stats = mv88e6390_stats_get_stats, 3973 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3974 .set_egress_port = mv88e6390_g1_set_egress_port, 3975 .watchdog_ops = &mv88e6390_watchdog_ops, 3976 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3977 .pot_clear = mv88e6xxx_g2_pot_clear, 3978 .reset = mv88e6352_g1_reset, 3979 .rmu_disable = mv88e6390_g1_rmu_disable, 3980 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3981 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3982 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3983 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3984 .serdes_power = mv88e6390_serdes_power, 3985 .serdes_get_lane = mv88e6390_serdes_get_lane, 3986 /* Check status register pause & lpa register */ 3987 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3988 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3989 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3990 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3991 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3992 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3993 .serdes_irq_status = mv88e6390_serdes_irq_status, 3994 .serdes_get_strings = mv88e6390_serdes_get_strings, 3995 .serdes_get_stats = mv88e6390_serdes_get_stats, 3996 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3997 .serdes_get_regs = mv88e6390_serdes_get_regs, 3998 .gpio_ops = &mv88e6352_gpio_ops, 3999 .phylink_validate = mv88e6390_phylink_validate, 4000 }; 4001 4002 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4003 /* MV88E6XXX_FAMILY_6390 */ 4004 .setup_errata = mv88e6390_setup_errata, 4005 .irl_init_all = mv88e6390_g2_irl_init_all, 4006 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4007 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4008 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4009 .phy_read = mv88e6xxx_g2_smi_phy_read, 4010 .phy_write = mv88e6xxx_g2_smi_phy_write, 4011 .port_set_link = mv88e6xxx_port_set_link, 4012 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4013 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4014 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4015 .port_tag_remap = mv88e6390_port_tag_remap, 4016 .port_set_policy = mv88e6352_port_set_policy, 4017 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4018 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4019 .port_set_ether_type = mv88e6351_port_set_ether_type, 4020 .port_pause_limit = mv88e6390_port_pause_limit, 4021 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4022 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4023 .port_get_cmode = mv88e6352_port_get_cmode, 4024 .port_set_cmode = mv88e6390x_port_set_cmode, 4025 .port_setup_message_port = mv88e6xxx_setup_message_port, 4026 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4027 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4028 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4029 .stats_get_strings = mv88e6320_stats_get_strings, 4030 .stats_get_stats = mv88e6390_stats_get_stats, 4031 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4032 .set_egress_port = mv88e6390_g1_set_egress_port, 4033 .watchdog_ops = &mv88e6390_watchdog_ops, 4034 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4035 .pot_clear = mv88e6xxx_g2_pot_clear, 4036 .reset = mv88e6352_g1_reset, 4037 .rmu_disable = mv88e6390_g1_rmu_disable, 4038 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4039 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4040 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4041 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4042 .serdes_power = mv88e6390_serdes_power, 4043 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4044 /* Check status register pause & lpa register */ 4045 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4046 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4047 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4048 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4049 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4050 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4051 .serdes_irq_status = mv88e6390_serdes_irq_status, 4052 .serdes_get_strings = mv88e6390_serdes_get_strings, 4053 .serdes_get_stats = mv88e6390_serdes_get_stats, 4054 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4055 .serdes_get_regs = mv88e6390_serdes_get_regs, 4056 .gpio_ops = &mv88e6352_gpio_ops, 4057 .phylink_validate = mv88e6390x_phylink_validate, 4058 }; 4059 4060 static const struct mv88e6xxx_ops mv88e6191_ops = { 4061 /* MV88E6XXX_FAMILY_6390 */ 4062 .setup_errata = mv88e6390_setup_errata, 4063 .irl_init_all = mv88e6390_g2_irl_init_all, 4064 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4065 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4066 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4067 .phy_read = mv88e6xxx_g2_smi_phy_read, 4068 .phy_write = mv88e6xxx_g2_smi_phy_write, 4069 .port_set_link = mv88e6xxx_port_set_link, 4070 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4071 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4072 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4073 .port_tag_remap = mv88e6390_port_tag_remap, 4074 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4075 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4076 .port_set_ether_type = mv88e6351_port_set_ether_type, 4077 .port_pause_limit = mv88e6390_port_pause_limit, 4078 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4079 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4080 .port_get_cmode = mv88e6352_port_get_cmode, 4081 .port_set_cmode = mv88e6390_port_set_cmode, 4082 .port_setup_message_port = mv88e6xxx_setup_message_port, 4083 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4084 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4085 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4086 .stats_get_strings = mv88e6320_stats_get_strings, 4087 .stats_get_stats = mv88e6390_stats_get_stats, 4088 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4089 .set_egress_port = mv88e6390_g1_set_egress_port, 4090 .watchdog_ops = &mv88e6390_watchdog_ops, 4091 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4092 .pot_clear = mv88e6xxx_g2_pot_clear, 4093 .reset = mv88e6352_g1_reset, 4094 .rmu_disable = mv88e6390_g1_rmu_disable, 4095 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4096 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4097 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4098 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4099 .serdes_power = mv88e6390_serdes_power, 4100 .serdes_get_lane = mv88e6390_serdes_get_lane, 4101 /* Check status register pause & lpa register */ 4102 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4103 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4104 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4105 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4106 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4107 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4108 .serdes_irq_status = mv88e6390_serdes_irq_status, 4109 .serdes_get_strings = mv88e6390_serdes_get_strings, 4110 .serdes_get_stats = mv88e6390_serdes_get_stats, 4111 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4112 .serdes_get_regs = mv88e6390_serdes_get_regs, 4113 .avb_ops = &mv88e6390_avb_ops, 4114 .ptp_ops = &mv88e6352_ptp_ops, 4115 .phylink_validate = mv88e6390_phylink_validate, 4116 }; 4117 4118 static const struct mv88e6xxx_ops mv88e6240_ops = { 4119 /* MV88E6XXX_FAMILY_6352 */ 4120 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4121 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4122 .irl_init_all = mv88e6352_g2_irl_init_all, 4123 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4124 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4125 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4126 .phy_read = mv88e6xxx_g2_smi_phy_read, 4127 .phy_write = mv88e6xxx_g2_smi_phy_write, 4128 .port_set_link = mv88e6xxx_port_set_link, 4129 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4130 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4131 .port_tag_remap = mv88e6095_port_tag_remap, 4132 .port_set_policy = mv88e6352_port_set_policy, 4133 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4134 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4135 .port_set_ether_type = mv88e6351_port_set_ether_type, 4136 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4137 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4138 .port_pause_limit = mv88e6097_port_pause_limit, 4139 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4140 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4141 .port_get_cmode = mv88e6352_port_get_cmode, 4142 .port_setup_message_port = mv88e6xxx_setup_message_port, 4143 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4144 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4145 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4146 .stats_get_strings = mv88e6095_stats_get_strings, 4147 .stats_get_stats = mv88e6095_stats_get_stats, 4148 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4149 .set_egress_port = mv88e6095_g1_set_egress_port, 4150 .watchdog_ops = &mv88e6097_watchdog_ops, 4151 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4152 .pot_clear = mv88e6xxx_g2_pot_clear, 4153 .reset = mv88e6352_g1_reset, 4154 .rmu_disable = mv88e6352_g1_rmu_disable, 4155 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4156 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4157 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4158 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4159 .serdes_get_lane = mv88e6352_serdes_get_lane, 4160 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4161 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4162 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4163 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4164 .serdes_power = mv88e6352_serdes_power, 4165 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4166 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4167 .serdes_irq_status = mv88e6352_serdes_irq_status, 4168 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4169 .serdes_get_regs = mv88e6352_serdes_get_regs, 4170 .gpio_ops = &mv88e6352_gpio_ops, 4171 .avb_ops = &mv88e6352_avb_ops, 4172 .ptp_ops = &mv88e6352_ptp_ops, 4173 .phylink_validate = mv88e6352_phylink_validate, 4174 }; 4175 4176 static const struct mv88e6xxx_ops mv88e6250_ops = { 4177 /* MV88E6XXX_FAMILY_6250 */ 4178 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4179 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4180 .irl_init_all = mv88e6352_g2_irl_init_all, 4181 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4182 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4183 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4184 .phy_read = mv88e6xxx_g2_smi_phy_read, 4185 .phy_write = mv88e6xxx_g2_smi_phy_write, 4186 .port_set_link = mv88e6xxx_port_set_link, 4187 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4188 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4189 .port_tag_remap = mv88e6095_port_tag_remap, 4190 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4191 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4192 .port_set_ether_type = mv88e6351_port_set_ether_type, 4193 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4194 .port_pause_limit = mv88e6097_port_pause_limit, 4195 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4196 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4197 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4198 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4199 .stats_get_strings = mv88e6250_stats_get_strings, 4200 .stats_get_stats = mv88e6250_stats_get_stats, 4201 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4202 .set_egress_port = mv88e6095_g1_set_egress_port, 4203 .watchdog_ops = &mv88e6250_watchdog_ops, 4204 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4205 .pot_clear = mv88e6xxx_g2_pot_clear, 4206 .reset = mv88e6250_g1_reset, 4207 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4208 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4209 .avb_ops = &mv88e6352_avb_ops, 4210 .ptp_ops = &mv88e6250_ptp_ops, 4211 .phylink_validate = mv88e6065_phylink_validate, 4212 }; 4213 4214 static const struct mv88e6xxx_ops mv88e6290_ops = { 4215 /* MV88E6XXX_FAMILY_6390 */ 4216 .setup_errata = mv88e6390_setup_errata, 4217 .irl_init_all = mv88e6390_g2_irl_init_all, 4218 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4219 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4221 .phy_read = mv88e6xxx_g2_smi_phy_read, 4222 .phy_write = mv88e6xxx_g2_smi_phy_write, 4223 .port_set_link = mv88e6xxx_port_set_link, 4224 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4225 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4226 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4227 .port_tag_remap = mv88e6390_port_tag_remap, 4228 .port_set_policy = mv88e6352_port_set_policy, 4229 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4230 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4231 .port_set_ether_type = mv88e6351_port_set_ether_type, 4232 .port_pause_limit = mv88e6390_port_pause_limit, 4233 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4234 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4235 .port_get_cmode = mv88e6352_port_get_cmode, 4236 .port_set_cmode = mv88e6390_port_set_cmode, 4237 .port_setup_message_port = mv88e6xxx_setup_message_port, 4238 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4239 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4240 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4241 .stats_get_strings = mv88e6320_stats_get_strings, 4242 .stats_get_stats = mv88e6390_stats_get_stats, 4243 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4244 .set_egress_port = mv88e6390_g1_set_egress_port, 4245 .watchdog_ops = &mv88e6390_watchdog_ops, 4246 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4247 .pot_clear = mv88e6xxx_g2_pot_clear, 4248 .reset = mv88e6352_g1_reset, 4249 .rmu_disable = mv88e6390_g1_rmu_disable, 4250 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4251 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4252 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4253 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4254 .serdes_power = mv88e6390_serdes_power, 4255 .serdes_get_lane = mv88e6390_serdes_get_lane, 4256 /* Check status register pause & lpa register */ 4257 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4258 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4259 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4260 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4261 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4262 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4263 .serdes_irq_status = mv88e6390_serdes_irq_status, 4264 .serdes_get_strings = mv88e6390_serdes_get_strings, 4265 .serdes_get_stats = mv88e6390_serdes_get_stats, 4266 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4267 .serdes_get_regs = mv88e6390_serdes_get_regs, 4268 .gpio_ops = &mv88e6352_gpio_ops, 4269 .avb_ops = &mv88e6390_avb_ops, 4270 .ptp_ops = &mv88e6352_ptp_ops, 4271 .phylink_validate = mv88e6390_phylink_validate, 4272 }; 4273 4274 static const struct mv88e6xxx_ops mv88e6320_ops = { 4275 /* MV88E6XXX_FAMILY_6320 */ 4276 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4277 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4278 .irl_init_all = mv88e6352_g2_irl_init_all, 4279 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4280 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4281 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4282 .phy_read = mv88e6xxx_g2_smi_phy_read, 4283 .phy_write = mv88e6xxx_g2_smi_phy_write, 4284 .port_set_link = mv88e6xxx_port_set_link, 4285 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4286 .port_tag_remap = mv88e6095_port_tag_remap, 4287 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4288 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4289 .port_set_ether_type = mv88e6351_port_set_ether_type, 4290 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4291 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4292 .port_pause_limit = mv88e6097_port_pause_limit, 4293 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4294 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4295 .port_get_cmode = mv88e6352_port_get_cmode, 4296 .port_setup_message_port = mv88e6xxx_setup_message_port, 4297 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4298 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4299 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4300 .stats_get_strings = mv88e6320_stats_get_strings, 4301 .stats_get_stats = mv88e6320_stats_get_stats, 4302 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4303 .set_egress_port = mv88e6095_g1_set_egress_port, 4304 .watchdog_ops = &mv88e6390_watchdog_ops, 4305 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4306 .pot_clear = mv88e6xxx_g2_pot_clear, 4307 .reset = mv88e6352_g1_reset, 4308 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4309 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4310 .gpio_ops = &mv88e6352_gpio_ops, 4311 .avb_ops = &mv88e6352_avb_ops, 4312 .ptp_ops = &mv88e6352_ptp_ops, 4313 .phylink_validate = mv88e6185_phylink_validate, 4314 }; 4315 4316 static const struct mv88e6xxx_ops mv88e6321_ops = { 4317 /* MV88E6XXX_FAMILY_6320 */ 4318 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4319 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4320 .irl_init_all = mv88e6352_g2_irl_init_all, 4321 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4322 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4323 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4324 .phy_read = mv88e6xxx_g2_smi_phy_read, 4325 .phy_write = mv88e6xxx_g2_smi_phy_write, 4326 .port_set_link = mv88e6xxx_port_set_link, 4327 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4328 .port_tag_remap = mv88e6095_port_tag_remap, 4329 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4330 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4331 .port_set_ether_type = mv88e6351_port_set_ether_type, 4332 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4333 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4334 .port_pause_limit = mv88e6097_port_pause_limit, 4335 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4336 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4337 .port_get_cmode = mv88e6352_port_get_cmode, 4338 .port_setup_message_port = mv88e6xxx_setup_message_port, 4339 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4340 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4341 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4342 .stats_get_strings = mv88e6320_stats_get_strings, 4343 .stats_get_stats = mv88e6320_stats_get_stats, 4344 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4345 .set_egress_port = mv88e6095_g1_set_egress_port, 4346 .watchdog_ops = &mv88e6390_watchdog_ops, 4347 .reset = mv88e6352_g1_reset, 4348 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4349 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4350 .gpio_ops = &mv88e6352_gpio_ops, 4351 .avb_ops = &mv88e6352_avb_ops, 4352 .ptp_ops = &mv88e6352_ptp_ops, 4353 .phylink_validate = mv88e6185_phylink_validate, 4354 }; 4355 4356 static const struct mv88e6xxx_ops mv88e6341_ops = { 4357 /* MV88E6XXX_FAMILY_6341 */ 4358 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4359 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4360 .irl_init_all = mv88e6352_g2_irl_init_all, 4361 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4362 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4363 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4364 .phy_read = mv88e6xxx_g2_smi_phy_read, 4365 .phy_write = mv88e6xxx_g2_smi_phy_write, 4366 .port_set_link = mv88e6xxx_port_set_link, 4367 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4368 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4369 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4370 .port_tag_remap = mv88e6095_port_tag_remap, 4371 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4372 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4373 .port_set_ether_type = mv88e6351_port_set_ether_type, 4374 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4375 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4376 .port_pause_limit = mv88e6097_port_pause_limit, 4377 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4378 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4379 .port_get_cmode = mv88e6352_port_get_cmode, 4380 .port_set_cmode = mv88e6341_port_set_cmode, 4381 .port_setup_message_port = mv88e6xxx_setup_message_port, 4382 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4383 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4384 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4385 .stats_get_strings = mv88e6320_stats_get_strings, 4386 .stats_get_stats = mv88e6390_stats_get_stats, 4387 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4388 .set_egress_port = mv88e6390_g1_set_egress_port, 4389 .watchdog_ops = &mv88e6390_watchdog_ops, 4390 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4391 .pot_clear = mv88e6xxx_g2_pot_clear, 4392 .reset = mv88e6352_g1_reset, 4393 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4394 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4395 .serdes_power = mv88e6390_serdes_power, 4396 .serdes_get_lane = mv88e6341_serdes_get_lane, 4397 /* Check status register pause & lpa register */ 4398 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4399 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4400 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4401 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4402 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4403 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4404 .serdes_irq_status = mv88e6390_serdes_irq_status, 4405 .gpio_ops = &mv88e6352_gpio_ops, 4406 .avb_ops = &mv88e6390_avb_ops, 4407 .ptp_ops = &mv88e6352_ptp_ops, 4408 .phylink_validate = mv88e6341_phylink_validate, 4409 }; 4410 4411 static const struct mv88e6xxx_ops mv88e6350_ops = { 4412 /* MV88E6XXX_FAMILY_6351 */ 4413 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4414 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4415 .irl_init_all = mv88e6352_g2_irl_init_all, 4416 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4417 .phy_read = mv88e6xxx_g2_smi_phy_read, 4418 .phy_write = mv88e6xxx_g2_smi_phy_write, 4419 .port_set_link = mv88e6xxx_port_set_link, 4420 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4421 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4422 .port_tag_remap = mv88e6095_port_tag_remap, 4423 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4424 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4425 .port_set_ether_type = mv88e6351_port_set_ether_type, 4426 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4427 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4428 .port_pause_limit = mv88e6097_port_pause_limit, 4429 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4430 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4431 .port_get_cmode = mv88e6352_port_get_cmode, 4432 .port_setup_message_port = mv88e6xxx_setup_message_port, 4433 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4434 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4435 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4436 .stats_get_strings = mv88e6095_stats_get_strings, 4437 .stats_get_stats = mv88e6095_stats_get_stats, 4438 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4439 .set_egress_port = mv88e6095_g1_set_egress_port, 4440 .watchdog_ops = &mv88e6097_watchdog_ops, 4441 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4442 .pot_clear = mv88e6xxx_g2_pot_clear, 4443 .reset = mv88e6352_g1_reset, 4444 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4445 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4446 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4447 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4448 .phylink_validate = mv88e6185_phylink_validate, 4449 }; 4450 4451 static const struct mv88e6xxx_ops mv88e6351_ops = { 4452 /* MV88E6XXX_FAMILY_6351 */ 4453 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4454 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4455 .irl_init_all = mv88e6352_g2_irl_init_all, 4456 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4457 .phy_read = mv88e6xxx_g2_smi_phy_read, 4458 .phy_write = mv88e6xxx_g2_smi_phy_write, 4459 .port_set_link = mv88e6xxx_port_set_link, 4460 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4461 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4462 .port_tag_remap = mv88e6095_port_tag_remap, 4463 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4464 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4465 .port_set_ether_type = mv88e6351_port_set_ether_type, 4466 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4467 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4468 .port_pause_limit = mv88e6097_port_pause_limit, 4469 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4470 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4471 .port_get_cmode = mv88e6352_port_get_cmode, 4472 .port_setup_message_port = mv88e6xxx_setup_message_port, 4473 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4474 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4475 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4476 .stats_get_strings = mv88e6095_stats_get_strings, 4477 .stats_get_stats = mv88e6095_stats_get_stats, 4478 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4479 .set_egress_port = mv88e6095_g1_set_egress_port, 4480 .watchdog_ops = &mv88e6097_watchdog_ops, 4481 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4482 .pot_clear = mv88e6xxx_g2_pot_clear, 4483 .reset = mv88e6352_g1_reset, 4484 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4485 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4486 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4487 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4488 .avb_ops = &mv88e6352_avb_ops, 4489 .ptp_ops = &mv88e6352_ptp_ops, 4490 .phylink_validate = mv88e6185_phylink_validate, 4491 }; 4492 4493 static const struct mv88e6xxx_ops mv88e6352_ops = { 4494 /* MV88E6XXX_FAMILY_6352 */ 4495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4496 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4497 .irl_init_all = mv88e6352_g2_irl_init_all, 4498 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4499 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4500 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4501 .phy_read = mv88e6xxx_g2_smi_phy_read, 4502 .phy_write = mv88e6xxx_g2_smi_phy_write, 4503 .port_set_link = mv88e6xxx_port_set_link, 4504 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4505 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4506 .port_tag_remap = mv88e6095_port_tag_remap, 4507 .port_set_policy = mv88e6352_port_set_policy, 4508 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4509 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4510 .port_set_ether_type = mv88e6351_port_set_ether_type, 4511 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4512 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4513 .port_pause_limit = mv88e6097_port_pause_limit, 4514 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4515 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4516 .port_get_cmode = mv88e6352_port_get_cmode, 4517 .port_setup_message_port = mv88e6xxx_setup_message_port, 4518 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4519 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4520 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4521 .stats_get_strings = mv88e6095_stats_get_strings, 4522 .stats_get_stats = mv88e6095_stats_get_stats, 4523 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4524 .set_egress_port = mv88e6095_g1_set_egress_port, 4525 .watchdog_ops = &mv88e6097_watchdog_ops, 4526 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4527 .pot_clear = mv88e6xxx_g2_pot_clear, 4528 .reset = mv88e6352_g1_reset, 4529 .rmu_disable = mv88e6352_g1_rmu_disable, 4530 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4531 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4532 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4533 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4534 .serdes_get_lane = mv88e6352_serdes_get_lane, 4535 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4536 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4537 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4538 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4539 .serdes_power = mv88e6352_serdes_power, 4540 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4541 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4542 .serdes_irq_status = mv88e6352_serdes_irq_status, 4543 .gpio_ops = &mv88e6352_gpio_ops, 4544 .avb_ops = &mv88e6352_avb_ops, 4545 .ptp_ops = &mv88e6352_ptp_ops, 4546 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4547 .serdes_get_strings = mv88e6352_serdes_get_strings, 4548 .serdes_get_stats = mv88e6352_serdes_get_stats, 4549 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4550 .serdes_get_regs = mv88e6352_serdes_get_regs, 4551 .phylink_validate = mv88e6352_phylink_validate, 4552 }; 4553 4554 static const struct mv88e6xxx_ops mv88e6390_ops = { 4555 /* MV88E6XXX_FAMILY_6390 */ 4556 .setup_errata = mv88e6390_setup_errata, 4557 .irl_init_all = mv88e6390_g2_irl_init_all, 4558 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4559 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4560 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4561 .phy_read = mv88e6xxx_g2_smi_phy_read, 4562 .phy_write = mv88e6xxx_g2_smi_phy_write, 4563 .port_set_link = mv88e6xxx_port_set_link, 4564 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4565 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4566 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4567 .port_tag_remap = mv88e6390_port_tag_remap, 4568 .port_set_policy = mv88e6352_port_set_policy, 4569 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4570 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4571 .port_set_ether_type = mv88e6351_port_set_ether_type, 4572 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4573 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4574 .port_pause_limit = mv88e6390_port_pause_limit, 4575 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4576 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4577 .port_get_cmode = mv88e6352_port_get_cmode, 4578 .port_set_cmode = mv88e6390_port_set_cmode, 4579 .port_setup_message_port = mv88e6xxx_setup_message_port, 4580 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4581 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4582 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4583 .stats_get_strings = mv88e6320_stats_get_strings, 4584 .stats_get_stats = mv88e6390_stats_get_stats, 4585 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4586 .set_egress_port = mv88e6390_g1_set_egress_port, 4587 .watchdog_ops = &mv88e6390_watchdog_ops, 4588 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4589 .pot_clear = mv88e6xxx_g2_pot_clear, 4590 .reset = mv88e6352_g1_reset, 4591 .rmu_disable = mv88e6390_g1_rmu_disable, 4592 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4593 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4594 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4595 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4596 .serdes_power = mv88e6390_serdes_power, 4597 .serdes_get_lane = mv88e6390_serdes_get_lane, 4598 /* Check status register pause & lpa register */ 4599 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4600 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4601 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4602 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4603 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4604 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4605 .serdes_irq_status = mv88e6390_serdes_irq_status, 4606 .gpio_ops = &mv88e6352_gpio_ops, 4607 .avb_ops = &mv88e6390_avb_ops, 4608 .ptp_ops = &mv88e6352_ptp_ops, 4609 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4610 .serdes_get_strings = mv88e6390_serdes_get_strings, 4611 .serdes_get_stats = mv88e6390_serdes_get_stats, 4612 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4613 .serdes_get_regs = mv88e6390_serdes_get_regs, 4614 .phylink_validate = mv88e6390_phylink_validate, 4615 }; 4616 4617 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4618 /* MV88E6XXX_FAMILY_6390 */ 4619 .setup_errata = mv88e6390_setup_errata, 4620 .irl_init_all = mv88e6390_g2_irl_init_all, 4621 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4622 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4623 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4624 .phy_read = mv88e6xxx_g2_smi_phy_read, 4625 .phy_write = mv88e6xxx_g2_smi_phy_write, 4626 .port_set_link = mv88e6xxx_port_set_link, 4627 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4628 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4629 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4630 .port_tag_remap = mv88e6390_port_tag_remap, 4631 .port_set_policy = mv88e6352_port_set_policy, 4632 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4633 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4634 .port_set_ether_type = mv88e6351_port_set_ether_type, 4635 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4636 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4637 .port_pause_limit = mv88e6390_port_pause_limit, 4638 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4639 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4640 .port_get_cmode = mv88e6352_port_get_cmode, 4641 .port_set_cmode = mv88e6390x_port_set_cmode, 4642 .port_setup_message_port = mv88e6xxx_setup_message_port, 4643 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4644 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4645 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4646 .stats_get_strings = mv88e6320_stats_get_strings, 4647 .stats_get_stats = mv88e6390_stats_get_stats, 4648 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4649 .set_egress_port = mv88e6390_g1_set_egress_port, 4650 .watchdog_ops = &mv88e6390_watchdog_ops, 4651 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4652 .pot_clear = mv88e6xxx_g2_pot_clear, 4653 .reset = mv88e6352_g1_reset, 4654 .rmu_disable = mv88e6390_g1_rmu_disable, 4655 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4656 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4657 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4658 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4659 .serdes_power = mv88e6390_serdes_power, 4660 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4661 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4662 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4663 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4664 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4665 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4666 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4667 .serdes_irq_status = mv88e6390_serdes_irq_status, 4668 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4669 .serdes_get_strings = mv88e6390_serdes_get_strings, 4670 .serdes_get_stats = mv88e6390_serdes_get_stats, 4671 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4672 .serdes_get_regs = mv88e6390_serdes_get_regs, 4673 .gpio_ops = &mv88e6352_gpio_ops, 4674 .avb_ops = &mv88e6390_avb_ops, 4675 .ptp_ops = &mv88e6352_ptp_ops, 4676 .phylink_validate = mv88e6390x_phylink_validate, 4677 }; 4678 4679 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4680 [MV88E6085] = { 4681 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4682 .family = MV88E6XXX_FAMILY_6097, 4683 .name = "Marvell 88E6085", 4684 .num_databases = 4096, 4685 .num_macs = 8192, 4686 .num_ports = 10, 4687 .num_internal_phys = 5, 4688 .max_vid = 4095, 4689 .port_base_addr = 0x10, 4690 .phy_base_addr = 0x0, 4691 .global1_addr = 0x1b, 4692 .global2_addr = 0x1c, 4693 .age_time_coeff = 15000, 4694 .g1_irqs = 8, 4695 .g2_irqs = 10, 4696 .atu_move_port_mask = 0xf, 4697 .pvt = true, 4698 .multi_chip = true, 4699 .tag_protocol = DSA_TAG_PROTO_DSA, 4700 .ops = &mv88e6085_ops, 4701 }, 4702 4703 [MV88E6095] = { 4704 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4705 .family = MV88E6XXX_FAMILY_6095, 4706 .name = "Marvell 88E6095/88E6095F", 4707 .num_databases = 256, 4708 .num_macs = 8192, 4709 .num_ports = 11, 4710 .num_internal_phys = 0, 4711 .max_vid = 4095, 4712 .port_base_addr = 0x10, 4713 .phy_base_addr = 0x0, 4714 .global1_addr = 0x1b, 4715 .global2_addr = 0x1c, 4716 .age_time_coeff = 15000, 4717 .g1_irqs = 8, 4718 .atu_move_port_mask = 0xf, 4719 .multi_chip = true, 4720 .tag_protocol = DSA_TAG_PROTO_DSA, 4721 .ops = &mv88e6095_ops, 4722 }, 4723 4724 [MV88E6097] = { 4725 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4726 .family = MV88E6XXX_FAMILY_6097, 4727 .name = "Marvell 88E6097/88E6097F", 4728 .num_databases = 4096, 4729 .num_macs = 8192, 4730 .num_ports = 11, 4731 .num_internal_phys = 8, 4732 .max_vid = 4095, 4733 .port_base_addr = 0x10, 4734 .phy_base_addr = 0x0, 4735 .global1_addr = 0x1b, 4736 .global2_addr = 0x1c, 4737 .age_time_coeff = 15000, 4738 .g1_irqs = 8, 4739 .g2_irqs = 10, 4740 .atu_move_port_mask = 0xf, 4741 .pvt = true, 4742 .multi_chip = true, 4743 .tag_protocol = DSA_TAG_PROTO_EDSA, 4744 .ops = &mv88e6097_ops, 4745 }, 4746 4747 [MV88E6123] = { 4748 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4749 .family = MV88E6XXX_FAMILY_6165, 4750 .name = "Marvell 88E6123", 4751 .num_databases = 4096, 4752 .num_macs = 1024, 4753 .num_ports = 3, 4754 .num_internal_phys = 5, 4755 .max_vid = 4095, 4756 .port_base_addr = 0x10, 4757 .phy_base_addr = 0x0, 4758 .global1_addr = 0x1b, 4759 .global2_addr = 0x1c, 4760 .age_time_coeff = 15000, 4761 .g1_irqs = 9, 4762 .g2_irqs = 10, 4763 .atu_move_port_mask = 0xf, 4764 .pvt = true, 4765 .multi_chip = true, 4766 .tag_protocol = DSA_TAG_PROTO_EDSA, 4767 .ops = &mv88e6123_ops, 4768 }, 4769 4770 [MV88E6131] = { 4771 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4772 .family = MV88E6XXX_FAMILY_6185, 4773 .name = "Marvell 88E6131", 4774 .num_databases = 256, 4775 .num_macs = 8192, 4776 .num_ports = 8, 4777 .num_internal_phys = 0, 4778 .max_vid = 4095, 4779 .port_base_addr = 0x10, 4780 .phy_base_addr = 0x0, 4781 .global1_addr = 0x1b, 4782 .global2_addr = 0x1c, 4783 .age_time_coeff = 15000, 4784 .g1_irqs = 9, 4785 .atu_move_port_mask = 0xf, 4786 .multi_chip = true, 4787 .tag_protocol = DSA_TAG_PROTO_DSA, 4788 .ops = &mv88e6131_ops, 4789 }, 4790 4791 [MV88E6141] = { 4792 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4793 .family = MV88E6XXX_FAMILY_6341, 4794 .name = "Marvell 88E6141", 4795 .num_databases = 4096, 4796 .num_macs = 2048, 4797 .num_ports = 6, 4798 .num_internal_phys = 5, 4799 .num_gpio = 11, 4800 .max_vid = 4095, 4801 .port_base_addr = 0x10, 4802 .phy_base_addr = 0x10, 4803 .global1_addr = 0x1b, 4804 .global2_addr = 0x1c, 4805 .age_time_coeff = 3750, 4806 .atu_move_port_mask = 0x1f, 4807 .g1_irqs = 9, 4808 .g2_irqs = 10, 4809 .pvt = true, 4810 .multi_chip = true, 4811 .tag_protocol = DSA_TAG_PROTO_EDSA, 4812 .ops = &mv88e6141_ops, 4813 }, 4814 4815 [MV88E6161] = { 4816 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4817 .family = MV88E6XXX_FAMILY_6165, 4818 .name = "Marvell 88E6161", 4819 .num_databases = 4096, 4820 .num_macs = 1024, 4821 .num_ports = 6, 4822 .num_internal_phys = 5, 4823 .max_vid = 4095, 4824 .port_base_addr = 0x10, 4825 .phy_base_addr = 0x0, 4826 .global1_addr = 0x1b, 4827 .global2_addr = 0x1c, 4828 .age_time_coeff = 15000, 4829 .g1_irqs = 9, 4830 .g2_irqs = 10, 4831 .atu_move_port_mask = 0xf, 4832 .pvt = true, 4833 .multi_chip = true, 4834 .tag_protocol = DSA_TAG_PROTO_EDSA, 4835 .ptp_support = true, 4836 .ops = &mv88e6161_ops, 4837 }, 4838 4839 [MV88E6165] = { 4840 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4841 .family = MV88E6XXX_FAMILY_6165, 4842 .name = "Marvell 88E6165", 4843 .num_databases = 4096, 4844 .num_macs = 8192, 4845 .num_ports = 6, 4846 .num_internal_phys = 0, 4847 .max_vid = 4095, 4848 .port_base_addr = 0x10, 4849 .phy_base_addr = 0x0, 4850 .global1_addr = 0x1b, 4851 .global2_addr = 0x1c, 4852 .age_time_coeff = 15000, 4853 .g1_irqs = 9, 4854 .g2_irqs = 10, 4855 .atu_move_port_mask = 0xf, 4856 .pvt = true, 4857 .multi_chip = true, 4858 .tag_protocol = DSA_TAG_PROTO_DSA, 4859 .ptp_support = true, 4860 .ops = &mv88e6165_ops, 4861 }, 4862 4863 [MV88E6171] = { 4864 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4865 .family = MV88E6XXX_FAMILY_6351, 4866 .name = "Marvell 88E6171", 4867 .num_databases = 4096, 4868 .num_macs = 8192, 4869 .num_ports = 7, 4870 .num_internal_phys = 5, 4871 .max_vid = 4095, 4872 .port_base_addr = 0x10, 4873 .phy_base_addr = 0x0, 4874 .global1_addr = 0x1b, 4875 .global2_addr = 0x1c, 4876 .age_time_coeff = 15000, 4877 .g1_irqs = 9, 4878 .g2_irqs = 10, 4879 .atu_move_port_mask = 0xf, 4880 .pvt = true, 4881 .multi_chip = true, 4882 .tag_protocol = DSA_TAG_PROTO_EDSA, 4883 .ops = &mv88e6171_ops, 4884 }, 4885 4886 [MV88E6172] = { 4887 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4888 .family = MV88E6XXX_FAMILY_6352, 4889 .name = "Marvell 88E6172", 4890 .num_databases = 4096, 4891 .num_macs = 8192, 4892 .num_ports = 7, 4893 .num_internal_phys = 5, 4894 .num_gpio = 15, 4895 .max_vid = 4095, 4896 .port_base_addr = 0x10, 4897 .phy_base_addr = 0x0, 4898 .global1_addr = 0x1b, 4899 .global2_addr = 0x1c, 4900 .age_time_coeff = 15000, 4901 .g1_irqs = 9, 4902 .g2_irqs = 10, 4903 .atu_move_port_mask = 0xf, 4904 .pvt = true, 4905 .multi_chip = true, 4906 .tag_protocol = DSA_TAG_PROTO_EDSA, 4907 .ops = &mv88e6172_ops, 4908 }, 4909 4910 [MV88E6175] = { 4911 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4912 .family = MV88E6XXX_FAMILY_6351, 4913 .name = "Marvell 88E6175", 4914 .num_databases = 4096, 4915 .num_macs = 8192, 4916 .num_ports = 7, 4917 .num_internal_phys = 5, 4918 .max_vid = 4095, 4919 .port_base_addr = 0x10, 4920 .phy_base_addr = 0x0, 4921 .global1_addr = 0x1b, 4922 .global2_addr = 0x1c, 4923 .age_time_coeff = 15000, 4924 .g1_irqs = 9, 4925 .g2_irqs = 10, 4926 .atu_move_port_mask = 0xf, 4927 .pvt = true, 4928 .multi_chip = true, 4929 .tag_protocol = DSA_TAG_PROTO_EDSA, 4930 .ops = &mv88e6175_ops, 4931 }, 4932 4933 [MV88E6176] = { 4934 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4935 .family = MV88E6XXX_FAMILY_6352, 4936 .name = "Marvell 88E6176", 4937 .num_databases = 4096, 4938 .num_macs = 8192, 4939 .num_ports = 7, 4940 .num_internal_phys = 5, 4941 .num_gpio = 15, 4942 .max_vid = 4095, 4943 .port_base_addr = 0x10, 4944 .phy_base_addr = 0x0, 4945 .global1_addr = 0x1b, 4946 .global2_addr = 0x1c, 4947 .age_time_coeff = 15000, 4948 .g1_irqs = 9, 4949 .g2_irqs = 10, 4950 .atu_move_port_mask = 0xf, 4951 .pvt = true, 4952 .multi_chip = true, 4953 .tag_protocol = DSA_TAG_PROTO_EDSA, 4954 .ops = &mv88e6176_ops, 4955 }, 4956 4957 [MV88E6185] = { 4958 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4959 .family = MV88E6XXX_FAMILY_6185, 4960 .name = "Marvell 88E6185", 4961 .num_databases = 256, 4962 .num_macs = 8192, 4963 .num_ports = 10, 4964 .num_internal_phys = 0, 4965 .max_vid = 4095, 4966 .port_base_addr = 0x10, 4967 .phy_base_addr = 0x0, 4968 .global1_addr = 0x1b, 4969 .global2_addr = 0x1c, 4970 .age_time_coeff = 15000, 4971 .g1_irqs = 8, 4972 .atu_move_port_mask = 0xf, 4973 .multi_chip = true, 4974 .tag_protocol = DSA_TAG_PROTO_EDSA, 4975 .ops = &mv88e6185_ops, 4976 }, 4977 4978 [MV88E6190] = { 4979 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4980 .family = MV88E6XXX_FAMILY_6390, 4981 .name = "Marvell 88E6190", 4982 .num_databases = 4096, 4983 .num_macs = 16384, 4984 .num_ports = 11, /* 10 + Z80 */ 4985 .num_internal_phys = 9, 4986 .num_gpio = 16, 4987 .max_vid = 8191, 4988 .port_base_addr = 0x0, 4989 .phy_base_addr = 0x0, 4990 .global1_addr = 0x1b, 4991 .global2_addr = 0x1c, 4992 .tag_protocol = DSA_TAG_PROTO_DSA, 4993 .age_time_coeff = 3750, 4994 .g1_irqs = 9, 4995 .g2_irqs = 14, 4996 .pvt = true, 4997 .multi_chip = true, 4998 .atu_move_port_mask = 0x1f, 4999 .ops = &mv88e6190_ops, 5000 }, 5001 5002 [MV88E6190X] = { 5003 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5004 .family = MV88E6XXX_FAMILY_6390, 5005 .name = "Marvell 88E6190X", 5006 .num_databases = 4096, 5007 .num_macs = 16384, 5008 .num_ports = 11, /* 10 + Z80 */ 5009 .num_internal_phys = 9, 5010 .num_gpio = 16, 5011 .max_vid = 8191, 5012 .port_base_addr = 0x0, 5013 .phy_base_addr = 0x0, 5014 .global1_addr = 0x1b, 5015 .global2_addr = 0x1c, 5016 .age_time_coeff = 3750, 5017 .g1_irqs = 9, 5018 .g2_irqs = 14, 5019 .atu_move_port_mask = 0x1f, 5020 .pvt = true, 5021 .multi_chip = true, 5022 .tag_protocol = DSA_TAG_PROTO_DSA, 5023 .ops = &mv88e6190x_ops, 5024 }, 5025 5026 [MV88E6191] = { 5027 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5028 .family = MV88E6XXX_FAMILY_6390, 5029 .name = "Marvell 88E6191", 5030 .num_databases = 4096, 5031 .num_macs = 16384, 5032 .num_ports = 11, /* 10 + Z80 */ 5033 .num_internal_phys = 9, 5034 .max_vid = 8191, 5035 .port_base_addr = 0x0, 5036 .phy_base_addr = 0x0, 5037 .global1_addr = 0x1b, 5038 .global2_addr = 0x1c, 5039 .age_time_coeff = 3750, 5040 .g1_irqs = 9, 5041 .g2_irqs = 14, 5042 .atu_move_port_mask = 0x1f, 5043 .pvt = true, 5044 .multi_chip = true, 5045 .tag_protocol = DSA_TAG_PROTO_DSA, 5046 .ptp_support = true, 5047 .ops = &mv88e6191_ops, 5048 }, 5049 5050 [MV88E6220] = { 5051 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5052 .family = MV88E6XXX_FAMILY_6250, 5053 .name = "Marvell 88E6220", 5054 .num_databases = 64, 5055 5056 /* Ports 2-4 are not routed to pins 5057 * => usable ports 0, 1, 5, 6 5058 */ 5059 .num_ports = 7, 5060 .num_internal_phys = 2, 5061 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5062 .max_vid = 4095, 5063 .port_base_addr = 0x08, 5064 .phy_base_addr = 0x00, 5065 .global1_addr = 0x0f, 5066 .global2_addr = 0x07, 5067 .age_time_coeff = 15000, 5068 .g1_irqs = 9, 5069 .g2_irqs = 10, 5070 .atu_move_port_mask = 0xf, 5071 .dual_chip = true, 5072 .tag_protocol = DSA_TAG_PROTO_DSA, 5073 .ptp_support = true, 5074 .ops = &mv88e6250_ops, 5075 }, 5076 5077 [MV88E6240] = { 5078 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5079 .family = MV88E6XXX_FAMILY_6352, 5080 .name = "Marvell 88E6240", 5081 .num_databases = 4096, 5082 .num_macs = 8192, 5083 .num_ports = 7, 5084 .num_internal_phys = 5, 5085 .num_gpio = 15, 5086 .max_vid = 4095, 5087 .port_base_addr = 0x10, 5088 .phy_base_addr = 0x0, 5089 .global1_addr = 0x1b, 5090 .global2_addr = 0x1c, 5091 .age_time_coeff = 15000, 5092 .g1_irqs = 9, 5093 .g2_irqs = 10, 5094 .atu_move_port_mask = 0xf, 5095 .pvt = true, 5096 .multi_chip = true, 5097 .tag_protocol = DSA_TAG_PROTO_EDSA, 5098 .ptp_support = true, 5099 .ops = &mv88e6240_ops, 5100 }, 5101 5102 [MV88E6250] = { 5103 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5104 .family = MV88E6XXX_FAMILY_6250, 5105 .name = "Marvell 88E6250", 5106 .num_databases = 64, 5107 .num_ports = 7, 5108 .num_internal_phys = 5, 5109 .max_vid = 4095, 5110 .port_base_addr = 0x08, 5111 .phy_base_addr = 0x00, 5112 .global1_addr = 0x0f, 5113 .global2_addr = 0x07, 5114 .age_time_coeff = 15000, 5115 .g1_irqs = 9, 5116 .g2_irqs = 10, 5117 .atu_move_port_mask = 0xf, 5118 .dual_chip = true, 5119 .tag_protocol = DSA_TAG_PROTO_DSA, 5120 .ptp_support = true, 5121 .ops = &mv88e6250_ops, 5122 }, 5123 5124 [MV88E6290] = { 5125 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5126 .family = MV88E6XXX_FAMILY_6390, 5127 .name = "Marvell 88E6290", 5128 .num_databases = 4096, 5129 .num_ports = 11, /* 10 + Z80 */ 5130 .num_internal_phys = 9, 5131 .num_gpio = 16, 5132 .max_vid = 8191, 5133 .port_base_addr = 0x0, 5134 .phy_base_addr = 0x0, 5135 .global1_addr = 0x1b, 5136 .global2_addr = 0x1c, 5137 .age_time_coeff = 3750, 5138 .g1_irqs = 9, 5139 .g2_irqs = 14, 5140 .atu_move_port_mask = 0x1f, 5141 .pvt = true, 5142 .multi_chip = true, 5143 .tag_protocol = DSA_TAG_PROTO_DSA, 5144 .ptp_support = true, 5145 .ops = &mv88e6290_ops, 5146 }, 5147 5148 [MV88E6320] = { 5149 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5150 .family = MV88E6XXX_FAMILY_6320, 5151 .name = "Marvell 88E6320", 5152 .num_databases = 4096, 5153 .num_macs = 8192, 5154 .num_ports = 7, 5155 .num_internal_phys = 5, 5156 .num_gpio = 15, 5157 .max_vid = 4095, 5158 .port_base_addr = 0x10, 5159 .phy_base_addr = 0x0, 5160 .global1_addr = 0x1b, 5161 .global2_addr = 0x1c, 5162 .age_time_coeff = 15000, 5163 .g1_irqs = 8, 5164 .g2_irqs = 10, 5165 .atu_move_port_mask = 0xf, 5166 .pvt = true, 5167 .multi_chip = true, 5168 .tag_protocol = DSA_TAG_PROTO_EDSA, 5169 .ptp_support = true, 5170 .ops = &mv88e6320_ops, 5171 }, 5172 5173 [MV88E6321] = { 5174 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5175 .family = MV88E6XXX_FAMILY_6320, 5176 .name = "Marvell 88E6321", 5177 .num_databases = 4096, 5178 .num_macs = 8192, 5179 .num_ports = 7, 5180 .num_internal_phys = 5, 5181 .num_gpio = 15, 5182 .max_vid = 4095, 5183 .port_base_addr = 0x10, 5184 .phy_base_addr = 0x0, 5185 .global1_addr = 0x1b, 5186 .global2_addr = 0x1c, 5187 .age_time_coeff = 15000, 5188 .g1_irqs = 8, 5189 .g2_irqs = 10, 5190 .atu_move_port_mask = 0xf, 5191 .multi_chip = true, 5192 .tag_protocol = DSA_TAG_PROTO_EDSA, 5193 .ptp_support = true, 5194 .ops = &mv88e6321_ops, 5195 }, 5196 5197 [MV88E6341] = { 5198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5199 .family = MV88E6XXX_FAMILY_6341, 5200 .name = "Marvell 88E6341", 5201 .num_databases = 4096, 5202 .num_macs = 2048, 5203 .num_internal_phys = 5, 5204 .num_ports = 6, 5205 .num_gpio = 11, 5206 .max_vid = 4095, 5207 .port_base_addr = 0x10, 5208 .phy_base_addr = 0x10, 5209 .global1_addr = 0x1b, 5210 .global2_addr = 0x1c, 5211 .age_time_coeff = 3750, 5212 .atu_move_port_mask = 0x1f, 5213 .g1_irqs = 9, 5214 .g2_irqs = 10, 5215 .pvt = true, 5216 .multi_chip = true, 5217 .tag_protocol = DSA_TAG_PROTO_EDSA, 5218 .ptp_support = true, 5219 .ops = &mv88e6341_ops, 5220 }, 5221 5222 [MV88E6350] = { 5223 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5224 .family = MV88E6XXX_FAMILY_6351, 5225 .name = "Marvell 88E6350", 5226 .num_databases = 4096, 5227 .num_macs = 8192, 5228 .num_ports = 7, 5229 .num_internal_phys = 5, 5230 .max_vid = 4095, 5231 .port_base_addr = 0x10, 5232 .phy_base_addr = 0x0, 5233 .global1_addr = 0x1b, 5234 .global2_addr = 0x1c, 5235 .age_time_coeff = 15000, 5236 .g1_irqs = 9, 5237 .g2_irqs = 10, 5238 .atu_move_port_mask = 0xf, 5239 .pvt = true, 5240 .multi_chip = true, 5241 .tag_protocol = DSA_TAG_PROTO_EDSA, 5242 .ops = &mv88e6350_ops, 5243 }, 5244 5245 [MV88E6351] = { 5246 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5247 .family = MV88E6XXX_FAMILY_6351, 5248 .name = "Marvell 88E6351", 5249 .num_databases = 4096, 5250 .num_macs = 8192, 5251 .num_ports = 7, 5252 .num_internal_phys = 5, 5253 .max_vid = 4095, 5254 .port_base_addr = 0x10, 5255 .phy_base_addr = 0x0, 5256 .global1_addr = 0x1b, 5257 .global2_addr = 0x1c, 5258 .age_time_coeff = 15000, 5259 .g1_irqs = 9, 5260 .g2_irqs = 10, 5261 .atu_move_port_mask = 0xf, 5262 .pvt = true, 5263 .multi_chip = true, 5264 .tag_protocol = DSA_TAG_PROTO_EDSA, 5265 .ops = &mv88e6351_ops, 5266 }, 5267 5268 [MV88E6352] = { 5269 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5270 .family = MV88E6XXX_FAMILY_6352, 5271 .name = "Marvell 88E6352", 5272 .num_databases = 4096, 5273 .num_macs = 8192, 5274 .num_ports = 7, 5275 .num_internal_phys = 5, 5276 .num_gpio = 15, 5277 .max_vid = 4095, 5278 .port_base_addr = 0x10, 5279 .phy_base_addr = 0x0, 5280 .global1_addr = 0x1b, 5281 .global2_addr = 0x1c, 5282 .age_time_coeff = 15000, 5283 .g1_irqs = 9, 5284 .g2_irqs = 10, 5285 .atu_move_port_mask = 0xf, 5286 .pvt = true, 5287 .multi_chip = true, 5288 .tag_protocol = DSA_TAG_PROTO_EDSA, 5289 .ptp_support = true, 5290 .ops = &mv88e6352_ops, 5291 }, 5292 [MV88E6390] = { 5293 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5294 .family = MV88E6XXX_FAMILY_6390, 5295 .name = "Marvell 88E6390", 5296 .num_databases = 4096, 5297 .num_macs = 16384, 5298 .num_ports = 11, /* 10 + Z80 */ 5299 .num_internal_phys = 9, 5300 .num_gpio = 16, 5301 .max_vid = 8191, 5302 .port_base_addr = 0x0, 5303 .phy_base_addr = 0x0, 5304 .global1_addr = 0x1b, 5305 .global2_addr = 0x1c, 5306 .age_time_coeff = 3750, 5307 .g1_irqs = 9, 5308 .g2_irqs = 14, 5309 .atu_move_port_mask = 0x1f, 5310 .pvt = true, 5311 .multi_chip = true, 5312 .tag_protocol = DSA_TAG_PROTO_DSA, 5313 .ptp_support = true, 5314 .ops = &mv88e6390_ops, 5315 }, 5316 [MV88E6390X] = { 5317 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5318 .family = MV88E6XXX_FAMILY_6390, 5319 .name = "Marvell 88E6390X", 5320 .num_databases = 4096, 5321 .num_macs = 16384, 5322 .num_ports = 11, /* 10 + Z80 */ 5323 .num_internal_phys = 9, 5324 .num_gpio = 16, 5325 .max_vid = 8191, 5326 .port_base_addr = 0x0, 5327 .phy_base_addr = 0x0, 5328 .global1_addr = 0x1b, 5329 .global2_addr = 0x1c, 5330 .age_time_coeff = 3750, 5331 .g1_irqs = 9, 5332 .g2_irqs = 14, 5333 .atu_move_port_mask = 0x1f, 5334 .pvt = true, 5335 .multi_chip = true, 5336 .tag_protocol = DSA_TAG_PROTO_DSA, 5337 .ptp_support = true, 5338 .ops = &mv88e6390x_ops, 5339 }, 5340 }; 5341 5342 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5343 { 5344 int i; 5345 5346 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5347 if (mv88e6xxx_table[i].prod_num == prod_num) 5348 return &mv88e6xxx_table[i]; 5349 5350 return NULL; 5351 } 5352 5353 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5354 { 5355 const struct mv88e6xxx_info *info; 5356 unsigned int prod_num, rev; 5357 u16 id; 5358 int err; 5359 5360 mv88e6xxx_reg_lock(chip); 5361 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5362 mv88e6xxx_reg_unlock(chip); 5363 if (err) 5364 return err; 5365 5366 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5367 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5368 5369 info = mv88e6xxx_lookup_info(prod_num); 5370 if (!info) 5371 return -ENODEV; 5372 5373 /* Update the compatible info with the probed one */ 5374 chip->info = info; 5375 5376 err = mv88e6xxx_g2_require(chip); 5377 if (err) 5378 return err; 5379 5380 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5381 chip->info->prod_num, chip->info->name, rev); 5382 5383 return 0; 5384 } 5385 5386 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5387 { 5388 struct mv88e6xxx_chip *chip; 5389 5390 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5391 if (!chip) 5392 return NULL; 5393 5394 chip->dev = dev; 5395 5396 mutex_init(&chip->reg_lock); 5397 INIT_LIST_HEAD(&chip->mdios); 5398 idr_init(&chip->policies); 5399 5400 return chip; 5401 } 5402 5403 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5404 int port, 5405 enum dsa_tag_protocol m) 5406 { 5407 struct mv88e6xxx_chip *chip = ds->priv; 5408 5409 return chip->info->tag_protocol; 5410 } 5411 5412 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5413 const struct switchdev_obj_port_mdb *mdb) 5414 { 5415 /* We don't need any dynamic resource from the kernel (yet), 5416 * so skip the prepare phase. 5417 */ 5418 5419 return 0; 5420 } 5421 5422 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5423 const struct switchdev_obj_port_mdb *mdb) 5424 { 5425 struct mv88e6xxx_chip *chip = ds->priv; 5426 5427 mv88e6xxx_reg_lock(chip); 5428 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5429 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5430 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5431 port); 5432 mv88e6xxx_reg_unlock(chip); 5433 } 5434 5435 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5436 const struct switchdev_obj_port_mdb *mdb) 5437 { 5438 struct mv88e6xxx_chip *chip = ds->priv; 5439 int err; 5440 5441 mv88e6xxx_reg_lock(chip); 5442 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5443 mv88e6xxx_reg_unlock(chip); 5444 5445 return err; 5446 } 5447 5448 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5449 struct dsa_mall_mirror_tc_entry *mirror, 5450 bool ingress) 5451 { 5452 enum mv88e6xxx_egress_direction direction = ingress ? 5453 MV88E6XXX_EGRESS_DIR_INGRESS : 5454 MV88E6XXX_EGRESS_DIR_EGRESS; 5455 struct mv88e6xxx_chip *chip = ds->priv; 5456 bool other_mirrors = false; 5457 int i; 5458 int err; 5459 5460 if (!chip->info->ops->set_egress_port) 5461 return -EOPNOTSUPP; 5462 5463 mutex_lock(&chip->reg_lock); 5464 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5465 mirror->to_local_port) { 5466 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5467 other_mirrors |= ingress ? 5468 chip->ports[i].mirror_ingress : 5469 chip->ports[i].mirror_egress; 5470 5471 /* Can't change egress port when other mirror is active */ 5472 if (other_mirrors) { 5473 err = -EBUSY; 5474 goto out; 5475 } 5476 5477 err = chip->info->ops->set_egress_port(chip, 5478 direction, 5479 mirror->to_local_port); 5480 if (err) 5481 goto out; 5482 } 5483 5484 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5485 out: 5486 mutex_unlock(&chip->reg_lock); 5487 5488 return err; 5489 } 5490 5491 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5492 struct dsa_mall_mirror_tc_entry *mirror) 5493 { 5494 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5495 MV88E6XXX_EGRESS_DIR_INGRESS : 5496 MV88E6XXX_EGRESS_DIR_EGRESS; 5497 struct mv88e6xxx_chip *chip = ds->priv; 5498 bool other_mirrors = false; 5499 int i; 5500 5501 mutex_lock(&chip->reg_lock); 5502 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5503 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5504 5505 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5506 other_mirrors |= mirror->ingress ? 5507 chip->ports[i].mirror_ingress : 5508 chip->ports[i].mirror_egress; 5509 5510 /* Reset egress port when no other mirror is active */ 5511 if (!other_mirrors) { 5512 if (chip->info->ops->set_egress_port(chip, 5513 direction, 5514 dsa_upstream_port(ds, 5515 port))) 5516 dev_err(ds->dev, "failed to set egress port\n"); 5517 } 5518 5519 mutex_unlock(&chip->reg_lock); 5520 } 5521 5522 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5523 bool unicast, bool multicast) 5524 { 5525 struct mv88e6xxx_chip *chip = ds->priv; 5526 int err = -EOPNOTSUPP; 5527 5528 mv88e6xxx_reg_lock(chip); 5529 if (chip->info->ops->port_set_egress_floods) 5530 err = chip->info->ops->port_set_egress_floods(chip, port, 5531 unicast, 5532 multicast); 5533 mv88e6xxx_reg_unlock(chip); 5534 5535 return err; 5536 } 5537 5538 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5539 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5540 .setup = mv88e6xxx_setup, 5541 .teardown = mv88e6xxx_teardown, 5542 .phylink_validate = mv88e6xxx_validate, 5543 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5544 .phylink_mac_config = mv88e6xxx_mac_config, 5545 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5546 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5547 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5548 .get_strings = mv88e6xxx_get_strings, 5549 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5550 .get_sset_count = mv88e6xxx_get_sset_count, 5551 .port_enable = mv88e6xxx_port_enable, 5552 .port_disable = mv88e6xxx_port_disable, 5553 .port_max_mtu = mv88e6xxx_get_max_mtu, 5554 .port_change_mtu = mv88e6xxx_change_mtu, 5555 .get_mac_eee = mv88e6xxx_get_mac_eee, 5556 .set_mac_eee = mv88e6xxx_set_mac_eee, 5557 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5558 .get_eeprom = mv88e6xxx_get_eeprom, 5559 .set_eeprom = mv88e6xxx_set_eeprom, 5560 .get_regs_len = mv88e6xxx_get_regs_len, 5561 .get_regs = mv88e6xxx_get_regs, 5562 .get_rxnfc = mv88e6xxx_get_rxnfc, 5563 .set_rxnfc = mv88e6xxx_set_rxnfc, 5564 .set_ageing_time = mv88e6xxx_set_ageing_time, 5565 .port_bridge_join = mv88e6xxx_port_bridge_join, 5566 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5567 .port_egress_floods = mv88e6xxx_port_egress_floods, 5568 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5569 .port_fast_age = mv88e6xxx_port_fast_age, 5570 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5571 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5572 .port_vlan_add = mv88e6xxx_port_vlan_add, 5573 .port_vlan_del = mv88e6xxx_port_vlan_del, 5574 .port_fdb_add = mv88e6xxx_port_fdb_add, 5575 .port_fdb_del = mv88e6xxx_port_fdb_del, 5576 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5577 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5578 .port_mdb_add = mv88e6xxx_port_mdb_add, 5579 .port_mdb_del = mv88e6xxx_port_mdb_del, 5580 .port_mirror_add = mv88e6xxx_port_mirror_add, 5581 .port_mirror_del = mv88e6xxx_port_mirror_del, 5582 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5583 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5584 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5585 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5586 .port_txtstamp = mv88e6xxx_port_txtstamp, 5587 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5588 .get_ts_info = mv88e6xxx_get_ts_info, 5589 .devlink_param_get = mv88e6xxx_devlink_param_get, 5590 .devlink_param_set = mv88e6xxx_devlink_param_set, 5591 }; 5592 5593 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5594 { 5595 struct device *dev = chip->dev; 5596 struct dsa_switch *ds; 5597 5598 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5599 if (!ds) 5600 return -ENOMEM; 5601 5602 ds->dev = dev; 5603 ds->num_ports = mv88e6xxx_num_ports(chip); 5604 ds->priv = chip; 5605 ds->dev = dev; 5606 ds->ops = &mv88e6xxx_switch_ops; 5607 ds->ageing_time_min = chip->info->age_time_coeff; 5608 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5609 5610 dev_set_drvdata(dev, ds); 5611 5612 return dsa_register_switch(ds); 5613 } 5614 5615 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5616 { 5617 dsa_unregister_switch(chip->ds); 5618 } 5619 5620 static const void *pdata_device_get_match_data(struct device *dev) 5621 { 5622 const struct of_device_id *matches = dev->driver->of_match_table; 5623 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5624 5625 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5626 matches++) { 5627 if (!strcmp(pdata->compatible, matches->compatible)) 5628 return matches->data; 5629 } 5630 return NULL; 5631 } 5632 5633 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5634 * would be lost after a power cycle so prevent it to be suspended. 5635 */ 5636 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5637 { 5638 return -EOPNOTSUPP; 5639 } 5640 5641 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5642 { 5643 return 0; 5644 } 5645 5646 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5647 5648 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5649 { 5650 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5651 const struct mv88e6xxx_info *compat_info = NULL; 5652 struct device *dev = &mdiodev->dev; 5653 struct device_node *np = dev->of_node; 5654 struct mv88e6xxx_chip *chip; 5655 int port; 5656 int err; 5657 5658 if (!np && !pdata) 5659 return -EINVAL; 5660 5661 if (np) 5662 compat_info = of_device_get_match_data(dev); 5663 5664 if (pdata) { 5665 compat_info = pdata_device_get_match_data(dev); 5666 5667 if (!pdata->netdev) 5668 return -EINVAL; 5669 5670 for (port = 0; port < DSA_MAX_PORTS; port++) { 5671 if (!(pdata->enabled_ports & (1 << port))) 5672 continue; 5673 if (strcmp(pdata->cd.port_names[port], "cpu")) 5674 continue; 5675 pdata->cd.netdev[port] = &pdata->netdev->dev; 5676 break; 5677 } 5678 } 5679 5680 if (!compat_info) 5681 return -EINVAL; 5682 5683 chip = mv88e6xxx_alloc_chip(dev); 5684 if (!chip) { 5685 err = -ENOMEM; 5686 goto out; 5687 } 5688 5689 chip->info = compat_info; 5690 5691 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5692 if (err) 5693 goto out; 5694 5695 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5696 if (IS_ERR(chip->reset)) { 5697 err = PTR_ERR(chip->reset); 5698 goto out; 5699 } 5700 if (chip->reset) 5701 usleep_range(1000, 2000); 5702 5703 err = mv88e6xxx_detect(chip); 5704 if (err) 5705 goto out; 5706 5707 mv88e6xxx_phy_init(chip); 5708 5709 if (chip->info->ops->get_eeprom) { 5710 if (np) 5711 of_property_read_u32(np, "eeprom-length", 5712 &chip->eeprom_len); 5713 else 5714 chip->eeprom_len = pdata->eeprom_len; 5715 } 5716 5717 mv88e6xxx_reg_lock(chip); 5718 err = mv88e6xxx_switch_reset(chip); 5719 mv88e6xxx_reg_unlock(chip); 5720 if (err) 5721 goto out; 5722 5723 if (np) { 5724 chip->irq = of_irq_get(np, 0); 5725 if (chip->irq == -EPROBE_DEFER) { 5726 err = chip->irq; 5727 goto out; 5728 } 5729 } 5730 5731 if (pdata) 5732 chip->irq = pdata->irq; 5733 5734 /* Has to be performed before the MDIO bus is created, because 5735 * the PHYs will link their interrupts to these interrupt 5736 * controllers 5737 */ 5738 mv88e6xxx_reg_lock(chip); 5739 if (chip->irq > 0) 5740 err = mv88e6xxx_g1_irq_setup(chip); 5741 else 5742 err = mv88e6xxx_irq_poll_setup(chip); 5743 mv88e6xxx_reg_unlock(chip); 5744 5745 if (err) 5746 goto out; 5747 5748 if (chip->info->g2_irqs > 0) { 5749 err = mv88e6xxx_g2_irq_setup(chip); 5750 if (err) 5751 goto out_g1_irq; 5752 } 5753 5754 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5755 if (err) 5756 goto out_g2_irq; 5757 5758 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5759 if (err) 5760 goto out_g1_atu_prob_irq; 5761 5762 err = mv88e6xxx_mdios_register(chip, np); 5763 if (err) 5764 goto out_g1_vtu_prob_irq; 5765 5766 err = mv88e6xxx_register_switch(chip); 5767 if (err) 5768 goto out_mdio; 5769 5770 return 0; 5771 5772 out_mdio: 5773 mv88e6xxx_mdios_unregister(chip); 5774 out_g1_vtu_prob_irq: 5775 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5776 out_g1_atu_prob_irq: 5777 mv88e6xxx_g1_atu_prob_irq_free(chip); 5778 out_g2_irq: 5779 if (chip->info->g2_irqs > 0) 5780 mv88e6xxx_g2_irq_free(chip); 5781 out_g1_irq: 5782 if (chip->irq > 0) 5783 mv88e6xxx_g1_irq_free(chip); 5784 else 5785 mv88e6xxx_irq_poll_free(chip); 5786 out: 5787 if (pdata) 5788 dev_put(pdata->netdev); 5789 5790 return err; 5791 } 5792 5793 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5794 { 5795 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5796 struct mv88e6xxx_chip *chip = ds->priv; 5797 5798 if (chip->info->ptp_support) { 5799 mv88e6xxx_hwtstamp_free(chip); 5800 mv88e6xxx_ptp_free(chip); 5801 } 5802 5803 mv88e6xxx_phy_destroy(chip); 5804 mv88e6xxx_unregister_switch(chip); 5805 mv88e6xxx_mdios_unregister(chip); 5806 5807 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5808 mv88e6xxx_g1_atu_prob_irq_free(chip); 5809 5810 if (chip->info->g2_irqs > 0) 5811 mv88e6xxx_g2_irq_free(chip); 5812 5813 if (chip->irq > 0) 5814 mv88e6xxx_g1_irq_free(chip); 5815 else 5816 mv88e6xxx_irq_poll_free(chip); 5817 } 5818 5819 static const struct of_device_id mv88e6xxx_of_match[] = { 5820 { 5821 .compatible = "marvell,mv88e6085", 5822 .data = &mv88e6xxx_table[MV88E6085], 5823 }, 5824 { 5825 .compatible = "marvell,mv88e6190", 5826 .data = &mv88e6xxx_table[MV88E6190], 5827 }, 5828 { 5829 .compatible = "marvell,mv88e6250", 5830 .data = &mv88e6xxx_table[MV88E6250], 5831 }, 5832 { /* sentinel */ }, 5833 }; 5834 5835 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5836 5837 static struct mdio_driver mv88e6xxx_driver = { 5838 .probe = mv88e6xxx_probe, 5839 .remove = mv88e6xxx_remove, 5840 .mdiodrv.driver = { 5841 .name = "mv88e6085", 5842 .of_match_table = mv88e6xxx_of_match, 5843 .pm = &mv88e6xxx_pm_ops, 5844 }, 5845 }; 5846 5847 mdio_module_driver(mv88e6xxx_driver); 5848 5849 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5850 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5851 MODULE_LICENSE("GPL"); 5852