1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_pause) { 453 err = chip->info->ops->port_set_pause(chip, port, pause); 454 if (err) 455 goto restore_link; 456 } 457 458 err = mv88e6xxx_port_config_interface(chip, port, mode); 459 restore_link: 460 if (chip->info->ops->port_set_link(chip, port, link)) 461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 462 463 return err; 464 } 465 466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 467 { 468 struct mv88e6xxx_chip *chip = ds->priv; 469 470 return port < chip->info->num_internal_phys; 471 } 472 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 474 { 475 u16 reg; 476 int err; 477 478 /* The 88e6250 family does not have the PHY detect bit. Instead, 479 * report whether the port is internal. 480 */ 481 if (chip->info->family == MV88E6XXX_FAMILY_6250) 482 return port < chip->info->num_internal_phys; 483 484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 485 if (err) { 486 dev_err(chip->dev, 487 "p%d: %s: failed to read port status\n", 488 port, __func__); 489 return err; 490 } 491 492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 493 } 494 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 496 struct phylink_link_state *state) 497 { 498 struct mv88e6xxx_chip *chip = ds->priv; 499 int lane; 500 int err; 501 502 mv88e6xxx_reg_lock(chip); 503 lane = mv88e6xxx_serdes_get_lane(chip, port); 504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 506 state); 507 else 508 err = -EOPNOTSUPP; 509 mv88e6xxx_reg_unlock(chip); 510 511 return err; 512 } 513 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 515 unsigned int mode, 516 phy_interface_t interface, 517 const unsigned long *advertise) 518 { 519 const struct mv88e6xxx_ops *ops = chip->info->ops; 520 int lane; 521 522 if (ops->serdes_pcs_config) { 523 lane = mv88e6xxx_serdes_get_lane(chip, port); 524 if (lane >= 0) 525 return ops->serdes_pcs_config(chip, port, lane, mode, 526 interface, advertise); 527 } 528 529 return 0; 530 } 531 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 533 { 534 struct mv88e6xxx_chip *chip = ds->priv; 535 const struct mv88e6xxx_ops *ops; 536 int err = 0; 537 int lane; 538 539 ops = chip->info->ops; 540 541 if (ops->serdes_pcs_an_restart) { 542 mv88e6xxx_reg_lock(chip); 543 lane = mv88e6xxx_serdes_get_lane(chip, port); 544 if (lane >= 0) 545 err = ops->serdes_pcs_an_restart(chip, port, lane); 546 mv88e6xxx_reg_unlock(chip); 547 548 if (err) 549 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 550 } 551 } 552 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 554 unsigned int mode, 555 int speed, int duplex) 556 { 557 const struct mv88e6xxx_ops *ops = chip->info->ops; 558 int lane; 559 560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 561 lane = mv88e6xxx_serdes_get_lane(chip, port); 562 if (lane >= 0) 563 return ops->serdes_pcs_link_up(chip, port, lane, 564 speed, duplex); 565 } 566 567 return 0; 568 } 569 570 static const u8 mv88e6185_phy_interface_modes[] = { 571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 578 }; 579 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 u8 cmode = chip->ports[port].cmode; 584 585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 586 587 if (mv88e6xxx_phy_is_internal(chip->ds, port)) { 588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 589 } else { 590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 591 mv88e6185_phy_interface_modes[cmode]) 592 __set_bit(mv88e6185_phy_interface_modes[cmode], 593 config->supported_interfaces); 594 595 config->mac_capabilities |= MAC_1000FD; 596 } 597 } 598 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 600 struct phylink_config *config) 601 { 602 u8 cmode = chip->ports[port].cmode; 603 604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 605 mv88e6185_phy_interface_modes[cmode]) 606 __set_bit(mv88e6185_phy_interface_modes[cmode], 607 config->supported_interfaces); 608 609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 610 MAC_1000FD; 611 } 612 613 static const u8 mv88e6xxx_phy_interface_modes[] = { 614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_MII, 615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_RMII, 618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 622 /* higher interface modes are not needed here, since ports supporting 623 * them are writable, and so the supported interfaces are filled in the 624 * corresponding .phylink_set_interfaces() implementation below 625 */ 626 }; 627 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 629 { 630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 631 mv88e6xxx_phy_interface_modes[cmode]) 632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 634 phy_interface_set_rgmii(supported); 635 } 636 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 638 struct phylink_config *config) 639 { 640 unsigned long *supported = config->supported_interfaces; 641 642 /* Translate the default cmode */ 643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 644 645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 646 } 647 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 649 { 650 u16 reg, val; 651 int err; 652 653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 654 if (err) 655 return err; 656 657 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 659 return 0xf; 660 661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 663 if (err) 664 return err; 665 666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 667 if (err) 668 return err; 669 670 /* Restore PHY_DETECT value */ 671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 672 if (err) 673 return err; 674 675 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 676 } 677 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config) 680 { 681 unsigned long *supported = config->supported_interfaces; 682 int err, cmode; 683 684 /* Translate the default cmode */ 685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 686 687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 688 MAC_1000FD; 689 690 /* Port 4 supports automedia if the serdes is associated with it. */ 691 if (port == 4) { 692 mv88e6xxx_reg_lock(chip); 693 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 694 if (err < 0) 695 dev_err(chip->dev, "p%d: failed to read scratch\n", 696 port); 697 if (err <= 0) 698 goto unlock; 699 700 cmode = mv88e6352_get_port4_serdes_cmode(chip); 701 if (cmode < 0) 702 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 703 port); 704 else 705 mv88e6xxx_translate_cmode(cmode, supported); 706 unlock: 707 mv88e6xxx_reg_unlock(chip); 708 } 709 } 710 711 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 712 struct phylink_config *config) 713 { 714 unsigned long *supported = config->supported_interfaces; 715 716 /* Translate the default cmode */ 717 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 718 719 /* No ethtool bits for 200Mbps */ 720 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 721 MAC_1000FD; 722 723 /* The C_Mode field is programmable on port 5 */ 724 if (port == 5) { 725 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 726 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 727 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 728 729 config->mac_capabilities |= MAC_2500FD; 730 } 731 } 732 733 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 734 struct phylink_config *config) 735 { 736 unsigned long *supported = config->supported_interfaces; 737 738 /* Translate the default cmode */ 739 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 740 741 /* No ethtool bits for 200Mbps */ 742 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 743 MAC_1000FD; 744 745 /* The C_Mode field is programmable on ports 9 and 10 */ 746 if (port == 9 || port == 10) { 747 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 748 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 749 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 750 751 config->mac_capabilities |= MAC_2500FD; 752 } 753 } 754 755 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 756 struct phylink_config *config) 757 { 758 unsigned long *supported = config->supported_interfaces; 759 760 mv88e6390_phylink_get_caps(chip, port, config); 761 762 /* For the 6x90X, ports 2-7 can be in automedia mode. 763 * (Note that 6x90 doesn't support RXAUI nor XAUI). 764 * 765 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 766 * configured for 1000BASE-X, SGMII or 2500BASE-X. 767 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 768 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 769 * 770 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 771 * configured for 1000BASE-X, SGMII or 2500BASE-X. 772 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 773 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 774 * 775 * For now, be permissive (as the old code was) and allow 1000BASE-X 776 * on ports 2..7. 777 */ 778 if (port >= 2 && port <= 7) 779 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 780 781 /* The C_Mode field can also be programmed for 10G speeds */ 782 if (port == 9 || port == 10) { 783 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 784 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 785 786 config->mac_capabilities |= MAC_10000FD; 787 } 788 } 789 790 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 791 struct phylink_config *config) 792 { 793 unsigned long *supported = config->supported_interfaces; 794 bool is_6191x = 795 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 796 797 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 798 799 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 800 MAC_1000FD; 801 802 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 803 if (port == 0 || port == 9 || port == 10) { 804 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 805 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 806 807 /* 6191X supports >1G modes only on port 10 */ 808 if (!is_6191x || port == 10) { 809 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 810 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 811 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 812 /* FIXME: USXGMII is not supported yet */ 813 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 814 815 config->mac_capabilities |= MAC_2500FD | MAC_5000FD | 816 MAC_10000FD; 817 } 818 } 819 820 if (port == 0) { 821 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 822 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 823 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 824 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 825 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 826 } 827 } 828 829 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 830 struct phylink_config *config) 831 { 832 struct mv88e6xxx_chip *chip = ds->priv; 833 834 chip->info->ops->phylink_get_caps(chip, port, config); 835 836 if (mv88e6xxx_phy_is_internal(ds, port)) { 837 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 838 config->supported_interfaces); 839 /* Internal ports with no phy-mode need GMII for PHYLIB */ 840 __set_bit(PHY_INTERFACE_MODE_GMII, 841 config->supported_interfaces); 842 } 843 } 844 845 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 846 unsigned int mode, 847 const struct phylink_link_state *state) 848 { 849 struct mv88e6xxx_chip *chip = ds->priv; 850 struct mv88e6xxx_port *p; 851 int err = 0; 852 853 p = &chip->ports[port]; 854 855 mv88e6xxx_reg_lock(chip); 856 857 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 858 /* In inband mode, the link may come up at any time while the 859 * link is not forced down. Force the link down while we 860 * reconfigure the interface mode. 861 */ 862 if (mode == MLO_AN_INBAND && 863 p->interface != state->interface && 864 chip->info->ops->port_set_link) 865 chip->info->ops->port_set_link(chip, port, 866 LINK_FORCED_DOWN); 867 868 err = mv88e6xxx_port_config_interface(chip, port, 869 state->interface); 870 if (err && err != -EOPNOTSUPP) 871 goto err_unlock; 872 873 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 874 state->interface, 875 state->advertising); 876 /* FIXME: we should restart negotiation if something changed - 877 * which is something we get if we convert to using phylinks 878 * PCS operations. 879 */ 880 if (err > 0) 881 err = 0; 882 } 883 884 /* Undo the forced down state above after completing configuration 885 * irrespective of its state on entry, which allows the link to come 886 * up in the in-band case where there is no separate SERDES. Also 887 * ensure that the link can come up if the PPU is in use and we are 888 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 889 */ 890 if (chip->info->ops->port_set_link && 891 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 892 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 893 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 894 895 p->interface = state->interface; 896 897 err_unlock: 898 mv88e6xxx_reg_unlock(chip); 899 900 if (err && err != -EOPNOTSUPP) 901 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 902 } 903 904 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 905 unsigned int mode, 906 phy_interface_t interface) 907 { 908 struct mv88e6xxx_chip *chip = ds->priv; 909 const struct mv88e6xxx_ops *ops; 910 int err = 0; 911 912 ops = chip->info->ops; 913 914 mv88e6xxx_reg_lock(chip); 915 /* Force the link down if we know the port may not be automatically 916 * updated by the switch or if we are using fixed-link mode. 917 */ 918 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 919 mode == MLO_AN_FIXED) && ops->port_sync_link) 920 err = ops->port_sync_link(chip, port, mode, false); 921 922 if (!err && ops->port_set_speed_duplex) 923 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 924 DUPLEX_UNFORCED); 925 mv88e6xxx_reg_unlock(chip); 926 927 if (err) 928 dev_err(chip->dev, 929 "p%d: failed to force MAC link down\n", port); 930 } 931 932 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 933 unsigned int mode, phy_interface_t interface, 934 struct phy_device *phydev, 935 int speed, int duplex, 936 bool tx_pause, bool rx_pause) 937 { 938 struct mv88e6xxx_chip *chip = ds->priv; 939 const struct mv88e6xxx_ops *ops; 940 int err = 0; 941 942 ops = chip->info->ops; 943 944 mv88e6xxx_reg_lock(chip); 945 /* Configure and force the link up if we know that the port may not 946 * automatically updated by the switch or if we are using fixed-link 947 * mode. 948 */ 949 if (!mv88e6xxx_port_ppu_updates(chip, port) || 950 mode == MLO_AN_FIXED) { 951 /* FIXME: for an automedia port, should we force the link 952 * down here - what if the link comes up due to "other" media 953 * while we're bringing the port up, how is the exclusivity 954 * handled in the Marvell hardware? E.g. port 2 on 88E6390 955 * shared between internal PHY and Serdes. 956 */ 957 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 958 duplex); 959 if (err) 960 goto error; 961 962 if (ops->port_set_speed_duplex) { 963 err = ops->port_set_speed_duplex(chip, port, 964 speed, duplex); 965 if (err && err != -EOPNOTSUPP) 966 goto error; 967 } 968 969 if (ops->port_sync_link) 970 err = ops->port_sync_link(chip, port, mode, true); 971 } 972 error: 973 mv88e6xxx_reg_unlock(chip); 974 975 if (err && err != -EOPNOTSUPP) 976 dev_err(ds->dev, 977 "p%d: failed to configure MAC link up\n", port); 978 } 979 980 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 981 { 982 if (!chip->info->ops->stats_snapshot) 983 return -EOPNOTSUPP; 984 985 return chip->info->ops->stats_snapshot(chip, port); 986 } 987 988 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 989 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 990 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 991 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 992 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 993 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 994 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 995 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 996 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 997 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 998 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 999 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 1000 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1001 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1002 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1003 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1004 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1005 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1006 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1007 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1008 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1009 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1010 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1011 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1012 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1013 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1014 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1015 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1016 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1017 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1018 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1019 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1020 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1021 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1022 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1023 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1024 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1025 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1026 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1027 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1028 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1029 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1030 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1031 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1032 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1033 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1034 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1035 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1036 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1037 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1038 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1039 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1040 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1041 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1042 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1043 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1044 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1045 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1046 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1047 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1048 }; 1049 1050 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1051 struct mv88e6xxx_hw_stat *s, 1052 int port, u16 bank1_select, 1053 u16 histogram) 1054 { 1055 u32 low; 1056 u32 high = 0; 1057 u16 reg = 0; 1058 int err; 1059 u64 value; 1060 1061 switch (s->type) { 1062 case STATS_TYPE_PORT: 1063 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1064 if (err) 1065 return U64_MAX; 1066 1067 low = reg; 1068 if (s->size == 4) { 1069 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1070 if (err) 1071 return U64_MAX; 1072 low |= ((u32)reg) << 16; 1073 } 1074 break; 1075 case STATS_TYPE_BANK1: 1076 reg = bank1_select; 1077 fallthrough; 1078 case STATS_TYPE_BANK0: 1079 reg |= s->reg | histogram; 1080 mv88e6xxx_g1_stats_read(chip, reg, &low); 1081 if (s->size == 8) 1082 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1083 break; 1084 default: 1085 return U64_MAX; 1086 } 1087 value = (((u64)high) << 32) | low; 1088 return value; 1089 } 1090 1091 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1092 uint8_t *data, int types) 1093 { 1094 struct mv88e6xxx_hw_stat *stat; 1095 int i, j; 1096 1097 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1098 stat = &mv88e6xxx_hw_stats[i]; 1099 if (stat->type & types) { 1100 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1101 ETH_GSTRING_LEN); 1102 j++; 1103 } 1104 } 1105 1106 return j; 1107 } 1108 1109 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1110 uint8_t *data) 1111 { 1112 return mv88e6xxx_stats_get_strings(chip, data, 1113 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1114 } 1115 1116 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1117 uint8_t *data) 1118 { 1119 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1120 } 1121 1122 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1123 uint8_t *data) 1124 { 1125 return mv88e6xxx_stats_get_strings(chip, data, 1126 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1127 } 1128 1129 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1130 "atu_member_violation", 1131 "atu_miss_violation", 1132 "atu_full_violation", 1133 "vtu_member_violation", 1134 "vtu_miss_violation", 1135 }; 1136 1137 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1138 { 1139 unsigned int i; 1140 1141 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1142 strscpy(data + i * ETH_GSTRING_LEN, 1143 mv88e6xxx_atu_vtu_stats_strings[i], 1144 ETH_GSTRING_LEN); 1145 } 1146 1147 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1148 u32 stringset, uint8_t *data) 1149 { 1150 struct mv88e6xxx_chip *chip = ds->priv; 1151 int count = 0; 1152 1153 if (stringset != ETH_SS_STATS) 1154 return; 1155 1156 mv88e6xxx_reg_lock(chip); 1157 1158 if (chip->info->ops->stats_get_strings) 1159 count = chip->info->ops->stats_get_strings(chip, data); 1160 1161 if (chip->info->ops->serdes_get_strings) { 1162 data += count * ETH_GSTRING_LEN; 1163 count = chip->info->ops->serdes_get_strings(chip, port, data); 1164 } 1165 1166 data += count * ETH_GSTRING_LEN; 1167 mv88e6xxx_atu_vtu_get_strings(data); 1168 1169 mv88e6xxx_reg_unlock(chip); 1170 } 1171 1172 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1173 int types) 1174 { 1175 struct mv88e6xxx_hw_stat *stat; 1176 int i, j; 1177 1178 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1179 stat = &mv88e6xxx_hw_stats[i]; 1180 if (stat->type & types) 1181 j++; 1182 } 1183 return j; 1184 } 1185 1186 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1187 { 1188 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1189 STATS_TYPE_PORT); 1190 } 1191 1192 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1193 { 1194 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1195 } 1196 1197 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1198 { 1199 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1200 STATS_TYPE_BANK1); 1201 } 1202 1203 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1204 { 1205 struct mv88e6xxx_chip *chip = ds->priv; 1206 int serdes_count = 0; 1207 int count = 0; 1208 1209 if (sset != ETH_SS_STATS) 1210 return 0; 1211 1212 mv88e6xxx_reg_lock(chip); 1213 if (chip->info->ops->stats_get_sset_count) 1214 count = chip->info->ops->stats_get_sset_count(chip); 1215 if (count < 0) 1216 goto out; 1217 1218 if (chip->info->ops->serdes_get_sset_count) 1219 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1220 port); 1221 if (serdes_count < 0) { 1222 count = serdes_count; 1223 goto out; 1224 } 1225 count += serdes_count; 1226 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1227 1228 out: 1229 mv88e6xxx_reg_unlock(chip); 1230 1231 return count; 1232 } 1233 1234 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1235 uint64_t *data, int types, 1236 u16 bank1_select, u16 histogram) 1237 { 1238 struct mv88e6xxx_hw_stat *stat; 1239 int i, j; 1240 1241 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1242 stat = &mv88e6xxx_hw_stats[i]; 1243 if (stat->type & types) { 1244 mv88e6xxx_reg_lock(chip); 1245 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1246 bank1_select, 1247 histogram); 1248 mv88e6xxx_reg_unlock(chip); 1249 1250 j++; 1251 } 1252 } 1253 return j; 1254 } 1255 1256 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1257 uint64_t *data) 1258 { 1259 return mv88e6xxx_stats_get_stats(chip, port, data, 1260 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1261 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1262 } 1263 1264 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1265 uint64_t *data) 1266 { 1267 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1268 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1269 } 1270 1271 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1272 uint64_t *data) 1273 { 1274 return mv88e6xxx_stats_get_stats(chip, port, data, 1275 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1276 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1277 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1278 } 1279 1280 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1281 uint64_t *data) 1282 { 1283 return mv88e6xxx_stats_get_stats(chip, port, data, 1284 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1285 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1286 0); 1287 } 1288 1289 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1290 uint64_t *data) 1291 { 1292 *data++ = chip->ports[port].atu_member_violation; 1293 *data++ = chip->ports[port].atu_miss_violation; 1294 *data++ = chip->ports[port].atu_full_violation; 1295 *data++ = chip->ports[port].vtu_member_violation; 1296 *data++ = chip->ports[port].vtu_miss_violation; 1297 } 1298 1299 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1300 uint64_t *data) 1301 { 1302 int count = 0; 1303 1304 if (chip->info->ops->stats_get_stats) 1305 count = chip->info->ops->stats_get_stats(chip, port, data); 1306 1307 mv88e6xxx_reg_lock(chip); 1308 if (chip->info->ops->serdes_get_stats) { 1309 data += count; 1310 count = chip->info->ops->serdes_get_stats(chip, port, data); 1311 } 1312 data += count; 1313 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1314 mv88e6xxx_reg_unlock(chip); 1315 } 1316 1317 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1318 uint64_t *data) 1319 { 1320 struct mv88e6xxx_chip *chip = ds->priv; 1321 int ret; 1322 1323 mv88e6xxx_reg_lock(chip); 1324 1325 ret = mv88e6xxx_stats_snapshot(chip, port); 1326 mv88e6xxx_reg_unlock(chip); 1327 1328 if (ret < 0) 1329 return; 1330 1331 mv88e6xxx_get_stats(chip, port, data); 1332 1333 } 1334 1335 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1336 { 1337 struct mv88e6xxx_chip *chip = ds->priv; 1338 int len; 1339 1340 len = 32 * sizeof(u16); 1341 if (chip->info->ops->serdes_get_regs_len) 1342 len += chip->info->ops->serdes_get_regs_len(chip, port); 1343 1344 return len; 1345 } 1346 1347 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1348 struct ethtool_regs *regs, void *_p) 1349 { 1350 struct mv88e6xxx_chip *chip = ds->priv; 1351 int err; 1352 u16 reg; 1353 u16 *p = _p; 1354 int i; 1355 1356 regs->version = chip->info->prod_num; 1357 1358 memset(p, 0xff, 32 * sizeof(u16)); 1359 1360 mv88e6xxx_reg_lock(chip); 1361 1362 for (i = 0; i < 32; i++) { 1363 1364 err = mv88e6xxx_port_read(chip, port, i, ®); 1365 if (!err) 1366 p[i] = reg; 1367 } 1368 1369 if (chip->info->ops->serdes_get_regs) 1370 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1371 1372 mv88e6xxx_reg_unlock(chip); 1373 } 1374 1375 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1376 struct ethtool_eee *e) 1377 { 1378 /* Nothing to do on the port's MAC */ 1379 return 0; 1380 } 1381 1382 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1383 struct ethtool_eee *e) 1384 { 1385 /* Nothing to do on the port's MAC */ 1386 return 0; 1387 } 1388 1389 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1390 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1391 { 1392 struct dsa_switch *ds = chip->ds; 1393 struct dsa_switch_tree *dst = ds->dst; 1394 struct dsa_port *dp, *other_dp; 1395 bool found = false; 1396 u16 pvlan; 1397 1398 /* dev is a physical switch */ 1399 if (dev <= dst->last_switch) { 1400 list_for_each_entry(dp, &dst->ports, list) { 1401 if (dp->ds->index == dev && dp->index == port) { 1402 /* dp might be a DSA link or a user port, so it 1403 * might or might not have a bridge. 1404 * Use the "found" variable for both cases. 1405 */ 1406 found = true; 1407 break; 1408 } 1409 } 1410 /* dev is a virtual bridge */ 1411 } else { 1412 list_for_each_entry(dp, &dst->ports, list) { 1413 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1414 1415 if (!bridge_num) 1416 continue; 1417 1418 if (bridge_num + dst->last_switch != dev) 1419 continue; 1420 1421 found = true; 1422 break; 1423 } 1424 } 1425 1426 /* Prevent frames from unknown switch or virtual bridge */ 1427 if (!found) 1428 return 0; 1429 1430 /* Frames from DSA links and CPU ports can egress any local port */ 1431 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1432 return mv88e6xxx_port_mask(chip); 1433 1434 pvlan = 0; 1435 1436 /* Frames from standalone user ports can only egress on the 1437 * upstream port. 1438 */ 1439 if (!dsa_port_bridge_dev_get(dp)) 1440 return BIT(dsa_switch_upstream_port(ds)); 1441 1442 /* Frames from bridged user ports can egress any local DSA 1443 * links and CPU ports, as well as any local member of their 1444 * bridge group. 1445 */ 1446 dsa_switch_for_each_port(other_dp, ds) 1447 if (other_dp->type == DSA_PORT_TYPE_CPU || 1448 other_dp->type == DSA_PORT_TYPE_DSA || 1449 dsa_port_bridge_same(dp, other_dp)) 1450 pvlan |= BIT(other_dp->index); 1451 1452 return pvlan; 1453 } 1454 1455 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1456 { 1457 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1458 1459 /* prevent frames from going back out of the port they came in on */ 1460 output_ports &= ~BIT(port); 1461 1462 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1463 } 1464 1465 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1466 u8 state) 1467 { 1468 struct mv88e6xxx_chip *chip = ds->priv; 1469 int err; 1470 1471 mv88e6xxx_reg_lock(chip); 1472 err = mv88e6xxx_port_set_state(chip, port, state); 1473 mv88e6xxx_reg_unlock(chip); 1474 1475 if (err) 1476 dev_err(ds->dev, "p%d: failed to update state\n", port); 1477 } 1478 1479 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1480 { 1481 int err; 1482 1483 if (chip->info->ops->ieee_pri_map) { 1484 err = chip->info->ops->ieee_pri_map(chip); 1485 if (err) 1486 return err; 1487 } 1488 1489 if (chip->info->ops->ip_pri_map) { 1490 err = chip->info->ops->ip_pri_map(chip); 1491 if (err) 1492 return err; 1493 } 1494 1495 return 0; 1496 } 1497 1498 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1499 { 1500 struct dsa_switch *ds = chip->ds; 1501 int target, port; 1502 int err; 1503 1504 if (!chip->info->global2_addr) 1505 return 0; 1506 1507 /* Initialize the routing port to the 32 possible target devices */ 1508 for (target = 0; target < 32; target++) { 1509 port = dsa_routing_port(ds, target); 1510 if (port == ds->num_ports) 1511 port = 0x1f; 1512 1513 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1514 if (err) 1515 return err; 1516 } 1517 1518 if (chip->info->ops->set_cascade_port) { 1519 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1520 err = chip->info->ops->set_cascade_port(chip, port); 1521 if (err) 1522 return err; 1523 } 1524 1525 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1526 if (err) 1527 return err; 1528 1529 return 0; 1530 } 1531 1532 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1533 { 1534 /* Clear all trunk masks and mapping */ 1535 if (chip->info->global2_addr) 1536 return mv88e6xxx_g2_trunk_clear(chip); 1537 1538 return 0; 1539 } 1540 1541 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1542 { 1543 if (chip->info->ops->rmu_disable) 1544 return chip->info->ops->rmu_disable(chip); 1545 1546 return 0; 1547 } 1548 1549 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1550 { 1551 if (chip->info->ops->pot_clear) 1552 return chip->info->ops->pot_clear(chip); 1553 1554 return 0; 1555 } 1556 1557 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1558 { 1559 if (chip->info->ops->mgmt_rsvd2cpu) 1560 return chip->info->ops->mgmt_rsvd2cpu(chip); 1561 1562 return 0; 1563 } 1564 1565 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1566 { 1567 int err; 1568 1569 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1570 if (err) 1571 return err; 1572 1573 /* The chips that have a "learn2all" bit in Global1, ATU 1574 * Control are precisely those whose port registers have a 1575 * Message Port bit in Port Control 1 and hence implement 1576 * ->port_setup_message_port. 1577 */ 1578 if (chip->info->ops->port_setup_message_port) { 1579 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1580 if (err) 1581 return err; 1582 } 1583 1584 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1585 } 1586 1587 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1588 { 1589 int port; 1590 int err; 1591 1592 if (!chip->info->ops->irl_init_all) 1593 return 0; 1594 1595 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1596 /* Disable ingress rate limiting by resetting all per port 1597 * ingress rate limit resources to their initial state. 1598 */ 1599 err = chip->info->ops->irl_init_all(chip, port); 1600 if (err) 1601 return err; 1602 } 1603 1604 return 0; 1605 } 1606 1607 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1608 { 1609 if (chip->info->ops->set_switch_mac) { 1610 u8 addr[ETH_ALEN]; 1611 1612 eth_random_addr(addr); 1613 1614 return chip->info->ops->set_switch_mac(chip, addr); 1615 } 1616 1617 return 0; 1618 } 1619 1620 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1621 { 1622 struct dsa_switch_tree *dst = chip->ds->dst; 1623 struct dsa_switch *ds; 1624 struct dsa_port *dp; 1625 u16 pvlan = 0; 1626 1627 if (!mv88e6xxx_has_pvt(chip)) 1628 return 0; 1629 1630 /* Skip the local source device, which uses in-chip port VLAN */ 1631 if (dev != chip->ds->index) { 1632 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1633 1634 ds = dsa_switch_find(dst->index, dev); 1635 dp = ds ? dsa_to_port(ds, port) : NULL; 1636 if (dp && dp->lag) { 1637 /* As the PVT is used to limit flooding of 1638 * FORWARD frames, which use the LAG ID as the 1639 * source port, we must translate dev/port to 1640 * the special "LAG device" in the PVT, using 1641 * the LAG ID (one-based) as the port number 1642 * (zero-based). 1643 */ 1644 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1645 port = dsa_port_lag_id_get(dp) - 1; 1646 } 1647 } 1648 1649 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1650 } 1651 1652 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1653 { 1654 int dev, port; 1655 int err; 1656 1657 if (!mv88e6xxx_has_pvt(chip)) 1658 return 0; 1659 1660 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1661 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1662 */ 1663 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1664 if (err) 1665 return err; 1666 1667 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1668 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1669 err = mv88e6xxx_pvt_map(chip, dev, port); 1670 if (err) 1671 return err; 1672 } 1673 } 1674 1675 return 0; 1676 } 1677 1678 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1679 u16 fid) 1680 { 1681 if (dsa_to_port(chip->ds, port)->lag) 1682 /* Hardware is incapable of fast-aging a LAG through a 1683 * regular ATU move operation. Until we have something 1684 * more fancy in place this is a no-op. 1685 */ 1686 return -EOPNOTSUPP; 1687 1688 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1689 } 1690 1691 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1692 { 1693 struct mv88e6xxx_chip *chip = ds->priv; 1694 int err; 1695 1696 mv88e6xxx_reg_lock(chip); 1697 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1698 mv88e6xxx_reg_unlock(chip); 1699 1700 if (err) 1701 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1702 port, err); 1703 } 1704 1705 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1706 { 1707 if (!mv88e6xxx_max_vid(chip)) 1708 return 0; 1709 1710 return mv88e6xxx_g1_vtu_flush(chip); 1711 } 1712 1713 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1714 struct mv88e6xxx_vtu_entry *entry) 1715 { 1716 int err; 1717 1718 if (!chip->info->ops->vtu_getnext) 1719 return -EOPNOTSUPP; 1720 1721 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1722 entry->valid = false; 1723 1724 err = chip->info->ops->vtu_getnext(chip, entry); 1725 1726 if (entry->vid != vid) 1727 entry->valid = false; 1728 1729 return err; 1730 } 1731 1732 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1733 int (*cb)(struct mv88e6xxx_chip *chip, 1734 const struct mv88e6xxx_vtu_entry *entry, 1735 void *priv), 1736 void *priv) 1737 { 1738 struct mv88e6xxx_vtu_entry entry = { 1739 .vid = mv88e6xxx_max_vid(chip), 1740 .valid = false, 1741 }; 1742 int err; 1743 1744 if (!chip->info->ops->vtu_getnext) 1745 return -EOPNOTSUPP; 1746 1747 do { 1748 err = chip->info->ops->vtu_getnext(chip, &entry); 1749 if (err) 1750 return err; 1751 1752 if (!entry.valid) 1753 break; 1754 1755 err = cb(chip, &entry, priv); 1756 if (err) 1757 return err; 1758 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1759 1760 return 0; 1761 } 1762 1763 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1764 struct mv88e6xxx_vtu_entry *entry) 1765 { 1766 if (!chip->info->ops->vtu_loadpurge) 1767 return -EOPNOTSUPP; 1768 1769 return chip->info->ops->vtu_loadpurge(chip, entry); 1770 } 1771 1772 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1773 const struct mv88e6xxx_vtu_entry *entry, 1774 void *_fid_bitmap) 1775 { 1776 unsigned long *fid_bitmap = _fid_bitmap; 1777 1778 set_bit(entry->fid, fid_bitmap); 1779 return 0; 1780 } 1781 1782 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1783 { 1784 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1785 1786 /* Every FID has an associated VID, so walking the VTU 1787 * will discover the full set of FIDs in use. 1788 */ 1789 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1790 } 1791 1792 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1793 { 1794 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1795 int err; 1796 1797 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1798 if (err) 1799 return err; 1800 1801 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1802 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1803 return -ENOSPC; 1804 1805 /* Clear the database */ 1806 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1807 } 1808 1809 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1810 struct mv88e6xxx_stu_entry *entry) 1811 { 1812 if (!chip->info->ops->stu_loadpurge) 1813 return -EOPNOTSUPP; 1814 1815 return chip->info->ops->stu_loadpurge(chip, entry); 1816 } 1817 1818 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1819 { 1820 struct mv88e6xxx_stu_entry stu = { 1821 .valid = true, 1822 .sid = 0 1823 }; 1824 1825 if (!mv88e6xxx_has_stu(chip)) 1826 return 0; 1827 1828 /* Make sure that SID 0 is always valid. This is used by VTU 1829 * entries that do not make use of the STU, e.g. when creating 1830 * a VLAN upper on a port that is also part of a VLAN 1831 * filtering bridge. 1832 */ 1833 return mv88e6xxx_stu_loadpurge(chip, &stu); 1834 } 1835 1836 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1837 { 1838 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1839 struct mv88e6xxx_mst *mst; 1840 1841 __set_bit(0, busy); 1842 1843 list_for_each_entry(mst, &chip->msts, node) 1844 __set_bit(mst->stu.sid, busy); 1845 1846 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1847 1848 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1849 } 1850 1851 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1852 { 1853 struct mv88e6xxx_mst *mst, *tmp; 1854 int err; 1855 1856 if (!sid) 1857 return 0; 1858 1859 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1860 if (mst->stu.sid != sid) 1861 continue; 1862 1863 if (!refcount_dec_and_test(&mst->refcnt)) 1864 return 0; 1865 1866 mst->stu.valid = false; 1867 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1868 if (err) { 1869 refcount_set(&mst->refcnt, 1); 1870 return err; 1871 } 1872 1873 list_del(&mst->node); 1874 kfree(mst); 1875 return 0; 1876 } 1877 1878 return -ENOENT; 1879 } 1880 1881 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1882 u16 msti, u8 *sid) 1883 { 1884 struct mv88e6xxx_mst *mst; 1885 int err, i; 1886 1887 if (!mv88e6xxx_has_stu(chip)) { 1888 err = -EOPNOTSUPP; 1889 goto err; 1890 } 1891 1892 if (!msti) { 1893 *sid = 0; 1894 return 0; 1895 } 1896 1897 list_for_each_entry(mst, &chip->msts, node) { 1898 if (mst->br == br && mst->msti == msti) { 1899 refcount_inc(&mst->refcnt); 1900 *sid = mst->stu.sid; 1901 return 0; 1902 } 1903 } 1904 1905 err = mv88e6xxx_sid_get(chip, sid); 1906 if (err) 1907 goto err; 1908 1909 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1910 if (!mst) { 1911 err = -ENOMEM; 1912 goto err; 1913 } 1914 1915 INIT_LIST_HEAD(&mst->node); 1916 refcount_set(&mst->refcnt, 1); 1917 mst->br = br; 1918 mst->msti = msti; 1919 mst->stu.valid = true; 1920 mst->stu.sid = *sid; 1921 1922 /* The bridge starts out all ports in the disabled state. But 1923 * a STU state of disabled means to go by the port-global 1924 * state. So we set all user port's initial state to blocking, 1925 * to match the bridge's behavior. 1926 */ 1927 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1928 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1929 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1930 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1931 1932 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1933 if (err) 1934 goto err_free; 1935 1936 list_add_tail(&mst->node, &chip->msts); 1937 return 0; 1938 1939 err_free: 1940 kfree(mst); 1941 err: 1942 return err; 1943 } 1944 1945 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1946 const struct switchdev_mst_state *st) 1947 { 1948 struct dsa_port *dp = dsa_to_port(ds, port); 1949 struct mv88e6xxx_chip *chip = ds->priv; 1950 struct mv88e6xxx_mst *mst; 1951 u8 state; 1952 int err; 1953 1954 if (!mv88e6xxx_has_stu(chip)) 1955 return -EOPNOTSUPP; 1956 1957 switch (st->state) { 1958 case BR_STATE_DISABLED: 1959 case BR_STATE_BLOCKING: 1960 case BR_STATE_LISTENING: 1961 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1962 break; 1963 case BR_STATE_LEARNING: 1964 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1965 break; 1966 case BR_STATE_FORWARDING: 1967 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1968 break; 1969 default: 1970 return -EINVAL; 1971 } 1972 1973 list_for_each_entry(mst, &chip->msts, node) { 1974 if (mst->br == dsa_port_bridge_dev_get(dp) && 1975 mst->msti == st->msti) { 1976 if (mst->stu.state[port] == state) 1977 return 0; 1978 1979 mst->stu.state[port] = state; 1980 mv88e6xxx_reg_lock(chip); 1981 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1982 mv88e6xxx_reg_unlock(chip); 1983 return err; 1984 } 1985 } 1986 1987 return -ENOENT; 1988 } 1989 1990 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1991 u16 vid) 1992 { 1993 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1994 struct mv88e6xxx_chip *chip = ds->priv; 1995 struct mv88e6xxx_vtu_entry vlan; 1996 int err; 1997 1998 /* DSA and CPU ports have to be members of multiple vlans */ 1999 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2000 return 0; 2001 2002 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2003 if (err) 2004 return err; 2005 2006 if (!vlan.valid) 2007 return 0; 2008 2009 dsa_switch_for_each_user_port(other_dp, ds) { 2010 struct net_device *other_br; 2011 2012 if (vlan.member[other_dp->index] == 2013 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2014 continue; 2015 2016 if (dsa_port_bridge_same(dp, other_dp)) 2017 break; /* same bridge, check next VLAN */ 2018 2019 other_br = dsa_port_bridge_dev_get(other_dp); 2020 if (!other_br) 2021 continue; 2022 2023 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2024 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2025 return -EOPNOTSUPP; 2026 } 2027 2028 return 0; 2029 } 2030 2031 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2032 { 2033 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2034 struct net_device *br = dsa_port_bridge_dev_get(dp); 2035 struct mv88e6xxx_port *p = &chip->ports[port]; 2036 u16 pvid = MV88E6XXX_VID_STANDALONE; 2037 bool drop_untagged = false; 2038 int err; 2039 2040 if (br) { 2041 if (br_vlan_enabled(br)) { 2042 pvid = p->bridge_pvid.vid; 2043 drop_untagged = !p->bridge_pvid.valid; 2044 } else { 2045 pvid = MV88E6XXX_VID_BRIDGED; 2046 } 2047 } 2048 2049 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2050 if (err) 2051 return err; 2052 2053 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2054 } 2055 2056 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2057 bool vlan_filtering, 2058 struct netlink_ext_ack *extack) 2059 { 2060 struct mv88e6xxx_chip *chip = ds->priv; 2061 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2062 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2063 int err; 2064 2065 if (!mv88e6xxx_max_vid(chip)) 2066 return -EOPNOTSUPP; 2067 2068 mv88e6xxx_reg_lock(chip); 2069 2070 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2071 if (err) 2072 goto unlock; 2073 2074 err = mv88e6xxx_port_commit_pvid(chip, port); 2075 if (err) 2076 goto unlock; 2077 2078 unlock: 2079 mv88e6xxx_reg_unlock(chip); 2080 2081 return err; 2082 } 2083 2084 static int 2085 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2086 const struct switchdev_obj_port_vlan *vlan) 2087 { 2088 struct mv88e6xxx_chip *chip = ds->priv; 2089 int err; 2090 2091 if (!mv88e6xxx_max_vid(chip)) 2092 return -EOPNOTSUPP; 2093 2094 /* If the requested port doesn't belong to the same bridge as the VLAN 2095 * members, do not support it (yet) and fallback to software VLAN. 2096 */ 2097 mv88e6xxx_reg_lock(chip); 2098 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2099 mv88e6xxx_reg_unlock(chip); 2100 2101 return err; 2102 } 2103 2104 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2105 const unsigned char *addr, u16 vid, 2106 u8 state) 2107 { 2108 struct mv88e6xxx_atu_entry entry; 2109 struct mv88e6xxx_vtu_entry vlan; 2110 u16 fid; 2111 int err; 2112 2113 /* Ports have two private address databases: one for when the port is 2114 * standalone and one for when the port is under a bridge and the 2115 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2116 * address database to remain 100% empty, so we never load an ATU entry 2117 * into a standalone port's database. Therefore, translate the null 2118 * VLAN ID into the port's database used for VLAN-unaware bridging. 2119 */ 2120 if (vid == 0) { 2121 fid = MV88E6XXX_FID_BRIDGED; 2122 } else { 2123 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2124 if (err) 2125 return err; 2126 2127 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2128 if (!vlan.valid) 2129 return -EOPNOTSUPP; 2130 2131 fid = vlan.fid; 2132 } 2133 2134 entry.state = 0; 2135 ether_addr_copy(entry.mac, addr); 2136 eth_addr_dec(entry.mac); 2137 2138 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2139 if (err) 2140 return err; 2141 2142 /* Initialize a fresh ATU entry if it isn't found */ 2143 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2144 memset(&entry, 0, sizeof(entry)); 2145 ether_addr_copy(entry.mac, addr); 2146 } 2147 2148 /* Purge the ATU entry only if no port is using it anymore */ 2149 if (!state) { 2150 entry.portvec &= ~BIT(port); 2151 if (!entry.portvec) 2152 entry.state = 0; 2153 } else { 2154 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2155 entry.portvec = BIT(port); 2156 else 2157 entry.portvec |= BIT(port); 2158 2159 entry.state = state; 2160 } 2161 2162 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2163 } 2164 2165 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2166 const struct mv88e6xxx_policy *policy) 2167 { 2168 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2169 enum mv88e6xxx_policy_action action = policy->action; 2170 const u8 *addr = policy->addr; 2171 u16 vid = policy->vid; 2172 u8 state; 2173 int err; 2174 int id; 2175 2176 if (!chip->info->ops->port_set_policy) 2177 return -EOPNOTSUPP; 2178 2179 switch (mapping) { 2180 case MV88E6XXX_POLICY_MAPPING_DA: 2181 case MV88E6XXX_POLICY_MAPPING_SA: 2182 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2183 state = 0; /* Dissociate the port and address */ 2184 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2185 is_multicast_ether_addr(addr)) 2186 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2187 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2188 is_unicast_ether_addr(addr)) 2189 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2190 else 2191 return -EOPNOTSUPP; 2192 2193 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2194 state); 2195 if (err) 2196 return err; 2197 break; 2198 default: 2199 return -EOPNOTSUPP; 2200 } 2201 2202 /* Skip the port's policy clearing if the mapping is still in use */ 2203 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2204 idr_for_each_entry(&chip->policies, policy, id) 2205 if (policy->port == port && 2206 policy->mapping == mapping && 2207 policy->action != action) 2208 return 0; 2209 2210 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2211 } 2212 2213 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2214 struct ethtool_rx_flow_spec *fs) 2215 { 2216 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2217 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2218 enum mv88e6xxx_policy_mapping mapping; 2219 enum mv88e6xxx_policy_action action; 2220 struct mv88e6xxx_policy *policy; 2221 u16 vid = 0; 2222 u8 *addr; 2223 int err; 2224 int id; 2225 2226 if (fs->location != RX_CLS_LOC_ANY) 2227 return -EINVAL; 2228 2229 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2230 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2231 else 2232 return -EOPNOTSUPP; 2233 2234 switch (fs->flow_type & ~FLOW_EXT) { 2235 case ETHER_FLOW: 2236 if (!is_zero_ether_addr(mac_mask->h_dest) && 2237 is_zero_ether_addr(mac_mask->h_source)) { 2238 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2239 addr = mac_entry->h_dest; 2240 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2241 !is_zero_ether_addr(mac_mask->h_source)) { 2242 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2243 addr = mac_entry->h_source; 2244 } else { 2245 /* Cannot support DA and SA mapping in the same rule */ 2246 return -EOPNOTSUPP; 2247 } 2248 break; 2249 default: 2250 return -EOPNOTSUPP; 2251 } 2252 2253 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2254 if (fs->m_ext.vlan_tci != htons(0xffff)) 2255 return -EOPNOTSUPP; 2256 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2257 } 2258 2259 idr_for_each_entry(&chip->policies, policy, id) { 2260 if (policy->port == port && policy->mapping == mapping && 2261 policy->action == action && policy->vid == vid && 2262 ether_addr_equal(policy->addr, addr)) 2263 return -EEXIST; 2264 } 2265 2266 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2267 if (!policy) 2268 return -ENOMEM; 2269 2270 fs->location = 0; 2271 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2272 GFP_KERNEL); 2273 if (err) { 2274 devm_kfree(chip->dev, policy); 2275 return err; 2276 } 2277 2278 memcpy(&policy->fs, fs, sizeof(*fs)); 2279 ether_addr_copy(policy->addr, addr); 2280 policy->mapping = mapping; 2281 policy->action = action; 2282 policy->port = port; 2283 policy->vid = vid; 2284 2285 err = mv88e6xxx_policy_apply(chip, port, policy); 2286 if (err) { 2287 idr_remove(&chip->policies, fs->location); 2288 devm_kfree(chip->dev, policy); 2289 return err; 2290 } 2291 2292 return 0; 2293 } 2294 2295 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2296 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2297 { 2298 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2299 struct mv88e6xxx_chip *chip = ds->priv; 2300 struct mv88e6xxx_policy *policy; 2301 int err; 2302 int id; 2303 2304 mv88e6xxx_reg_lock(chip); 2305 2306 switch (rxnfc->cmd) { 2307 case ETHTOOL_GRXCLSRLCNT: 2308 rxnfc->data = 0; 2309 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2310 rxnfc->rule_cnt = 0; 2311 idr_for_each_entry(&chip->policies, policy, id) 2312 if (policy->port == port) 2313 rxnfc->rule_cnt++; 2314 err = 0; 2315 break; 2316 case ETHTOOL_GRXCLSRULE: 2317 err = -ENOENT; 2318 policy = idr_find(&chip->policies, fs->location); 2319 if (policy) { 2320 memcpy(fs, &policy->fs, sizeof(*fs)); 2321 err = 0; 2322 } 2323 break; 2324 case ETHTOOL_GRXCLSRLALL: 2325 rxnfc->data = 0; 2326 rxnfc->rule_cnt = 0; 2327 idr_for_each_entry(&chip->policies, policy, id) 2328 if (policy->port == port) 2329 rule_locs[rxnfc->rule_cnt++] = id; 2330 err = 0; 2331 break; 2332 default: 2333 err = -EOPNOTSUPP; 2334 break; 2335 } 2336 2337 mv88e6xxx_reg_unlock(chip); 2338 2339 return err; 2340 } 2341 2342 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2343 struct ethtool_rxnfc *rxnfc) 2344 { 2345 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2346 struct mv88e6xxx_chip *chip = ds->priv; 2347 struct mv88e6xxx_policy *policy; 2348 int err; 2349 2350 mv88e6xxx_reg_lock(chip); 2351 2352 switch (rxnfc->cmd) { 2353 case ETHTOOL_SRXCLSRLINS: 2354 err = mv88e6xxx_policy_insert(chip, port, fs); 2355 break; 2356 case ETHTOOL_SRXCLSRLDEL: 2357 err = -ENOENT; 2358 policy = idr_remove(&chip->policies, fs->location); 2359 if (policy) { 2360 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2361 err = mv88e6xxx_policy_apply(chip, port, policy); 2362 devm_kfree(chip->dev, policy); 2363 } 2364 break; 2365 default: 2366 err = -EOPNOTSUPP; 2367 break; 2368 } 2369 2370 mv88e6xxx_reg_unlock(chip); 2371 2372 return err; 2373 } 2374 2375 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2376 u16 vid) 2377 { 2378 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2379 u8 broadcast[ETH_ALEN]; 2380 2381 eth_broadcast_addr(broadcast); 2382 2383 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2384 } 2385 2386 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2387 { 2388 int port; 2389 int err; 2390 2391 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2392 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2393 struct net_device *brport; 2394 2395 if (dsa_is_unused_port(chip->ds, port)) 2396 continue; 2397 2398 brport = dsa_port_to_bridge_port(dp); 2399 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2400 /* Skip bridged user ports where broadcast 2401 * flooding is disabled. 2402 */ 2403 continue; 2404 2405 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2406 if (err) 2407 return err; 2408 } 2409 2410 return 0; 2411 } 2412 2413 struct mv88e6xxx_port_broadcast_sync_ctx { 2414 int port; 2415 bool flood; 2416 }; 2417 2418 static int 2419 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2420 const struct mv88e6xxx_vtu_entry *vlan, 2421 void *_ctx) 2422 { 2423 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2424 u8 broadcast[ETH_ALEN]; 2425 u8 state; 2426 2427 if (ctx->flood) 2428 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2429 else 2430 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2431 2432 eth_broadcast_addr(broadcast); 2433 2434 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2435 vlan->vid, state); 2436 } 2437 2438 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2439 bool flood) 2440 { 2441 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2442 .port = port, 2443 .flood = flood, 2444 }; 2445 struct mv88e6xxx_vtu_entry vid0 = { 2446 .vid = 0, 2447 }; 2448 int err; 2449 2450 /* Update the port's private database... */ 2451 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2452 if (err) 2453 return err; 2454 2455 /* ...and the database for all VLANs. */ 2456 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2457 &ctx); 2458 } 2459 2460 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2461 u16 vid, u8 member, bool warn) 2462 { 2463 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2464 struct mv88e6xxx_vtu_entry vlan; 2465 int i, err; 2466 2467 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2468 if (err) 2469 return err; 2470 2471 if (!vlan.valid) { 2472 memset(&vlan, 0, sizeof(vlan)); 2473 2474 if (vid == MV88E6XXX_VID_STANDALONE) 2475 vlan.policy = true; 2476 2477 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2478 if (err) 2479 return err; 2480 2481 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2482 if (i == port) 2483 vlan.member[i] = member; 2484 else 2485 vlan.member[i] = non_member; 2486 2487 vlan.vid = vid; 2488 vlan.valid = true; 2489 2490 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2491 if (err) 2492 return err; 2493 2494 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2495 if (err) 2496 return err; 2497 } else if (vlan.member[port] != member) { 2498 vlan.member[port] = member; 2499 2500 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2501 if (err) 2502 return err; 2503 } else if (warn) { 2504 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2505 port, vid); 2506 } 2507 2508 return 0; 2509 } 2510 2511 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2512 const struct switchdev_obj_port_vlan *vlan, 2513 struct netlink_ext_ack *extack) 2514 { 2515 struct mv88e6xxx_chip *chip = ds->priv; 2516 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2517 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2518 struct mv88e6xxx_port *p = &chip->ports[port]; 2519 bool warn; 2520 u8 member; 2521 int err; 2522 2523 if (!vlan->vid) 2524 return 0; 2525 2526 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2527 if (err) 2528 return err; 2529 2530 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2531 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2532 else if (untagged) 2533 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2534 else 2535 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2536 2537 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2538 * and then the CPU port. Do not warn for duplicates for the CPU port. 2539 */ 2540 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2541 2542 mv88e6xxx_reg_lock(chip); 2543 2544 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2545 if (err) { 2546 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2547 vlan->vid, untagged ? 'u' : 't'); 2548 goto out; 2549 } 2550 2551 if (pvid) { 2552 p->bridge_pvid.vid = vlan->vid; 2553 p->bridge_pvid.valid = true; 2554 2555 err = mv88e6xxx_port_commit_pvid(chip, port); 2556 if (err) 2557 goto out; 2558 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2559 /* The old pvid was reinstalled as a non-pvid VLAN */ 2560 p->bridge_pvid.valid = false; 2561 2562 err = mv88e6xxx_port_commit_pvid(chip, port); 2563 if (err) 2564 goto out; 2565 } 2566 2567 out: 2568 mv88e6xxx_reg_unlock(chip); 2569 2570 return err; 2571 } 2572 2573 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2574 int port, u16 vid) 2575 { 2576 struct mv88e6xxx_vtu_entry vlan; 2577 int i, err; 2578 2579 if (!vid) 2580 return 0; 2581 2582 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2583 if (err) 2584 return err; 2585 2586 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2587 * tell switchdev that this VLAN is likely handled in software. 2588 */ 2589 if (!vlan.valid || 2590 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2591 return -EOPNOTSUPP; 2592 2593 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2594 2595 /* keep the VLAN unless all ports are excluded */ 2596 vlan.valid = false; 2597 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2598 if (vlan.member[i] != 2599 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2600 vlan.valid = true; 2601 break; 2602 } 2603 } 2604 2605 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2606 if (err) 2607 return err; 2608 2609 if (!vlan.valid) { 2610 err = mv88e6xxx_mst_put(chip, vlan.sid); 2611 if (err) 2612 return err; 2613 } 2614 2615 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2616 } 2617 2618 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2619 const struct switchdev_obj_port_vlan *vlan) 2620 { 2621 struct mv88e6xxx_chip *chip = ds->priv; 2622 struct mv88e6xxx_port *p = &chip->ports[port]; 2623 int err = 0; 2624 u16 pvid; 2625 2626 if (!mv88e6xxx_max_vid(chip)) 2627 return -EOPNOTSUPP; 2628 2629 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2630 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2631 * switchdev workqueue to ensure that all FDB entries are deleted 2632 * before we remove the VLAN. 2633 */ 2634 dsa_flush_workqueue(); 2635 2636 mv88e6xxx_reg_lock(chip); 2637 2638 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2639 if (err) 2640 goto unlock; 2641 2642 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2643 if (err) 2644 goto unlock; 2645 2646 if (vlan->vid == pvid) { 2647 p->bridge_pvid.valid = false; 2648 2649 err = mv88e6xxx_port_commit_pvid(chip, port); 2650 if (err) 2651 goto unlock; 2652 } 2653 2654 unlock: 2655 mv88e6xxx_reg_unlock(chip); 2656 2657 return err; 2658 } 2659 2660 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2661 { 2662 struct mv88e6xxx_chip *chip = ds->priv; 2663 struct mv88e6xxx_vtu_entry vlan; 2664 int err; 2665 2666 mv88e6xxx_reg_lock(chip); 2667 2668 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2669 if (err) 2670 goto unlock; 2671 2672 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2673 2674 unlock: 2675 mv88e6xxx_reg_unlock(chip); 2676 2677 return err; 2678 } 2679 2680 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2681 struct dsa_bridge bridge, 2682 const struct switchdev_vlan_msti *msti) 2683 { 2684 struct mv88e6xxx_chip *chip = ds->priv; 2685 struct mv88e6xxx_vtu_entry vlan; 2686 u8 old_sid, new_sid; 2687 int err; 2688 2689 if (!mv88e6xxx_has_stu(chip)) 2690 return -EOPNOTSUPP; 2691 2692 mv88e6xxx_reg_lock(chip); 2693 2694 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2695 if (err) 2696 goto unlock; 2697 2698 if (!vlan.valid) { 2699 err = -EINVAL; 2700 goto unlock; 2701 } 2702 2703 old_sid = vlan.sid; 2704 2705 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2706 if (err) 2707 goto unlock; 2708 2709 if (new_sid != old_sid) { 2710 vlan.sid = new_sid; 2711 2712 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2713 if (err) { 2714 mv88e6xxx_mst_put(chip, new_sid); 2715 goto unlock; 2716 } 2717 } 2718 2719 err = mv88e6xxx_mst_put(chip, old_sid); 2720 2721 unlock: 2722 mv88e6xxx_reg_unlock(chip); 2723 return err; 2724 } 2725 2726 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2727 const unsigned char *addr, u16 vid, 2728 struct dsa_db db) 2729 { 2730 struct mv88e6xxx_chip *chip = ds->priv; 2731 int err; 2732 2733 mv88e6xxx_reg_lock(chip); 2734 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2735 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2736 mv88e6xxx_reg_unlock(chip); 2737 2738 return err; 2739 } 2740 2741 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2742 const unsigned char *addr, u16 vid, 2743 struct dsa_db db) 2744 { 2745 struct mv88e6xxx_chip *chip = ds->priv; 2746 int err; 2747 2748 mv88e6xxx_reg_lock(chip); 2749 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2750 mv88e6xxx_reg_unlock(chip); 2751 2752 return err; 2753 } 2754 2755 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2756 u16 fid, u16 vid, int port, 2757 dsa_fdb_dump_cb_t *cb, void *data) 2758 { 2759 struct mv88e6xxx_atu_entry addr; 2760 bool is_static; 2761 int err; 2762 2763 addr.state = 0; 2764 eth_broadcast_addr(addr.mac); 2765 2766 do { 2767 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2768 if (err) 2769 return err; 2770 2771 if (!addr.state) 2772 break; 2773 2774 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2775 continue; 2776 2777 if (!is_unicast_ether_addr(addr.mac)) 2778 continue; 2779 2780 is_static = (addr.state == 2781 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2782 err = cb(addr.mac, vid, is_static, data); 2783 if (err) 2784 return err; 2785 } while (!is_broadcast_ether_addr(addr.mac)); 2786 2787 return err; 2788 } 2789 2790 struct mv88e6xxx_port_db_dump_vlan_ctx { 2791 int port; 2792 dsa_fdb_dump_cb_t *cb; 2793 void *data; 2794 }; 2795 2796 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2797 const struct mv88e6xxx_vtu_entry *entry, 2798 void *_data) 2799 { 2800 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2801 2802 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2803 ctx->port, ctx->cb, ctx->data); 2804 } 2805 2806 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2807 dsa_fdb_dump_cb_t *cb, void *data) 2808 { 2809 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2810 .port = port, 2811 .cb = cb, 2812 .data = data, 2813 }; 2814 u16 fid; 2815 int err; 2816 2817 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2818 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2819 if (err) 2820 return err; 2821 2822 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2823 if (err) 2824 return err; 2825 2826 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2827 } 2828 2829 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2830 dsa_fdb_dump_cb_t *cb, void *data) 2831 { 2832 struct mv88e6xxx_chip *chip = ds->priv; 2833 int err; 2834 2835 mv88e6xxx_reg_lock(chip); 2836 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2837 mv88e6xxx_reg_unlock(chip); 2838 2839 return err; 2840 } 2841 2842 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2843 struct dsa_bridge bridge) 2844 { 2845 struct dsa_switch *ds = chip->ds; 2846 struct dsa_switch_tree *dst = ds->dst; 2847 struct dsa_port *dp; 2848 int err; 2849 2850 list_for_each_entry(dp, &dst->ports, list) { 2851 if (dsa_port_offloads_bridge(dp, &bridge)) { 2852 if (dp->ds == ds) { 2853 /* This is a local bridge group member, 2854 * remap its Port VLAN Map. 2855 */ 2856 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2857 if (err) 2858 return err; 2859 } else { 2860 /* This is an external bridge group member, 2861 * remap its cross-chip Port VLAN Table entry. 2862 */ 2863 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2864 dp->index); 2865 if (err) 2866 return err; 2867 } 2868 } 2869 } 2870 2871 return 0; 2872 } 2873 2874 /* Treat the software bridge as a virtual single-port switch behind the 2875 * CPU and map in the PVT. First dst->last_switch elements are taken by 2876 * physical switches, so start from beyond that range. 2877 */ 2878 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2879 unsigned int bridge_num) 2880 { 2881 u8 dev = bridge_num + ds->dst->last_switch; 2882 struct mv88e6xxx_chip *chip = ds->priv; 2883 2884 return mv88e6xxx_pvt_map(chip, dev, 0); 2885 } 2886 2887 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2888 struct dsa_bridge bridge, 2889 bool *tx_fwd_offload, 2890 struct netlink_ext_ack *extack) 2891 { 2892 struct mv88e6xxx_chip *chip = ds->priv; 2893 int err; 2894 2895 mv88e6xxx_reg_lock(chip); 2896 2897 err = mv88e6xxx_bridge_map(chip, bridge); 2898 if (err) 2899 goto unlock; 2900 2901 err = mv88e6xxx_port_set_map_da(chip, port, true); 2902 if (err) 2903 goto unlock; 2904 2905 err = mv88e6xxx_port_commit_pvid(chip, port); 2906 if (err) 2907 goto unlock; 2908 2909 if (mv88e6xxx_has_pvt(chip)) { 2910 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2911 if (err) 2912 goto unlock; 2913 2914 *tx_fwd_offload = true; 2915 } 2916 2917 unlock: 2918 mv88e6xxx_reg_unlock(chip); 2919 2920 return err; 2921 } 2922 2923 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2924 struct dsa_bridge bridge) 2925 { 2926 struct mv88e6xxx_chip *chip = ds->priv; 2927 int err; 2928 2929 mv88e6xxx_reg_lock(chip); 2930 2931 if (bridge.tx_fwd_offload && 2932 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2933 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2934 2935 if (mv88e6xxx_bridge_map(chip, bridge) || 2936 mv88e6xxx_port_vlan_map(chip, port)) 2937 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2938 2939 err = mv88e6xxx_port_set_map_da(chip, port, false); 2940 if (err) 2941 dev_err(ds->dev, 2942 "port %d failed to restore map-DA: %pe\n", 2943 port, ERR_PTR(err)); 2944 2945 err = mv88e6xxx_port_commit_pvid(chip, port); 2946 if (err) 2947 dev_err(ds->dev, 2948 "port %d failed to restore standalone pvid: %pe\n", 2949 port, ERR_PTR(err)); 2950 2951 mv88e6xxx_reg_unlock(chip); 2952 } 2953 2954 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2955 int tree_index, int sw_index, 2956 int port, struct dsa_bridge bridge, 2957 struct netlink_ext_ack *extack) 2958 { 2959 struct mv88e6xxx_chip *chip = ds->priv; 2960 int err; 2961 2962 if (tree_index != ds->dst->index) 2963 return 0; 2964 2965 mv88e6xxx_reg_lock(chip); 2966 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2967 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2968 mv88e6xxx_reg_unlock(chip); 2969 2970 return err; 2971 } 2972 2973 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2974 int tree_index, int sw_index, 2975 int port, struct dsa_bridge bridge) 2976 { 2977 struct mv88e6xxx_chip *chip = ds->priv; 2978 2979 if (tree_index != ds->dst->index) 2980 return; 2981 2982 mv88e6xxx_reg_lock(chip); 2983 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2984 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2985 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2986 mv88e6xxx_reg_unlock(chip); 2987 } 2988 2989 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2990 { 2991 if (chip->info->ops->reset) 2992 return chip->info->ops->reset(chip); 2993 2994 return 0; 2995 } 2996 2997 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2998 { 2999 struct gpio_desc *gpiod = chip->reset; 3000 3001 /* If there is a GPIO connected to the reset pin, toggle it */ 3002 if (gpiod) { 3003 gpiod_set_value_cansleep(gpiod, 1); 3004 usleep_range(10000, 20000); 3005 gpiod_set_value_cansleep(gpiod, 0); 3006 usleep_range(10000, 20000); 3007 3008 mv88e6xxx_g1_wait_eeprom_done(chip); 3009 } 3010 } 3011 3012 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3013 { 3014 int i, err; 3015 3016 /* Set all ports to the Disabled state */ 3017 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3018 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3019 if (err) 3020 return err; 3021 } 3022 3023 /* Wait for transmit queues to drain, 3024 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3025 */ 3026 usleep_range(2000, 4000); 3027 3028 return 0; 3029 } 3030 3031 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3032 { 3033 int err; 3034 3035 err = mv88e6xxx_disable_ports(chip); 3036 if (err) 3037 return err; 3038 3039 mv88e6xxx_hardware_reset(chip); 3040 3041 return mv88e6xxx_software_reset(chip); 3042 } 3043 3044 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3045 enum mv88e6xxx_frame_mode frame, 3046 enum mv88e6xxx_egress_mode egress, u16 etype) 3047 { 3048 int err; 3049 3050 if (!chip->info->ops->port_set_frame_mode) 3051 return -EOPNOTSUPP; 3052 3053 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3054 if (err) 3055 return err; 3056 3057 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3058 if (err) 3059 return err; 3060 3061 if (chip->info->ops->port_set_ether_type) 3062 return chip->info->ops->port_set_ether_type(chip, port, etype); 3063 3064 return 0; 3065 } 3066 3067 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3068 { 3069 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3070 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3071 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3072 } 3073 3074 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3075 { 3076 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3077 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3078 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3079 } 3080 3081 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3082 { 3083 return mv88e6xxx_set_port_mode(chip, port, 3084 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3085 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3086 ETH_P_EDSA); 3087 } 3088 3089 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3090 { 3091 if (dsa_is_dsa_port(chip->ds, port)) 3092 return mv88e6xxx_set_port_mode_dsa(chip, port); 3093 3094 if (dsa_is_user_port(chip->ds, port)) 3095 return mv88e6xxx_set_port_mode_normal(chip, port); 3096 3097 /* Setup CPU port mode depending on its supported tag format */ 3098 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3099 return mv88e6xxx_set_port_mode_dsa(chip, port); 3100 3101 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3102 return mv88e6xxx_set_port_mode_edsa(chip, port); 3103 3104 return -EINVAL; 3105 } 3106 3107 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3108 { 3109 bool message = dsa_is_dsa_port(chip->ds, port); 3110 3111 return mv88e6xxx_port_set_message_port(chip, port, message); 3112 } 3113 3114 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3115 { 3116 int err; 3117 3118 if (chip->info->ops->port_set_ucast_flood) { 3119 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3120 if (err) 3121 return err; 3122 } 3123 if (chip->info->ops->port_set_mcast_flood) { 3124 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3125 if (err) 3126 return err; 3127 } 3128 3129 return 0; 3130 } 3131 3132 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3133 { 3134 struct mv88e6xxx_port *mvp = dev_id; 3135 struct mv88e6xxx_chip *chip = mvp->chip; 3136 irqreturn_t ret = IRQ_NONE; 3137 int port = mvp->port; 3138 int lane; 3139 3140 mv88e6xxx_reg_lock(chip); 3141 lane = mv88e6xxx_serdes_get_lane(chip, port); 3142 if (lane >= 0) 3143 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3144 mv88e6xxx_reg_unlock(chip); 3145 3146 return ret; 3147 } 3148 3149 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3150 int lane) 3151 { 3152 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3153 unsigned int irq; 3154 int err; 3155 3156 /* Nothing to request if this SERDES port has no IRQ */ 3157 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3158 if (!irq) 3159 return 0; 3160 3161 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3162 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3163 3164 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3165 mv88e6xxx_reg_unlock(chip); 3166 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3167 IRQF_ONESHOT, dev_id->serdes_irq_name, 3168 dev_id); 3169 mv88e6xxx_reg_lock(chip); 3170 if (err) 3171 return err; 3172 3173 dev_id->serdes_irq = irq; 3174 3175 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3176 } 3177 3178 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3179 int lane) 3180 { 3181 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3182 unsigned int irq = dev_id->serdes_irq; 3183 int err; 3184 3185 /* Nothing to free if no IRQ has been requested */ 3186 if (!irq) 3187 return 0; 3188 3189 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3190 3191 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3192 mv88e6xxx_reg_unlock(chip); 3193 free_irq(irq, dev_id); 3194 mv88e6xxx_reg_lock(chip); 3195 3196 dev_id->serdes_irq = 0; 3197 3198 return err; 3199 } 3200 3201 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3202 bool on) 3203 { 3204 int lane; 3205 int err; 3206 3207 lane = mv88e6xxx_serdes_get_lane(chip, port); 3208 if (lane < 0) 3209 return 0; 3210 3211 if (on) { 3212 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3213 if (err) 3214 return err; 3215 3216 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3217 } else { 3218 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3219 if (err) 3220 return err; 3221 3222 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3223 } 3224 3225 return err; 3226 } 3227 3228 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3229 enum mv88e6xxx_egress_direction direction, 3230 int port) 3231 { 3232 int err; 3233 3234 if (!chip->info->ops->set_egress_port) 3235 return -EOPNOTSUPP; 3236 3237 err = chip->info->ops->set_egress_port(chip, direction, port); 3238 if (err) 3239 return err; 3240 3241 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3242 chip->ingress_dest_port = port; 3243 else 3244 chip->egress_dest_port = port; 3245 3246 return 0; 3247 } 3248 3249 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3250 { 3251 struct dsa_switch *ds = chip->ds; 3252 int upstream_port; 3253 int err; 3254 3255 upstream_port = dsa_upstream_port(ds, port); 3256 if (chip->info->ops->port_set_upstream_port) { 3257 err = chip->info->ops->port_set_upstream_port(chip, port, 3258 upstream_port); 3259 if (err) 3260 return err; 3261 } 3262 3263 if (port == upstream_port) { 3264 if (chip->info->ops->set_cpu_port) { 3265 err = chip->info->ops->set_cpu_port(chip, 3266 upstream_port); 3267 if (err) 3268 return err; 3269 } 3270 3271 err = mv88e6xxx_set_egress_port(chip, 3272 MV88E6XXX_EGRESS_DIR_INGRESS, 3273 upstream_port); 3274 if (err && err != -EOPNOTSUPP) 3275 return err; 3276 3277 err = mv88e6xxx_set_egress_port(chip, 3278 MV88E6XXX_EGRESS_DIR_EGRESS, 3279 upstream_port); 3280 if (err && err != -EOPNOTSUPP) 3281 return err; 3282 } 3283 3284 return 0; 3285 } 3286 3287 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3288 { 3289 struct device_node *phy_handle = NULL; 3290 struct dsa_switch *ds = chip->ds; 3291 phy_interface_t mode; 3292 struct dsa_port *dp; 3293 int tx_amp, speed; 3294 int err; 3295 u16 reg; 3296 3297 chip->ports[port].chip = chip; 3298 chip->ports[port].port = port; 3299 3300 dp = dsa_to_port(ds, port); 3301 3302 /* MAC Forcing register: don't force link, speed, duplex or flow control 3303 * state to any particular values on physical ports, but force the CPU 3304 * port and all DSA ports to their maximum bandwidth and full duplex. 3305 */ 3306 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3307 struct phylink_config pl_config = {}; 3308 unsigned long caps; 3309 3310 mv88e6xxx_get_caps(ds, port, &pl_config); 3311 3312 caps = pl_config.mac_capabilities; 3313 3314 if (chip->info->ops->port_max_speed_mode) 3315 mode = chip->info->ops->port_max_speed_mode(port); 3316 else 3317 mode = PHY_INTERFACE_MODE_NA; 3318 3319 if (caps & MAC_10000FD) 3320 speed = SPEED_10000; 3321 else if (caps & MAC_5000FD) 3322 speed = SPEED_5000; 3323 else if (caps & MAC_2500FD) 3324 speed = SPEED_2500; 3325 else if (caps & MAC_1000) 3326 speed = SPEED_1000; 3327 else if (caps & MAC_100) 3328 speed = SPEED_100; 3329 else 3330 speed = SPEED_10; 3331 3332 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3333 speed, DUPLEX_FULL, 3334 PAUSE_OFF, mode); 3335 } else { 3336 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3337 SPEED_UNFORCED, DUPLEX_UNFORCED, 3338 PAUSE_ON, 3339 PHY_INTERFACE_MODE_NA); 3340 } 3341 if (err) 3342 return err; 3343 3344 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3345 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3346 * tunneling, determine priority by looking at 802.1p and IP 3347 * priority fields (IP prio has precedence), and set STP state 3348 * to Forwarding. 3349 * 3350 * If this is the CPU link, use DSA or EDSA tagging depending 3351 * on which tagging mode was configured. 3352 * 3353 * If this is a link to another switch, use DSA tagging mode. 3354 * 3355 * If this is the upstream port for this switch, enable 3356 * forwarding of unknown unicasts and multicasts. 3357 */ 3358 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 3359 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3360 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3361 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3362 if (err) 3363 return err; 3364 3365 err = mv88e6xxx_setup_port_mode(chip, port); 3366 if (err) 3367 return err; 3368 3369 err = mv88e6xxx_setup_egress_floods(chip, port); 3370 if (err) 3371 return err; 3372 3373 /* Port Control 2: don't force a good FCS, set the MTU size to 3374 * 10222 bytes, disable 802.1q tags checking, don't discard 3375 * tagged or untagged frames on this port, skip destination 3376 * address lookup on user ports, disable ARP mirroring and don't 3377 * send a copy of all transmitted/received frames on this port 3378 * to the CPU. 3379 */ 3380 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3381 if (err) 3382 return err; 3383 3384 err = mv88e6xxx_setup_upstream_port(chip, port); 3385 if (err) 3386 return err; 3387 3388 /* On chips that support it, set all downstream DSA ports' 3389 * VLAN policy to TRAP. In combination with loading 3390 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3391 * provides a better isolation barrier between standalone 3392 * ports, as the ATU is bypassed on any intermediate switches 3393 * between the incoming port and the CPU. 3394 */ 3395 if (dsa_is_downstream_port(ds, port) && 3396 chip->info->ops->port_set_policy) { 3397 err = chip->info->ops->port_set_policy(chip, port, 3398 MV88E6XXX_POLICY_MAPPING_VTU, 3399 MV88E6XXX_POLICY_ACTION_TRAP); 3400 if (err) 3401 return err; 3402 } 3403 3404 /* User ports start out in standalone mode and 802.1Q is 3405 * therefore disabled. On DSA ports, all valid VIDs are always 3406 * loaded in the VTU - therefore, enable 802.1Q in order to take 3407 * advantage of VLAN policy on chips that supports it. 3408 */ 3409 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3410 dsa_is_user_port(ds, port) ? 3411 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3412 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3413 if (err) 3414 return err; 3415 3416 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3417 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3418 * the first free FID. This will be used as the private PVID for 3419 * unbridged ports. Shared (DSA and CPU) ports must also be 3420 * members of this VID, in order to trap all frames assigned to 3421 * it to the CPU. 3422 */ 3423 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3424 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3425 false); 3426 if (err) 3427 return err; 3428 3429 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3430 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3431 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3432 * as the private PVID on ports under a VLAN-unaware bridge. 3433 * Shared (DSA and CPU) ports must also be members of it, to translate 3434 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3435 * relying on their port default FID. 3436 */ 3437 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3438 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3439 false); 3440 if (err) 3441 return err; 3442 3443 if (chip->info->ops->port_set_jumbo_size) { 3444 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3445 if (err) 3446 return err; 3447 } 3448 3449 /* Port Association Vector: disable automatic address learning 3450 * on all user ports since they start out in standalone 3451 * mode. When joining a bridge, learning will be configured to 3452 * match the bridge port settings. Enable learning on all 3453 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3454 * learning process. 3455 * 3456 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3457 * and RefreshLocked. I.e. setup standard automatic learning. 3458 */ 3459 if (dsa_is_user_port(ds, port)) 3460 reg = 0; 3461 else 3462 reg = 1 << port; 3463 3464 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3465 reg); 3466 if (err) 3467 return err; 3468 3469 /* Egress rate control 2: disable egress rate control. */ 3470 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3471 0x0000); 3472 if (err) 3473 return err; 3474 3475 if (chip->info->ops->port_pause_limit) { 3476 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3477 if (err) 3478 return err; 3479 } 3480 3481 if (chip->info->ops->port_disable_learn_limit) { 3482 err = chip->info->ops->port_disable_learn_limit(chip, port); 3483 if (err) 3484 return err; 3485 } 3486 3487 if (chip->info->ops->port_disable_pri_override) { 3488 err = chip->info->ops->port_disable_pri_override(chip, port); 3489 if (err) 3490 return err; 3491 } 3492 3493 if (chip->info->ops->port_tag_remap) { 3494 err = chip->info->ops->port_tag_remap(chip, port); 3495 if (err) 3496 return err; 3497 } 3498 3499 if (chip->info->ops->port_egress_rate_limiting) { 3500 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3501 if (err) 3502 return err; 3503 } 3504 3505 if (chip->info->ops->port_setup_message_port) { 3506 err = chip->info->ops->port_setup_message_port(chip, port); 3507 if (err) 3508 return err; 3509 } 3510 3511 if (chip->info->ops->serdes_set_tx_amplitude) { 3512 if (dp) 3513 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3514 3515 if (phy_handle && !of_property_read_u32(phy_handle, 3516 "tx-p2p-microvolt", 3517 &tx_amp)) 3518 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3519 port, tx_amp); 3520 if (phy_handle) { 3521 of_node_put(phy_handle); 3522 if (err) 3523 return err; 3524 } 3525 } 3526 3527 /* Port based VLAN map: give each port the same default address 3528 * database, and allow bidirectional communication between the 3529 * CPU and DSA port(s), and the other ports. 3530 */ 3531 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3532 if (err) 3533 return err; 3534 3535 err = mv88e6xxx_port_vlan_map(chip, port); 3536 if (err) 3537 return err; 3538 3539 /* Default VLAN ID and priority: don't set a default VLAN 3540 * ID, and set the default packet priority to zero. 3541 */ 3542 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3543 } 3544 3545 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3546 { 3547 struct mv88e6xxx_chip *chip = ds->priv; 3548 3549 if (chip->info->ops->port_set_jumbo_size) 3550 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3551 else if (chip->info->ops->set_max_frame_size) 3552 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3553 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3554 } 3555 3556 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3557 { 3558 struct mv88e6xxx_chip *chip = ds->priv; 3559 int ret = 0; 3560 3561 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3562 new_mtu += EDSA_HLEN; 3563 3564 mv88e6xxx_reg_lock(chip); 3565 if (chip->info->ops->port_set_jumbo_size) 3566 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3567 else if (chip->info->ops->set_max_frame_size) 3568 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3569 else 3570 if (new_mtu > 1522) 3571 ret = -EINVAL; 3572 mv88e6xxx_reg_unlock(chip); 3573 3574 return ret; 3575 } 3576 3577 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3578 struct phy_device *phydev) 3579 { 3580 struct mv88e6xxx_chip *chip = ds->priv; 3581 int err; 3582 3583 mv88e6xxx_reg_lock(chip); 3584 err = mv88e6xxx_serdes_power(chip, port, true); 3585 mv88e6xxx_reg_unlock(chip); 3586 3587 return err; 3588 } 3589 3590 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3591 { 3592 struct mv88e6xxx_chip *chip = ds->priv; 3593 3594 mv88e6xxx_reg_lock(chip); 3595 if (mv88e6xxx_serdes_power(chip, port, false)) 3596 dev_err(chip->dev, "failed to power off SERDES\n"); 3597 mv88e6xxx_reg_unlock(chip); 3598 } 3599 3600 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3601 unsigned int ageing_time) 3602 { 3603 struct mv88e6xxx_chip *chip = ds->priv; 3604 int err; 3605 3606 mv88e6xxx_reg_lock(chip); 3607 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3608 mv88e6xxx_reg_unlock(chip); 3609 3610 return err; 3611 } 3612 3613 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3614 { 3615 int err; 3616 3617 /* Initialize the statistics unit */ 3618 if (chip->info->ops->stats_set_histogram) { 3619 err = chip->info->ops->stats_set_histogram(chip); 3620 if (err) 3621 return err; 3622 } 3623 3624 return mv88e6xxx_g1_stats_clear(chip); 3625 } 3626 3627 /* Check if the errata has already been applied. */ 3628 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3629 { 3630 int port; 3631 int err; 3632 u16 val; 3633 3634 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3635 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3636 if (err) { 3637 dev_err(chip->dev, 3638 "Error reading hidden register: %d\n", err); 3639 return false; 3640 } 3641 if (val != 0x01c0) 3642 return false; 3643 } 3644 3645 return true; 3646 } 3647 3648 /* The 6390 copper ports have an errata which require poking magic 3649 * values into undocumented hidden registers and then performing a 3650 * software reset. 3651 */ 3652 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3653 { 3654 int port; 3655 int err; 3656 3657 if (mv88e6390_setup_errata_applied(chip)) 3658 return 0; 3659 3660 /* Set the ports into blocking mode */ 3661 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3662 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3663 if (err) 3664 return err; 3665 } 3666 3667 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3668 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3669 if (err) 3670 return err; 3671 } 3672 3673 return mv88e6xxx_software_reset(chip); 3674 } 3675 3676 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3677 { 3678 mv88e6xxx_teardown_devlink_params(ds); 3679 dsa_devlink_resources_unregister(ds); 3680 mv88e6xxx_teardown_devlink_regions_global(ds); 3681 } 3682 3683 static int mv88e6xxx_setup(struct dsa_switch *ds) 3684 { 3685 struct mv88e6xxx_chip *chip = ds->priv; 3686 u8 cmode; 3687 int err; 3688 int i; 3689 3690 chip->ds = ds; 3691 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3692 3693 /* Since virtual bridges are mapped in the PVT, the number we support 3694 * depends on the physical switch topology. We need to let DSA figure 3695 * that out and therefore we cannot set this at dsa_register_switch() 3696 * time. 3697 */ 3698 if (mv88e6xxx_has_pvt(chip)) 3699 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3700 ds->dst->last_switch - 1; 3701 3702 mv88e6xxx_reg_lock(chip); 3703 3704 if (chip->info->ops->setup_errata) { 3705 err = chip->info->ops->setup_errata(chip); 3706 if (err) 3707 goto unlock; 3708 } 3709 3710 /* Cache the cmode of each port. */ 3711 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3712 if (chip->info->ops->port_get_cmode) { 3713 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3714 if (err) 3715 goto unlock; 3716 3717 chip->ports[i].cmode = cmode; 3718 } 3719 } 3720 3721 err = mv88e6xxx_vtu_setup(chip); 3722 if (err) 3723 goto unlock; 3724 3725 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3726 * VTU, thereby also flushing the STU). 3727 */ 3728 err = mv88e6xxx_stu_setup(chip); 3729 if (err) 3730 goto unlock; 3731 3732 /* Setup Switch Port Registers */ 3733 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3734 if (dsa_is_unused_port(ds, i)) 3735 continue; 3736 3737 /* Prevent the use of an invalid port. */ 3738 if (mv88e6xxx_is_invalid_port(chip, i)) { 3739 dev_err(chip->dev, "port %d is invalid\n", i); 3740 err = -EINVAL; 3741 goto unlock; 3742 } 3743 3744 err = mv88e6xxx_setup_port(chip, i); 3745 if (err) 3746 goto unlock; 3747 } 3748 3749 err = mv88e6xxx_irl_setup(chip); 3750 if (err) 3751 goto unlock; 3752 3753 err = mv88e6xxx_mac_setup(chip); 3754 if (err) 3755 goto unlock; 3756 3757 err = mv88e6xxx_phy_setup(chip); 3758 if (err) 3759 goto unlock; 3760 3761 err = mv88e6xxx_pvt_setup(chip); 3762 if (err) 3763 goto unlock; 3764 3765 err = mv88e6xxx_atu_setup(chip); 3766 if (err) 3767 goto unlock; 3768 3769 err = mv88e6xxx_broadcast_setup(chip, 0); 3770 if (err) 3771 goto unlock; 3772 3773 err = mv88e6xxx_pot_setup(chip); 3774 if (err) 3775 goto unlock; 3776 3777 err = mv88e6xxx_rmu_setup(chip); 3778 if (err) 3779 goto unlock; 3780 3781 err = mv88e6xxx_rsvd2cpu_setup(chip); 3782 if (err) 3783 goto unlock; 3784 3785 err = mv88e6xxx_trunk_setup(chip); 3786 if (err) 3787 goto unlock; 3788 3789 err = mv88e6xxx_devmap_setup(chip); 3790 if (err) 3791 goto unlock; 3792 3793 err = mv88e6xxx_pri_setup(chip); 3794 if (err) 3795 goto unlock; 3796 3797 /* Setup PTP Hardware Clock and timestamping */ 3798 if (chip->info->ptp_support) { 3799 err = mv88e6xxx_ptp_setup(chip); 3800 if (err) 3801 goto unlock; 3802 3803 err = mv88e6xxx_hwtstamp_setup(chip); 3804 if (err) 3805 goto unlock; 3806 } 3807 3808 err = mv88e6xxx_stats_setup(chip); 3809 if (err) 3810 goto unlock; 3811 3812 unlock: 3813 mv88e6xxx_reg_unlock(chip); 3814 3815 if (err) 3816 return err; 3817 3818 /* Have to be called without holding the register lock, since 3819 * they take the devlink lock, and we later take the locks in 3820 * the reverse order when getting/setting parameters or 3821 * resource occupancy. 3822 */ 3823 err = mv88e6xxx_setup_devlink_resources(ds); 3824 if (err) 3825 return err; 3826 3827 err = mv88e6xxx_setup_devlink_params(ds); 3828 if (err) 3829 goto out_resources; 3830 3831 err = mv88e6xxx_setup_devlink_regions_global(ds); 3832 if (err) 3833 goto out_params; 3834 3835 return 0; 3836 3837 out_params: 3838 mv88e6xxx_teardown_devlink_params(ds); 3839 out_resources: 3840 dsa_devlink_resources_unregister(ds); 3841 3842 return err; 3843 } 3844 3845 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3846 { 3847 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3848 } 3849 3850 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3851 { 3852 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3853 } 3854 3855 /* prod_id for switch families which do not have a PHY model number */ 3856 static const u16 family_prod_id_table[] = { 3857 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3858 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3859 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3860 }; 3861 3862 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3863 { 3864 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3865 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3866 u16 prod_id; 3867 u16 val; 3868 int err; 3869 3870 if (!chip->info->ops->phy_read) 3871 return -EOPNOTSUPP; 3872 3873 mv88e6xxx_reg_lock(chip); 3874 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3875 mv88e6xxx_reg_unlock(chip); 3876 3877 /* Some internal PHYs don't have a model number. */ 3878 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3879 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3880 prod_id = family_prod_id_table[chip->info->family]; 3881 if (prod_id) 3882 val |= prod_id >> 4; 3883 } 3884 3885 return err ? err : val; 3886 } 3887 3888 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3889 { 3890 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3891 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3892 int err; 3893 3894 if (!chip->info->ops->phy_write) 3895 return -EOPNOTSUPP; 3896 3897 mv88e6xxx_reg_lock(chip); 3898 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3899 mv88e6xxx_reg_unlock(chip); 3900 3901 return err; 3902 } 3903 3904 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3905 struct device_node *np, 3906 bool external) 3907 { 3908 static int index; 3909 struct mv88e6xxx_mdio_bus *mdio_bus; 3910 struct mii_bus *bus; 3911 int err; 3912 3913 if (external) { 3914 mv88e6xxx_reg_lock(chip); 3915 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3916 mv88e6xxx_reg_unlock(chip); 3917 3918 if (err) 3919 return err; 3920 } 3921 3922 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3923 if (!bus) 3924 return -ENOMEM; 3925 3926 mdio_bus = bus->priv; 3927 mdio_bus->bus = bus; 3928 mdio_bus->chip = chip; 3929 INIT_LIST_HEAD(&mdio_bus->list); 3930 mdio_bus->external = external; 3931 3932 if (np) { 3933 bus->name = np->full_name; 3934 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3935 } else { 3936 bus->name = "mv88e6xxx SMI"; 3937 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3938 } 3939 3940 bus->read = mv88e6xxx_mdio_read; 3941 bus->write = mv88e6xxx_mdio_write; 3942 bus->parent = chip->dev; 3943 3944 if (!external) { 3945 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3946 if (err) 3947 goto out; 3948 } 3949 3950 err = of_mdiobus_register(bus, np); 3951 if (err) { 3952 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3953 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3954 goto out; 3955 } 3956 3957 if (external) 3958 list_add_tail(&mdio_bus->list, &chip->mdios); 3959 else 3960 list_add(&mdio_bus->list, &chip->mdios); 3961 3962 return 0; 3963 3964 out: 3965 mdiobus_free(bus); 3966 return err; 3967 } 3968 3969 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3970 3971 { 3972 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3973 struct mii_bus *bus; 3974 3975 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3976 bus = mdio_bus->bus; 3977 3978 if (!mdio_bus->external) 3979 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3980 3981 mdiobus_unregister(bus); 3982 mdiobus_free(bus); 3983 } 3984 } 3985 3986 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3987 struct device_node *np) 3988 { 3989 struct device_node *child; 3990 int err; 3991 3992 /* Always register one mdio bus for the internal/default mdio 3993 * bus. This maybe represented in the device tree, but is 3994 * optional. 3995 */ 3996 child = of_get_child_by_name(np, "mdio"); 3997 err = mv88e6xxx_mdio_register(chip, child, false); 3998 of_node_put(child); 3999 if (err) 4000 return err; 4001 4002 /* Walk the device tree, and see if there are any other nodes 4003 * which say they are compatible with the external mdio 4004 * bus. 4005 */ 4006 for_each_available_child_of_node(np, child) { 4007 if (of_device_is_compatible( 4008 child, "marvell,mv88e6xxx-mdio-external")) { 4009 err = mv88e6xxx_mdio_register(chip, child, true); 4010 if (err) { 4011 mv88e6xxx_mdios_unregister(chip); 4012 of_node_put(child); 4013 return err; 4014 } 4015 } 4016 } 4017 4018 return 0; 4019 } 4020 4021 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4022 { 4023 struct mv88e6xxx_chip *chip = ds->priv; 4024 4025 return chip->eeprom_len; 4026 } 4027 4028 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4029 struct ethtool_eeprom *eeprom, u8 *data) 4030 { 4031 struct mv88e6xxx_chip *chip = ds->priv; 4032 int err; 4033 4034 if (!chip->info->ops->get_eeprom) 4035 return -EOPNOTSUPP; 4036 4037 mv88e6xxx_reg_lock(chip); 4038 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4039 mv88e6xxx_reg_unlock(chip); 4040 4041 if (err) 4042 return err; 4043 4044 eeprom->magic = 0xc3ec4951; 4045 4046 return 0; 4047 } 4048 4049 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4050 struct ethtool_eeprom *eeprom, u8 *data) 4051 { 4052 struct mv88e6xxx_chip *chip = ds->priv; 4053 int err; 4054 4055 if (!chip->info->ops->set_eeprom) 4056 return -EOPNOTSUPP; 4057 4058 if (eeprom->magic != 0xc3ec4951) 4059 return -EINVAL; 4060 4061 mv88e6xxx_reg_lock(chip); 4062 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4063 mv88e6xxx_reg_unlock(chip); 4064 4065 return err; 4066 } 4067 4068 static const struct mv88e6xxx_ops mv88e6085_ops = { 4069 /* MV88E6XXX_FAMILY_6097 */ 4070 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4071 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4072 .irl_init_all = mv88e6352_g2_irl_init_all, 4073 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4074 .phy_read = mv88e6185_phy_ppu_read, 4075 .phy_write = mv88e6185_phy_ppu_write, 4076 .port_set_link = mv88e6xxx_port_set_link, 4077 .port_sync_link = mv88e6xxx_port_sync_link, 4078 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4079 .port_tag_remap = mv88e6095_port_tag_remap, 4080 .port_set_policy = mv88e6352_port_set_policy, 4081 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4082 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4083 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4084 .port_set_ether_type = mv88e6351_port_set_ether_type, 4085 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4086 .port_pause_limit = mv88e6097_port_pause_limit, 4087 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4088 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4089 .port_get_cmode = mv88e6185_port_get_cmode, 4090 .port_setup_message_port = mv88e6xxx_setup_message_port, 4091 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4092 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4093 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4094 .stats_get_strings = mv88e6095_stats_get_strings, 4095 .stats_get_stats = mv88e6095_stats_get_stats, 4096 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4097 .set_egress_port = mv88e6095_g1_set_egress_port, 4098 .watchdog_ops = &mv88e6097_watchdog_ops, 4099 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4100 .pot_clear = mv88e6xxx_g2_pot_clear, 4101 .ppu_enable = mv88e6185_g1_ppu_enable, 4102 .ppu_disable = mv88e6185_g1_ppu_disable, 4103 .reset = mv88e6185_g1_reset, 4104 .rmu_disable = mv88e6085_g1_rmu_disable, 4105 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4106 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4107 .stu_getnext = mv88e6352_g1_stu_getnext, 4108 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4109 .phylink_get_caps = mv88e6185_phylink_get_caps, 4110 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4111 }; 4112 4113 static const struct mv88e6xxx_ops mv88e6095_ops = { 4114 /* MV88E6XXX_FAMILY_6095 */ 4115 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4116 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4117 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4118 .phy_read = mv88e6185_phy_ppu_read, 4119 .phy_write = mv88e6185_phy_ppu_write, 4120 .port_set_link = mv88e6xxx_port_set_link, 4121 .port_sync_link = mv88e6185_port_sync_link, 4122 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4123 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4124 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4125 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4126 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4127 .port_get_cmode = mv88e6185_port_get_cmode, 4128 .port_setup_message_port = mv88e6xxx_setup_message_port, 4129 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4130 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4131 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4132 .stats_get_strings = mv88e6095_stats_get_strings, 4133 .stats_get_stats = mv88e6095_stats_get_stats, 4134 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4135 .serdes_power = mv88e6185_serdes_power, 4136 .serdes_get_lane = mv88e6185_serdes_get_lane, 4137 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4138 .ppu_enable = mv88e6185_g1_ppu_enable, 4139 .ppu_disable = mv88e6185_g1_ppu_disable, 4140 .reset = mv88e6185_g1_reset, 4141 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4142 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4143 .phylink_get_caps = mv88e6095_phylink_get_caps, 4144 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4145 }; 4146 4147 static const struct mv88e6xxx_ops mv88e6097_ops = { 4148 /* MV88E6XXX_FAMILY_6097 */ 4149 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4150 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4151 .irl_init_all = mv88e6352_g2_irl_init_all, 4152 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4153 .phy_read = mv88e6xxx_g2_smi_phy_read, 4154 .phy_write = mv88e6xxx_g2_smi_phy_write, 4155 .port_set_link = mv88e6xxx_port_set_link, 4156 .port_sync_link = mv88e6185_port_sync_link, 4157 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4158 .port_tag_remap = mv88e6095_port_tag_remap, 4159 .port_set_policy = mv88e6352_port_set_policy, 4160 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4161 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4162 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4163 .port_set_ether_type = mv88e6351_port_set_ether_type, 4164 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4165 .port_pause_limit = mv88e6097_port_pause_limit, 4166 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4167 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4168 .port_get_cmode = mv88e6185_port_get_cmode, 4169 .port_setup_message_port = mv88e6xxx_setup_message_port, 4170 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4171 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4172 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4173 .stats_get_strings = mv88e6095_stats_get_strings, 4174 .stats_get_stats = mv88e6095_stats_get_stats, 4175 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4176 .set_egress_port = mv88e6095_g1_set_egress_port, 4177 .watchdog_ops = &mv88e6097_watchdog_ops, 4178 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4179 .serdes_power = mv88e6185_serdes_power, 4180 .serdes_get_lane = mv88e6185_serdes_get_lane, 4181 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4182 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4183 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4184 .serdes_irq_status = mv88e6097_serdes_irq_status, 4185 .pot_clear = mv88e6xxx_g2_pot_clear, 4186 .reset = mv88e6352_g1_reset, 4187 .rmu_disable = mv88e6085_g1_rmu_disable, 4188 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4189 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4190 .phylink_get_caps = mv88e6095_phylink_get_caps, 4191 .stu_getnext = mv88e6352_g1_stu_getnext, 4192 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4193 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4194 }; 4195 4196 static const struct mv88e6xxx_ops mv88e6123_ops = { 4197 /* MV88E6XXX_FAMILY_6165 */ 4198 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4199 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4200 .irl_init_all = mv88e6352_g2_irl_init_all, 4201 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4202 .phy_read = mv88e6xxx_g2_smi_phy_read, 4203 .phy_write = mv88e6xxx_g2_smi_phy_write, 4204 .port_set_link = mv88e6xxx_port_set_link, 4205 .port_sync_link = mv88e6xxx_port_sync_link, 4206 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4207 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4208 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4209 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4210 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4211 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4212 .port_get_cmode = mv88e6185_port_get_cmode, 4213 .port_setup_message_port = mv88e6xxx_setup_message_port, 4214 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4215 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4216 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4217 .stats_get_strings = mv88e6095_stats_get_strings, 4218 .stats_get_stats = mv88e6095_stats_get_stats, 4219 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4220 .set_egress_port = mv88e6095_g1_set_egress_port, 4221 .watchdog_ops = &mv88e6097_watchdog_ops, 4222 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4223 .pot_clear = mv88e6xxx_g2_pot_clear, 4224 .reset = mv88e6352_g1_reset, 4225 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4226 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4227 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4228 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4229 .stu_getnext = mv88e6352_g1_stu_getnext, 4230 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4231 .phylink_get_caps = mv88e6185_phylink_get_caps, 4232 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4233 }; 4234 4235 static const struct mv88e6xxx_ops mv88e6131_ops = { 4236 /* MV88E6XXX_FAMILY_6185 */ 4237 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4238 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4239 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4240 .phy_read = mv88e6185_phy_ppu_read, 4241 .phy_write = mv88e6185_phy_ppu_write, 4242 .port_set_link = mv88e6xxx_port_set_link, 4243 .port_sync_link = mv88e6xxx_port_sync_link, 4244 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4245 .port_tag_remap = mv88e6095_port_tag_remap, 4246 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4247 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4248 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4249 .port_set_ether_type = mv88e6351_port_set_ether_type, 4250 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4251 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4252 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4253 .port_pause_limit = mv88e6097_port_pause_limit, 4254 .port_set_pause = mv88e6185_port_set_pause, 4255 .port_get_cmode = mv88e6185_port_get_cmode, 4256 .port_setup_message_port = mv88e6xxx_setup_message_port, 4257 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4258 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4259 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4260 .stats_get_strings = mv88e6095_stats_get_strings, 4261 .stats_get_stats = mv88e6095_stats_get_stats, 4262 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4263 .set_egress_port = mv88e6095_g1_set_egress_port, 4264 .watchdog_ops = &mv88e6097_watchdog_ops, 4265 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4266 .ppu_enable = mv88e6185_g1_ppu_enable, 4267 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4268 .ppu_disable = mv88e6185_g1_ppu_disable, 4269 .reset = mv88e6185_g1_reset, 4270 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4271 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4272 .phylink_get_caps = mv88e6185_phylink_get_caps, 4273 }; 4274 4275 static const struct mv88e6xxx_ops mv88e6141_ops = { 4276 /* MV88E6XXX_FAMILY_6341 */ 4277 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4278 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4279 .irl_init_all = mv88e6352_g2_irl_init_all, 4280 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4281 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4283 .phy_read = mv88e6xxx_g2_smi_phy_read, 4284 .phy_write = mv88e6xxx_g2_smi_phy_write, 4285 .port_set_link = mv88e6xxx_port_set_link, 4286 .port_sync_link = mv88e6xxx_port_sync_link, 4287 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4288 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4289 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4290 .port_tag_remap = mv88e6095_port_tag_remap, 4291 .port_set_policy = mv88e6352_port_set_policy, 4292 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4293 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4294 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4295 .port_set_ether_type = mv88e6351_port_set_ether_type, 4296 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4297 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4298 .port_pause_limit = mv88e6097_port_pause_limit, 4299 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4300 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4301 .port_get_cmode = mv88e6352_port_get_cmode, 4302 .port_set_cmode = mv88e6341_port_set_cmode, 4303 .port_setup_message_port = mv88e6xxx_setup_message_port, 4304 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4305 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4306 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4307 .stats_get_strings = mv88e6320_stats_get_strings, 4308 .stats_get_stats = mv88e6390_stats_get_stats, 4309 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4310 .set_egress_port = mv88e6390_g1_set_egress_port, 4311 .watchdog_ops = &mv88e6390_watchdog_ops, 4312 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4313 .pot_clear = mv88e6xxx_g2_pot_clear, 4314 .reset = mv88e6352_g1_reset, 4315 .rmu_disable = mv88e6390_g1_rmu_disable, 4316 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4317 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4318 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4319 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4320 .stu_getnext = mv88e6352_g1_stu_getnext, 4321 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4322 .serdes_power = mv88e6390_serdes_power, 4323 .serdes_get_lane = mv88e6341_serdes_get_lane, 4324 /* Check status register pause & lpa register */ 4325 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4326 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4327 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4328 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4329 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4330 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4331 .serdes_irq_status = mv88e6390_serdes_irq_status, 4332 .gpio_ops = &mv88e6352_gpio_ops, 4333 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4334 .serdes_get_strings = mv88e6390_serdes_get_strings, 4335 .serdes_get_stats = mv88e6390_serdes_get_stats, 4336 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4337 .serdes_get_regs = mv88e6390_serdes_get_regs, 4338 .phylink_get_caps = mv88e6341_phylink_get_caps, 4339 }; 4340 4341 static const struct mv88e6xxx_ops mv88e6161_ops = { 4342 /* MV88E6XXX_FAMILY_6165 */ 4343 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4344 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4345 .irl_init_all = mv88e6352_g2_irl_init_all, 4346 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4347 .phy_read = mv88e6xxx_g2_smi_phy_read, 4348 .phy_write = mv88e6xxx_g2_smi_phy_write, 4349 .port_set_link = mv88e6xxx_port_set_link, 4350 .port_sync_link = mv88e6xxx_port_sync_link, 4351 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4352 .port_tag_remap = mv88e6095_port_tag_remap, 4353 .port_set_policy = mv88e6352_port_set_policy, 4354 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4355 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4356 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4357 .port_set_ether_type = mv88e6351_port_set_ether_type, 4358 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4359 .port_pause_limit = mv88e6097_port_pause_limit, 4360 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4361 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4362 .port_get_cmode = mv88e6185_port_get_cmode, 4363 .port_setup_message_port = mv88e6xxx_setup_message_port, 4364 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4365 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4366 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4367 .stats_get_strings = mv88e6095_stats_get_strings, 4368 .stats_get_stats = mv88e6095_stats_get_stats, 4369 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4370 .set_egress_port = mv88e6095_g1_set_egress_port, 4371 .watchdog_ops = &mv88e6097_watchdog_ops, 4372 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4373 .pot_clear = mv88e6xxx_g2_pot_clear, 4374 .reset = mv88e6352_g1_reset, 4375 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4376 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4377 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4378 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4379 .stu_getnext = mv88e6352_g1_stu_getnext, 4380 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4381 .avb_ops = &mv88e6165_avb_ops, 4382 .ptp_ops = &mv88e6165_ptp_ops, 4383 .phylink_get_caps = mv88e6185_phylink_get_caps, 4384 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4385 }; 4386 4387 static const struct mv88e6xxx_ops mv88e6165_ops = { 4388 /* MV88E6XXX_FAMILY_6165 */ 4389 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4390 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4391 .irl_init_all = mv88e6352_g2_irl_init_all, 4392 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4393 .phy_read = mv88e6165_phy_read, 4394 .phy_write = mv88e6165_phy_write, 4395 .port_set_link = mv88e6xxx_port_set_link, 4396 .port_sync_link = mv88e6xxx_port_sync_link, 4397 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4400 .port_get_cmode = mv88e6185_port_get_cmode, 4401 .port_setup_message_port = mv88e6xxx_setup_message_port, 4402 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4403 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4404 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4405 .stats_get_strings = mv88e6095_stats_get_strings, 4406 .stats_get_stats = mv88e6095_stats_get_stats, 4407 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4408 .set_egress_port = mv88e6095_g1_set_egress_port, 4409 .watchdog_ops = &mv88e6097_watchdog_ops, 4410 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4411 .pot_clear = mv88e6xxx_g2_pot_clear, 4412 .reset = mv88e6352_g1_reset, 4413 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4414 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4415 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4416 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4417 .stu_getnext = mv88e6352_g1_stu_getnext, 4418 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4419 .avb_ops = &mv88e6165_avb_ops, 4420 .ptp_ops = &mv88e6165_ptp_ops, 4421 .phylink_get_caps = mv88e6185_phylink_get_caps, 4422 }; 4423 4424 static const struct mv88e6xxx_ops mv88e6171_ops = { 4425 /* MV88E6XXX_FAMILY_6351 */ 4426 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4427 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4428 .irl_init_all = mv88e6352_g2_irl_init_all, 4429 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4430 .phy_read = mv88e6xxx_g2_smi_phy_read, 4431 .phy_write = mv88e6xxx_g2_smi_phy_write, 4432 .port_set_link = mv88e6xxx_port_set_link, 4433 .port_sync_link = mv88e6xxx_port_sync_link, 4434 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4435 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4436 .port_tag_remap = mv88e6095_port_tag_remap, 4437 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4438 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4439 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4440 .port_set_ether_type = mv88e6351_port_set_ether_type, 4441 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4442 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4443 .port_pause_limit = mv88e6097_port_pause_limit, 4444 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4445 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4446 .port_get_cmode = mv88e6352_port_get_cmode, 4447 .port_setup_message_port = mv88e6xxx_setup_message_port, 4448 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4449 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4450 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4451 .stats_get_strings = mv88e6095_stats_get_strings, 4452 .stats_get_stats = mv88e6095_stats_get_stats, 4453 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4454 .set_egress_port = mv88e6095_g1_set_egress_port, 4455 .watchdog_ops = &mv88e6097_watchdog_ops, 4456 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4457 .pot_clear = mv88e6xxx_g2_pot_clear, 4458 .reset = mv88e6352_g1_reset, 4459 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4460 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4461 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4462 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4463 .stu_getnext = mv88e6352_g1_stu_getnext, 4464 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4465 .phylink_get_caps = mv88e6185_phylink_get_caps, 4466 }; 4467 4468 static const struct mv88e6xxx_ops mv88e6172_ops = { 4469 /* MV88E6XXX_FAMILY_6352 */ 4470 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4471 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4472 .irl_init_all = mv88e6352_g2_irl_init_all, 4473 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4474 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4475 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4476 .phy_read = mv88e6xxx_g2_smi_phy_read, 4477 .phy_write = mv88e6xxx_g2_smi_phy_write, 4478 .port_set_link = mv88e6xxx_port_set_link, 4479 .port_sync_link = mv88e6xxx_port_sync_link, 4480 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4481 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4482 .port_tag_remap = mv88e6095_port_tag_remap, 4483 .port_set_policy = mv88e6352_port_set_policy, 4484 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4485 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4486 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4487 .port_set_ether_type = mv88e6351_port_set_ether_type, 4488 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4489 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4490 .port_pause_limit = mv88e6097_port_pause_limit, 4491 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4492 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4493 .port_get_cmode = mv88e6352_port_get_cmode, 4494 .port_setup_message_port = mv88e6xxx_setup_message_port, 4495 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4496 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4497 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4498 .stats_get_strings = mv88e6095_stats_get_strings, 4499 .stats_get_stats = mv88e6095_stats_get_stats, 4500 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4501 .set_egress_port = mv88e6095_g1_set_egress_port, 4502 .watchdog_ops = &mv88e6097_watchdog_ops, 4503 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4504 .pot_clear = mv88e6xxx_g2_pot_clear, 4505 .reset = mv88e6352_g1_reset, 4506 .rmu_disable = mv88e6352_g1_rmu_disable, 4507 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4508 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4509 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4510 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4511 .stu_getnext = mv88e6352_g1_stu_getnext, 4512 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4513 .serdes_get_lane = mv88e6352_serdes_get_lane, 4514 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4515 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4516 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4517 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4518 .serdes_power = mv88e6352_serdes_power, 4519 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4520 .serdes_get_regs = mv88e6352_serdes_get_regs, 4521 .gpio_ops = &mv88e6352_gpio_ops, 4522 .phylink_get_caps = mv88e6352_phylink_get_caps, 4523 }; 4524 4525 static const struct mv88e6xxx_ops mv88e6175_ops = { 4526 /* MV88E6XXX_FAMILY_6351 */ 4527 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4528 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4529 .irl_init_all = mv88e6352_g2_irl_init_all, 4530 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4531 .phy_read = mv88e6xxx_g2_smi_phy_read, 4532 .phy_write = mv88e6xxx_g2_smi_phy_write, 4533 .port_set_link = mv88e6xxx_port_set_link, 4534 .port_sync_link = mv88e6xxx_port_sync_link, 4535 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4536 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4537 .port_tag_remap = mv88e6095_port_tag_remap, 4538 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4539 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4540 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4541 .port_set_ether_type = mv88e6351_port_set_ether_type, 4542 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4543 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4544 .port_pause_limit = mv88e6097_port_pause_limit, 4545 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4546 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4547 .port_get_cmode = mv88e6352_port_get_cmode, 4548 .port_setup_message_port = mv88e6xxx_setup_message_port, 4549 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4550 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4551 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4552 .stats_get_strings = mv88e6095_stats_get_strings, 4553 .stats_get_stats = mv88e6095_stats_get_stats, 4554 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4555 .set_egress_port = mv88e6095_g1_set_egress_port, 4556 .watchdog_ops = &mv88e6097_watchdog_ops, 4557 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4558 .pot_clear = mv88e6xxx_g2_pot_clear, 4559 .reset = mv88e6352_g1_reset, 4560 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4561 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4562 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4563 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4564 .stu_getnext = mv88e6352_g1_stu_getnext, 4565 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4566 .phylink_get_caps = mv88e6185_phylink_get_caps, 4567 }; 4568 4569 static const struct mv88e6xxx_ops mv88e6176_ops = { 4570 /* MV88E6XXX_FAMILY_6352 */ 4571 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4572 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4573 .irl_init_all = mv88e6352_g2_irl_init_all, 4574 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4575 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4576 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4577 .phy_read = mv88e6xxx_g2_smi_phy_read, 4578 .phy_write = mv88e6xxx_g2_smi_phy_write, 4579 .port_set_link = mv88e6xxx_port_set_link, 4580 .port_sync_link = mv88e6xxx_port_sync_link, 4581 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4582 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4583 .port_tag_remap = mv88e6095_port_tag_remap, 4584 .port_set_policy = mv88e6352_port_set_policy, 4585 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4586 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4587 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4588 .port_set_ether_type = mv88e6351_port_set_ether_type, 4589 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4590 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4591 .port_pause_limit = mv88e6097_port_pause_limit, 4592 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4593 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4594 .port_get_cmode = mv88e6352_port_get_cmode, 4595 .port_setup_message_port = mv88e6xxx_setup_message_port, 4596 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4597 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4598 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4599 .stats_get_strings = mv88e6095_stats_get_strings, 4600 .stats_get_stats = mv88e6095_stats_get_stats, 4601 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4602 .set_egress_port = mv88e6095_g1_set_egress_port, 4603 .watchdog_ops = &mv88e6097_watchdog_ops, 4604 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4605 .pot_clear = mv88e6xxx_g2_pot_clear, 4606 .reset = mv88e6352_g1_reset, 4607 .rmu_disable = mv88e6352_g1_rmu_disable, 4608 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4609 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4610 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4611 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4612 .stu_getnext = mv88e6352_g1_stu_getnext, 4613 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4614 .serdes_get_lane = mv88e6352_serdes_get_lane, 4615 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4616 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4617 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4618 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4619 .serdes_power = mv88e6352_serdes_power, 4620 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4621 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4622 .serdes_irq_status = mv88e6352_serdes_irq_status, 4623 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4624 .serdes_get_regs = mv88e6352_serdes_get_regs, 4625 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4626 .gpio_ops = &mv88e6352_gpio_ops, 4627 .phylink_get_caps = mv88e6352_phylink_get_caps, 4628 }; 4629 4630 static const struct mv88e6xxx_ops mv88e6185_ops = { 4631 /* MV88E6XXX_FAMILY_6185 */ 4632 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4633 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4634 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4635 .phy_read = mv88e6185_phy_ppu_read, 4636 .phy_write = mv88e6185_phy_ppu_write, 4637 .port_set_link = mv88e6xxx_port_set_link, 4638 .port_sync_link = mv88e6185_port_sync_link, 4639 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4640 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4641 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4642 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4643 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4644 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4645 .port_set_pause = mv88e6185_port_set_pause, 4646 .port_get_cmode = mv88e6185_port_get_cmode, 4647 .port_setup_message_port = mv88e6xxx_setup_message_port, 4648 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4649 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4650 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4651 .stats_get_strings = mv88e6095_stats_get_strings, 4652 .stats_get_stats = mv88e6095_stats_get_stats, 4653 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4654 .set_egress_port = mv88e6095_g1_set_egress_port, 4655 .watchdog_ops = &mv88e6097_watchdog_ops, 4656 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4657 .serdes_power = mv88e6185_serdes_power, 4658 .serdes_get_lane = mv88e6185_serdes_get_lane, 4659 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4660 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4661 .ppu_enable = mv88e6185_g1_ppu_enable, 4662 .ppu_disable = mv88e6185_g1_ppu_disable, 4663 .reset = mv88e6185_g1_reset, 4664 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4665 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4666 .phylink_get_caps = mv88e6185_phylink_get_caps, 4667 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4668 }; 4669 4670 static const struct mv88e6xxx_ops mv88e6190_ops = { 4671 /* MV88E6XXX_FAMILY_6390 */ 4672 .setup_errata = mv88e6390_setup_errata, 4673 .irl_init_all = mv88e6390_g2_irl_init_all, 4674 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4675 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4676 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4677 .phy_read = mv88e6xxx_g2_smi_phy_read, 4678 .phy_write = mv88e6xxx_g2_smi_phy_write, 4679 .port_set_link = mv88e6xxx_port_set_link, 4680 .port_sync_link = mv88e6xxx_port_sync_link, 4681 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4682 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4683 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4684 .port_tag_remap = mv88e6390_port_tag_remap, 4685 .port_set_policy = mv88e6352_port_set_policy, 4686 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4687 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4688 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4689 .port_set_ether_type = mv88e6351_port_set_ether_type, 4690 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4691 .port_pause_limit = mv88e6390_port_pause_limit, 4692 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4693 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4694 .port_get_cmode = mv88e6352_port_get_cmode, 4695 .port_set_cmode = mv88e6390_port_set_cmode, 4696 .port_setup_message_port = mv88e6xxx_setup_message_port, 4697 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4698 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4699 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4700 .stats_get_strings = mv88e6320_stats_get_strings, 4701 .stats_get_stats = mv88e6390_stats_get_stats, 4702 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4703 .set_egress_port = mv88e6390_g1_set_egress_port, 4704 .watchdog_ops = &mv88e6390_watchdog_ops, 4705 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4706 .pot_clear = mv88e6xxx_g2_pot_clear, 4707 .reset = mv88e6352_g1_reset, 4708 .rmu_disable = mv88e6390_g1_rmu_disable, 4709 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4710 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4711 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4712 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4713 .stu_getnext = mv88e6390_g1_stu_getnext, 4714 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4715 .serdes_power = mv88e6390_serdes_power, 4716 .serdes_get_lane = mv88e6390_serdes_get_lane, 4717 /* Check status register pause & lpa register */ 4718 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4719 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4720 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4721 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4722 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4723 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4724 .serdes_irq_status = mv88e6390_serdes_irq_status, 4725 .serdes_get_strings = mv88e6390_serdes_get_strings, 4726 .serdes_get_stats = mv88e6390_serdes_get_stats, 4727 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4728 .serdes_get_regs = mv88e6390_serdes_get_regs, 4729 .gpio_ops = &mv88e6352_gpio_ops, 4730 .phylink_get_caps = mv88e6390_phylink_get_caps, 4731 }; 4732 4733 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4734 /* MV88E6XXX_FAMILY_6390 */ 4735 .setup_errata = mv88e6390_setup_errata, 4736 .irl_init_all = mv88e6390_g2_irl_init_all, 4737 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4738 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4739 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4740 .phy_read = mv88e6xxx_g2_smi_phy_read, 4741 .phy_write = mv88e6xxx_g2_smi_phy_write, 4742 .port_set_link = mv88e6xxx_port_set_link, 4743 .port_sync_link = mv88e6xxx_port_sync_link, 4744 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4745 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4746 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4747 .port_tag_remap = mv88e6390_port_tag_remap, 4748 .port_set_policy = mv88e6352_port_set_policy, 4749 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4750 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4751 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4752 .port_set_ether_type = mv88e6351_port_set_ether_type, 4753 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4754 .port_pause_limit = mv88e6390_port_pause_limit, 4755 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4756 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4757 .port_get_cmode = mv88e6352_port_get_cmode, 4758 .port_set_cmode = mv88e6390x_port_set_cmode, 4759 .port_setup_message_port = mv88e6xxx_setup_message_port, 4760 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4761 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4762 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4763 .stats_get_strings = mv88e6320_stats_get_strings, 4764 .stats_get_stats = mv88e6390_stats_get_stats, 4765 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4766 .set_egress_port = mv88e6390_g1_set_egress_port, 4767 .watchdog_ops = &mv88e6390_watchdog_ops, 4768 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4769 .pot_clear = mv88e6xxx_g2_pot_clear, 4770 .reset = mv88e6352_g1_reset, 4771 .rmu_disable = mv88e6390_g1_rmu_disable, 4772 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4773 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4774 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4775 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4776 .stu_getnext = mv88e6390_g1_stu_getnext, 4777 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4778 .serdes_power = mv88e6390_serdes_power, 4779 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4780 /* Check status register pause & lpa register */ 4781 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4782 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4783 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4784 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4785 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4786 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4787 .serdes_irq_status = mv88e6390_serdes_irq_status, 4788 .serdes_get_strings = mv88e6390_serdes_get_strings, 4789 .serdes_get_stats = mv88e6390_serdes_get_stats, 4790 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4791 .serdes_get_regs = mv88e6390_serdes_get_regs, 4792 .gpio_ops = &mv88e6352_gpio_ops, 4793 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4794 }; 4795 4796 static const struct mv88e6xxx_ops mv88e6191_ops = { 4797 /* MV88E6XXX_FAMILY_6390 */ 4798 .setup_errata = mv88e6390_setup_errata, 4799 .irl_init_all = mv88e6390_g2_irl_init_all, 4800 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4801 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4802 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4803 .phy_read = mv88e6xxx_g2_smi_phy_read, 4804 .phy_write = mv88e6xxx_g2_smi_phy_write, 4805 .port_set_link = mv88e6xxx_port_set_link, 4806 .port_sync_link = mv88e6xxx_port_sync_link, 4807 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4808 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4809 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4810 .port_tag_remap = mv88e6390_port_tag_remap, 4811 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4812 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4813 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4814 .port_set_ether_type = mv88e6351_port_set_ether_type, 4815 .port_pause_limit = mv88e6390_port_pause_limit, 4816 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4817 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4818 .port_get_cmode = mv88e6352_port_get_cmode, 4819 .port_set_cmode = mv88e6390_port_set_cmode, 4820 .port_setup_message_port = mv88e6xxx_setup_message_port, 4821 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4822 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4823 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4824 .stats_get_strings = mv88e6320_stats_get_strings, 4825 .stats_get_stats = mv88e6390_stats_get_stats, 4826 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4827 .set_egress_port = mv88e6390_g1_set_egress_port, 4828 .watchdog_ops = &mv88e6390_watchdog_ops, 4829 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4830 .pot_clear = mv88e6xxx_g2_pot_clear, 4831 .reset = mv88e6352_g1_reset, 4832 .rmu_disable = mv88e6390_g1_rmu_disable, 4833 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4834 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4835 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4836 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4837 .stu_getnext = mv88e6390_g1_stu_getnext, 4838 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4839 .serdes_power = mv88e6390_serdes_power, 4840 .serdes_get_lane = mv88e6390_serdes_get_lane, 4841 /* Check status register pause & lpa register */ 4842 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4843 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4844 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4845 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4846 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4847 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4848 .serdes_irq_status = mv88e6390_serdes_irq_status, 4849 .serdes_get_strings = mv88e6390_serdes_get_strings, 4850 .serdes_get_stats = mv88e6390_serdes_get_stats, 4851 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4852 .serdes_get_regs = mv88e6390_serdes_get_regs, 4853 .avb_ops = &mv88e6390_avb_ops, 4854 .ptp_ops = &mv88e6352_ptp_ops, 4855 .phylink_get_caps = mv88e6390_phylink_get_caps, 4856 }; 4857 4858 static const struct mv88e6xxx_ops mv88e6240_ops = { 4859 /* MV88E6XXX_FAMILY_6352 */ 4860 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4861 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4862 .irl_init_all = mv88e6352_g2_irl_init_all, 4863 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4864 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4865 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4866 .phy_read = mv88e6xxx_g2_smi_phy_read, 4867 .phy_write = mv88e6xxx_g2_smi_phy_write, 4868 .port_set_link = mv88e6xxx_port_set_link, 4869 .port_sync_link = mv88e6xxx_port_sync_link, 4870 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4871 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4872 .port_tag_remap = mv88e6095_port_tag_remap, 4873 .port_set_policy = mv88e6352_port_set_policy, 4874 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4875 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4876 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4877 .port_set_ether_type = mv88e6351_port_set_ether_type, 4878 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4879 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4880 .port_pause_limit = mv88e6097_port_pause_limit, 4881 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4882 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4883 .port_get_cmode = mv88e6352_port_get_cmode, 4884 .port_setup_message_port = mv88e6xxx_setup_message_port, 4885 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4886 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4887 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4888 .stats_get_strings = mv88e6095_stats_get_strings, 4889 .stats_get_stats = mv88e6095_stats_get_stats, 4890 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4891 .set_egress_port = mv88e6095_g1_set_egress_port, 4892 .watchdog_ops = &mv88e6097_watchdog_ops, 4893 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4894 .pot_clear = mv88e6xxx_g2_pot_clear, 4895 .reset = mv88e6352_g1_reset, 4896 .rmu_disable = mv88e6352_g1_rmu_disable, 4897 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4898 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4899 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4900 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4901 .stu_getnext = mv88e6352_g1_stu_getnext, 4902 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4903 .serdes_get_lane = mv88e6352_serdes_get_lane, 4904 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4905 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4906 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4907 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4908 .serdes_power = mv88e6352_serdes_power, 4909 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4910 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4911 .serdes_irq_status = mv88e6352_serdes_irq_status, 4912 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4913 .serdes_get_regs = mv88e6352_serdes_get_regs, 4914 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4915 .gpio_ops = &mv88e6352_gpio_ops, 4916 .avb_ops = &mv88e6352_avb_ops, 4917 .ptp_ops = &mv88e6352_ptp_ops, 4918 .phylink_get_caps = mv88e6352_phylink_get_caps, 4919 }; 4920 4921 static const struct mv88e6xxx_ops mv88e6250_ops = { 4922 /* MV88E6XXX_FAMILY_6250 */ 4923 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4924 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4925 .irl_init_all = mv88e6352_g2_irl_init_all, 4926 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4927 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4928 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4929 .phy_read = mv88e6xxx_g2_smi_phy_read, 4930 .phy_write = mv88e6xxx_g2_smi_phy_write, 4931 .port_set_link = mv88e6xxx_port_set_link, 4932 .port_sync_link = mv88e6xxx_port_sync_link, 4933 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4934 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4935 .port_tag_remap = mv88e6095_port_tag_remap, 4936 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4937 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4938 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4939 .port_set_ether_type = mv88e6351_port_set_ether_type, 4940 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4941 .port_pause_limit = mv88e6097_port_pause_limit, 4942 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4943 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4944 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4945 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4946 .stats_get_strings = mv88e6250_stats_get_strings, 4947 .stats_get_stats = mv88e6250_stats_get_stats, 4948 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4949 .set_egress_port = mv88e6095_g1_set_egress_port, 4950 .watchdog_ops = &mv88e6250_watchdog_ops, 4951 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4952 .pot_clear = mv88e6xxx_g2_pot_clear, 4953 .reset = mv88e6250_g1_reset, 4954 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4955 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4956 .avb_ops = &mv88e6352_avb_ops, 4957 .ptp_ops = &mv88e6250_ptp_ops, 4958 .phylink_get_caps = mv88e6250_phylink_get_caps, 4959 }; 4960 4961 static const struct mv88e6xxx_ops mv88e6290_ops = { 4962 /* MV88E6XXX_FAMILY_6390 */ 4963 .setup_errata = mv88e6390_setup_errata, 4964 .irl_init_all = mv88e6390_g2_irl_init_all, 4965 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4966 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4967 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4968 .phy_read = mv88e6xxx_g2_smi_phy_read, 4969 .phy_write = mv88e6xxx_g2_smi_phy_write, 4970 .port_set_link = mv88e6xxx_port_set_link, 4971 .port_sync_link = mv88e6xxx_port_sync_link, 4972 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4973 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4974 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4975 .port_tag_remap = mv88e6390_port_tag_remap, 4976 .port_set_policy = mv88e6352_port_set_policy, 4977 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4978 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4979 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4980 .port_set_ether_type = mv88e6351_port_set_ether_type, 4981 .port_pause_limit = mv88e6390_port_pause_limit, 4982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4984 .port_get_cmode = mv88e6352_port_get_cmode, 4985 .port_set_cmode = mv88e6390_port_set_cmode, 4986 .port_setup_message_port = mv88e6xxx_setup_message_port, 4987 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4988 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4989 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4990 .stats_get_strings = mv88e6320_stats_get_strings, 4991 .stats_get_stats = mv88e6390_stats_get_stats, 4992 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4993 .set_egress_port = mv88e6390_g1_set_egress_port, 4994 .watchdog_ops = &mv88e6390_watchdog_ops, 4995 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4996 .pot_clear = mv88e6xxx_g2_pot_clear, 4997 .reset = mv88e6352_g1_reset, 4998 .rmu_disable = mv88e6390_g1_rmu_disable, 4999 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5000 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5001 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5002 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5003 .stu_getnext = mv88e6390_g1_stu_getnext, 5004 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5005 .serdes_power = mv88e6390_serdes_power, 5006 .serdes_get_lane = mv88e6390_serdes_get_lane, 5007 /* Check status register pause & lpa register */ 5008 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5009 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5010 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5011 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5012 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5013 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5014 .serdes_irq_status = mv88e6390_serdes_irq_status, 5015 .serdes_get_strings = mv88e6390_serdes_get_strings, 5016 .serdes_get_stats = mv88e6390_serdes_get_stats, 5017 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5018 .serdes_get_regs = mv88e6390_serdes_get_regs, 5019 .gpio_ops = &mv88e6352_gpio_ops, 5020 .avb_ops = &mv88e6390_avb_ops, 5021 .ptp_ops = &mv88e6352_ptp_ops, 5022 .phylink_get_caps = mv88e6390_phylink_get_caps, 5023 }; 5024 5025 static const struct mv88e6xxx_ops mv88e6320_ops = { 5026 /* MV88E6XXX_FAMILY_6320 */ 5027 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5028 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5029 .irl_init_all = mv88e6352_g2_irl_init_all, 5030 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5031 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5032 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5033 .phy_read = mv88e6xxx_g2_smi_phy_read, 5034 .phy_write = mv88e6xxx_g2_smi_phy_write, 5035 .port_set_link = mv88e6xxx_port_set_link, 5036 .port_sync_link = mv88e6xxx_port_sync_link, 5037 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5038 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5039 .port_tag_remap = mv88e6095_port_tag_remap, 5040 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5041 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5042 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5043 .port_set_ether_type = mv88e6351_port_set_ether_type, 5044 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5045 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5046 .port_pause_limit = mv88e6097_port_pause_limit, 5047 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5048 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5049 .port_get_cmode = mv88e6352_port_get_cmode, 5050 .port_setup_message_port = mv88e6xxx_setup_message_port, 5051 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5052 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5053 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5054 .stats_get_strings = mv88e6320_stats_get_strings, 5055 .stats_get_stats = mv88e6320_stats_get_stats, 5056 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5057 .set_egress_port = mv88e6095_g1_set_egress_port, 5058 .watchdog_ops = &mv88e6390_watchdog_ops, 5059 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5060 .pot_clear = mv88e6xxx_g2_pot_clear, 5061 .reset = mv88e6352_g1_reset, 5062 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5063 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5064 .gpio_ops = &mv88e6352_gpio_ops, 5065 .avb_ops = &mv88e6352_avb_ops, 5066 .ptp_ops = &mv88e6352_ptp_ops, 5067 .phylink_get_caps = mv88e6185_phylink_get_caps, 5068 }; 5069 5070 static const struct mv88e6xxx_ops mv88e6321_ops = { 5071 /* MV88E6XXX_FAMILY_6320 */ 5072 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5073 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5074 .irl_init_all = mv88e6352_g2_irl_init_all, 5075 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5076 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5077 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5078 .phy_read = mv88e6xxx_g2_smi_phy_read, 5079 .phy_write = mv88e6xxx_g2_smi_phy_write, 5080 .port_set_link = mv88e6xxx_port_set_link, 5081 .port_sync_link = mv88e6xxx_port_sync_link, 5082 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5083 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5084 .port_tag_remap = mv88e6095_port_tag_remap, 5085 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5086 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5087 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5088 .port_set_ether_type = mv88e6351_port_set_ether_type, 5089 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5090 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5091 .port_pause_limit = mv88e6097_port_pause_limit, 5092 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5093 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5094 .port_get_cmode = mv88e6352_port_get_cmode, 5095 .port_setup_message_port = mv88e6xxx_setup_message_port, 5096 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5097 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5098 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5099 .stats_get_strings = mv88e6320_stats_get_strings, 5100 .stats_get_stats = mv88e6320_stats_get_stats, 5101 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5102 .set_egress_port = mv88e6095_g1_set_egress_port, 5103 .watchdog_ops = &mv88e6390_watchdog_ops, 5104 .reset = mv88e6352_g1_reset, 5105 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5106 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5107 .gpio_ops = &mv88e6352_gpio_ops, 5108 .avb_ops = &mv88e6352_avb_ops, 5109 .ptp_ops = &mv88e6352_ptp_ops, 5110 .phylink_get_caps = mv88e6185_phylink_get_caps, 5111 }; 5112 5113 static const struct mv88e6xxx_ops mv88e6341_ops = { 5114 /* MV88E6XXX_FAMILY_6341 */ 5115 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5116 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5117 .irl_init_all = mv88e6352_g2_irl_init_all, 5118 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5119 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5120 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5121 .phy_read = mv88e6xxx_g2_smi_phy_read, 5122 .phy_write = mv88e6xxx_g2_smi_phy_write, 5123 .port_set_link = mv88e6xxx_port_set_link, 5124 .port_sync_link = mv88e6xxx_port_sync_link, 5125 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5126 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5127 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5128 .port_tag_remap = mv88e6095_port_tag_remap, 5129 .port_set_policy = mv88e6352_port_set_policy, 5130 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5131 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5132 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5133 .port_set_ether_type = mv88e6351_port_set_ether_type, 5134 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5135 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5136 .port_pause_limit = mv88e6097_port_pause_limit, 5137 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5138 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5139 .port_get_cmode = mv88e6352_port_get_cmode, 5140 .port_set_cmode = mv88e6341_port_set_cmode, 5141 .port_setup_message_port = mv88e6xxx_setup_message_port, 5142 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5143 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5144 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5145 .stats_get_strings = mv88e6320_stats_get_strings, 5146 .stats_get_stats = mv88e6390_stats_get_stats, 5147 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5148 .set_egress_port = mv88e6390_g1_set_egress_port, 5149 .watchdog_ops = &mv88e6390_watchdog_ops, 5150 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5151 .pot_clear = mv88e6xxx_g2_pot_clear, 5152 .reset = mv88e6352_g1_reset, 5153 .rmu_disable = mv88e6390_g1_rmu_disable, 5154 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5155 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5156 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5157 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5158 .stu_getnext = mv88e6352_g1_stu_getnext, 5159 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5160 .serdes_power = mv88e6390_serdes_power, 5161 .serdes_get_lane = mv88e6341_serdes_get_lane, 5162 /* Check status register pause & lpa register */ 5163 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5164 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5165 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5166 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5167 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5168 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5169 .serdes_irq_status = mv88e6390_serdes_irq_status, 5170 .gpio_ops = &mv88e6352_gpio_ops, 5171 .avb_ops = &mv88e6390_avb_ops, 5172 .ptp_ops = &mv88e6352_ptp_ops, 5173 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5174 .serdes_get_strings = mv88e6390_serdes_get_strings, 5175 .serdes_get_stats = mv88e6390_serdes_get_stats, 5176 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5177 .serdes_get_regs = mv88e6390_serdes_get_regs, 5178 .phylink_get_caps = mv88e6341_phylink_get_caps, 5179 }; 5180 5181 static const struct mv88e6xxx_ops mv88e6350_ops = { 5182 /* MV88E6XXX_FAMILY_6351 */ 5183 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5184 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5185 .irl_init_all = mv88e6352_g2_irl_init_all, 5186 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5187 .phy_read = mv88e6xxx_g2_smi_phy_read, 5188 .phy_write = mv88e6xxx_g2_smi_phy_write, 5189 .port_set_link = mv88e6xxx_port_set_link, 5190 .port_sync_link = mv88e6xxx_port_sync_link, 5191 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5192 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5193 .port_tag_remap = mv88e6095_port_tag_remap, 5194 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5195 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5196 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5197 .port_set_ether_type = mv88e6351_port_set_ether_type, 5198 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5199 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5200 .port_pause_limit = mv88e6097_port_pause_limit, 5201 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5202 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5203 .port_get_cmode = mv88e6352_port_get_cmode, 5204 .port_setup_message_port = mv88e6xxx_setup_message_port, 5205 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5206 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5207 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5208 .stats_get_strings = mv88e6095_stats_get_strings, 5209 .stats_get_stats = mv88e6095_stats_get_stats, 5210 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5211 .set_egress_port = mv88e6095_g1_set_egress_port, 5212 .watchdog_ops = &mv88e6097_watchdog_ops, 5213 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5214 .pot_clear = mv88e6xxx_g2_pot_clear, 5215 .reset = mv88e6352_g1_reset, 5216 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5217 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5218 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5219 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5220 .stu_getnext = mv88e6352_g1_stu_getnext, 5221 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5222 .phylink_get_caps = mv88e6185_phylink_get_caps, 5223 }; 5224 5225 static const struct mv88e6xxx_ops mv88e6351_ops = { 5226 /* MV88E6XXX_FAMILY_6351 */ 5227 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5228 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5229 .irl_init_all = mv88e6352_g2_irl_init_all, 5230 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5231 .phy_read = mv88e6xxx_g2_smi_phy_read, 5232 .phy_write = mv88e6xxx_g2_smi_phy_write, 5233 .port_set_link = mv88e6xxx_port_set_link, 5234 .port_sync_link = mv88e6xxx_port_sync_link, 5235 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5236 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5237 .port_tag_remap = mv88e6095_port_tag_remap, 5238 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5239 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5240 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5241 .port_set_ether_type = mv88e6351_port_set_ether_type, 5242 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5243 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5244 .port_pause_limit = mv88e6097_port_pause_limit, 5245 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5246 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5247 .port_get_cmode = mv88e6352_port_get_cmode, 5248 .port_setup_message_port = mv88e6xxx_setup_message_port, 5249 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5250 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5251 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5252 .stats_get_strings = mv88e6095_stats_get_strings, 5253 .stats_get_stats = mv88e6095_stats_get_stats, 5254 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5255 .set_egress_port = mv88e6095_g1_set_egress_port, 5256 .watchdog_ops = &mv88e6097_watchdog_ops, 5257 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5258 .pot_clear = mv88e6xxx_g2_pot_clear, 5259 .reset = mv88e6352_g1_reset, 5260 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5261 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5262 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5263 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5264 .stu_getnext = mv88e6352_g1_stu_getnext, 5265 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5266 .avb_ops = &mv88e6352_avb_ops, 5267 .ptp_ops = &mv88e6352_ptp_ops, 5268 .phylink_get_caps = mv88e6185_phylink_get_caps, 5269 }; 5270 5271 static const struct mv88e6xxx_ops mv88e6352_ops = { 5272 /* MV88E6XXX_FAMILY_6352 */ 5273 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5274 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5275 .irl_init_all = mv88e6352_g2_irl_init_all, 5276 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5277 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5278 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5279 .phy_read = mv88e6xxx_g2_smi_phy_read, 5280 .phy_write = mv88e6xxx_g2_smi_phy_write, 5281 .port_set_link = mv88e6xxx_port_set_link, 5282 .port_sync_link = mv88e6xxx_port_sync_link, 5283 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5284 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5285 .port_tag_remap = mv88e6095_port_tag_remap, 5286 .port_set_policy = mv88e6352_port_set_policy, 5287 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5288 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5289 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5290 .port_set_ether_type = mv88e6351_port_set_ether_type, 5291 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5292 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5293 .port_pause_limit = mv88e6097_port_pause_limit, 5294 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5295 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5296 .port_get_cmode = mv88e6352_port_get_cmode, 5297 .port_setup_message_port = mv88e6xxx_setup_message_port, 5298 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5299 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5300 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5301 .stats_get_strings = mv88e6095_stats_get_strings, 5302 .stats_get_stats = mv88e6095_stats_get_stats, 5303 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5304 .set_egress_port = mv88e6095_g1_set_egress_port, 5305 .watchdog_ops = &mv88e6097_watchdog_ops, 5306 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5307 .pot_clear = mv88e6xxx_g2_pot_clear, 5308 .reset = mv88e6352_g1_reset, 5309 .rmu_disable = mv88e6352_g1_rmu_disable, 5310 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5311 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5312 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5313 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5314 .stu_getnext = mv88e6352_g1_stu_getnext, 5315 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5316 .serdes_get_lane = mv88e6352_serdes_get_lane, 5317 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5318 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5319 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5320 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5321 .serdes_power = mv88e6352_serdes_power, 5322 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5323 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5324 .serdes_irq_status = mv88e6352_serdes_irq_status, 5325 .gpio_ops = &mv88e6352_gpio_ops, 5326 .avb_ops = &mv88e6352_avb_ops, 5327 .ptp_ops = &mv88e6352_ptp_ops, 5328 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5329 .serdes_get_strings = mv88e6352_serdes_get_strings, 5330 .serdes_get_stats = mv88e6352_serdes_get_stats, 5331 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5332 .serdes_get_regs = mv88e6352_serdes_get_regs, 5333 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5334 .phylink_get_caps = mv88e6352_phylink_get_caps, 5335 }; 5336 5337 static const struct mv88e6xxx_ops mv88e6390_ops = { 5338 /* MV88E6XXX_FAMILY_6390 */ 5339 .setup_errata = mv88e6390_setup_errata, 5340 .irl_init_all = mv88e6390_g2_irl_init_all, 5341 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5342 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5343 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5344 .phy_read = mv88e6xxx_g2_smi_phy_read, 5345 .phy_write = mv88e6xxx_g2_smi_phy_write, 5346 .port_set_link = mv88e6xxx_port_set_link, 5347 .port_sync_link = mv88e6xxx_port_sync_link, 5348 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5349 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5350 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5351 .port_tag_remap = mv88e6390_port_tag_remap, 5352 .port_set_policy = mv88e6352_port_set_policy, 5353 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5354 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5355 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5356 .port_set_ether_type = mv88e6351_port_set_ether_type, 5357 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5358 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5359 .port_pause_limit = mv88e6390_port_pause_limit, 5360 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5361 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5362 .port_get_cmode = mv88e6352_port_get_cmode, 5363 .port_set_cmode = mv88e6390_port_set_cmode, 5364 .port_setup_message_port = mv88e6xxx_setup_message_port, 5365 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5366 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5367 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5368 .stats_get_strings = mv88e6320_stats_get_strings, 5369 .stats_get_stats = mv88e6390_stats_get_stats, 5370 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5371 .set_egress_port = mv88e6390_g1_set_egress_port, 5372 .watchdog_ops = &mv88e6390_watchdog_ops, 5373 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5374 .pot_clear = mv88e6xxx_g2_pot_clear, 5375 .reset = mv88e6352_g1_reset, 5376 .rmu_disable = mv88e6390_g1_rmu_disable, 5377 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5378 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5379 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5380 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5381 .stu_getnext = mv88e6390_g1_stu_getnext, 5382 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5383 .serdes_power = mv88e6390_serdes_power, 5384 .serdes_get_lane = mv88e6390_serdes_get_lane, 5385 /* Check status register pause & lpa register */ 5386 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5387 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5388 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5389 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5390 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5391 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5392 .serdes_irq_status = mv88e6390_serdes_irq_status, 5393 .gpio_ops = &mv88e6352_gpio_ops, 5394 .avb_ops = &mv88e6390_avb_ops, 5395 .ptp_ops = &mv88e6352_ptp_ops, 5396 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5397 .serdes_get_strings = mv88e6390_serdes_get_strings, 5398 .serdes_get_stats = mv88e6390_serdes_get_stats, 5399 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5400 .serdes_get_regs = mv88e6390_serdes_get_regs, 5401 .phylink_get_caps = mv88e6390_phylink_get_caps, 5402 }; 5403 5404 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5405 /* MV88E6XXX_FAMILY_6390 */ 5406 .setup_errata = mv88e6390_setup_errata, 5407 .irl_init_all = mv88e6390_g2_irl_init_all, 5408 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5409 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5410 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5411 .phy_read = mv88e6xxx_g2_smi_phy_read, 5412 .phy_write = mv88e6xxx_g2_smi_phy_write, 5413 .port_set_link = mv88e6xxx_port_set_link, 5414 .port_sync_link = mv88e6xxx_port_sync_link, 5415 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5416 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5417 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5418 .port_tag_remap = mv88e6390_port_tag_remap, 5419 .port_set_policy = mv88e6352_port_set_policy, 5420 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5421 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5422 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5423 .port_set_ether_type = mv88e6351_port_set_ether_type, 5424 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5425 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5426 .port_pause_limit = mv88e6390_port_pause_limit, 5427 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5428 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5429 .port_get_cmode = mv88e6352_port_get_cmode, 5430 .port_set_cmode = mv88e6390x_port_set_cmode, 5431 .port_setup_message_port = mv88e6xxx_setup_message_port, 5432 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5433 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5434 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5435 .stats_get_strings = mv88e6320_stats_get_strings, 5436 .stats_get_stats = mv88e6390_stats_get_stats, 5437 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5438 .set_egress_port = mv88e6390_g1_set_egress_port, 5439 .watchdog_ops = &mv88e6390_watchdog_ops, 5440 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5441 .pot_clear = mv88e6xxx_g2_pot_clear, 5442 .reset = mv88e6352_g1_reset, 5443 .rmu_disable = mv88e6390_g1_rmu_disable, 5444 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5445 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5446 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5447 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5448 .stu_getnext = mv88e6390_g1_stu_getnext, 5449 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5450 .serdes_power = mv88e6390_serdes_power, 5451 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5452 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5453 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5454 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5455 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5456 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5457 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5458 .serdes_irq_status = mv88e6390_serdes_irq_status, 5459 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5460 .serdes_get_strings = mv88e6390_serdes_get_strings, 5461 .serdes_get_stats = mv88e6390_serdes_get_stats, 5462 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5463 .serdes_get_regs = mv88e6390_serdes_get_regs, 5464 .gpio_ops = &mv88e6352_gpio_ops, 5465 .avb_ops = &mv88e6390_avb_ops, 5466 .ptp_ops = &mv88e6352_ptp_ops, 5467 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5468 }; 5469 5470 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5471 /* MV88E6XXX_FAMILY_6393 */ 5472 .setup_errata = mv88e6393x_serdes_setup_errata, 5473 .irl_init_all = mv88e6390_g2_irl_init_all, 5474 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5475 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5476 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5477 .phy_read = mv88e6xxx_g2_smi_phy_read, 5478 .phy_write = mv88e6xxx_g2_smi_phy_write, 5479 .port_set_link = mv88e6xxx_port_set_link, 5480 .port_sync_link = mv88e6xxx_port_sync_link, 5481 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5482 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5483 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5484 .port_tag_remap = mv88e6390_port_tag_remap, 5485 .port_set_policy = mv88e6393x_port_set_policy, 5486 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5487 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5488 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5489 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5490 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5492 .port_pause_limit = mv88e6390_port_pause_limit, 5493 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5494 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5495 .port_get_cmode = mv88e6352_port_get_cmode, 5496 .port_set_cmode = mv88e6393x_port_set_cmode, 5497 .port_setup_message_port = mv88e6xxx_setup_message_port, 5498 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5499 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5500 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5501 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5502 .stats_get_strings = mv88e6320_stats_get_strings, 5503 .stats_get_stats = mv88e6390_stats_get_stats, 5504 /* .set_cpu_port is missing because this family does not support a global 5505 * CPU port, only per port CPU port which is set via 5506 * .port_set_upstream_port method. 5507 */ 5508 .set_egress_port = mv88e6393x_set_egress_port, 5509 .watchdog_ops = &mv88e6390_watchdog_ops, 5510 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5511 .pot_clear = mv88e6xxx_g2_pot_clear, 5512 .reset = mv88e6352_g1_reset, 5513 .rmu_disable = mv88e6390_g1_rmu_disable, 5514 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5515 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5516 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5517 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5518 .stu_getnext = mv88e6390_g1_stu_getnext, 5519 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5520 .serdes_power = mv88e6393x_serdes_power, 5521 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5522 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5523 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5524 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5525 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5526 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5527 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5528 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5529 /* TODO: serdes stats */ 5530 .gpio_ops = &mv88e6352_gpio_ops, 5531 .avb_ops = &mv88e6390_avb_ops, 5532 .ptp_ops = &mv88e6352_ptp_ops, 5533 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5534 }; 5535 5536 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5537 [MV88E6085] = { 5538 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5539 .family = MV88E6XXX_FAMILY_6097, 5540 .name = "Marvell 88E6085", 5541 .num_databases = 4096, 5542 .num_macs = 8192, 5543 .num_ports = 10, 5544 .num_internal_phys = 5, 5545 .max_vid = 4095, 5546 .max_sid = 63, 5547 .port_base_addr = 0x10, 5548 .phy_base_addr = 0x0, 5549 .global1_addr = 0x1b, 5550 .global2_addr = 0x1c, 5551 .age_time_coeff = 15000, 5552 .g1_irqs = 8, 5553 .g2_irqs = 10, 5554 .atu_move_port_mask = 0xf, 5555 .pvt = true, 5556 .multi_chip = true, 5557 .ops = &mv88e6085_ops, 5558 }, 5559 5560 [MV88E6095] = { 5561 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5562 .family = MV88E6XXX_FAMILY_6095, 5563 .name = "Marvell 88E6095/88E6095F", 5564 .num_databases = 256, 5565 .num_macs = 8192, 5566 .num_ports = 11, 5567 .num_internal_phys = 0, 5568 .max_vid = 4095, 5569 .port_base_addr = 0x10, 5570 .phy_base_addr = 0x0, 5571 .global1_addr = 0x1b, 5572 .global2_addr = 0x1c, 5573 .age_time_coeff = 15000, 5574 .g1_irqs = 8, 5575 .atu_move_port_mask = 0xf, 5576 .multi_chip = true, 5577 .ops = &mv88e6095_ops, 5578 }, 5579 5580 [MV88E6097] = { 5581 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5582 .family = MV88E6XXX_FAMILY_6097, 5583 .name = "Marvell 88E6097/88E6097F", 5584 .num_databases = 4096, 5585 .num_macs = 8192, 5586 .num_ports = 11, 5587 .num_internal_phys = 8, 5588 .max_vid = 4095, 5589 .max_sid = 63, 5590 .port_base_addr = 0x10, 5591 .phy_base_addr = 0x0, 5592 .global1_addr = 0x1b, 5593 .global2_addr = 0x1c, 5594 .age_time_coeff = 15000, 5595 .g1_irqs = 8, 5596 .g2_irqs = 10, 5597 .atu_move_port_mask = 0xf, 5598 .pvt = true, 5599 .multi_chip = true, 5600 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5601 .ops = &mv88e6097_ops, 5602 }, 5603 5604 [MV88E6123] = { 5605 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5606 .family = MV88E6XXX_FAMILY_6165, 5607 .name = "Marvell 88E6123", 5608 .num_databases = 4096, 5609 .num_macs = 1024, 5610 .num_ports = 3, 5611 .num_internal_phys = 5, 5612 .max_vid = 4095, 5613 .max_sid = 63, 5614 .port_base_addr = 0x10, 5615 .phy_base_addr = 0x0, 5616 .global1_addr = 0x1b, 5617 .global2_addr = 0x1c, 5618 .age_time_coeff = 15000, 5619 .g1_irqs = 9, 5620 .g2_irqs = 10, 5621 .atu_move_port_mask = 0xf, 5622 .pvt = true, 5623 .multi_chip = true, 5624 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5625 .ops = &mv88e6123_ops, 5626 }, 5627 5628 [MV88E6131] = { 5629 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5630 .family = MV88E6XXX_FAMILY_6185, 5631 .name = "Marvell 88E6131", 5632 .num_databases = 256, 5633 .num_macs = 8192, 5634 .num_ports = 8, 5635 .num_internal_phys = 0, 5636 .max_vid = 4095, 5637 .port_base_addr = 0x10, 5638 .phy_base_addr = 0x0, 5639 .global1_addr = 0x1b, 5640 .global2_addr = 0x1c, 5641 .age_time_coeff = 15000, 5642 .g1_irqs = 9, 5643 .atu_move_port_mask = 0xf, 5644 .multi_chip = true, 5645 .ops = &mv88e6131_ops, 5646 }, 5647 5648 [MV88E6141] = { 5649 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5650 .family = MV88E6XXX_FAMILY_6341, 5651 .name = "Marvell 88E6141", 5652 .num_databases = 4096, 5653 .num_macs = 2048, 5654 .num_ports = 6, 5655 .num_internal_phys = 5, 5656 .num_gpio = 11, 5657 .max_vid = 4095, 5658 .max_sid = 63, 5659 .port_base_addr = 0x10, 5660 .phy_base_addr = 0x10, 5661 .global1_addr = 0x1b, 5662 .global2_addr = 0x1c, 5663 .age_time_coeff = 3750, 5664 .atu_move_port_mask = 0x1f, 5665 .g1_irqs = 9, 5666 .g2_irqs = 10, 5667 .pvt = true, 5668 .multi_chip = true, 5669 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5670 .ops = &mv88e6141_ops, 5671 }, 5672 5673 [MV88E6161] = { 5674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5675 .family = MV88E6XXX_FAMILY_6165, 5676 .name = "Marvell 88E6161", 5677 .num_databases = 4096, 5678 .num_macs = 1024, 5679 .num_ports = 6, 5680 .num_internal_phys = 5, 5681 .max_vid = 4095, 5682 .max_sid = 63, 5683 .port_base_addr = 0x10, 5684 .phy_base_addr = 0x0, 5685 .global1_addr = 0x1b, 5686 .global2_addr = 0x1c, 5687 .age_time_coeff = 15000, 5688 .g1_irqs = 9, 5689 .g2_irqs = 10, 5690 .atu_move_port_mask = 0xf, 5691 .pvt = true, 5692 .multi_chip = true, 5693 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5694 .ptp_support = true, 5695 .ops = &mv88e6161_ops, 5696 }, 5697 5698 [MV88E6165] = { 5699 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5700 .family = MV88E6XXX_FAMILY_6165, 5701 .name = "Marvell 88E6165", 5702 .num_databases = 4096, 5703 .num_macs = 8192, 5704 .num_ports = 6, 5705 .num_internal_phys = 0, 5706 .max_vid = 4095, 5707 .max_sid = 63, 5708 .port_base_addr = 0x10, 5709 .phy_base_addr = 0x0, 5710 .global1_addr = 0x1b, 5711 .global2_addr = 0x1c, 5712 .age_time_coeff = 15000, 5713 .g1_irqs = 9, 5714 .g2_irqs = 10, 5715 .atu_move_port_mask = 0xf, 5716 .pvt = true, 5717 .multi_chip = true, 5718 .ptp_support = true, 5719 .ops = &mv88e6165_ops, 5720 }, 5721 5722 [MV88E6171] = { 5723 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5724 .family = MV88E6XXX_FAMILY_6351, 5725 .name = "Marvell 88E6171", 5726 .num_databases = 4096, 5727 .num_macs = 8192, 5728 .num_ports = 7, 5729 .num_internal_phys = 5, 5730 .max_vid = 4095, 5731 .max_sid = 63, 5732 .port_base_addr = 0x10, 5733 .phy_base_addr = 0x0, 5734 .global1_addr = 0x1b, 5735 .global2_addr = 0x1c, 5736 .age_time_coeff = 15000, 5737 .g1_irqs = 9, 5738 .g2_irqs = 10, 5739 .atu_move_port_mask = 0xf, 5740 .pvt = true, 5741 .multi_chip = true, 5742 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5743 .ops = &mv88e6171_ops, 5744 }, 5745 5746 [MV88E6172] = { 5747 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5748 .family = MV88E6XXX_FAMILY_6352, 5749 .name = "Marvell 88E6172", 5750 .num_databases = 4096, 5751 .num_macs = 8192, 5752 .num_ports = 7, 5753 .num_internal_phys = 5, 5754 .num_gpio = 15, 5755 .max_vid = 4095, 5756 .max_sid = 63, 5757 .port_base_addr = 0x10, 5758 .phy_base_addr = 0x0, 5759 .global1_addr = 0x1b, 5760 .global2_addr = 0x1c, 5761 .age_time_coeff = 15000, 5762 .g1_irqs = 9, 5763 .g2_irqs = 10, 5764 .atu_move_port_mask = 0xf, 5765 .pvt = true, 5766 .multi_chip = true, 5767 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5768 .ops = &mv88e6172_ops, 5769 }, 5770 5771 [MV88E6175] = { 5772 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5773 .family = MV88E6XXX_FAMILY_6351, 5774 .name = "Marvell 88E6175", 5775 .num_databases = 4096, 5776 .num_macs = 8192, 5777 .num_ports = 7, 5778 .num_internal_phys = 5, 5779 .max_vid = 4095, 5780 .max_sid = 63, 5781 .port_base_addr = 0x10, 5782 .phy_base_addr = 0x0, 5783 .global1_addr = 0x1b, 5784 .global2_addr = 0x1c, 5785 .age_time_coeff = 15000, 5786 .g1_irqs = 9, 5787 .g2_irqs = 10, 5788 .atu_move_port_mask = 0xf, 5789 .pvt = true, 5790 .multi_chip = true, 5791 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5792 .ops = &mv88e6175_ops, 5793 }, 5794 5795 [MV88E6176] = { 5796 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5797 .family = MV88E6XXX_FAMILY_6352, 5798 .name = "Marvell 88E6176", 5799 .num_databases = 4096, 5800 .num_macs = 8192, 5801 .num_ports = 7, 5802 .num_internal_phys = 5, 5803 .num_gpio = 15, 5804 .max_vid = 4095, 5805 .max_sid = 63, 5806 .port_base_addr = 0x10, 5807 .phy_base_addr = 0x0, 5808 .global1_addr = 0x1b, 5809 .global2_addr = 0x1c, 5810 .age_time_coeff = 15000, 5811 .g1_irqs = 9, 5812 .g2_irqs = 10, 5813 .atu_move_port_mask = 0xf, 5814 .pvt = true, 5815 .multi_chip = true, 5816 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5817 .ops = &mv88e6176_ops, 5818 }, 5819 5820 [MV88E6185] = { 5821 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5822 .family = MV88E6XXX_FAMILY_6185, 5823 .name = "Marvell 88E6185", 5824 .num_databases = 256, 5825 .num_macs = 8192, 5826 .num_ports = 10, 5827 .num_internal_phys = 0, 5828 .max_vid = 4095, 5829 .port_base_addr = 0x10, 5830 .phy_base_addr = 0x0, 5831 .global1_addr = 0x1b, 5832 .global2_addr = 0x1c, 5833 .age_time_coeff = 15000, 5834 .g1_irqs = 8, 5835 .atu_move_port_mask = 0xf, 5836 .multi_chip = true, 5837 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5838 .ops = &mv88e6185_ops, 5839 }, 5840 5841 [MV88E6190] = { 5842 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5843 .family = MV88E6XXX_FAMILY_6390, 5844 .name = "Marvell 88E6190", 5845 .num_databases = 4096, 5846 .num_macs = 16384, 5847 .num_ports = 11, /* 10 + Z80 */ 5848 .num_internal_phys = 9, 5849 .num_gpio = 16, 5850 .max_vid = 8191, 5851 .max_sid = 63, 5852 .port_base_addr = 0x0, 5853 .phy_base_addr = 0x0, 5854 .global1_addr = 0x1b, 5855 .global2_addr = 0x1c, 5856 .age_time_coeff = 3750, 5857 .g1_irqs = 9, 5858 .g2_irqs = 14, 5859 .pvt = true, 5860 .multi_chip = true, 5861 .atu_move_port_mask = 0x1f, 5862 .ops = &mv88e6190_ops, 5863 }, 5864 5865 [MV88E6190X] = { 5866 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5867 .family = MV88E6XXX_FAMILY_6390, 5868 .name = "Marvell 88E6190X", 5869 .num_databases = 4096, 5870 .num_macs = 16384, 5871 .num_ports = 11, /* 10 + Z80 */ 5872 .num_internal_phys = 9, 5873 .num_gpio = 16, 5874 .max_vid = 8191, 5875 .max_sid = 63, 5876 .port_base_addr = 0x0, 5877 .phy_base_addr = 0x0, 5878 .global1_addr = 0x1b, 5879 .global2_addr = 0x1c, 5880 .age_time_coeff = 3750, 5881 .g1_irqs = 9, 5882 .g2_irqs = 14, 5883 .atu_move_port_mask = 0x1f, 5884 .pvt = true, 5885 .multi_chip = true, 5886 .ops = &mv88e6190x_ops, 5887 }, 5888 5889 [MV88E6191] = { 5890 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5891 .family = MV88E6XXX_FAMILY_6390, 5892 .name = "Marvell 88E6191", 5893 .num_databases = 4096, 5894 .num_macs = 16384, 5895 .num_ports = 11, /* 10 + Z80 */ 5896 .num_internal_phys = 9, 5897 .max_vid = 8191, 5898 .max_sid = 63, 5899 .port_base_addr = 0x0, 5900 .phy_base_addr = 0x0, 5901 .global1_addr = 0x1b, 5902 .global2_addr = 0x1c, 5903 .age_time_coeff = 3750, 5904 .g1_irqs = 9, 5905 .g2_irqs = 14, 5906 .atu_move_port_mask = 0x1f, 5907 .pvt = true, 5908 .multi_chip = true, 5909 .ptp_support = true, 5910 .ops = &mv88e6191_ops, 5911 }, 5912 5913 [MV88E6191X] = { 5914 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5915 .family = MV88E6XXX_FAMILY_6393, 5916 .name = "Marvell 88E6191X", 5917 .num_databases = 4096, 5918 .num_ports = 11, /* 10 + Z80 */ 5919 .num_internal_phys = 9, 5920 .max_vid = 8191, 5921 .max_sid = 63, 5922 .port_base_addr = 0x0, 5923 .phy_base_addr = 0x0, 5924 .global1_addr = 0x1b, 5925 .global2_addr = 0x1c, 5926 .age_time_coeff = 3750, 5927 .g1_irqs = 10, 5928 .g2_irqs = 14, 5929 .atu_move_port_mask = 0x1f, 5930 .pvt = true, 5931 .multi_chip = true, 5932 .ptp_support = true, 5933 .ops = &mv88e6393x_ops, 5934 }, 5935 5936 [MV88E6193X] = { 5937 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5938 .family = MV88E6XXX_FAMILY_6393, 5939 .name = "Marvell 88E6193X", 5940 .num_databases = 4096, 5941 .num_ports = 11, /* 10 + Z80 */ 5942 .num_internal_phys = 9, 5943 .max_vid = 8191, 5944 .max_sid = 63, 5945 .port_base_addr = 0x0, 5946 .phy_base_addr = 0x0, 5947 .global1_addr = 0x1b, 5948 .global2_addr = 0x1c, 5949 .age_time_coeff = 3750, 5950 .g1_irqs = 10, 5951 .g2_irqs = 14, 5952 .atu_move_port_mask = 0x1f, 5953 .pvt = true, 5954 .multi_chip = true, 5955 .ptp_support = true, 5956 .ops = &mv88e6393x_ops, 5957 }, 5958 5959 [MV88E6220] = { 5960 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5961 .family = MV88E6XXX_FAMILY_6250, 5962 .name = "Marvell 88E6220", 5963 .num_databases = 64, 5964 5965 /* Ports 2-4 are not routed to pins 5966 * => usable ports 0, 1, 5, 6 5967 */ 5968 .num_ports = 7, 5969 .num_internal_phys = 2, 5970 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5971 .max_vid = 4095, 5972 .port_base_addr = 0x08, 5973 .phy_base_addr = 0x00, 5974 .global1_addr = 0x0f, 5975 .global2_addr = 0x07, 5976 .age_time_coeff = 15000, 5977 .g1_irqs = 9, 5978 .g2_irqs = 10, 5979 .atu_move_port_mask = 0xf, 5980 .dual_chip = true, 5981 .ptp_support = true, 5982 .ops = &mv88e6250_ops, 5983 }, 5984 5985 [MV88E6240] = { 5986 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5987 .family = MV88E6XXX_FAMILY_6352, 5988 .name = "Marvell 88E6240", 5989 .num_databases = 4096, 5990 .num_macs = 8192, 5991 .num_ports = 7, 5992 .num_internal_phys = 5, 5993 .num_gpio = 15, 5994 .max_vid = 4095, 5995 .max_sid = 63, 5996 .port_base_addr = 0x10, 5997 .phy_base_addr = 0x0, 5998 .global1_addr = 0x1b, 5999 .global2_addr = 0x1c, 6000 .age_time_coeff = 15000, 6001 .g1_irqs = 9, 6002 .g2_irqs = 10, 6003 .atu_move_port_mask = 0xf, 6004 .pvt = true, 6005 .multi_chip = true, 6006 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6007 .ptp_support = true, 6008 .ops = &mv88e6240_ops, 6009 }, 6010 6011 [MV88E6250] = { 6012 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6013 .family = MV88E6XXX_FAMILY_6250, 6014 .name = "Marvell 88E6250", 6015 .num_databases = 64, 6016 .num_ports = 7, 6017 .num_internal_phys = 5, 6018 .max_vid = 4095, 6019 .port_base_addr = 0x08, 6020 .phy_base_addr = 0x00, 6021 .global1_addr = 0x0f, 6022 .global2_addr = 0x07, 6023 .age_time_coeff = 15000, 6024 .g1_irqs = 9, 6025 .g2_irqs = 10, 6026 .atu_move_port_mask = 0xf, 6027 .dual_chip = true, 6028 .ptp_support = true, 6029 .ops = &mv88e6250_ops, 6030 }, 6031 6032 [MV88E6290] = { 6033 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6034 .family = MV88E6XXX_FAMILY_6390, 6035 .name = "Marvell 88E6290", 6036 .num_databases = 4096, 6037 .num_ports = 11, /* 10 + Z80 */ 6038 .num_internal_phys = 9, 6039 .num_gpio = 16, 6040 .max_vid = 8191, 6041 .max_sid = 63, 6042 .port_base_addr = 0x0, 6043 .phy_base_addr = 0x0, 6044 .global1_addr = 0x1b, 6045 .global2_addr = 0x1c, 6046 .age_time_coeff = 3750, 6047 .g1_irqs = 9, 6048 .g2_irqs = 14, 6049 .atu_move_port_mask = 0x1f, 6050 .pvt = true, 6051 .multi_chip = true, 6052 .ptp_support = true, 6053 .ops = &mv88e6290_ops, 6054 }, 6055 6056 [MV88E6320] = { 6057 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6058 .family = MV88E6XXX_FAMILY_6320, 6059 .name = "Marvell 88E6320", 6060 .num_databases = 4096, 6061 .num_macs = 8192, 6062 .num_ports = 7, 6063 .num_internal_phys = 5, 6064 .num_gpio = 15, 6065 .max_vid = 4095, 6066 .port_base_addr = 0x10, 6067 .phy_base_addr = 0x0, 6068 .global1_addr = 0x1b, 6069 .global2_addr = 0x1c, 6070 .age_time_coeff = 15000, 6071 .g1_irqs = 8, 6072 .g2_irqs = 10, 6073 .atu_move_port_mask = 0xf, 6074 .pvt = true, 6075 .multi_chip = true, 6076 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6077 .ptp_support = true, 6078 .ops = &mv88e6320_ops, 6079 }, 6080 6081 [MV88E6321] = { 6082 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6083 .family = MV88E6XXX_FAMILY_6320, 6084 .name = "Marvell 88E6321", 6085 .num_databases = 4096, 6086 .num_macs = 8192, 6087 .num_ports = 7, 6088 .num_internal_phys = 5, 6089 .num_gpio = 15, 6090 .max_vid = 4095, 6091 .port_base_addr = 0x10, 6092 .phy_base_addr = 0x0, 6093 .global1_addr = 0x1b, 6094 .global2_addr = 0x1c, 6095 .age_time_coeff = 15000, 6096 .g1_irqs = 8, 6097 .g2_irqs = 10, 6098 .atu_move_port_mask = 0xf, 6099 .multi_chip = true, 6100 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6101 .ptp_support = true, 6102 .ops = &mv88e6321_ops, 6103 }, 6104 6105 [MV88E6341] = { 6106 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6107 .family = MV88E6XXX_FAMILY_6341, 6108 .name = "Marvell 88E6341", 6109 .num_databases = 4096, 6110 .num_macs = 2048, 6111 .num_internal_phys = 5, 6112 .num_ports = 6, 6113 .num_gpio = 11, 6114 .max_vid = 4095, 6115 .max_sid = 63, 6116 .port_base_addr = 0x10, 6117 .phy_base_addr = 0x10, 6118 .global1_addr = 0x1b, 6119 .global2_addr = 0x1c, 6120 .age_time_coeff = 3750, 6121 .atu_move_port_mask = 0x1f, 6122 .g1_irqs = 9, 6123 .g2_irqs = 10, 6124 .pvt = true, 6125 .multi_chip = true, 6126 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6127 .ptp_support = true, 6128 .ops = &mv88e6341_ops, 6129 }, 6130 6131 [MV88E6350] = { 6132 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6133 .family = MV88E6XXX_FAMILY_6351, 6134 .name = "Marvell 88E6350", 6135 .num_databases = 4096, 6136 .num_macs = 8192, 6137 .num_ports = 7, 6138 .num_internal_phys = 5, 6139 .max_vid = 4095, 6140 .max_sid = 63, 6141 .port_base_addr = 0x10, 6142 .phy_base_addr = 0x0, 6143 .global1_addr = 0x1b, 6144 .global2_addr = 0x1c, 6145 .age_time_coeff = 15000, 6146 .g1_irqs = 9, 6147 .g2_irqs = 10, 6148 .atu_move_port_mask = 0xf, 6149 .pvt = true, 6150 .multi_chip = true, 6151 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6152 .ops = &mv88e6350_ops, 6153 }, 6154 6155 [MV88E6351] = { 6156 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6157 .family = MV88E6XXX_FAMILY_6351, 6158 .name = "Marvell 88E6351", 6159 .num_databases = 4096, 6160 .num_macs = 8192, 6161 .num_ports = 7, 6162 .num_internal_phys = 5, 6163 .max_vid = 4095, 6164 .max_sid = 63, 6165 .port_base_addr = 0x10, 6166 .phy_base_addr = 0x0, 6167 .global1_addr = 0x1b, 6168 .global2_addr = 0x1c, 6169 .age_time_coeff = 15000, 6170 .g1_irqs = 9, 6171 .g2_irqs = 10, 6172 .atu_move_port_mask = 0xf, 6173 .pvt = true, 6174 .multi_chip = true, 6175 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6176 .ops = &mv88e6351_ops, 6177 }, 6178 6179 [MV88E6352] = { 6180 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6181 .family = MV88E6XXX_FAMILY_6352, 6182 .name = "Marvell 88E6352", 6183 .num_databases = 4096, 6184 .num_macs = 8192, 6185 .num_ports = 7, 6186 .num_internal_phys = 5, 6187 .num_gpio = 15, 6188 .max_vid = 4095, 6189 .max_sid = 63, 6190 .port_base_addr = 0x10, 6191 .phy_base_addr = 0x0, 6192 .global1_addr = 0x1b, 6193 .global2_addr = 0x1c, 6194 .age_time_coeff = 15000, 6195 .g1_irqs = 9, 6196 .g2_irqs = 10, 6197 .atu_move_port_mask = 0xf, 6198 .pvt = true, 6199 .multi_chip = true, 6200 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6201 .ptp_support = true, 6202 .ops = &mv88e6352_ops, 6203 }, 6204 [MV88E6390] = { 6205 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6206 .family = MV88E6XXX_FAMILY_6390, 6207 .name = "Marvell 88E6390", 6208 .num_databases = 4096, 6209 .num_macs = 16384, 6210 .num_ports = 11, /* 10 + Z80 */ 6211 .num_internal_phys = 9, 6212 .num_gpio = 16, 6213 .max_vid = 8191, 6214 .max_sid = 63, 6215 .port_base_addr = 0x0, 6216 .phy_base_addr = 0x0, 6217 .global1_addr = 0x1b, 6218 .global2_addr = 0x1c, 6219 .age_time_coeff = 3750, 6220 .g1_irqs = 9, 6221 .g2_irqs = 14, 6222 .atu_move_port_mask = 0x1f, 6223 .pvt = true, 6224 .multi_chip = true, 6225 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6226 .ptp_support = true, 6227 .ops = &mv88e6390_ops, 6228 }, 6229 [MV88E6390X] = { 6230 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6231 .family = MV88E6XXX_FAMILY_6390, 6232 .name = "Marvell 88E6390X", 6233 .num_databases = 4096, 6234 .num_macs = 16384, 6235 .num_ports = 11, /* 10 + Z80 */ 6236 .num_internal_phys = 9, 6237 .num_gpio = 16, 6238 .max_vid = 8191, 6239 .max_sid = 63, 6240 .port_base_addr = 0x0, 6241 .phy_base_addr = 0x0, 6242 .global1_addr = 0x1b, 6243 .global2_addr = 0x1c, 6244 .age_time_coeff = 3750, 6245 .g1_irqs = 9, 6246 .g2_irqs = 14, 6247 .atu_move_port_mask = 0x1f, 6248 .pvt = true, 6249 .multi_chip = true, 6250 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6251 .ptp_support = true, 6252 .ops = &mv88e6390x_ops, 6253 }, 6254 6255 [MV88E6393X] = { 6256 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6257 .family = MV88E6XXX_FAMILY_6393, 6258 .name = "Marvell 88E6393X", 6259 .num_databases = 4096, 6260 .num_ports = 11, /* 10 + Z80 */ 6261 .num_internal_phys = 9, 6262 .max_vid = 8191, 6263 .max_sid = 63, 6264 .port_base_addr = 0x0, 6265 .phy_base_addr = 0x0, 6266 .global1_addr = 0x1b, 6267 .global2_addr = 0x1c, 6268 .age_time_coeff = 3750, 6269 .g1_irqs = 10, 6270 .g2_irqs = 14, 6271 .atu_move_port_mask = 0x1f, 6272 .pvt = true, 6273 .multi_chip = true, 6274 .ptp_support = true, 6275 .ops = &mv88e6393x_ops, 6276 }, 6277 }; 6278 6279 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6280 { 6281 int i; 6282 6283 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6284 if (mv88e6xxx_table[i].prod_num == prod_num) 6285 return &mv88e6xxx_table[i]; 6286 6287 return NULL; 6288 } 6289 6290 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6291 { 6292 const struct mv88e6xxx_info *info; 6293 unsigned int prod_num, rev; 6294 u16 id; 6295 int err; 6296 6297 mv88e6xxx_reg_lock(chip); 6298 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6299 mv88e6xxx_reg_unlock(chip); 6300 if (err) 6301 return err; 6302 6303 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6304 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6305 6306 info = mv88e6xxx_lookup_info(prod_num); 6307 if (!info) 6308 return -ENODEV; 6309 6310 /* Update the compatible info with the probed one */ 6311 chip->info = info; 6312 6313 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6314 chip->info->prod_num, chip->info->name, rev); 6315 6316 return 0; 6317 } 6318 6319 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6320 struct mdio_device *mdiodev) 6321 { 6322 int err; 6323 6324 /* dual_chip takes precedence over single/multi-chip modes */ 6325 if (chip->info->dual_chip) 6326 return -EINVAL; 6327 6328 /* If the mdio addr is 16 indicating the first port address of a switch 6329 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6330 * configured in single chip addressing mode. Setup the smi access as 6331 * single chip addressing mode and attempt to detect the model of the 6332 * switch, if this fails the device is not configured in single chip 6333 * addressing mode. 6334 */ 6335 if (mdiodev->addr != 16) 6336 return -EINVAL; 6337 6338 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6339 if (err) 6340 return err; 6341 6342 return mv88e6xxx_detect(chip); 6343 } 6344 6345 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6346 { 6347 struct mv88e6xxx_chip *chip; 6348 6349 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6350 if (!chip) 6351 return NULL; 6352 6353 chip->dev = dev; 6354 6355 mutex_init(&chip->reg_lock); 6356 INIT_LIST_HEAD(&chip->mdios); 6357 idr_init(&chip->policies); 6358 INIT_LIST_HEAD(&chip->msts); 6359 6360 return chip; 6361 } 6362 6363 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6364 int port, 6365 enum dsa_tag_protocol m) 6366 { 6367 struct mv88e6xxx_chip *chip = ds->priv; 6368 6369 return chip->tag_protocol; 6370 } 6371 6372 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6373 enum dsa_tag_protocol proto) 6374 { 6375 struct mv88e6xxx_chip *chip = ds->priv; 6376 enum dsa_tag_protocol old_protocol; 6377 struct dsa_port *cpu_dp; 6378 int err; 6379 6380 switch (proto) { 6381 case DSA_TAG_PROTO_EDSA: 6382 switch (chip->info->edsa_support) { 6383 case MV88E6XXX_EDSA_UNSUPPORTED: 6384 return -EPROTONOSUPPORT; 6385 case MV88E6XXX_EDSA_UNDOCUMENTED: 6386 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6387 fallthrough; 6388 case MV88E6XXX_EDSA_SUPPORTED: 6389 break; 6390 } 6391 break; 6392 case DSA_TAG_PROTO_DSA: 6393 break; 6394 default: 6395 return -EPROTONOSUPPORT; 6396 } 6397 6398 old_protocol = chip->tag_protocol; 6399 chip->tag_protocol = proto; 6400 6401 mv88e6xxx_reg_lock(chip); 6402 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6403 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6404 if (err) { 6405 mv88e6xxx_reg_unlock(chip); 6406 goto unwind; 6407 } 6408 } 6409 mv88e6xxx_reg_unlock(chip); 6410 6411 return 0; 6412 6413 unwind: 6414 chip->tag_protocol = old_protocol; 6415 6416 mv88e6xxx_reg_lock(chip); 6417 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6418 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6419 mv88e6xxx_reg_unlock(chip); 6420 6421 return err; 6422 } 6423 6424 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6425 const struct switchdev_obj_port_mdb *mdb, 6426 struct dsa_db db) 6427 { 6428 struct mv88e6xxx_chip *chip = ds->priv; 6429 int err; 6430 6431 mv88e6xxx_reg_lock(chip); 6432 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6433 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6434 mv88e6xxx_reg_unlock(chip); 6435 6436 return err; 6437 } 6438 6439 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6440 const struct switchdev_obj_port_mdb *mdb, 6441 struct dsa_db db) 6442 { 6443 struct mv88e6xxx_chip *chip = ds->priv; 6444 int err; 6445 6446 mv88e6xxx_reg_lock(chip); 6447 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6448 mv88e6xxx_reg_unlock(chip); 6449 6450 return err; 6451 } 6452 6453 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6454 struct dsa_mall_mirror_tc_entry *mirror, 6455 bool ingress, 6456 struct netlink_ext_ack *extack) 6457 { 6458 enum mv88e6xxx_egress_direction direction = ingress ? 6459 MV88E6XXX_EGRESS_DIR_INGRESS : 6460 MV88E6XXX_EGRESS_DIR_EGRESS; 6461 struct mv88e6xxx_chip *chip = ds->priv; 6462 bool other_mirrors = false; 6463 int i; 6464 int err; 6465 6466 mutex_lock(&chip->reg_lock); 6467 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6468 mirror->to_local_port) { 6469 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6470 other_mirrors |= ingress ? 6471 chip->ports[i].mirror_ingress : 6472 chip->ports[i].mirror_egress; 6473 6474 /* Can't change egress port when other mirror is active */ 6475 if (other_mirrors) { 6476 err = -EBUSY; 6477 goto out; 6478 } 6479 6480 err = mv88e6xxx_set_egress_port(chip, direction, 6481 mirror->to_local_port); 6482 if (err) 6483 goto out; 6484 } 6485 6486 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6487 out: 6488 mutex_unlock(&chip->reg_lock); 6489 6490 return err; 6491 } 6492 6493 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6494 struct dsa_mall_mirror_tc_entry *mirror) 6495 { 6496 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6497 MV88E6XXX_EGRESS_DIR_INGRESS : 6498 MV88E6XXX_EGRESS_DIR_EGRESS; 6499 struct mv88e6xxx_chip *chip = ds->priv; 6500 bool other_mirrors = false; 6501 int i; 6502 6503 mutex_lock(&chip->reg_lock); 6504 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6505 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6506 6507 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6508 other_mirrors |= mirror->ingress ? 6509 chip->ports[i].mirror_ingress : 6510 chip->ports[i].mirror_egress; 6511 6512 /* Reset egress port when no other mirror is active */ 6513 if (!other_mirrors) { 6514 if (mv88e6xxx_set_egress_port(chip, direction, 6515 dsa_upstream_port(ds, port))) 6516 dev_err(ds->dev, "failed to set egress port\n"); 6517 } 6518 6519 mutex_unlock(&chip->reg_lock); 6520 } 6521 6522 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6523 struct switchdev_brport_flags flags, 6524 struct netlink_ext_ack *extack) 6525 { 6526 struct mv88e6xxx_chip *chip = ds->priv; 6527 const struct mv88e6xxx_ops *ops; 6528 6529 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6530 BR_BCAST_FLOOD | BR_PORT_LOCKED)) 6531 return -EINVAL; 6532 6533 ops = chip->info->ops; 6534 6535 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6536 return -EINVAL; 6537 6538 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6539 return -EINVAL; 6540 6541 return 0; 6542 } 6543 6544 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6545 struct switchdev_brport_flags flags, 6546 struct netlink_ext_ack *extack) 6547 { 6548 struct mv88e6xxx_chip *chip = ds->priv; 6549 int err = -EOPNOTSUPP; 6550 6551 mv88e6xxx_reg_lock(chip); 6552 6553 if (flags.mask & BR_LEARNING) { 6554 bool learning = !!(flags.val & BR_LEARNING); 6555 u16 pav = learning ? (1 << port) : 0; 6556 6557 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6558 if (err) 6559 goto out; 6560 } 6561 6562 if (flags.mask & BR_FLOOD) { 6563 bool unicast = !!(flags.val & BR_FLOOD); 6564 6565 err = chip->info->ops->port_set_ucast_flood(chip, port, 6566 unicast); 6567 if (err) 6568 goto out; 6569 } 6570 6571 if (flags.mask & BR_MCAST_FLOOD) { 6572 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6573 6574 err = chip->info->ops->port_set_mcast_flood(chip, port, 6575 multicast); 6576 if (err) 6577 goto out; 6578 } 6579 6580 if (flags.mask & BR_BCAST_FLOOD) { 6581 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6582 6583 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6584 if (err) 6585 goto out; 6586 } 6587 6588 if (flags.mask & BR_PORT_LOCKED) { 6589 bool locked = !!(flags.val & BR_PORT_LOCKED); 6590 6591 err = mv88e6xxx_port_set_lock(chip, port, locked); 6592 if (err) 6593 goto out; 6594 } 6595 out: 6596 mv88e6xxx_reg_unlock(chip); 6597 6598 return err; 6599 } 6600 6601 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6602 struct dsa_lag lag, 6603 struct netdev_lag_upper_info *info, 6604 struct netlink_ext_ack *extack) 6605 { 6606 struct mv88e6xxx_chip *chip = ds->priv; 6607 struct dsa_port *dp; 6608 int members = 0; 6609 6610 if (!mv88e6xxx_has_lag(chip)) { 6611 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6612 return false; 6613 } 6614 6615 if (!lag.id) 6616 return false; 6617 6618 dsa_lag_foreach_port(dp, ds->dst, &lag) 6619 /* Includes the port joining the LAG */ 6620 members++; 6621 6622 if (members > 8) { 6623 NL_SET_ERR_MSG_MOD(extack, 6624 "Cannot offload more than 8 LAG ports"); 6625 return false; 6626 } 6627 6628 /* We could potentially relax this to include active 6629 * backup in the future. 6630 */ 6631 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6632 NL_SET_ERR_MSG_MOD(extack, 6633 "Can only offload LAG using hash TX type"); 6634 return false; 6635 } 6636 6637 /* Ideally we would also validate that the hash type matches 6638 * the hardware. Alas, this is always set to unknown on team 6639 * interfaces. 6640 */ 6641 return true; 6642 } 6643 6644 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6645 { 6646 struct mv88e6xxx_chip *chip = ds->priv; 6647 struct dsa_port *dp; 6648 u16 map = 0; 6649 int id; 6650 6651 /* DSA LAG IDs are one-based, hardware is zero-based */ 6652 id = lag.id - 1; 6653 6654 /* Build the map of all ports to distribute flows destined for 6655 * this LAG. This can be either a local user port, or a DSA 6656 * port if the LAG port is on a remote chip. 6657 */ 6658 dsa_lag_foreach_port(dp, ds->dst, &lag) 6659 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6660 6661 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6662 } 6663 6664 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6665 /* Row number corresponds to the number of active members in a 6666 * LAG. Each column states which of the eight hash buckets are 6667 * mapped to the column:th port in the LAG. 6668 * 6669 * Example: In a LAG with three active ports, the second port 6670 * ([2][1]) would be selected for traffic mapped to buckets 6671 * 3,4,5 (0x38). 6672 */ 6673 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6674 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6675 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6676 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6677 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6678 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6679 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6680 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6681 }; 6682 6683 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6684 int num_tx, int nth) 6685 { 6686 u8 active = 0; 6687 int i; 6688 6689 num_tx = num_tx <= 8 ? num_tx : 8; 6690 if (nth < num_tx) 6691 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6692 6693 for (i = 0; i < 8; i++) { 6694 if (BIT(i) & active) 6695 mask[i] |= BIT(port); 6696 } 6697 } 6698 6699 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6700 { 6701 struct mv88e6xxx_chip *chip = ds->priv; 6702 unsigned int id, num_tx; 6703 struct dsa_port *dp; 6704 struct dsa_lag *lag; 6705 int i, err, nth; 6706 u16 mask[8]; 6707 u16 ivec; 6708 6709 /* Assume no port is a member of any LAG. */ 6710 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6711 6712 /* Disable all masks for ports that _are_ members of a LAG. */ 6713 dsa_switch_for_each_port(dp, ds) { 6714 if (!dp->lag) 6715 continue; 6716 6717 ivec &= ~BIT(dp->index); 6718 } 6719 6720 for (i = 0; i < 8; i++) 6721 mask[i] = ivec; 6722 6723 /* Enable the correct subset of masks for all LAG ports that 6724 * are in the Tx set. 6725 */ 6726 dsa_lags_foreach_id(id, ds->dst) { 6727 lag = dsa_lag_by_id(ds->dst, id); 6728 if (!lag) 6729 continue; 6730 6731 num_tx = 0; 6732 dsa_lag_foreach_port(dp, ds->dst, lag) { 6733 if (dp->lag_tx_enabled) 6734 num_tx++; 6735 } 6736 6737 if (!num_tx) 6738 continue; 6739 6740 nth = 0; 6741 dsa_lag_foreach_port(dp, ds->dst, lag) { 6742 if (!dp->lag_tx_enabled) 6743 continue; 6744 6745 if (dp->ds == ds) 6746 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6747 num_tx, nth); 6748 6749 nth++; 6750 } 6751 } 6752 6753 for (i = 0; i < 8; i++) { 6754 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6755 if (err) 6756 return err; 6757 } 6758 6759 return 0; 6760 } 6761 6762 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6763 struct dsa_lag lag) 6764 { 6765 int err; 6766 6767 err = mv88e6xxx_lag_sync_masks(ds); 6768 6769 if (!err) 6770 err = mv88e6xxx_lag_sync_map(ds, lag); 6771 6772 return err; 6773 } 6774 6775 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6776 { 6777 struct mv88e6xxx_chip *chip = ds->priv; 6778 int err; 6779 6780 mv88e6xxx_reg_lock(chip); 6781 err = mv88e6xxx_lag_sync_masks(ds); 6782 mv88e6xxx_reg_unlock(chip); 6783 return err; 6784 } 6785 6786 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6787 struct dsa_lag lag, 6788 struct netdev_lag_upper_info *info, 6789 struct netlink_ext_ack *extack) 6790 { 6791 struct mv88e6xxx_chip *chip = ds->priv; 6792 int err, id; 6793 6794 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6795 return -EOPNOTSUPP; 6796 6797 /* DSA LAG IDs are one-based */ 6798 id = lag.id - 1; 6799 6800 mv88e6xxx_reg_lock(chip); 6801 6802 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6803 if (err) 6804 goto err_unlock; 6805 6806 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6807 if (err) 6808 goto err_clear_trunk; 6809 6810 mv88e6xxx_reg_unlock(chip); 6811 return 0; 6812 6813 err_clear_trunk: 6814 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6815 err_unlock: 6816 mv88e6xxx_reg_unlock(chip); 6817 return err; 6818 } 6819 6820 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6821 struct dsa_lag lag) 6822 { 6823 struct mv88e6xxx_chip *chip = ds->priv; 6824 int err_sync, err_trunk; 6825 6826 mv88e6xxx_reg_lock(chip); 6827 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6828 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6829 mv88e6xxx_reg_unlock(chip); 6830 return err_sync ? : err_trunk; 6831 } 6832 6833 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6834 int port) 6835 { 6836 struct mv88e6xxx_chip *chip = ds->priv; 6837 int err; 6838 6839 mv88e6xxx_reg_lock(chip); 6840 err = mv88e6xxx_lag_sync_masks(ds); 6841 mv88e6xxx_reg_unlock(chip); 6842 return err; 6843 } 6844 6845 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6846 int port, struct dsa_lag lag, 6847 struct netdev_lag_upper_info *info, 6848 struct netlink_ext_ack *extack) 6849 { 6850 struct mv88e6xxx_chip *chip = ds->priv; 6851 int err; 6852 6853 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6854 return -EOPNOTSUPP; 6855 6856 mv88e6xxx_reg_lock(chip); 6857 6858 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6859 if (err) 6860 goto unlock; 6861 6862 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6863 6864 unlock: 6865 mv88e6xxx_reg_unlock(chip); 6866 return err; 6867 } 6868 6869 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6870 int port, struct dsa_lag lag) 6871 { 6872 struct mv88e6xxx_chip *chip = ds->priv; 6873 int err_sync, err_pvt; 6874 6875 mv88e6xxx_reg_lock(chip); 6876 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6877 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6878 mv88e6xxx_reg_unlock(chip); 6879 return err_sync ? : err_pvt; 6880 } 6881 6882 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6883 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6884 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6885 .setup = mv88e6xxx_setup, 6886 .teardown = mv88e6xxx_teardown, 6887 .port_setup = mv88e6xxx_port_setup, 6888 .port_teardown = mv88e6xxx_port_teardown, 6889 .phylink_get_caps = mv88e6xxx_get_caps, 6890 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6891 .phylink_mac_config = mv88e6xxx_mac_config, 6892 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6893 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6894 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6895 .get_strings = mv88e6xxx_get_strings, 6896 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6897 .get_sset_count = mv88e6xxx_get_sset_count, 6898 .port_enable = mv88e6xxx_port_enable, 6899 .port_disable = mv88e6xxx_port_disable, 6900 .port_max_mtu = mv88e6xxx_get_max_mtu, 6901 .port_change_mtu = mv88e6xxx_change_mtu, 6902 .get_mac_eee = mv88e6xxx_get_mac_eee, 6903 .set_mac_eee = mv88e6xxx_set_mac_eee, 6904 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6905 .get_eeprom = mv88e6xxx_get_eeprom, 6906 .set_eeprom = mv88e6xxx_set_eeprom, 6907 .get_regs_len = mv88e6xxx_get_regs_len, 6908 .get_regs = mv88e6xxx_get_regs, 6909 .get_rxnfc = mv88e6xxx_get_rxnfc, 6910 .set_rxnfc = mv88e6xxx_set_rxnfc, 6911 .set_ageing_time = mv88e6xxx_set_ageing_time, 6912 .port_bridge_join = mv88e6xxx_port_bridge_join, 6913 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6914 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6915 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6916 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6917 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6918 .port_fast_age = mv88e6xxx_port_fast_age, 6919 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6920 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6921 .port_vlan_add = mv88e6xxx_port_vlan_add, 6922 .port_vlan_del = mv88e6xxx_port_vlan_del, 6923 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6924 .port_fdb_add = mv88e6xxx_port_fdb_add, 6925 .port_fdb_del = mv88e6xxx_port_fdb_del, 6926 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6927 .port_mdb_add = mv88e6xxx_port_mdb_add, 6928 .port_mdb_del = mv88e6xxx_port_mdb_del, 6929 .port_mirror_add = mv88e6xxx_port_mirror_add, 6930 .port_mirror_del = mv88e6xxx_port_mirror_del, 6931 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6932 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6933 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6934 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6935 .port_txtstamp = mv88e6xxx_port_txtstamp, 6936 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6937 .get_ts_info = mv88e6xxx_get_ts_info, 6938 .devlink_param_get = mv88e6xxx_devlink_param_get, 6939 .devlink_param_set = mv88e6xxx_devlink_param_set, 6940 .devlink_info_get = mv88e6xxx_devlink_info_get, 6941 .port_lag_change = mv88e6xxx_port_lag_change, 6942 .port_lag_join = mv88e6xxx_port_lag_join, 6943 .port_lag_leave = mv88e6xxx_port_lag_leave, 6944 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6945 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6946 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6947 }; 6948 6949 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6950 { 6951 struct device *dev = chip->dev; 6952 struct dsa_switch *ds; 6953 6954 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6955 if (!ds) 6956 return -ENOMEM; 6957 6958 ds->dev = dev; 6959 ds->num_ports = mv88e6xxx_num_ports(chip); 6960 ds->priv = chip; 6961 ds->dev = dev; 6962 ds->ops = &mv88e6xxx_switch_ops; 6963 ds->ageing_time_min = chip->info->age_time_coeff; 6964 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6965 6966 /* Some chips support up to 32, but that requires enabling the 6967 * 5-bit port mode, which we do not support. 640k^W16 ought to 6968 * be enough for anyone. 6969 */ 6970 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6971 6972 dev_set_drvdata(dev, ds); 6973 6974 return dsa_register_switch(ds); 6975 } 6976 6977 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6978 { 6979 dsa_unregister_switch(chip->ds); 6980 } 6981 6982 static const void *pdata_device_get_match_data(struct device *dev) 6983 { 6984 const struct of_device_id *matches = dev->driver->of_match_table; 6985 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6986 6987 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6988 matches++) { 6989 if (!strcmp(pdata->compatible, matches->compatible)) 6990 return matches->data; 6991 } 6992 return NULL; 6993 } 6994 6995 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6996 * would be lost after a power cycle so prevent it to be suspended. 6997 */ 6998 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6999 { 7000 return -EOPNOTSUPP; 7001 } 7002 7003 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7004 { 7005 return 0; 7006 } 7007 7008 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7009 7010 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7011 { 7012 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7013 const struct mv88e6xxx_info *compat_info = NULL; 7014 struct device *dev = &mdiodev->dev; 7015 struct device_node *np = dev->of_node; 7016 struct mv88e6xxx_chip *chip; 7017 int port; 7018 int err; 7019 7020 if (!np && !pdata) 7021 return -EINVAL; 7022 7023 if (np) 7024 compat_info = of_device_get_match_data(dev); 7025 7026 if (pdata) { 7027 compat_info = pdata_device_get_match_data(dev); 7028 7029 if (!pdata->netdev) 7030 return -EINVAL; 7031 7032 for (port = 0; port < DSA_MAX_PORTS; port++) { 7033 if (!(pdata->enabled_ports & (1 << port))) 7034 continue; 7035 if (strcmp(pdata->cd.port_names[port], "cpu")) 7036 continue; 7037 pdata->cd.netdev[port] = &pdata->netdev->dev; 7038 break; 7039 } 7040 } 7041 7042 if (!compat_info) 7043 return -EINVAL; 7044 7045 chip = mv88e6xxx_alloc_chip(dev); 7046 if (!chip) { 7047 err = -ENOMEM; 7048 goto out; 7049 } 7050 7051 chip->info = compat_info; 7052 7053 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7054 if (IS_ERR(chip->reset)) { 7055 err = PTR_ERR(chip->reset); 7056 goto out; 7057 } 7058 if (chip->reset) 7059 usleep_range(1000, 2000); 7060 7061 /* Detect if the device is configured in single chip addressing mode, 7062 * otherwise continue with address specific smi init/detection. 7063 */ 7064 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7065 if (err) { 7066 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7067 if (err) 7068 goto out; 7069 7070 err = mv88e6xxx_detect(chip); 7071 if (err) 7072 goto out; 7073 } 7074 7075 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7076 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7077 else 7078 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7079 7080 mv88e6xxx_phy_init(chip); 7081 7082 if (chip->info->ops->get_eeprom) { 7083 if (np) 7084 of_property_read_u32(np, "eeprom-length", 7085 &chip->eeprom_len); 7086 else 7087 chip->eeprom_len = pdata->eeprom_len; 7088 } 7089 7090 mv88e6xxx_reg_lock(chip); 7091 err = mv88e6xxx_switch_reset(chip); 7092 mv88e6xxx_reg_unlock(chip); 7093 if (err) 7094 goto out; 7095 7096 if (np) { 7097 chip->irq = of_irq_get(np, 0); 7098 if (chip->irq == -EPROBE_DEFER) { 7099 err = chip->irq; 7100 goto out; 7101 } 7102 } 7103 7104 if (pdata) 7105 chip->irq = pdata->irq; 7106 7107 /* Has to be performed before the MDIO bus is created, because 7108 * the PHYs will link their interrupts to these interrupt 7109 * controllers 7110 */ 7111 mv88e6xxx_reg_lock(chip); 7112 if (chip->irq > 0) 7113 err = mv88e6xxx_g1_irq_setup(chip); 7114 else 7115 err = mv88e6xxx_irq_poll_setup(chip); 7116 mv88e6xxx_reg_unlock(chip); 7117 7118 if (err) 7119 goto out; 7120 7121 if (chip->info->g2_irqs > 0) { 7122 err = mv88e6xxx_g2_irq_setup(chip); 7123 if (err) 7124 goto out_g1_irq; 7125 } 7126 7127 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7128 if (err) 7129 goto out_g2_irq; 7130 7131 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7132 if (err) 7133 goto out_g1_atu_prob_irq; 7134 7135 err = mv88e6xxx_mdios_register(chip, np); 7136 if (err) 7137 goto out_g1_vtu_prob_irq; 7138 7139 err = mv88e6xxx_register_switch(chip); 7140 if (err) 7141 goto out_mdio; 7142 7143 return 0; 7144 7145 out_mdio: 7146 mv88e6xxx_mdios_unregister(chip); 7147 out_g1_vtu_prob_irq: 7148 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7149 out_g1_atu_prob_irq: 7150 mv88e6xxx_g1_atu_prob_irq_free(chip); 7151 out_g2_irq: 7152 if (chip->info->g2_irqs > 0) 7153 mv88e6xxx_g2_irq_free(chip); 7154 out_g1_irq: 7155 if (chip->irq > 0) 7156 mv88e6xxx_g1_irq_free(chip); 7157 else 7158 mv88e6xxx_irq_poll_free(chip); 7159 out: 7160 if (pdata) 7161 dev_put(pdata->netdev); 7162 7163 return err; 7164 } 7165 7166 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7167 { 7168 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7169 struct mv88e6xxx_chip *chip; 7170 7171 if (!ds) 7172 return; 7173 7174 chip = ds->priv; 7175 7176 if (chip->info->ptp_support) { 7177 mv88e6xxx_hwtstamp_free(chip); 7178 mv88e6xxx_ptp_free(chip); 7179 } 7180 7181 mv88e6xxx_phy_destroy(chip); 7182 mv88e6xxx_unregister_switch(chip); 7183 mv88e6xxx_mdios_unregister(chip); 7184 7185 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7186 mv88e6xxx_g1_atu_prob_irq_free(chip); 7187 7188 if (chip->info->g2_irqs > 0) 7189 mv88e6xxx_g2_irq_free(chip); 7190 7191 if (chip->irq > 0) 7192 mv88e6xxx_g1_irq_free(chip); 7193 else 7194 mv88e6xxx_irq_poll_free(chip); 7195 } 7196 7197 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7198 { 7199 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7200 7201 if (!ds) 7202 return; 7203 7204 dsa_switch_shutdown(ds); 7205 7206 dev_set_drvdata(&mdiodev->dev, NULL); 7207 } 7208 7209 static const struct of_device_id mv88e6xxx_of_match[] = { 7210 { 7211 .compatible = "marvell,mv88e6085", 7212 .data = &mv88e6xxx_table[MV88E6085], 7213 }, 7214 { 7215 .compatible = "marvell,mv88e6190", 7216 .data = &mv88e6xxx_table[MV88E6190], 7217 }, 7218 { 7219 .compatible = "marvell,mv88e6250", 7220 .data = &mv88e6xxx_table[MV88E6250], 7221 }, 7222 { /* sentinel */ }, 7223 }; 7224 7225 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7226 7227 static struct mdio_driver mv88e6xxx_driver = { 7228 .probe = mv88e6xxx_probe, 7229 .remove = mv88e6xxx_remove, 7230 .shutdown = mv88e6xxx_shutdown, 7231 .mdiodrv.driver = { 7232 .name = "mv88e6085", 7233 .of_match_table = mv88e6xxx_of_match, 7234 .pm = &mv88e6xxx_pm_ops, 7235 }, 7236 }; 7237 7238 mdio_module_driver(mv88e6xxx_driver); 7239 7240 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7241 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7242 MODULE_LICENSE("GPL"); 7243