1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "devlink.h" 36 #include "global1.h" 37 #include "global2.h" 38 #include "hwtstamp.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "ptp.h" 42 #include "serdes.h" 43 #include "smi.h" 44 45 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 46 { 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 48 dev_err(chip->dev, "Switch registers lock not held!\n"); 49 dump_stack(); 50 } 51 } 52 53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 54 { 55 int err; 56 57 assert_reg_lock(chip); 58 59 err = mv88e6xxx_smi_read(chip, addr, reg, val); 60 if (err) 61 return err; 62 63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 64 addr, reg, *val); 65 66 return 0; 67 } 68 69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 70 { 71 int err; 72 73 assert_reg_lock(chip); 74 75 err = mv88e6xxx_smi_write(chip, addr, reg, val); 76 if (err) 77 return err; 78 79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 80 addr, reg, val); 81 82 return 0; 83 } 84 85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 86 u16 mask, u16 val) 87 { 88 u16 data; 89 int err; 90 int i; 91 92 /* There's no bus specific operation to wait for a mask */ 93 for (i = 0; i < 16; i++) { 94 err = mv88e6xxx_read(chip, addr, reg, &data); 95 if (err) 96 return err; 97 98 if ((data & mask) == val) 99 return 0; 100 101 usleep_range(1000, 2000); 102 } 103 104 dev_err(chip->dev, "Timeout while waiting for switch\n"); 105 return -ETIMEDOUT; 106 } 107 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 109 int bit, int val) 110 { 111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 112 val ? BIT(bit) : 0x0000); 113 } 114 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 116 { 117 struct mv88e6xxx_mdio_bus *mdio_bus; 118 119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 120 list); 121 if (!mdio_bus) 122 return NULL; 123 124 return mdio_bus->bus; 125 } 126 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 128 { 129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 130 unsigned int n = d->hwirq; 131 132 chip->g1_irq.masked |= (1 << n); 133 } 134 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked &= ~(1 << n); 141 } 142 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 144 { 145 unsigned int nhandled = 0; 146 unsigned int sub_irq; 147 unsigned int n; 148 u16 reg; 149 u16 ctl1; 150 int err; 151 152 mv88e6xxx_reg_lock(chip); 153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 154 mv88e6xxx_reg_unlock(chip); 155 156 if (err) 157 goto out; 158 159 do { 160 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 161 if (reg & (1 << n)) { 162 sub_irq = irq_find_mapping(chip->g1_irq.domain, 163 n); 164 handle_nested_irq(sub_irq); 165 ++nhandled; 166 } 167 } 168 169 mv88e6xxx_reg_lock(chip); 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 171 if (err) 172 goto unlock; 173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 174 unlock: 175 mv88e6xxx_reg_unlock(chip); 176 if (err) 177 goto out; 178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 179 } while (reg & ctl1); 180 181 out: 182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 183 } 184 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 186 { 187 struct mv88e6xxx_chip *chip = dev_id; 188 189 return mv88e6xxx_g1_irq_thread_work(chip); 190 } 191 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 193 { 194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 195 196 mv88e6xxx_reg_lock(chip); 197 } 198 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 200 { 201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 203 u16 reg; 204 int err; 205 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 207 if (err) 208 goto out; 209 210 reg &= ~mask; 211 reg |= (~chip->g1_irq.masked & mask); 212 213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 214 if (err) 215 goto out; 216 217 out: 218 mv88e6xxx_reg_unlock(chip); 219 } 220 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 222 .name = "mv88e6xxx-g1", 223 .irq_mask = mv88e6xxx_g1_irq_mask, 224 .irq_unmask = mv88e6xxx_g1_irq_unmask, 225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 227 }; 228 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 230 unsigned int irq, 231 irq_hw_number_t hwirq) 232 { 233 struct mv88e6xxx_chip *chip = d->host_data; 234 235 irq_set_chip_data(irq, d->host_data); 236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 237 irq_set_noprobe(irq); 238 239 return 0; 240 } 241 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 243 .map = mv88e6xxx_g1_irq_domain_map, 244 .xlate = irq_domain_xlate_twocell, 245 }; 246 247 /* To be called with reg_lock held */ 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 249 { 250 int irq, virq; 251 u16 mask; 252 253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 256 257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 258 virq = irq_find_mapping(chip->g1_irq.domain, irq); 259 irq_dispose_mapping(virq); 260 } 261 262 irq_domain_remove(chip->g1_irq.domain); 263 } 264 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 266 { 267 /* 268 * free_irq must be called without reg_lock taken because the irq 269 * handler takes this lock, too. 270 */ 271 free_irq(chip->irq, chip); 272 273 mv88e6xxx_reg_lock(chip); 274 mv88e6xxx_g1_irq_free_common(chip); 275 mv88e6xxx_reg_unlock(chip); 276 } 277 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 279 { 280 int err, irq, virq; 281 u16 reg, mask; 282 283 chip->g1_irq.nirqs = chip->info->g1_irqs; 284 chip->g1_irq.domain = irq_domain_add_simple( 285 NULL, chip->g1_irq.nirqs, 0, 286 &mv88e6xxx_g1_irq_domain_ops, chip); 287 if (!chip->g1_irq.domain) 288 return -ENOMEM; 289 290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 291 irq_create_mapping(chip->g1_irq.domain, irq); 292 293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 294 chip->g1_irq.masked = ~0; 295 296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 297 if (err) 298 goto out_mapping; 299 300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 303 if (err) 304 goto out_disable; 305 306 /* Reading the interrupt status clears (most of) them */ 307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 308 if (err) 309 goto out_disable; 310 311 return 0; 312 313 out_disable: 314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 316 317 out_mapping: 318 for (irq = 0; irq < 16; irq++) { 319 virq = irq_find_mapping(chip->g1_irq.domain, irq); 320 irq_dispose_mapping(virq); 321 } 322 323 irq_domain_remove(chip->g1_irq.domain); 324 325 return err; 326 } 327 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 329 { 330 static struct lock_class_key lock_key; 331 static struct lock_class_key request_key; 332 int err; 333 334 err = mv88e6xxx_g1_irq_setup_common(chip); 335 if (err) 336 return err; 337 338 /* These lock classes tells lockdep that global 1 irqs are in 339 * a different category than their parent GPIO, so it won't 340 * report false recursion. 341 */ 342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 343 344 snprintf(chip->irq_name, sizeof(chip->irq_name), 345 "mv88e6xxx-%s", dev_name(chip->dev)); 346 347 mv88e6xxx_reg_unlock(chip); 348 err = request_threaded_irq(chip->irq, NULL, 349 mv88e6xxx_g1_irq_thread_fn, 350 IRQF_ONESHOT | IRQF_SHARED, 351 chip->irq_name, chip); 352 mv88e6xxx_reg_lock(chip); 353 if (err) 354 mv88e6xxx_g1_irq_free_common(chip); 355 356 return err; 357 } 358 359 static void mv88e6xxx_irq_poll(struct kthread_work *work) 360 { 361 struct mv88e6xxx_chip *chip = container_of(work, 362 struct mv88e6xxx_chip, 363 irq_poll_work.work); 364 mv88e6xxx_g1_irq_thread_work(chip); 365 366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 367 msecs_to_jiffies(100)); 368 } 369 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 371 { 372 int err; 373 374 err = mv88e6xxx_g1_irq_setup_common(chip); 375 if (err) 376 return err; 377 378 kthread_init_delayed_work(&chip->irq_poll_work, 379 mv88e6xxx_irq_poll); 380 381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 382 if (IS_ERR(chip->kworker)) 383 return PTR_ERR(chip->kworker); 384 385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 386 msecs_to_jiffies(100)); 387 388 return 0; 389 } 390 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 392 { 393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 394 kthread_destroy_worker(chip->kworker); 395 396 mv88e6xxx_reg_lock(chip); 397 mv88e6xxx_g1_irq_free_common(chip); 398 mv88e6xxx_reg_unlock(chip); 399 } 400 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 402 int port, phy_interface_t interface) 403 { 404 int err; 405 406 if (chip->info->ops->port_set_rgmii_delay) { 407 err = chip->info->ops->port_set_rgmii_delay(chip, port, 408 interface); 409 if (err && err != -EOPNOTSUPP) 410 return err; 411 } 412 413 if (chip->info->ops->port_set_cmode) { 414 err = chip->info->ops->port_set_cmode(chip, port, 415 interface); 416 if (err && err != -EOPNOTSUPP) 417 return err; 418 } 419 420 return 0; 421 } 422 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 424 int link, int speed, int duplex, int pause, 425 phy_interface_t mode) 426 { 427 int err; 428 429 if (!chip->info->ops->port_set_link) 430 return 0; 431 432 /* Port's MAC control must not be changed unless the link is down */ 433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 434 if (err) 435 return err; 436 437 if (chip->info->ops->port_set_speed_duplex) { 438 err = chip->info->ops->port_set_speed_duplex(chip, port, 439 speed, duplex); 440 if (err && err != -EOPNOTSUPP) 441 goto restore_link; 442 } 443 444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 445 mode = chip->info->ops->port_max_speed_mode(port); 446 447 if (chip->info->ops->port_set_pause) { 448 err = chip->info->ops->port_set_pause(chip, port, pause); 449 if (err) 450 goto restore_link; 451 } 452 453 err = mv88e6xxx_port_config_interface(chip, port, mode); 454 restore_link: 455 if (chip->info->ops->port_set_link(chip, port, link)) 456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 457 458 return err; 459 } 460 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 462 { 463 struct mv88e6xxx_chip *chip = ds->priv; 464 465 return port < chip->info->num_internal_phys; 466 } 467 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 469 { 470 u16 reg; 471 int err; 472 473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 474 if (err) { 475 dev_err(chip->dev, 476 "p%d: %s: failed to read port status\n", 477 port, __func__); 478 return err; 479 } 480 481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 482 } 483 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 485 struct phylink_link_state *state) 486 { 487 struct mv88e6xxx_chip *chip = ds->priv; 488 int lane; 489 int err; 490 491 mv88e6xxx_reg_lock(chip); 492 lane = mv88e6xxx_serdes_get_lane(chip, port); 493 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 495 state); 496 else 497 err = -EOPNOTSUPP; 498 mv88e6xxx_reg_unlock(chip); 499 500 return err; 501 } 502 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 504 unsigned int mode, 505 phy_interface_t interface, 506 const unsigned long *advertise) 507 { 508 const struct mv88e6xxx_ops *ops = chip->info->ops; 509 int lane; 510 511 if (ops->serdes_pcs_config) { 512 lane = mv88e6xxx_serdes_get_lane(chip, port); 513 if (lane >= 0) 514 return ops->serdes_pcs_config(chip, port, lane, mode, 515 interface, advertise); 516 } 517 518 return 0; 519 } 520 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 522 { 523 struct mv88e6xxx_chip *chip = ds->priv; 524 const struct mv88e6xxx_ops *ops; 525 int err = 0; 526 int lane; 527 528 ops = chip->info->ops; 529 530 if (ops->serdes_pcs_an_restart) { 531 mv88e6xxx_reg_lock(chip); 532 lane = mv88e6xxx_serdes_get_lane(chip, port); 533 if (lane >= 0) 534 err = ops->serdes_pcs_an_restart(chip, port, lane); 535 mv88e6xxx_reg_unlock(chip); 536 537 if (err) 538 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 539 } 540 } 541 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 543 unsigned int mode, 544 int speed, int duplex) 545 { 546 const struct mv88e6xxx_ops *ops = chip->info->ops; 547 int lane; 548 549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane >= 0) 552 return ops->serdes_pcs_link_up(chip, port, lane, 553 speed, duplex); 554 } 555 556 return 0; 557 } 558 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 560 unsigned long *mask, 561 struct phylink_link_state *state) 562 { 563 if (!phy_interface_mode_is_8023z(state->interface)) { 564 /* 10M and 100M are only supported in non-802.3z mode */ 565 phylink_set(mask, 10baseT_Half); 566 phylink_set(mask, 10baseT_Full); 567 phylink_set(mask, 100baseT_Half); 568 phylink_set(mask, 100baseT_Full); 569 } 570 } 571 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 573 unsigned long *mask, 574 struct phylink_link_state *state) 575 { 576 /* FIXME: if the port is in 1000Base-X mode, then it only supports 577 * 1000M FD speeds. In this case, CMODE will indicate 5. 578 */ 579 phylink_set(mask, 1000baseT_Full); 580 phylink_set(mask, 1000baseX_Full); 581 582 mv88e6065_phylink_validate(chip, port, mask, state); 583 } 584 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 586 unsigned long *mask, 587 struct phylink_link_state *state) 588 { 589 if (port >= 5) 590 phylink_set(mask, 2500baseX_Full); 591 592 /* No ethtool bits for 200Mbps */ 593 phylink_set(mask, 1000baseT_Full); 594 phylink_set(mask, 1000baseX_Full); 595 596 mv88e6065_phylink_validate(chip, port, mask, state); 597 } 598 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 600 unsigned long *mask, 601 struct phylink_link_state *state) 602 { 603 /* No ethtool bits for 200Mbps */ 604 phylink_set(mask, 1000baseT_Full); 605 phylink_set(mask, 1000baseX_Full); 606 607 mv88e6065_phylink_validate(chip, port, mask, state); 608 } 609 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 611 unsigned long *mask, 612 struct phylink_link_state *state) 613 { 614 if (port >= 9) { 615 phylink_set(mask, 2500baseX_Full); 616 phylink_set(mask, 2500baseT_Full); 617 } 618 619 /* No ethtool bits for 200Mbps */ 620 phylink_set(mask, 1000baseT_Full); 621 phylink_set(mask, 1000baseX_Full); 622 623 mv88e6065_phylink_validate(chip, port, mask, state); 624 } 625 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 627 unsigned long *mask, 628 struct phylink_link_state *state) 629 { 630 if (port >= 9) { 631 phylink_set(mask, 10000baseT_Full); 632 phylink_set(mask, 10000baseKR_Full); 633 } 634 635 mv88e6390_phylink_validate(chip, port, mask, state); 636 } 637 638 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 639 unsigned long *mask, 640 struct phylink_link_state *state) 641 { 642 if (port == 0 || port == 9 || port == 10) { 643 phylink_set(mask, 10000baseT_Full); 644 phylink_set(mask, 10000baseKR_Full); 645 phylink_set(mask, 10000baseCR_Full); 646 phylink_set(mask, 10000baseSR_Full); 647 phylink_set(mask, 10000baseLR_Full); 648 phylink_set(mask, 10000baseLRM_Full); 649 phylink_set(mask, 10000baseER_Full); 650 phylink_set(mask, 5000baseT_Full); 651 phylink_set(mask, 2500baseX_Full); 652 phylink_set(mask, 2500baseT_Full); 653 } 654 655 phylink_set(mask, 1000baseT_Full); 656 phylink_set(mask, 1000baseX_Full); 657 658 mv88e6065_phylink_validate(chip, port, mask, state); 659 } 660 661 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 662 unsigned long *supported, 663 struct phylink_link_state *state) 664 { 665 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 666 struct mv88e6xxx_chip *chip = ds->priv; 667 668 /* Allow all the expected bits */ 669 phylink_set(mask, Autoneg); 670 phylink_set(mask, Pause); 671 phylink_set_port_modes(mask); 672 673 if (chip->info->ops->phylink_validate) 674 chip->info->ops->phylink_validate(chip, port, mask, state); 675 676 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 677 bitmap_and(state->advertising, state->advertising, mask, 678 __ETHTOOL_LINK_MODE_MASK_NBITS); 679 680 /* We can only operate at 2500BaseX or 1000BaseX. If requested 681 * to advertise both, only report advertising at 2500BaseX. 682 */ 683 phylink_helper_basex_speed(state); 684 } 685 686 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 687 unsigned int mode, 688 const struct phylink_link_state *state) 689 { 690 struct mv88e6xxx_chip *chip = ds->priv; 691 struct mv88e6xxx_port *p; 692 int err; 693 694 p = &chip->ports[port]; 695 696 /* FIXME: is this the correct test? If we're in fixed mode on an 697 * internal port, why should we process this any different from 698 * PHY mode? On the other hand, the port may be automedia between 699 * an internal PHY and the serdes... 700 */ 701 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 702 return; 703 704 mv88e6xxx_reg_lock(chip); 705 /* In inband mode, the link may come up at any time while the link 706 * is not forced down. Force the link down while we reconfigure the 707 * interface mode. 708 */ 709 if (mode == MLO_AN_INBAND && p->interface != state->interface && 710 chip->info->ops->port_set_link) 711 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 712 713 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 714 if (err && err != -EOPNOTSUPP) 715 goto err_unlock; 716 717 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 718 state->advertising); 719 /* FIXME: we should restart negotiation if something changed - which 720 * is something we get if we convert to using phylinks PCS operations. 721 */ 722 if (err > 0) 723 err = 0; 724 725 /* Undo the forced down state above after completing configuration 726 * irrespective of its state on entry, which allows the link to come up. 727 */ 728 if (mode == MLO_AN_INBAND && p->interface != state->interface && 729 chip->info->ops->port_set_link) 730 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 731 732 p->interface = state->interface; 733 734 err_unlock: 735 mv88e6xxx_reg_unlock(chip); 736 737 if (err && err != -EOPNOTSUPP) 738 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 739 } 740 741 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 742 unsigned int mode, 743 phy_interface_t interface) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 const struct mv88e6xxx_ops *ops; 747 int err = 0; 748 749 ops = chip->info->ops; 750 751 mv88e6xxx_reg_lock(chip); 752 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 753 mode == MLO_AN_FIXED) && ops->port_sync_link) 754 err = ops->port_sync_link(chip, port, mode, false); 755 mv88e6xxx_reg_unlock(chip); 756 757 if (err) 758 dev_err(chip->dev, 759 "p%d: failed to force MAC link down\n", port); 760 } 761 762 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 763 unsigned int mode, phy_interface_t interface, 764 struct phy_device *phydev, 765 int speed, int duplex, 766 bool tx_pause, bool rx_pause) 767 { 768 struct mv88e6xxx_chip *chip = ds->priv; 769 const struct mv88e6xxx_ops *ops; 770 int err = 0; 771 772 ops = chip->info->ops; 773 774 mv88e6xxx_reg_lock(chip); 775 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 776 /* FIXME: for an automedia port, should we force the link 777 * down here - what if the link comes up due to "other" media 778 * while we're bringing the port up, how is the exclusivity 779 * handled in the Marvell hardware? E.g. port 2 on 88E6390 780 * shared between internal PHY and Serdes. 781 */ 782 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 783 duplex); 784 if (err) 785 goto error; 786 787 if (ops->port_set_speed_duplex) { 788 err = ops->port_set_speed_duplex(chip, port, 789 speed, duplex); 790 if (err && err != -EOPNOTSUPP) 791 goto error; 792 } 793 794 if (ops->port_sync_link) 795 err = ops->port_sync_link(chip, port, mode, true); 796 } 797 error: 798 mv88e6xxx_reg_unlock(chip); 799 800 if (err && err != -EOPNOTSUPP) 801 dev_err(ds->dev, 802 "p%d: failed to configure MAC link up\n", port); 803 } 804 805 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 806 { 807 if (!chip->info->ops->stats_snapshot) 808 return -EOPNOTSUPP; 809 810 return chip->info->ops->stats_snapshot(chip, port); 811 } 812 813 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 814 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 815 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 816 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 817 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 818 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 819 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 820 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 821 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 822 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 823 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 824 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 825 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 826 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 827 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 828 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 829 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 830 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 831 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 832 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 833 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 834 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 835 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 836 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 837 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 838 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 839 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 840 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 841 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 842 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 843 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 844 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 845 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 846 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 847 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 848 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 849 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 850 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 851 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 852 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 853 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 854 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 855 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 856 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 857 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 858 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 859 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 860 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 861 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 862 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 863 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 864 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 865 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 866 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 867 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 868 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 869 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 870 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 871 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 872 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 873 }; 874 875 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 876 struct mv88e6xxx_hw_stat *s, 877 int port, u16 bank1_select, 878 u16 histogram) 879 { 880 u32 low; 881 u32 high = 0; 882 u16 reg = 0; 883 int err; 884 u64 value; 885 886 switch (s->type) { 887 case STATS_TYPE_PORT: 888 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 889 if (err) 890 return U64_MAX; 891 892 low = reg; 893 if (s->size == 4) { 894 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 895 if (err) 896 return U64_MAX; 897 low |= ((u32)reg) << 16; 898 } 899 break; 900 case STATS_TYPE_BANK1: 901 reg = bank1_select; 902 fallthrough; 903 case STATS_TYPE_BANK0: 904 reg |= s->reg | histogram; 905 mv88e6xxx_g1_stats_read(chip, reg, &low); 906 if (s->size == 8) 907 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 908 break; 909 default: 910 return U64_MAX; 911 } 912 value = (((u64)high) << 32) | low; 913 return value; 914 } 915 916 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 917 uint8_t *data, int types) 918 { 919 struct mv88e6xxx_hw_stat *stat; 920 int i, j; 921 922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 923 stat = &mv88e6xxx_hw_stats[i]; 924 if (stat->type & types) { 925 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 926 ETH_GSTRING_LEN); 927 j++; 928 } 929 } 930 931 return j; 932 } 933 934 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 935 uint8_t *data) 936 { 937 return mv88e6xxx_stats_get_strings(chip, data, 938 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 939 } 940 941 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 942 uint8_t *data) 943 { 944 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 945 } 946 947 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 948 uint8_t *data) 949 { 950 return mv88e6xxx_stats_get_strings(chip, data, 951 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 952 } 953 954 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 955 "atu_member_violation", 956 "atu_miss_violation", 957 "atu_full_violation", 958 "vtu_member_violation", 959 "vtu_miss_violation", 960 }; 961 962 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 963 { 964 unsigned int i; 965 966 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 967 strlcpy(data + i * ETH_GSTRING_LEN, 968 mv88e6xxx_atu_vtu_stats_strings[i], 969 ETH_GSTRING_LEN); 970 } 971 972 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 973 u32 stringset, uint8_t *data) 974 { 975 struct mv88e6xxx_chip *chip = ds->priv; 976 int count = 0; 977 978 if (stringset != ETH_SS_STATS) 979 return; 980 981 mv88e6xxx_reg_lock(chip); 982 983 if (chip->info->ops->stats_get_strings) 984 count = chip->info->ops->stats_get_strings(chip, data); 985 986 if (chip->info->ops->serdes_get_strings) { 987 data += count * ETH_GSTRING_LEN; 988 count = chip->info->ops->serdes_get_strings(chip, port, data); 989 } 990 991 data += count * ETH_GSTRING_LEN; 992 mv88e6xxx_atu_vtu_get_strings(data); 993 994 mv88e6xxx_reg_unlock(chip); 995 } 996 997 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 998 int types) 999 { 1000 struct mv88e6xxx_hw_stat *stat; 1001 int i, j; 1002 1003 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1004 stat = &mv88e6xxx_hw_stats[i]; 1005 if (stat->type & types) 1006 j++; 1007 } 1008 return j; 1009 } 1010 1011 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1012 { 1013 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1014 STATS_TYPE_PORT); 1015 } 1016 1017 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1018 { 1019 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1020 } 1021 1022 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1023 { 1024 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1025 STATS_TYPE_BANK1); 1026 } 1027 1028 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1029 { 1030 struct mv88e6xxx_chip *chip = ds->priv; 1031 int serdes_count = 0; 1032 int count = 0; 1033 1034 if (sset != ETH_SS_STATS) 1035 return 0; 1036 1037 mv88e6xxx_reg_lock(chip); 1038 if (chip->info->ops->stats_get_sset_count) 1039 count = chip->info->ops->stats_get_sset_count(chip); 1040 if (count < 0) 1041 goto out; 1042 1043 if (chip->info->ops->serdes_get_sset_count) 1044 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1045 port); 1046 if (serdes_count < 0) { 1047 count = serdes_count; 1048 goto out; 1049 } 1050 count += serdes_count; 1051 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1052 1053 out: 1054 mv88e6xxx_reg_unlock(chip); 1055 1056 return count; 1057 } 1058 1059 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1060 uint64_t *data, int types, 1061 u16 bank1_select, u16 histogram) 1062 { 1063 struct mv88e6xxx_hw_stat *stat; 1064 int i, j; 1065 1066 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1067 stat = &mv88e6xxx_hw_stats[i]; 1068 if (stat->type & types) { 1069 mv88e6xxx_reg_lock(chip); 1070 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1071 bank1_select, 1072 histogram); 1073 mv88e6xxx_reg_unlock(chip); 1074 1075 j++; 1076 } 1077 } 1078 return j; 1079 } 1080 1081 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1082 uint64_t *data) 1083 { 1084 return mv88e6xxx_stats_get_stats(chip, port, data, 1085 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1086 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1087 } 1088 1089 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1090 uint64_t *data) 1091 { 1092 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1093 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1094 } 1095 1096 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1097 uint64_t *data) 1098 { 1099 return mv88e6xxx_stats_get_stats(chip, port, data, 1100 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1101 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1102 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1103 } 1104 1105 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1106 uint64_t *data) 1107 { 1108 return mv88e6xxx_stats_get_stats(chip, port, data, 1109 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1110 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1111 0); 1112 } 1113 1114 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1115 uint64_t *data) 1116 { 1117 *data++ = chip->ports[port].atu_member_violation; 1118 *data++ = chip->ports[port].atu_miss_violation; 1119 *data++ = chip->ports[port].atu_full_violation; 1120 *data++ = chip->ports[port].vtu_member_violation; 1121 *data++ = chip->ports[port].vtu_miss_violation; 1122 } 1123 1124 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1125 uint64_t *data) 1126 { 1127 int count = 0; 1128 1129 if (chip->info->ops->stats_get_stats) 1130 count = chip->info->ops->stats_get_stats(chip, port, data); 1131 1132 mv88e6xxx_reg_lock(chip); 1133 if (chip->info->ops->serdes_get_stats) { 1134 data += count; 1135 count = chip->info->ops->serdes_get_stats(chip, port, data); 1136 } 1137 data += count; 1138 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1139 mv88e6xxx_reg_unlock(chip); 1140 } 1141 1142 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1143 uint64_t *data) 1144 { 1145 struct mv88e6xxx_chip *chip = ds->priv; 1146 int ret; 1147 1148 mv88e6xxx_reg_lock(chip); 1149 1150 ret = mv88e6xxx_stats_snapshot(chip, port); 1151 mv88e6xxx_reg_unlock(chip); 1152 1153 if (ret < 0) 1154 return; 1155 1156 mv88e6xxx_get_stats(chip, port, data); 1157 1158 } 1159 1160 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1161 { 1162 struct mv88e6xxx_chip *chip = ds->priv; 1163 int len; 1164 1165 len = 32 * sizeof(u16); 1166 if (chip->info->ops->serdes_get_regs_len) 1167 len += chip->info->ops->serdes_get_regs_len(chip, port); 1168 1169 return len; 1170 } 1171 1172 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1173 struct ethtool_regs *regs, void *_p) 1174 { 1175 struct mv88e6xxx_chip *chip = ds->priv; 1176 int err; 1177 u16 reg; 1178 u16 *p = _p; 1179 int i; 1180 1181 regs->version = chip->info->prod_num; 1182 1183 memset(p, 0xff, 32 * sizeof(u16)); 1184 1185 mv88e6xxx_reg_lock(chip); 1186 1187 for (i = 0; i < 32; i++) { 1188 1189 err = mv88e6xxx_port_read(chip, port, i, ®); 1190 if (!err) 1191 p[i] = reg; 1192 } 1193 1194 if (chip->info->ops->serdes_get_regs) 1195 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1196 1197 mv88e6xxx_reg_unlock(chip); 1198 } 1199 1200 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1201 struct ethtool_eee *e) 1202 { 1203 /* Nothing to do on the port's MAC */ 1204 return 0; 1205 } 1206 1207 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1208 struct ethtool_eee *e) 1209 { 1210 /* Nothing to do on the port's MAC */ 1211 return 0; 1212 } 1213 1214 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1215 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1216 { 1217 struct dsa_switch *ds = chip->ds; 1218 struct dsa_switch_tree *dst = ds->dst; 1219 struct net_device *br; 1220 struct dsa_port *dp; 1221 bool found = false; 1222 u16 pvlan; 1223 1224 /* dev is a physical switch */ 1225 if (dev <= dst->last_switch) { 1226 list_for_each_entry(dp, &dst->ports, list) { 1227 if (dp->ds->index == dev && dp->index == port) { 1228 /* dp might be a DSA link or a user port, so it 1229 * might or might not have a bridge_dev 1230 * pointer. Use the "found" variable for both 1231 * cases. 1232 */ 1233 br = dp->bridge_dev; 1234 found = true; 1235 break; 1236 } 1237 } 1238 /* dev is a virtual bridge */ 1239 } else { 1240 list_for_each_entry(dp, &dst->ports, list) { 1241 if (dp->bridge_num < 0) 1242 continue; 1243 1244 if (dp->bridge_num + 1 + dst->last_switch != dev) 1245 continue; 1246 1247 br = dp->bridge_dev; 1248 found = true; 1249 break; 1250 } 1251 } 1252 1253 /* Prevent frames from unknown switch or virtual bridge */ 1254 if (!found) 1255 return 0; 1256 1257 /* Frames from DSA links and CPU ports can egress any local port */ 1258 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1259 return mv88e6xxx_port_mask(chip); 1260 1261 pvlan = 0; 1262 1263 /* Frames from user ports can egress any local DSA links and CPU ports, 1264 * as well as any local member of their bridge group. 1265 */ 1266 list_for_each_entry(dp, &dst->ports, list) 1267 if (dp->ds == ds && 1268 (dp->type == DSA_PORT_TYPE_CPU || 1269 dp->type == DSA_PORT_TYPE_DSA || 1270 (br && dp->bridge_dev == br))) 1271 pvlan |= BIT(dp->index); 1272 1273 return pvlan; 1274 } 1275 1276 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1277 { 1278 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1279 1280 /* prevent frames from going back out of the port they came in on */ 1281 output_ports &= ~BIT(port); 1282 1283 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1284 } 1285 1286 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1287 u8 state) 1288 { 1289 struct mv88e6xxx_chip *chip = ds->priv; 1290 int err; 1291 1292 mv88e6xxx_reg_lock(chip); 1293 err = mv88e6xxx_port_set_state(chip, port, state); 1294 mv88e6xxx_reg_unlock(chip); 1295 1296 if (err) 1297 dev_err(ds->dev, "p%d: failed to update state\n", port); 1298 } 1299 1300 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1301 { 1302 int err; 1303 1304 if (chip->info->ops->ieee_pri_map) { 1305 err = chip->info->ops->ieee_pri_map(chip); 1306 if (err) 1307 return err; 1308 } 1309 1310 if (chip->info->ops->ip_pri_map) { 1311 err = chip->info->ops->ip_pri_map(chip); 1312 if (err) 1313 return err; 1314 } 1315 1316 return 0; 1317 } 1318 1319 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1320 { 1321 struct dsa_switch *ds = chip->ds; 1322 int target, port; 1323 int err; 1324 1325 if (!chip->info->global2_addr) 1326 return 0; 1327 1328 /* Initialize the routing port to the 32 possible target devices */ 1329 for (target = 0; target < 32; target++) { 1330 port = dsa_routing_port(ds, target); 1331 if (port == ds->num_ports) 1332 port = 0x1f; 1333 1334 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1335 if (err) 1336 return err; 1337 } 1338 1339 if (chip->info->ops->set_cascade_port) { 1340 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1341 err = chip->info->ops->set_cascade_port(chip, port); 1342 if (err) 1343 return err; 1344 } 1345 1346 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1347 if (err) 1348 return err; 1349 1350 return 0; 1351 } 1352 1353 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1354 { 1355 /* Clear all trunk masks and mapping */ 1356 if (chip->info->global2_addr) 1357 return mv88e6xxx_g2_trunk_clear(chip); 1358 1359 return 0; 1360 } 1361 1362 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1363 { 1364 if (chip->info->ops->rmu_disable) 1365 return chip->info->ops->rmu_disable(chip); 1366 1367 return 0; 1368 } 1369 1370 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1371 { 1372 if (chip->info->ops->pot_clear) 1373 return chip->info->ops->pot_clear(chip); 1374 1375 return 0; 1376 } 1377 1378 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1379 { 1380 if (chip->info->ops->mgmt_rsvd2cpu) 1381 return chip->info->ops->mgmt_rsvd2cpu(chip); 1382 1383 return 0; 1384 } 1385 1386 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1387 { 1388 int err; 1389 1390 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1391 if (err) 1392 return err; 1393 1394 /* The chips that have a "learn2all" bit in Global1, ATU 1395 * Control are precisely those whose port registers have a 1396 * Message Port bit in Port Control 1 and hence implement 1397 * ->port_setup_message_port. 1398 */ 1399 if (chip->info->ops->port_setup_message_port) { 1400 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1401 if (err) 1402 return err; 1403 } 1404 1405 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1406 } 1407 1408 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1409 { 1410 int port; 1411 int err; 1412 1413 if (!chip->info->ops->irl_init_all) 1414 return 0; 1415 1416 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1417 /* Disable ingress rate limiting by resetting all per port 1418 * ingress rate limit resources to their initial state. 1419 */ 1420 err = chip->info->ops->irl_init_all(chip, port); 1421 if (err) 1422 return err; 1423 } 1424 1425 return 0; 1426 } 1427 1428 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1429 { 1430 if (chip->info->ops->set_switch_mac) { 1431 u8 addr[ETH_ALEN]; 1432 1433 eth_random_addr(addr); 1434 1435 return chip->info->ops->set_switch_mac(chip, addr); 1436 } 1437 1438 return 0; 1439 } 1440 1441 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1442 { 1443 struct dsa_switch_tree *dst = chip->ds->dst; 1444 struct dsa_switch *ds; 1445 struct dsa_port *dp; 1446 u16 pvlan = 0; 1447 1448 if (!mv88e6xxx_has_pvt(chip)) 1449 return 0; 1450 1451 /* Skip the local source device, which uses in-chip port VLAN */ 1452 if (dev != chip->ds->index) { 1453 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1454 1455 ds = dsa_switch_find(dst->index, dev); 1456 dp = ds ? dsa_to_port(ds, port) : NULL; 1457 if (dp && dp->lag_dev) { 1458 /* As the PVT is used to limit flooding of 1459 * FORWARD frames, which use the LAG ID as the 1460 * source port, we must translate dev/port to 1461 * the special "LAG device" in the PVT, using 1462 * the LAG ID as the port number. 1463 */ 1464 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1465 port = dsa_lag_id(dst, dp->lag_dev); 1466 } 1467 } 1468 1469 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1470 } 1471 1472 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1473 { 1474 int dev, port; 1475 int err; 1476 1477 if (!mv88e6xxx_has_pvt(chip)) 1478 return 0; 1479 1480 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1481 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1482 */ 1483 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1484 if (err) 1485 return err; 1486 1487 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1488 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1489 err = mv88e6xxx_pvt_map(chip, dev, port); 1490 if (err) 1491 return err; 1492 } 1493 } 1494 1495 return 0; 1496 } 1497 1498 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1499 { 1500 struct mv88e6xxx_chip *chip = ds->priv; 1501 int err; 1502 1503 if (dsa_to_port(ds, port)->lag_dev) 1504 /* Hardware is incapable of fast-aging a LAG through a 1505 * regular ATU move operation. Until we have something 1506 * more fancy in place this is a no-op. 1507 */ 1508 return; 1509 1510 mv88e6xxx_reg_lock(chip); 1511 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1512 mv88e6xxx_reg_unlock(chip); 1513 1514 if (err) 1515 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1516 } 1517 1518 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1519 { 1520 if (!mv88e6xxx_max_vid(chip)) 1521 return 0; 1522 1523 return mv88e6xxx_g1_vtu_flush(chip); 1524 } 1525 1526 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1527 struct mv88e6xxx_vtu_entry *entry) 1528 { 1529 int err; 1530 1531 if (!chip->info->ops->vtu_getnext) 1532 return -EOPNOTSUPP; 1533 1534 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1535 entry->valid = false; 1536 1537 err = chip->info->ops->vtu_getnext(chip, entry); 1538 1539 if (entry->vid != vid) 1540 entry->valid = false; 1541 1542 return err; 1543 } 1544 1545 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1546 int (*cb)(struct mv88e6xxx_chip *chip, 1547 const struct mv88e6xxx_vtu_entry *entry, 1548 void *priv), 1549 void *priv) 1550 { 1551 struct mv88e6xxx_vtu_entry entry = { 1552 .vid = mv88e6xxx_max_vid(chip), 1553 .valid = false, 1554 }; 1555 int err; 1556 1557 if (!chip->info->ops->vtu_getnext) 1558 return -EOPNOTSUPP; 1559 1560 do { 1561 err = chip->info->ops->vtu_getnext(chip, &entry); 1562 if (err) 1563 return err; 1564 1565 if (!entry.valid) 1566 break; 1567 1568 err = cb(chip, &entry, priv); 1569 if (err) 1570 return err; 1571 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1572 1573 return 0; 1574 } 1575 1576 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1577 struct mv88e6xxx_vtu_entry *entry) 1578 { 1579 if (!chip->info->ops->vtu_loadpurge) 1580 return -EOPNOTSUPP; 1581 1582 return chip->info->ops->vtu_loadpurge(chip, entry); 1583 } 1584 1585 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1586 const struct mv88e6xxx_vtu_entry *entry, 1587 void *_fid_bitmap) 1588 { 1589 unsigned long *fid_bitmap = _fid_bitmap; 1590 1591 set_bit(entry->fid, fid_bitmap); 1592 return 0; 1593 } 1594 1595 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1596 { 1597 int i, err; 1598 u16 fid; 1599 1600 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1601 1602 /* Set every FID bit used by the (un)bridged ports */ 1603 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1604 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1605 if (err) 1606 return err; 1607 1608 set_bit(fid, fid_bitmap); 1609 } 1610 1611 /* Set every FID bit used by the VLAN entries */ 1612 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1613 } 1614 1615 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1616 { 1617 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1618 int err; 1619 1620 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1621 if (err) 1622 return err; 1623 1624 /* The reset value 0x000 is used to indicate that multiple address 1625 * databases are not needed. Return the next positive available. 1626 */ 1627 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1628 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1629 return -ENOSPC; 1630 1631 /* Clear the database */ 1632 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1633 } 1634 1635 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1636 u16 vid) 1637 { 1638 struct mv88e6xxx_chip *chip = ds->priv; 1639 struct mv88e6xxx_vtu_entry vlan; 1640 int i, err; 1641 1642 /* DSA and CPU ports have to be members of multiple vlans */ 1643 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1644 return 0; 1645 1646 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1647 if (err) 1648 return err; 1649 1650 if (!vlan.valid) 1651 return 0; 1652 1653 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1654 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1655 continue; 1656 1657 if (!dsa_to_port(ds, i)->slave) 1658 continue; 1659 1660 if (vlan.member[i] == 1661 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1662 continue; 1663 1664 if (dsa_to_port(ds, i)->bridge_dev == 1665 dsa_to_port(ds, port)->bridge_dev) 1666 break; /* same bridge, check next VLAN */ 1667 1668 if (!dsa_to_port(ds, i)->bridge_dev) 1669 continue; 1670 1671 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1672 port, vlan.vid, i, 1673 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1674 return -EOPNOTSUPP; 1675 } 1676 1677 return 0; 1678 } 1679 1680 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1681 bool vlan_filtering, 1682 struct netlink_ext_ack *extack) 1683 { 1684 struct mv88e6xxx_chip *chip = ds->priv; 1685 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1686 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1687 int err; 1688 1689 if (!mv88e6xxx_max_vid(chip)) 1690 return -EOPNOTSUPP; 1691 1692 mv88e6xxx_reg_lock(chip); 1693 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1694 mv88e6xxx_reg_unlock(chip); 1695 1696 return err; 1697 } 1698 1699 static int 1700 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1701 const struct switchdev_obj_port_vlan *vlan) 1702 { 1703 struct mv88e6xxx_chip *chip = ds->priv; 1704 int err; 1705 1706 if (!mv88e6xxx_max_vid(chip)) 1707 return -EOPNOTSUPP; 1708 1709 /* If the requested port doesn't belong to the same bridge as the VLAN 1710 * members, do not support it (yet) and fallback to software VLAN. 1711 */ 1712 mv88e6xxx_reg_lock(chip); 1713 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1714 mv88e6xxx_reg_unlock(chip); 1715 1716 return err; 1717 } 1718 1719 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1720 const unsigned char *addr, u16 vid, 1721 u8 state) 1722 { 1723 struct mv88e6xxx_atu_entry entry; 1724 struct mv88e6xxx_vtu_entry vlan; 1725 u16 fid; 1726 int err; 1727 1728 /* Null VLAN ID corresponds to the port private database */ 1729 if (vid == 0) { 1730 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1731 if (err) 1732 return err; 1733 } else { 1734 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1735 if (err) 1736 return err; 1737 1738 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1739 if (!vlan.valid) 1740 return -EOPNOTSUPP; 1741 1742 fid = vlan.fid; 1743 } 1744 1745 entry.state = 0; 1746 ether_addr_copy(entry.mac, addr); 1747 eth_addr_dec(entry.mac); 1748 1749 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1750 if (err) 1751 return err; 1752 1753 /* Initialize a fresh ATU entry if it isn't found */ 1754 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1755 memset(&entry, 0, sizeof(entry)); 1756 ether_addr_copy(entry.mac, addr); 1757 } 1758 1759 /* Purge the ATU entry only if no port is using it anymore */ 1760 if (!state) { 1761 entry.portvec &= ~BIT(port); 1762 if (!entry.portvec) 1763 entry.state = 0; 1764 } else { 1765 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1766 entry.portvec = BIT(port); 1767 else 1768 entry.portvec |= BIT(port); 1769 1770 entry.state = state; 1771 } 1772 1773 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1774 } 1775 1776 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1777 const struct mv88e6xxx_policy *policy) 1778 { 1779 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1780 enum mv88e6xxx_policy_action action = policy->action; 1781 const u8 *addr = policy->addr; 1782 u16 vid = policy->vid; 1783 u8 state; 1784 int err; 1785 int id; 1786 1787 if (!chip->info->ops->port_set_policy) 1788 return -EOPNOTSUPP; 1789 1790 switch (mapping) { 1791 case MV88E6XXX_POLICY_MAPPING_DA: 1792 case MV88E6XXX_POLICY_MAPPING_SA: 1793 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1794 state = 0; /* Dissociate the port and address */ 1795 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1796 is_multicast_ether_addr(addr)) 1797 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1798 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1799 is_unicast_ether_addr(addr)) 1800 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1801 else 1802 return -EOPNOTSUPP; 1803 1804 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1805 state); 1806 if (err) 1807 return err; 1808 break; 1809 default: 1810 return -EOPNOTSUPP; 1811 } 1812 1813 /* Skip the port's policy clearing if the mapping is still in use */ 1814 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1815 idr_for_each_entry(&chip->policies, policy, id) 1816 if (policy->port == port && 1817 policy->mapping == mapping && 1818 policy->action != action) 1819 return 0; 1820 1821 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1822 } 1823 1824 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1825 struct ethtool_rx_flow_spec *fs) 1826 { 1827 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1828 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1829 enum mv88e6xxx_policy_mapping mapping; 1830 enum mv88e6xxx_policy_action action; 1831 struct mv88e6xxx_policy *policy; 1832 u16 vid = 0; 1833 u8 *addr; 1834 int err; 1835 int id; 1836 1837 if (fs->location != RX_CLS_LOC_ANY) 1838 return -EINVAL; 1839 1840 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1841 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1842 else 1843 return -EOPNOTSUPP; 1844 1845 switch (fs->flow_type & ~FLOW_EXT) { 1846 case ETHER_FLOW: 1847 if (!is_zero_ether_addr(mac_mask->h_dest) && 1848 is_zero_ether_addr(mac_mask->h_source)) { 1849 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1850 addr = mac_entry->h_dest; 1851 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1852 !is_zero_ether_addr(mac_mask->h_source)) { 1853 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1854 addr = mac_entry->h_source; 1855 } else { 1856 /* Cannot support DA and SA mapping in the same rule */ 1857 return -EOPNOTSUPP; 1858 } 1859 break; 1860 default: 1861 return -EOPNOTSUPP; 1862 } 1863 1864 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1865 if (fs->m_ext.vlan_tci != htons(0xffff)) 1866 return -EOPNOTSUPP; 1867 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1868 } 1869 1870 idr_for_each_entry(&chip->policies, policy, id) { 1871 if (policy->port == port && policy->mapping == mapping && 1872 policy->action == action && policy->vid == vid && 1873 ether_addr_equal(policy->addr, addr)) 1874 return -EEXIST; 1875 } 1876 1877 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1878 if (!policy) 1879 return -ENOMEM; 1880 1881 fs->location = 0; 1882 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1883 GFP_KERNEL); 1884 if (err) { 1885 devm_kfree(chip->dev, policy); 1886 return err; 1887 } 1888 1889 memcpy(&policy->fs, fs, sizeof(*fs)); 1890 ether_addr_copy(policy->addr, addr); 1891 policy->mapping = mapping; 1892 policy->action = action; 1893 policy->port = port; 1894 policy->vid = vid; 1895 1896 err = mv88e6xxx_policy_apply(chip, port, policy); 1897 if (err) { 1898 idr_remove(&chip->policies, fs->location); 1899 devm_kfree(chip->dev, policy); 1900 return err; 1901 } 1902 1903 return 0; 1904 } 1905 1906 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1907 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1908 { 1909 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1910 struct mv88e6xxx_chip *chip = ds->priv; 1911 struct mv88e6xxx_policy *policy; 1912 int err; 1913 int id; 1914 1915 mv88e6xxx_reg_lock(chip); 1916 1917 switch (rxnfc->cmd) { 1918 case ETHTOOL_GRXCLSRLCNT: 1919 rxnfc->data = 0; 1920 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1921 rxnfc->rule_cnt = 0; 1922 idr_for_each_entry(&chip->policies, policy, id) 1923 if (policy->port == port) 1924 rxnfc->rule_cnt++; 1925 err = 0; 1926 break; 1927 case ETHTOOL_GRXCLSRULE: 1928 err = -ENOENT; 1929 policy = idr_find(&chip->policies, fs->location); 1930 if (policy) { 1931 memcpy(fs, &policy->fs, sizeof(*fs)); 1932 err = 0; 1933 } 1934 break; 1935 case ETHTOOL_GRXCLSRLALL: 1936 rxnfc->data = 0; 1937 rxnfc->rule_cnt = 0; 1938 idr_for_each_entry(&chip->policies, policy, id) 1939 if (policy->port == port) 1940 rule_locs[rxnfc->rule_cnt++] = id; 1941 err = 0; 1942 break; 1943 default: 1944 err = -EOPNOTSUPP; 1945 break; 1946 } 1947 1948 mv88e6xxx_reg_unlock(chip); 1949 1950 return err; 1951 } 1952 1953 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1954 struct ethtool_rxnfc *rxnfc) 1955 { 1956 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1957 struct mv88e6xxx_chip *chip = ds->priv; 1958 struct mv88e6xxx_policy *policy; 1959 int err; 1960 1961 mv88e6xxx_reg_lock(chip); 1962 1963 switch (rxnfc->cmd) { 1964 case ETHTOOL_SRXCLSRLINS: 1965 err = mv88e6xxx_policy_insert(chip, port, fs); 1966 break; 1967 case ETHTOOL_SRXCLSRLDEL: 1968 err = -ENOENT; 1969 policy = idr_remove(&chip->policies, fs->location); 1970 if (policy) { 1971 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1972 err = mv88e6xxx_policy_apply(chip, port, policy); 1973 devm_kfree(chip->dev, policy); 1974 } 1975 break; 1976 default: 1977 err = -EOPNOTSUPP; 1978 break; 1979 } 1980 1981 mv88e6xxx_reg_unlock(chip); 1982 1983 return err; 1984 } 1985 1986 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1987 u16 vid) 1988 { 1989 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1990 u8 broadcast[ETH_ALEN]; 1991 1992 eth_broadcast_addr(broadcast); 1993 1994 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1995 } 1996 1997 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1998 { 1999 int port; 2000 int err; 2001 2002 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2003 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2004 struct net_device *brport; 2005 2006 if (dsa_is_unused_port(chip->ds, port)) 2007 continue; 2008 2009 brport = dsa_port_to_bridge_port(dp); 2010 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2011 /* Skip bridged user ports where broadcast 2012 * flooding is disabled. 2013 */ 2014 continue; 2015 2016 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2017 if (err) 2018 return err; 2019 } 2020 2021 return 0; 2022 } 2023 2024 struct mv88e6xxx_port_broadcast_sync_ctx { 2025 int port; 2026 bool flood; 2027 }; 2028 2029 static int 2030 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2031 const struct mv88e6xxx_vtu_entry *vlan, 2032 void *_ctx) 2033 { 2034 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2035 u8 broadcast[ETH_ALEN]; 2036 u8 state; 2037 2038 if (ctx->flood) 2039 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2040 else 2041 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2042 2043 eth_broadcast_addr(broadcast); 2044 2045 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2046 vlan->vid, state); 2047 } 2048 2049 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2050 bool flood) 2051 { 2052 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2053 .port = port, 2054 .flood = flood, 2055 }; 2056 struct mv88e6xxx_vtu_entry vid0 = { 2057 .vid = 0, 2058 }; 2059 int err; 2060 2061 /* Update the port's private database... */ 2062 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2063 if (err) 2064 return err; 2065 2066 /* ...and the database for all VLANs. */ 2067 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2068 &ctx); 2069 } 2070 2071 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2072 u16 vid, u8 member, bool warn) 2073 { 2074 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2075 struct mv88e6xxx_vtu_entry vlan; 2076 int i, err; 2077 2078 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2079 if (err) 2080 return err; 2081 2082 if (!vlan.valid) { 2083 memset(&vlan, 0, sizeof(vlan)); 2084 2085 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2086 if (err) 2087 return err; 2088 2089 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2090 if (i == port) 2091 vlan.member[i] = member; 2092 else 2093 vlan.member[i] = non_member; 2094 2095 vlan.vid = vid; 2096 vlan.valid = true; 2097 2098 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2099 if (err) 2100 return err; 2101 2102 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2103 if (err) 2104 return err; 2105 } else if (vlan.member[port] != member) { 2106 vlan.member[port] = member; 2107 2108 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2109 if (err) 2110 return err; 2111 } else if (warn) { 2112 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2113 port, vid); 2114 } 2115 2116 return 0; 2117 } 2118 2119 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2120 const struct switchdev_obj_port_vlan *vlan, 2121 struct netlink_ext_ack *extack) 2122 { 2123 struct mv88e6xxx_chip *chip = ds->priv; 2124 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2125 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2126 bool warn; 2127 u8 member; 2128 int err; 2129 2130 if (!vlan->vid) 2131 return 0; 2132 2133 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2134 if (err) 2135 return err; 2136 2137 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2138 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2139 else if (untagged) 2140 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2141 else 2142 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2143 2144 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2145 * and then the CPU port. Do not warn for duplicates for the CPU port. 2146 */ 2147 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2148 2149 mv88e6xxx_reg_lock(chip); 2150 2151 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2152 if (err) { 2153 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2154 vlan->vid, untagged ? 'u' : 't'); 2155 goto out; 2156 } 2157 2158 if (pvid) { 2159 err = mv88e6xxx_port_set_pvid(chip, port, vlan->vid); 2160 if (err) { 2161 dev_err(ds->dev, "p%d: failed to set PVID %d\n", 2162 port, vlan->vid); 2163 goto out; 2164 } 2165 } 2166 out: 2167 mv88e6xxx_reg_unlock(chip); 2168 2169 return err; 2170 } 2171 2172 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2173 int port, u16 vid) 2174 { 2175 struct mv88e6xxx_vtu_entry vlan; 2176 int i, err; 2177 2178 if (!vid) 2179 return 0; 2180 2181 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2182 if (err) 2183 return err; 2184 2185 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2186 * tell switchdev that this VLAN is likely handled in software. 2187 */ 2188 if (!vlan.valid || 2189 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2190 return -EOPNOTSUPP; 2191 2192 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2193 2194 /* keep the VLAN unless all ports are excluded */ 2195 vlan.valid = false; 2196 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2197 if (vlan.member[i] != 2198 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2199 vlan.valid = true; 2200 break; 2201 } 2202 } 2203 2204 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2205 if (err) 2206 return err; 2207 2208 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2209 } 2210 2211 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2212 const struct switchdev_obj_port_vlan *vlan) 2213 { 2214 struct mv88e6xxx_chip *chip = ds->priv; 2215 int err = 0; 2216 u16 pvid; 2217 2218 if (!mv88e6xxx_max_vid(chip)) 2219 return -EOPNOTSUPP; 2220 2221 mv88e6xxx_reg_lock(chip); 2222 2223 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2224 if (err) 2225 goto unlock; 2226 2227 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2228 if (err) 2229 goto unlock; 2230 2231 if (vlan->vid == pvid) { 2232 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2233 if (err) 2234 goto unlock; 2235 } 2236 2237 unlock: 2238 mv88e6xxx_reg_unlock(chip); 2239 2240 return err; 2241 } 2242 2243 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2244 const unsigned char *addr, u16 vid) 2245 { 2246 struct mv88e6xxx_chip *chip = ds->priv; 2247 int err; 2248 2249 mv88e6xxx_reg_lock(chip); 2250 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2251 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2252 mv88e6xxx_reg_unlock(chip); 2253 2254 return err; 2255 } 2256 2257 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2258 const unsigned char *addr, u16 vid) 2259 { 2260 struct mv88e6xxx_chip *chip = ds->priv; 2261 int err; 2262 2263 mv88e6xxx_reg_lock(chip); 2264 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2265 mv88e6xxx_reg_unlock(chip); 2266 2267 return err; 2268 } 2269 2270 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2271 u16 fid, u16 vid, int port, 2272 dsa_fdb_dump_cb_t *cb, void *data) 2273 { 2274 struct mv88e6xxx_atu_entry addr; 2275 bool is_static; 2276 int err; 2277 2278 addr.state = 0; 2279 eth_broadcast_addr(addr.mac); 2280 2281 do { 2282 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2283 if (err) 2284 return err; 2285 2286 if (!addr.state) 2287 break; 2288 2289 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2290 continue; 2291 2292 if (!is_unicast_ether_addr(addr.mac)) 2293 continue; 2294 2295 is_static = (addr.state == 2296 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2297 err = cb(addr.mac, vid, is_static, data); 2298 if (err) 2299 return err; 2300 } while (!is_broadcast_ether_addr(addr.mac)); 2301 2302 return err; 2303 } 2304 2305 struct mv88e6xxx_port_db_dump_vlan_ctx { 2306 int port; 2307 dsa_fdb_dump_cb_t *cb; 2308 void *data; 2309 }; 2310 2311 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2312 const struct mv88e6xxx_vtu_entry *entry, 2313 void *_data) 2314 { 2315 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2316 2317 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2318 ctx->port, ctx->cb, ctx->data); 2319 } 2320 2321 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2322 dsa_fdb_dump_cb_t *cb, void *data) 2323 { 2324 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2325 .port = port, 2326 .cb = cb, 2327 .data = data, 2328 }; 2329 u16 fid; 2330 int err; 2331 2332 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2333 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2334 if (err) 2335 return err; 2336 2337 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2338 if (err) 2339 return err; 2340 2341 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2342 } 2343 2344 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2345 dsa_fdb_dump_cb_t *cb, void *data) 2346 { 2347 struct mv88e6xxx_chip *chip = ds->priv; 2348 int err; 2349 2350 mv88e6xxx_reg_lock(chip); 2351 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2352 mv88e6xxx_reg_unlock(chip); 2353 2354 return err; 2355 } 2356 2357 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2358 struct net_device *br) 2359 { 2360 struct dsa_switch *ds = chip->ds; 2361 struct dsa_switch_tree *dst = ds->dst; 2362 struct dsa_port *dp; 2363 int err; 2364 2365 list_for_each_entry(dp, &dst->ports, list) { 2366 if (dp->bridge_dev == br) { 2367 if (dp->ds == ds) { 2368 /* This is a local bridge group member, 2369 * remap its Port VLAN Map. 2370 */ 2371 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2372 if (err) 2373 return err; 2374 } else { 2375 /* This is an external bridge group member, 2376 * remap its cross-chip Port VLAN Table entry. 2377 */ 2378 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2379 dp->index); 2380 if (err) 2381 return err; 2382 } 2383 } 2384 } 2385 2386 return 0; 2387 } 2388 2389 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2390 struct net_device *br) 2391 { 2392 struct mv88e6xxx_chip *chip = ds->priv; 2393 int err; 2394 2395 mv88e6xxx_reg_lock(chip); 2396 err = mv88e6xxx_bridge_map(chip, br); 2397 mv88e6xxx_reg_unlock(chip); 2398 2399 return err; 2400 } 2401 2402 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2403 struct net_device *br) 2404 { 2405 struct mv88e6xxx_chip *chip = ds->priv; 2406 2407 mv88e6xxx_reg_lock(chip); 2408 if (mv88e6xxx_bridge_map(chip, br) || 2409 mv88e6xxx_port_vlan_map(chip, port)) 2410 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2411 mv88e6xxx_reg_unlock(chip); 2412 } 2413 2414 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2415 int tree_index, int sw_index, 2416 int port, struct net_device *br) 2417 { 2418 struct mv88e6xxx_chip *chip = ds->priv; 2419 int err; 2420 2421 if (tree_index != ds->dst->index) 2422 return 0; 2423 2424 mv88e6xxx_reg_lock(chip); 2425 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2426 mv88e6xxx_reg_unlock(chip); 2427 2428 return err; 2429 } 2430 2431 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2432 int tree_index, int sw_index, 2433 int port, struct net_device *br) 2434 { 2435 struct mv88e6xxx_chip *chip = ds->priv; 2436 2437 if (tree_index != ds->dst->index) 2438 return; 2439 2440 mv88e6xxx_reg_lock(chip); 2441 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2442 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2443 mv88e6xxx_reg_unlock(chip); 2444 } 2445 2446 /* Treat the software bridge as a virtual single-port switch behind the 2447 * CPU and map in the PVT. First dst->last_switch elements are taken by 2448 * physical switches, so start from beyond that range. 2449 */ 2450 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2451 int bridge_num) 2452 { 2453 u8 dev = bridge_num + ds->dst->last_switch + 1; 2454 struct mv88e6xxx_chip *chip = ds->priv; 2455 int err; 2456 2457 mv88e6xxx_reg_lock(chip); 2458 err = mv88e6xxx_pvt_map(chip, dev, 0); 2459 mv88e6xxx_reg_unlock(chip); 2460 2461 return err; 2462 } 2463 2464 static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port, 2465 struct net_device *br, 2466 int bridge_num) 2467 { 2468 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2469 } 2470 2471 static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port, 2472 struct net_device *br, 2473 int bridge_num) 2474 { 2475 int err; 2476 2477 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2478 if (err) { 2479 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n", 2480 ERR_PTR(err)); 2481 } 2482 } 2483 2484 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2485 { 2486 if (chip->info->ops->reset) 2487 return chip->info->ops->reset(chip); 2488 2489 return 0; 2490 } 2491 2492 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2493 { 2494 struct gpio_desc *gpiod = chip->reset; 2495 2496 /* If there is a GPIO connected to the reset pin, toggle it */ 2497 if (gpiod) { 2498 gpiod_set_value_cansleep(gpiod, 1); 2499 usleep_range(10000, 20000); 2500 gpiod_set_value_cansleep(gpiod, 0); 2501 usleep_range(10000, 20000); 2502 2503 mv88e6xxx_g1_wait_eeprom_done(chip); 2504 } 2505 } 2506 2507 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2508 { 2509 int i, err; 2510 2511 /* Set all ports to the Disabled state */ 2512 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2513 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2514 if (err) 2515 return err; 2516 } 2517 2518 /* Wait for transmit queues to drain, 2519 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2520 */ 2521 usleep_range(2000, 4000); 2522 2523 return 0; 2524 } 2525 2526 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2527 { 2528 int err; 2529 2530 err = mv88e6xxx_disable_ports(chip); 2531 if (err) 2532 return err; 2533 2534 mv88e6xxx_hardware_reset(chip); 2535 2536 return mv88e6xxx_software_reset(chip); 2537 } 2538 2539 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2540 enum mv88e6xxx_frame_mode frame, 2541 enum mv88e6xxx_egress_mode egress, u16 etype) 2542 { 2543 int err; 2544 2545 if (!chip->info->ops->port_set_frame_mode) 2546 return -EOPNOTSUPP; 2547 2548 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2549 if (err) 2550 return err; 2551 2552 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2553 if (err) 2554 return err; 2555 2556 if (chip->info->ops->port_set_ether_type) 2557 return chip->info->ops->port_set_ether_type(chip, port, etype); 2558 2559 return 0; 2560 } 2561 2562 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2563 { 2564 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2565 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2566 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2567 } 2568 2569 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2570 { 2571 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2572 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2573 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2574 } 2575 2576 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2577 { 2578 return mv88e6xxx_set_port_mode(chip, port, 2579 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2580 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2581 ETH_P_EDSA); 2582 } 2583 2584 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2585 { 2586 if (dsa_is_dsa_port(chip->ds, port)) 2587 return mv88e6xxx_set_port_mode_dsa(chip, port); 2588 2589 if (dsa_is_user_port(chip->ds, port)) 2590 return mv88e6xxx_set_port_mode_normal(chip, port); 2591 2592 /* Setup CPU port mode depending on its supported tag format */ 2593 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2594 return mv88e6xxx_set_port_mode_dsa(chip, port); 2595 2596 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2597 return mv88e6xxx_set_port_mode_edsa(chip, port); 2598 2599 return -EINVAL; 2600 } 2601 2602 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2603 { 2604 bool message = dsa_is_dsa_port(chip->ds, port); 2605 2606 return mv88e6xxx_port_set_message_port(chip, port, message); 2607 } 2608 2609 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2610 { 2611 int err; 2612 2613 if (chip->info->ops->port_set_ucast_flood) { 2614 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2615 if (err) 2616 return err; 2617 } 2618 if (chip->info->ops->port_set_mcast_flood) { 2619 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2620 if (err) 2621 return err; 2622 } 2623 2624 return 0; 2625 } 2626 2627 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2628 { 2629 struct mv88e6xxx_port *mvp = dev_id; 2630 struct mv88e6xxx_chip *chip = mvp->chip; 2631 irqreturn_t ret = IRQ_NONE; 2632 int port = mvp->port; 2633 int lane; 2634 2635 mv88e6xxx_reg_lock(chip); 2636 lane = mv88e6xxx_serdes_get_lane(chip, port); 2637 if (lane >= 0) 2638 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2639 mv88e6xxx_reg_unlock(chip); 2640 2641 return ret; 2642 } 2643 2644 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2645 int lane) 2646 { 2647 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2648 unsigned int irq; 2649 int err; 2650 2651 /* Nothing to request if this SERDES port has no IRQ */ 2652 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2653 if (!irq) 2654 return 0; 2655 2656 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2657 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2658 2659 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2660 mv88e6xxx_reg_unlock(chip); 2661 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2662 IRQF_ONESHOT, dev_id->serdes_irq_name, 2663 dev_id); 2664 mv88e6xxx_reg_lock(chip); 2665 if (err) 2666 return err; 2667 2668 dev_id->serdes_irq = irq; 2669 2670 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2671 } 2672 2673 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2674 int lane) 2675 { 2676 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2677 unsigned int irq = dev_id->serdes_irq; 2678 int err; 2679 2680 /* Nothing to free if no IRQ has been requested */ 2681 if (!irq) 2682 return 0; 2683 2684 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2685 2686 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2687 mv88e6xxx_reg_unlock(chip); 2688 free_irq(irq, dev_id); 2689 mv88e6xxx_reg_lock(chip); 2690 2691 dev_id->serdes_irq = 0; 2692 2693 return err; 2694 } 2695 2696 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2697 bool on) 2698 { 2699 int lane; 2700 int err; 2701 2702 lane = mv88e6xxx_serdes_get_lane(chip, port); 2703 if (lane < 0) 2704 return 0; 2705 2706 if (on) { 2707 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2708 if (err) 2709 return err; 2710 2711 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2712 } else { 2713 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2714 if (err) 2715 return err; 2716 2717 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2718 } 2719 2720 return err; 2721 } 2722 2723 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2724 enum mv88e6xxx_egress_direction direction, 2725 int port) 2726 { 2727 int err; 2728 2729 if (!chip->info->ops->set_egress_port) 2730 return -EOPNOTSUPP; 2731 2732 err = chip->info->ops->set_egress_port(chip, direction, port); 2733 if (err) 2734 return err; 2735 2736 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2737 chip->ingress_dest_port = port; 2738 else 2739 chip->egress_dest_port = port; 2740 2741 return 0; 2742 } 2743 2744 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2745 { 2746 struct dsa_switch *ds = chip->ds; 2747 int upstream_port; 2748 int err; 2749 2750 upstream_port = dsa_upstream_port(ds, port); 2751 if (chip->info->ops->port_set_upstream_port) { 2752 err = chip->info->ops->port_set_upstream_port(chip, port, 2753 upstream_port); 2754 if (err) 2755 return err; 2756 } 2757 2758 if (port == upstream_port) { 2759 if (chip->info->ops->set_cpu_port) { 2760 err = chip->info->ops->set_cpu_port(chip, 2761 upstream_port); 2762 if (err) 2763 return err; 2764 } 2765 2766 err = mv88e6xxx_set_egress_port(chip, 2767 MV88E6XXX_EGRESS_DIR_INGRESS, 2768 upstream_port); 2769 if (err && err != -EOPNOTSUPP) 2770 return err; 2771 2772 err = mv88e6xxx_set_egress_port(chip, 2773 MV88E6XXX_EGRESS_DIR_EGRESS, 2774 upstream_port); 2775 if (err && err != -EOPNOTSUPP) 2776 return err; 2777 } 2778 2779 return 0; 2780 } 2781 2782 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2783 { 2784 struct dsa_switch *ds = chip->ds; 2785 int err; 2786 u16 reg; 2787 2788 chip->ports[port].chip = chip; 2789 chip->ports[port].port = port; 2790 2791 /* MAC Forcing register: don't force link, speed, duplex or flow control 2792 * state to any particular values on physical ports, but force the CPU 2793 * port and all DSA ports to their maximum bandwidth and full duplex. 2794 */ 2795 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2796 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2797 SPEED_MAX, DUPLEX_FULL, 2798 PAUSE_OFF, 2799 PHY_INTERFACE_MODE_NA); 2800 else 2801 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2802 SPEED_UNFORCED, DUPLEX_UNFORCED, 2803 PAUSE_ON, 2804 PHY_INTERFACE_MODE_NA); 2805 if (err) 2806 return err; 2807 2808 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2809 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2810 * tunneling, determine priority by looking at 802.1p and IP 2811 * priority fields (IP prio has precedence), and set STP state 2812 * to Forwarding. 2813 * 2814 * If this is the CPU link, use DSA or EDSA tagging depending 2815 * on which tagging mode was configured. 2816 * 2817 * If this is a link to another switch, use DSA tagging mode. 2818 * 2819 * If this is the upstream port for this switch, enable 2820 * forwarding of unknown unicasts and multicasts. 2821 */ 2822 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2823 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2824 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2825 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2826 if (err) 2827 return err; 2828 2829 err = mv88e6xxx_setup_port_mode(chip, port); 2830 if (err) 2831 return err; 2832 2833 err = mv88e6xxx_setup_egress_floods(chip, port); 2834 if (err) 2835 return err; 2836 2837 /* Port Control 2: don't force a good FCS, set the MTU size to 2838 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2839 * untagged frames on this port, do a destination address lookup on all 2840 * received packets as usual, disable ARP mirroring and don't send a 2841 * copy of all transmitted/received frames on this port to the CPU. 2842 */ 2843 err = mv88e6xxx_port_set_map_da(chip, port); 2844 if (err) 2845 return err; 2846 2847 err = mv88e6xxx_setup_upstream_port(chip, port); 2848 if (err) 2849 return err; 2850 2851 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2852 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2853 if (err) 2854 return err; 2855 2856 if (chip->info->ops->port_set_jumbo_size) { 2857 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2858 if (err) 2859 return err; 2860 } 2861 2862 /* Port Association Vector: disable automatic address learning 2863 * on all user ports since they start out in standalone 2864 * mode. When joining a bridge, learning will be configured to 2865 * match the bridge port settings. Enable learning on all 2866 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2867 * learning process. 2868 * 2869 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2870 * and RefreshLocked. I.e. setup standard automatic learning. 2871 */ 2872 if (dsa_is_user_port(ds, port)) 2873 reg = 0; 2874 else 2875 reg = 1 << port; 2876 2877 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2878 reg); 2879 if (err) 2880 return err; 2881 2882 /* Egress rate control 2: disable egress rate control. */ 2883 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2884 0x0000); 2885 if (err) 2886 return err; 2887 2888 if (chip->info->ops->port_pause_limit) { 2889 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2890 if (err) 2891 return err; 2892 } 2893 2894 if (chip->info->ops->port_disable_learn_limit) { 2895 err = chip->info->ops->port_disable_learn_limit(chip, port); 2896 if (err) 2897 return err; 2898 } 2899 2900 if (chip->info->ops->port_disable_pri_override) { 2901 err = chip->info->ops->port_disable_pri_override(chip, port); 2902 if (err) 2903 return err; 2904 } 2905 2906 if (chip->info->ops->port_tag_remap) { 2907 err = chip->info->ops->port_tag_remap(chip, port); 2908 if (err) 2909 return err; 2910 } 2911 2912 if (chip->info->ops->port_egress_rate_limiting) { 2913 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2914 if (err) 2915 return err; 2916 } 2917 2918 if (chip->info->ops->port_setup_message_port) { 2919 err = chip->info->ops->port_setup_message_port(chip, port); 2920 if (err) 2921 return err; 2922 } 2923 2924 /* Port based VLAN map: give each port the same default address 2925 * database, and allow bidirectional communication between the 2926 * CPU and DSA port(s), and the other ports. 2927 */ 2928 err = mv88e6xxx_port_set_fid(chip, port, 0); 2929 if (err) 2930 return err; 2931 2932 err = mv88e6xxx_port_vlan_map(chip, port); 2933 if (err) 2934 return err; 2935 2936 /* Default VLAN ID and priority: don't set a default VLAN 2937 * ID, and set the default packet priority to zero. 2938 */ 2939 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2940 } 2941 2942 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2943 { 2944 struct mv88e6xxx_chip *chip = ds->priv; 2945 2946 if (chip->info->ops->port_set_jumbo_size) 2947 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 2948 else if (chip->info->ops->set_max_frame_size) 2949 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 2950 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 2951 } 2952 2953 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2954 { 2955 struct mv88e6xxx_chip *chip = ds->priv; 2956 int ret = 0; 2957 2958 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2959 new_mtu += EDSA_HLEN; 2960 2961 mv88e6xxx_reg_lock(chip); 2962 if (chip->info->ops->port_set_jumbo_size) 2963 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2964 else if (chip->info->ops->set_max_frame_size) 2965 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 2966 else 2967 if (new_mtu > 1522) 2968 ret = -EINVAL; 2969 mv88e6xxx_reg_unlock(chip); 2970 2971 return ret; 2972 } 2973 2974 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2975 struct phy_device *phydev) 2976 { 2977 struct mv88e6xxx_chip *chip = ds->priv; 2978 int err; 2979 2980 mv88e6xxx_reg_lock(chip); 2981 err = mv88e6xxx_serdes_power(chip, port, true); 2982 mv88e6xxx_reg_unlock(chip); 2983 2984 return err; 2985 } 2986 2987 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2988 { 2989 struct mv88e6xxx_chip *chip = ds->priv; 2990 2991 mv88e6xxx_reg_lock(chip); 2992 if (mv88e6xxx_serdes_power(chip, port, false)) 2993 dev_err(chip->dev, "failed to power off SERDES\n"); 2994 mv88e6xxx_reg_unlock(chip); 2995 } 2996 2997 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2998 unsigned int ageing_time) 2999 { 3000 struct mv88e6xxx_chip *chip = ds->priv; 3001 int err; 3002 3003 mv88e6xxx_reg_lock(chip); 3004 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3005 mv88e6xxx_reg_unlock(chip); 3006 3007 return err; 3008 } 3009 3010 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3011 { 3012 int err; 3013 3014 /* Initialize the statistics unit */ 3015 if (chip->info->ops->stats_set_histogram) { 3016 err = chip->info->ops->stats_set_histogram(chip); 3017 if (err) 3018 return err; 3019 } 3020 3021 return mv88e6xxx_g1_stats_clear(chip); 3022 } 3023 3024 /* Check if the errata has already been applied. */ 3025 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3026 { 3027 int port; 3028 int err; 3029 u16 val; 3030 3031 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3032 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3033 if (err) { 3034 dev_err(chip->dev, 3035 "Error reading hidden register: %d\n", err); 3036 return false; 3037 } 3038 if (val != 0x01c0) 3039 return false; 3040 } 3041 3042 return true; 3043 } 3044 3045 /* The 6390 copper ports have an errata which require poking magic 3046 * values into undocumented hidden registers and then performing a 3047 * software reset. 3048 */ 3049 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3050 { 3051 int port; 3052 int err; 3053 3054 if (mv88e6390_setup_errata_applied(chip)) 3055 return 0; 3056 3057 /* Set the ports into blocking mode */ 3058 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3059 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3060 if (err) 3061 return err; 3062 } 3063 3064 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3065 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3066 if (err) 3067 return err; 3068 } 3069 3070 return mv88e6xxx_software_reset(chip); 3071 } 3072 3073 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3074 { 3075 mv88e6xxx_teardown_devlink_params(ds); 3076 dsa_devlink_resources_unregister(ds); 3077 mv88e6xxx_teardown_devlink_regions_global(ds); 3078 } 3079 3080 static int mv88e6xxx_setup(struct dsa_switch *ds) 3081 { 3082 struct mv88e6xxx_chip *chip = ds->priv; 3083 u8 cmode; 3084 int err; 3085 int i; 3086 3087 chip->ds = ds; 3088 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3089 3090 /* Since virtual bridges are mapped in the PVT, the number we support 3091 * depends on the physical switch topology. We need to let DSA figure 3092 * that out and therefore we cannot set this at dsa_register_switch() 3093 * time. 3094 */ 3095 if (mv88e6xxx_has_pvt(chip)) 3096 ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3097 ds->dst->last_switch - 1; 3098 3099 mv88e6xxx_reg_lock(chip); 3100 3101 if (chip->info->ops->setup_errata) { 3102 err = chip->info->ops->setup_errata(chip); 3103 if (err) 3104 goto unlock; 3105 } 3106 3107 /* Cache the cmode of each port. */ 3108 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3109 if (chip->info->ops->port_get_cmode) { 3110 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3111 if (err) 3112 goto unlock; 3113 3114 chip->ports[i].cmode = cmode; 3115 } 3116 } 3117 3118 /* Setup Switch Port Registers */ 3119 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3120 if (dsa_is_unused_port(ds, i)) 3121 continue; 3122 3123 /* Prevent the use of an invalid port. */ 3124 if (mv88e6xxx_is_invalid_port(chip, i)) { 3125 dev_err(chip->dev, "port %d is invalid\n", i); 3126 err = -EINVAL; 3127 goto unlock; 3128 } 3129 3130 err = mv88e6xxx_setup_port(chip, i); 3131 if (err) 3132 goto unlock; 3133 } 3134 3135 err = mv88e6xxx_irl_setup(chip); 3136 if (err) 3137 goto unlock; 3138 3139 err = mv88e6xxx_mac_setup(chip); 3140 if (err) 3141 goto unlock; 3142 3143 err = mv88e6xxx_phy_setup(chip); 3144 if (err) 3145 goto unlock; 3146 3147 err = mv88e6xxx_vtu_setup(chip); 3148 if (err) 3149 goto unlock; 3150 3151 err = mv88e6xxx_pvt_setup(chip); 3152 if (err) 3153 goto unlock; 3154 3155 err = mv88e6xxx_atu_setup(chip); 3156 if (err) 3157 goto unlock; 3158 3159 err = mv88e6xxx_broadcast_setup(chip, 0); 3160 if (err) 3161 goto unlock; 3162 3163 err = mv88e6xxx_pot_setup(chip); 3164 if (err) 3165 goto unlock; 3166 3167 err = mv88e6xxx_rmu_setup(chip); 3168 if (err) 3169 goto unlock; 3170 3171 err = mv88e6xxx_rsvd2cpu_setup(chip); 3172 if (err) 3173 goto unlock; 3174 3175 err = mv88e6xxx_trunk_setup(chip); 3176 if (err) 3177 goto unlock; 3178 3179 err = mv88e6xxx_devmap_setup(chip); 3180 if (err) 3181 goto unlock; 3182 3183 err = mv88e6xxx_pri_setup(chip); 3184 if (err) 3185 goto unlock; 3186 3187 /* Setup PTP Hardware Clock and timestamping */ 3188 if (chip->info->ptp_support) { 3189 err = mv88e6xxx_ptp_setup(chip); 3190 if (err) 3191 goto unlock; 3192 3193 err = mv88e6xxx_hwtstamp_setup(chip); 3194 if (err) 3195 goto unlock; 3196 } 3197 3198 err = mv88e6xxx_stats_setup(chip); 3199 if (err) 3200 goto unlock; 3201 3202 unlock: 3203 mv88e6xxx_reg_unlock(chip); 3204 3205 if (err) 3206 return err; 3207 3208 /* Have to be called without holding the register lock, since 3209 * they take the devlink lock, and we later take the locks in 3210 * the reverse order when getting/setting parameters or 3211 * resource occupancy. 3212 */ 3213 err = mv88e6xxx_setup_devlink_resources(ds); 3214 if (err) 3215 return err; 3216 3217 err = mv88e6xxx_setup_devlink_params(ds); 3218 if (err) 3219 goto out_resources; 3220 3221 err = mv88e6xxx_setup_devlink_regions_global(ds); 3222 if (err) 3223 goto out_params; 3224 3225 return 0; 3226 3227 out_params: 3228 mv88e6xxx_teardown_devlink_params(ds); 3229 out_resources: 3230 dsa_devlink_resources_unregister(ds); 3231 3232 return err; 3233 } 3234 3235 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3236 { 3237 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3238 } 3239 3240 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3241 { 3242 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3243 } 3244 3245 /* prod_id for switch families which do not have a PHY model number */ 3246 static const u16 family_prod_id_table[] = { 3247 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3248 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3249 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3250 }; 3251 3252 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3253 { 3254 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3255 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3256 u16 prod_id; 3257 u16 val; 3258 int err; 3259 3260 if (!chip->info->ops->phy_read) 3261 return -EOPNOTSUPP; 3262 3263 mv88e6xxx_reg_lock(chip); 3264 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3265 mv88e6xxx_reg_unlock(chip); 3266 3267 /* Some internal PHYs don't have a model number. */ 3268 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3269 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3270 prod_id = family_prod_id_table[chip->info->family]; 3271 if (prod_id) 3272 val |= prod_id >> 4; 3273 } 3274 3275 return err ? err : val; 3276 } 3277 3278 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3279 { 3280 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3281 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3282 int err; 3283 3284 if (!chip->info->ops->phy_write) 3285 return -EOPNOTSUPP; 3286 3287 mv88e6xxx_reg_lock(chip); 3288 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3289 mv88e6xxx_reg_unlock(chip); 3290 3291 return err; 3292 } 3293 3294 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3295 struct device_node *np, 3296 bool external) 3297 { 3298 static int index; 3299 struct mv88e6xxx_mdio_bus *mdio_bus; 3300 struct mii_bus *bus; 3301 int err; 3302 3303 if (external) { 3304 mv88e6xxx_reg_lock(chip); 3305 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3306 mv88e6xxx_reg_unlock(chip); 3307 3308 if (err) 3309 return err; 3310 } 3311 3312 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3313 if (!bus) 3314 return -ENOMEM; 3315 3316 mdio_bus = bus->priv; 3317 mdio_bus->bus = bus; 3318 mdio_bus->chip = chip; 3319 INIT_LIST_HEAD(&mdio_bus->list); 3320 mdio_bus->external = external; 3321 3322 if (np) { 3323 bus->name = np->full_name; 3324 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3325 } else { 3326 bus->name = "mv88e6xxx SMI"; 3327 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3328 } 3329 3330 bus->read = mv88e6xxx_mdio_read; 3331 bus->write = mv88e6xxx_mdio_write; 3332 bus->parent = chip->dev; 3333 3334 if (!external) { 3335 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3336 if (err) 3337 return err; 3338 } 3339 3340 err = of_mdiobus_register(bus, np); 3341 if (err) { 3342 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3343 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3344 return err; 3345 } 3346 3347 if (external) 3348 list_add_tail(&mdio_bus->list, &chip->mdios); 3349 else 3350 list_add(&mdio_bus->list, &chip->mdios); 3351 3352 return 0; 3353 } 3354 3355 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3356 3357 { 3358 struct mv88e6xxx_mdio_bus *mdio_bus; 3359 struct mii_bus *bus; 3360 3361 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3362 bus = mdio_bus->bus; 3363 3364 if (!mdio_bus->external) 3365 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3366 3367 mdiobus_unregister(bus); 3368 } 3369 } 3370 3371 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3372 struct device_node *np) 3373 { 3374 struct device_node *child; 3375 int err; 3376 3377 /* Always register one mdio bus for the internal/default mdio 3378 * bus. This maybe represented in the device tree, but is 3379 * optional. 3380 */ 3381 child = of_get_child_by_name(np, "mdio"); 3382 err = mv88e6xxx_mdio_register(chip, child, false); 3383 if (err) 3384 return err; 3385 3386 /* Walk the device tree, and see if there are any other nodes 3387 * which say they are compatible with the external mdio 3388 * bus. 3389 */ 3390 for_each_available_child_of_node(np, child) { 3391 if (of_device_is_compatible( 3392 child, "marvell,mv88e6xxx-mdio-external")) { 3393 err = mv88e6xxx_mdio_register(chip, child, true); 3394 if (err) { 3395 mv88e6xxx_mdios_unregister(chip); 3396 of_node_put(child); 3397 return err; 3398 } 3399 } 3400 } 3401 3402 return 0; 3403 } 3404 3405 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3406 { 3407 struct mv88e6xxx_chip *chip = ds->priv; 3408 3409 return chip->eeprom_len; 3410 } 3411 3412 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3413 struct ethtool_eeprom *eeprom, u8 *data) 3414 { 3415 struct mv88e6xxx_chip *chip = ds->priv; 3416 int err; 3417 3418 if (!chip->info->ops->get_eeprom) 3419 return -EOPNOTSUPP; 3420 3421 mv88e6xxx_reg_lock(chip); 3422 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3423 mv88e6xxx_reg_unlock(chip); 3424 3425 if (err) 3426 return err; 3427 3428 eeprom->magic = 0xc3ec4951; 3429 3430 return 0; 3431 } 3432 3433 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3434 struct ethtool_eeprom *eeprom, u8 *data) 3435 { 3436 struct mv88e6xxx_chip *chip = ds->priv; 3437 int err; 3438 3439 if (!chip->info->ops->set_eeprom) 3440 return -EOPNOTSUPP; 3441 3442 if (eeprom->magic != 0xc3ec4951) 3443 return -EINVAL; 3444 3445 mv88e6xxx_reg_lock(chip); 3446 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3447 mv88e6xxx_reg_unlock(chip); 3448 3449 return err; 3450 } 3451 3452 static const struct mv88e6xxx_ops mv88e6085_ops = { 3453 /* MV88E6XXX_FAMILY_6097 */ 3454 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3455 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3456 .irl_init_all = mv88e6352_g2_irl_init_all, 3457 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3458 .phy_read = mv88e6185_phy_ppu_read, 3459 .phy_write = mv88e6185_phy_ppu_write, 3460 .port_set_link = mv88e6xxx_port_set_link, 3461 .port_sync_link = mv88e6xxx_port_sync_link, 3462 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3463 .port_tag_remap = mv88e6095_port_tag_remap, 3464 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3465 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3466 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3467 .port_set_ether_type = mv88e6351_port_set_ether_type, 3468 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3469 .port_pause_limit = mv88e6097_port_pause_limit, 3470 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3471 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3472 .port_get_cmode = mv88e6185_port_get_cmode, 3473 .port_setup_message_port = mv88e6xxx_setup_message_port, 3474 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3475 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3476 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3477 .stats_get_strings = mv88e6095_stats_get_strings, 3478 .stats_get_stats = mv88e6095_stats_get_stats, 3479 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3480 .set_egress_port = mv88e6095_g1_set_egress_port, 3481 .watchdog_ops = &mv88e6097_watchdog_ops, 3482 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3483 .pot_clear = mv88e6xxx_g2_pot_clear, 3484 .ppu_enable = mv88e6185_g1_ppu_enable, 3485 .ppu_disable = mv88e6185_g1_ppu_disable, 3486 .reset = mv88e6185_g1_reset, 3487 .rmu_disable = mv88e6085_g1_rmu_disable, 3488 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3489 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3490 .phylink_validate = mv88e6185_phylink_validate, 3491 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3492 }; 3493 3494 static const struct mv88e6xxx_ops mv88e6095_ops = { 3495 /* MV88E6XXX_FAMILY_6095 */ 3496 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3497 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3498 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3499 .phy_read = mv88e6185_phy_ppu_read, 3500 .phy_write = mv88e6185_phy_ppu_write, 3501 .port_set_link = mv88e6xxx_port_set_link, 3502 .port_sync_link = mv88e6185_port_sync_link, 3503 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3504 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3505 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3506 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3507 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3508 .port_get_cmode = mv88e6185_port_get_cmode, 3509 .port_setup_message_port = mv88e6xxx_setup_message_port, 3510 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3511 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3512 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3513 .stats_get_strings = mv88e6095_stats_get_strings, 3514 .stats_get_stats = mv88e6095_stats_get_stats, 3515 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3516 .serdes_power = mv88e6185_serdes_power, 3517 .serdes_get_lane = mv88e6185_serdes_get_lane, 3518 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3519 .ppu_enable = mv88e6185_g1_ppu_enable, 3520 .ppu_disable = mv88e6185_g1_ppu_disable, 3521 .reset = mv88e6185_g1_reset, 3522 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3523 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3524 .phylink_validate = mv88e6185_phylink_validate, 3525 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3526 }; 3527 3528 static const struct mv88e6xxx_ops mv88e6097_ops = { 3529 /* MV88E6XXX_FAMILY_6097 */ 3530 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3531 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3532 .irl_init_all = mv88e6352_g2_irl_init_all, 3533 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3534 .phy_read = mv88e6xxx_g2_smi_phy_read, 3535 .phy_write = mv88e6xxx_g2_smi_phy_write, 3536 .port_set_link = mv88e6xxx_port_set_link, 3537 .port_sync_link = mv88e6185_port_sync_link, 3538 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3539 .port_tag_remap = mv88e6095_port_tag_remap, 3540 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3541 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3542 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3543 .port_set_ether_type = mv88e6351_port_set_ether_type, 3544 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3545 .port_pause_limit = mv88e6097_port_pause_limit, 3546 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3547 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3548 .port_get_cmode = mv88e6185_port_get_cmode, 3549 .port_setup_message_port = mv88e6xxx_setup_message_port, 3550 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3551 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3552 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3553 .stats_get_strings = mv88e6095_stats_get_strings, 3554 .stats_get_stats = mv88e6095_stats_get_stats, 3555 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3556 .set_egress_port = mv88e6095_g1_set_egress_port, 3557 .watchdog_ops = &mv88e6097_watchdog_ops, 3558 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3559 .serdes_power = mv88e6185_serdes_power, 3560 .serdes_get_lane = mv88e6185_serdes_get_lane, 3561 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3562 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3563 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3564 .serdes_irq_status = mv88e6097_serdes_irq_status, 3565 .pot_clear = mv88e6xxx_g2_pot_clear, 3566 .reset = mv88e6352_g1_reset, 3567 .rmu_disable = mv88e6085_g1_rmu_disable, 3568 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3569 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3570 .phylink_validate = mv88e6185_phylink_validate, 3571 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3572 }; 3573 3574 static const struct mv88e6xxx_ops mv88e6123_ops = { 3575 /* MV88E6XXX_FAMILY_6165 */ 3576 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3577 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3578 .irl_init_all = mv88e6352_g2_irl_init_all, 3579 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3580 .phy_read = mv88e6xxx_g2_smi_phy_read, 3581 .phy_write = mv88e6xxx_g2_smi_phy_write, 3582 .port_set_link = mv88e6xxx_port_set_link, 3583 .port_sync_link = mv88e6xxx_port_sync_link, 3584 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3585 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3586 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3587 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3588 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3589 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3590 .port_get_cmode = mv88e6185_port_get_cmode, 3591 .port_setup_message_port = mv88e6xxx_setup_message_port, 3592 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3593 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3594 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3595 .stats_get_strings = mv88e6095_stats_get_strings, 3596 .stats_get_stats = mv88e6095_stats_get_stats, 3597 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3598 .set_egress_port = mv88e6095_g1_set_egress_port, 3599 .watchdog_ops = &mv88e6097_watchdog_ops, 3600 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3601 .pot_clear = mv88e6xxx_g2_pot_clear, 3602 .reset = mv88e6352_g1_reset, 3603 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3604 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3605 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3606 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3607 .phylink_validate = mv88e6185_phylink_validate, 3608 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3609 }; 3610 3611 static const struct mv88e6xxx_ops mv88e6131_ops = { 3612 /* MV88E6XXX_FAMILY_6185 */ 3613 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3614 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3615 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3616 .phy_read = mv88e6185_phy_ppu_read, 3617 .phy_write = mv88e6185_phy_ppu_write, 3618 .port_set_link = mv88e6xxx_port_set_link, 3619 .port_sync_link = mv88e6xxx_port_sync_link, 3620 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3621 .port_tag_remap = mv88e6095_port_tag_remap, 3622 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3623 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3624 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3625 .port_set_ether_type = mv88e6351_port_set_ether_type, 3626 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3627 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3628 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3629 .port_pause_limit = mv88e6097_port_pause_limit, 3630 .port_set_pause = mv88e6185_port_set_pause, 3631 .port_get_cmode = mv88e6185_port_get_cmode, 3632 .port_setup_message_port = mv88e6xxx_setup_message_port, 3633 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3634 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3635 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3636 .stats_get_strings = mv88e6095_stats_get_strings, 3637 .stats_get_stats = mv88e6095_stats_get_stats, 3638 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3639 .set_egress_port = mv88e6095_g1_set_egress_port, 3640 .watchdog_ops = &mv88e6097_watchdog_ops, 3641 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3642 .ppu_enable = mv88e6185_g1_ppu_enable, 3643 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3644 .ppu_disable = mv88e6185_g1_ppu_disable, 3645 .reset = mv88e6185_g1_reset, 3646 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3647 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3648 .phylink_validate = mv88e6185_phylink_validate, 3649 }; 3650 3651 static const struct mv88e6xxx_ops mv88e6141_ops = { 3652 /* MV88E6XXX_FAMILY_6341 */ 3653 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3654 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3655 .irl_init_all = mv88e6352_g2_irl_init_all, 3656 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3657 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3658 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3659 .phy_read = mv88e6xxx_g2_smi_phy_read, 3660 .phy_write = mv88e6xxx_g2_smi_phy_write, 3661 .port_set_link = mv88e6xxx_port_set_link, 3662 .port_sync_link = mv88e6xxx_port_sync_link, 3663 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3664 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3665 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3666 .port_tag_remap = mv88e6095_port_tag_remap, 3667 .port_set_policy = mv88e6352_port_set_policy, 3668 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3669 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3670 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3671 .port_set_ether_type = mv88e6351_port_set_ether_type, 3672 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3673 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3674 .port_pause_limit = mv88e6097_port_pause_limit, 3675 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3676 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3677 .port_get_cmode = mv88e6352_port_get_cmode, 3678 .port_set_cmode = mv88e6341_port_set_cmode, 3679 .port_setup_message_port = mv88e6xxx_setup_message_port, 3680 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3681 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3682 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3683 .stats_get_strings = mv88e6320_stats_get_strings, 3684 .stats_get_stats = mv88e6390_stats_get_stats, 3685 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3686 .set_egress_port = mv88e6390_g1_set_egress_port, 3687 .watchdog_ops = &mv88e6390_watchdog_ops, 3688 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3689 .pot_clear = mv88e6xxx_g2_pot_clear, 3690 .reset = mv88e6352_g1_reset, 3691 .rmu_disable = mv88e6390_g1_rmu_disable, 3692 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3693 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3694 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3695 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3696 .serdes_power = mv88e6390_serdes_power, 3697 .serdes_get_lane = mv88e6341_serdes_get_lane, 3698 /* Check status register pause & lpa register */ 3699 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3700 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3701 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3702 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3703 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3704 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3705 .serdes_irq_status = mv88e6390_serdes_irq_status, 3706 .gpio_ops = &mv88e6352_gpio_ops, 3707 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3708 .serdes_get_strings = mv88e6390_serdes_get_strings, 3709 .serdes_get_stats = mv88e6390_serdes_get_stats, 3710 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3711 .serdes_get_regs = mv88e6390_serdes_get_regs, 3712 .phylink_validate = mv88e6341_phylink_validate, 3713 }; 3714 3715 static const struct mv88e6xxx_ops mv88e6161_ops = { 3716 /* MV88E6XXX_FAMILY_6165 */ 3717 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3718 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3719 .irl_init_all = mv88e6352_g2_irl_init_all, 3720 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3721 .phy_read = mv88e6xxx_g2_smi_phy_read, 3722 .phy_write = mv88e6xxx_g2_smi_phy_write, 3723 .port_set_link = mv88e6xxx_port_set_link, 3724 .port_sync_link = mv88e6xxx_port_sync_link, 3725 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3726 .port_tag_remap = mv88e6095_port_tag_remap, 3727 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3728 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3729 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3730 .port_set_ether_type = mv88e6351_port_set_ether_type, 3731 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3732 .port_pause_limit = mv88e6097_port_pause_limit, 3733 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3734 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3735 .port_get_cmode = mv88e6185_port_get_cmode, 3736 .port_setup_message_port = mv88e6xxx_setup_message_port, 3737 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3738 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3739 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3740 .stats_get_strings = mv88e6095_stats_get_strings, 3741 .stats_get_stats = mv88e6095_stats_get_stats, 3742 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3743 .set_egress_port = mv88e6095_g1_set_egress_port, 3744 .watchdog_ops = &mv88e6097_watchdog_ops, 3745 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3746 .pot_clear = mv88e6xxx_g2_pot_clear, 3747 .reset = mv88e6352_g1_reset, 3748 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3749 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3750 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3751 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3752 .avb_ops = &mv88e6165_avb_ops, 3753 .ptp_ops = &mv88e6165_ptp_ops, 3754 .phylink_validate = mv88e6185_phylink_validate, 3755 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3756 }; 3757 3758 static const struct mv88e6xxx_ops mv88e6165_ops = { 3759 /* MV88E6XXX_FAMILY_6165 */ 3760 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3761 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3762 .irl_init_all = mv88e6352_g2_irl_init_all, 3763 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3764 .phy_read = mv88e6165_phy_read, 3765 .phy_write = mv88e6165_phy_write, 3766 .port_set_link = mv88e6xxx_port_set_link, 3767 .port_sync_link = mv88e6xxx_port_sync_link, 3768 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3769 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3770 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3771 .port_get_cmode = mv88e6185_port_get_cmode, 3772 .port_setup_message_port = mv88e6xxx_setup_message_port, 3773 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3774 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3775 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3776 .stats_get_strings = mv88e6095_stats_get_strings, 3777 .stats_get_stats = mv88e6095_stats_get_stats, 3778 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3779 .set_egress_port = mv88e6095_g1_set_egress_port, 3780 .watchdog_ops = &mv88e6097_watchdog_ops, 3781 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3782 .pot_clear = mv88e6xxx_g2_pot_clear, 3783 .reset = mv88e6352_g1_reset, 3784 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3785 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3786 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3787 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3788 .avb_ops = &mv88e6165_avb_ops, 3789 .ptp_ops = &mv88e6165_ptp_ops, 3790 .phylink_validate = mv88e6185_phylink_validate, 3791 }; 3792 3793 static const struct mv88e6xxx_ops mv88e6171_ops = { 3794 /* MV88E6XXX_FAMILY_6351 */ 3795 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3796 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3797 .irl_init_all = mv88e6352_g2_irl_init_all, 3798 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3799 .phy_read = mv88e6xxx_g2_smi_phy_read, 3800 .phy_write = mv88e6xxx_g2_smi_phy_write, 3801 .port_set_link = mv88e6xxx_port_set_link, 3802 .port_sync_link = mv88e6xxx_port_sync_link, 3803 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3804 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3805 .port_tag_remap = mv88e6095_port_tag_remap, 3806 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3807 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3808 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3809 .port_set_ether_type = mv88e6351_port_set_ether_type, 3810 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3811 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3812 .port_pause_limit = mv88e6097_port_pause_limit, 3813 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3814 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3815 .port_get_cmode = mv88e6352_port_get_cmode, 3816 .port_setup_message_port = mv88e6xxx_setup_message_port, 3817 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3818 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3819 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3820 .stats_get_strings = mv88e6095_stats_get_strings, 3821 .stats_get_stats = mv88e6095_stats_get_stats, 3822 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3823 .set_egress_port = mv88e6095_g1_set_egress_port, 3824 .watchdog_ops = &mv88e6097_watchdog_ops, 3825 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3826 .pot_clear = mv88e6xxx_g2_pot_clear, 3827 .reset = mv88e6352_g1_reset, 3828 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3829 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3830 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3831 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3832 .phylink_validate = mv88e6185_phylink_validate, 3833 }; 3834 3835 static const struct mv88e6xxx_ops mv88e6172_ops = { 3836 /* MV88E6XXX_FAMILY_6352 */ 3837 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3838 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3839 .irl_init_all = mv88e6352_g2_irl_init_all, 3840 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3841 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3842 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3843 .phy_read = mv88e6xxx_g2_smi_phy_read, 3844 .phy_write = mv88e6xxx_g2_smi_phy_write, 3845 .port_set_link = mv88e6xxx_port_set_link, 3846 .port_sync_link = mv88e6xxx_port_sync_link, 3847 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3848 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3849 .port_tag_remap = mv88e6095_port_tag_remap, 3850 .port_set_policy = mv88e6352_port_set_policy, 3851 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3852 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3853 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3854 .port_set_ether_type = mv88e6351_port_set_ether_type, 3855 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3856 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3857 .port_pause_limit = mv88e6097_port_pause_limit, 3858 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3859 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3860 .port_get_cmode = mv88e6352_port_get_cmode, 3861 .port_setup_message_port = mv88e6xxx_setup_message_port, 3862 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3863 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3864 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3865 .stats_get_strings = mv88e6095_stats_get_strings, 3866 .stats_get_stats = mv88e6095_stats_get_stats, 3867 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3868 .set_egress_port = mv88e6095_g1_set_egress_port, 3869 .watchdog_ops = &mv88e6097_watchdog_ops, 3870 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3871 .pot_clear = mv88e6xxx_g2_pot_clear, 3872 .reset = mv88e6352_g1_reset, 3873 .rmu_disable = mv88e6352_g1_rmu_disable, 3874 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3875 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3876 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3877 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3878 .serdes_get_lane = mv88e6352_serdes_get_lane, 3879 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3880 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3881 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3882 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3883 .serdes_power = mv88e6352_serdes_power, 3884 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3885 .serdes_get_regs = mv88e6352_serdes_get_regs, 3886 .gpio_ops = &mv88e6352_gpio_ops, 3887 .phylink_validate = mv88e6352_phylink_validate, 3888 }; 3889 3890 static const struct mv88e6xxx_ops mv88e6175_ops = { 3891 /* MV88E6XXX_FAMILY_6351 */ 3892 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3893 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3894 .irl_init_all = mv88e6352_g2_irl_init_all, 3895 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3896 .phy_read = mv88e6xxx_g2_smi_phy_read, 3897 .phy_write = mv88e6xxx_g2_smi_phy_write, 3898 .port_set_link = mv88e6xxx_port_set_link, 3899 .port_sync_link = mv88e6xxx_port_sync_link, 3900 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3901 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3902 .port_tag_remap = mv88e6095_port_tag_remap, 3903 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3904 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3905 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3906 .port_set_ether_type = mv88e6351_port_set_ether_type, 3907 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3908 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3909 .port_pause_limit = mv88e6097_port_pause_limit, 3910 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3911 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3912 .port_get_cmode = mv88e6352_port_get_cmode, 3913 .port_setup_message_port = mv88e6xxx_setup_message_port, 3914 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3915 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3916 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3917 .stats_get_strings = mv88e6095_stats_get_strings, 3918 .stats_get_stats = mv88e6095_stats_get_stats, 3919 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3920 .set_egress_port = mv88e6095_g1_set_egress_port, 3921 .watchdog_ops = &mv88e6097_watchdog_ops, 3922 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3923 .pot_clear = mv88e6xxx_g2_pot_clear, 3924 .reset = mv88e6352_g1_reset, 3925 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3926 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3927 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3928 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3929 .phylink_validate = mv88e6185_phylink_validate, 3930 }; 3931 3932 static const struct mv88e6xxx_ops mv88e6176_ops = { 3933 /* MV88E6XXX_FAMILY_6352 */ 3934 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3935 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3936 .irl_init_all = mv88e6352_g2_irl_init_all, 3937 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3938 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3939 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3940 .phy_read = mv88e6xxx_g2_smi_phy_read, 3941 .phy_write = mv88e6xxx_g2_smi_phy_write, 3942 .port_set_link = mv88e6xxx_port_set_link, 3943 .port_sync_link = mv88e6xxx_port_sync_link, 3944 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3945 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3946 .port_tag_remap = mv88e6095_port_tag_remap, 3947 .port_set_policy = mv88e6352_port_set_policy, 3948 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3949 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3950 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3951 .port_set_ether_type = mv88e6351_port_set_ether_type, 3952 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3953 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3954 .port_pause_limit = mv88e6097_port_pause_limit, 3955 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3956 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3957 .port_get_cmode = mv88e6352_port_get_cmode, 3958 .port_setup_message_port = mv88e6xxx_setup_message_port, 3959 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3960 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3961 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3962 .stats_get_strings = mv88e6095_stats_get_strings, 3963 .stats_get_stats = mv88e6095_stats_get_stats, 3964 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3965 .set_egress_port = mv88e6095_g1_set_egress_port, 3966 .watchdog_ops = &mv88e6097_watchdog_ops, 3967 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3968 .pot_clear = mv88e6xxx_g2_pot_clear, 3969 .reset = mv88e6352_g1_reset, 3970 .rmu_disable = mv88e6352_g1_rmu_disable, 3971 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3972 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3973 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3974 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3975 .serdes_get_lane = mv88e6352_serdes_get_lane, 3976 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3977 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3978 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3979 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3980 .serdes_power = mv88e6352_serdes_power, 3981 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3982 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3983 .serdes_irq_status = mv88e6352_serdes_irq_status, 3984 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3985 .serdes_get_regs = mv88e6352_serdes_get_regs, 3986 .gpio_ops = &mv88e6352_gpio_ops, 3987 .phylink_validate = mv88e6352_phylink_validate, 3988 }; 3989 3990 static const struct mv88e6xxx_ops mv88e6185_ops = { 3991 /* MV88E6XXX_FAMILY_6185 */ 3992 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3993 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3994 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3995 .phy_read = mv88e6185_phy_ppu_read, 3996 .phy_write = mv88e6185_phy_ppu_write, 3997 .port_set_link = mv88e6xxx_port_set_link, 3998 .port_sync_link = mv88e6185_port_sync_link, 3999 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4000 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4001 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4002 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4003 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4004 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4005 .port_set_pause = mv88e6185_port_set_pause, 4006 .port_get_cmode = mv88e6185_port_get_cmode, 4007 .port_setup_message_port = mv88e6xxx_setup_message_port, 4008 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4009 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4010 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4011 .stats_get_strings = mv88e6095_stats_get_strings, 4012 .stats_get_stats = mv88e6095_stats_get_stats, 4013 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4014 .set_egress_port = mv88e6095_g1_set_egress_port, 4015 .watchdog_ops = &mv88e6097_watchdog_ops, 4016 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4017 .serdes_power = mv88e6185_serdes_power, 4018 .serdes_get_lane = mv88e6185_serdes_get_lane, 4019 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4020 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4021 .ppu_enable = mv88e6185_g1_ppu_enable, 4022 .ppu_disable = mv88e6185_g1_ppu_disable, 4023 .reset = mv88e6185_g1_reset, 4024 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4025 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4026 .phylink_validate = mv88e6185_phylink_validate, 4027 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4028 }; 4029 4030 static const struct mv88e6xxx_ops mv88e6190_ops = { 4031 /* MV88E6XXX_FAMILY_6390 */ 4032 .setup_errata = mv88e6390_setup_errata, 4033 .irl_init_all = mv88e6390_g2_irl_init_all, 4034 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4035 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4037 .phy_read = mv88e6xxx_g2_smi_phy_read, 4038 .phy_write = mv88e6xxx_g2_smi_phy_write, 4039 .port_set_link = mv88e6xxx_port_set_link, 4040 .port_sync_link = mv88e6xxx_port_sync_link, 4041 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4042 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4043 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4044 .port_tag_remap = mv88e6390_port_tag_remap, 4045 .port_set_policy = mv88e6352_port_set_policy, 4046 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4047 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4048 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4049 .port_set_ether_type = mv88e6351_port_set_ether_type, 4050 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4051 .port_pause_limit = mv88e6390_port_pause_limit, 4052 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4053 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4054 .port_get_cmode = mv88e6352_port_get_cmode, 4055 .port_set_cmode = mv88e6390_port_set_cmode, 4056 .port_setup_message_port = mv88e6xxx_setup_message_port, 4057 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4058 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4059 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4060 .stats_get_strings = mv88e6320_stats_get_strings, 4061 .stats_get_stats = mv88e6390_stats_get_stats, 4062 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4063 .set_egress_port = mv88e6390_g1_set_egress_port, 4064 .watchdog_ops = &mv88e6390_watchdog_ops, 4065 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4066 .pot_clear = mv88e6xxx_g2_pot_clear, 4067 .reset = mv88e6352_g1_reset, 4068 .rmu_disable = mv88e6390_g1_rmu_disable, 4069 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4070 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4071 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4072 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4073 .serdes_power = mv88e6390_serdes_power, 4074 .serdes_get_lane = mv88e6390_serdes_get_lane, 4075 /* Check status register pause & lpa register */ 4076 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4077 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4078 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4079 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4080 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4081 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4082 .serdes_irq_status = mv88e6390_serdes_irq_status, 4083 .serdes_get_strings = mv88e6390_serdes_get_strings, 4084 .serdes_get_stats = mv88e6390_serdes_get_stats, 4085 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4086 .serdes_get_regs = mv88e6390_serdes_get_regs, 4087 .gpio_ops = &mv88e6352_gpio_ops, 4088 .phylink_validate = mv88e6390_phylink_validate, 4089 }; 4090 4091 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4092 /* MV88E6XXX_FAMILY_6390 */ 4093 .setup_errata = mv88e6390_setup_errata, 4094 .irl_init_all = mv88e6390_g2_irl_init_all, 4095 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4096 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4097 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4098 .phy_read = mv88e6xxx_g2_smi_phy_read, 4099 .phy_write = mv88e6xxx_g2_smi_phy_write, 4100 .port_set_link = mv88e6xxx_port_set_link, 4101 .port_sync_link = mv88e6xxx_port_sync_link, 4102 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4103 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4104 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4105 .port_tag_remap = mv88e6390_port_tag_remap, 4106 .port_set_policy = mv88e6352_port_set_policy, 4107 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4108 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4109 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4110 .port_set_ether_type = mv88e6351_port_set_ether_type, 4111 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4112 .port_pause_limit = mv88e6390_port_pause_limit, 4113 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4114 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4115 .port_get_cmode = mv88e6352_port_get_cmode, 4116 .port_set_cmode = mv88e6390x_port_set_cmode, 4117 .port_setup_message_port = mv88e6xxx_setup_message_port, 4118 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4119 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4120 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4121 .stats_get_strings = mv88e6320_stats_get_strings, 4122 .stats_get_stats = mv88e6390_stats_get_stats, 4123 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4124 .set_egress_port = mv88e6390_g1_set_egress_port, 4125 .watchdog_ops = &mv88e6390_watchdog_ops, 4126 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4127 .pot_clear = mv88e6xxx_g2_pot_clear, 4128 .reset = mv88e6352_g1_reset, 4129 .rmu_disable = mv88e6390_g1_rmu_disable, 4130 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4131 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4132 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4133 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4134 .serdes_power = mv88e6390_serdes_power, 4135 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4136 /* Check status register pause & lpa register */ 4137 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4138 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4139 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4140 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4141 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4142 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4143 .serdes_irq_status = mv88e6390_serdes_irq_status, 4144 .serdes_get_strings = mv88e6390_serdes_get_strings, 4145 .serdes_get_stats = mv88e6390_serdes_get_stats, 4146 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4147 .serdes_get_regs = mv88e6390_serdes_get_regs, 4148 .gpio_ops = &mv88e6352_gpio_ops, 4149 .phylink_validate = mv88e6390x_phylink_validate, 4150 }; 4151 4152 static const struct mv88e6xxx_ops mv88e6191_ops = { 4153 /* MV88E6XXX_FAMILY_6390 */ 4154 .setup_errata = mv88e6390_setup_errata, 4155 .irl_init_all = mv88e6390_g2_irl_init_all, 4156 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4157 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4158 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4159 .phy_read = mv88e6xxx_g2_smi_phy_read, 4160 .phy_write = mv88e6xxx_g2_smi_phy_write, 4161 .port_set_link = mv88e6xxx_port_set_link, 4162 .port_sync_link = mv88e6xxx_port_sync_link, 4163 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4164 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4165 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4166 .port_tag_remap = mv88e6390_port_tag_remap, 4167 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4168 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4169 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4170 .port_set_ether_type = mv88e6351_port_set_ether_type, 4171 .port_pause_limit = mv88e6390_port_pause_limit, 4172 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4173 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4174 .port_get_cmode = mv88e6352_port_get_cmode, 4175 .port_set_cmode = mv88e6390_port_set_cmode, 4176 .port_setup_message_port = mv88e6xxx_setup_message_port, 4177 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4178 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4179 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4180 .stats_get_strings = mv88e6320_stats_get_strings, 4181 .stats_get_stats = mv88e6390_stats_get_stats, 4182 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4183 .set_egress_port = mv88e6390_g1_set_egress_port, 4184 .watchdog_ops = &mv88e6390_watchdog_ops, 4185 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4186 .pot_clear = mv88e6xxx_g2_pot_clear, 4187 .reset = mv88e6352_g1_reset, 4188 .rmu_disable = mv88e6390_g1_rmu_disable, 4189 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4190 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4191 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4192 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4193 .serdes_power = mv88e6390_serdes_power, 4194 .serdes_get_lane = mv88e6390_serdes_get_lane, 4195 /* Check status register pause & lpa register */ 4196 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4197 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4198 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4199 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4200 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4201 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4202 .serdes_irq_status = mv88e6390_serdes_irq_status, 4203 .serdes_get_strings = mv88e6390_serdes_get_strings, 4204 .serdes_get_stats = mv88e6390_serdes_get_stats, 4205 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4206 .serdes_get_regs = mv88e6390_serdes_get_regs, 4207 .avb_ops = &mv88e6390_avb_ops, 4208 .ptp_ops = &mv88e6352_ptp_ops, 4209 .phylink_validate = mv88e6390_phylink_validate, 4210 }; 4211 4212 static const struct mv88e6xxx_ops mv88e6240_ops = { 4213 /* MV88E6XXX_FAMILY_6352 */ 4214 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4215 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4216 .irl_init_all = mv88e6352_g2_irl_init_all, 4217 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4218 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4219 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4220 .phy_read = mv88e6xxx_g2_smi_phy_read, 4221 .phy_write = mv88e6xxx_g2_smi_phy_write, 4222 .port_set_link = mv88e6xxx_port_set_link, 4223 .port_sync_link = mv88e6xxx_port_sync_link, 4224 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4225 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4226 .port_tag_remap = mv88e6095_port_tag_remap, 4227 .port_set_policy = mv88e6352_port_set_policy, 4228 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4229 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4230 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4231 .port_set_ether_type = mv88e6351_port_set_ether_type, 4232 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4233 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4234 .port_pause_limit = mv88e6097_port_pause_limit, 4235 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4236 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4237 .port_get_cmode = mv88e6352_port_get_cmode, 4238 .port_setup_message_port = mv88e6xxx_setup_message_port, 4239 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4240 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4241 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4242 .stats_get_strings = mv88e6095_stats_get_strings, 4243 .stats_get_stats = mv88e6095_stats_get_stats, 4244 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4245 .set_egress_port = mv88e6095_g1_set_egress_port, 4246 .watchdog_ops = &mv88e6097_watchdog_ops, 4247 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4248 .pot_clear = mv88e6xxx_g2_pot_clear, 4249 .reset = mv88e6352_g1_reset, 4250 .rmu_disable = mv88e6352_g1_rmu_disable, 4251 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4252 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4253 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4254 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4255 .serdes_get_lane = mv88e6352_serdes_get_lane, 4256 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4257 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4258 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4259 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4260 .serdes_power = mv88e6352_serdes_power, 4261 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4262 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4263 .serdes_irq_status = mv88e6352_serdes_irq_status, 4264 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4265 .serdes_get_regs = mv88e6352_serdes_get_regs, 4266 .gpio_ops = &mv88e6352_gpio_ops, 4267 .avb_ops = &mv88e6352_avb_ops, 4268 .ptp_ops = &mv88e6352_ptp_ops, 4269 .phylink_validate = mv88e6352_phylink_validate, 4270 }; 4271 4272 static const struct mv88e6xxx_ops mv88e6250_ops = { 4273 /* MV88E6XXX_FAMILY_6250 */ 4274 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4275 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4276 .irl_init_all = mv88e6352_g2_irl_init_all, 4277 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4278 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4279 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4280 .phy_read = mv88e6xxx_g2_smi_phy_read, 4281 .phy_write = mv88e6xxx_g2_smi_phy_write, 4282 .port_set_link = mv88e6xxx_port_set_link, 4283 .port_sync_link = mv88e6xxx_port_sync_link, 4284 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4285 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4286 .port_tag_remap = mv88e6095_port_tag_remap, 4287 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4288 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4289 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4290 .port_set_ether_type = mv88e6351_port_set_ether_type, 4291 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4292 .port_pause_limit = mv88e6097_port_pause_limit, 4293 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4294 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4295 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4296 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4297 .stats_get_strings = mv88e6250_stats_get_strings, 4298 .stats_get_stats = mv88e6250_stats_get_stats, 4299 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4300 .set_egress_port = mv88e6095_g1_set_egress_port, 4301 .watchdog_ops = &mv88e6250_watchdog_ops, 4302 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4303 .pot_clear = mv88e6xxx_g2_pot_clear, 4304 .reset = mv88e6250_g1_reset, 4305 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4306 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4307 .avb_ops = &mv88e6352_avb_ops, 4308 .ptp_ops = &mv88e6250_ptp_ops, 4309 .phylink_validate = mv88e6065_phylink_validate, 4310 }; 4311 4312 static const struct mv88e6xxx_ops mv88e6290_ops = { 4313 /* MV88E6XXX_FAMILY_6390 */ 4314 .setup_errata = mv88e6390_setup_errata, 4315 .irl_init_all = mv88e6390_g2_irl_init_all, 4316 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4317 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4319 .phy_read = mv88e6xxx_g2_smi_phy_read, 4320 .phy_write = mv88e6xxx_g2_smi_phy_write, 4321 .port_set_link = mv88e6xxx_port_set_link, 4322 .port_sync_link = mv88e6xxx_port_sync_link, 4323 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4324 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4325 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4326 .port_tag_remap = mv88e6390_port_tag_remap, 4327 .port_set_policy = mv88e6352_port_set_policy, 4328 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4329 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4330 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4331 .port_set_ether_type = mv88e6351_port_set_ether_type, 4332 .port_pause_limit = mv88e6390_port_pause_limit, 4333 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4334 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4335 .port_get_cmode = mv88e6352_port_get_cmode, 4336 .port_set_cmode = mv88e6390_port_set_cmode, 4337 .port_setup_message_port = mv88e6xxx_setup_message_port, 4338 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4339 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4340 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4341 .stats_get_strings = mv88e6320_stats_get_strings, 4342 .stats_get_stats = mv88e6390_stats_get_stats, 4343 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4344 .set_egress_port = mv88e6390_g1_set_egress_port, 4345 .watchdog_ops = &mv88e6390_watchdog_ops, 4346 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4347 .pot_clear = mv88e6xxx_g2_pot_clear, 4348 .reset = mv88e6352_g1_reset, 4349 .rmu_disable = mv88e6390_g1_rmu_disable, 4350 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4351 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4352 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4353 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4354 .serdes_power = mv88e6390_serdes_power, 4355 .serdes_get_lane = mv88e6390_serdes_get_lane, 4356 /* Check status register pause & lpa register */ 4357 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4358 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4359 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4360 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4361 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4362 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4363 .serdes_irq_status = mv88e6390_serdes_irq_status, 4364 .serdes_get_strings = mv88e6390_serdes_get_strings, 4365 .serdes_get_stats = mv88e6390_serdes_get_stats, 4366 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4367 .serdes_get_regs = mv88e6390_serdes_get_regs, 4368 .gpio_ops = &mv88e6352_gpio_ops, 4369 .avb_ops = &mv88e6390_avb_ops, 4370 .ptp_ops = &mv88e6352_ptp_ops, 4371 .phylink_validate = mv88e6390_phylink_validate, 4372 }; 4373 4374 static const struct mv88e6xxx_ops mv88e6320_ops = { 4375 /* MV88E6XXX_FAMILY_6320 */ 4376 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4377 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4378 .irl_init_all = mv88e6352_g2_irl_init_all, 4379 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4380 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4381 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4382 .phy_read = mv88e6xxx_g2_smi_phy_read, 4383 .phy_write = mv88e6xxx_g2_smi_phy_write, 4384 .port_set_link = mv88e6xxx_port_set_link, 4385 .port_sync_link = mv88e6xxx_port_sync_link, 4386 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4387 .port_tag_remap = mv88e6095_port_tag_remap, 4388 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4389 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4390 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4391 .port_set_ether_type = mv88e6351_port_set_ether_type, 4392 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4393 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4394 .port_pause_limit = mv88e6097_port_pause_limit, 4395 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4396 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4397 .port_get_cmode = mv88e6352_port_get_cmode, 4398 .port_setup_message_port = mv88e6xxx_setup_message_port, 4399 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4400 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4401 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4402 .stats_get_strings = mv88e6320_stats_get_strings, 4403 .stats_get_stats = mv88e6320_stats_get_stats, 4404 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4405 .set_egress_port = mv88e6095_g1_set_egress_port, 4406 .watchdog_ops = &mv88e6390_watchdog_ops, 4407 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4408 .pot_clear = mv88e6xxx_g2_pot_clear, 4409 .reset = mv88e6352_g1_reset, 4410 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4411 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4412 .gpio_ops = &mv88e6352_gpio_ops, 4413 .avb_ops = &mv88e6352_avb_ops, 4414 .ptp_ops = &mv88e6352_ptp_ops, 4415 .phylink_validate = mv88e6185_phylink_validate, 4416 }; 4417 4418 static const struct mv88e6xxx_ops mv88e6321_ops = { 4419 /* MV88E6XXX_FAMILY_6320 */ 4420 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4421 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4422 .irl_init_all = mv88e6352_g2_irl_init_all, 4423 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4424 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4425 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4426 .phy_read = mv88e6xxx_g2_smi_phy_read, 4427 .phy_write = mv88e6xxx_g2_smi_phy_write, 4428 .port_set_link = mv88e6xxx_port_set_link, 4429 .port_sync_link = mv88e6xxx_port_sync_link, 4430 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4431 .port_tag_remap = mv88e6095_port_tag_remap, 4432 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4433 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4434 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4435 .port_set_ether_type = mv88e6351_port_set_ether_type, 4436 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4437 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4438 .port_pause_limit = mv88e6097_port_pause_limit, 4439 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4440 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4441 .port_get_cmode = mv88e6352_port_get_cmode, 4442 .port_setup_message_port = mv88e6xxx_setup_message_port, 4443 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4444 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4445 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4446 .stats_get_strings = mv88e6320_stats_get_strings, 4447 .stats_get_stats = mv88e6320_stats_get_stats, 4448 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4449 .set_egress_port = mv88e6095_g1_set_egress_port, 4450 .watchdog_ops = &mv88e6390_watchdog_ops, 4451 .reset = mv88e6352_g1_reset, 4452 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4453 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4454 .gpio_ops = &mv88e6352_gpio_ops, 4455 .avb_ops = &mv88e6352_avb_ops, 4456 .ptp_ops = &mv88e6352_ptp_ops, 4457 .phylink_validate = mv88e6185_phylink_validate, 4458 }; 4459 4460 static const struct mv88e6xxx_ops mv88e6341_ops = { 4461 /* MV88E6XXX_FAMILY_6341 */ 4462 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4463 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4464 .irl_init_all = mv88e6352_g2_irl_init_all, 4465 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4466 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4467 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4468 .phy_read = mv88e6xxx_g2_smi_phy_read, 4469 .phy_write = mv88e6xxx_g2_smi_phy_write, 4470 .port_set_link = mv88e6xxx_port_set_link, 4471 .port_sync_link = mv88e6xxx_port_sync_link, 4472 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4473 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4474 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4475 .port_tag_remap = mv88e6095_port_tag_remap, 4476 .port_set_policy = mv88e6352_port_set_policy, 4477 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4478 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4479 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4480 .port_set_ether_type = mv88e6351_port_set_ether_type, 4481 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4482 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4483 .port_pause_limit = mv88e6097_port_pause_limit, 4484 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4485 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4486 .port_get_cmode = mv88e6352_port_get_cmode, 4487 .port_set_cmode = mv88e6341_port_set_cmode, 4488 .port_setup_message_port = mv88e6xxx_setup_message_port, 4489 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4490 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4491 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4492 .stats_get_strings = mv88e6320_stats_get_strings, 4493 .stats_get_stats = mv88e6390_stats_get_stats, 4494 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4495 .set_egress_port = mv88e6390_g1_set_egress_port, 4496 .watchdog_ops = &mv88e6390_watchdog_ops, 4497 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4498 .pot_clear = mv88e6xxx_g2_pot_clear, 4499 .reset = mv88e6352_g1_reset, 4500 .rmu_disable = mv88e6390_g1_rmu_disable, 4501 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4502 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4503 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4504 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4505 .serdes_power = mv88e6390_serdes_power, 4506 .serdes_get_lane = mv88e6341_serdes_get_lane, 4507 /* Check status register pause & lpa register */ 4508 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4509 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4510 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4511 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4512 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4513 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4514 .serdes_irq_status = mv88e6390_serdes_irq_status, 4515 .gpio_ops = &mv88e6352_gpio_ops, 4516 .avb_ops = &mv88e6390_avb_ops, 4517 .ptp_ops = &mv88e6352_ptp_ops, 4518 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4519 .serdes_get_strings = mv88e6390_serdes_get_strings, 4520 .serdes_get_stats = mv88e6390_serdes_get_stats, 4521 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4522 .serdes_get_regs = mv88e6390_serdes_get_regs, 4523 .phylink_validate = mv88e6341_phylink_validate, 4524 }; 4525 4526 static const struct mv88e6xxx_ops mv88e6350_ops = { 4527 /* MV88E6XXX_FAMILY_6351 */ 4528 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4529 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4530 .irl_init_all = mv88e6352_g2_irl_init_all, 4531 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4532 .phy_read = mv88e6xxx_g2_smi_phy_read, 4533 .phy_write = mv88e6xxx_g2_smi_phy_write, 4534 .port_set_link = mv88e6xxx_port_set_link, 4535 .port_sync_link = mv88e6xxx_port_sync_link, 4536 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4537 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4538 .port_tag_remap = mv88e6095_port_tag_remap, 4539 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4540 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4541 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4542 .port_set_ether_type = mv88e6351_port_set_ether_type, 4543 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4544 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4545 .port_pause_limit = mv88e6097_port_pause_limit, 4546 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4547 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4548 .port_get_cmode = mv88e6352_port_get_cmode, 4549 .port_setup_message_port = mv88e6xxx_setup_message_port, 4550 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4551 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4552 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4553 .stats_get_strings = mv88e6095_stats_get_strings, 4554 .stats_get_stats = mv88e6095_stats_get_stats, 4555 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4556 .set_egress_port = mv88e6095_g1_set_egress_port, 4557 .watchdog_ops = &mv88e6097_watchdog_ops, 4558 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4559 .pot_clear = mv88e6xxx_g2_pot_clear, 4560 .reset = mv88e6352_g1_reset, 4561 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4562 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4563 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4564 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4565 .phylink_validate = mv88e6185_phylink_validate, 4566 }; 4567 4568 static const struct mv88e6xxx_ops mv88e6351_ops = { 4569 /* MV88E6XXX_FAMILY_6351 */ 4570 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4571 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4572 .irl_init_all = mv88e6352_g2_irl_init_all, 4573 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4574 .phy_read = mv88e6xxx_g2_smi_phy_read, 4575 .phy_write = mv88e6xxx_g2_smi_phy_write, 4576 .port_set_link = mv88e6xxx_port_set_link, 4577 .port_sync_link = mv88e6xxx_port_sync_link, 4578 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4579 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4580 .port_tag_remap = mv88e6095_port_tag_remap, 4581 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4582 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4583 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4584 .port_set_ether_type = mv88e6351_port_set_ether_type, 4585 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4586 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4587 .port_pause_limit = mv88e6097_port_pause_limit, 4588 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4589 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4590 .port_get_cmode = mv88e6352_port_get_cmode, 4591 .port_setup_message_port = mv88e6xxx_setup_message_port, 4592 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4593 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4594 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4595 .stats_get_strings = mv88e6095_stats_get_strings, 4596 .stats_get_stats = mv88e6095_stats_get_stats, 4597 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4598 .set_egress_port = mv88e6095_g1_set_egress_port, 4599 .watchdog_ops = &mv88e6097_watchdog_ops, 4600 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4601 .pot_clear = mv88e6xxx_g2_pot_clear, 4602 .reset = mv88e6352_g1_reset, 4603 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4604 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4605 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4606 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4607 .avb_ops = &mv88e6352_avb_ops, 4608 .ptp_ops = &mv88e6352_ptp_ops, 4609 .phylink_validate = mv88e6185_phylink_validate, 4610 }; 4611 4612 static const struct mv88e6xxx_ops mv88e6352_ops = { 4613 /* MV88E6XXX_FAMILY_6352 */ 4614 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4615 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4616 .irl_init_all = mv88e6352_g2_irl_init_all, 4617 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4618 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4619 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4620 .phy_read = mv88e6xxx_g2_smi_phy_read, 4621 .phy_write = mv88e6xxx_g2_smi_phy_write, 4622 .port_set_link = mv88e6xxx_port_set_link, 4623 .port_sync_link = mv88e6xxx_port_sync_link, 4624 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4625 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4626 .port_tag_remap = mv88e6095_port_tag_remap, 4627 .port_set_policy = mv88e6352_port_set_policy, 4628 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4629 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4630 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4631 .port_set_ether_type = mv88e6351_port_set_ether_type, 4632 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4633 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4634 .port_pause_limit = mv88e6097_port_pause_limit, 4635 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4636 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4637 .port_get_cmode = mv88e6352_port_get_cmode, 4638 .port_setup_message_port = mv88e6xxx_setup_message_port, 4639 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4640 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4641 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4642 .stats_get_strings = mv88e6095_stats_get_strings, 4643 .stats_get_stats = mv88e6095_stats_get_stats, 4644 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4645 .set_egress_port = mv88e6095_g1_set_egress_port, 4646 .watchdog_ops = &mv88e6097_watchdog_ops, 4647 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4648 .pot_clear = mv88e6xxx_g2_pot_clear, 4649 .reset = mv88e6352_g1_reset, 4650 .rmu_disable = mv88e6352_g1_rmu_disable, 4651 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4652 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4653 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4654 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4655 .serdes_get_lane = mv88e6352_serdes_get_lane, 4656 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4657 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4658 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4659 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4660 .serdes_power = mv88e6352_serdes_power, 4661 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4662 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4663 .serdes_irq_status = mv88e6352_serdes_irq_status, 4664 .gpio_ops = &mv88e6352_gpio_ops, 4665 .avb_ops = &mv88e6352_avb_ops, 4666 .ptp_ops = &mv88e6352_ptp_ops, 4667 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4668 .serdes_get_strings = mv88e6352_serdes_get_strings, 4669 .serdes_get_stats = mv88e6352_serdes_get_stats, 4670 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4671 .serdes_get_regs = mv88e6352_serdes_get_regs, 4672 .phylink_validate = mv88e6352_phylink_validate, 4673 }; 4674 4675 static const struct mv88e6xxx_ops mv88e6390_ops = { 4676 /* MV88E6XXX_FAMILY_6390 */ 4677 .setup_errata = mv88e6390_setup_errata, 4678 .irl_init_all = mv88e6390_g2_irl_init_all, 4679 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4680 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4682 .phy_read = mv88e6xxx_g2_smi_phy_read, 4683 .phy_write = mv88e6xxx_g2_smi_phy_write, 4684 .port_set_link = mv88e6xxx_port_set_link, 4685 .port_sync_link = mv88e6xxx_port_sync_link, 4686 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4687 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4688 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4689 .port_tag_remap = mv88e6390_port_tag_remap, 4690 .port_set_policy = mv88e6352_port_set_policy, 4691 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4692 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4693 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4694 .port_set_ether_type = mv88e6351_port_set_ether_type, 4695 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4696 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4697 .port_pause_limit = mv88e6390_port_pause_limit, 4698 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4699 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4700 .port_get_cmode = mv88e6352_port_get_cmode, 4701 .port_set_cmode = mv88e6390_port_set_cmode, 4702 .port_setup_message_port = mv88e6xxx_setup_message_port, 4703 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4704 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4705 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4706 .stats_get_strings = mv88e6320_stats_get_strings, 4707 .stats_get_stats = mv88e6390_stats_get_stats, 4708 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4709 .set_egress_port = mv88e6390_g1_set_egress_port, 4710 .watchdog_ops = &mv88e6390_watchdog_ops, 4711 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4712 .pot_clear = mv88e6xxx_g2_pot_clear, 4713 .reset = mv88e6352_g1_reset, 4714 .rmu_disable = mv88e6390_g1_rmu_disable, 4715 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4716 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4717 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4718 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4719 .serdes_power = mv88e6390_serdes_power, 4720 .serdes_get_lane = mv88e6390_serdes_get_lane, 4721 /* Check status register pause & lpa register */ 4722 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4723 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4724 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4725 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4726 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4727 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4728 .serdes_irq_status = mv88e6390_serdes_irq_status, 4729 .gpio_ops = &mv88e6352_gpio_ops, 4730 .avb_ops = &mv88e6390_avb_ops, 4731 .ptp_ops = &mv88e6352_ptp_ops, 4732 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4733 .serdes_get_strings = mv88e6390_serdes_get_strings, 4734 .serdes_get_stats = mv88e6390_serdes_get_stats, 4735 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4736 .serdes_get_regs = mv88e6390_serdes_get_regs, 4737 .phylink_validate = mv88e6390_phylink_validate, 4738 }; 4739 4740 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4741 /* MV88E6XXX_FAMILY_6390 */ 4742 .setup_errata = mv88e6390_setup_errata, 4743 .irl_init_all = mv88e6390_g2_irl_init_all, 4744 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4745 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4746 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4747 .phy_read = mv88e6xxx_g2_smi_phy_read, 4748 .phy_write = mv88e6xxx_g2_smi_phy_write, 4749 .port_set_link = mv88e6xxx_port_set_link, 4750 .port_sync_link = mv88e6xxx_port_sync_link, 4751 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4752 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4753 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4754 .port_tag_remap = mv88e6390_port_tag_remap, 4755 .port_set_policy = mv88e6352_port_set_policy, 4756 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4757 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4758 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4759 .port_set_ether_type = mv88e6351_port_set_ether_type, 4760 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4761 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4762 .port_pause_limit = mv88e6390_port_pause_limit, 4763 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4764 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4765 .port_get_cmode = mv88e6352_port_get_cmode, 4766 .port_set_cmode = mv88e6390x_port_set_cmode, 4767 .port_setup_message_port = mv88e6xxx_setup_message_port, 4768 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4769 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4770 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4771 .stats_get_strings = mv88e6320_stats_get_strings, 4772 .stats_get_stats = mv88e6390_stats_get_stats, 4773 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4774 .set_egress_port = mv88e6390_g1_set_egress_port, 4775 .watchdog_ops = &mv88e6390_watchdog_ops, 4776 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4777 .pot_clear = mv88e6xxx_g2_pot_clear, 4778 .reset = mv88e6352_g1_reset, 4779 .rmu_disable = mv88e6390_g1_rmu_disable, 4780 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4781 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4782 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4783 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4784 .serdes_power = mv88e6390_serdes_power, 4785 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4786 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4787 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4788 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4789 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4790 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4791 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4792 .serdes_irq_status = mv88e6390_serdes_irq_status, 4793 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4794 .serdes_get_strings = mv88e6390_serdes_get_strings, 4795 .serdes_get_stats = mv88e6390_serdes_get_stats, 4796 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4797 .serdes_get_regs = mv88e6390_serdes_get_regs, 4798 .gpio_ops = &mv88e6352_gpio_ops, 4799 .avb_ops = &mv88e6390_avb_ops, 4800 .ptp_ops = &mv88e6352_ptp_ops, 4801 .phylink_validate = mv88e6390x_phylink_validate, 4802 }; 4803 4804 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4805 /* MV88E6XXX_FAMILY_6393 */ 4806 .setup_errata = mv88e6393x_serdes_setup_errata, 4807 .irl_init_all = mv88e6390_g2_irl_init_all, 4808 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4809 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4810 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4811 .phy_read = mv88e6xxx_g2_smi_phy_read, 4812 .phy_write = mv88e6xxx_g2_smi_phy_write, 4813 .port_set_link = mv88e6xxx_port_set_link, 4814 .port_sync_link = mv88e6xxx_port_sync_link, 4815 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4816 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4817 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4818 .port_tag_remap = mv88e6390_port_tag_remap, 4819 .port_set_policy = mv88e6393x_port_set_policy, 4820 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4821 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4822 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4823 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4824 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4825 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4826 .port_pause_limit = mv88e6390_port_pause_limit, 4827 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4828 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4829 .port_get_cmode = mv88e6352_port_get_cmode, 4830 .port_set_cmode = mv88e6393x_port_set_cmode, 4831 .port_setup_message_port = mv88e6xxx_setup_message_port, 4832 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4833 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4834 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4835 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4836 .stats_get_strings = mv88e6320_stats_get_strings, 4837 .stats_get_stats = mv88e6390_stats_get_stats, 4838 /* .set_cpu_port is missing because this family does not support a global 4839 * CPU port, only per port CPU port which is set via 4840 * .port_set_upstream_port method. 4841 */ 4842 .set_egress_port = mv88e6393x_set_egress_port, 4843 .watchdog_ops = &mv88e6390_watchdog_ops, 4844 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4845 .pot_clear = mv88e6xxx_g2_pot_clear, 4846 .reset = mv88e6352_g1_reset, 4847 .rmu_disable = mv88e6390_g1_rmu_disable, 4848 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4849 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4850 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4851 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4852 .serdes_power = mv88e6393x_serdes_power, 4853 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4854 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4855 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4856 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4857 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4858 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4859 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4860 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4861 /* TODO: serdes stats */ 4862 .gpio_ops = &mv88e6352_gpio_ops, 4863 .avb_ops = &mv88e6390_avb_ops, 4864 .ptp_ops = &mv88e6352_ptp_ops, 4865 .phylink_validate = mv88e6393x_phylink_validate, 4866 }; 4867 4868 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4869 [MV88E6085] = { 4870 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4871 .family = MV88E6XXX_FAMILY_6097, 4872 .name = "Marvell 88E6085", 4873 .num_databases = 4096, 4874 .num_macs = 8192, 4875 .num_ports = 10, 4876 .num_internal_phys = 5, 4877 .max_vid = 4095, 4878 .port_base_addr = 0x10, 4879 .phy_base_addr = 0x0, 4880 .global1_addr = 0x1b, 4881 .global2_addr = 0x1c, 4882 .age_time_coeff = 15000, 4883 .g1_irqs = 8, 4884 .g2_irqs = 10, 4885 .atu_move_port_mask = 0xf, 4886 .pvt = true, 4887 .multi_chip = true, 4888 .ops = &mv88e6085_ops, 4889 }, 4890 4891 [MV88E6095] = { 4892 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4893 .family = MV88E6XXX_FAMILY_6095, 4894 .name = "Marvell 88E6095/88E6095F", 4895 .num_databases = 256, 4896 .num_macs = 8192, 4897 .num_ports = 11, 4898 .num_internal_phys = 0, 4899 .max_vid = 4095, 4900 .port_base_addr = 0x10, 4901 .phy_base_addr = 0x0, 4902 .global1_addr = 0x1b, 4903 .global2_addr = 0x1c, 4904 .age_time_coeff = 15000, 4905 .g1_irqs = 8, 4906 .atu_move_port_mask = 0xf, 4907 .multi_chip = true, 4908 .ops = &mv88e6095_ops, 4909 }, 4910 4911 [MV88E6097] = { 4912 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4913 .family = MV88E6XXX_FAMILY_6097, 4914 .name = "Marvell 88E6097/88E6097F", 4915 .num_databases = 4096, 4916 .num_macs = 8192, 4917 .num_ports = 11, 4918 .num_internal_phys = 8, 4919 .max_vid = 4095, 4920 .port_base_addr = 0x10, 4921 .phy_base_addr = 0x0, 4922 .global1_addr = 0x1b, 4923 .global2_addr = 0x1c, 4924 .age_time_coeff = 15000, 4925 .g1_irqs = 8, 4926 .g2_irqs = 10, 4927 .atu_move_port_mask = 0xf, 4928 .pvt = true, 4929 .multi_chip = true, 4930 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 4931 .ops = &mv88e6097_ops, 4932 }, 4933 4934 [MV88E6123] = { 4935 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4936 .family = MV88E6XXX_FAMILY_6165, 4937 .name = "Marvell 88E6123", 4938 .num_databases = 4096, 4939 .num_macs = 1024, 4940 .num_ports = 3, 4941 .num_internal_phys = 5, 4942 .max_vid = 4095, 4943 .port_base_addr = 0x10, 4944 .phy_base_addr = 0x0, 4945 .global1_addr = 0x1b, 4946 .global2_addr = 0x1c, 4947 .age_time_coeff = 15000, 4948 .g1_irqs = 9, 4949 .g2_irqs = 10, 4950 .atu_move_port_mask = 0xf, 4951 .pvt = true, 4952 .multi_chip = true, 4953 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 4954 .ops = &mv88e6123_ops, 4955 }, 4956 4957 [MV88E6131] = { 4958 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4959 .family = MV88E6XXX_FAMILY_6185, 4960 .name = "Marvell 88E6131", 4961 .num_databases = 256, 4962 .num_macs = 8192, 4963 .num_ports = 8, 4964 .num_internal_phys = 0, 4965 .max_vid = 4095, 4966 .port_base_addr = 0x10, 4967 .phy_base_addr = 0x0, 4968 .global1_addr = 0x1b, 4969 .global2_addr = 0x1c, 4970 .age_time_coeff = 15000, 4971 .g1_irqs = 9, 4972 .atu_move_port_mask = 0xf, 4973 .multi_chip = true, 4974 .ops = &mv88e6131_ops, 4975 }, 4976 4977 [MV88E6141] = { 4978 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4979 .family = MV88E6XXX_FAMILY_6341, 4980 .name = "Marvell 88E6141", 4981 .num_databases = 4096, 4982 .num_macs = 2048, 4983 .num_ports = 6, 4984 .num_internal_phys = 5, 4985 .num_gpio = 11, 4986 .max_vid = 4095, 4987 .port_base_addr = 0x10, 4988 .phy_base_addr = 0x10, 4989 .global1_addr = 0x1b, 4990 .global2_addr = 0x1c, 4991 .age_time_coeff = 3750, 4992 .atu_move_port_mask = 0x1f, 4993 .g1_irqs = 9, 4994 .g2_irqs = 10, 4995 .pvt = true, 4996 .multi_chip = true, 4997 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 4998 .ops = &mv88e6141_ops, 4999 }, 5000 5001 [MV88E6161] = { 5002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5003 .family = MV88E6XXX_FAMILY_6165, 5004 .name = "Marvell 88E6161", 5005 .num_databases = 4096, 5006 .num_macs = 1024, 5007 .num_ports = 6, 5008 .num_internal_phys = 5, 5009 .max_vid = 4095, 5010 .port_base_addr = 0x10, 5011 .phy_base_addr = 0x0, 5012 .global1_addr = 0x1b, 5013 .global2_addr = 0x1c, 5014 .age_time_coeff = 15000, 5015 .g1_irqs = 9, 5016 .g2_irqs = 10, 5017 .atu_move_port_mask = 0xf, 5018 .pvt = true, 5019 .multi_chip = true, 5020 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5021 .ptp_support = true, 5022 .ops = &mv88e6161_ops, 5023 }, 5024 5025 [MV88E6165] = { 5026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5027 .family = MV88E6XXX_FAMILY_6165, 5028 .name = "Marvell 88E6165", 5029 .num_databases = 4096, 5030 .num_macs = 8192, 5031 .num_ports = 6, 5032 .num_internal_phys = 0, 5033 .max_vid = 4095, 5034 .port_base_addr = 0x10, 5035 .phy_base_addr = 0x0, 5036 .global1_addr = 0x1b, 5037 .global2_addr = 0x1c, 5038 .age_time_coeff = 15000, 5039 .g1_irqs = 9, 5040 .g2_irqs = 10, 5041 .atu_move_port_mask = 0xf, 5042 .pvt = true, 5043 .multi_chip = true, 5044 .ptp_support = true, 5045 .ops = &mv88e6165_ops, 5046 }, 5047 5048 [MV88E6171] = { 5049 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5050 .family = MV88E6XXX_FAMILY_6351, 5051 .name = "Marvell 88E6171", 5052 .num_databases = 4096, 5053 .num_macs = 8192, 5054 .num_ports = 7, 5055 .num_internal_phys = 5, 5056 .max_vid = 4095, 5057 .port_base_addr = 0x10, 5058 .phy_base_addr = 0x0, 5059 .global1_addr = 0x1b, 5060 .global2_addr = 0x1c, 5061 .age_time_coeff = 15000, 5062 .g1_irqs = 9, 5063 .g2_irqs = 10, 5064 .atu_move_port_mask = 0xf, 5065 .pvt = true, 5066 .multi_chip = true, 5067 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5068 .ops = &mv88e6171_ops, 5069 }, 5070 5071 [MV88E6172] = { 5072 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5073 .family = MV88E6XXX_FAMILY_6352, 5074 .name = "Marvell 88E6172", 5075 .num_databases = 4096, 5076 .num_macs = 8192, 5077 .num_ports = 7, 5078 .num_internal_phys = 5, 5079 .num_gpio = 15, 5080 .max_vid = 4095, 5081 .port_base_addr = 0x10, 5082 .phy_base_addr = 0x0, 5083 .global1_addr = 0x1b, 5084 .global2_addr = 0x1c, 5085 .age_time_coeff = 15000, 5086 .g1_irqs = 9, 5087 .g2_irqs = 10, 5088 .atu_move_port_mask = 0xf, 5089 .pvt = true, 5090 .multi_chip = true, 5091 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5092 .ops = &mv88e6172_ops, 5093 }, 5094 5095 [MV88E6175] = { 5096 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5097 .family = MV88E6XXX_FAMILY_6351, 5098 .name = "Marvell 88E6175", 5099 .num_databases = 4096, 5100 .num_macs = 8192, 5101 .num_ports = 7, 5102 .num_internal_phys = 5, 5103 .max_vid = 4095, 5104 .port_base_addr = 0x10, 5105 .phy_base_addr = 0x0, 5106 .global1_addr = 0x1b, 5107 .global2_addr = 0x1c, 5108 .age_time_coeff = 15000, 5109 .g1_irqs = 9, 5110 .g2_irqs = 10, 5111 .atu_move_port_mask = 0xf, 5112 .pvt = true, 5113 .multi_chip = true, 5114 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5115 .ops = &mv88e6175_ops, 5116 }, 5117 5118 [MV88E6176] = { 5119 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5120 .family = MV88E6XXX_FAMILY_6352, 5121 .name = "Marvell 88E6176", 5122 .num_databases = 4096, 5123 .num_macs = 8192, 5124 .num_ports = 7, 5125 .num_internal_phys = 5, 5126 .num_gpio = 15, 5127 .max_vid = 4095, 5128 .port_base_addr = 0x10, 5129 .phy_base_addr = 0x0, 5130 .global1_addr = 0x1b, 5131 .global2_addr = 0x1c, 5132 .age_time_coeff = 15000, 5133 .g1_irqs = 9, 5134 .g2_irqs = 10, 5135 .atu_move_port_mask = 0xf, 5136 .pvt = true, 5137 .multi_chip = true, 5138 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5139 .ops = &mv88e6176_ops, 5140 }, 5141 5142 [MV88E6185] = { 5143 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5144 .family = MV88E6XXX_FAMILY_6185, 5145 .name = "Marvell 88E6185", 5146 .num_databases = 256, 5147 .num_macs = 8192, 5148 .num_ports = 10, 5149 .num_internal_phys = 0, 5150 .max_vid = 4095, 5151 .port_base_addr = 0x10, 5152 .phy_base_addr = 0x0, 5153 .global1_addr = 0x1b, 5154 .global2_addr = 0x1c, 5155 .age_time_coeff = 15000, 5156 .g1_irqs = 8, 5157 .atu_move_port_mask = 0xf, 5158 .multi_chip = true, 5159 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5160 .ops = &mv88e6185_ops, 5161 }, 5162 5163 [MV88E6190] = { 5164 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5165 .family = MV88E6XXX_FAMILY_6390, 5166 .name = "Marvell 88E6190", 5167 .num_databases = 4096, 5168 .num_macs = 16384, 5169 .num_ports = 11, /* 10 + Z80 */ 5170 .num_internal_phys = 9, 5171 .num_gpio = 16, 5172 .max_vid = 8191, 5173 .port_base_addr = 0x0, 5174 .phy_base_addr = 0x0, 5175 .global1_addr = 0x1b, 5176 .global2_addr = 0x1c, 5177 .age_time_coeff = 3750, 5178 .g1_irqs = 9, 5179 .g2_irqs = 14, 5180 .pvt = true, 5181 .multi_chip = true, 5182 .atu_move_port_mask = 0x1f, 5183 .ops = &mv88e6190_ops, 5184 }, 5185 5186 [MV88E6190X] = { 5187 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5188 .family = MV88E6XXX_FAMILY_6390, 5189 .name = "Marvell 88E6190X", 5190 .num_databases = 4096, 5191 .num_macs = 16384, 5192 .num_ports = 11, /* 10 + Z80 */ 5193 .num_internal_phys = 9, 5194 .num_gpio = 16, 5195 .max_vid = 8191, 5196 .port_base_addr = 0x0, 5197 .phy_base_addr = 0x0, 5198 .global1_addr = 0x1b, 5199 .global2_addr = 0x1c, 5200 .age_time_coeff = 3750, 5201 .g1_irqs = 9, 5202 .g2_irqs = 14, 5203 .atu_move_port_mask = 0x1f, 5204 .pvt = true, 5205 .multi_chip = true, 5206 .ops = &mv88e6190x_ops, 5207 }, 5208 5209 [MV88E6191] = { 5210 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5211 .family = MV88E6XXX_FAMILY_6390, 5212 .name = "Marvell 88E6191", 5213 .num_databases = 4096, 5214 .num_macs = 16384, 5215 .num_ports = 11, /* 10 + Z80 */ 5216 .num_internal_phys = 9, 5217 .max_vid = 8191, 5218 .port_base_addr = 0x0, 5219 .phy_base_addr = 0x0, 5220 .global1_addr = 0x1b, 5221 .global2_addr = 0x1c, 5222 .age_time_coeff = 3750, 5223 .g1_irqs = 9, 5224 .g2_irqs = 14, 5225 .atu_move_port_mask = 0x1f, 5226 .pvt = true, 5227 .multi_chip = true, 5228 .ptp_support = true, 5229 .ops = &mv88e6191_ops, 5230 }, 5231 5232 [MV88E6191X] = { 5233 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5234 .family = MV88E6XXX_FAMILY_6393, 5235 .name = "Marvell 88E6191X", 5236 .num_databases = 4096, 5237 .num_ports = 11, /* 10 + Z80 */ 5238 .num_internal_phys = 9, 5239 .max_vid = 8191, 5240 .port_base_addr = 0x0, 5241 .phy_base_addr = 0x0, 5242 .global1_addr = 0x1b, 5243 .global2_addr = 0x1c, 5244 .age_time_coeff = 3750, 5245 .g1_irqs = 10, 5246 .g2_irqs = 14, 5247 .atu_move_port_mask = 0x1f, 5248 .pvt = true, 5249 .multi_chip = true, 5250 .ptp_support = true, 5251 .ops = &mv88e6393x_ops, 5252 }, 5253 5254 [MV88E6193X] = { 5255 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5256 .family = MV88E6XXX_FAMILY_6393, 5257 .name = "Marvell 88E6193X", 5258 .num_databases = 4096, 5259 .num_ports = 11, /* 10 + Z80 */ 5260 .num_internal_phys = 9, 5261 .max_vid = 8191, 5262 .port_base_addr = 0x0, 5263 .phy_base_addr = 0x0, 5264 .global1_addr = 0x1b, 5265 .global2_addr = 0x1c, 5266 .age_time_coeff = 3750, 5267 .g1_irqs = 10, 5268 .g2_irqs = 14, 5269 .atu_move_port_mask = 0x1f, 5270 .pvt = true, 5271 .multi_chip = true, 5272 .ptp_support = true, 5273 .ops = &mv88e6393x_ops, 5274 }, 5275 5276 [MV88E6220] = { 5277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5278 .family = MV88E6XXX_FAMILY_6250, 5279 .name = "Marvell 88E6220", 5280 .num_databases = 64, 5281 5282 /* Ports 2-4 are not routed to pins 5283 * => usable ports 0, 1, 5, 6 5284 */ 5285 .num_ports = 7, 5286 .num_internal_phys = 2, 5287 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5288 .max_vid = 4095, 5289 .port_base_addr = 0x08, 5290 .phy_base_addr = 0x00, 5291 .global1_addr = 0x0f, 5292 .global2_addr = 0x07, 5293 .age_time_coeff = 15000, 5294 .g1_irqs = 9, 5295 .g2_irqs = 10, 5296 .atu_move_port_mask = 0xf, 5297 .dual_chip = true, 5298 .ptp_support = true, 5299 .ops = &mv88e6250_ops, 5300 }, 5301 5302 [MV88E6240] = { 5303 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5304 .family = MV88E6XXX_FAMILY_6352, 5305 .name = "Marvell 88E6240", 5306 .num_databases = 4096, 5307 .num_macs = 8192, 5308 .num_ports = 7, 5309 .num_internal_phys = 5, 5310 .num_gpio = 15, 5311 .max_vid = 4095, 5312 .port_base_addr = 0x10, 5313 .phy_base_addr = 0x0, 5314 .global1_addr = 0x1b, 5315 .global2_addr = 0x1c, 5316 .age_time_coeff = 15000, 5317 .g1_irqs = 9, 5318 .g2_irqs = 10, 5319 .atu_move_port_mask = 0xf, 5320 .pvt = true, 5321 .multi_chip = true, 5322 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5323 .ptp_support = true, 5324 .ops = &mv88e6240_ops, 5325 }, 5326 5327 [MV88E6250] = { 5328 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5329 .family = MV88E6XXX_FAMILY_6250, 5330 .name = "Marvell 88E6250", 5331 .num_databases = 64, 5332 .num_ports = 7, 5333 .num_internal_phys = 5, 5334 .max_vid = 4095, 5335 .port_base_addr = 0x08, 5336 .phy_base_addr = 0x00, 5337 .global1_addr = 0x0f, 5338 .global2_addr = 0x07, 5339 .age_time_coeff = 15000, 5340 .g1_irqs = 9, 5341 .g2_irqs = 10, 5342 .atu_move_port_mask = 0xf, 5343 .dual_chip = true, 5344 .ptp_support = true, 5345 .ops = &mv88e6250_ops, 5346 }, 5347 5348 [MV88E6290] = { 5349 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5350 .family = MV88E6XXX_FAMILY_6390, 5351 .name = "Marvell 88E6290", 5352 .num_databases = 4096, 5353 .num_ports = 11, /* 10 + Z80 */ 5354 .num_internal_phys = 9, 5355 .num_gpio = 16, 5356 .max_vid = 8191, 5357 .port_base_addr = 0x0, 5358 .phy_base_addr = 0x0, 5359 .global1_addr = 0x1b, 5360 .global2_addr = 0x1c, 5361 .age_time_coeff = 3750, 5362 .g1_irqs = 9, 5363 .g2_irqs = 14, 5364 .atu_move_port_mask = 0x1f, 5365 .pvt = true, 5366 .multi_chip = true, 5367 .ptp_support = true, 5368 .ops = &mv88e6290_ops, 5369 }, 5370 5371 [MV88E6320] = { 5372 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5373 .family = MV88E6XXX_FAMILY_6320, 5374 .name = "Marvell 88E6320", 5375 .num_databases = 4096, 5376 .num_macs = 8192, 5377 .num_ports = 7, 5378 .num_internal_phys = 5, 5379 .num_gpio = 15, 5380 .max_vid = 4095, 5381 .port_base_addr = 0x10, 5382 .phy_base_addr = 0x0, 5383 .global1_addr = 0x1b, 5384 .global2_addr = 0x1c, 5385 .age_time_coeff = 15000, 5386 .g1_irqs = 8, 5387 .g2_irqs = 10, 5388 .atu_move_port_mask = 0xf, 5389 .pvt = true, 5390 .multi_chip = true, 5391 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5392 .ptp_support = true, 5393 .ops = &mv88e6320_ops, 5394 }, 5395 5396 [MV88E6321] = { 5397 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5398 .family = MV88E6XXX_FAMILY_6320, 5399 .name = "Marvell 88E6321", 5400 .num_databases = 4096, 5401 .num_macs = 8192, 5402 .num_ports = 7, 5403 .num_internal_phys = 5, 5404 .num_gpio = 15, 5405 .max_vid = 4095, 5406 .port_base_addr = 0x10, 5407 .phy_base_addr = 0x0, 5408 .global1_addr = 0x1b, 5409 .global2_addr = 0x1c, 5410 .age_time_coeff = 15000, 5411 .g1_irqs = 8, 5412 .g2_irqs = 10, 5413 .atu_move_port_mask = 0xf, 5414 .multi_chip = true, 5415 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5416 .ptp_support = true, 5417 .ops = &mv88e6321_ops, 5418 }, 5419 5420 [MV88E6341] = { 5421 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5422 .family = MV88E6XXX_FAMILY_6341, 5423 .name = "Marvell 88E6341", 5424 .num_databases = 4096, 5425 .num_macs = 2048, 5426 .num_internal_phys = 5, 5427 .num_ports = 6, 5428 .num_gpio = 11, 5429 .max_vid = 4095, 5430 .port_base_addr = 0x10, 5431 .phy_base_addr = 0x10, 5432 .global1_addr = 0x1b, 5433 .global2_addr = 0x1c, 5434 .age_time_coeff = 3750, 5435 .atu_move_port_mask = 0x1f, 5436 .g1_irqs = 9, 5437 .g2_irqs = 10, 5438 .pvt = true, 5439 .multi_chip = true, 5440 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5441 .ptp_support = true, 5442 .ops = &mv88e6341_ops, 5443 }, 5444 5445 [MV88E6350] = { 5446 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5447 .family = MV88E6XXX_FAMILY_6351, 5448 .name = "Marvell 88E6350", 5449 .num_databases = 4096, 5450 .num_macs = 8192, 5451 .num_ports = 7, 5452 .num_internal_phys = 5, 5453 .max_vid = 4095, 5454 .port_base_addr = 0x10, 5455 .phy_base_addr = 0x0, 5456 .global1_addr = 0x1b, 5457 .global2_addr = 0x1c, 5458 .age_time_coeff = 15000, 5459 .g1_irqs = 9, 5460 .g2_irqs = 10, 5461 .atu_move_port_mask = 0xf, 5462 .pvt = true, 5463 .multi_chip = true, 5464 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5465 .ops = &mv88e6350_ops, 5466 }, 5467 5468 [MV88E6351] = { 5469 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5470 .family = MV88E6XXX_FAMILY_6351, 5471 .name = "Marvell 88E6351", 5472 .num_databases = 4096, 5473 .num_macs = 8192, 5474 .num_ports = 7, 5475 .num_internal_phys = 5, 5476 .max_vid = 4095, 5477 .port_base_addr = 0x10, 5478 .phy_base_addr = 0x0, 5479 .global1_addr = 0x1b, 5480 .global2_addr = 0x1c, 5481 .age_time_coeff = 15000, 5482 .g1_irqs = 9, 5483 .g2_irqs = 10, 5484 .atu_move_port_mask = 0xf, 5485 .pvt = true, 5486 .multi_chip = true, 5487 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5488 .ops = &mv88e6351_ops, 5489 }, 5490 5491 [MV88E6352] = { 5492 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5493 .family = MV88E6XXX_FAMILY_6352, 5494 .name = "Marvell 88E6352", 5495 .num_databases = 4096, 5496 .num_macs = 8192, 5497 .num_ports = 7, 5498 .num_internal_phys = 5, 5499 .num_gpio = 15, 5500 .max_vid = 4095, 5501 .port_base_addr = 0x10, 5502 .phy_base_addr = 0x0, 5503 .global1_addr = 0x1b, 5504 .global2_addr = 0x1c, 5505 .age_time_coeff = 15000, 5506 .g1_irqs = 9, 5507 .g2_irqs = 10, 5508 .atu_move_port_mask = 0xf, 5509 .pvt = true, 5510 .multi_chip = true, 5511 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5512 .ptp_support = true, 5513 .ops = &mv88e6352_ops, 5514 }, 5515 [MV88E6390] = { 5516 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5517 .family = MV88E6XXX_FAMILY_6390, 5518 .name = "Marvell 88E6390", 5519 .num_databases = 4096, 5520 .num_macs = 16384, 5521 .num_ports = 11, /* 10 + Z80 */ 5522 .num_internal_phys = 9, 5523 .num_gpio = 16, 5524 .max_vid = 8191, 5525 .port_base_addr = 0x0, 5526 .phy_base_addr = 0x0, 5527 .global1_addr = 0x1b, 5528 .global2_addr = 0x1c, 5529 .age_time_coeff = 3750, 5530 .g1_irqs = 9, 5531 .g2_irqs = 14, 5532 .atu_move_port_mask = 0x1f, 5533 .pvt = true, 5534 .multi_chip = true, 5535 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5536 .ptp_support = true, 5537 .ops = &mv88e6390_ops, 5538 }, 5539 [MV88E6390X] = { 5540 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5541 .family = MV88E6XXX_FAMILY_6390, 5542 .name = "Marvell 88E6390X", 5543 .num_databases = 4096, 5544 .num_macs = 16384, 5545 .num_ports = 11, /* 10 + Z80 */ 5546 .num_internal_phys = 9, 5547 .num_gpio = 16, 5548 .max_vid = 8191, 5549 .port_base_addr = 0x0, 5550 .phy_base_addr = 0x0, 5551 .global1_addr = 0x1b, 5552 .global2_addr = 0x1c, 5553 .age_time_coeff = 3750, 5554 .g1_irqs = 9, 5555 .g2_irqs = 14, 5556 .atu_move_port_mask = 0x1f, 5557 .pvt = true, 5558 .multi_chip = true, 5559 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5560 .ptp_support = true, 5561 .ops = &mv88e6390x_ops, 5562 }, 5563 5564 [MV88E6393X] = { 5565 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5566 .family = MV88E6XXX_FAMILY_6393, 5567 .name = "Marvell 88E6393X", 5568 .num_databases = 4096, 5569 .num_ports = 11, /* 10 + Z80 */ 5570 .num_internal_phys = 9, 5571 .max_vid = 8191, 5572 .port_base_addr = 0x0, 5573 .phy_base_addr = 0x0, 5574 .global1_addr = 0x1b, 5575 .global2_addr = 0x1c, 5576 .age_time_coeff = 3750, 5577 .g1_irqs = 10, 5578 .g2_irqs = 14, 5579 .atu_move_port_mask = 0x1f, 5580 .pvt = true, 5581 .multi_chip = true, 5582 .ptp_support = true, 5583 .ops = &mv88e6393x_ops, 5584 }, 5585 }; 5586 5587 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5588 { 5589 int i; 5590 5591 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5592 if (mv88e6xxx_table[i].prod_num == prod_num) 5593 return &mv88e6xxx_table[i]; 5594 5595 return NULL; 5596 } 5597 5598 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5599 { 5600 const struct mv88e6xxx_info *info; 5601 unsigned int prod_num, rev; 5602 u16 id; 5603 int err; 5604 5605 mv88e6xxx_reg_lock(chip); 5606 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5607 mv88e6xxx_reg_unlock(chip); 5608 if (err) 5609 return err; 5610 5611 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5612 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5613 5614 info = mv88e6xxx_lookup_info(prod_num); 5615 if (!info) 5616 return -ENODEV; 5617 5618 /* Update the compatible info with the probed one */ 5619 chip->info = info; 5620 5621 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5622 chip->info->prod_num, chip->info->name, rev); 5623 5624 return 0; 5625 } 5626 5627 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5628 { 5629 struct mv88e6xxx_chip *chip; 5630 5631 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5632 if (!chip) 5633 return NULL; 5634 5635 chip->dev = dev; 5636 5637 mutex_init(&chip->reg_lock); 5638 INIT_LIST_HEAD(&chip->mdios); 5639 idr_init(&chip->policies); 5640 5641 return chip; 5642 } 5643 5644 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5645 int port, 5646 enum dsa_tag_protocol m) 5647 { 5648 struct mv88e6xxx_chip *chip = ds->priv; 5649 5650 return chip->tag_protocol; 5651 } 5652 5653 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5654 enum dsa_tag_protocol proto) 5655 { 5656 struct mv88e6xxx_chip *chip = ds->priv; 5657 enum dsa_tag_protocol old_protocol; 5658 int err; 5659 5660 switch (proto) { 5661 case DSA_TAG_PROTO_EDSA: 5662 switch (chip->info->edsa_support) { 5663 case MV88E6XXX_EDSA_UNSUPPORTED: 5664 return -EPROTONOSUPPORT; 5665 case MV88E6XXX_EDSA_UNDOCUMENTED: 5666 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5667 fallthrough; 5668 case MV88E6XXX_EDSA_SUPPORTED: 5669 break; 5670 } 5671 break; 5672 case DSA_TAG_PROTO_DSA: 5673 break; 5674 default: 5675 return -EPROTONOSUPPORT; 5676 } 5677 5678 old_protocol = chip->tag_protocol; 5679 chip->tag_protocol = proto; 5680 5681 mv88e6xxx_reg_lock(chip); 5682 err = mv88e6xxx_setup_port_mode(chip, port); 5683 mv88e6xxx_reg_unlock(chip); 5684 5685 if (err) 5686 chip->tag_protocol = old_protocol; 5687 5688 return err; 5689 } 5690 5691 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5692 const struct switchdev_obj_port_mdb *mdb) 5693 { 5694 struct mv88e6xxx_chip *chip = ds->priv; 5695 int err; 5696 5697 mv88e6xxx_reg_lock(chip); 5698 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5699 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5700 mv88e6xxx_reg_unlock(chip); 5701 5702 return err; 5703 } 5704 5705 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5706 const struct switchdev_obj_port_mdb *mdb) 5707 { 5708 struct mv88e6xxx_chip *chip = ds->priv; 5709 int err; 5710 5711 mv88e6xxx_reg_lock(chip); 5712 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5713 mv88e6xxx_reg_unlock(chip); 5714 5715 return err; 5716 } 5717 5718 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5719 struct dsa_mall_mirror_tc_entry *mirror, 5720 bool ingress) 5721 { 5722 enum mv88e6xxx_egress_direction direction = ingress ? 5723 MV88E6XXX_EGRESS_DIR_INGRESS : 5724 MV88E6XXX_EGRESS_DIR_EGRESS; 5725 struct mv88e6xxx_chip *chip = ds->priv; 5726 bool other_mirrors = false; 5727 int i; 5728 int err; 5729 5730 mutex_lock(&chip->reg_lock); 5731 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5732 mirror->to_local_port) { 5733 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5734 other_mirrors |= ingress ? 5735 chip->ports[i].mirror_ingress : 5736 chip->ports[i].mirror_egress; 5737 5738 /* Can't change egress port when other mirror is active */ 5739 if (other_mirrors) { 5740 err = -EBUSY; 5741 goto out; 5742 } 5743 5744 err = mv88e6xxx_set_egress_port(chip, direction, 5745 mirror->to_local_port); 5746 if (err) 5747 goto out; 5748 } 5749 5750 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5751 out: 5752 mutex_unlock(&chip->reg_lock); 5753 5754 return err; 5755 } 5756 5757 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5758 struct dsa_mall_mirror_tc_entry *mirror) 5759 { 5760 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5761 MV88E6XXX_EGRESS_DIR_INGRESS : 5762 MV88E6XXX_EGRESS_DIR_EGRESS; 5763 struct mv88e6xxx_chip *chip = ds->priv; 5764 bool other_mirrors = false; 5765 int i; 5766 5767 mutex_lock(&chip->reg_lock); 5768 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5769 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5770 5771 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5772 other_mirrors |= mirror->ingress ? 5773 chip->ports[i].mirror_ingress : 5774 chip->ports[i].mirror_egress; 5775 5776 /* Reset egress port when no other mirror is active */ 5777 if (!other_mirrors) { 5778 if (mv88e6xxx_set_egress_port(chip, direction, 5779 dsa_upstream_port(ds, port))) 5780 dev_err(ds->dev, "failed to set egress port\n"); 5781 } 5782 5783 mutex_unlock(&chip->reg_lock); 5784 } 5785 5786 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5787 struct switchdev_brport_flags flags, 5788 struct netlink_ext_ack *extack) 5789 { 5790 struct mv88e6xxx_chip *chip = ds->priv; 5791 const struct mv88e6xxx_ops *ops; 5792 5793 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5794 BR_BCAST_FLOOD)) 5795 return -EINVAL; 5796 5797 ops = chip->info->ops; 5798 5799 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5800 return -EINVAL; 5801 5802 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5803 return -EINVAL; 5804 5805 return 0; 5806 } 5807 5808 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5809 struct switchdev_brport_flags flags, 5810 struct netlink_ext_ack *extack) 5811 { 5812 struct mv88e6xxx_chip *chip = ds->priv; 5813 int err = -EOPNOTSUPP; 5814 5815 mv88e6xxx_reg_lock(chip); 5816 5817 if (flags.mask & BR_LEARNING) { 5818 bool learning = !!(flags.val & BR_LEARNING); 5819 u16 pav = learning ? (1 << port) : 0; 5820 5821 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5822 if (err) 5823 goto out; 5824 } 5825 5826 if (flags.mask & BR_FLOOD) { 5827 bool unicast = !!(flags.val & BR_FLOOD); 5828 5829 err = chip->info->ops->port_set_ucast_flood(chip, port, 5830 unicast); 5831 if (err) 5832 goto out; 5833 } 5834 5835 if (flags.mask & BR_MCAST_FLOOD) { 5836 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5837 5838 err = chip->info->ops->port_set_mcast_flood(chip, port, 5839 multicast); 5840 if (err) 5841 goto out; 5842 } 5843 5844 if (flags.mask & BR_BCAST_FLOOD) { 5845 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5846 5847 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5848 if (err) 5849 goto out; 5850 } 5851 5852 out: 5853 mv88e6xxx_reg_unlock(chip); 5854 5855 return err; 5856 } 5857 5858 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5859 struct net_device *lag, 5860 struct netdev_lag_upper_info *info) 5861 { 5862 struct mv88e6xxx_chip *chip = ds->priv; 5863 struct dsa_port *dp; 5864 int id, members = 0; 5865 5866 if (!mv88e6xxx_has_lag(chip)) 5867 return false; 5868 5869 id = dsa_lag_id(ds->dst, lag); 5870 if (id < 0 || id >= ds->num_lag_ids) 5871 return false; 5872 5873 dsa_lag_foreach_port(dp, ds->dst, lag) 5874 /* Includes the port joining the LAG */ 5875 members++; 5876 5877 if (members > 8) 5878 return false; 5879 5880 /* We could potentially relax this to include active 5881 * backup in the future. 5882 */ 5883 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5884 return false; 5885 5886 /* Ideally we would also validate that the hash type matches 5887 * the hardware. Alas, this is always set to unknown on team 5888 * interfaces. 5889 */ 5890 return true; 5891 } 5892 5893 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5894 { 5895 struct mv88e6xxx_chip *chip = ds->priv; 5896 struct dsa_port *dp; 5897 u16 map = 0; 5898 int id; 5899 5900 id = dsa_lag_id(ds->dst, lag); 5901 5902 /* Build the map of all ports to distribute flows destined for 5903 * this LAG. This can be either a local user port, or a DSA 5904 * port if the LAG port is on a remote chip. 5905 */ 5906 dsa_lag_foreach_port(dp, ds->dst, lag) 5907 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5908 5909 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 5910 } 5911 5912 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 5913 /* Row number corresponds to the number of active members in a 5914 * LAG. Each column states which of the eight hash buckets are 5915 * mapped to the column:th port in the LAG. 5916 * 5917 * Example: In a LAG with three active ports, the second port 5918 * ([2][1]) would be selected for traffic mapped to buckets 5919 * 3,4,5 (0x38). 5920 */ 5921 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 5922 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 5923 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 5924 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 5925 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 5926 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 5927 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 5928 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 5929 }; 5930 5931 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 5932 int num_tx, int nth) 5933 { 5934 u8 active = 0; 5935 int i; 5936 5937 num_tx = num_tx <= 8 ? num_tx : 8; 5938 if (nth < num_tx) 5939 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 5940 5941 for (i = 0; i < 8; i++) { 5942 if (BIT(i) & active) 5943 mask[i] |= BIT(port); 5944 } 5945 } 5946 5947 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 5948 { 5949 struct mv88e6xxx_chip *chip = ds->priv; 5950 unsigned int id, num_tx; 5951 struct net_device *lag; 5952 struct dsa_port *dp; 5953 int i, err, nth; 5954 u16 mask[8]; 5955 u16 ivec; 5956 5957 /* Assume no port is a member of any LAG. */ 5958 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 5959 5960 /* Disable all masks for ports that _are_ members of a LAG. */ 5961 list_for_each_entry(dp, &ds->dst->ports, list) { 5962 if (!dp->lag_dev || dp->ds != ds) 5963 continue; 5964 5965 ivec &= ~BIT(dp->index); 5966 } 5967 5968 for (i = 0; i < 8; i++) 5969 mask[i] = ivec; 5970 5971 /* Enable the correct subset of masks for all LAG ports that 5972 * are in the Tx set. 5973 */ 5974 dsa_lags_foreach_id(id, ds->dst) { 5975 lag = dsa_lag_dev(ds->dst, id); 5976 if (!lag) 5977 continue; 5978 5979 num_tx = 0; 5980 dsa_lag_foreach_port(dp, ds->dst, lag) { 5981 if (dp->lag_tx_enabled) 5982 num_tx++; 5983 } 5984 5985 if (!num_tx) 5986 continue; 5987 5988 nth = 0; 5989 dsa_lag_foreach_port(dp, ds->dst, lag) { 5990 if (!dp->lag_tx_enabled) 5991 continue; 5992 5993 if (dp->ds == ds) 5994 mv88e6xxx_lag_set_port_mask(mask, dp->index, 5995 num_tx, nth); 5996 5997 nth++; 5998 } 5999 } 6000 6001 for (i = 0; i < 8; i++) { 6002 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6003 if (err) 6004 return err; 6005 } 6006 6007 return 0; 6008 } 6009 6010 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6011 struct net_device *lag) 6012 { 6013 int err; 6014 6015 err = mv88e6xxx_lag_sync_masks(ds); 6016 6017 if (!err) 6018 err = mv88e6xxx_lag_sync_map(ds, lag); 6019 6020 return err; 6021 } 6022 6023 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6024 { 6025 struct mv88e6xxx_chip *chip = ds->priv; 6026 int err; 6027 6028 mv88e6xxx_reg_lock(chip); 6029 err = mv88e6xxx_lag_sync_masks(ds); 6030 mv88e6xxx_reg_unlock(chip); 6031 return err; 6032 } 6033 6034 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6035 struct net_device *lag, 6036 struct netdev_lag_upper_info *info) 6037 { 6038 struct mv88e6xxx_chip *chip = ds->priv; 6039 int err, id; 6040 6041 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6042 return -EOPNOTSUPP; 6043 6044 id = dsa_lag_id(ds->dst, lag); 6045 6046 mv88e6xxx_reg_lock(chip); 6047 6048 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6049 if (err) 6050 goto err_unlock; 6051 6052 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6053 if (err) 6054 goto err_clear_trunk; 6055 6056 mv88e6xxx_reg_unlock(chip); 6057 return 0; 6058 6059 err_clear_trunk: 6060 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6061 err_unlock: 6062 mv88e6xxx_reg_unlock(chip); 6063 return err; 6064 } 6065 6066 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6067 struct net_device *lag) 6068 { 6069 struct mv88e6xxx_chip *chip = ds->priv; 6070 int err_sync, err_trunk; 6071 6072 mv88e6xxx_reg_lock(chip); 6073 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6074 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6075 mv88e6xxx_reg_unlock(chip); 6076 return err_sync ? : err_trunk; 6077 } 6078 6079 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6080 int port) 6081 { 6082 struct mv88e6xxx_chip *chip = ds->priv; 6083 int err; 6084 6085 mv88e6xxx_reg_lock(chip); 6086 err = mv88e6xxx_lag_sync_masks(ds); 6087 mv88e6xxx_reg_unlock(chip); 6088 return err; 6089 } 6090 6091 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6092 int port, struct net_device *lag, 6093 struct netdev_lag_upper_info *info) 6094 { 6095 struct mv88e6xxx_chip *chip = ds->priv; 6096 int err; 6097 6098 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6099 return -EOPNOTSUPP; 6100 6101 mv88e6xxx_reg_lock(chip); 6102 6103 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6104 if (err) 6105 goto unlock; 6106 6107 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6108 6109 unlock: 6110 mv88e6xxx_reg_unlock(chip); 6111 return err; 6112 } 6113 6114 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6115 int port, struct net_device *lag) 6116 { 6117 struct mv88e6xxx_chip *chip = ds->priv; 6118 int err_sync, err_pvt; 6119 6120 mv88e6xxx_reg_lock(chip); 6121 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6122 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6123 mv88e6xxx_reg_unlock(chip); 6124 return err_sync ? : err_pvt; 6125 } 6126 6127 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6128 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6129 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6130 .setup = mv88e6xxx_setup, 6131 .teardown = mv88e6xxx_teardown, 6132 .port_setup = mv88e6xxx_port_setup, 6133 .port_teardown = mv88e6xxx_port_teardown, 6134 .phylink_validate = mv88e6xxx_validate, 6135 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6136 .phylink_mac_config = mv88e6xxx_mac_config, 6137 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6138 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6139 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6140 .get_strings = mv88e6xxx_get_strings, 6141 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6142 .get_sset_count = mv88e6xxx_get_sset_count, 6143 .port_enable = mv88e6xxx_port_enable, 6144 .port_disable = mv88e6xxx_port_disable, 6145 .port_max_mtu = mv88e6xxx_get_max_mtu, 6146 .port_change_mtu = mv88e6xxx_change_mtu, 6147 .get_mac_eee = mv88e6xxx_get_mac_eee, 6148 .set_mac_eee = mv88e6xxx_set_mac_eee, 6149 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6150 .get_eeprom = mv88e6xxx_get_eeprom, 6151 .set_eeprom = mv88e6xxx_set_eeprom, 6152 .get_regs_len = mv88e6xxx_get_regs_len, 6153 .get_regs = mv88e6xxx_get_regs, 6154 .get_rxnfc = mv88e6xxx_get_rxnfc, 6155 .set_rxnfc = mv88e6xxx_set_rxnfc, 6156 .set_ageing_time = mv88e6xxx_set_ageing_time, 6157 .port_bridge_join = mv88e6xxx_port_bridge_join, 6158 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6159 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6160 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6161 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6162 .port_fast_age = mv88e6xxx_port_fast_age, 6163 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6164 .port_vlan_add = mv88e6xxx_port_vlan_add, 6165 .port_vlan_del = mv88e6xxx_port_vlan_del, 6166 .port_fdb_add = mv88e6xxx_port_fdb_add, 6167 .port_fdb_del = mv88e6xxx_port_fdb_del, 6168 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6169 .port_mdb_add = mv88e6xxx_port_mdb_add, 6170 .port_mdb_del = mv88e6xxx_port_mdb_del, 6171 .port_mirror_add = mv88e6xxx_port_mirror_add, 6172 .port_mirror_del = mv88e6xxx_port_mirror_del, 6173 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6174 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6175 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6176 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6177 .port_txtstamp = mv88e6xxx_port_txtstamp, 6178 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6179 .get_ts_info = mv88e6xxx_get_ts_info, 6180 .devlink_param_get = mv88e6xxx_devlink_param_get, 6181 .devlink_param_set = mv88e6xxx_devlink_param_set, 6182 .devlink_info_get = mv88e6xxx_devlink_info_get, 6183 .port_lag_change = mv88e6xxx_port_lag_change, 6184 .port_lag_join = mv88e6xxx_port_lag_join, 6185 .port_lag_leave = mv88e6xxx_port_lag_leave, 6186 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6187 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6188 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6189 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload, 6190 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload, 6191 }; 6192 6193 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6194 { 6195 struct device *dev = chip->dev; 6196 struct dsa_switch *ds; 6197 6198 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6199 if (!ds) 6200 return -ENOMEM; 6201 6202 ds->dev = dev; 6203 ds->num_ports = mv88e6xxx_num_ports(chip); 6204 ds->priv = chip; 6205 ds->dev = dev; 6206 ds->ops = &mv88e6xxx_switch_ops; 6207 ds->ageing_time_min = chip->info->age_time_coeff; 6208 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6209 6210 /* Some chips support up to 32, but that requires enabling the 6211 * 5-bit port mode, which we do not support. 640k^W16 ought to 6212 * be enough for anyone. 6213 */ 6214 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6215 6216 dev_set_drvdata(dev, ds); 6217 6218 return dsa_register_switch(ds); 6219 } 6220 6221 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6222 { 6223 dsa_unregister_switch(chip->ds); 6224 } 6225 6226 static const void *pdata_device_get_match_data(struct device *dev) 6227 { 6228 const struct of_device_id *matches = dev->driver->of_match_table; 6229 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6230 6231 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6232 matches++) { 6233 if (!strcmp(pdata->compatible, matches->compatible)) 6234 return matches->data; 6235 } 6236 return NULL; 6237 } 6238 6239 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6240 * would be lost after a power cycle so prevent it to be suspended. 6241 */ 6242 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6243 { 6244 return -EOPNOTSUPP; 6245 } 6246 6247 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6248 { 6249 return 0; 6250 } 6251 6252 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6253 6254 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6255 { 6256 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6257 const struct mv88e6xxx_info *compat_info = NULL; 6258 struct device *dev = &mdiodev->dev; 6259 struct device_node *np = dev->of_node; 6260 struct mv88e6xxx_chip *chip; 6261 int port; 6262 int err; 6263 6264 if (!np && !pdata) 6265 return -EINVAL; 6266 6267 if (np) 6268 compat_info = of_device_get_match_data(dev); 6269 6270 if (pdata) { 6271 compat_info = pdata_device_get_match_data(dev); 6272 6273 if (!pdata->netdev) 6274 return -EINVAL; 6275 6276 for (port = 0; port < DSA_MAX_PORTS; port++) { 6277 if (!(pdata->enabled_ports & (1 << port))) 6278 continue; 6279 if (strcmp(pdata->cd.port_names[port], "cpu")) 6280 continue; 6281 pdata->cd.netdev[port] = &pdata->netdev->dev; 6282 break; 6283 } 6284 } 6285 6286 if (!compat_info) 6287 return -EINVAL; 6288 6289 chip = mv88e6xxx_alloc_chip(dev); 6290 if (!chip) { 6291 err = -ENOMEM; 6292 goto out; 6293 } 6294 6295 chip->info = compat_info; 6296 6297 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6298 if (err) 6299 goto out; 6300 6301 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6302 if (IS_ERR(chip->reset)) { 6303 err = PTR_ERR(chip->reset); 6304 goto out; 6305 } 6306 if (chip->reset) 6307 usleep_range(1000, 2000); 6308 6309 err = mv88e6xxx_detect(chip); 6310 if (err) 6311 goto out; 6312 6313 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6314 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6315 else 6316 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6317 6318 mv88e6xxx_phy_init(chip); 6319 6320 if (chip->info->ops->get_eeprom) { 6321 if (np) 6322 of_property_read_u32(np, "eeprom-length", 6323 &chip->eeprom_len); 6324 else 6325 chip->eeprom_len = pdata->eeprom_len; 6326 } 6327 6328 mv88e6xxx_reg_lock(chip); 6329 err = mv88e6xxx_switch_reset(chip); 6330 mv88e6xxx_reg_unlock(chip); 6331 if (err) 6332 goto out; 6333 6334 if (np) { 6335 chip->irq = of_irq_get(np, 0); 6336 if (chip->irq == -EPROBE_DEFER) { 6337 err = chip->irq; 6338 goto out; 6339 } 6340 } 6341 6342 if (pdata) 6343 chip->irq = pdata->irq; 6344 6345 /* Has to be performed before the MDIO bus is created, because 6346 * the PHYs will link their interrupts to these interrupt 6347 * controllers 6348 */ 6349 mv88e6xxx_reg_lock(chip); 6350 if (chip->irq > 0) 6351 err = mv88e6xxx_g1_irq_setup(chip); 6352 else 6353 err = mv88e6xxx_irq_poll_setup(chip); 6354 mv88e6xxx_reg_unlock(chip); 6355 6356 if (err) 6357 goto out; 6358 6359 if (chip->info->g2_irqs > 0) { 6360 err = mv88e6xxx_g2_irq_setup(chip); 6361 if (err) 6362 goto out_g1_irq; 6363 } 6364 6365 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6366 if (err) 6367 goto out_g2_irq; 6368 6369 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6370 if (err) 6371 goto out_g1_atu_prob_irq; 6372 6373 err = mv88e6xxx_mdios_register(chip, np); 6374 if (err) 6375 goto out_g1_vtu_prob_irq; 6376 6377 err = mv88e6xxx_register_switch(chip); 6378 if (err) 6379 goto out_mdio; 6380 6381 return 0; 6382 6383 out_mdio: 6384 mv88e6xxx_mdios_unregister(chip); 6385 out_g1_vtu_prob_irq: 6386 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6387 out_g1_atu_prob_irq: 6388 mv88e6xxx_g1_atu_prob_irq_free(chip); 6389 out_g2_irq: 6390 if (chip->info->g2_irqs > 0) 6391 mv88e6xxx_g2_irq_free(chip); 6392 out_g1_irq: 6393 if (chip->irq > 0) 6394 mv88e6xxx_g1_irq_free(chip); 6395 else 6396 mv88e6xxx_irq_poll_free(chip); 6397 out: 6398 if (pdata) 6399 dev_put(pdata->netdev); 6400 6401 return err; 6402 } 6403 6404 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6405 { 6406 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6407 struct mv88e6xxx_chip *chip; 6408 6409 if (!ds) 6410 return; 6411 6412 chip = ds->priv; 6413 6414 if (chip->info->ptp_support) { 6415 mv88e6xxx_hwtstamp_free(chip); 6416 mv88e6xxx_ptp_free(chip); 6417 } 6418 6419 mv88e6xxx_phy_destroy(chip); 6420 mv88e6xxx_unregister_switch(chip); 6421 mv88e6xxx_mdios_unregister(chip); 6422 6423 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6424 mv88e6xxx_g1_atu_prob_irq_free(chip); 6425 6426 if (chip->info->g2_irqs > 0) 6427 mv88e6xxx_g2_irq_free(chip); 6428 6429 if (chip->irq > 0) 6430 mv88e6xxx_g1_irq_free(chip); 6431 else 6432 mv88e6xxx_irq_poll_free(chip); 6433 6434 dev_set_drvdata(&mdiodev->dev, NULL); 6435 } 6436 6437 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6438 { 6439 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6440 6441 if (!ds) 6442 return; 6443 6444 dsa_switch_shutdown(ds); 6445 6446 dev_set_drvdata(&mdiodev->dev, NULL); 6447 } 6448 6449 static const struct of_device_id mv88e6xxx_of_match[] = { 6450 { 6451 .compatible = "marvell,mv88e6085", 6452 .data = &mv88e6xxx_table[MV88E6085], 6453 }, 6454 { 6455 .compatible = "marvell,mv88e6190", 6456 .data = &mv88e6xxx_table[MV88E6190], 6457 }, 6458 { 6459 .compatible = "marvell,mv88e6250", 6460 .data = &mv88e6xxx_table[MV88E6250], 6461 }, 6462 { /* sentinel */ }, 6463 }; 6464 6465 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6466 6467 static struct mdio_driver mv88e6xxx_driver = { 6468 .probe = mv88e6xxx_probe, 6469 .remove = mv88e6xxx_remove, 6470 .shutdown = mv88e6xxx_shutdown, 6471 .mdiodrv.driver = { 6472 .name = "mv88e6085", 6473 .of_match_table = mv88e6xxx_of_match, 6474 .pm = &mv88e6xxx_pm_ops, 6475 }, 6476 }; 6477 6478 mdio_module_driver(mv88e6xxx_driver); 6479 6480 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6481 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6482 MODULE_LICENSE("GPL"); 6483