1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/delay.h> 14 #include <linux/etherdevice.h> 15 #include <linux/ethtool.h> 16 #include <linux/if_bridge.h> 17 #include <linux/interrupt.h> 18 #include <linux/irq.h> 19 #include <linux/irqdomain.h> 20 #include <linux/jiffies.h> 21 #include <linux/list.h> 22 #include <linux/mdio.h> 23 #include <linux/module.h> 24 #include <linux/of_device.h> 25 #include <linux/of_irq.h> 26 #include <linux/of_mdio.h> 27 #include <linux/platform_data/mv88e6xxx.h> 28 #include <linux/netdevice.h> 29 #include <linux/gpio/consumer.h> 30 #include <linux/phy.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 85 { 86 struct mv88e6xxx_mdio_bus *mdio_bus; 87 88 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 89 list); 90 if (!mdio_bus) 91 return NULL; 92 93 return mdio_bus->bus; 94 } 95 96 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 97 { 98 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 99 unsigned int n = d->hwirq; 100 101 chip->g1_irq.masked |= (1 << n); 102 } 103 104 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 105 { 106 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 107 unsigned int n = d->hwirq; 108 109 chip->g1_irq.masked &= ~(1 << n); 110 } 111 112 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 113 { 114 unsigned int nhandled = 0; 115 unsigned int sub_irq; 116 unsigned int n; 117 u16 reg; 118 u16 ctl1; 119 int err; 120 121 mv88e6xxx_reg_lock(chip); 122 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 123 mv88e6xxx_reg_unlock(chip); 124 125 if (err) 126 goto out; 127 128 do { 129 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 130 if (reg & (1 << n)) { 131 sub_irq = irq_find_mapping(chip->g1_irq.domain, 132 n); 133 handle_nested_irq(sub_irq); 134 ++nhandled; 135 } 136 } 137 138 mv88e6xxx_reg_lock(chip); 139 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 140 if (err) 141 goto unlock; 142 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 143 unlock: 144 mv88e6xxx_reg_unlock(chip); 145 if (err) 146 goto out; 147 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 148 } while (reg & ctl1); 149 150 out: 151 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 152 } 153 154 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 155 { 156 struct mv88e6xxx_chip *chip = dev_id; 157 158 return mv88e6xxx_g1_irq_thread_work(chip); 159 } 160 161 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 162 { 163 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 164 165 mv88e6xxx_reg_lock(chip); 166 } 167 168 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 169 { 170 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 171 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 172 u16 reg; 173 int err; 174 175 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 176 if (err) 177 goto out; 178 179 reg &= ~mask; 180 reg |= (~chip->g1_irq.masked & mask); 181 182 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 183 if (err) 184 goto out; 185 186 out: 187 mv88e6xxx_reg_unlock(chip); 188 } 189 190 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 191 .name = "mv88e6xxx-g1", 192 .irq_mask = mv88e6xxx_g1_irq_mask, 193 .irq_unmask = mv88e6xxx_g1_irq_unmask, 194 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 195 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 196 }; 197 198 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 199 unsigned int irq, 200 irq_hw_number_t hwirq) 201 { 202 struct mv88e6xxx_chip *chip = d->host_data; 203 204 irq_set_chip_data(irq, d->host_data); 205 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 206 irq_set_noprobe(irq); 207 208 return 0; 209 } 210 211 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 212 .map = mv88e6xxx_g1_irq_domain_map, 213 .xlate = irq_domain_xlate_twocell, 214 }; 215 216 /* To be called with reg_lock held */ 217 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 218 { 219 int irq, virq; 220 u16 mask; 221 222 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 223 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 224 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 225 226 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 227 virq = irq_find_mapping(chip->g1_irq.domain, irq); 228 irq_dispose_mapping(virq); 229 } 230 231 irq_domain_remove(chip->g1_irq.domain); 232 } 233 234 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 235 { 236 /* 237 * free_irq must be called without reg_lock taken because the irq 238 * handler takes this lock, too. 239 */ 240 free_irq(chip->irq, chip); 241 242 mv88e6xxx_reg_lock(chip); 243 mv88e6xxx_g1_irq_free_common(chip); 244 mv88e6xxx_reg_unlock(chip); 245 } 246 247 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 248 { 249 int err, irq, virq; 250 u16 reg, mask; 251 252 chip->g1_irq.nirqs = chip->info->g1_irqs; 253 chip->g1_irq.domain = irq_domain_add_simple( 254 NULL, chip->g1_irq.nirqs, 0, 255 &mv88e6xxx_g1_irq_domain_ops, chip); 256 if (!chip->g1_irq.domain) 257 return -ENOMEM; 258 259 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 260 irq_create_mapping(chip->g1_irq.domain, irq); 261 262 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 263 chip->g1_irq.masked = ~0; 264 265 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 266 if (err) 267 goto out_mapping; 268 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 271 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 272 if (err) 273 goto out_disable; 274 275 /* Reading the interrupt status clears (most of) them */ 276 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 277 if (err) 278 goto out_disable; 279 280 return 0; 281 282 out_disable: 283 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 284 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 285 286 out_mapping: 287 for (irq = 0; irq < 16; irq++) { 288 virq = irq_find_mapping(chip->g1_irq.domain, irq); 289 irq_dispose_mapping(virq); 290 } 291 292 irq_domain_remove(chip->g1_irq.domain); 293 294 return err; 295 } 296 297 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 298 { 299 static struct lock_class_key lock_key; 300 static struct lock_class_key request_key; 301 int err; 302 303 err = mv88e6xxx_g1_irq_setup_common(chip); 304 if (err) 305 return err; 306 307 /* These lock classes tells lockdep that global 1 irqs are in 308 * a different category than their parent GPIO, so it won't 309 * report false recursion. 310 */ 311 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 312 313 mv88e6xxx_reg_unlock(chip); 314 err = request_threaded_irq(chip->irq, NULL, 315 mv88e6xxx_g1_irq_thread_fn, 316 IRQF_ONESHOT | IRQF_SHARED, 317 dev_name(chip->dev), chip); 318 mv88e6xxx_reg_lock(chip); 319 if (err) 320 mv88e6xxx_g1_irq_free_common(chip); 321 322 return err; 323 } 324 325 static void mv88e6xxx_irq_poll(struct kthread_work *work) 326 { 327 struct mv88e6xxx_chip *chip = container_of(work, 328 struct mv88e6xxx_chip, 329 irq_poll_work.work); 330 mv88e6xxx_g1_irq_thread_work(chip); 331 332 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 333 msecs_to_jiffies(100)); 334 } 335 336 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 337 { 338 int err; 339 340 err = mv88e6xxx_g1_irq_setup_common(chip); 341 if (err) 342 return err; 343 344 kthread_init_delayed_work(&chip->irq_poll_work, 345 mv88e6xxx_irq_poll); 346 347 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 348 if (IS_ERR(chip->kworker)) 349 return PTR_ERR(chip->kworker); 350 351 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 352 msecs_to_jiffies(100)); 353 354 return 0; 355 } 356 357 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 358 { 359 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 360 kthread_destroy_worker(chip->kworker); 361 362 mv88e6xxx_reg_lock(chip); 363 mv88e6xxx_g1_irq_free_common(chip); 364 mv88e6xxx_reg_unlock(chip); 365 } 366 367 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 368 { 369 int i; 370 371 for (i = 0; i < 16; i++) { 372 u16 val; 373 int err; 374 375 err = mv88e6xxx_read(chip, addr, reg, &val); 376 if (err) 377 return err; 378 379 if (!(val & mask)) 380 return 0; 381 382 usleep_range(1000, 2000); 383 } 384 385 dev_err(chip->dev, "Timeout while waiting for switch\n"); 386 return -ETIMEDOUT; 387 } 388 389 /* Indirect write to single pointer-data register with an Update bit */ 390 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 391 { 392 u16 val; 393 int err; 394 395 /* Wait until the previous operation is completed */ 396 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 397 if (err) 398 return err; 399 400 /* Set the Update bit to trigger a write operation */ 401 val = BIT(15) | update; 402 403 return mv88e6xxx_write(chip, addr, reg, val); 404 } 405 406 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 407 int speed, int duplex, int pause, 408 phy_interface_t mode) 409 { 410 struct phylink_link_state state; 411 int err; 412 413 if (!chip->info->ops->port_set_link) 414 return 0; 415 416 if (!chip->info->ops->port_link_state) 417 return 0; 418 419 err = chip->info->ops->port_link_state(chip, port, &state); 420 if (err) 421 return err; 422 423 /* Has anything actually changed? We don't expect the 424 * interface mode to change without one of the other 425 * parameters also changing 426 */ 427 if (state.link == link && 428 state.speed == speed && 429 state.duplex == duplex) 430 return 0; 431 432 /* Port's MAC control must not be changed unless the link is down */ 433 err = chip->info->ops->port_set_link(chip, port, 0); 434 if (err) 435 return err; 436 437 if (chip->info->ops->port_set_speed) { 438 err = chip->info->ops->port_set_speed(chip, port, speed); 439 if (err && err != -EOPNOTSUPP) 440 goto restore_link; 441 } 442 443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 444 mode = chip->info->ops->port_max_speed_mode(port); 445 446 if (chip->info->ops->port_set_pause) { 447 err = chip->info->ops->port_set_pause(chip, port, pause); 448 if (err) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_duplex) { 453 err = chip->info->ops->port_set_duplex(chip, port, duplex); 454 if (err && err != -EOPNOTSUPP) 455 goto restore_link; 456 } 457 458 if (chip->info->ops->port_set_rgmii_delay) { 459 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 460 if (err && err != -EOPNOTSUPP) 461 goto restore_link; 462 } 463 464 if (chip->info->ops->port_set_cmode) { 465 err = chip->info->ops->port_set_cmode(chip, port, mode); 466 if (err && err != -EOPNOTSUPP) 467 goto restore_link; 468 } 469 470 err = 0; 471 restore_link: 472 if (chip->info->ops->port_set_link(chip, port, link)) 473 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 474 475 return err; 476 } 477 478 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 479 { 480 struct mv88e6xxx_chip *chip = ds->priv; 481 482 return port < chip->info->num_internal_phys; 483 } 484 485 /* We expect the switch to perform auto negotiation if there is a real 486 * phy. However, in the case of a fixed link phy, we force the port 487 * settings from the fixed link settings. 488 */ 489 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 490 struct phy_device *phydev) 491 { 492 struct mv88e6xxx_chip *chip = ds->priv; 493 int err; 494 495 if (!phy_is_pseudo_fixed_link(phydev) && 496 mv88e6xxx_phy_is_internal(ds, port)) 497 return; 498 499 mv88e6xxx_reg_lock(chip); 500 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 501 phydev->duplex, phydev->pause, 502 phydev->interface); 503 mv88e6xxx_reg_unlock(chip); 504 505 if (err && err != -EOPNOTSUPP) 506 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 507 } 508 509 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 510 unsigned long *mask, 511 struct phylink_link_state *state) 512 { 513 if (!phy_interface_mode_is_8023z(state->interface)) { 514 /* 10M and 100M are only supported in non-802.3z mode */ 515 phylink_set(mask, 10baseT_Half); 516 phylink_set(mask, 10baseT_Full); 517 phylink_set(mask, 100baseT_Half); 518 phylink_set(mask, 100baseT_Full); 519 } 520 } 521 522 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 523 unsigned long *mask, 524 struct phylink_link_state *state) 525 { 526 /* FIXME: if the port is in 1000Base-X mode, then it only supports 527 * 1000M FD speeds. In this case, CMODE will indicate 5. 528 */ 529 phylink_set(mask, 1000baseT_Full); 530 phylink_set(mask, 1000baseX_Full); 531 532 mv88e6065_phylink_validate(chip, port, mask, state); 533 } 534 535 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 536 unsigned long *mask, 537 struct phylink_link_state *state) 538 { 539 if (port >= 5) 540 phylink_set(mask, 2500baseX_Full); 541 542 /* No ethtool bits for 200Mbps */ 543 phylink_set(mask, 1000baseT_Full); 544 phylink_set(mask, 1000baseX_Full); 545 546 mv88e6065_phylink_validate(chip, port, mask, state); 547 } 548 549 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 550 unsigned long *mask, 551 struct phylink_link_state *state) 552 { 553 /* No ethtool bits for 200Mbps */ 554 phylink_set(mask, 1000baseT_Full); 555 phylink_set(mask, 1000baseX_Full); 556 557 mv88e6065_phylink_validate(chip, port, mask, state); 558 } 559 560 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 561 unsigned long *mask, 562 struct phylink_link_state *state) 563 { 564 if (port >= 9) { 565 phylink_set(mask, 2500baseX_Full); 566 phylink_set(mask, 2500baseT_Full); 567 } 568 569 /* No ethtool bits for 200Mbps */ 570 phylink_set(mask, 1000baseT_Full); 571 phylink_set(mask, 1000baseX_Full); 572 573 mv88e6065_phylink_validate(chip, port, mask, state); 574 } 575 576 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 577 unsigned long *mask, 578 struct phylink_link_state *state) 579 { 580 if (port >= 9) { 581 phylink_set(mask, 10000baseT_Full); 582 phylink_set(mask, 10000baseKR_Full); 583 } 584 585 mv88e6390_phylink_validate(chip, port, mask, state); 586 } 587 588 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 589 unsigned long *supported, 590 struct phylink_link_state *state) 591 { 592 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 593 struct mv88e6xxx_chip *chip = ds->priv; 594 595 /* Allow all the expected bits */ 596 phylink_set(mask, Autoneg); 597 phylink_set(mask, Pause); 598 phylink_set_port_modes(mask); 599 600 if (chip->info->ops->phylink_validate) 601 chip->info->ops->phylink_validate(chip, port, mask, state); 602 603 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 604 bitmap_and(state->advertising, state->advertising, mask, 605 __ETHTOOL_LINK_MODE_MASK_NBITS); 606 607 /* We can only operate at 2500BaseX or 1000BaseX. If requested 608 * to advertise both, only report advertising at 2500BaseX. 609 */ 610 phylink_helper_basex_speed(state); 611 } 612 613 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 614 struct phylink_link_state *state) 615 { 616 struct mv88e6xxx_chip *chip = ds->priv; 617 int err; 618 619 mv88e6xxx_reg_lock(chip); 620 if (chip->info->ops->port_link_state) 621 err = chip->info->ops->port_link_state(chip, port, state); 622 else 623 err = -EOPNOTSUPP; 624 mv88e6xxx_reg_unlock(chip); 625 626 return err; 627 } 628 629 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 630 unsigned int mode, 631 const struct phylink_link_state *state) 632 { 633 struct mv88e6xxx_chip *chip = ds->priv; 634 int speed, duplex, link, pause, err; 635 636 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 637 return; 638 639 if (mode == MLO_AN_FIXED) { 640 link = LINK_FORCED_UP; 641 speed = state->speed; 642 duplex = state->duplex; 643 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 644 link = state->link; 645 speed = state->speed; 646 duplex = state->duplex; 647 } else { 648 speed = SPEED_UNFORCED; 649 duplex = DUPLEX_UNFORCED; 650 link = LINK_UNFORCED; 651 } 652 pause = !!phylink_test(state->advertising, Pause); 653 654 mv88e6xxx_reg_lock(chip); 655 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 656 state->interface); 657 mv88e6xxx_reg_unlock(chip); 658 659 if (err && err != -EOPNOTSUPP) 660 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 661 } 662 663 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 664 { 665 struct mv88e6xxx_chip *chip = ds->priv; 666 int err; 667 668 mv88e6xxx_reg_lock(chip); 669 err = chip->info->ops->port_set_link(chip, port, link); 670 mv88e6xxx_reg_unlock(chip); 671 672 if (err) 673 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 674 } 675 676 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 677 unsigned int mode, 678 phy_interface_t interface) 679 { 680 if (mode == MLO_AN_FIXED) 681 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 682 } 683 684 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 685 unsigned int mode, phy_interface_t interface, 686 struct phy_device *phydev) 687 { 688 if (mode == MLO_AN_FIXED) 689 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 690 } 691 692 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 693 { 694 if (!chip->info->ops->stats_snapshot) 695 return -EOPNOTSUPP; 696 697 return chip->info->ops->stats_snapshot(chip, port); 698 } 699 700 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 701 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 702 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 703 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 704 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 705 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 706 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 707 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 708 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 709 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 710 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 711 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 712 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 713 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 714 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 715 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 716 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 717 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 718 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 719 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 720 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 721 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 722 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 723 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 724 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 725 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 726 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 727 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 728 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 729 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 730 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 731 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 732 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 733 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 734 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 735 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 736 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 737 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 738 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 739 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 740 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 741 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 742 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 743 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 744 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 745 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 746 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 747 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 748 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 749 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 750 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 751 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 752 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 753 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 754 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 755 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 756 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 757 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 758 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 759 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 760 }; 761 762 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 763 struct mv88e6xxx_hw_stat *s, 764 int port, u16 bank1_select, 765 u16 histogram) 766 { 767 u32 low; 768 u32 high = 0; 769 u16 reg = 0; 770 int err; 771 u64 value; 772 773 switch (s->type) { 774 case STATS_TYPE_PORT: 775 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 776 if (err) 777 return U64_MAX; 778 779 low = reg; 780 if (s->size == 4) { 781 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 782 if (err) 783 return U64_MAX; 784 low |= ((u32)reg) << 16; 785 } 786 break; 787 case STATS_TYPE_BANK1: 788 reg = bank1_select; 789 /* fall through */ 790 case STATS_TYPE_BANK0: 791 reg |= s->reg | histogram; 792 mv88e6xxx_g1_stats_read(chip, reg, &low); 793 if (s->size == 8) 794 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 795 break; 796 default: 797 return U64_MAX; 798 } 799 value = (((u64)high) << 32) | low; 800 return value; 801 } 802 803 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 804 uint8_t *data, int types) 805 { 806 struct mv88e6xxx_hw_stat *stat; 807 int i, j; 808 809 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 810 stat = &mv88e6xxx_hw_stats[i]; 811 if (stat->type & types) { 812 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 813 ETH_GSTRING_LEN); 814 j++; 815 } 816 } 817 818 return j; 819 } 820 821 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 822 uint8_t *data) 823 { 824 return mv88e6xxx_stats_get_strings(chip, data, 825 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 826 } 827 828 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 829 uint8_t *data) 830 { 831 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 832 } 833 834 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 835 uint8_t *data) 836 { 837 return mv88e6xxx_stats_get_strings(chip, data, 838 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 839 } 840 841 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 842 "atu_member_violation", 843 "atu_miss_violation", 844 "atu_full_violation", 845 "vtu_member_violation", 846 "vtu_miss_violation", 847 }; 848 849 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 850 { 851 unsigned int i; 852 853 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 854 strlcpy(data + i * ETH_GSTRING_LEN, 855 mv88e6xxx_atu_vtu_stats_strings[i], 856 ETH_GSTRING_LEN); 857 } 858 859 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 860 u32 stringset, uint8_t *data) 861 { 862 struct mv88e6xxx_chip *chip = ds->priv; 863 int count = 0; 864 865 if (stringset != ETH_SS_STATS) 866 return; 867 868 mv88e6xxx_reg_lock(chip); 869 870 if (chip->info->ops->stats_get_strings) 871 count = chip->info->ops->stats_get_strings(chip, data); 872 873 if (chip->info->ops->serdes_get_strings) { 874 data += count * ETH_GSTRING_LEN; 875 count = chip->info->ops->serdes_get_strings(chip, port, data); 876 } 877 878 data += count * ETH_GSTRING_LEN; 879 mv88e6xxx_atu_vtu_get_strings(data); 880 881 mv88e6xxx_reg_unlock(chip); 882 } 883 884 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 885 int types) 886 { 887 struct mv88e6xxx_hw_stat *stat; 888 int i, j; 889 890 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 891 stat = &mv88e6xxx_hw_stats[i]; 892 if (stat->type & types) 893 j++; 894 } 895 return j; 896 } 897 898 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 899 { 900 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 901 STATS_TYPE_PORT); 902 } 903 904 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 905 { 906 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 907 } 908 909 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 910 { 911 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 912 STATS_TYPE_BANK1); 913 } 914 915 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 916 { 917 struct mv88e6xxx_chip *chip = ds->priv; 918 int serdes_count = 0; 919 int count = 0; 920 921 if (sset != ETH_SS_STATS) 922 return 0; 923 924 mv88e6xxx_reg_lock(chip); 925 if (chip->info->ops->stats_get_sset_count) 926 count = chip->info->ops->stats_get_sset_count(chip); 927 if (count < 0) 928 goto out; 929 930 if (chip->info->ops->serdes_get_sset_count) 931 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 932 port); 933 if (serdes_count < 0) { 934 count = serdes_count; 935 goto out; 936 } 937 count += serdes_count; 938 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 939 940 out: 941 mv88e6xxx_reg_unlock(chip); 942 943 return count; 944 } 945 946 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 947 uint64_t *data, int types, 948 u16 bank1_select, u16 histogram) 949 { 950 struct mv88e6xxx_hw_stat *stat; 951 int i, j; 952 953 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 954 stat = &mv88e6xxx_hw_stats[i]; 955 if (stat->type & types) { 956 mv88e6xxx_reg_lock(chip); 957 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 958 bank1_select, 959 histogram); 960 mv88e6xxx_reg_unlock(chip); 961 962 j++; 963 } 964 } 965 return j; 966 } 967 968 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 969 uint64_t *data) 970 { 971 return mv88e6xxx_stats_get_stats(chip, port, data, 972 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 973 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 974 } 975 976 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 977 uint64_t *data) 978 { 979 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 980 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 981 } 982 983 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 984 uint64_t *data) 985 { 986 return mv88e6xxx_stats_get_stats(chip, port, data, 987 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 988 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 989 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 990 } 991 992 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 993 uint64_t *data) 994 { 995 return mv88e6xxx_stats_get_stats(chip, port, data, 996 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 997 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 998 0); 999 } 1000 1001 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1002 uint64_t *data) 1003 { 1004 *data++ = chip->ports[port].atu_member_violation; 1005 *data++ = chip->ports[port].atu_miss_violation; 1006 *data++ = chip->ports[port].atu_full_violation; 1007 *data++ = chip->ports[port].vtu_member_violation; 1008 *data++ = chip->ports[port].vtu_miss_violation; 1009 } 1010 1011 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1012 uint64_t *data) 1013 { 1014 int count = 0; 1015 1016 if (chip->info->ops->stats_get_stats) 1017 count = chip->info->ops->stats_get_stats(chip, port, data); 1018 1019 mv88e6xxx_reg_lock(chip); 1020 if (chip->info->ops->serdes_get_stats) { 1021 data += count; 1022 count = chip->info->ops->serdes_get_stats(chip, port, data); 1023 } 1024 data += count; 1025 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1026 mv88e6xxx_reg_unlock(chip); 1027 } 1028 1029 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1030 uint64_t *data) 1031 { 1032 struct mv88e6xxx_chip *chip = ds->priv; 1033 int ret; 1034 1035 mv88e6xxx_reg_lock(chip); 1036 1037 ret = mv88e6xxx_stats_snapshot(chip, port); 1038 mv88e6xxx_reg_unlock(chip); 1039 1040 if (ret < 0) 1041 return; 1042 1043 mv88e6xxx_get_stats(chip, port, data); 1044 1045 } 1046 1047 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1048 { 1049 return 32 * sizeof(u16); 1050 } 1051 1052 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1053 struct ethtool_regs *regs, void *_p) 1054 { 1055 struct mv88e6xxx_chip *chip = ds->priv; 1056 int err; 1057 u16 reg; 1058 u16 *p = _p; 1059 int i; 1060 1061 regs->version = chip->info->prod_num; 1062 1063 memset(p, 0xff, 32 * sizeof(u16)); 1064 1065 mv88e6xxx_reg_lock(chip); 1066 1067 for (i = 0; i < 32; i++) { 1068 1069 err = mv88e6xxx_port_read(chip, port, i, ®); 1070 if (!err) 1071 p[i] = reg; 1072 } 1073 1074 mv88e6xxx_reg_unlock(chip); 1075 } 1076 1077 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1078 struct ethtool_eee *e) 1079 { 1080 /* Nothing to do on the port's MAC */ 1081 return 0; 1082 } 1083 1084 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1085 struct ethtool_eee *e) 1086 { 1087 /* Nothing to do on the port's MAC */ 1088 return 0; 1089 } 1090 1091 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1092 { 1093 struct dsa_switch *ds = NULL; 1094 struct net_device *br; 1095 u16 pvlan; 1096 int i; 1097 1098 if (dev < DSA_MAX_SWITCHES) 1099 ds = chip->ds->dst->ds[dev]; 1100 1101 /* Prevent frames from unknown switch or port */ 1102 if (!ds || port >= ds->num_ports) 1103 return 0; 1104 1105 /* Frames from DSA links and CPU ports can egress any local port */ 1106 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1107 return mv88e6xxx_port_mask(chip); 1108 1109 br = ds->ports[port].bridge_dev; 1110 pvlan = 0; 1111 1112 /* Frames from user ports can egress any local DSA links and CPU ports, 1113 * as well as any local member of their bridge group. 1114 */ 1115 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1116 if (dsa_is_cpu_port(chip->ds, i) || 1117 dsa_is_dsa_port(chip->ds, i) || 1118 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1119 pvlan |= BIT(i); 1120 1121 return pvlan; 1122 } 1123 1124 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1125 { 1126 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1127 1128 /* prevent frames from going back out of the port they came in on */ 1129 output_ports &= ~BIT(port); 1130 1131 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1132 } 1133 1134 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1135 u8 state) 1136 { 1137 struct mv88e6xxx_chip *chip = ds->priv; 1138 int err; 1139 1140 mv88e6xxx_reg_lock(chip); 1141 err = mv88e6xxx_port_set_state(chip, port, state); 1142 mv88e6xxx_reg_unlock(chip); 1143 1144 if (err) 1145 dev_err(ds->dev, "p%d: failed to update state\n", port); 1146 } 1147 1148 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1149 { 1150 int err; 1151 1152 if (chip->info->ops->ieee_pri_map) { 1153 err = chip->info->ops->ieee_pri_map(chip); 1154 if (err) 1155 return err; 1156 } 1157 1158 if (chip->info->ops->ip_pri_map) { 1159 err = chip->info->ops->ip_pri_map(chip); 1160 if (err) 1161 return err; 1162 } 1163 1164 return 0; 1165 } 1166 1167 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1168 { 1169 int target, port; 1170 int err; 1171 1172 if (!chip->info->global2_addr) 1173 return 0; 1174 1175 /* Initialize the routing port to the 32 possible target devices */ 1176 for (target = 0; target < 32; target++) { 1177 port = 0x1f; 1178 if (target < DSA_MAX_SWITCHES) 1179 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1180 port = chip->ds->rtable[target]; 1181 1182 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1183 if (err) 1184 return err; 1185 } 1186 1187 if (chip->info->ops->set_cascade_port) { 1188 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1189 err = chip->info->ops->set_cascade_port(chip, port); 1190 if (err) 1191 return err; 1192 } 1193 1194 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1195 if (err) 1196 return err; 1197 1198 return 0; 1199 } 1200 1201 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1202 { 1203 /* Clear all trunk masks and mapping */ 1204 if (chip->info->global2_addr) 1205 return mv88e6xxx_g2_trunk_clear(chip); 1206 1207 return 0; 1208 } 1209 1210 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1211 { 1212 if (chip->info->ops->rmu_disable) 1213 return chip->info->ops->rmu_disable(chip); 1214 1215 return 0; 1216 } 1217 1218 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1219 { 1220 if (chip->info->ops->pot_clear) 1221 return chip->info->ops->pot_clear(chip); 1222 1223 return 0; 1224 } 1225 1226 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1227 { 1228 if (chip->info->ops->mgmt_rsvd2cpu) 1229 return chip->info->ops->mgmt_rsvd2cpu(chip); 1230 1231 return 0; 1232 } 1233 1234 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1235 { 1236 int err; 1237 1238 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1239 if (err) 1240 return err; 1241 1242 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1243 if (err) 1244 return err; 1245 1246 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1247 } 1248 1249 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1250 { 1251 int port; 1252 int err; 1253 1254 if (!chip->info->ops->irl_init_all) 1255 return 0; 1256 1257 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1258 /* Disable ingress rate limiting by resetting all per port 1259 * ingress rate limit resources to their initial state. 1260 */ 1261 err = chip->info->ops->irl_init_all(chip, port); 1262 if (err) 1263 return err; 1264 } 1265 1266 return 0; 1267 } 1268 1269 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1270 { 1271 if (chip->info->ops->set_switch_mac) { 1272 u8 addr[ETH_ALEN]; 1273 1274 eth_random_addr(addr); 1275 1276 return chip->info->ops->set_switch_mac(chip, addr); 1277 } 1278 1279 return 0; 1280 } 1281 1282 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1283 { 1284 u16 pvlan = 0; 1285 1286 if (!mv88e6xxx_has_pvt(chip)) 1287 return -EOPNOTSUPP; 1288 1289 /* Skip the local source device, which uses in-chip port VLAN */ 1290 if (dev != chip->ds->index) 1291 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1292 1293 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1294 } 1295 1296 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1297 { 1298 int dev, port; 1299 int err; 1300 1301 if (!mv88e6xxx_has_pvt(chip)) 1302 return 0; 1303 1304 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1305 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1306 */ 1307 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1308 if (err) 1309 return err; 1310 1311 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1312 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1313 err = mv88e6xxx_pvt_map(chip, dev, port); 1314 if (err) 1315 return err; 1316 } 1317 } 1318 1319 return 0; 1320 } 1321 1322 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1323 { 1324 struct mv88e6xxx_chip *chip = ds->priv; 1325 int err; 1326 1327 mv88e6xxx_reg_lock(chip); 1328 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1329 mv88e6xxx_reg_unlock(chip); 1330 1331 if (err) 1332 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1333 } 1334 1335 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1336 { 1337 if (!chip->info->max_vid) 1338 return 0; 1339 1340 return mv88e6xxx_g1_vtu_flush(chip); 1341 } 1342 1343 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1344 struct mv88e6xxx_vtu_entry *entry) 1345 { 1346 if (!chip->info->ops->vtu_getnext) 1347 return -EOPNOTSUPP; 1348 1349 return chip->info->ops->vtu_getnext(chip, entry); 1350 } 1351 1352 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1353 struct mv88e6xxx_vtu_entry *entry) 1354 { 1355 if (!chip->info->ops->vtu_loadpurge) 1356 return -EOPNOTSUPP; 1357 1358 return chip->info->ops->vtu_loadpurge(chip, entry); 1359 } 1360 1361 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1362 { 1363 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1364 struct mv88e6xxx_vtu_entry vlan; 1365 int i, err; 1366 1367 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1368 1369 /* Set every FID bit used by the (un)bridged ports */ 1370 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1371 err = mv88e6xxx_port_get_fid(chip, i, fid); 1372 if (err) 1373 return err; 1374 1375 set_bit(*fid, fid_bitmap); 1376 } 1377 1378 /* Set every FID bit used by the VLAN entries */ 1379 vlan.vid = chip->info->max_vid; 1380 vlan.valid = false; 1381 1382 do { 1383 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1384 if (err) 1385 return err; 1386 1387 if (!vlan.valid) 1388 break; 1389 1390 set_bit(vlan.fid, fid_bitmap); 1391 } while (vlan.vid < chip->info->max_vid); 1392 1393 /* The reset value 0x000 is used to indicate that multiple address 1394 * databases are not needed. Return the next positive available. 1395 */ 1396 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1397 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1398 return -ENOSPC; 1399 1400 /* Clear the database */ 1401 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1402 } 1403 1404 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1405 u16 vid_begin, u16 vid_end) 1406 { 1407 struct mv88e6xxx_chip *chip = ds->priv; 1408 struct mv88e6xxx_vtu_entry vlan; 1409 int i, err; 1410 1411 /* DSA and CPU ports have to be members of multiple vlans */ 1412 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1413 return 0; 1414 1415 if (!vid_begin) 1416 return -EOPNOTSUPP; 1417 1418 vlan.vid = vid_begin - 1; 1419 vlan.valid = false; 1420 1421 do { 1422 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1423 if (err) 1424 return err; 1425 1426 if (!vlan.valid) 1427 break; 1428 1429 if (vlan.vid > vid_end) 1430 break; 1431 1432 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1433 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1434 continue; 1435 1436 if (!ds->ports[i].slave) 1437 continue; 1438 1439 if (vlan.member[i] == 1440 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1441 continue; 1442 1443 if (dsa_to_port(ds, i)->bridge_dev == 1444 ds->ports[port].bridge_dev) 1445 break; /* same bridge, check next VLAN */ 1446 1447 if (!dsa_to_port(ds, i)->bridge_dev) 1448 continue; 1449 1450 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1451 port, vlan.vid, i, 1452 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1453 return -EOPNOTSUPP; 1454 } 1455 } while (vlan.vid < vid_end); 1456 1457 return 0; 1458 } 1459 1460 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1461 bool vlan_filtering) 1462 { 1463 struct mv88e6xxx_chip *chip = ds->priv; 1464 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1465 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1466 int err; 1467 1468 if (!chip->info->max_vid) 1469 return -EOPNOTSUPP; 1470 1471 mv88e6xxx_reg_lock(chip); 1472 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1473 mv88e6xxx_reg_unlock(chip); 1474 1475 return err; 1476 } 1477 1478 static int 1479 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1480 const struct switchdev_obj_port_vlan *vlan) 1481 { 1482 struct mv88e6xxx_chip *chip = ds->priv; 1483 int err; 1484 1485 if (!chip->info->max_vid) 1486 return -EOPNOTSUPP; 1487 1488 /* If the requested port doesn't belong to the same bridge as the VLAN 1489 * members, do not support it (yet) and fallback to software VLAN. 1490 */ 1491 mv88e6xxx_reg_lock(chip); 1492 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1493 vlan->vid_end); 1494 mv88e6xxx_reg_unlock(chip); 1495 1496 /* We don't need any dynamic resource from the kernel (yet), 1497 * so skip the prepare phase. 1498 */ 1499 return err; 1500 } 1501 1502 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1503 const unsigned char *addr, u16 vid, 1504 u8 state) 1505 { 1506 struct mv88e6xxx_atu_entry entry; 1507 struct mv88e6xxx_vtu_entry vlan; 1508 u16 fid; 1509 int err; 1510 1511 /* Null VLAN ID corresponds to the port private database */ 1512 if (vid == 0) { 1513 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1514 if (err) 1515 return err; 1516 } else { 1517 vlan.vid = vid - 1; 1518 vlan.valid = false; 1519 1520 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1521 if (err) 1522 return err; 1523 1524 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1525 if (vlan.vid != vid || !vlan.valid) 1526 return -EOPNOTSUPP; 1527 1528 fid = vlan.fid; 1529 } 1530 1531 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1532 ether_addr_copy(entry.mac, addr); 1533 eth_addr_dec(entry.mac); 1534 1535 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1536 if (err) 1537 return err; 1538 1539 /* Initialize a fresh ATU entry if it isn't found */ 1540 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1541 !ether_addr_equal(entry.mac, addr)) { 1542 memset(&entry, 0, sizeof(entry)); 1543 ether_addr_copy(entry.mac, addr); 1544 } 1545 1546 /* Purge the ATU entry only if no port is using it anymore */ 1547 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1548 entry.portvec &= ~BIT(port); 1549 if (!entry.portvec) 1550 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1551 } else { 1552 entry.portvec |= BIT(port); 1553 entry.state = state; 1554 } 1555 1556 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1557 } 1558 1559 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1560 u16 vid) 1561 { 1562 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1563 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1564 1565 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1566 } 1567 1568 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1569 { 1570 int port; 1571 int err; 1572 1573 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1574 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1575 if (err) 1576 return err; 1577 } 1578 1579 return 0; 1580 } 1581 1582 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1583 u16 vid, u8 member) 1584 { 1585 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1586 struct mv88e6xxx_vtu_entry vlan; 1587 int i, err; 1588 1589 if (!vid) 1590 return -EOPNOTSUPP; 1591 1592 vlan.vid = vid - 1; 1593 vlan.valid = false; 1594 1595 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1596 if (err) 1597 return err; 1598 1599 if (vlan.vid != vid || !vlan.valid) { 1600 memset(&vlan, 0, sizeof(vlan)); 1601 1602 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1603 if (err) 1604 return err; 1605 1606 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1607 if (i == port) 1608 vlan.member[i] = member; 1609 else 1610 vlan.member[i] = non_member; 1611 1612 vlan.vid = vid; 1613 vlan.valid = true; 1614 1615 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1616 if (err) 1617 return err; 1618 1619 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1620 if (err) 1621 return err; 1622 } else if (vlan.member[port] != member) { 1623 vlan.member[port] = member; 1624 1625 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1626 if (err) 1627 return err; 1628 } else { 1629 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1630 port, vid); 1631 } 1632 1633 return 0; 1634 } 1635 1636 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1637 const struct switchdev_obj_port_vlan *vlan) 1638 { 1639 struct mv88e6xxx_chip *chip = ds->priv; 1640 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1641 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1642 u8 member; 1643 u16 vid; 1644 1645 if (!chip->info->max_vid) 1646 return; 1647 1648 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1649 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1650 else if (untagged) 1651 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1652 else 1653 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1654 1655 mv88e6xxx_reg_lock(chip); 1656 1657 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1658 if (mv88e6xxx_port_vlan_join(chip, port, vid, member)) 1659 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1660 vid, untagged ? 'u' : 't'); 1661 1662 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1663 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1664 vlan->vid_end); 1665 1666 mv88e6xxx_reg_unlock(chip); 1667 } 1668 1669 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1670 int port, u16 vid) 1671 { 1672 struct mv88e6xxx_vtu_entry vlan; 1673 int i, err; 1674 1675 if (!vid) 1676 return -EOPNOTSUPP; 1677 1678 vlan.vid = vid - 1; 1679 vlan.valid = false; 1680 1681 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1682 if (err) 1683 return err; 1684 1685 /* If the VLAN doesn't exist in hardware or the port isn't a member, 1686 * tell switchdev that this VLAN is likely handled in software. 1687 */ 1688 if (vlan.vid != vid || !vlan.valid || 1689 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1690 return -EOPNOTSUPP; 1691 1692 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1693 1694 /* keep the VLAN unless all ports are excluded */ 1695 vlan.valid = false; 1696 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1697 if (vlan.member[i] != 1698 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1699 vlan.valid = true; 1700 break; 1701 } 1702 } 1703 1704 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1705 if (err) 1706 return err; 1707 1708 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1709 } 1710 1711 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1712 const struct switchdev_obj_port_vlan *vlan) 1713 { 1714 struct mv88e6xxx_chip *chip = ds->priv; 1715 u16 pvid, vid; 1716 int err = 0; 1717 1718 if (!chip->info->max_vid) 1719 return -EOPNOTSUPP; 1720 1721 mv88e6xxx_reg_lock(chip); 1722 1723 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1724 if (err) 1725 goto unlock; 1726 1727 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1728 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 1729 if (err) 1730 goto unlock; 1731 1732 if (vid == pvid) { 1733 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1734 if (err) 1735 goto unlock; 1736 } 1737 } 1738 1739 unlock: 1740 mv88e6xxx_reg_unlock(chip); 1741 1742 return err; 1743 } 1744 1745 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1746 const unsigned char *addr, u16 vid) 1747 { 1748 struct mv88e6xxx_chip *chip = ds->priv; 1749 int err; 1750 1751 mv88e6xxx_reg_lock(chip); 1752 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1753 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1754 mv88e6xxx_reg_unlock(chip); 1755 1756 return err; 1757 } 1758 1759 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1760 const unsigned char *addr, u16 vid) 1761 { 1762 struct mv88e6xxx_chip *chip = ds->priv; 1763 int err; 1764 1765 mv88e6xxx_reg_lock(chip); 1766 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1767 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1768 mv88e6xxx_reg_unlock(chip); 1769 1770 return err; 1771 } 1772 1773 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1774 u16 fid, u16 vid, int port, 1775 dsa_fdb_dump_cb_t *cb, void *data) 1776 { 1777 struct mv88e6xxx_atu_entry addr; 1778 bool is_static; 1779 int err; 1780 1781 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1782 eth_broadcast_addr(addr.mac); 1783 1784 do { 1785 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1786 if (err) 1787 return err; 1788 1789 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1790 break; 1791 1792 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1793 continue; 1794 1795 if (!is_unicast_ether_addr(addr.mac)) 1796 continue; 1797 1798 is_static = (addr.state == 1799 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1800 err = cb(addr.mac, vid, is_static, data); 1801 if (err) 1802 return err; 1803 } while (!is_broadcast_ether_addr(addr.mac)); 1804 1805 return err; 1806 } 1807 1808 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1809 dsa_fdb_dump_cb_t *cb, void *data) 1810 { 1811 struct mv88e6xxx_vtu_entry vlan; 1812 u16 fid; 1813 int err; 1814 1815 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1816 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1817 if (err) 1818 return err; 1819 1820 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1821 if (err) 1822 return err; 1823 1824 /* Dump VLANs' Filtering Information Databases */ 1825 vlan.vid = chip->info->max_vid; 1826 vlan.valid = false; 1827 1828 do { 1829 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1830 if (err) 1831 return err; 1832 1833 if (!vlan.valid) 1834 break; 1835 1836 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1837 cb, data); 1838 if (err) 1839 return err; 1840 } while (vlan.vid < chip->info->max_vid); 1841 1842 return err; 1843 } 1844 1845 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1846 dsa_fdb_dump_cb_t *cb, void *data) 1847 { 1848 struct mv88e6xxx_chip *chip = ds->priv; 1849 int err; 1850 1851 mv88e6xxx_reg_lock(chip); 1852 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1853 mv88e6xxx_reg_unlock(chip); 1854 1855 return err; 1856 } 1857 1858 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1859 struct net_device *br) 1860 { 1861 struct dsa_switch *ds; 1862 int port; 1863 int dev; 1864 int err; 1865 1866 /* Remap the Port VLAN of each local bridge group member */ 1867 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1868 if (chip->ds->ports[port].bridge_dev == br) { 1869 err = mv88e6xxx_port_vlan_map(chip, port); 1870 if (err) 1871 return err; 1872 } 1873 } 1874 1875 if (!mv88e6xxx_has_pvt(chip)) 1876 return 0; 1877 1878 /* Remap the Port VLAN of each cross-chip bridge group member */ 1879 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1880 ds = chip->ds->dst->ds[dev]; 1881 if (!ds) 1882 break; 1883 1884 for (port = 0; port < ds->num_ports; ++port) { 1885 if (ds->ports[port].bridge_dev == br) { 1886 err = mv88e6xxx_pvt_map(chip, dev, port); 1887 if (err) 1888 return err; 1889 } 1890 } 1891 } 1892 1893 return 0; 1894 } 1895 1896 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1897 struct net_device *br) 1898 { 1899 struct mv88e6xxx_chip *chip = ds->priv; 1900 int err; 1901 1902 mv88e6xxx_reg_lock(chip); 1903 err = mv88e6xxx_bridge_map(chip, br); 1904 mv88e6xxx_reg_unlock(chip); 1905 1906 return err; 1907 } 1908 1909 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1910 struct net_device *br) 1911 { 1912 struct mv88e6xxx_chip *chip = ds->priv; 1913 1914 mv88e6xxx_reg_lock(chip); 1915 if (mv88e6xxx_bridge_map(chip, br) || 1916 mv88e6xxx_port_vlan_map(chip, port)) 1917 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1918 mv88e6xxx_reg_unlock(chip); 1919 } 1920 1921 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1922 int port, struct net_device *br) 1923 { 1924 struct mv88e6xxx_chip *chip = ds->priv; 1925 int err; 1926 1927 if (!mv88e6xxx_has_pvt(chip)) 1928 return 0; 1929 1930 mv88e6xxx_reg_lock(chip); 1931 err = mv88e6xxx_pvt_map(chip, dev, port); 1932 mv88e6xxx_reg_unlock(chip); 1933 1934 return err; 1935 } 1936 1937 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1938 int port, struct net_device *br) 1939 { 1940 struct mv88e6xxx_chip *chip = ds->priv; 1941 1942 if (!mv88e6xxx_has_pvt(chip)) 1943 return; 1944 1945 mv88e6xxx_reg_lock(chip); 1946 if (mv88e6xxx_pvt_map(chip, dev, port)) 1947 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1948 mv88e6xxx_reg_unlock(chip); 1949 } 1950 1951 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1952 { 1953 if (chip->info->ops->reset) 1954 return chip->info->ops->reset(chip); 1955 1956 return 0; 1957 } 1958 1959 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1960 { 1961 struct gpio_desc *gpiod = chip->reset; 1962 1963 /* If there is a GPIO connected to the reset pin, toggle it */ 1964 if (gpiod) { 1965 gpiod_set_value_cansleep(gpiod, 1); 1966 usleep_range(10000, 20000); 1967 gpiod_set_value_cansleep(gpiod, 0); 1968 usleep_range(10000, 20000); 1969 } 1970 } 1971 1972 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1973 { 1974 int i, err; 1975 1976 /* Set all ports to the Disabled state */ 1977 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1978 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1979 if (err) 1980 return err; 1981 } 1982 1983 /* Wait for transmit queues to drain, 1984 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1985 */ 1986 usleep_range(2000, 4000); 1987 1988 return 0; 1989 } 1990 1991 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1992 { 1993 int err; 1994 1995 err = mv88e6xxx_disable_ports(chip); 1996 if (err) 1997 return err; 1998 1999 mv88e6xxx_hardware_reset(chip); 2000 2001 return mv88e6xxx_software_reset(chip); 2002 } 2003 2004 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2005 enum mv88e6xxx_frame_mode frame, 2006 enum mv88e6xxx_egress_mode egress, u16 etype) 2007 { 2008 int err; 2009 2010 if (!chip->info->ops->port_set_frame_mode) 2011 return -EOPNOTSUPP; 2012 2013 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2014 if (err) 2015 return err; 2016 2017 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2018 if (err) 2019 return err; 2020 2021 if (chip->info->ops->port_set_ether_type) 2022 return chip->info->ops->port_set_ether_type(chip, port, etype); 2023 2024 return 0; 2025 } 2026 2027 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2028 { 2029 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2030 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2031 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2032 } 2033 2034 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2035 { 2036 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2037 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2038 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2039 } 2040 2041 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2042 { 2043 return mv88e6xxx_set_port_mode(chip, port, 2044 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2045 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2046 ETH_P_EDSA); 2047 } 2048 2049 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2050 { 2051 if (dsa_is_dsa_port(chip->ds, port)) 2052 return mv88e6xxx_set_port_mode_dsa(chip, port); 2053 2054 if (dsa_is_user_port(chip->ds, port)) 2055 return mv88e6xxx_set_port_mode_normal(chip, port); 2056 2057 /* Setup CPU port mode depending on its supported tag format */ 2058 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2059 return mv88e6xxx_set_port_mode_dsa(chip, port); 2060 2061 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2062 return mv88e6xxx_set_port_mode_edsa(chip, port); 2063 2064 return -EINVAL; 2065 } 2066 2067 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2068 { 2069 bool message = dsa_is_dsa_port(chip->ds, port); 2070 2071 return mv88e6xxx_port_set_message_port(chip, port, message); 2072 } 2073 2074 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2075 { 2076 struct dsa_switch *ds = chip->ds; 2077 bool flood; 2078 2079 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2080 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2081 if (chip->info->ops->port_set_egress_floods) 2082 return chip->info->ops->port_set_egress_floods(chip, port, 2083 flood, flood); 2084 2085 return 0; 2086 } 2087 2088 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2089 bool on) 2090 { 2091 if (chip->info->ops->serdes_power) 2092 return chip->info->ops->serdes_power(chip, port, on); 2093 2094 return 0; 2095 } 2096 2097 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2098 { 2099 struct dsa_switch *ds = chip->ds; 2100 int upstream_port; 2101 int err; 2102 2103 upstream_port = dsa_upstream_port(ds, port); 2104 if (chip->info->ops->port_set_upstream_port) { 2105 err = chip->info->ops->port_set_upstream_port(chip, port, 2106 upstream_port); 2107 if (err) 2108 return err; 2109 } 2110 2111 if (port == upstream_port) { 2112 if (chip->info->ops->set_cpu_port) { 2113 err = chip->info->ops->set_cpu_port(chip, 2114 upstream_port); 2115 if (err) 2116 return err; 2117 } 2118 2119 if (chip->info->ops->set_egress_port) { 2120 err = chip->info->ops->set_egress_port(chip, 2121 upstream_port); 2122 if (err) 2123 return err; 2124 } 2125 } 2126 2127 return 0; 2128 } 2129 2130 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2131 { 2132 struct dsa_switch *ds = chip->ds; 2133 int err; 2134 u16 reg; 2135 2136 chip->ports[port].chip = chip; 2137 chip->ports[port].port = port; 2138 2139 /* MAC Forcing register: don't force link, speed, duplex or flow control 2140 * state to any particular values on physical ports, but force the CPU 2141 * port and all DSA ports to their maximum bandwidth and full duplex. 2142 */ 2143 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2144 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2145 SPEED_MAX, DUPLEX_FULL, 2146 PAUSE_OFF, 2147 PHY_INTERFACE_MODE_NA); 2148 else 2149 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2150 SPEED_UNFORCED, DUPLEX_UNFORCED, 2151 PAUSE_ON, 2152 PHY_INTERFACE_MODE_NA); 2153 if (err) 2154 return err; 2155 2156 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2157 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2158 * tunneling, determine priority by looking at 802.1p and IP 2159 * priority fields (IP prio has precedence), and set STP state 2160 * to Forwarding. 2161 * 2162 * If this is the CPU link, use DSA or EDSA tagging depending 2163 * on which tagging mode was configured. 2164 * 2165 * If this is a link to another switch, use DSA tagging mode. 2166 * 2167 * If this is the upstream port for this switch, enable 2168 * forwarding of unknown unicasts and multicasts. 2169 */ 2170 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2171 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2172 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2173 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2174 if (err) 2175 return err; 2176 2177 err = mv88e6xxx_setup_port_mode(chip, port); 2178 if (err) 2179 return err; 2180 2181 err = mv88e6xxx_setup_egress_floods(chip, port); 2182 if (err) 2183 return err; 2184 2185 /* Enable the SERDES interface for DSA and CPU ports. Normal 2186 * ports SERDES are enabled when the port is enabled, thus 2187 * saving a bit of power. 2188 */ 2189 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2190 err = mv88e6xxx_serdes_power(chip, port, true); 2191 if (err) 2192 return err; 2193 } 2194 2195 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2196 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2197 * untagged frames on this port, do a destination address lookup on all 2198 * received packets as usual, disable ARP mirroring and don't send a 2199 * copy of all transmitted/received frames on this port to the CPU. 2200 */ 2201 err = mv88e6xxx_port_set_map_da(chip, port); 2202 if (err) 2203 return err; 2204 2205 err = mv88e6xxx_setup_upstream_port(chip, port); 2206 if (err) 2207 return err; 2208 2209 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2210 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2211 if (err) 2212 return err; 2213 2214 if (chip->info->ops->port_set_jumbo_size) { 2215 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2216 if (err) 2217 return err; 2218 } 2219 2220 /* Port Association Vector: when learning source addresses 2221 * of packets, add the address to the address database using 2222 * a port bitmap that has only the bit for this port set and 2223 * the other bits clear. 2224 */ 2225 reg = 1 << port; 2226 /* Disable learning for CPU port */ 2227 if (dsa_is_cpu_port(ds, port)) 2228 reg = 0; 2229 2230 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2231 reg); 2232 if (err) 2233 return err; 2234 2235 /* Egress rate control 2: disable egress rate control. */ 2236 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2237 0x0000); 2238 if (err) 2239 return err; 2240 2241 if (chip->info->ops->port_pause_limit) { 2242 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2243 if (err) 2244 return err; 2245 } 2246 2247 if (chip->info->ops->port_disable_learn_limit) { 2248 err = chip->info->ops->port_disable_learn_limit(chip, port); 2249 if (err) 2250 return err; 2251 } 2252 2253 if (chip->info->ops->port_disable_pri_override) { 2254 err = chip->info->ops->port_disable_pri_override(chip, port); 2255 if (err) 2256 return err; 2257 } 2258 2259 if (chip->info->ops->port_tag_remap) { 2260 err = chip->info->ops->port_tag_remap(chip, port); 2261 if (err) 2262 return err; 2263 } 2264 2265 if (chip->info->ops->port_egress_rate_limiting) { 2266 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2267 if (err) 2268 return err; 2269 } 2270 2271 if (chip->info->ops->port_setup_message_port) { 2272 err = chip->info->ops->port_setup_message_port(chip, port); 2273 if (err) 2274 return err; 2275 } 2276 2277 /* Port based VLAN map: give each port the same default address 2278 * database, and allow bidirectional communication between the 2279 * CPU and DSA port(s), and the other ports. 2280 */ 2281 err = mv88e6xxx_port_set_fid(chip, port, 0); 2282 if (err) 2283 return err; 2284 2285 err = mv88e6xxx_port_vlan_map(chip, port); 2286 if (err) 2287 return err; 2288 2289 /* Default VLAN ID and priority: don't set a default VLAN 2290 * ID, and set the default packet priority to zero. 2291 */ 2292 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2293 } 2294 2295 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2296 struct phy_device *phydev) 2297 { 2298 struct mv88e6xxx_chip *chip = ds->priv; 2299 int err; 2300 2301 mv88e6xxx_reg_lock(chip); 2302 2303 err = mv88e6xxx_serdes_power(chip, port, true); 2304 2305 if (!err && chip->info->ops->serdes_irq_setup) 2306 err = chip->info->ops->serdes_irq_setup(chip, port); 2307 2308 mv88e6xxx_reg_unlock(chip); 2309 2310 return err; 2311 } 2312 2313 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2314 { 2315 struct mv88e6xxx_chip *chip = ds->priv; 2316 2317 mv88e6xxx_reg_lock(chip); 2318 2319 if (mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED)) 2320 dev_err(chip->dev, "failed to disable port\n"); 2321 2322 if (chip->info->ops->serdes_irq_free) 2323 chip->info->ops->serdes_irq_free(chip, port); 2324 2325 if (mv88e6xxx_serdes_power(chip, port, false)) 2326 dev_err(chip->dev, "failed to power off SERDES\n"); 2327 2328 mv88e6xxx_reg_unlock(chip); 2329 } 2330 2331 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2332 unsigned int ageing_time) 2333 { 2334 struct mv88e6xxx_chip *chip = ds->priv; 2335 int err; 2336 2337 mv88e6xxx_reg_lock(chip); 2338 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2339 mv88e6xxx_reg_unlock(chip); 2340 2341 return err; 2342 } 2343 2344 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2345 { 2346 int err; 2347 2348 /* Initialize the statistics unit */ 2349 if (chip->info->ops->stats_set_histogram) { 2350 err = chip->info->ops->stats_set_histogram(chip); 2351 if (err) 2352 return err; 2353 } 2354 2355 return mv88e6xxx_g1_stats_clear(chip); 2356 } 2357 2358 /* The mv88e6390 has some hidden registers used for debug and 2359 * development. The errata also makes use of them. 2360 */ 2361 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port, 2362 int reg, u16 val) 2363 { 2364 u16 ctrl; 2365 int err; 2366 2367 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT, 2368 PORT_RESERVED_1A, val); 2369 if (err) 2370 return err; 2371 2372 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE | 2373 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2374 reg; 2375 2376 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2377 PORT_RESERVED_1A, ctrl); 2378 } 2379 2380 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip) 2381 { 2382 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT, 2383 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY); 2384 } 2385 2386 2387 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port, 2388 int reg, u16 *val) 2389 { 2390 u16 ctrl; 2391 int err; 2392 2393 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ | 2394 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2395 reg; 2396 2397 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2398 PORT_RESERVED_1A, ctrl); 2399 if (err) 2400 return err; 2401 2402 err = mv88e6390_hidden_wait(chip); 2403 if (err) 2404 return err; 2405 2406 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT, 2407 PORT_RESERVED_1A, val); 2408 } 2409 2410 /* Check if the errata has already been applied. */ 2411 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2412 { 2413 int port; 2414 int err; 2415 u16 val; 2416 2417 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2418 err = mv88e6390_hidden_read(chip, port, 0, &val); 2419 if (err) { 2420 dev_err(chip->dev, 2421 "Error reading hidden register: %d\n", err); 2422 return false; 2423 } 2424 if (val != 0x01c0) 2425 return false; 2426 } 2427 2428 return true; 2429 } 2430 2431 /* The 6390 copper ports have an errata which require poking magic 2432 * values into undocumented hidden registers and then performing a 2433 * software reset. 2434 */ 2435 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2436 { 2437 int port; 2438 int err; 2439 2440 if (mv88e6390_setup_errata_applied(chip)) 2441 return 0; 2442 2443 /* Set the ports into blocking mode */ 2444 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2445 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2446 if (err) 2447 return err; 2448 } 2449 2450 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2451 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0); 2452 if (err) 2453 return err; 2454 } 2455 2456 return mv88e6xxx_software_reset(chip); 2457 } 2458 2459 static int mv88e6xxx_setup(struct dsa_switch *ds) 2460 { 2461 struct mv88e6xxx_chip *chip = ds->priv; 2462 u8 cmode; 2463 int err; 2464 int i; 2465 2466 chip->ds = ds; 2467 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2468 2469 mv88e6xxx_reg_lock(chip); 2470 2471 if (chip->info->ops->setup_errata) { 2472 err = chip->info->ops->setup_errata(chip); 2473 if (err) 2474 goto unlock; 2475 } 2476 2477 /* Cache the cmode of each port. */ 2478 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2479 if (chip->info->ops->port_get_cmode) { 2480 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2481 if (err) 2482 goto unlock; 2483 2484 chip->ports[i].cmode = cmode; 2485 } 2486 } 2487 2488 /* Setup Switch Port Registers */ 2489 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2490 /* Prevent the use of an invalid port. */ 2491 if (mv88e6xxx_is_invalid_port(chip, i) && 2492 !dsa_is_unused_port(ds, i)) { 2493 dev_err(chip->dev, "port %d is invalid\n", i); 2494 err = -EINVAL; 2495 goto unlock; 2496 } 2497 2498 if (dsa_is_unused_port(ds, i)) { 2499 err = mv88e6xxx_port_set_state(chip, i, 2500 BR_STATE_DISABLED); 2501 if (err) 2502 goto unlock; 2503 2504 err = mv88e6xxx_serdes_power(chip, i, false); 2505 if (err) 2506 goto unlock; 2507 2508 continue; 2509 } 2510 2511 err = mv88e6xxx_setup_port(chip, i); 2512 if (err) 2513 goto unlock; 2514 } 2515 2516 err = mv88e6xxx_irl_setup(chip); 2517 if (err) 2518 goto unlock; 2519 2520 err = mv88e6xxx_mac_setup(chip); 2521 if (err) 2522 goto unlock; 2523 2524 err = mv88e6xxx_phy_setup(chip); 2525 if (err) 2526 goto unlock; 2527 2528 err = mv88e6xxx_vtu_setup(chip); 2529 if (err) 2530 goto unlock; 2531 2532 err = mv88e6xxx_pvt_setup(chip); 2533 if (err) 2534 goto unlock; 2535 2536 err = mv88e6xxx_atu_setup(chip); 2537 if (err) 2538 goto unlock; 2539 2540 err = mv88e6xxx_broadcast_setup(chip, 0); 2541 if (err) 2542 goto unlock; 2543 2544 err = mv88e6xxx_pot_setup(chip); 2545 if (err) 2546 goto unlock; 2547 2548 err = mv88e6xxx_rmu_setup(chip); 2549 if (err) 2550 goto unlock; 2551 2552 err = mv88e6xxx_rsvd2cpu_setup(chip); 2553 if (err) 2554 goto unlock; 2555 2556 err = mv88e6xxx_trunk_setup(chip); 2557 if (err) 2558 goto unlock; 2559 2560 err = mv88e6xxx_devmap_setup(chip); 2561 if (err) 2562 goto unlock; 2563 2564 err = mv88e6xxx_pri_setup(chip); 2565 if (err) 2566 goto unlock; 2567 2568 /* Setup PTP Hardware Clock and timestamping */ 2569 if (chip->info->ptp_support) { 2570 err = mv88e6xxx_ptp_setup(chip); 2571 if (err) 2572 goto unlock; 2573 2574 err = mv88e6xxx_hwtstamp_setup(chip); 2575 if (err) 2576 goto unlock; 2577 } 2578 2579 err = mv88e6xxx_stats_setup(chip); 2580 if (err) 2581 goto unlock; 2582 2583 unlock: 2584 mv88e6xxx_reg_unlock(chip); 2585 2586 return err; 2587 } 2588 2589 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2590 { 2591 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2592 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2593 u16 val; 2594 int err; 2595 2596 if (!chip->info->ops->phy_read) 2597 return -EOPNOTSUPP; 2598 2599 mv88e6xxx_reg_lock(chip); 2600 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2601 mv88e6xxx_reg_unlock(chip); 2602 2603 if (reg == MII_PHYSID2) { 2604 /* Some internal PHYs don't have a model number. */ 2605 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2606 /* Then there is the 6165 family. It gets is 2607 * PHYs correct. But it can also have two 2608 * SERDES interfaces in the PHY address 2609 * space. And these don't have a model 2610 * number. But they are not PHYs, so we don't 2611 * want to give them something a PHY driver 2612 * will recognise. 2613 * 2614 * Use the mv88e6390 family model number 2615 * instead, for anything which really could be 2616 * a PHY, 2617 */ 2618 if (!(val & 0x3f0)) 2619 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2620 } 2621 2622 return err ? err : val; 2623 } 2624 2625 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2626 { 2627 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2628 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2629 int err; 2630 2631 if (!chip->info->ops->phy_write) 2632 return -EOPNOTSUPP; 2633 2634 mv88e6xxx_reg_lock(chip); 2635 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2636 mv88e6xxx_reg_unlock(chip); 2637 2638 return err; 2639 } 2640 2641 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2642 struct device_node *np, 2643 bool external) 2644 { 2645 static int index; 2646 struct mv88e6xxx_mdio_bus *mdio_bus; 2647 struct mii_bus *bus; 2648 int err; 2649 2650 if (external) { 2651 mv88e6xxx_reg_lock(chip); 2652 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2653 mv88e6xxx_reg_unlock(chip); 2654 2655 if (err) 2656 return err; 2657 } 2658 2659 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2660 if (!bus) 2661 return -ENOMEM; 2662 2663 mdio_bus = bus->priv; 2664 mdio_bus->bus = bus; 2665 mdio_bus->chip = chip; 2666 INIT_LIST_HEAD(&mdio_bus->list); 2667 mdio_bus->external = external; 2668 2669 if (np) { 2670 bus->name = np->full_name; 2671 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2672 } else { 2673 bus->name = "mv88e6xxx SMI"; 2674 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2675 } 2676 2677 bus->read = mv88e6xxx_mdio_read; 2678 bus->write = mv88e6xxx_mdio_write; 2679 bus->parent = chip->dev; 2680 2681 if (!external) { 2682 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2683 if (err) 2684 return err; 2685 } 2686 2687 err = of_mdiobus_register(bus, np); 2688 if (err) { 2689 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2690 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2691 return err; 2692 } 2693 2694 if (external) 2695 list_add_tail(&mdio_bus->list, &chip->mdios); 2696 else 2697 list_add(&mdio_bus->list, &chip->mdios); 2698 2699 return 0; 2700 } 2701 2702 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2703 { .compatible = "marvell,mv88e6xxx-mdio-external", 2704 .data = (void *)true }, 2705 { }, 2706 }; 2707 2708 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2709 2710 { 2711 struct mv88e6xxx_mdio_bus *mdio_bus; 2712 struct mii_bus *bus; 2713 2714 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2715 bus = mdio_bus->bus; 2716 2717 if (!mdio_bus->external) 2718 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2719 2720 mdiobus_unregister(bus); 2721 } 2722 } 2723 2724 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2725 struct device_node *np) 2726 { 2727 const struct of_device_id *match; 2728 struct device_node *child; 2729 int err; 2730 2731 /* Always register one mdio bus for the internal/default mdio 2732 * bus. This maybe represented in the device tree, but is 2733 * optional. 2734 */ 2735 child = of_get_child_by_name(np, "mdio"); 2736 err = mv88e6xxx_mdio_register(chip, child, false); 2737 if (err) 2738 return err; 2739 2740 /* Walk the device tree, and see if there are any other nodes 2741 * which say they are compatible with the external mdio 2742 * bus. 2743 */ 2744 for_each_available_child_of_node(np, child) { 2745 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2746 if (match) { 2747 err = mv88e6xxx_mdio_register(chip, child, true); 2748 if (err) { 2749 mv88e6xxx_mdios_unregister(chip); 2750 return err; 2751 } 2752 } 2753 } 2754 2755 return 0; 2756 } 2757 2758 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2759 { 2760 struct mv88e6xxx_chip *chip = ds->priv; 2761 2762 return chip->eeprom_len; 2763 } 2764 2765 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2766 struct ethtool_eeprom *eeprom, u8 *data) 2767 { 2768 struct mv88e6xxx_chip *chip = ds->priv; 2769 int err; 2770 2771 if (!chip->info->ops->get_eeprom) 2772 return -EOPNOTSUPP; 2773 2774 mv88e6xxx_reg_lock(chip); 2775 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2776 mv88e6xxx_reg_unlock(chip); 2777 2778 if (err) 2779 return err; 2780 2781 eeprom->magic = 0xc3ec4951; 2782 2783 return 0; 2784 } 2785 2786 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2787 struct ethtool_eeprom *eeprom, u8 *data) 2788 { 2789 struct mv88e6xxx_chip *chip = ds->priv; 2790 int err; 2791 2792 if (!chip->info->ops->set_eeprom) 2793 return -EOPNOTSUPP; 2794 2795 if (eeprom->magic != 0xc3ec4951) 2796 return -EINVAL; 2797 2798 mv88e6xxx_reg_lock(chip); 2799 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2800 mv88e6xxx_reg_unlock(chip); 2801 2802 return err; 2803 } 2804 2805 static const struct mv88e6xxx_ops mv88e6085_ops = { 2806 /* MV88E6XXX_FAMILY_6097 */ 2807 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2808 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2809 .irl_init_all = mv88e6352_g2_irl_init_all, 2810 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2811 .phy_read = mv88e6185_phy_ppu_read, 2812 .phy_write = mv88e6185_phy_ppu_write, 2813 .port_set_link = mv88e6xxx_port_set_link, 2814 .port_set_duplex = mv88e6xxx_port_set_duplex, 2815 .port_set_speed = mv88e6185_port_set_speed, 2816 .port_tag_remap = mv88e6095_port_tag_remap, 2817 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2818 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2819 .port_set_ether_type = mv88e6351_port_set_ether_type, 2820 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2821 .port_pause_limit = mv88e6097_port_pause_limit, 2822 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2823 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2824 .port_link_state = mv88e6352_port_link_state, 2825 .port_get_cmode = mv88e6185_port_get_cmode, 2826 .port_setup_message_port = mv88e6xxx_setup_message_port, 2827 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2828 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2829 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2830 .stats_get_strings = mv88e6095_stats_get_strings, 2831 .stats_get_stats = mv88e6095_stats_get_stats, 2832 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2833 .set_egress_port = mv88e6095_g1_set_egress_port, 2834 .watchdog_ops = &mv88e6097_watchdog_ops, 2835 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2836 .pot_clear = mv88e6xxx_g2_pot_clear, 2837 .ppu_enable = mv88e6185_g1_ppu_enable, 2838 .ppu_disable = mv88e6185_g1_ppu_disable, 2839 .reset = mv88e6185_g1_reset, 2840 .rmu_disable = mv88e6085_g1_rmu_disable, 2841 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2842 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2843 .phylink_validate = mv88e6185_phylink_validate, 2844 }; 2845 2846 static const struct mv88e6xxx_ops mv88e6095_ops = { 2847 /* MV88E6XXX_FAMILY_6095 */ 2848 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2849 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2850 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2851 .phy_read = mv88e6185_phy_ppu_read, 2852 .phy_write = mv88e6185_phy_ppu_write, 2853 .port_set_link = mv88e6xxx_port_set_link, 2854 .port_set_duplex = mv88e6xxx_port_set_duplex, 2855 .port_set_speed = mv88e6185_port_set_speed, 2856 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2857 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2858 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2859 .port_link_state = mv88e6185_port_link_state, 2860 .port_get_cmode = mv88e6185_port_get_cmode, 2861 .port_setup_message_port = mv88e6xxx_setup_message_port, 2862 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2863 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2864 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2865 .stats_get_strings = mv88e6095_stats_get_strings, 2866 .stats_get_stats = mv88e6095_stats_get_stats, 2867 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2868 .ppu_enable = mv88e6185_g1_ppu_enable, 2869 .ppu_disable = mv88e6185_g1_ppu_disable, 2870 .reset = mv88e6185_g1_reset, 2871 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2872 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2873 .phylink_validate = mv88e6185_phylink_validate, 2874 }; 2875 2876 static const struct mv88e6xxx_ops mv88e6097_ops = { 2877 /* MV88E6XXX_FAMILY_6097 */ 2878 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2879 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2880 .irl_init_all = mv88e6352_g2_irl_init_all, 2881 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2882 .phy_read = mv88e6xxx_g2_smi_phy_read, 2883 .phy_write = mv88e6xxx_g2_smi_phy_write, 2884 .port_set_link = mv88e6xxx_port_set_link, 2885 .port_set_duplex = mv88e6xxx_port_set_duplex, 2886 .port_set_speed = mv88e6185_port_set_speed, 2887 .port_tag_remap = mv88e6095_port_tag_remap, 2888 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2889 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2890 .port_set_ether_type = mv88e6351_port_set_ether_type, 2891 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2892 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2893 .port_pause_limit = mv88e6097_port_pause_limit, 2894 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2895 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2896 .port_link_state = mv88e6352_port_link_state, 2897 .port_get_cmode = mv88e6185_port_get_cmode, 2898 .port_setup_message_port = mv88e6xxx_setup_message_port, 2899 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2900 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2901 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2902 .stats_get_strings = mv88e6095_stats_get_strings, 2903 .stats_get_stats = mv88e6095_stats_get_stats, 2904 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2905 .set_egress_port = mv88e6095_g1_set_egress_port, 2906 .watchdog_ops = &mv88e6097_watchdog_ops, 2907 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2908 .pot_clear = mv88e6xxx_g2_pot_clear, 2909 .reset = mv88e6352_g1_reset, 2910 .rmu_disable = mv88e6085_g1_rmu_disable, 2911 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2912 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2913 .phylink_validate = mv88e6185_phylink_validate, 2914 }; 2915 2916 static const struct mv88e6xxx_ops mv88e6123_ops = { 2917 /* MV88E6XXX_FAMILY_6165 */ 2918 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2919 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2920 .irl_init_all = mv88e6352_g2_irl_init_all, 2921 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2922 .phy_read = mv88e6xxx_g2_smi_phy_read, 2923 .phy_write = mv88e6xxx_g2_smi_phy_write, 2924 .port_set_link = mv88e6xxx_port_set_link, 2925 .port_set_duplex = mv88e6xxx_port_set_duplex, 2926 .port_set_speed = mv88e6185_port_set_speed, 2927 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2928 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2929 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2930 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2931 .port_link_state = mv88e6352_port_link_state, 2932 .port_get_cmode = mv88e6185_port_get_cmode, 2933 .port_setup_message_port = mv88e6xxx_setup_message_port, 2934 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2935 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2936 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2937 .stats_get_strings = mv88e6095_stats_get_strings, 2938 .stats_get_stats = mv88e6095_stats_get_stats, 2939 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2940 .set_egress_port = mv88e6095_g1_set_egress_port, 2941 .watchdog_ops = &mv88e6097_watchdog_ops, 2942 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2943 .pot_clear = mv88e6xxx_g2_pot_clear, 2944 .reset = mv88e6352_g1_reset, 2945 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2946 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2947 .phylink_validate = mv88e6185_phylink_validate, 2948 }; 2949 2950 static const struct mv88e6xxx_ops mv88e6131_ops = { 2951 /* MV88E6XXX_FAMILY_6185 */ 2952 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2953 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2954 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2955 .phy_read = mv88e6185_phy_ppu_read, 2956 .phy_write = mv88e6185_phy_ppu_write, 2957 .port_set_link = mv88e6xxx_port_set_link, 2958 .port_set_duplex = mv88e6xxx_port_set_duplex, 2959 .port_set_speed = mv88e6185_port_set_speed, 2960 .port_tag_remap = mv88e6095_port_tag_remap, 2961 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2962 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2963 .port_set_ether_type = mv88e6351_port_set_ether_type, 2964 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2965 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2966 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2967 .port_pause_limit = mv88e6097_port_pause_limit, 2968 .port_set_pause = mv88e6185_port_set_pause, 2969 .port_link_state = mv88e6352_port_link_state, 2970 .port_get_cmode = mv88e6185_port_get_cmode, 2971 .port_setup_message_port = mv88e6xxx_setup_message_port, 2972 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2973 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2974 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2975 .stats_get_strings = mv88e6095_stats_get_strings, 2976 .stats_get_stats = mv88e6095_stats_get_stats, 2977 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2978 .set_egress_port = mv88e6095_g1_set_egress_port, 2979 .watchdog_ops = &mv88e6097_watchdog_ops, 2980 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2981 .ppu_enable = mv88e6185_g1_ppu_enable, 2982 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2983 .ppu_disable = mv88e6185_g1_ppu_disable, 2984 .reset = mv88e6185_g1_reset, 2985 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2986 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2987 .phylink_validate = mv88e6185_phylink_validate, 2988 }; 2989 2990 static const struct mv88e6xxx_ops mv88e6141_ops = { 2991 /* MV88E6XXX_FAMILY_6341 */ 2992 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2993 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2994 .irl_init_all = mv88e6352_g2_irl_init_all, 2995 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2996 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2997 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2998 .phy_read = mv88e6xxx_g2_smi_phy_read, 2999 .phy_write = mv88e6xxx_g2_smi_phy_write, 3000 .port_set_link = mv88e6xxx_port_set_link, 3001 .port_set_duplex = mv88e6xxx_port_set_duplex, 3002 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3003 .port_set_speed = mv88e6341_port_set_speed, 3004 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3005 .port_tag_remap = mv88e6095_port_tag_remap, 3006 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3007 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3008 .port_set_ether_type = mv88e6351_port_set_ether_type, 3009 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3010 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3011 .port_pause_limit = mv88e6097_port_pause_limit, 3012 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3013 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3014 .port_link_state = mv88e6352_port_link_state, 3015 .port_get_cmode = mv88e6352_port_get_cmode, 3016 .port_setup_message_port = mv88e6xxx_setup_message_port, 3017 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3018 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3019 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3020 .stats_get_strings = mv88e6320_stats_get_strings, 3021 .stats_get_stats = mv88e6390_stats_get_stats, 3022 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3023 .set_egress_port = mv88e6390_g1_set_egress_port, 3024 .watchdog_ops = &mv88e6390_watchdog_ops, 3025 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3026 .pot_clear = mv88e6xxx_g2_pot_clear, 3027 .reset = mv88e6352_g1_reset, 3028 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3029 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3030 .serdes_power = mv88e6341_serdes_power, 3031 .gpio_ops = &mv88e6352_gpio_ops, 3032 .phylink_validate = mv88e6341_phylink_validate, 3033 }; 3034 3035 static const struct mv88e6xxx_ops mv88e6161_ops = { 3036 /* MV88E6XXX_FAMILY_6165 */ 3037 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3038 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3039 .irl_init_all = mv88e6352_g2_irl_init_all, 3040 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3041 .phy_read = mv88e6xxx_g2_smi_phy_read, 3042 .phy_write = mv88e6xxx_g2_smi_phy_write, 3043 .port_set_link = mv88e6xxx_port_set_link, 3044 .port_set_duplex = mv88e6xxx_port_set_duplex, 3045 .port_set_speed = mv88e6185_port_set_speed, 3046 .port_tag_remap = mv88e6095_port_tag_remap, 3047 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3048 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3049 .port_set_ether_type = mv88e6351_port_set_ether_type, 3050 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3051 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3052 .port_pause_limit = mv88e6097_port_pause_limit, 3053 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3054 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3055 .port_link_state = mv88e6352_port_link_state, 3056 .port_get_cmode = mv88e6185_port_get_cmode, 3057 .port_setup_message_port = mv88e6xxx_setup_message_port, 3058 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3059 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3060 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3061 .stats_get_strings = mv88e6095_stats_get_strings, 3062 .stats_get_stats = mv88e6095_stats_get_stats, 3063 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3064 .set_egress_port = mv88e6095_g1_set_egress_port, 3065 .watchdog_ops = &mv88e6097_watchdog_ops, 3066 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3067 .pot_clear = mv88e6xxx_g2_pot_clear, 3068 .reset = mv88e6352_g1_reset, 3069 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3070 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3071 .avb_ops = &mv88e6165_avb_ops, 3072 .ptp_ops = &mv88e6165_ptp_ops, 3073 .phylink_validate = mv88e6185_phylink_validate, 3074 }; 3075 3076 static const struct mv88e6xxx_ops mv88e6165_ops = { 3077 /* MV88E6XXX_FAMILY_6165 */ 3078 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3079 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3080 .irl_init_all = mv88e6352_g2_irl_init_all, 3081 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3082 .phy_read = mv88e6165_phy_read, 3083 .phy_write = mv88e6165_phy_write, 3084 .port_set_link = mv88e6xxx_port_set_link, 3085 .port_set_duplex = mv88e6xxx_port_set_duplex, 3086 .port_set_speed = mv88e6185_port_set_speed, 3087 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3088 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3089 .port_link_state = mv88e6352_port_link_state, 3090 .port_get_cmode = mv88e6185_port_get_cmode, 3091 .port_setup_message_port = mv88e6xxx_setup_message_port, 3092 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3093 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3094 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3095 .stats_get_strings = mv88e6095_stats_get_strings, 3096 .stats_get_stats = mv88e6095_stats_get_stats, 3097 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3098 .set_egress_port = mv88e6095_g1_set_egress_port, 3099 .watchdog_ops = &mv88e6097_watchdog_ops, 3100 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3101 .pot_clear = mv88e6xxx_g2_pot_clear, 3102 .reset = mv88e6352_g1_reset, 3103 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3104 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3105 .avb_ops = &mv88e6165_avb_ops, 3106 .ptp_ops = &mv88e6165_ptp_ops, 3107 .phylink_validate = mv88e6185_phylink_validate, 3108 }; 3109 3110 static const struct mv88e6xxx_ops mv88e6171_ops = { 3111 /* MV88E6XXX_FAMILY_6351 */ 3112 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3113 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3114 .irl_init_all = mv88e6352_g2_irl_init_all, 3115 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3116 .phy_read = mv88e6xxx_g2_smi_phy_read, 3117 .phy_write = mv88e6xxx_g2_smi_phy_write, 3118 .port_set_link = mv88e6xxx_port_set_link, 3119 .port_set_duplex = mv88e6xxx_port_set_duplex, 3120 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3121 .port_set_speed = mv88e6185_port_set_speed, 3122 .port_tag_remap = mv88e6095_port_tag_remap, 3123 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3124 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3125 .port_set_ether_type = mv88e6351_port_set_ether_type, 3126 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3127 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3128 .port_pause_limit = mv88e6097_port_pause_limit, 3129 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3130 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3131 .port_link_state = mv88e6352_port_link_state, 3132 .port_get_cmode = mv88e6352_port_get_cmode, 3133 .port_setup_message_port = mv88e6xxx_setup_message_port, 3134 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3135 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3136 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3137 .stats_get_strings = mv88e6095_stats_get_strings, 3138 .stats_get_stats = mv88e6095_stats_get_stats, 3139 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3140 .set_egress_port = mv88e6095_g1_set_egress_port, 3141 .watchdog_ops = &mv88e6097_watchdog_ops, 3142 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3143 .pot_clear = mv88e6xxx_g2_pot_clear, 3144 .reset = mv88e6352_g1_reset, 3145 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3146 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3147 .phylink_validate = mv88e6185_phylink_validate, 3148 }; 3149 3150 static const struct mv88e6xxx_ops mv88e6172_ops = { 3151 /* MV88E6XXX_FAMILY_6352 */ 3152 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3153 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3154 .irl_init_all = mv88e6352_g2_irl_init_all, 3155 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3156 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3157 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3158 .phy_read = mv88e6xxx_g2_smi_phy_read, 3159 .phy_write = mv88e6xxx_g2_smi_phy_write, 3160 .port_set_link = mv88e6xxx_port_set_link, 3161 .port_set_duplex = mv88e6xxx_port_set_duplex, 3162 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3163 .port_set_speed = mv88e6352_port_set_speed, 3164 .port_tag_remap = mv88e6095_port_tag_remap, 3165 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3166 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3167 .port_set_ether_type = mv88e6351_port_set_ether_type, 3168 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3169 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3170 .port_pause_limit = mv88e6097_port_pause_limit, 3171 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3172 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3173 .port_link_state = mv88e6352_port_link_state, 3174 .port_get_cmode = mv88e6352_port_get_cmode, 3175 .port_setup_message_port = mv88e6xxx_setup_message_port, 3176 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3177 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3178 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3179 .stats_get_strings = mv88e6095_stats_get_strings, 3180 .stats_get_stats = mv88e6095_stats_get_stats, 3181 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3182 .set_egress_port = mv88e6095_g1_set_egress_port, 3183 .watchdog_ops = &mv88e6097_watchdog_ops, 3184 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3185 .pot_clear = mv88e6xxx_g2_pot_clear, 3186 .reset = mv88e6352_g1_reset, 3187 .rmu_disable = mv88e6352_g1_rmu_disable, 3188 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3189 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3190 .serdes_power = mv88e6352_serdes_power, 3191 .gpio_ops = &mv88e6352_gpio_ops, 3192 .phylink_validate = mv88e6352_phylink_validate, 3193 }; 3194 3195 static const struct mv88e6xxx_ops mv88e6175_ops = { 3196 /* MV88E6XXX_FAMILY_6351 */ 3197 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3198 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3199 .irl_init_all = mv88e6352_g2_irl_init_all, 3200 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3201 .phy_read = mv88e6xxx_g2_smi_phy_read, 3202 .phy_write = mv88e6xxx_g2_smi_phy_write, 3203 .port_set_link = mv88e6xxx_port_set_link, 3204 .port_set_duplex = mv88e6xxx_port_set_duplex, 3205 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3206 .port_set_speed = mv88e6185_port_set_speed, 3207 .port_tag_remap = mv88e6095_port_tag_remap, 3208 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3209 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3210 .port_set_ether_type = mv88e6351_port_set_ether_type, 3211 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3212 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3213 .port_pause_limit = mv88e6097_port_pause_limit, 3214 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3215 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3216 .port_link_state = mv88e6352_port_link_state, 3217 .port_get_cmode = mv88e6352_port_get_cmode, 3218 .port_setup_message_port = mv88e6xxx_setup_message_port, 3219 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3220 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3221 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3222 .stats_get_strings = mv88e6095_stats_get_strings, 3223 .stats_get_stats = mv88e6095_stats_get_stats, 3224 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3225 .set_egress_port = mv88e6095_g1_set_egress_port, 3226 .watchdog_ops = &mv88e6097_watchdog_ops, 3227 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3228 .pot_clear = mv88e6xxx_g2_pot_clear, 3229 .reset = mv88e6352_g1_reset, 3230 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3231 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3232 .phylink_validate = mv88e6185_phylink_validate, 3233 }; 3234 3235 static const struct mv88e6xxx_ops mv88e6176_ops = { 3236 /* MV88E6XXX_FAMILY_6352 */ 3237 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3238 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3239 .irl_init_all = mv88e6352_g2_irl_init_all, 3240 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3241 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3243 .phy_read = mv88e6xxx_g2_smi_phy_read, 3244 .phy_write = mv88e6xxx_g2_smi_phy_write, 3245 .port_set_link = mv88e6xxx_port_set_link, 3246 .port_set_duplex = mv88e6xxx_port_set_duplex, 3247 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3248 .port_set_speed = mv88e6352_port_set_speed, 3249 .port_tag_remap = mv88e6095_port_tag_remap, 3250 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3251 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3252 .port_set_ether_type = mv88e6351_port_set_ether_type, 3253 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3254 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3255 .port_pause_limit = mv88e6097_port_pause_limit, 3256 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3257 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3258 .port_link_state = mv88e6352_port_link_state, 3259 .port_get_cmode = mv88e6352_port_get_cmode, 3260 .port_setup_message_port = mv88e6xxx_setup_message_port, 3261 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3262 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3263 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3264 .stats_get_strings = mv88e6095_stats_get_strings, 3265 .stats_get_stats = mv88e6095_stats_get_stats, 3266 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3267 .set_egress_port = mv88e6095_g1_set_egress_port, 3268 .watchdog_ops = &mv88e6097_watchdog_ops, 3269 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3270 .pot_clear = mv88e6xxx_g2_pot_clear, 3271 .reset = mv88e6352_g1_reset, 3272 .rmu_disable = mv88e6352_g1_rmu_disable, 3273 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3274 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3275 .serdes_power = mv88e6352_serdes_power, 3276 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3277 .serdes_irq_free = mv88e6352_serdes_irq_free, 3278 .gpio_ops = &mv88e6352_gpio_ops, 3279 .phylink_validate = mv88e6352_phylink_validate, 3280 }; 3281 3282 static const struct mv88e6xxx_ops mv88e6185_ops = { 3283 /* MV88E6XXX_FAMILY_6185 */ 3284 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3285 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3286 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3287 .phy_read = mv88e6185_phy_ppu_read, 3288 .phy_write = mv88e6185_phy_ppu_write, 3289 .port_set_link = mv88e6xxx_port_set_link, 3290 .port_set_duplex = mv88e6xxx_port_set_duplex, 3291 .port_set_speed = mv88e6185_port_set_speed, 3292 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3293 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3294 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3295 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3296 .port_set_pause = mv88e6185_port_set_pause, 3297 .port_link_state = mv88e6185_port_link_state, 3298 .port_get_cmode = mv88e6185_port_get_cmode, 3299 .port_setup_message_port = mv88e6xxx_setup_message_port, 3300 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3301 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3302 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3303 .stats_get_strings = mv88e6095_stats_get_strings, 3304 .stats_get_stats = mv88e6095_stats_get_stats, 3305 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3306 .set_egress_port = mv88e6095_g1_set_egress_port, 3307 .watchdog_ops = &mv88e6097_watchdog_ops, 3308 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3309 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3310 .ppu_enable = mv88e6185_g1_ppu_enable, 3311 .ppu_disable = mv88e6185_g1_ppu_disable, 3312 .reset = mv88e6185_g1_reset, 3313 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3314 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3315 .phylink_validate = mv88e6185_phylink_validate, 3316 }; 3317 3318 static const struct mv88e6xxx_ops mv88e6190_ops = { 3319 /* MV88E6XXX_FAMILY_6390 */ 3320 .setup_errata = mv88e6390_setup_errata, 3321 .irl_init_all = mv88e6390_g2_irl_init_all, 3322 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3323 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3324 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3325 .phy_read = mv88e6xxx_g2_smi_phy_read, 3326 .phy_write = mv88e6xxx_g2_smi_phy_write, 3327 .port_set_link = mv88e6xxx_port_set_link, 3328 .port_set_duplex = mv88e6xxx_port_set_duplex, 3329 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3330 .port_set_speed = mv88e6390_port_set_speed, 3331 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3332 .port_tag_remap = mv88e6390_port_tag_remap, 3333 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3334 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3335 .port_set_ether_type = mv88e6351_port_set_ether_type, 3336 .port_pause_limit = mv88e6390_port_pause_limit, 3337 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3338 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3339 .port_link_state = mv88e6352_port_link_state, 3340 .port_get_cmode = mv88e6352_port_get_cmode, 3341 .port_set_cmode = mv88e6390_port_set_cmode, 3342 .port_setup_message_port = mv88e6xxx_setup_message_port, 3343 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3344 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3345 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3346 .stats_get_strings = mv88e6320_stats_get_strings, 3347 .stats_get_stats = mv88e6390_stats_get_stats, 3348 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3349 .set_egress_port = mv88e6390_g1_set_egress_port, 3350 .watchdog_ops = &mv88e6390_watchdog_ops, 3351 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3352 .pot_clear = mv88e6xxx_g2_pot_clear, 3353 .reset = mv88e6352_g1_reset, 3354 .rmu_disable = mv88e6390_g1_rmu_disable, 3355 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3356 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3357 .serdes_power = mv88e6390_serdes_power, 3358 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3359 .serdes_irq_free = mv88e6390_serdes_irq_free, 3360 .gpio_ops = &mv88e6352_gpio_ops, 3361 .phylink_validate = mv88e6390_phylink_validate, 3362 }; 3363 3364 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3365 /* MV88E6XXX_FAMILY_6390 */ 3366 .setup_errata = mv88e6390_setup_errata, 3367 .irl_init_all = mv88e6390_g2_irl_init_all, 3368 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3369 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3370 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3371 .phy_read = mv88e6xxx_g2_smi_phy_read, 3372 .phy_write = mv88e6xxx_g2_smi_phy_write, 3373 .port_set_link = mv88e6xxx_port_set_link, 3374 .port_set_duplex = mv88e6xxx_port_set_duplex, 3375 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3376 .port_set_speed = mv88e6390x_port_set_speed, 3377 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3378 .port_tag_remap = mv88e6390_port_tag_remap, 3379 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3380 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3381 .port_set_ether_type = mv88e6351_port_set_ether_type, 3382 .port_pause_limit = mv88e6390_port_pause_limit, 3383 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3384 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3385 .port_link_state = mv88e6352_port_link_state, 3386 .port_get_cmode = mv88e6352_port_get_cmode, 3387 .port_set_cmode = mv88e6390x_port_set_cmode, 3388 .port_setup_message_port = mv88e6xxx_setup_message_port, 3389 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3390 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3391 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3392 .stats_get_strings = mv88e6320_stats_get_strings, 3393 .stats_get_stats = mv88e6390_stats_get_stats, 3394 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3395 .set_egress_port = mv88e6390_g1_set_egress_port, 3396 .watchdog_ops = &mv88e6390_watchdog_ops, 3397 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3398 .pot_clear = mv88e6xxx_g2_pot_clear, 3399 .reset = mv88e6352_g1_reset, 3400 .rmu_disable = mv88e6390_g1_rmu_disable, 3401 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3402 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3403 .serdes_power = mv88e6390x_serdes_power, 3404 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3405 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3406 .gpio_ops = &mv88e6352_gpio_ops, 3407 .phylink_validate = mv88e6390x_phylink_validate, 3408 }; 3409 3410 static const struct mv88e6xxx_ops mv88e6191_ops = { 3411 /* MV88E6XXX_FAMILY_6390 */ 3412 .setup_errata = mv88e6390_setup_errata, 3413 .irl_init_all = mv88e6390_g2_irl_init_all, 3414 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3415 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3416 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3417 .phy_read = mv88e6xxx_g2_smi_phy_read, 3418 .phy_write = mv88e6xxx_g2_smi_phy_write, 3419 .port_set_link = mv88e6xxx_port_set_link, 3420 .port_set_duplex = mv88e6xxx_port_set_duplex, 3421 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3422 .port_set_speed = mv88e6390_port_set_speed, 3423 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3424 .port_tag_remap = mv88e6390_port_tag_remap, 3425 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3426 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3427 .port_set_ether_type = mv88e6351_port_set_ether_type, 3428 .port_pause_limit = mv88e6390_port_pause_limit, 3429 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3430 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3431 .port_link_state = mv88e6352_port_link_state, 3432 .port_get_cmode = mv88e6352_port_get_cmode, 3433 .port_set_cmode = mv88e6390_port_set_cmode, 3434 .port_setup_message_port = mv88e6xxx_setup_message_port, 3435 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3436 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3437 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3438 .stats_get_strings = mv88e6320_stats_get_strings, 3439 .stats_get_stats = mv88e6390_stats_get_stats, 3440 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3441 .set_egress_port = mv88e6390_g1_set_egress_port, 3442 .watchdog_ops = &mv88e6390_watchdog_ops, 3443 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3444 .pot_clear = mv88e6xxx_g2_pot_clear, 3445 .reset = mv88e6352_g1_reset, 3446 .rmu_disable = mv88e6390_g1_rmu_disable, 3447 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3448 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3449 .serdes_power = mv88e6390_serdes_power, 3450 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3451 .serdes_irq_free = mv88e6390_serdes_irq_free, 3452 .avb_ops = &mv88e6390_avb_ops, 3453 .ptp_ops = &mv88e6352_ptp_ops, 3454 .phylink_validate = mv88e6390_phylink_validate, 3455 }; 3456 3457 static const struct mv88e6xxx_ops mv88e6240_ops = { 3458 /* MV88E6XXX_FAMILY_6352 */ 3459 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3460 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3461 .irl_init_all = mv88e6352_g2_irl_init_all, 3462 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3463 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3464 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3465 .phy_read = mv88e6xxx_g2_smi_phy_read, 3466 .phy_write = mv88e6xxx_g2_smi_phy_write, 3467 .port_set_link = mv88e6xxx_port_set_link, 3468 .port_set_duplex = mv88e6xxx_port_set_duplex, 3469 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3470 .port_set_speed = mv88e6352_port_set_speed, 3471 .port_tag_remap = mv88e6095_port_tag_remap, 3472 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3473 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3474 .port_set_ether_type = mv88e6351_port_set_ether_type, 3475 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3476 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3477 .port_pause_limit = mv88e6097_port_pause_limit, 3478 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3479 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3480 .port_link_state = mv88e6352_port_link_state, 3481 .port_get_cmode = mv88e6352_port_get_cmode, 3482 .port_setup_message_port = mv88e6xxx_setup_message_port, 3483 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3484 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3485 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3486 .stats_get_strings = mv88e6095_stats_get_strings, 3487 .stats_get_stats = mv88e6095_stats_get_stats, 3488 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3489 .set_egress_port = mv88e6095_g1_set_egress_port, 3490 .watchdog_ops = &mv88e6097_watchdog_ops, 3491 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3492 .pot_clear = mv88e6xxx_g2_pot_clear, 3493 .reset = mv88e6352_g1_reset, 3494 .rmu_disable = mv88e6352_g1_rmu_disable, 3495 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3496 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3497 .serdes_power = mv88e6352_serdes_power, 3498 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3499 .serdes_irq_free = mv88e6352_serdes_irq_free, 3500 .gpio_ops = &mv88e6352_gpio_ops, 3501 .avb_ops = &mv88e6352_avb_ops, 3502 .ptp_ops = &mv88e6352_ptp_ops, 3503 .phylink_validate = mv88e6352_phylink_validate, 3504 }; 3505 3506 static const struct mv88e6xxx_ops mv88e6250_ops = { 3507 /* MV88E6XXX_FAMILY_6250 */ 3508 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 3509 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3510 .irl_init_all = mv88e6352_g2_irl_init_all, 3511 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3512 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3513 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3514 .phy_read = mv88e6xxx_g2_smi_phy_read, 3515 .phy_write = mv88e6xxx_g2_smi_phy_write, 3516 .port_set_link = mv88e6xxx_port_set_link, 3517 .port_set_duplex = mv88e6xxx_port_set_duplex, 3518 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3519 .port_set_speed = mv88e6250_port_set_speed, 3520 .port_tag_remap = mv88e6095_port_tag_remap, 3521 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3522 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3523 .port_set_ether_type = mv88e6351_port_set_ether_type, 3524 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3525 .port_pause_limit = mv88e6097_port_pause_limit, 3526 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3527 .port_link_state = mv88e6250_port_link_state, 3528 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3529 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3530 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 3531 .stats_get_strings = mv88e6250_stats_get_strings, 3532 .stats_get_stats = mv88e6250_stats_get_stats, 3533 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3534 .set_egress_port = mv88e6095_g1_set_egress_port, 3535 .watchdog_ops = &mv88e6250_watchdog_ops, 3536 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3537 .pot_clear = mv88e6xxx_g2_pot_clear, 3538 .reset = mv88e6250_g1_reset, 3539 .vtu_getnext = mv88e6250_g1_vtu_getnext, 3540 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 3541 .avb_ops = &mv88e6352_avb_ops, 3542 .ptp_ops = &mv88e6250_ptp_ops, 3543 .phylink_validate = mv88e6065_phylink_validate, 3544 }; 3545 3546 static const struct mv88e6xxx_ops mv88e6290_ops = { 3547 /* MV88E6XXX_FAMILY_6390 */ 3548 .setup_errata = mv88e6390_setup_errata, 3549 .irl_init_all = mv88e6390_g2_irl_init_all, 3550 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3551 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3552 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3553 .phy_read = mv88e6xxx_g2_smi_phy_read, 3554 .phy_write = mv88e6xxx_g2_smi_phy_write, 3555 .port_set_link = mv88e6xxx_port_set_link, 3556 .port_set_duplex = mv88e6xxx_port_set_duplex, 3557 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3558 .port_set_speed = mv88e6390_port_set_speed, 3559 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3560 .port_tag_remap = mv88e6390_port_tag_remap, 3561 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3562 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3563 .port_set_ether_type = mv88e6351_port_set_ether_type, 3564 .port_pause_limit = mv88e6390_port_pause_limit, 3565 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3566 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3567 .port_link_state = mv88e6352_port_link_state, 3568 .port_get_cmode = mv88e6352_port_get_cmode, 3569 .port_set_cmode = mv88e6390_port_set_cmode, 3570 .port_setup_message_port = mv88e6xxx_setup_message_port, 3571 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3572 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3573 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3574 .stats_get_strings = mv88e6320_stats_get_strings, 3575 .stats_get_stats = mv88e6390_stats_get_stats, 3576 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3577 .set_egress_port = mv88e6390_g1_set_egress_port, 3578 .watchdog_ops = &mv88e6390_watchdog_ops, 3579 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3580 .pot_clear = mv88e6xxx_g2_pot_clear, 3581 .reset = mv88e6352_g1_reset, 3582 .rmu_disable = mv88e6390_g1_rmu_disable, 3583 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3584 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3585 .serdes_power = mv88e6390_serdes_power, 3586 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3587 .serdes_irq_free = mv88e6390_serdes_irq_free, 3588 .gpio_ops = &mv88e6352_gpio_ops, 3589 .avb_ops = &mv88e6390_avb_ops, 3590 .ptp_ops = &mv88e6352_ptp_ops, 3591 .phylink_validate = mv88e6390_phylink_validate, 3592 }; 3593 3594 static const struct mv88e6xxx_ops mv88e6320_ops = { 3595 /* MV88E6XXX_FAMILY_6320 */ 3596 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3597 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3598 .irl_init_all = mv88e6352_g2_irl_init_all, 3599 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3600 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3601 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3602 .phy_read = mv88e6xxx_g2_smi_phy_read, 3603 .phy_write = mv88e6xxx_g2_smi_phy_write, 3604 .port_set_link = mv88e6xxx_port_set_link, 3605 .port_set_duplex = mv88e6xxx_port_set_duplex, 3606 .port_set_speed = mv88e6185_port_set_speed, 3607 .port_tag_remap = mv88e6095_port_tag_remap, 3608 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3609 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3610 .port_set_ether_type = mv88e6351_port_set_ether_type, 3611 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3612 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3613 .port_pause_limit = mv88e6097_port_pause_limit, 3614 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3615 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3616 .port_link_state = mv88e6352_port_link_state, 3617 .port_get_cmode = mv88e6352_port_get_cmode, 3618 .port_setup_message_port = mv88e6xxx_setup_message_port, 3619 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3620 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3621 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3622 .stats_get_strings = mv88e6320_stats_get_strings, 3623 .stats_get_stats = mv88e6320_stats_get_stats, 3624 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3625 .set_egress_port = mv88e6095_g1_set_egress_port, 3626 .watchdog_ops = &mv88e6390_watchdog_ops, 3627 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3628 .pot_clear = mv88e6xxx_g2_pot_clear, 3629 .reset = mv88e6352_g1_reset, 3630 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3631 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3632 .gpio_ops = &mv88e6352_gpio_ops, 3633 .avb_ops = &mv88e6352_avb_ops, 3634 .ptp_ops = &mv88e6352_ptp_ops, 3635 .phylink_validate = mv88e6185_phylink_validate, 3636 }; 3637 3638 static const struct mv88e6xxx_ops mv88e6321_ops = { 3639 /* MV88E6XXX_FAMILY_6320 */ 3640 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3641 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3642 .irl_init_all = mv88e6352_g2_irl_init_all, 3643 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3644 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3645 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3646 .phy_read = mv88e6xxx_g2_smi_phy_read, 3647 .phy_write = mv88e6xxx_g2_smi_phy_write, 3648 .port_set_link = mv88e6xxx_port_set_link, 3649 .port_set_duplex = mv88e6xxx_port_set_duplex, 3650 .port_set_speed = mv88e6185_port_set_speed, 3651 .port_tag_remap = mv88e6095_port_tag_remap, 3652 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3653 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3654 .port_set_ether_type = mv88e6351_port_set_ether_type, 3655 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3656 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3657 .port_pause_limit = mv88e6097_port_pause_limit, 3658 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3659 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3660 .port_link_state = mv88e6352_port_link_state, 3661 .port_get_cmode = mv88e6352_port_get_cmode, 3662 .port_setup_message_port = mv88e6xxx_setup_message_port, 3663 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3664 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3665 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3666 .stats_get_strings = mv88e6320_stats_get_strings, 3667 .stats_get_stats = mv88e6320_stats_get_stats, 3668 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3669 .set_egress_port = mv88e6095_g1_set_egress_port, 3670 .watchdog_ops = &mv88e6390_watchdog_ops, 3671 .reset = mv88e6352_g1_reset, 3672 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3673 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3674 .gpio_ops = &mv88e6352_gpio_ops, 3675 .avb_ops = &mv88e6352_avb_ops, 3676 .ptp_ops = &mv88e6352_ptp_ops, 3677 .phylink_validate = mv88e6185_phylink_validate, 3678 }; 3679 3680 static const struct mv88e6xxx_ops mv88e6341_ops = { 3681 /* MV88E6XXX_FAMILY_6341 */ 3682 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3683 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3684 .irl_init_all = mv88e6352_g2_irl_init_all, 3685 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3686 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3687 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3688 .phy_read = mv88e6xxx_g2_smi_phy_read, 3689 .phy_write = mv88e6xxx_g2_smi_phy_write, 3690 .port_set_link = mv88e6xxx_port_set_link, 3691 .port_set_duplex = mv88e6xxx_port_set_duplex, 3692 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3693 .port_set_speed = mv88e6341_port_set_speed, 3694 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3695 .port_tag_remap = mv88e6095_port_tag_remap, 3696 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3697 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3698 .port_set_ether_type = mv88e6351_port_set_ether_type, 3699 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3700 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3701 .port_pause_limit = mv88e6097_port_pause_limit, 3702 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3703 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3704 .port_link_state = mv88e6352_port_link_state, 3705 .port_get_cmode = mv88e6352_port_get_cmode, 3706 .port_setup_message_port = mv88e6xxx_setup_message_port, 3707 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3708 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3709 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3710 .stats_get_strings = mv88e6320_stats_get_strings, 3711 .stats_get_stats = mv88e6390_stats_get_stats, 3712 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3713 .set_egress_port = mv88e6390_g1_set_egress_port, 3714 .watchdog_ops = &mv88e6390_watchdog_ops, 3715 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3716 .pot_clear = mv88e6xxx_g2_pot_clear, 3717 .reset = mv88e6352_g1_reset, 3718 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3719 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3720 .serdes_power = mv88e6341_serdes_power, 3721 .gpio_ops = &mv88e6352_gpio_ops, 3722 .avb_ops = &mv88e6390_avb_ops, 3723 .ptp_ops = &mv88e6352_ptp_ops, 3724 .phylink_validate = mv88e6341_phylink_validate, 3725 }; 3726 3727 static const struct mv88e6xxx_ops mv88e6350_ops = { 3728 /* MV88E6XXX_FAMILY_6351 */ 3729 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3730 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3731 .irl_init_all = mv88e6352_g2_irl_init_all, 3732 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3733 .phy_read = mv88e6xxx_g2_smi_phy_read, 3734 .phy_write = mv88e6xxx_g2_smi_phy_write, 3735 .port_set_link = mv88e6xxx_port_set_link, 3736 .port_set_duplex = mv88e6xxx_port_set_duplex, 3737 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3738 .port_set_speed = mv88e6185_port_set_speed, 3739 .port_tag_remap = mv88e6095_port_tag_remap, 3740 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3741 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3742 .port_set_ether_type = mv88e6351_port_set_ether_type, 3743 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3744 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3745 .port_pause_limit = mv88e6097_port_pause_limit, 3746 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3747 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3748 .port_link_state = mv88e6352_port_link_state, 3749 .port_get_cmode = mv88e6352_port_get_cmode, 3750 .port_setup_message_port = mv88e6xxx_setup_message_port, 3751 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3752 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3753 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3754 .stats_get_strings = mv88e6095_stats_get_strings, 3755 .stats_get_stats = mv88e6095_stats_get_stats, 3756 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3757 .set_egress_port = mv88e6095_g1_set_egress_port, 3758 .watchdog_ops = &mv88e6097_watchdog_ops, 3759 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3760 .pot_clear = mv88e6xxx_g2_pot_clear, 3761 .reset = mv88e6352_g1_reset, 3762 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3763 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3764 .phylink_validate = mv88e6185_phylink_validate, 3765 }; 3766 3767 static const struct mv88e6xxx_ops mv88e6351_ops = { 3768 /* MV88E6XXX_FAMILY_6351 */ 3769 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3770 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3771 .irl_init_all = mv88e6352_g2_irl_init_all, 3772 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3773 .phy_read = mv88e6xxx_g2_smi_phy_read, 3774 .phy_write = mv88e6xxx_g2_smi_phy_write, 3775 .port_set_link = mv88e6xxx_port_set_link, 3776 .port_set_duplex = mv88e6xxx_port_set_duplex, 3777 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3778 .port_set_speed = mv88e6185_port_set_speed, 3779 .port_tag_remap = mv88e6095_port_tag_remap, 3780 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3781 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3782 .port_set_ether_type = mv88e6351_port_set_ether_type, 3783 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3784 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3785 .port_pause_limit = mv88e6097_port_pause_limit, 3786 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3787 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3788 .port_link_state = mv88e6352_port_link_state, 3789 .port_get_cmode = mv88e6352_port_get_cmode, 3790 .port_setup_message_port = mv88e6xxx_setup_message_port, 3791 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3792 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3793 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3794 .stats_get_strings = mv88e6095_stats_get_strings, 3795 .stats_get_stats = mv88e6095_stats_get_stats, 3796 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3797 .set_egress_port = mv88e6095_g1_set_egress_port, 3798 .watchdog_ops = &mv88e6097_watchdog_ops, 3799 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3800 .pot_clear = mv88e6xxx_g2_pot_clear, 3801 .reset = mv88e6352_g1_reset, 3802 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3803 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3804 .avb_ops = &mv88e6352_avb_ops, 3805 .ptp_ops = &mv88e6352_ptp_ops, 3806 .phylink_validate = mv88e6185_phylink_validate, 3807 }; 3808 3809 static const struct mv88e6xxx_ops mv88e6352_ops = { 3810 /* MV88E6XXX_FAMILY_6352 */ 3811 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3812 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3813 .irl_init_all = mv88e6352_g2_irl_init_all, 3814 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3815 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3816 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3817 .phy_read = mv88e6xxx_g2_smi_phy_read, 3818 .phy_write = mv88e6xxx_g2_smi_phy_write, 3819 .port_set_link = mv88e6xxx_port_set_link, 3820 .port_set_duplex = mv88e6xxx_port_set_duplex, 3821 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3822 .port_set_speed = mv88e6352_port_set_speed, 3823 .port_tag_remap = mv88e6095_port_tag_remap, 3824 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3825 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3826 .port_set_ether_type = mv88e6351_port_set_ether_type, 3827 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3828 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3829 .port_pause_limit = mv88e6097_port_pause_limit, 3830 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3831 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3832 .port_link_state = mv88e6352_port_link_state, 3833 .port_get_cmode = mv88e6352_port_get_cmode, 3834 .port_setup_message_port = mv88e6xxx_setup_message_port, 3835 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3836 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3837 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3838 .stats_get_strings = mv88e6095_stats_get_strings, 3839 .stats_get_stats = mv88e6095_stats_get_stats, 3840 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3841 .set_egress_port = mv88e6095_g1_set_egress_port, 3842 .watchdog_ops = &mv88e6097_watchdog_ops, 3843 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3844 .pot_clear = mv88e6xxx_g2_pot_clear, 3845 .reset = mv88e6352_g1_reset, 3846 .rmu_disable = mv88e6352_g1_rmu_disable, 3847 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3848 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3849 .serdes_power = mv88e6352_serdes_power, 3850 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3851 .serdes_irq_free = mv88e6352_serdes_irq_free, 3852 .gpio_ops = &mv88e6352_gpio_ops, 3853 .avb_ops = &mv88e6352_avb_ops, 3854 .ptp_ops = &mv88e6352_ptp_ops, 3855 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3856 .serdes_get_strings = mv88e6352_serdes_get_strings, 3857 .serdes_get_stats = mv88e6352_serdes_get_stats, 3858 .phylink_validate = mv88e6352_phylink_validate, 3859 }; 3860 3861 static const struct mv88e6xxx_ops mv88e6390_ops = { 3862 /* MV88E6XXX_FAMILY_6390 */ 3863 .setup_errata = mv88e6390_setup_errata, 3864 .irl_init_all = mv88e6390_g2_irl_init_all, 3865 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3866 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3867 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3868 .phy_read = mv88e6xxx_g2_smi_phy_read, 3869 .phy_write = mv88e6xxx_g2_smi_phy_write, 3870 .port_set_link = mv88e6xxx_port_set_link, 3871 .port_set_duplex = mv88e6xxx_port_set_duplex, 3872 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3873 .port_set_speed = mv88e6390_port_set_speed, 3874 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3875 .port_tag_remap = mv88e6390_port_tag_remap, 3876 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3877 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3878 .port_set_ether_type = mv88e6351_port_set_ether_type, 3879 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3880 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3881 .port_pause_limit = mv88e6390_port_pause_limit, 3882 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3883 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3884 .port_link_state = mv88e6352_port_link_state, 3885 .port_get_cmode = mv88e6352_port_get_cmode, 3886 .port_set_cmode = mv88e6390_port_set_cmode, 3887 .port_setup_message_port = mv88e6xxx_setup_message_port, 3888 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3889 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3890 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3891 .stats_get_strings = mv88e6320_stats_get_strings, 3892 .stats_get_stats = mv88e6390_stats_get_stats, 3893 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3894 .set_egress_port = mv88e6390_g1_set_egress_port, 3895 .watchdog_ops = &mv88e6390_watchdog_ops, 3896 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3897 .pot_clear = mv88e6xxx_g2_pot_clear, 3898 .reset = mv88e6352_g1_reset, 3899 .rmu_disable = mv88e6390_g1_rmu_disable, 3900 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3901 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3902 .serdes_power = mv88e6390_serdes_power, 3903 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3904 .serdes_irq_free = mv88e6390_serdes_irq_free, 3905 .gpio_ops = &mv88e6352_gpio_ops, 3906 .avb_ops = &mv88e6390_avb_ops, 3907 .ptp_ops = &mv88e6352_ptp_ops, 3908 .phylink_validate = mv88e6390_phylink_validate, 3909 }; 3910 3911 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3912 /* MV88E6XXX_FAMILY_6390 */ 3913 .setup_errata = mv88e6390_setup_errata, 3914 .irl_init_all = mv88e6390_g2_irl_init_all, 3915 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3916 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3917 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3918 .phy_read = mv88e6xxx_g2_smi_phy_read, 3919 .phy_write = mv88e6xxx_g2_smi_phy_write, 3920 .port_set_link = mv88e6xxx_port_set_link, 3921 .port_set_duplex = mv88e6xxx_port_set_duplex, 3922 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3923 .port_set_speed = mv88e6390x_port_set_speed, 3924 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3925 .port_tag_remap = mv88e6390_port_tag_remap, 3926 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3927 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3928 .port_set_ether_type = mv88e6351_port_set_ether_type, 3929 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3930 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3931 .port_pause_limit = mv88e6390_port_pause_limit, 3932 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3933 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3934 .port_link_state = mv88e6352_port_link_state, 3935 .port_get_cmode = mv88e6352_port_get_cmode, 3936 .port_set_cmode = mv88e6390x_port_set_cmode, 3937 .port_setup_message_port = mv88e6xxx_setup_message_port, 3938 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3939 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3940 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3941 .stats_get_strings = mv88e6320_stats_get_strings, 3942 .stats_get_stats = mv88e6390_stats_get_stats, 3943 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3944 .set_egress_port = mv88e6390_g1_set_egress_port, 3945 .watchdog_ops = &mv88e6390_watchdog_ops, 3946 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3947 .pot_clear = mv88e6xxx_g2_pot_clear, 3948 .reset = mv88e6352_g1_reset, 3949 .rmu_disable = mv88e6390_g1_rmu_disable, 3950 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3951 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3952 .serdes_power = mv88e6390x_serdes_power, 3953 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3954 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3955 .gpio_ops = &mv88e6352_gpio_ops, 3956 .avb_ops = &mv88e6390_avb_ops, 3957 .ptp_ops = &mv88e6352_ptp_ops, 3958 .phylink_validate = mv88e6390x_phylink_validate, 3959 }; 3960 3961 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3962 [MV88E6085] = { 3963 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3964 .family = MV88E6XXX_FAMILY_6097, 3965 .name = "Marvell 88E6085", 3966 .num_databases = 4096, 3967 .num_ports = 10, 3968 .num_internal_phys = 5, 3969 .max_vid = 4095, 3970 .port_base_addr = 0x10, 3971 .phy_base_addr = 0x0, 3972 .global1_addr = 0x1b, 3973 .global2_addr = 0x1c, 3974 .age_time_coeff = 15000, 3975 .g1_irqs = 8, 3976 .g2_irqs = 10, 3977 .atu_move_port_mask = 0xf, 3978 .pvt = true, 3979 .multi_chip = true, 3980 .tag_protocol = DSA_TAG_PROTO_DSA, 3981 .ops = &mv88e6085_ops, 3982 }, 3983 3984 [MV88E6095] = { 3985 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3986 .family = MV88E6XXX_FAMILY_6095, 3987 .name = "Marvell 88E6095/88E6095F", 3988 .num_databases = 256, 3989 .num_ports = 11, 3990 .num_internal_phys = 0, 3991 .max_vid = 4095, 3992 .port_base_addr = 0x10, 3993 .phy_base_addr = 0x0, 3994 .global1_addr = 0x1b, 3995 .global2_addr = 0x1c, 3996 .age_time_coeff = 15000, 3997 .g1_irqs = 8, 3998 .atu_move_port_mask = 0xf, 3999 .multi_chip = true, 4000 .tag_protocol = DSA_TAG_PROTO_DSA, 4001 .ops = &mv88e6095_ops, 4002 }, 4003 4004 [MV88E6097] = { 4005 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4006 .family = MV88E6XXX_FAMILY_6097, 4007 .name = "Marvell 88E6097/88E6097F", 4008 .num_databases = 4096, 4009 .num_ports = 11, 4010 .num_internal_phys = 8, 4011 .max_vid = 4095, 4012 .port_base_addr = 0x10, 4013 .phy_base_addr = 0x0, 4014 .global1_addr = 0x1b, 4015 .global2_addr = 0x1c, 4016 .age_time_coeff = 15000, 4017 .g1_irqs = 8, 4018 .g2_irqs = 10, 4019 .atu_move_port_mask = 0xf, 4020 .pvt = true, 4021 .multi_chip = true, 4022 .tag_protocol = DSA_TAG_PROTO_EDSA, 4023 .ops = &mv88e6097_ops, 4024 }, 4025 4026 [MV88E6123] = { 4027 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4028 .family = MV88E6XXX_FAMILY_6165, 4029 .name = "Marvell 88E6123", 4030 .num_databases = 4096, 4031 .num_ports = 3, 4032 .num_internal_phys = 5, 4033 .max_vid = 4095, 4034 .port_base_addr = 0x10, 4035 .phy_base_addr = 0x0, 4036 .global1_addr = 0x1b, 4037 .global2_addr = 0x1c, 4038 .age_time_coeff = 15000, 4039 .g1_irqs = 9, 4040 .g2_irqs = 10, 4041 .atu_move_port_mask = 0xf, 4042 .pvt = true, 4043 .multi_chip = true, 4044 .tag_protocol = DSA_TAG_PROTO_EDSA, 4045 .ops = &mv88e6123_ops, 4046 }, 4047 4048 [MV88E6131] = { 4049 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4050 .family = MV88E6XXX_FAMILY_6185, 4051 .name = "Marvell 88E6131", 4052 .num_databases = 256, 4053 .num_ports = 8, 4054 .num_internal_phys = 0, 4055 .max_vid = 4095, 4056 .port_base_addr = 0x10, 4057 .phy_base_addr = 0x0, 4058 .global1_addr = 0x1b, 4059 .global2_addr = 0x1c, 4060 .age_time_coeff = 15000, 4061 .g1_irqs = 9, 4062 .atu_move_port_mask = 0xf, 4063 .multi_chip = true, 4064 .tag_protocol = DSA_TAG_PROTO_DSA, 4065 .ops = &mv88e6131_ops, 4066 }, 4067 4068 [MV88E6141] = { 4069 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4070 .family = MV88E6XXX_FAMILY_6341, 4071 .name = "Marvell 88E6141", 4072 .num_databases = 4096, 4073 .num_ports = 6, 4074 .num_internal_phys = 5, 4075 .num_gpio = 11, 4076 .max_vid = 4095, 4077 .port_base_addr = 0x10, 4078 .phy_base_addr = 0x10, 4079 .global1_addr = 0x1b, 4080 .global2_addr = 0x1c, 4081 .age_time_coeff = 3750, 4082 .atu_move_port_mask = 0x1f, 4083 .g1_irqs = 9, 4084 .g2_irqs = 10, 4085 .pvt = true, 4086 .multi_chip = true, 4087 .tag_protocol = DSA_TAG_PROTO_EDSA, 4088 .ops = &mv88e6141_ops, 4089 }, 4090 4091 [MV88E6161] = { 4092 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4093 .family = MV88E6XXX_FAMILY_6165, 4094 .name = "Marvell 88E6161", 4095 .num_databases = 4096, 4096 .num_ports = 6, 4097 .num_internal_phys = 5, 4098 .max_vid = 4095, 4099 .port_base_addr = 0x10, 4100 .phy_base_addr = 0x0, 4101 .global1_addr = 0x1b, 4102 .global2_addr = 0x1c, 4103 .age_time_coeff = 15000, 4104 .g1_irqs = 9, 4105 .g2_irqs = 10, 4106 .atu_move_port_mask = 0xf, 4107 .pvt = true, 4108 .multi_chip = true, 4109 .tag_protocol = DSA_TAG_PROTO_EDSA, 4110 .ptp_support = true, 4111 .ops = &mv88e6161_ops, 4112 }, 4113 4114 [MV88E6165] = { 4115 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4116 .family = MV88E6XXX_FAMILY_6165, 4117 .name = "Marvell 88E6165", 4118 .num_databases = 4096, 4119 .num_ports = 6, 4120 .num_internal_phys = 0, 4121 .max_vid = 4095, 4122 .port_base_addr = 0x10, 4123 .phy_base_addr = 0x0, 4124 .global1_addr = 0x1b, 4125 .global2_addr = 0x1c, 4126 .age_time_coeff = 15000, 4127 .g1_irqs = 9, 4128 .g2_irqs = 10, 4129 .atu_move_port_mask = 0xf, 4130 .pvt = true, 4131 .multi_chip = true, 4132 .tag_protocol = DSA_TAG_PROTO_DSA, 4133 .ptp_support = true, 4134 .ops = &mv88e6165_ops, 4135 }, 4136 4137 [MV88E6171] = { 4138 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4139 .family = MV88E6XXX_FAMILY_6351, 4140 .name = "Marvell 88E6171", 4141 .num_databases = 4096, 4142 .num_ports = 7, 4143 .num_internal_phys = 5, 4144 .max_vid = 4095, 4145 .port_base_addr = 0x10, 4146 .phy_base_addr = 0x0, 4147 .global1_addr = 0x1b, 4148 .global2_addr = 0x1c, 4149 .age_time_coeff = 15000, 4150 .g1_irqs = 9, 4151 .g2_irqs = 10, 4152 .atu_move_port_mask = 0xf, 4153 .pvt = true, 4154 .multi_chip = true, 4155 .tag_protocol = DSA_TAG_PROTO_EDSA, 4156 .ops = &mv88e6171_ops, 4157 }, 4158 4159 [MV88E6172] = { 4160 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4161 .family = MV88E6XXX_FAMILY_6352, 4162 .name = "Marvell 88E6172", 4163 .num_databases = 4096, 4164 .num_ports = 7, 4165 .num_internal_phys = 5, 4166 .num_gpio = 15, 4167 .max_vid = 4095, 4168 .port_base_addr = 0x10, 4169 .phy_base_addr = 0x0, 4170 .global1_addr = 0x1b, 4171 .global2_addr = 0x1c, 4172 .age_time_coeff = 15000, 4173 .g1_irqs = 9, 4174 .g2_irqs = 10, 4175 .atu_move_port_mask = 0xf, 4176 .pvt = true, 4177 .multi_chip = true, 4178 .tag_protocol = DSA_TAG_PROTO_EDSA, 4179 .ops = &mv88e6172_ops, 4180 }, 4181 4182 [MV88E6175] = { 4183 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4184 .family = MV88E6XXX_FAMILY_6351, 4185 .name = "Marvell 88E6175", 4186 .num_databases = 4096, 4187 .num_ports = 7, 4188 .num_internal_phys = 5, 4189 .max_vid = 4095, 4190 .port_base_addr = 0x10, 4191 .phy_base_addr = 0x0, 4192 .global1_addr = 0x1b, 4193 .global2_addr = 0x1c, 4194 .age_time_coeff = 15000, 4195 .g1_irqs = 9, 4196 .g2_irqs = 10, 4197 .atu_move_port_mask = 0xf, 4198 .pvt = true, 4199 .multi_chip = true, 4200 .tag_protocol = DSA_TAG_PROTO_EDSA, 4201 .ops = &mv88e6175_ops, 4202 }, 4203 4204 [MV88E6176] = { 4205 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4206 .family = MV88E6XXX_FAMILY_6352, 4207 .name = "Marvell 88E6176", 4208 .num_databases = 4096, 4209 .num_ports = 7, 4210 .num_internal_phys = 5, 4211 .num_gpio = 15, 4212 .max_vid = 4095, 4213 .port_base_addr = 0x10, 4214 .phy_base_addr = 0x0, 4215 .global1_addr = 0x1b, 4216 .global2_addr = 0x1c, 4217 .age_time_coeff = 15000, 4218 .g1_irqs = 9, 4219 .g2_irqs = 10, 4220 .atu_move_port_mask = 0xf, 4221 .pvt = true, 4222 .multi_chip = true, 4223 .tag_protocol = DSA_TAG_PROTO_EDSA, 4224 .ops = &mv88e6176_ops, 4225 }, 4226 4227 [MV88E6185] = { 4228 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4229 .family = MV88E6XXX_FAMILY_6185, 4230 .name = "Marvell 88E6185", 4231 .num_databases = 256, 4232 .num_ports = 10, 4233 .num_internal_phys = 0, 4234 .max_vid = 4095, 4235 .port_base_addr = 0x10, 4236 .phy_base_addr = 0x0, 4237 .global1_addr = 0x1b, 4238 .global2_addr = 0x1c, 4239 .age_time_coeff = 15000, 4240 .g1_irqs = 8, 4241 .atu_move_port_mask = 0xf, 4242 .multi_chip = true, 4243 .tag_protocol = DSA_TAG_PROTO_EDSA, 4244 .ops = &mv88e6185_ops, 4245 }, 4246 4247 [MV88E6190] = { 4248 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4249 .family = MV88E6XXX_FAMILY_6390, 4250 .name = "Marvell 88E6190", 4251 .num_databases = 4096, 4252 .num_ports = 11, /* 10 + Z80 */ 4253 .num_internal_phys = 9, 4254 .num_gpio = 16, 4255 .max_vid = 8191, 4256 .port_base_addr = 0x0, 4257 .phy_base_addr = 0x0, 4258 .global1_addr = 0x1b, 4259 .global2_addr = 0x1c, 4260 .tag_protocol = DSA_TAG_PROTO_DSA, 4261 .age_time_coeff = 3750, 4262 .g1_irqs = 9, 4263 .g2_irqs = 14, 4264 .pvt = true, 4265 .multi_chip = true, 4266 .atu_move_port_mask = 0x1f, 4267 .ops = &mv88e6190_ops, 4268 }, 4269 4270 [MV88E6190X] = { 4271 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4272 .family = MV88E6XXX_FAMILY_6390, 4273 .name = "Marvell 88E6190X", 4274 .num_databases = 4096, 4275 .num_ports = 11, /* 10 + Z80 */ 4276 .num_internal_phys = 9, 4277 .num_gpio = 16, 4278 .max_vid = 8191, 4279 .port_base_addr = 0x0, 4280 .phy_base_addr = 0x0, 4281 .global1_addr = 0x1b, 4282 .global2_addr = 0x1c, 4283 .age_time_coeff = 3750, 4284 .g1_irqs = 9, 4285 .g2_irqs = 14, 4286 .atu_move_port_mask = 0x1f, 4287 .pvt = true, 4288 .multi_chip = true, 4289 .tag_protocol = DSA_TAG_PROTO_DSA, 4290 .ops = &mv88e6190x_ops, 4291 }, 4292 4293 [MV88E6191] = { 4294 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4295 .family = MV88E6XXX_FAMILY_6390, 4296 .name = "Marvell 88E6191", 4297 .num_databases = 4096, 4298 .num_ports = 11, /* 10 + Z80 */ 4299 .num_internal_phys = 9, 4300 .max_vid = 8191, 4301 .port_base_addr = 0x0, 4302 .phy_base_addr = 0x0, 4303 .global1_addr = 0x1b, 4304 .global2_addr = 0x1c, 4305 .age_time_coeff = 3750, 4306 .g1_irqs = 9, 4307 .g2_irqs = 14, 4308 .atu_move_port_mask = 0x1f, 4309 .pvt = true, 4310 .multi_chip = true, 4311 .tag_protocol = DSA_TAG_PROTO_DSA, 4312 .ptp_support = true, 4313 .ops = &mv88e6191_ops, 4314 }, 4315 4316 [MV88E6220] = { 4317 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4318 .family = MV88E6XXX_FAMILY_6250, 4319 .name = "Marvell 88E6220", 4320 .num_databases = 64, 4321 4322 /* Ports 2-4 are not routed to pins 4323 * => usable ports 0, 1, 5, 6 4324 */ 4325 .num_ports = 7, 4326 .num_internal_phys = 2, 4327 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4328 .max_vid = 4095, 4329 .port_base_addr = 0x08, 4330 .phy_base_addr = 0x00, 4331 .global1_addr = 0x0f, 4332 .global2_addr = 0x07, 4333 .age_time_coeff = 15000, 4334 .g1_irqs = 9, 4335 .g2_irqs = 10, 4336 .atu_move_port_mask = 0xf, 4337 .dual_chip = true, 4338 .tag_protocol = DSA_TAG_PROTO_DSA, 4339 .ptp_support = true, 4340 .ops = &mv88e6250_ops, 4341 }, 4342 4343 [MV88E6240] = { 4344 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4345 .family = MV88E6XXX_FAMILY_6352, 4346 .name = "Marvell 88E6240", 4347 .num_databases = 4096, 4348 .num_ports = 7, 4349 .num_internal_phys = 5, 4350 .num_gpio = 15, 4351 .max_vid = 4095, 4352 .port_base_addr = 0x10, 4353 .phy_base_addr = 0x0, 4354 .global1_addr = 0x1b, 4355 .global2_addr = 0x1c, 4356 .age_time_coeff = 15000, 4357 .g1_irqs = 9, 4358 .g2_irqs = 10, 4359 .atu_move_port_mask = 0xf, 4360 .pvt = true, 4361 .multi_chip = true, 4362 .tag_protocol = DSA_TAG_PROTO_EDSA, 4363 .ptp_support = true, 4364 .ops = &mv88e6240_ops, 4365 }, 4366 4367 [MV88E6250] = { 4368 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4369 .family = MV88E6XXX_FAMILY_6250, 4370 .name = "Marvell 88E6250", 4371 .num_databases = 64, 4372 .num_ports = 7, 4373 .num_internal_phys = 5, 4374 .max_vid = 4095, 4375 .port_base_addr = 0x08, 4376 .phy_base_addr = 0x00, 4377 .global1_addr = 0x0f, 4378 .global2_addr = 0x07, 4379 .age_time_coeff = 15000, 4380 .g1_irqs = 9, 4381 .g2_irqs = 10, 4382 .atu_move_port_mask = 0xf, 4383 .dual_chip = true, 4384 .tag_protocol = DSA_TAG_PROTO_DSA, 4385 .ptp_support = true, 4386 .ops = &mv88e6250_ops, 4387 }, 4388 4389 [MV88E6290] = { 4390 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4391 .family = MV88E6XXX_FAMILY_6390, 4392 .name = "Marvell 88E6290", 4393 .num_databases = 4096, 4394 .num_ports = 11, /* 10 + Z80 */ 4395 .num_internal_phys = 9, 4396 .num_gpio = 16, 4397 .max_vid = 8191, 4398 .port_base_addr = 0x0, 4399 .phy_base_addr = 0x0, 4400 .global1_addr = 0x1b, 4401 .global2_addr = 0x1c, 4402 .age_time_coeff = 3750, 4403 .g1_irqs = 9, 4404 .g2_irqs = 14, 4405 .atu_move_port_mask = 0x1f, 4406 .pvt = true, 4407 .multi_chip = true, 4408 .tag_protocol = DSA_TAG_PROTO_DSA, 4409 .ptp_support = true, 4410 .ops = &mv88e6290_ops, 4411 }, 4412 4413 [MV88E6320] = { 4414 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4415 .family = MV88E6XXX_FAMILY_6320, 4416 .name = "Marvell 88E6320", 4417 .num_databases = 4096, 4418 .num_ports = 7, 4419 .num_internal_phys = 5, 4420 .num_gpio = 15, 4421 .max_vid = 4095, 4422 .port_base_addr = 0x10, 4423 .phy_base_addr = 0x0, 4424 .global1_addr = 0x1b, 4425 .global2_addr = 0x1c, 4426 .age_time_coeff = 15000, 4427 .g1_irqs = 8, 4428 .g2_irqs = 10, 4429 .atu_move_port_mask = 0xf, 4430 .pvt = true, 4431 .multi_chip = true, 4432 .tag_protocol = DSA_TAG_PROTO_EDSA, 4433 .ptp_support = true, 4434 .ops = &mv88e6320_ops, 4435 }, 4436 4437 [MV88E6321] = { 4438 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4439 .family = MV88E6XXX_FAMILY_6320, 4440 .name = "Marvell 88E6321", 4441 .num_databases = 4096, 4442 .num_ports = 7, 4443 .num_internal_phys = 5, 4444 .num_gpio = 15, 4445 .max_vid = 4095, 4446 .port_base_addr = 0x10, 4447 .phy_base_addr = 0x0, 4448 .global1_addr = 0x1b, 4449 .global2_addr = 0x1c, 4450 .age_time_coeff = 15000, 4451 .g1_irqs = 8, 4452 .g2_irqs = 10, 4453 .atu_move_port_mask = 0xf, 4454 .multi_chip = true, 4455 .tag_protocol = DSA_TAG_PROTO_EDSA, 4456 .ptp_support = true, 4457 .ops = &mv88e6321_ops, 4458 }, 4459 4460 [MV88E6341] = { 4461 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4462 .family = MV88E6XXX_FAMILY_6341, 4463 .name = "Marvell 88E6341", 4464 .num_databases = 4096, 4465 .num_internal_phys = 5, 4466 .num_ports = 6, 4467 .num_gpio = 11, 4468 .max_vid = 4095, 4469 .port_base_addr = 0x10, 4470 .phy_base_addr = 0x10, 4471 .global1_addr = 0x1b, 4472 .global2_addr = 0x1c, 4473 .age_time_coeff = 3750, 4474 .atu_move_port_mask = 0x1f, 4475 .g1_irqs = 9, 4476 .g2_irqs = 10, 4477 .pvt = true, 4478 .multi_chip = true, 4479 .tag_protocol = DSA_TAG_PROTO_EDSA, 4480 .ptp_support = true, 4481 .ops = &mv88e6341_ops, 4482 }, 4483 4484 [MV88E6350] = { 4485 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4486 .family = MV88E6XXX_FAMILY_6351, 4487 .name = "Marvell 88E6350", 4488 .num_databases = 4096, 4489 .num_ports = 7, 4490 .num_internal_phys = 5, 4491 .max_vid = 4095, 4492 .port_base_addr = 0x10, 4493 .phy_base_addr = 0x0, 4494 .global1_addr = 0x1b, 4495 .global2_addr = 0x1c, 4496 .age_time_coeff = 15000, 4497 .g1_irqs = 9, 4498 .g2_irqs = 10, 4499 .atu_move_port_mask = 0xf, 4500 .pvt = true, 4501 .multi_chip = true, 4502 .tag_protocol = DSA_TAG_PROTO_EDSA, 4503 .ops = &mv88e6350_ops, 4504 }, 4505 4506 [MV88E6351] = { 4507 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4508 .family = MV88E6XXX_FAMILY_6351, 4509 .name = "Marvell 88E6351", 4510 .num_databases = 4096, 4511 .num_ports = 7, 4512 .num_internal_phys = 5, 4513 .max_vid = 4095, 4514 .port_base_addr = 0x10, 4515 .phy_base_addr = 0x0, 4516 .global1_addr = 0x1b, 4517 .global2_addr = 0x1c, 4518 .age_time_coeff = 15000, 4519 .g1_irqs = 9, 4520 .g2_irqs = 10, 4521 .atu_move_port_mask = 0xf, 4522 .pvt = true, 4523 .multi_chip = true, 4524 .tag_protocol = DSA_TAG_PROTO_EDSA, 4525 .ops = &mv88e6351_ops, 4526 }, 4527 4528 [MV88E6352] = { 4529 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4530 .family = MV88E6XXX_FAMILY_6352, 4531 .name = "Marvell 88E6352", 4532 .num_databases = 4096, 4533 .num_ports = 7, 4534 .num_internal_phys = 5, 4535 .num_gpio = 15, 4536 .max_vid = 4095, 4537 .port_base_addr = 0x10, 4538 .phy_base_addr = 0x0, 4539 .global1_addr = 0x1b, 4540 .global2_addr = 0x1c, 4541 .age_time_coeff = 15000, 4542 .g1_irqs = 9, 4543 .g2_irqs = 10, 4544 .atu_move_port_mask = 0xf, 4545 .pvt = true, 4546 .multi_chip = true, 4547 .tag_protocol = DSA_TAG_PROTO_EDSA, 4548 .ptp_support = true, 4549 .ops = &mv88e6352_ops, 4550 }, 4551 [MV88E6390] = { 4552 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4553 .family = MV88E6XXX_FAMILY_6390, 4554 .name = "Marvell 88E6390", 4555 .num_databases = 4096, 4556 .num_ports = 11, /* 10 + Z80 */ 4557 .num_internal_phys = 9, 4558 .num_gpio = 16, 4559 .max_vid = 8191, 4560 .port_base_addr = 0x0, 4561 .phy_base_addr = 0x0, 4562 .global1_addr = 0x1b, 4563 .global2_addr = 0x1c, 4564 .age_time_coeff = 3750, 4565 .g1_irqs = 9, 4566 .g2_irqs = 14, 4567 .atu_move_port_mask = 0x1f, 4568 .pvt = true, 4569 .multi_chip = true, 4570 .tag_protocol = DSA_TAG_PROTO_DSA, 4571 .ptp_support = true, 4572 .ops = &mv88e6390_ops, 4573 }, 4574 [MV88E6390X] = { 4575 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4576 .family = MV88E6XXX_FAMILY_6390, 4577 .name = "Marvell 88E6390X", 4578 .num_databases = 4096, 4579 .num_ports = 11, /* 10 + Z80 */ 4580 .num_internal_phys = 9, 4581 .num_gpio = 16, 4582 .max_vid = 8191, 4583 .port_base_addr = 0x0, 4584 .phy_base_addr = 0x0, 4585 .global1_addr = 0x1b, 4586 .global2_addr = 0x1c, 4587 .age_time_coeff = 3750, 4588 .g1_irqs = 9, 4589 .g2_irqs = 14, 4590 .atu_move_port_mask = 0x1f, 4591 .pvt = true, 4592 .multi_chip = true, 4593 .tag_protocol = DSA_TAG_PROTO_DSA, 4594 .ptp_support = true, 4595 .ops = &mv88e6390x_ops, 4596 }, 4597 }; 4598 4599 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4600 { 4601 int i; 4602 4603 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4604 if (mv88e6xxx_table[i].prod_num == prod_num) 4605 return &mv88e6xxx_table[i]; 4606 4607 return NULL; 4608 } 4609 4610 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4611 { 4612 const struct mv88e6xxx_info *info; 4613 unsigned int prod_num, rev; 4614 u16 id; 4615 int err; 4616 4617 mv88e6xxx_reg_lock(chip); 4618 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4619 mv88e6xxx_reg_unlock(chip); 4620 if (err) 4621 return err; 4622 4623 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4624 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4625 4626 info = mv88e6xxx_lookup_info(prod_num); 4627 if (!info) 4628 return -ENODEV; 4629 4630 /* Update the compatible info with the probed one */ 4631 chip->info = info; 4632 4633 err = mv88e6xxx_g2_require(chip); 4634 if (err) 4635 return err; 4636 4637 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4638 chip->info->prod_num, chip->info->name, rev); 4639 4640 return 0; 4641 } 4642 4643 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4644 { 4645 struct mv88e6xxx_chip *chip; 4646 4647 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4648 if (!chip) 4649 return NULL; 4650 4651 chip->dev = dev; 4652 4653 mutex_init(&chip->reg_lock); 4654 INIT_LIST_HEAD(&chip->mdios); 4655 4656 return chip; 4657 } 4658 4659 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4660 int port) 4661 { 4662 struct mv88e6xxx_chip *chip = ds->priv; 4663 4664 return chip->info->tag_protocol; 4665 } 4666 4667 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4668 const struct switchdev_obj_port_mdb *mdb) 4669 { 4670 /* We don't need any dynamic resource from the kernel (yet), 4671 * so skip the prepare phase. 4672 */ 4673 4674 return 0; 4675 } 4676 4677 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4678 const struct switchdev_obj_port_mdb *mdb) 4679 { 4680 struct mv88e6xxx_chip *chip = ds->priv; 4681 4682 mv88e6xxx_reg_lock(chip); 4683 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4684 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4685 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4686 port); 4687 mv88e6xxx_reg_unlock(chip); 4688 } 4689 4690 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4691 const struct switchdev_obj_port_mdb *mdb) 4692 { 4693 struct mv88e6xxx_chip *chip = ds->priv; 4694 int err; 4695 4696 mv88e6xxx_reg_lock(chip); 4697 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4698 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4699 mv88e6xxx_reg_unlock(chip); 4700 4701 return err; 4702 } 4703 4704 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 4705 bool unicast, bool multicast) 4706 { 4707 struct mv88e6xxx_chip *chip = ds->priv; 4708 int err = -EOPNOTSUPP; 4709 4710 mv88e6xxx_reg_lock(chip); 4711 if (chip->info->ops->port_set_egress_floods) 4712 err = chip->info->ops->port_set_egress_floods(chip, port, 4713 unicast, 4714 multicast); 4715 mv88e6xxx_reg_unlock(chip); 4716 4717 return err; 4718 } 4719 4720 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4721 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4722 .setup = mv88e6xxx_setup, 4723 .adjust_link = mv88e6xxx_adjust_link, 4724 .phylink_validate = mv88e6xxx_validate, 4725 .phylink_mac_link_state = mv88e6xxx_link_state, 4726 .phylink_mac_config = mv88e6xxx_mac_config, 4727 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4728 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4729 .get_strings = mv88e6xxx_get_strings, 4730 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4731 .get_sset_count = mv88e6xxx_get_sset_count, 4732 .port_enable = mv88e6xxx_port_enable, 4733 .port_disable = mv88e6xxx_port_disable, 4734 .get_mac_eee = mv88e6xxx_get_mac_eee, 4735 .set_mac_eee = mv88e6xxx_set_mac_eee, 4736 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4737 .get_eeprom = mv88e6xxx_get_eeprom, 4738 .set_eeprom = mv88e6xxx_set_eeprom, 4739 .get_regs_len = mv88e6xxx_get_regs_len, 4740 .get_regs = mv88e6xxx_get_regs, 4741 .set_ageing_time = mv88e6xxx_set_ageing_time, 4742 .port_bridge_join = mv88e6xxx_port_bridge_join, 4743 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4744 .port_egress_floods = mv88e6xxx_port_egress_floods, 4745 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4746 .port_fast_age = mv88e6xxx_port_fast_age, 4747 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4748 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4749 .port_vlan_add = mv88e6xxx_port_vlan_add, 4750 .port_vlan_del = mv88e6xxx_port_vlan_del, 4751 .port_fdb_add = mv88e6xxx_port_fdb_add, 4752 .port_fdb_del = mv88e6xxx_port_fdb_del, 4753 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4754 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4755 .port_mdb_add = mv88e6xxx_port_mdb_add, 4756 .port_mdb_del = mv88e6xxx_port_mdb_del, 4757 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4758 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4759 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4760 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4761 .port_txtstamp = mv88e6xxx_port_txtstamp, 4762 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4763 .get_ts_info = mv88e6xxx_get_ts_info, 4764 }; 4765 4766 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4767 { 4768 struct device *dev = chip->dev; 4769 struct dsa_switch *ds; 4770 4771 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4772 if (!ds) 4773 return -ENOMEM; 4774 4775 ds->priv = chip; 4776 ds->dev = dev; 4777 ds->ops = &mv88e6xxx_switch_ops; 4778 ds->ageing_time_min = chip->info->age_time_coeff; 4779 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4780 4781 dev_set_drvdata(dev, ds); 4782 4783 return dsa_register_switch(ds); 4784 } 4785 4786 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4787 { 4788 dsa_unregister_switch(chip->ds); 4789 } 4790 4791 static const void *pdata_device_get_match_data(struct device *dev) 4792 { 4793 const struct of_device_id *matches = dev->driver->of_match_table; 4794 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4795 4796 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4797 matches++) { 4798 if (!strcmp(pdata->compatible, matches->compatible)) 4799 return matches->data; 4800 } 4801 return NULL; 4802 } 4803 4804 /* There is no suspend to RAM support at DSA level yet, the switch configuration 4805 * would be lost after a power cycle so prevent it to be suspended. 4806 */ 4807 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 4808 { 4809 return -EOPNOTSUPP; 4810 } 4811 4812 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 4813 { 4814 return 0; 4815 } 4816 4817 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 4818 4819 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4820 { 4821 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4822 const struct mv88e6xxx_info *compat_info = NULL; 4823 struct device *dev = &mdiodev->dev; 4824 struct device_node *np = dev->of_node; 4825 struct mv88e6xxx_chip *chip; 4826 int port; 4827 int err; 4828 4829 if (!np && !pdata) 4830 return -EINVAL; 4831 4832 if (np) 4833 compat_info = of_device_get_match_data(dev); 4834 4835 if (pdata) { 4836 compat_info = pdata_device_get_match_data(dev); 4837 4838 if (!pdata->netdev) 4839 return -EINVAL; 4840 4841 for (port = 0; port < DSA_MAX_PORTS; port++) { 4842 if (!(pdata->enabled_ports & (1 << port))) 4843 continue; 4844 if (strcmp(pdata->cd.port_names[port], "cpu")) 4845 continue; 4846 pdata->cd.netdev[port] = &pdata->netdev->dev; 4847 break; 4848 } 4849 } 4850 4851 if (!compat_info) 4852 return -EINVAL; 4853 4854 chip = mv88e6xxx_alloc_chip(dev); 4855 if (!chip) { 4856 err = -ENOMEM; 4857 goto out; 4858 } 4859 4860 chip->info = compat_info; 4861 4862 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4863 if (err) 4864 goto out; 4865 4866 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4867 if (IS_ERR(chip->reset)) { 4868 err = PTR_ERR(chip->reset); 4869 goto out; 4870 } 4871 if (chip->reset) 4872 usleep_range(1000, 2000); 4873 4874 err = mv88e6xxx_detect(chip); 4875 if (err) 4876 goto out; 4877 4878 mv88e6xxx_phy_init(chip); 4879 4880 if (chip->info->ops->get_eeprom) { 4881 if (np) 4882 of_property_read_u32(np, "eeprom-length", 4883 &chip->eeprom_len); 4884 else 4885 chip->eeprom_len = pdata->eeprom_len; 4886 } 4887 4888 mv88e6xxx_reg_lock(chip); 4889 err = mv88e6xxx_switch_reset(chip); 4890 mv88e6xxx_reg_unlock(chip); 4891 if (err) 4892 goto out; 4893 4894 if (np) { 4895 chip->irq = of_irq_get(np, 0); 4896 if (chip->irq == -EPROBE_DEFER) { 4897 err = chip->irq; 4898 goto out; 4899 } 4900 } 4901 4902 if (pdata) 4903 chip->irq = pdata->irq; 4904 4905 /* Has to be performed before the MDIO bus is created, because 4906 * the PHYs will link their interrupts to these interrupt 4907 * controllers 4908 */ 4909 mv88e6xxx_reg_lock(chip); 4910 if (chip->irq > 0) 4911 err = mv88e6xxx_g1_irq_setup(chip); 4912 else 4913 err = mv88e6xxx_irq_poll_setup(chip); 4914 mv88e6xxx_reg_unlock(chip); 4915 4916 if (err) 4917 goto out; 4918 4919 if (chip->info->g2_irqs > 0) { 4920 err = mv88e6xxx_g2_irq_setup(chip); 4921 if (err) 4922 goto out_g1_irq; 4923 } 4924 4925 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4926 if (err) 4927 goto out_g2_irq; 4928 4929 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4930 if (err) 4931 goto out_g1_atu_prob_irq; 4932 4933 err = mv88e6xxx_mdios_register(chip, np); 4934 if (err) 4935 goto out_g1_vtu_prob_irq; 4936 4937 err = mv88e6xxx_register_switch(chip); 4938 if (err) 4939 goto out_mdio; 4940 4941 return 0; 4942 4943 out_mdio: 4944 mv88e6xxx_mdios_unregister(chip); 4945 out_g1_vtu_prob_irq: 4946 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4947 out_g1_atu_prob_irq: 4948 mv88e6xxx_g1_atu_prob_irq_free(chip); 4949 out_g2_irq: 4950 if (chip->info->g2_irqs > 0) 4951 mv88e6xxx_g2_irq_free(chip); 4952 out_g1_irq: 4953 if (chip->irq > 0) 4954 mv88e6xxx_g1_irq_free(chip); 4955 else 4956 mv88e6xxx_irq_poll_free(chip); 4957 out: 4958 if (pdata) 4959 dev_put(pdata->netdev); 4960 4961 return err; 4962 } 4963 4964 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4965 { 4966 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4967 struct mv88e6xxx_chip *chip = ds->priv; 4968 4969 if (chip->info->ptp_support) { 4970 mv88e6xxx_hwtstamp_free(chip); 4971 mv88e6xxx_ptp_free(chip); 4972 } 4973 4974 mv88e6xxx_phy_destroy(chip); 4975 mv88e6xxx_unregister_switch(chip); 4976 mv88e6xxx_mdios_unregister(chip); 4977 4978 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4979 mv88e6xxx_g1_atu_prob_irq_free(chip); 4980 4981 if (chip->info->g2_irqs > 0) 4982 mv88e6xxx_g2_irq_free(chip); 4983 4984 if (chip->irq > 0) 4985 mv88e6xxx_g1_irq_free(chip); 4986 else 4987 mv88e6xxx_irq_poll_free(chip); 4988 } 4989 4990 static const struct of_device_id mv88e6xxx_of_match[] = { 4991 { 4992 .compatible = "marvell,mv88e6085", 4993 .data = &mv88e6xxx_table[MV88E6085], 4994 }, 4995 { 4996 .compatible = "marvell,mv88e6190", 4997 .data = &mv88e6xxx_table[MV88E6190], 4998 }, 4999 { 5000 .compatible = "marvell,mv88e6250", 5001 .data = &mv88e6xxx_table[MV88E6250], 5002 }, 5003 { /* sentinel */ }, 5004 }; 5005 5006 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5007 5008 static struct mdio_driver mv88e6xxx_driver = { 5009 .probe = mv88e6xxx_probe, 5010 .remove = mv88e6xxx_remove, 5011 .mdiodrv.driver = { 5012 .name = "mv88e6085", 5013 .of_match_table = mv88e6xxx_of_match, 5014 .pm = &mv88e6xxx_pm_ops, 5015 }, 5016 }; 5017 5018 mdio_module_driver(mv88e6xxx_driver); 5019 5020 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5021 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5022 MODULE_LICENSE("GPL"); 5023