1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/platform_data/mv88e6xxx.h> 32 #include <linux/netdevice.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/phy.h> 35 #include <linux/phylink.h> 36 #include <net/dsa.h> 37 38 #include "chip.h" 39 #include "global1.h" 40 #include "global2.h" 41 #include "hwtstamp.h" 42 #include "phy.h" 43 #include "port.h" 44 #include "ptp.h" 45 #include "serdes.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 57 * 58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 59 * is the only device connected to the SMI master. In this mode it responds to 60 * all 32 possible SMI addresses, and thus maps directly the internal devices. 61 * 62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 63 * multiple devices to share the SMI interface. In this mode it responds to only 64 * 2 registers, used to indirectly access the internal SMI devices. 65 */ 66 67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 68 int addr, int reg, u16 *val) 69 { 70 if (!chip->smi_ops) 71 return -EOPNOTSUPP; 72 73 return chip->smi_ops->read(chip, addr, reg, val); 74 } 75 76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 77 int addr, int reg, u16 val) 78 { 79 if (!chip->smi_ops) 80 return -EOPNOTSUPP; 81 82 return chip->smi_ops->write(chip, addr, reg, val); 83 } 84 85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 86 int addr, int reg, u16 *val) 87 { 88 int ret; 89 90 ret = mdiobus_read_nested(chip->bus, addr, reg); 91 if (ret < 0) 92 return ret; 93 94 *val = ret & 0xffff; 95 96 return 0; 97 } 98 99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 100 int addr, int reg, u16 val) 101 { 102 int ret; 103 104 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 105 if (ret < 0) 106 return ret; 107 108 return 0; 109 } 110 111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 112 .read = mv88e6xxx_smi_single_chip_read, 113 .write = mv88e6xxx_smi_single_chip_write, 114 }; 115 116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 117 { 118 int ret; 119 int i; 120 121 for (i = 0; i < 16; i++) { 122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 123 if (ret < 0) 124 return ret; 125 126 if ((ret & SMI_CMD_BUSY) == 0) 127 return 0; 128 } 129 130 return -ETIMEDOUT; 131 } 132 133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 134 int addr, int reg, u16 *val) 135 { 136 int ret; 137 138 /* Wait for the bus to become free. */ 139 ret = mv88e6xxx_smi_multi_chip_wait(chip); 140 if (ret < 0) 141 return ret; 142 143 /* Transmit the read command. */ 144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 145 SMI_CMD_OP_22_READ | (addr << 5) | reg); 146 if (ret < 0) 147 return ret; 148 149 /* Wait for the read command to complete. */ 150 ret = mv88e6xxx_smi_multi_chip_wait(chip); 151 if (ret < 0) 152 return ret; 153 154 /* Read the data. */ 155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 156 if (ret < 0) 157 return ret; 158 159 *val = ret & 0xffff; 160 161 return 0; 162 } 163 164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 165 int addr, int reg, u16 val) 166 { 167 int ret; 168 169 /* Wait for the bus to become free. */ 170 ret = mv88e6xxx_smi_multi_chip_wait(chip); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the data to write. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 176 if (ret < 0) 177 return ret; 178 179 /* Transmit the write command. */ 180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 182 if (ret < 0) 183 return ret; 184 185 /* Wait for the write command to complete. */ 186 ret = mv88e6xxx_smi_multi_chip_wait(chip); 187 if (ret < 0) 188 return ret; 189 190 return 0; 191 } 192 193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 194 .read = mv88e6xxx_smi_multi_chip_read, 195 .write = mv88e6xxx_smi_multi_chip_write, 196 }; 197 198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 199 { 200 int err; 201 202 assert_reg_lock(chip); 203 204 err = mv88e6xxx_smi_read(chip, addr, reg, val); 205 if (err) 206 return err; 207 208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 209 addr, reg, *val); 210 211 return 0; 212 } 213 214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 215 { 216 int err; 217 218 assert_reg_lock(chip); 219 220 err = mv88e6xxx_smi_write(chip, addr, reg, val); 221 if (err) 222 return err; 223 224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 225 addr, reg, val); 226 227 return 0; 228 } 229 230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 231 { 232 struct mv88e6xxx_mdio_bus *mdio_bus; 233 234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 235 list); 236 if (!mdio_bus) 237 return NULL; 238 239 return mdio_bus->bus; 240 } 241 242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 243 { 244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 245 unsigned int n = d->hwirq; 246 247 chip->g1_irq.masked |= (1 << n); 248 } 249 250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 251 { 252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 253 unsigned int n = d->hwirq; 254 255 chip->g1_irq.masked &= ~(1 << n); 256 } 257 258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 259 { 260 unsigned int nhandled = 0; 261 unsigned int sub_irq; 262 unsigned int n; 263 u16 reg; 264 int err; 265 266 mutex_lock(&chip->reg_lock); 267 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 268 mutex_unlock(&chip->reg_lock); 269 270 if (err) 271 goto out; 272 273 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 274 if (reg & (1 << n)) { 275 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 276 handle_nested_irq(sub_irq); 277 ++nhandled; 278 } 279 } 280 out: 281 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 282 } 283 284 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 285 { 286 struct mv88e6xxx_chip *chip = dev_id; 287 288 return mv88e6xxx_g1_irq_thread_work(chip); 289 } 290 291 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 292 { 293 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 294 295 mutex_lock(&chip->reg_lock); 296 } 297 298 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 299 { 300 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 301 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 302 u16 reg; 303 int err; 304 305 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 306 if (err) 307 goto out; 308 309 reg &= ~mask; 310 reg |= (~chip->g1_irq.masked & mask); 311 312 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 313 if (err) 314 goto out; 315 316 out: 317 mutex_unlock(&chip->reg_lock); 318 } 319 320 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 321 .name = "mv88e6xxx-g1", 322 .irq_mask = mv88e6xxx_g1_irq_mask, 323 .irq_unmask = mv88e6xxx_g1_irq_unmask, 324 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 325 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 326 }; 327 328 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 329 unsigned int irq, 330 irq_hw_number_t hwirq) 331 { 332 struct mv88e6xxx_chip *chip = d->host_data; 333 334 irq_set_chip_data(irq, d->host_data); 335 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 336 irq_set_noprobe(irq); 337 338 return 0; 339 } 340 341 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 342 .map = mv88e6xxx_g1_irq_domain_map, 343 .xlate = irq_domain_xlate_twocell, 344 }; 345 346 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 347 { 348 int irq, virq; 349 u16 mask; 350 351 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 352 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 353 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 354 355 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 356 virq = irq_find_mapping(chip->g1_irq.domain, irq); 357 irq_dispose_mapping(virq); 358 } 359 360 irq_domain_remove(chip->g1_irq.domain); 361 } 362 363 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 364 { 365 mv88e6xxx_g1_irq_free_common(chip); 366 367 free_irq(chip->irq, chip); 368 } 369 370 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 371 { 372 int err, irq, virq; 373 u16 reg, mask; 374 375 chip->g1_irq.nirqs = chip->info->g1_irqs; 376 chip->g1_irq.domain = irq_domain_add_simple( 377 NULL, chip->g1_irq.nirqs, 0, 378 &mv88e6xxx_g1_irq_domain_ops, chip); 379 if (!chip->g1_irq.domain) 380 return -ENOMEM; 381 382 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 383 irq_create_mapping(chip->g1_irq.domain, irq); 384 385 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 386 chip->g1_irq.masked = ~0; 387 388 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 389 if (err) 390 goto out_mapping; 391 392 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 393 394 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 395 if (err) 396 goto out_disable; 397 398 /* Reading the interrupt status clears (most of) them */ 399 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 400 if (err) 401 goto out_disable; 402 403 return 0; 404 405 out_disable: 406 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 407 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 408 409 out_mapping: 410 for (irq = 0; irq < 16; irq++) { 411 virq = irq_find_mapping(chip->g1_irq.domain, irq); 412 irq_dispose_mapping(virq); 413 } 414 415 irq_domain_remove(chip->g1_irq.domain); 416 417 return err; 418 } 419 420 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 421 { 422 int err; 423 424 err = mv88e6xxx_g1_irq_setup_common(chip); 425 if (err) 426 return err; 427 428 err = request_threaded_irq(chip->irq, NULL, 429 mv88e6xxx_g1_irq_thread_fn, 430 IRQF_ONESHOT, 431 dev_name(chip->dev), chip); 432 if (err) 433 mv88e6xxx_g1_irq_free_common(chip); 434 435 return err; 436 } 437 438 static void mv88e6xxx_irq_poll(struct kthread_work *work) 439 { 440 struct mv88e6xxx_chip *chip = container_of(work, 441 struct mv88e6xxx_chip, 442 irq_poll_work.work); 443 mv88e6xxx_g1_irq_thread_work(chip); 444 445 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 446 msecs_to_jiffies(100)); 447 } 448 449 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 450 { 451 int err; 452 453 err = mv88e6xxx_g1_irq_setup_common(chip); 454 if (err) 455 return err; 456 457 kthread_init_delayed_work(&chip->irq_poll_work, 458 mv88e6xxx_irq_poll); 459 460 chip->kworker = kthread_create_worker(0, dev_name(chip->dev)); 461 if (IS_ERR(chip->kworker)) 462 return PTR_ERR(chip->kworker); 463 464 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 465 msecs_to_jiffies(100)); 466 467 return 0; 468 } 469 470 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 471 { 472 mv88e6xxx_g1_irq_free_common(chip); 473 474 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 475 kthread_destroy_worker(chip->kworker); 476 } 477 478 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 479 { 480 int i; 481 482 for (i = 0; i < 16; i++) { 483 u16 val; 484 int err; 485 486 err = mv88e6xxx_read(chip, addr, reg, &val); 487 if (err) 488 return err; 489 490 if (!(val & mask)) 491 return 0; 492 493 usleep_range(1000, 2000); 494 } 495 496 dev_err(chip->dev, "Timeout while waiting for switch\n"); 497 return -ETIMEDOUT; 498 } 499 500 /* Indirect write to single pointer-data register with an Update bit */ 501 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 502 { 503 u16 val; 504 int err; 505 506 /* Wait until the previous operation is completed */ 507 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 508 if (err) 509 return err; 510 511 /* Set the Update bit to trigger a write operation */ 512 val = BIT(15) | update; 513 514 return mv88e6xxx_write(chip, addr, reg, val); 515 } 516 517 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 518 int link, int speed, int duplex, 519 phy_interface_t mode) 520 { 521 int err; 522 523 if (!chip->info->ops->port_set_link) 524 return 0; 525 526 /* Port's MAC control must not be changed unless the link is down */ 527 err = chip->info->ops->port_set_link(chip, port, 0); 528 if (err) 529 return err; 530 531 if (chip->info->ops->port_set_speed) { 532 err = chip->info->ops->port_set_speed(chip, port, speed); 533 if (err && err != -EOPNOTSUPP) 534 goto restore_link; 535 } 536 537 if (chip->info->ops->port_set_duplex) { 538 err = chip->info->ops->port_set_duplex(chip, port, duplex); 539 if (err && err != -EOPNOTSUPP) 540 goto restore_link; 541 } 542 543 if (chip->info->ops->port_set_rgmii_delay) { 544 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 545 if (err && err != -EOPNOTSUPP) 546 goto restore_link; 547 } 548 549 if (chip->info->ops->port_set_cmode) { 550 err = chip->info->ops->port_set_cmode(chip, port, mode); 551 if (err && err != -EOPNOTSUPP) 552 goto restore_link; 553 } 554 555 err = 0; 556 restore_link: 557 if (chip->info->ops->port_set_link(chip, port, link)) 558 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 559 560 return err; 561 } 562 563 /* We expect the switch to perform auto negotiation if there is a real 564 * phy. However, in the case of a fixed link phy, we force the port 565 * settings from the fixed link settings. 566 */ 567 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 568 struct phy_device *phydev) 569 { 570 struct mv88e6xxx_chip *chip = ds->priv; 571 int err; 572 573 if (!phy_is_pseudo_fixed_link(phydev)) 574 return; 575 576 mutex_lock(&chip->reg_lock); 577 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 578 phydev->duplex, phydev->interface); 579 mutex_unlock(&chip->reg_lock); 580 581 if (err && err != -EOPNOTSUPP) 582 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 583 } 584 585 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 586 unsigned long *supported, 587 struct phylink_link_state *state) 588 { 589 } 590 591 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 592 struct phylink_link_state *state) 593 { 594 struct mv88e6xxx_chip *chip = ds->priv; 595 int err; 596 597 mutex_lock(&chip->reg_lock); 598 err = mv88e6xxx_port_link_state(chip, port, state); 599 mutex_unlock(&chip->reg_lock); 600 601 return err; 602 } 603 604 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 605 unsigned int mode, 606 const struct phylink_link_state *state) 607 { 608 struct mv88e6xxx_chip *chip = ds->priv; 609 int speed, duplex, link, err; 610 611 if (mode == MLO_AN_PHY) 612 return; 613 614 if (mode == MLO_AN_FIXED) { 615 link = LINK_FORCED_UP; 616 speed = state->speed; 617 duplex = state->duplex; 618 } else { 619 speed = SPEED_UNFORCED; 620 duplex = DUPLEX_UNFORCED; 621 link = LINK_UNFORCED; 622 } 623 624 mutex_lock(&chip->reg_lock); 625 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, 626 state->interface); 627 mutex_unlock(&chip->reg_lock); 628 629 if (err && err != -EOPNOTSUPP) 630 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 631 } 632 633 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 634 { 635 struct mv88e6xxx_chip *chip = ds->priv; 636 int err; 637 638 mutex_lock(&chip->reg_lock); 639 err = chip->info->ops->port_set_link(chip, port, link); 640 mutex_unlock(&chip->reg_lock); 641 642 if (err) 643 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 644 } 645 646 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 647 unsigned int mode, 648 phy_interface_t interface) 649 { 650 if (mode == MLO_AN_FIXED) 651 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 652 } 653 654 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 655 unsigned int mode, phy_interface_t interface, 656 struct phy_device *phydev) 657 { 658 if (mode == MLO_AN_FIXED) 659 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 660 } 661 662 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 663 { 664 if (!chip->info->ops->stats_snapshot) 665 return -EOPNOTSUPP; 666 667 return chip->info->ops->stats_snapshot(chip, port); 668 } 669 670 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 671 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 672 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 673 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 674 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 675 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 676 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 677 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 678 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 679 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 680 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 681 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 682 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 683 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 684 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 685 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 686 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 687 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 688 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 689 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 690 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 691 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 692 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 693 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 694 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 695 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 696 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 697 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 698 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 699 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 700 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 701 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 702 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 703 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 704 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 705 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 706 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 707 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 708 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 709 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 710 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 711 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 712 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 713 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 714 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 715 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 716 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 717 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 718 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 719 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 720 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 721 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 722 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 723 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 724 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 725 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 726 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 727 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 728 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 729 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 730 }; 731 732 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 733 struct mv88e6xxx_hw_stat *s, 734 int port, u16 bank1_select, 735 u16 histogram) 736 { 737 u32 low; 738 u32 high = 0; 739 u16 reg = 0; 740 int err; 741 u64 value; 742 743 switch (s->type) { 744 case STATS_TYPE_PORT: 745 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 746 if (err) 747 return U64_MAX; 748 749 low = reg; 750 if (s->size == 4) { 751 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 752 if (err) 753 return U64_MAX; 754 high = reg; 755 } 756 break; 757 case STATS_TYPE_BANK1: 758 reg = bank1_select; 759 /* fall through */ 760 case STATS_TYPE_BANK0: 761 reg |= s->reg | histogram; 762 mv88e6xxx_g1_stats_read(chip, reg, &low); 763 if (s->size == 8) 764 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 765 break; 766 default: 767 return U64_MAX; 768 } 769 value = (((u64)high) << 16) | low; 770 return value; 771 } 772 773 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 774 uint8_t *data, int types) 775 { 776 struct mv88e6xxx_hw_stat *stat; 777 int i, j; 778 779 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 780 stat = &mv88e6xxx_hw_stats[i]; 781 if (stat->type & types) { 782 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 783 ETH_GSTRING_LEN); 784 j++; 785 } 786 } 787 788 return j; 789 } 790 791 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 792 uint8_t *data) 793 { 794 return mv88e6xxx_stats_get_strings(chip, data, 795 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 796 } 797 798 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 799 uint8_t *data) 800 { 801 return mv88e6xxx_stats_get_strings(chip, data, 802 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 803 } 804 805 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 806 "atu_member_violation", 807 "atu_miss_violation", 808 "atu_full_violation", 809 "vtu_member_violation", 810 "vtu_miss_violation", 811 }; 812 813 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 814 { 815 unsigned int i; 816 817 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 818 strlcpy(data + i * ETH_GSTRING_LEN, 819 mv88e6xxx_atu_vtu_stats_strings[i], 820 ETH_GSTRING_LEN); 821 } 822 823 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 824 u32 stringset, uint8_t *data) 825 { 826 struct mv88e6xxx_chip *chip = ds->priv; 827 int count = 0; 828 829 if (stringset != ETH_SS_STATS) 830 return; 831 832 mutex_lock(&chip->reg_lock); 833 834 if (chip->info->ops->stats_get_strings) 835 count = chip->info->ops->stats_get_strings(chip, data); 836 837 if (chip->info->ops->serdes_get_strings) { 838 data += count * ETH_GSTRING_LEN; 839 count = chip->info->ops->serdes_get_strings(chip, port, data); 840 } 841 842 data += count * ETH_GSTRING_LEN; 843 mv88e6xxx_atu_vtu_get_strings(data); 844 845 mutex_unlock(&chip->reg_lock); 846 } 847 848 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 849 int types) 850 { 851 struct mv88e6xxx_hw_stat *stat; 852 int i, j; 853 854 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 855 stat = &mv88e6xxx_hw_stats[i]; 856 if (stat->type & types) 857 j++; 858 } 859 return j; 860 } 861 862 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 863 { 864 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 865 STATS_TYPE_PORT); 866 } 867 868 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 869 { 870 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 871 STATS_TYPE_BANK1); 872 } 873 874 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 875 { 876 struct mv88e6xxx_chip *chip = ds->priv; 877 int serdes_count = 0; 878 int count = 0; 879 880 if (sset != ETH_SS_STATS) 881 return 0; 882 883 mutex_lock(&chip->reg_lock); 884 if (chip->info->ops->stats_get_sset_count) 885 count = chip->info->ops->stats_get_sset_count(chip); 886 if (count < 0) 887 goto out; 888 889 if (chip->info->ops->serdes_get_sset_count) 890 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 891 port); 892 if (serdes_count < 0) { 893 count = serdes_count; 894 goto out; 895 } 896 count += serdes_count; 897 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 898 899 out: 900 mutex_unlock(&chip->reg_lock); 901 902 return count; 903 } 904 905 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 906 uint64_t *data, int types, 907 u16 bank1_select, u16 histogram) 908 { 909 struct mv88e6xxx_hw_stat *stat; 910 int i, j; 911 912 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 913 stat = &mv88e6xxx_hw_stats[i]; 914 if (stat->type & types) { 915 mutex_lock(&chip->reg_lock); 916 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 917 bank1_select, 918 histogram); 919 mutex_unlock(&chip->reg_lock); 920 921 j++; 922 } 923 } 924 return j; 925 } 926 927 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 928 uint64_t *data) 929 { 930 return mv88e6xxx_stats_get_stats(chip, port, data, 931 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 932 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 933 } 934 935 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 936 uint64_t *data) 937 { 938 return mv88e6xxx_stats_get_stats(chip, port, data, 939 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 940 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 941 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 942 } 943 944 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 945 uint64_t *data) 946 { 947 return mv88e6xxx_stats_get_stats(chip, port, data, 948 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 949 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 950 0); 951 } 952 953 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 954 uint64_t *data) 955 { 956 *data++ = chip->ports[port].atu_member_violation; 957 *data++ = chip->ports[port].atu_miss_violation; 958 *data++ = chip->ports[port].atu_full_violation; 959 *data++ = chip->ports[port].vtu_member_violation; 960 *data++ = chip->ports[port].vtu_miss_violation; 961 } 962 963 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 964 uint64_t *data) 965 { 966 int count = 0; 967 968 if (chip->info->ops->stats_get_stats) 969 count = chip->info->ops->stats_get_stats(chip, port, data); 970 971 mutex_lock(&chip->reg_lock); 972 if (chip->info->ops->serdes_get_stats) { 973 data += count; 974 count = chip->info->ops->serdes_get_stats(chip, port, data); 975 } 976 data += count; 977 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 978 mutex_unlock(&chip->reg_lock); 979 } 980 981 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 982 uint64_t *data) 983 { 984 struct mv88e6xxx_chip *chip = ds->priv; 985 int ret; 986 987 mutex_lock(&chip->reg_lock); 988 989 ret = mv88e6xxx_stats_snapshot(chip, port); 990 mutex_unlock(&chip->reg_lock); 991 992 if (ret < 0) 993 return; 994 995 mv88e6xxx_get_stats(chip, port, data); 996 997 } 998 999 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1000 { 1001 return 32 * sizeof(u16); 1002 } 1003 1004 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1005 struct ethtool_regs *regs, void *_p) 1006 { 1007 struct mv88e6xxx_chip *chip = ds->priv; 1008 int err; 1009 u16 reg; 1010 u16 *p = _p; 1011 int i; 1012 1013 regs->version = 0; 1014 1015 memset(p, 0xff, 32 * sizeof(u16)); 1016 1017 mutex_lock(&chip->reg_lock); 1018 1019 for (i = 0; i < 32; i++) { 1020 1021 err = mv88e6xxx_port_read(chip, port, i, ®); 1022 if (!err) 1023 p[i] = reg; 1024 } 1025 1026 mutex_unlock(&chip->reg_lock); 1027 } 1028 1029 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1030 struct ethtool_eee *e) 1031 { 1032 /* Nothing to do on the port's MAC */ 1033 return 0; 1034 } 1035 1036 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1037 struct ethtool_eee *e) 1038 { 1039 /* Nothing to do on the port's MAC */ 1040 return 0; 1041 } 1042 1043 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1044 { 1045 struct dsa_switch *ds = NULL; 1046 struct net_device *br; 1047 u16 pvlan; 1048 int i; 1049 1050 if (dev < DSA_MAX_SWITCHES) 1051 ds = chip->ds->dst->ds[dev]; 1052 1053 /* Prevent frames from unknown switch or port */ 1054 if (!ds || port >= ds->num_ports) 1055 return 0; 1056 1057 /* Frames from DSA links and CPU ports can egress any local port */ 1058 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1059 return mv88e6xxx_port_mask(chip); 1060 1061 br = ds->ports[port].bridge_dev; 1062 pvlan = 0; 1063 1064 /* Frames from user ports can egress any local DSA links and CPU ports, 1065 * as well as any local member of their bridge group. 1066 */ 1067 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1068 if (dsa_is_cpu_port(chip->ds, i) || 1069 dsa_is_dsa_port(chip->ds, i) || 1070 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1071 pvlan |= BIT(i); 1072 1073 return pvlan; 1074 } 1075 1076 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1077 { 1078 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1079 1080 /* prevent frames from going back out of the port they came in on */ 1081 output_ports &= ~BIT(port); 1082 1083 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1084 } 1085 1086 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1087 u8 state) 1088 { 1089 struct mv88e6xxx_chip *chip = ds->priv; 1090 int err; 1091 1092 mutex_lock(&chip->reg_lock); 1093 err = mv88e6xxx_port_set_state(chip, port, state); 1094 mutex_unlock(&chip->reg_lock); 1095 1096 if (err) 1097 dev_err(ds->dev, "p%d: failed to update state\n", port); 1098 } 1099 1100 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1101 { 1102 int err; 1103 1104 if (chip->info->ops->ieee_pri_map) { 1105 err = chip->info->ops->ieee_pri_map(chip); 1106 if (err) 1107 return err; 1108 } 1109 1110 if (chip->info->ops->ip_pri_map) { 1111 err = chip->info->ops->ip_pri_map(chip); 1112 if (err) 1113 return err; 1114 } 1115 1116 return 0; 1117 } 1118 1119 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1120 { 1121 int target, port; 1122 int err; 1123 1124 if (!chip->info->global2_addr) 1125 return 0; 1126 1127 /* Initialize the routing port to the 32 possible target devices */ 1128 for (target = 0; target < 32; target++) { 1129 port = 0x1f; 1130 if (target < DSA_MAX_SWITCHES) 1131 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1132 port = chip->ds->rtable[target]; 1133 1134 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1135 if (err) 1136 return err; 1137 } 1138 1139 if (chip->info->ops->set_cascade_port) { 1140 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1141 err = chip->info->ops->set_cascade_port(chip, port); 1142 if (err) 1143 return err; 1144 } 1145 1146 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1147 if (err) 1148 return err; 1149 1150 return 0; 1151 } 1152 1153 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1154 { 1155 /* Clear all trunk masks and mapping */ 1156 if (chip->info->global2_addr) 1157 return mv88e6xxx_g2_trunk_clear(chip); 1158 1159 return 0; 1160 } 1161 1162 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1163 { 1164 if (chip->info->ops->rmu_disable) 1165 return chip->info->ops->rmu_disable(chip); 1166 1167 return 0; 1168 } 1169 1170 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1171 { 1172 if (chip->info->ops->pot_clear) 1173 return chip->info->ops->pot_clear(chip); 1174 1175 return 0; 1176 } 1177 1178 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1179 { 1180 if (chip->info->ops->mgmt_rsvd2cpu) 1181 return chip->info->ops->mgmt_rsvd2cpu(chip); 1182 1183 return 0; 1184 } 1185 1186 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1187 { 1188 int err; 1189 1190 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1191 if (err) 1192 return err; 1193 1194 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1195 if (err) 1196 return err; 1197 1198 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1199 } 1200 1201 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1202 { 1203 int port; 1204 int err; 1205 1206 if (!chip->info->ops->irl_init_all) 1207 return 0; 1208 1209 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1210 /* Disable ingress rate limiting by resetting all per port 1211 * ingress rate limit resources to their initial state. 1212 */ 1213 err = chip->info->ops->irl_init_all(chip, port); 1214 if (err) 1215 return err; 1216 } 1217 1218 return 0; 1219 } 1220 1221 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1222 { 1223 if (chip->info->ops->set_switch_mac) { 1224 u8 addr[ETH_ALEN]; 1225 1226 eth_random_addr(addr); 1227 1228 return chip->info->ops->set_switch_mac(chip, addr); 1229 } 1230 1231 return 0; 1232 } 1233 1234 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1235 { 1236 u16 pvlan = 0; 1237 1238 if (!mv88e6xxx_has_pvt(chip)) 1239 return -EOPNOTSUPP; 1240 1241 /* Skip the local source device, which uses in-chip port VLAN */ 1242 if (dev != chip->ds->index) 1243 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1244 1245 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1246 } 1247 1248 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1249 { 1250 int dev, port; 1251 int err; 1252 1253 if (!mv88e6xxx_has_pvt(chip)) 1254 return 0; 1255 1256 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1257 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1258 */ 1259 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1260 if (err) 1261 return err; 1262 1263 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1264 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1265 err = mv88e6xxx_pvt_map(chip, dev, port); 1266 if (err) 1267 return err; 1268 } 1269 } 1270 1271 return 0; 1272 } 1273 1274 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1275 { 1276 struct mv88e6xxx_chip *chip = ds->priv; 1277 int err; 1278 1279 mutex_lock(&chip->reg_lock); 1280 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1281 mutex_unlock(&chip->reg_lock); 1282 1283 if (err) 1284 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1285 } 1286 1287 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1288 { 1289 if (!chip->info->max_vid) 1290 return 0; 1291 1292 return mv88e6xxx_g1_vtu_flush(chip); 1293 } 1294 1295 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1296 struct mv88e6xxx_vtu_entry *entry) 1297 { 1298 if (!chip->info->ops->vtu_getnext) 1299 return -EOPNOTSUPP; 1300 1301 return chip->info->ops->vtu_getnext(chip, entry); 1302 } 1303 1304 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1305 struct mv88e6xxx_vtu_entry *entry) 1306 { 1307 if (!chip->info->ops->vtu_loadpurge) 1308 return -EOPNOTSUPP; 1309 1310 return chip->info->ops->vtu_loadpurge(chip, entry); 1311 } 1312 1313 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1314 { 1315 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1316 struct mv88e6xxx_vtu_entry vlan = { 1317 .vid = chip->info->max_vid, 1318 }; 1319 int i, err; 1320 1321 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1322 1323 /* Set every FID bit used by the (un)bridged ports */ 1324 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1325 err = mv88e6xxx_port_get_fid(chip, i, fid); 1326 if (err) 1327 return err; 1328 1329 set_bit(*fid, fid_bitmap); 1330 } 1331 1332 /* Set every FID bit used by the VLAN entries */ 1333 do { 1334 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1335 if (err) 1336 return err; 1337 1338 if (!vlan.valid) 1339 break; 1340 1341 set_bit(vlan.fid, fid_bitmap); 1342 } while (vlan.vid < chip->info->max_vid); 1343 1344 /* The reset value 0x000 is used to indicate that multiple address 1345 * databases are not needed. Return the next positive available. 1346 */ 1347 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1348 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1349 return -ENOSPC; 1350 1351 /* Clear the database */ 1352 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1353 } 1354 1355 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1356 struct mv88e6xxx_vtu_entry *entry, bool new) 1357 { 1358 int err; 1359 1360 if (!vid) 1361 return -EINVAL; 1362 1363 entry->vid = vid - 1; 1364 entry->valid = false; 1365 1366 err = mv88e6xxx_vtu_getnext(chip, entry); 1367 if (err) 1368 return err; 1369 1370 if (entry->vid == vid && entry->valid) 1371 return 0; 1372 1373 if (new) { 1374 int i; 1375 1376 /* Initialize a fresh VLAN entry */ 1377 memset(entry, 0, sizeof(*entry)); 1378 entry->valid = true; 1379 entry->vid = vid; 1380 1381 /* Exclude all ports */ 1382 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1383 entry->member[i] = 1384 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1385 1386 return mv88e6xxx_atu_new(chip, &entry->fid); 1387 } 1388 1389 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1390 return -EOPNOTSUPP; 1391 } 1392 1393 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1394 u16 vid_begin, u16 vid_end) 1395 { 1396 struct mv88e6xxx_chip *chip = ds->priv; 1397 struct mv88e6xxx_vtu_entry vlan = { 1398 .vid = vid_begin - 1, 1399 }; 1400 int i, err; 1401 1402 /* DSA and CPU ports have to be members of multiple vlans */ 1403 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1404 return 0; 1405 1406 if (!vid_begin) 1407 return -EOPNOTSUPP; 1408 1409 mutex_lock(&chip->reg_lock); 1410 1411 do { 1412 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1413 if (err) 1414 goto unlock; 1415 1416 if (!vlan.valid) 1417 break; 1418 1419 if (vlan.vid > vid_end) 1420 break; 1421 1422 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1423 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1424 continue; 1425 1426 if (!ds->ports[i].slave) 1427 continue; 1428 1429 if (vlan.member[i] == 1430 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1431 continue; 1432 1433 if (dsa_to_port(ds, i)->bridge_dev == 1434 ds->ports[port].bridge_dev) 1435 break; /* same bridge, check next VLAN */ 1436 1437 if (!dsa_to_port(ds, i)->bridge_dev) 1438 continue; 1439 1440 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1441 port, vlan.vid, i, 1442 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1443 err = -EOPNOTSUPP; 1444 goto unlock; 1445 } 1446 } while (vlan.vid < vid_end); 1447 1448 unlock: 1449 mutex_unlock(&chip->reg_lock); 1450 1451 return err; 1452 } 1453 1454 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1455 bool vlan_filtering) 1456 { 1457 struct mv88e6xxx_chip *chip = ds->priv; 1458 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1459 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1460 int err; 1461 1462 if (!chip->info->max_vid) 1463 return -EOPNOTSUPP; 1464 1465 mutex_lock(&chip->reg_lock); 1466 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1467 mutex_unlock(&chip->reg_lock); 1468 1469 return err; 1470 } 1471 1472 static int 1473 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1474 const struct switchdev_obj_port_vlan *vlan) 1475 { 1476 struct mv88e6xxx_chip *chip = ds->priv; 1477 int err; 1478 1479 if (!chip->info->max_vid) 1480 return -EOPNOTSUPP; 1481 1482 /* If the requested port doesn't belong to the same bridge as the VLAN 1483 * members, do not support it (yet) and fallback to software VLAN. 1484 */ 1485 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1486 vlan->vid_end); 1487 if (err) 1488 return err; 1489 1490 /* We don't need any dynamic resource from the kernel (yet), 1491 * so skip the prepare phase. 1492 */ 1493 return 0; 1494 } 1495 1496 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1497 const unsigned char *addr, u16 vid, 1498 u8 state) 1499 { 1500 struct mv88e6xxx_vtu_entry vlan; 1501 struct mv88e6xxx_atu_entry entry; 1502 int err; 1503 1504 /* Null VLAN ID corresponds to the port private database */ 1505 if (vid == 0) 1506 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1507 else 1508 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1509 if (err) 1510 return err; 1511 1512 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1513 ether_addr_copy(entry.mac, addr); 1514 eth_addr_dec(entry.mac); 1515 1516 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1517 if (err) 1518 return err; 1519 1520 /* Initialize a fresh ATU entry if it isn't found */ 1521 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1522 !ether_addr_equal(entry.mac, addr)) { 1523 memset(&entry, 0, sizeof(entry)); 1524 ether_addr_copy(entry.mac, addr); 1525 } 1526 1527 /* Purge the ATU entry only if no port is using it anymore */ 1528 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1529 entry.portvec &= ~BIT(port); 1530 if (!entry.portvec) 1531 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1532 } else { 1533 entry.portvec |= BIT(port); 1534 entry.state = state; 1535 } 1536 1537 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1538 } 1539 1540 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1541 u16 vid) 1542 { 1543 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1544 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1545 1546 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1547 } 1548 1549 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1550 { 1551 int port; 1552 int err; 1553 1554 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1555 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1556 if (err) 1557 return err; 1558 } 1559 1560 return 0; 1561 } 1562 1563 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1564 u16 vid, u8 member) 1565 { 1566 struct mv88e6xxx_vtu_entry vlan; 1567 int err; 1568 1569 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1570 if (err) 1571 return err; 1572 1573 vlan.member[port] = member; 1574 1575 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1576 if (err) 1577 return err; 1578 1579 return mv88e6xxx_broadcast_setup(chip, vid); 1580 } 1581 1582 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1583 const struct switchdev_obj_port_vlan *vlan) 1584 { 1585 struct mv88e6xxx_chip *chip = ds->priv; 1586 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1587 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1588 u8 member; 1589 u16 vid; 1590 1591 if (!chip->info->max_vid) 1592 return; 1593 1594 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1595 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1596 else if (untagged) 1597 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1598 else 1599 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1600 1601 mutex_lock(&chip->reg_lock); 1602 1603 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1604 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1605 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1606 vid, untagged ? 'u' : 't'); 1607 1608 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1609 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1610 vlan->vid_end); 1611 1612 mutex_unlock(&chip->reg_lock); 1613 } 1614 1615 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1616 int port, u16 vid) 1617 { 1618 struct mv88e6xxx_vtu_entry vlan; 1619 int i, err; 1620 1621 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1622 if (err) 1623 return err; 1624 1625 /* Tell switchdev if this VLAN is handled in software */ 1626 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1627 return -EOPNOTSUPP; 1628 1629 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1630 1631 /* keep the VLAN unless all ports are excluded */ 1632 vlan.valid = false; 1633 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1634 if (vlan.member[i] != 1635 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1636 vlan.valid = true; 1637 break; 1638 } 1639 } 1640 1641 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1642 if (err) 1643 return err; 1644 1645 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1646 } 1647 1648 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1649 const struct switchdev_obj_port_vlan *vlan) 1650 { 1651 struct mv88e6xxx_chip *chip = ds->priv; 1652 u16 pvid, vid; 1653 int err = 0; 1654 1655 if (!chip->info->max_vid) 1656 return -EOPNOTSUPP; 1657 1658 mutex_lock(&chip->reg_lock); 1659 1660 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1661 if (err) 1662 goto unlock; 1663 1664 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1665 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1666 if (err) 1667 goto unlock; 1668 1669 if (vid == pvid) { 1670 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1671 if (err) 1672 goto unlock; 1673 } 1674 } 1675 1676 unlock: 1677 mutex_unlock(&chip->reg_lock); 1678 1679 return err; 1680 } 1681 1682 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1683 const unsigned char *addr, u16 vid) 1684 { 1685 struct mv88e6xxx_chip *chip = ds->priv; 1686 int err; 1687 1688 mutex_lock(&chip->reg_lock); 1689 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1690 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1691 mutex_unlock(&chip->reg_lock); 1692 1693 return err; 1694 } 1695 1696 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1697 const unsigned char *addr, u16 vid) 1698 { 1699 struct mv88e6xxx_chip *chip = ds->priv; 1700 int err; 1701 1702 mutex_lock(&chip->reg_lock); 1703 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1704 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1705 mutex_unlock(&chip->reg_lock); 1706 1707 return err; 1708 } 1709 1710 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1711 u16 fid, u16 vid, int port, 1712 dsa_fdb_dump_cb_t *cb, void *data) 1713 { 1714 struct mv88e6xxx_atu_entry addr; 1715 bool is_static; 1716 int err; 1717 1718 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1719 eth_broadcast_addr(addr.mac); 1720 1721 do { 1722 mutex_lock(&chip->reg_lock); 1723 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1724 mutex_unlock(&chip->reg_lock); 1725 if (err) 1726 return err; 1727 1728 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1729 break; 1730 1731 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1732 continue; 1733 1734 if (!is_unicast_ether_addr(addr.mac)) 1735 continue; 1736 1737 is_static = (addr.state == 1738 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1739 err = cb(addr.mac, vid, is_static, data); 1740 if (err) 1741 return err; 1742 } while (!is_broadcast_ether_addr(addr.mac)); 1743 1744 return err; 1745 } 1746 1747 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1748 dsa_fdb_dump_cb_t *cb, void *data) 1749 { 1750 struct mv88e6xxx_vtu_entry vlan = { 1751 .vid = chip->info->max_vid, 1752 }; 1753 u16 fid; 1754 int err; 1755 1756 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1757 mutex_lock(&chip->reg_lock); 1758 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1759 mutex_unlock(&chip->reg_lock); 1760 1761 if (err) 1762 return err; 1763 1764 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1765 if (err) 1766 return err; 1767 1768 /* Dump VLANs' Filtering Information Databases */ 1769 do { 1770 mutex_lock(&chip->reg_lock); 1771 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1772 mutex_unlock(&chip->reg_lock); 1773 if (err) 1774 return err; 1775 1776 if (!vlan.valid) 1777 break; 1778 1779 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1780 cb, data); 1781 if (err) 1782 return err; 1783 } while (vlan.vid < chip->info->max_vid); 1784 1785 return err; 1786 } 1787 1788 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1789 dsa_fdb_dump_cb_t *cb, void *data) 1790 { 1791 struct mv88e6xxx_chip *chip = ds->priv; 1792 1793 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1794 } 1795 1796 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1797 struct net_device *br) 1798 { 1799 struct dsa_switch *ds; 1800 int port; 1801 int dev; 1802 int err; 1803 1804 /* Remap the Port VLAN of each local bridge group member */ 1805 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1806 if (chip->ds->ports[port].bridge_dev == br) { 1807 err = mv88e6xxx_port_vlan_map(chip, port); 1808 if (err) 1809 return err; 1810 } 1811 } 1812 1813 if (!mv88e6xxx_has_pvt(chip)) 1814 return 0; 1815 1816 /* Remap the Port VLAN of each cross-chip bridge group member */ 1817 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1818 ds = chip->ds->dst->ds[dev]; 1819 if (!ds) 1820 break; 1821 1822 for (port = 0; port < ds->num_ports; ++port) { 1823 if (ds->ports[port].bridge_dev == br) { 1824 err = mv88e6xxx_pvt_map(chip, dev, port); 1825 if (err) 1826 return err; 1827 } 1828 } 1829 } 1830 1831 return 0; 1832 } 1833 1834 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1835 struct net_device *br) 1836 { 1837 struct mv88e6xxx_chip *chip = ds->priv; 1838 int err; 1839 1840 mutex_lock(&chip->reg_lock); 1841 err = mv88e6xxx_bridge_map(chip, br); 1842 mutex_unlock(&chip->reg_lock); 1843 1844 return err; 1845 } 1846 1847 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1848 struct net_device *br) 1849 { 1850 struct mv88e6xxx_chip *chip = ds->priv; 1851 1852 mutex_lock(&chip->reg_lock); 1853 if (mv88e6xxx_bridge_map(chip, br) || 1854 mv88e6xxx_port_vlan_map(chip, port)) 1855 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1856 mutex_unlock(&chip->reg_lock); 1857 } 1858 1859 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1860 int port, struct net_device *br) 1861 { 1862 struct mv88e6xxx_chip *chip = ds->priv; 1863 int err; 1864 1865 if (!mv88e6xxx_has_pvt(chip)) 1866 return 0; 1867 1868 mutex_lock(&chip->reg_lock); 1869 err = mv88e6xxx_pvt_map(chip, dev, port); 1870 mutex_unlock(&chip->reg_lock); 1871 1872 return err; 1873 } 1874 1875 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1876 int port, struct net_device *br) 1877 { 1878 struct mv88e6xxx_chip *chip = ds->priv; 1879 1880 if (!mv88e6xxx_has_pvt(chip)) 1881 return; 1882 1883 mutex_lock(&chip->reg_lock); 1884 if (mv88e6xxx_pvt_map(chip, dev, port)) 1885 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1886 mutex_unlock(&chip->reg_lock); 1887 } 1888 1889 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1890 { 1891 if (chip->info->ops->reset) 1892 return chip->info->ops->reset(chip); 1893 1894 return 0; 1895 } 1896 1897 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1898 { 1899 struct gpio_desc *gpiod = chip->reset; 1900 1901 /* If there is a GPIO connected to the reset pin, toggle it */ 1902 if (gpiod) { 1903 gpiod_set_value_cansleep(gpiod, 1); 1904 usleep_range(10000, 20000); 1905 gpiod_set_value_cansleep(gpiod, 0); 1906 usleep_range(10000, 20000); 1907 } 1908 } 1909 1910 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1911 { 1912 int i, err; 1913 1914 /* Set all ports to the Disabled state */ 1915 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1916 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1917 if (err) 1918 return err; 1919 } 1920 1921 /* Wait for transmit queues to drain, 1922 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1923 */ 1924 usleep_range(2000, 4000); 1925 1926 return 0; 1927 } 1928 1929 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1930 { 1931 int err; 1932 1933 err = mv88e6xxx_disable_ports(chip); 1934 if (err) 1935 return err; 1936 1937 mv88e6xxx_hardware_reset(chip); 1938 1939 return mv88e6xxx_software_reset(chip); 1940 } 1941 1942 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1943 enum mv88e6xxx_frame_mode frame, 1944 enum mv88e6xxx_egress_mode egress, u16 etype) 1945 { 1946 int err; 1947 1948 if (!chip->info->ops->port_set_frame_mode) 1949 return -EOPNOTSUPP; 1950 1951 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1952 if (err) 1953 return err; 1954 1955 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1956 if (err) 1957 return err; 1958 1959 if (chip->info->ops->port_set_ether_type) 1960 return chip->info->ops->port_set_ether_type(chip, port, etype); 1961 1962 return 0; 1963 } 1964 1965 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1966 { 1967 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1968 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1969 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1970 } 1971 1972 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1973 { 1974 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1975 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1976 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1977 } 1978 1979 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1980 { 1981 return mv88e6xxx_set_port_mode(chip, port, 1982 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1983 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1984 ETH_P_EDSA); 1985 } 1986 1987 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1988 { 1989 if (dsa_is_dsa_port(chip->ds, port)) 1990 return mv88e6xxx_set_port_mode_dsa(chip, port); 1991 1992 if (dsa_is_user_port(chip->ds, port)) 1993 return mv88e6xxx_set_port_mode_normal(chip, port); 1994 1995 /* Setup CPU port mode depending on its supported tag format */ 1996 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1997 return mv88e6xxx_set_port_mode_dsa(chip, port); 1998 1999 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2000 return mv88e6xxx_set_port_mode_edsa(chip, port); 2001 2002 return -EINVAL; 2003 } 2004 2005 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2006 { 2007 bool message = dsa_is_dsa_port(chip->ds, port); 2008 2009 return mv88e6xxx_port_set_message_port(chip, port, message); 2010 } 2011 2012 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2013 { 2014 struct dsa_switch *ds = chip->ds; 2015 bool flood; 2016 2017 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2018 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2019 if (chip->info->ops->port_set_egress_floods) 2020 return chip->info->ops->port_set_egress_floods(chip, port, 2021 flood, flood); 2022 2023 return 0; 2024 } 2025 2026 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2027 bool on) 2028 { 2029 if (chip->info->ops->serdes_power) 2030 return chip->info->ops->serdes_power(chip, port, on); 2031 2032 return 0; 2033 } 2034 2035 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2036 { 2037 struct dsa_switch *ds = chip->ds; 2038 int upstream_port; 2039 int err; 2040 2041 upstream_port = dsa_upstream_port(ds, port); 2042 if (chip->info->ops->port_set_upstream_port) { 2043 err = chip->info->ops->port_set_upstream_port(chip, port, 2044 upstream_port); 2045 if (err) 2046 return err; 2047 } 2048 2049 if (port == upstream_port) { 2050 if (chip->info->ops->set_cpu_port) { 2051 err = chip->info->ops->set_cpu_port(chip, 2052 upstream_port); 2053 if (err) 2054 return err; 2055 } 2056 2057 if (chip->info->ops->set_egress_port) { 2058 err = chip->info->ops->set_egress_port(chip, 2059 upstream_port); 2060 if (err) 2061 return err; 2062 } 2063 } 2064 2065 return 0; 2066 } 2067 2068 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2069 { 2070 struct dsa_switch *ds = chip->ds; 2071 int err; 2072 u16 reg; 2073 2074 /* MAC Forcing register: don't force link, speed, duplex or flow control 2075 * state to any particular values on physical ports, but force the CPU 2076 * port and all DSA ports to their maximum bandwidth and full duplex. 2077 */ 2078 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2079 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2080 SPEED_MAX, DUPLEX_FULL, 2081 PHY_INTERFACE_MODE_NA); 2082 else 2083 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2084 SPEED_UNFORCED, DUPLEX_UNFORCED, 2085 PHY_INTERFACE_MODE_NA); 2086 if (err) 2087 return err; 2088 2089 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2090 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2091 * tunneling, determine priority by looking at 802.1p and IP 2092 * priority fields (IP prio has precedence), and set STP state 2093 * to Forwarding. 2094 * 2095 * If this is the CPU link, use DSA or EDSA tagging depending 2096 * on which tagging mode was configured. 2097 * 2098 * If this is a link to another switch, use DSA tagging mode. 2099 * 2100 * If this is the upstream port for this switch, enable 2101 * forwarding of unknown unicasts and multicasts. 2102 */ 2103 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2104 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2105 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2106 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2107 if (err) 2108 return err; 2109 2110 err = mv88e6xxx_setup_port_mode(chip, port); 2111 if (err) 2112 return err; 2113 2114 err = mv88e6xxx_setup_egress_floods(chip, port); 2115 if (err) 2116 return err; 2117 2118 /* Enable the SERDES interface for DSA and CPU ports. Normal 2119 * ports SERDES are enabled when the port is enabled, thus 2120 * saving a bit of power. 2121 */ 2122 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2123 err = mv88e6xxx_serdes_power(chip, port, true); 2124 if (err) 2125 return err; 2126 } 2127 2128 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2129 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2130 * untagged frames on this port, do a destination address lookup on all 2131 * received packets as usual, disable ARP mirroring and don't send a 2132 * copy of all transmitted/received frames on this port to the CPU. 2133 */ 2134 err = mv88e6xxx_port_set_map_da(chip, port); 2135 if (err) 2136 return err; 2137 2138 err = mv88e6xxx_setup_upstream_port(chip, port); 2139 if (err) 2140 return err; 2141 2142 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2143 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2144 if (err) 2145 return err; 2146 2147 if (chip->info->ops->port_set_jumbo_size) { 2148 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2149 if (err) 2150 return err; 2151 } 2152 2153 /* Port Association Vector: when learning source addresses 2154 * of packets, add the address to the address database using 2155 * a port bitmap that has only the bit for this port set and 2156 * the other bits clear. 2157 */ 2158 reg = 1 << port; 2159 /* Disable learning for CPU port */ 2160 if (dsa_is_cpu_port(ds, port)) 2161 reg = 0; 2162 2163 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2164 reg); 2165 if (err) 2166 return err; 2167 2168 /* Egress rate control 2: disable egress rate control. */ 2169 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2170 0x0000); 2171 if (err) 2172 return err; 2173 2174 if (chip->info->ops->port_pause_limit) { 2175 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2176 if (err) 2177 return err; 2178 } 2179 2180 if (chip->info->ops->port_disable_learn_limit) { 2181 err = chip->info->ops->port_disable_learn_limit(chip, port); 2182 if (err) 2183 return err; 2184 } 2185 2186 if (chip->info->ops->port_disable_pri_override) { 2187 err = chip->info->ops->port_disable_pri_override(chip, port); 2188 if (err) 2189 return err; 2190 } 2191 2192 if (chip->info->ops->port_tag_remap) { 2193 err = chip->info->ops->port_tag_remap(chip, port); 2194 if (err) 2195 return err; 2196 } 2197 2198 if (chip->info->ops->port_egress_rate_limiting) { 2199 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2200 if (err) 2201 return err; 2202 } 2203 2204 err = mv88e6xxx_setup_message_port(chip, port); 2205 if (err) 2206 return err; 2207 2208 /* Port based VLAN map: give each port the same default address 2209 * database, and allow bidirectional communication between the 2210 * CPU and DSA port(s), and the other ports. 2211 */ 2212 err = mv88e6xxx_port_set_fid(chip, port, 0); 2213 if (err) 2214 return err; 2215 2216 err = mv88e6xxx_port_vlan_map(chip, port); 2217 if (err) 2218 return err; 2219 2220 /* Default VLAN ID and priority: don't set a default VLAN 2221 * ID, and set the default packet priority to zero. 2222 */ 2223 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2224 } 2225 2226 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2227 struct phy_device *phydev) 2228 { 2229 struct mv88e6xxx_chip *chip = ds->priv; 2230 int err; 2231 2232 mutex_lock(&chip->reg_lock); 2233 err = mv88e6xxx_serdes_power(chip, port, true); 2234 mutex_unlock(&chip->reg_lock); 2235 2236 return err; 2237 } 2238 2239 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 2240 struct phy_device *phydev) 2241 { 2242 struct mv88e6xxx_chip *chip = ds->priv; 2243 2244 mutex_lock(&chip->reg_lock); 2245 if (mv88e6xxx_serdes_power(chip, port, false)) 2246 dev_err(chip->dev, "failed to power off SERDES\n"); 2247 mutex_unlock(&chip->reg_lock); 2248 } 2249 2250 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2251 unsigned int ageing_time) 2252 { 2253 struct mv88e6xxx_chip *chip = ds->priv; 2254 int err; 2255 2256 mutex_lock(&chip->reg_lock); 2257 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2258 mutex_unlock(&chip->reg_lock); 2259 2260 return err; 2261 } 2262 2263 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2264 { 2265 int err; 2266 2267 /* Initialize the statistics unit */ 2268 if (chip->info->ops->stats_set_histogram) { 2269 err = chip->info->ops->stats_set_histogram(chip); 2270 if (err) 2271 return err; 2272 } 2273 2274 return mv88e6xxx_g1_stats_clear(chip); 2275 } 2276 2277 static int mv88e6xxx_setup(struct dsa_switch *ds) 2278 { 2279 struct mv88e6xxx_chip *chip = ds->priv; 2280 int err; 2281 int i; 2282 2283 chip->ds = ds; 2284 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2285 2286 mutex_lock(&chip->reg_lock); 2287 2288 /* Setup Switch Port Registers */ 2289 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2290 if (dsa_is_unused_port(ds, i)) 2291 continue; 2292 2293 err = mv88e6xxx_setup_port(chip, i); 2294 if (err) 2295 goto unlock; 2296 } 2297 2298 err = mv88e6xxx_irl_setup(chip); 2299 if (err) 2300 goto unlock; 2301 2302 err = mv88e6xxx_mac_setup(chip); 2303 if (err) 2304 goto unlock; 2305 2306 err = mv88e6xxx_phy_setup(chip); 2307 if (err) 2308 goto unlock; 2309 2310 err = mv88e6xxx_vtu_setup(chip); 2311 if (err) 2312 goto unlock; 2313 2314 err = mv88e6xxx_pvt_setup(chip); 2315 if (err) 2316 goto unlock; 2317 2318 err = mv88e6xxx_atu_setup(chip); 2319 if (err) 2320 goto unlock; 2321 2322 err = mv88e6xxx_broadcast_setup(chip, 0); 2323 if (err) 2324 goto unlock; 2325 2326 err = mv88e6xxx_pot_setup(chip); 2327 if (err) 2328 goto unlock; 2329 2330 err = mv88e6xxx_rmu_setup(chip); 2331 if (err) 2332 goto unlock; 2333 2334 err = mv88e6xxx_rsvd2cpu_setup(chip); 2335 if (err) 2336 goto unlock; 2337 2338 err = mv88e6xxx_trunk_setup(chip); 2339 if (err) 2340 goto unlock; 2341 2342 err = mv88e6xxx_devmap_setup(chip); 2343 if (err) 2344 goto unlock; 2345 2346 err = mv88e6xxx_pri_setup(chip); 2347 if (err) 2348 goto unlock; 2349 2350 /* Setup PTP Hardware Clock and timestamping */ 2351 if (chip->info->ptp_support) { 2352 err = mv88e6xxx_ptp_setup(chip); 2353 if (err) 2354 goto unlock; 2355 2356 err = mv88e6xxx_hwtstamp_setup(chip); 2357 if (err) 2358 goto unlock; 2359 } 2360 2361 err = mv88e6xxx_stats_setup(chip); 2362 if (err) 2363 goto unlock; 2364 2365 unlock: 2366 mutex_unlock(&chip->reg_lock); 2367 2368 return err; 2369 } 2370 2371 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2372 { 2373 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2374 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2375 u16 val; 2376 int err; 2377 2378 if (!chip->info->ops->phy_read) 2379 return -EOPNOTSUPP; 2380 2381 mutex_lock(&chip->reg_lock); 2382 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2383 mutex_unlock(&chip->reg_lock); 2384 2385 if (reg == MII_PHYSID2) { 2386 /* Some internal PHYS don't have a model number. Use 2387 * the mv88e6390 family model number instead. 2388 */ 2389 if (!(val & 0x3f0)) 2390 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2391 } 2392 2393 return err ? err : val; 2394 } 2395 2396 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2397 { 2398 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2399 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2400 int err; 2401 2402 if (!chip->info->ops->phy_write) 2403 return -EOPNOTSUPP; 2404 2405 mutex_lock(&chip->reg_lock); 2406 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2407 mutex_unlock(&chip->reg_lock); 2408 2409 return err; 2410 } 2411 2412 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2413 struct device_node *np, 2414 bool external) 2415 { 2416 static int index; 2417 struct mv88e6xxx_mdio_bus *mdio_bus; 2418 struct mii_bus *bus; 2419 int err; 2420 2421 if (external) { 2422 mutex_lock(&chip->reg_lock); 2423 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2424 mutex_unlock(&chip->reg_lock); 2425 2426 if (err) 2427 return err; 2428 } 2429 2430 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2431 if (!bus) 2432 return -ENOMEM; 2433 2434 mdio_bus = bus->priv; 2435 mdio_bus->bus = bus; 2436 mdio_bus->chip = chip; 2437 INIT_LIST_HEAD(&mdio_bus->list); 2438 mdio_bus->external = external; 2439 2440 if (np) { 2441 bus->name = np->full_name; 2442 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2443 } else { 2444 bus->name = "mv88e6xxx SMI"; 2445 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2446 } 2447 2448 bus->read = mv88e6xxx_mdio_read; 2449 bus->write = mv88e6xxx_mdio_write; 2450 bus->parent = chip->dev; 2451 2452 if (!external) { 2453 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2454 if (err) 2455 return err; 2456 } 2457 2458 err = of_mdiobus_register(bus, np); 2459 if (err) { 2460 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2461 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2462 return err; 2463 } 2464 2465 if (external) 2466 list_add_tail(&mdio_bus->list, &chip->mdios); 2467 else 2468 list_add(&mdio_bus->list, &chip->mdios); 2469 2470 return 0; 2471 } 2472 2473 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2474 { .compatible = "marvell,mv88e6xxx-mdio-external", 2475 .data = (void *)true }, 2476 { }, 2477 }; 2478 2479 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2480 2481 { 2482 struct mv88e6xxx_mdio_bus *mdio_bus; 2483 struct mii_bus *bus; 2484 2485 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2486 bus = mdio_bus->bus; 2487 2488 if (!mdio_bus->external) 2489 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2490 2491 mdiobus_unregister(bus); 2492 } 2493 } 2494 2495 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2496 struct device_node *np) 2497 { 2498 const struct of_device_id *match; 2499 struct device_node *child; 2500 int err; 2501 2502 /* Always register one mdio bus for the internal/default mdio 2503 * bus. This maybe represented in the device tree, but is 2504 * optional. 2505 */ 2506 child = of_get_child_by_name(np, "mdio"); 2507 err = mv88e6xxx_mdio_register(chip, child, false); 2508 if (err) 2509 return err; 2510 2511 /* Walk the device tree, and see if there are any other nodes 2512 * which say they are compatible with the external mdio 2513 * bus. 2514 */ 2515 for_each_available_child_of_node(np, child) { 2516 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2517 if (match) { 2518 err = mv88e6xxx_mdio_register(chip, child, true); 2519 if (err) { 2520 mv88e6xxx_mdios_unregister(chip); 2521 return err; 2522 } 2523 } 2524 } 2525 2526 return 0; 2527 } 2528 2529 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2530 { 2531 struct mv88e6xxx_chip *chip = ds->priv; 2532 2533 return chip->eeprom_len; 2534 } 2535 2536 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2537 struct ethtool_eeprom *eeprom, u8 *data) 2538 { 2539 struct mv88e6xxx_chip *chip = ds->priv; 2540 int err; 2541 2542 if (!chip->info->ops->get_eeprom) 2543 return -EOPNOTSUPP; 2544 2545 mutex_lock(&chip->reg_lock); 2546 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2547 mutex_unlock(&chip->reg_lock); 2548 2549 if (err) 2550 return err; 2551 2552 eeprom->magic = 0xc3ec4951; 2553 2554 return 0; 2555 } 2556 2557 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2558 struct ethtool_eeprom *eeprom, u8 *data) 2559 { 2560 struct mv88e6xxx_chip *chip = ds->priv; 2561 int err; 2562 2563 if (!chip->info->ops->set_eeprom) 2564 return -EOPNOTSUPP; 2565 2566 if (eeprom->magic != 0xc3ec4951) 2567 return -EINVAL; 2568 2569 mutex_lock(&chip->reg_lock); 2570 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2571 mutex_unlock(&chip->reg_lock); 2572 2573 return err; 2574 } 2575 2576 static const struct mv88e6xxx_ops mv88e6085_ops = { 2577 /* MV88E6XXX_FAMILY_6097 */ 2578 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2579 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2580 .irl_init_all = mv88e6352_g2_irl_init_all, 2581 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2582 .phy_read = mv88e6185_phy_ppu_read, 2583 .phy_write = mv88e6185_phy_ppu_write, 2584 .port_set_link = mv88e6xxx_port_set_link, 2585 .port_set_duplex = mv88e6xxx_port_set_duplex, 2586 .port_set_speed = mv88e6185_port_set_speed, 2587 .port_tag_remap = mv88e6095_port_tag_remap, 2588 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2589 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2590 .port_set_ether_type = mv88e6351_port_set_ether_type, 2591 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2592 .port_pause_limit = mv88e6097_port_pause_limit, 2593 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2594 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2595 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2596 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2597 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2598 .stats_get_strings = mv88e6095_stats_get_strings, 2599 .stats_get_stats = mv88e6095_stats_get_stats, 2600 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2601 .set_egress_port = mv88e6095_g1_set_egress_port, 2602 .watchdog_ops = &mv88e6097_watchdog_ops, 2603 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2604 .pot_clear = mv88e6xxx_g2_pot_clear, 2605 .ppu_enable = mv88e6185_g1_ppu_enable, 2606 .ppu_disable = mv88e6185_g1_ppu_disable, 2607 .reset = mv88e6185_g1_reset, 2608 .rmu_disable = mv88e6085_g1_rmu_disable, 2609 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2610 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2611 .serdes_power = mv88e6341_serdes_power, 2612 }; 2613 2614 static const struct mv88e6xxx_ops mv88e6095_ops = { 2615 /* MV88E6XXX_FAMILY_6095 */ 2616 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2617 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2618 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2619 .phy_read = mv88e6185_phy_ppu_read, 2620 .phy_write = mv88e6185_phy_ppu_write, 2621 .port_set_link = mv88e6xxx_port_set_link, 2622 .port_set_duplex = mv88e6xxx_port_set_duplex, 2623 .port_set_speed = mv88e6185_port_set_speed, 2624 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2625 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2626 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2627 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2628 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2629 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2630 .stats_get_strings = mv88e6095_stats_get_strings, 2631 .stats_get_stats = mv88e6095_stats_get_stats, 2632 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2633 .ppu_enable = mv88e6185_g1_ppu_enable, 2634 .ppu_disable = mv88e6185_g1_ppu_disable, 2635 .reset = mv88e6185_g1_reset, 2636 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2637 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2638 }; 2639 2640 static const struct mv88e6xxx_ops mv88e6097_ops = { 2641 /* MV88E6XXX_FAMILY_6097 */ 2642 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2643 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2644 .irl_init_all = mv88e6352_g2_irl_init_all, 2645 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2646 .phy_read = mv88e6xxx_g2_smi_phy_read, 2647 .phy_write = mv88e6xxx_g2_smi_phy_write, 2648 .port_set_link = mv88e6xxx_port_set_link, 2649 .port_set_duplex = mv88e6xxx_port_set_duplex, 2650 .port_set_speed = mv88e6185_port_set_speed, 2651 .port_tag_remap = mv88e6095_port_tag_remap, 2652 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2653 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2654 .port_set_ether_type = mv88e6351_port_set_ether_type, 2655 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2656 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2657 .port_pause_limit = mv88e6097_port_pause_limit, 2658 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2659 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2660 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2661 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2662 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2663 .stats_get_strings = mv88e6095_stats_get_strings, 2664 .stats_get_stats = mv88e6095_stats_get_stats, 2665 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2666 .set_egress_port = mv88e6095_g1_set_egress_port, 2667 .watchdog_ops = &mv88e6097_watchdog_ops, 2668 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2669 .pot_clear = mv88e6xxx_g2_pot_clear, 2670 .reset = mv88e6352_g1_reset, 2671 .rmu_disable = mv88e6085_g1_rmu_disable, 2672 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2673 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2674 }; 2675 2676 static const struct mv88e6xxx_ops mv88e6123_ops = { 2677 /* MV88E6XXX_FAMILY_6165 */ 2678 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2679 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2680 .irl_init_all = mv88e6352_g2_irl_init_all, 2681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2682 .phy_read = mv88e6xxx_g2_smi_phy_read, 2683 .phy_write = mv88e6xxx_g2_smi_phy_write, 2684 .port_set_link = mv88e6xxx_port_set_link, 2685 .port_set_duplex = mv88e6xxx_port_set_duplex, 2686 .port_set_speed = mv88e6185_port_set_speed, 2687 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2688 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2689 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2690 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2691 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2692 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2693 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2694 .stats_get_strings = mv88e6095_stats_get_strings, 2695 .stats_get_stats = mv88e6095_stats_get_stats, 2696 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2697 .set_egress_port = mv88e6095_g1_set_egress_port, 2698 .watchdog_ops = &mv88e6097_watchdog_ops, 2699 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2700 .pot_clear = mv88e6xxx_g2_pot_clear, 2701 .reset = mv88e6352_g1_reset, 2702 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2703 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2704 }; 2705 2706 static const struct mv88e6xxx_ops mv88e6131_ops = { 2707 /* MV88E6XXX_FAMILY_6185 */ 2708 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2709 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2710 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2711 .phy_read = mv88e6185_phy_ppu_read, 2712 .phy_write = mv88e6185_phy_ppu_write, 2713 .port_set_link = mv88e6xxx_port_set_link, 2714 .port_set_duplex = mv88e6xxx_port_set_duplex, 2715 .port_set_speed = mv88e6185_port_set_speed, 2716 .port_tag_remap = mv88e6095_port_tag_remap, 2717 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2718 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2719 .port_set_ether_type = mv88e6351_port_set_ether_type, 2720 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2721 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2722 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2723 .port_pause_limit = mv88e6097_port_pause_limit, 2724 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2725 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2726 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2727 .stats_get_strings = mv88e6095_stats_get_strings, 2728 .stats_get_stats = mv88e6095_stats_get_stats, 2729 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2730 .set_egress_port = mv88e6095_g1_set_egress_port, 2731 .watchdog_ops = &mv88e6097_watchdog_ops, 2732 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2733 .ppu_enable = mv88e6185_g1_ppu_enable, 2734 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2735 .ppu_disable = mv88e6185_g1_ppu_disable, 2736 .reset = mv88e6185_g1_reset, 2737 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2738 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2739 }; 2740 2741 static const struct mv88e6xxx_ops mv88e6141_ops = { 2742 /* MV88E6XXX_FAMILY_6341 */ 2743 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2744 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2745 .irl_init_all = mv88e6352_g2_irl_init_all, 2746 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2747 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2748 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2749 .phy_read = mv88e6xxx_g2_smi_phy_read, 2750 .phy_write = mv88e6xxx_g2_smi_phy_write, 2751 .port_set_link = mv88e6xxx_port_set_link, 2752 .port_set_duplex = mv88e6xxx_port_set_duplex, 2753 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2754 .port_set_speed = mv88e6390_port_set_speed, 2755 .port_tag_remap = mv88e6095_port_tag_remap, 2756 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2757 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2758 .port_set_ether_type = mv88e6351_port_set_ether_type, 2759 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2760 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2761 .port_pause_limit = mv88e6097_port_pause_limit, 2762 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2763 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2764 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2765 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2766 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2767 .stats_get_strings = mv88e6320_stats_get_strings, 2768 .stats_get_stats = mv88e6390_stats_get_stats, 2769 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2770 .set_egress_port = mv88e6390_g1_set_egress_port, 2771 .watchdog_ops = &mv88e6390_watchdog_ops, 2772 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2773 .pot_clear = mv88e6xxx_g2_pot_clear, 2774 .reset = mv88e6352_g1_reset, 2775 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2776 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2777 .gpio_ops = &mv88e6352_gpio_ops, 2778 }; 2779 2780 static const struct mv88e6xxx_ops mv88e6161_ops = { 2781 /* MV88E6XXX_FAMILY_6165 */ 2782 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2783 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2784 .irl_init_all = mv88e6352_g2_irl_init_all, 2785 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2786 .phy_read = mv88e6xxx_g2_smi_phy_read, 2787 .phy_write = mv88e6xxx_g2_smi_phy_write, 2788 .port_set_link = mv88e6xxx_port_set_link, 2789 .port_set_duplex = mv88e6xxx_port_set_duplex, 2790 .port_set_speed = mv88e6185_port_set_speed, 2791 .port_tag_remap = mv88e6095_port_tag_remap, 2792 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2793 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2794 .port_set_ether_type = mv88e6351_port_set_ether_type, 2795 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2796 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2797 .port_pause_limit = mv88e6097_port_pause_limit, 2798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2800 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2801 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2802 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2803 .stats_get_strings = mv88e6095_stats_get_strings, 2804 .stats_get_stats = mv88e6095_stats_get_stats, 2805 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2806 .set_egress_port = mv88e6095_g1_set_egress_port, 2807 .watchdog_ops = &mv88e6097_watchdog_ops, 2808 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2809 .pot_clear = mv88e6xxx_g2_pot_clear, 2810 .reset = mv88e6352_g1_reset, 2811 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2812 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2813 .avb_ops = &mv88e6165_avb_ops, 2814 .ptp_ops = &mv88e6165_ptp_ops, 2815 }; 2816 2817 static const struct mv88e6xxx_ops mv88e6165_ops = { 2818 /* MV88E6XXX_FAMILY_6165 */ 2819 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2820 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2821 .irl_init_all = mv88e6352_g2_irl_init_all, 2822 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2823 .phy_read = mv88e6165_phy_read, 2824 .phy_write = mv88e6165_phy_write, 2825 .port_set_link = mv88e6xxx_port_set_link, 2826 .port_set_duplex = mv88e6xxx_port_set_duplex, 2827 .port_set_speed = mv88e6185_port_set_speed, 2828 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2829 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2830 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2831 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2832 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2833 .stats_get_strings = mv88e6095_stats_get_strings, 2834 .stats_get_stats = mv88e6095_stats_get_stats, 2835 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2836 .set_egress_port = mv88e6095_g1_set_egress_port, 2837 .watchdog_ops = &mv88e6097_watchdog_ops, 2838 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2839 .pot_clear = mv88e6xxx_g2_pot_clear, 2840 .reset = mv88e6352_g1_reset, 2841 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2842 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2843 .avb_ops = &mv88e6165_avb_ops, 2844 .ptp_ops = &mv88e6165_ptp_ops, 2845 }; 2846 2847 static const struct mv88e6xxx_ops mv88e6171_ops = { 2848 /* MV88E6XXX_FAMILY_6351 */ 2849 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2850 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2851 .irl_init_all = mv88e6352_g2_irl_init_all, 2852 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2853 .phy_read = mv88e6xxx_g2_smi_phy_read, 2854 .phy_write = mv88e6xxx_g2_smi_phy_write, 2855 .port_set_link = mv88e6xxx_port_set_link, 2856 .port_set_duplex = mv88e6xxx_port_set_duplex, 2857 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2858 .port_set_speed = mv88e6185_port_set_speed, 2859 .port_tag_remap = mv88e6095_port_tag_remap, 2860 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2861 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2862 .port_set_ether_type = mv88e6351_port_set_ether_type, 2863 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2864 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2865 .port_pause_limit = mv88e6097_port_pause_limit, 2866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2868 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2869 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2870 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2871 .stats_get_strings = mv88e6095_stats_get_strings, 2872 .stats_get_stats = mv88e6095_stats_get_stats, 2873 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2874 .set_egress_port = mv88e6095_g1_set_egress_port, 2875 .watchdog_ops = &mv88e6097_watchdog_ops, 2876 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2877 .pot_clear = mv88e6xxx_g2_pot_clear, 2878 .reset = mv88e6352_g1_reset, 2879 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2880 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2881 }; 2882 2883 static const struct mv88e6xxx_ops mv88e6172_ops = { 2884 /* MV88E6XXX_FAMILY_6352 */ 2885 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2886 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2887 .irl_init_all = mv88e6352_g2_irl_init_all, 2888 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2889 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2890 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2891 .phy_read = mv88e6xxx_g2_smi_phy_read, 2892 .phy_write = mv88e6xxx_g2_smi_phy_write, 2893 .port_set_link = mv88e6xxx_port_set_link, 2894 .port_set_duplex = mv88e6xxx_port_set_duplex, 2895 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2896 .port_set_speed = mv88e6352_port_set_speed, 2897 .port_tag_remap = mv88e6095_port_tag_remap, 2898 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2899 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2900 .port_set_ether_type = mv88e6351_port_set_ether_type, 2901 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2902 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2903 .port_pause_limit = mv88e6097_port_pause_limit, 2904 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2905 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2906 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2907 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2908 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2909 .stats_get_strings = mv88e6095_stats_get_strings, 2910 .stats_get_stats = mv88e6095_stats_get_stats, 2911 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2912 .set_egress_port = mv88e6095_g1_set_egress_port, 2913 .watchdog_ops = &mv88e6097_watchdog_ops, 2914 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2915 .pot_clear = mv88e6xxx_g2_pot_clear, 2916 .reset = mv88e6352_g1_reset, 2917 .rmu_disable = mv88e6352_g1_rmu_disable, 2918 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2919 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2920 .serdes_power = mv88e6352_serdes_power, 2921 .gpio_ops = &mv88e6352_gpio_ops, 2922 }; 2923 2924 static const struct mv88e6xxx_ops mv88e6175_ops = { 2925 /* MV88E6XXX_FAMILY_6351 */ 2926 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2927 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2928 .irl_init_all = mv88e6352_g2_irl_init_all, 2929 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2930 .phy_read = mv88e6xxx_g2_smi_phy_read, 2931 .phy_write = mv88e6xxx_g2_smi_phy_write, 2932 .port_set_link = mv88e6xxx_port_set_link, 2933 .port_set_duplex = mv88e6xxx_port_set_duplex, 2934 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2935 .port_set_speed = mv88e6185_port_set_speed, 2936 .port_tag_remap = mv88e6095_port_tag_remap, 2937 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2938 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2939 .port_set_ether_type = mv88e6351_port_set_ether_type, 2940 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2941 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2942 .port_pause_limit = mv88e6097_port_pause_limit, 2943 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2944 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2945 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2946 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2947 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2948 .stats_get_strings = mv88e6095_stats_get_strings, 2949 .stats_get_stats = mv88e6095_stats_get_stats, 2950 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2951 .set_egress_port = mv88e6095_g1_set_egress_port, 2952 .watchdog_ops = &mv88e6097_watchdog_ops, 2953 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2954 .pot_clear = mv88e6xxx_g2_pot_clear, 2955 .reset = mv88e6352_g1_reset, 2956 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2957 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2958 .serdes_power = mv88e6341_serdes_power, 2959 }; 2960 2961 static const struct mv88e6xxx_ops mv88e6176_ops = { 2962 /* MV88E6XXX_FAMILY_6352 */ 2963 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2964 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2965 .irl_init_all = mv88e6352_g2_irl_init_all, 2966 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2967 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2968 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2969 .phy_read = mv88e6xxx_g2_smi_phy_read, 2970 .phy_write = mv88e6xxx_g2_smi_phy_write, 2971 .port_set_link = mv88e6xxx_port_set_link, 2972 .port_set_duplex = mv88e6xxx_port_set_duplex, 2973 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2974 .port_set_speed = mv88e6352_port_set_speed, 2975 .port_tag_remap = mv88e6095_port_tag_remap, 2976 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2977 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2978 .port_set_ether_type = mv88e6351_port_set_ether_type, 2979 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2980 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2981 .port_pause_limit = mv88e6097_port_pause_limit, 2982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2984 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2985 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2986 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2987 .stats_get_strings = mv88e6095_stats_get_strings, 2988 .stats_get_stats = mv88e6095_stats_get_stats, 2989 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2990 .set_egress_port = mv88e6095_g1_set_egress_port, 2991 .watchdog_ops = &mv88e6097_watchdog_ops, 2992 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2993 .pot_clear = mv88e6xxx_g2_pot_clear, 2994 .reset = mv88e6352_g1_reset, 2995 .rmu_disable = mv88e6352_g1_rmu_disable, 2996 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2997 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2998 .serdes_power = mv88e6352_serdes_power, 2999 .gpio_ops = &mv88e6352_gpio_ops, 3000 }; 3001 3002 static const struct mv88e6xxx_ops mv88e6185_ops = { 3003 /* MV88E6XXX_FAMILY_6185 */ 3004 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3005 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3006 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3007 .phy_read = mv88e6185_phy_ppu_read, 3008 .phy_write = mv88e6185_phy_ppu_write, 3009 .port_set_link = mv88e6xxx_port_set_link, 3010 .port_set_duplex = mv88e6xxx_port_set_duplex, 3011 .port_set_speed = mv88e6185_port_set_speed, 3012 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3013 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3014 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3015 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3016 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3017 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3018 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3019 .stats_get_strings = mv88e6095_stats_get_strings, 3020 .stats_get_stats = mv88e6095_stats_get_stats, 3021 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3022 .set_egress_port = mv88e6095_g1_set_egress_port, 3023 .watchdog_ops = &mv88e6097_watchdog_ops, 3024 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3025 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3026 .ppu_enable = mv88e6185_g1_ppu_enable, 3027 .ppu_disable = mv88e6185_g1_ppu_disable, 3028 .reset = mv88e6185_g1_reset, 3029 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3030 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3031 }; 3032 3033 static const struct mv88e6xxx_ops mv88e6190_ops = { 3034 /* MV88E6XXX_FAMILY_6390 */ 3035 .irl_init_all = mv88e6390_g2_irl_init_all, 3036 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3037 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3038 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3039 .phy_read = mv88e6xxx_g2_smi_phy_read, 3040 .phy_write = mv88e6xxx_g2_smi_phy_write, 3041 .port_set_link = mv88e6xxx_port_set_link, 3042 .port_set_duplex = mv88e6xxx_port_set_duplex, 3043 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3044 .port_set_speed = mv88e6390_port_set_speed, 3045 .port_tag_remap = mv88e6390_port_tag_remap, 3046 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3047 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3048 .port_set_ether_type = mv88e6351_port_set_ether_type, 3049 .port_pause_limit = mv88e6390_port_pause_limit, 3050 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3051 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3052 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3053 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3054 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3055 .stats_get_strings = mv88e6320_stats_get_strings, 3056 .stats_get_stats = mv88e6390_stats_get_stats, 3057 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3058 .set_egress_port = mv88e6390_g1_set_egress_port, 3059 .watchdog_ops = &mv88e6390_watchdog_ops, 3060 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3061 .pot_clear = mv88e6xxx_g2_pot_clear, 3062 .reset = mv88e6352_g1_reset, 3063 .rmu_disable = mv88e6390_g1_rmu_disable, 3064 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3065 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3066 .serdes_power = mv88e6390_serdes_power, 3067 .gpio_ops = &mv88e6352_gpio_ops, 3068 }; 3069 3070 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3071 /* MV88E6XXX_FAMILY_6390 */ 3072 .irl_init_all = mv88e6390_g2_irl_init_all, 3073 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3074 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3075 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3076 .phy_read = mv88e6xxx_g2_smi_phy_read, 3077 .phy_write = mv88e6xxx_g2_smi_phy_write, 3078 .port_set_link = mv88e6xxx_port_set_link, 3079 .port_set_duplex = mv88e6xxx_port_set_duplex, 3080 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3081 .port_set_speed = mv88e6390x_port_set_speed, 3082 .port_tag_remap = mv88e6390_port_tag_remap, 3083 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3084 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3085 .port_set_ether_type = mv88e6351_port_set_ether_type, 3086 .port_pause_limit = mv88e6390_port_pause_limit, 3087 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3088 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3089 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3090 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3091 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3092 .stats_get_strings = mv88e6320_stats_get_strings, 3093 .stats_get_stats = mv88e6390_stats_get_stats, 3094 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3095 .set_egress_port = mv88e6390_g1_set_egress_port, 3096 .watchdog_ops = &mv88e6390_watchdog_ops, 3097 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3098 .pot_clear = mv88e6xxx_g2_pot_clear, 3099 .reset = mv88e6352_g1_reset, 3100 .rmu_disable = mv88e6390_g1_rmu_disable, 3101 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3102 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3103 .serdes_power = mv88e6390_serdes_power, 3104 .gpio_ops = &mv88e6352_gpio_ops, 3105 }; 3106 3107 static const struct mv88e6xxx_ops mv88e6191_ops = { 3108 /* MV88E6XXX_FAMILY_6390 */ 3109 .irl_init_all = mv88e6390_g2_irl_init_all, 3110 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3111 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3112 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3113 .phy_read = mv88e6xxx_g2_smi_phy_read, 3114 .phy_write = mv88e6xxx_g2_smi_phy_write, 3115 .port_set_link = mv88e6xxx_port_set_link, 3116 .port_set_duplex = mv88e6xxx_port_set_duplex, 3117 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3118 .port_set_speed = mv88e6390_port_set_speed, 3119 .port_tag_remap = mv88e6390_port_tag_remap, 3120 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3121 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3122 .port_set_ether_type = mv88e6351_port_set_ether_type, 3123 .port_pause_limit = mv88e6390_port_pause_limit, 3124 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3125 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3126 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3127 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3128 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3129 .stats_get_strings = mv88e6320_stats_get_strings, 3130 .stats_get_stats = mv88e6390_stats_get_stats, 3131 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3132 .set_egress_port = mv88e6390_g1_set_egress_port, 3133 .watchdog_ops = &mv88e6390_watchdog_ops, 3134 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3135 .pot_clear = mv88e6xxx_g2_pot_clear, 3136 .reset = mv88e6352_g1_reset, 3137 .rmu_disable = mv88e6390_g1_rmu_disable, 3138 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3139 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3140 .serdes_power = mv88e6390_serdes_power, 3141 .avb_ops = &mv88e6390_avb_ops, 3142 .ptp_ops = &mv88e6352_ptp_ops, 3143 }; 3144 3145 static const struct mv88e6xxx_ops mv88e6240_ops = { 3146 /* MV88E6XXX_FAMILY_6352 */ 3147 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3148 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3149 .irl_init_all = mv88e6352_g2_irl_init_all, 3150 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3151 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3152 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3153 .phy_read = mv88e6xxx_g2_smi_phy_read, 3154 .phy_write = mv88e6xxx_g2_smi_phy_write, 3155 .port_set_link = mv88e6xxx_port_set_link, 3156 .port_set_duplex = mv88e6xxx_port_set_duplex, 3157 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3158 .port_set_speed = mv88e6352_port_set_speed, 3159 .port_tag_remap = mv88e6095_port_tag_remap, 3160 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3161 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3162 .port_set_ether_type = mv88e6351_port_set_ether_type, 3163 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3164 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3165 .port_pause_limit = mv88e6097_port_pause_limit, 3166 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3167 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3168 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3169 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3170 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3171 .stats_get_strings = mv88e6095_stats_get_strings, 3172 .stats_get_stats = mv88e6095_stats_get_stats, 3173 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3174 .set_egress_port = mv88e6095_g1_set_egress_port, 3175 .watchdog_ops = &mv88e6097_watchdog_ops, 3176 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3177 .pot_clear = mv88e6xxx_g2_pot_clear, 3178 .reset = mv88e6352_g1_reset, 3179 .rmu_disable = mv88e6352_g1_rmu_disable, 3180 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3181 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3182 .serdes_power = mv88e6352_serdes_power, 3183 .gpio_ops = &mv88e6352_gpio_ops, 3184 .avb_ops = &mv88e6352_avb_ops, 3185 .ptp_ops = &mv88e6352_ptp_ops, 3186 }; 3187 3188 static const struct mv88e6xxx_ops mv88e6290_ops = { 3189 /* MV88E6XXX_FAMILY_6390 */ 3190 .irl_init_all = mv88e6390_g2_irl_init_all, 3191 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3192 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3193 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3194 .phy_read = mv88e6xxx_g2_smi_phy_read, 3195 .phy_write = mv88e6xxx_g2_smi_phy_write, 3196 .port_set_link = mv88e6xxx_port_set_link, 3197 .port_set_duplex = mv88e6xxx_port_set_duplex, 3198 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3199 .port_set_speed = mv88e6390_port_set_speed, 3200 .port_tag_remap = mv88e6390_port_tag_remap, 3201 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3202 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3203 .port_set_ether_type = mv88e6351_port_set_ether_type, 3204 .port_pause_limit = mv88e6390_port_pause_limit, 3205 .port_set_cmode = mv88e6390x_port_set_cmode, 3206 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3207 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3208 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3209 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3210 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3211 .stats_get_strings = mv88e6320_stats_get_strings, 3212 .stats_get_stats = mv88e6390_stats_get_stats, 3213 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3214 .set_egress_port = mv88e6390_g1_set_egress_port, 3215 .watchdog_ops = &mv88e6390_watchdog_ops, 3216 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3217 .pot_clear = mv88e6xxx_g2_pot_clear, 3218 .reset = mv88e6352_g1_reset, 3219 .rmu_disable = mv88e6390_g1_rmu_disable, 3220 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3221 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3222 .serdes_power = mv88e6390_serdes_power, 3223 .gpio_ops = &mv88e6352_gpio_ops, 3224 .avb_ops = &mv88e6390_avb_ops, 3225 .ptp_ops = &mv88e6352_ptp_ops, 3226 }; 3227 3228 static const struct mv88e6xxx_ops mv88e6320_ops = { 3229 /* MV88E6XXX_FAMILY_6320 */ 3230 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3231 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3232 .irl_init_all = mv88e6352_g2_irl_init_all, 3233 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3234 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3235 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3236 .phy_read = mv88e6xxx_g2_smi_phy_read, 3237 .phy_write = mv88e6xxx_g2_smi_phy_write, 3238 .port_set_link = mv88e6xxx_port_set_link, 3239 .port_set_duplex = mv88e6xxx_port_set_duplex, 3240 .port_set_speed = mv88e6185_port_set_speed, 3241 .port_tag_remap = mv88e6095_port_tag_remap, 3242 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3243 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3244 .port_set_ether_type = mv88e6351_port_set_ether_type, 3245 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3246 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3247 .port_pause_limit = mv88e6097_port_pause_limit, 3248 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3249 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3250 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3251 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3252 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3253 .stats_get_strings = mv88e6320_stats_get_strings, 3254 .stats_get_stats = mv88e6320_stats_get_stats, 3255 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3256 .set_egress_port = mv88e6095_g1_set_egress_port, 3257 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3258 .pot_clear = mv88e6xxx_g2_pot_clear, 3259 .reset = mv88e6352_g1_reset, 3260 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3261 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3262 .gpio_ops = &mv88e6352_gpio_ops, 3263 .avb_ops = &mv88e6352_avb_ops, 3264 .ptp_ops = &mv88e6352_ptp_ops, 3265 }; 3266 3267 static const struct mv88e6xxx_ops mv88e6321_ops = { 3268 /* MV88E6XXX_FAMILY_6320 */ 3269 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3270 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3271 .irl_init_all = mv88e6352_g2_irl_init_all, 3272 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3273 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3274 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3275 .phy_read = mv88e6xxx_g2_smi_phy_read, 3276 .phy_write = mv88e6xxx_g2_smi_phy_write, 3277 .port_set_link = mv88e6xxx_port_set_link, 3278 .port_set_duplex = mv88e6xxx_port_set_duplex, 3279 .port_set_speed = mv88e6185_port_set_speed, 3280 .port_tag_remap = mv88e6095_port_tag_remap, 3281 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3282 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3283 .port_set_ether_type = mv88e6351_port_set_ether_type, 3284 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3285 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3286 .port_pause_limit = mv88e6097_port_pause_limit, 3287 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3288 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3289 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3290 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3291 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3292 .stats_get_strings = mv88e6320_stats_get_strings, 3293 .stats_get_stats = mv88e6320_stats_get_stats, 3294 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3295 .set_egress_port = mv88e6095_g1_set_egress_port, 3296 .reset = mv88e6352_g1_reset, 3297 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3298 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3299 .gpio_ops = &mv88e6352_gpio_ops, 3300 .avb_ops = &mv88e6352_avb_ops, 3301 .ptp_ops = &mv88e6352_ptp_ops, 3302 }; 3303 3304 static const struct mv88e6xxx_ops mv88e6341_ops = { 3305 /* MV88E6XXX_FAMILY_6341 */ 3306 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3307 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3308 .irl_init_all = mv88e6352_g2_irl_init_all, 3309 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3310 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3311 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3312 .phy_read = mv88e6xxx_g2_smi_phy_read, 3313 .phy_write = mv88e6xxx_g2_smi_phy_write, 3314 .port_set_link = mv88e6xxx_port_set_link, 3315 .port_set_duplex = mv88e6xxx_port_set_duplex, 3316 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3317 .port_set_speed = mv88e6390_port_set_speed, 3318 .port_tag_remap = mv88e6095_port_tag_remap, 3319 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3320 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3321 .port_set_ether_type = mv88e6351_port_set_ether_type, 3322 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3323 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3324 .port_pause_limit = mv88e6097_port_pause_limit, 3325 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3326 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3327 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3328 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3329 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3330 .stats_get_strings = mv88e6320_stats_get_strings, 3331 .stats_get_stats = mv88e6390_stats_get_stats, 3332 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3333 .set_egress_port = mv88e6390_g1_set_egress_port, 3334 .watchdog_ops = &mv88e6390_watchdog_ops, 3335 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3336 .pot_clear = mv88e6xxx_g2_pot_clear, 3337 .reset = mv88e6352_g1_reset, 3338 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3339 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3340 .gpio_ops = &mv88e6352_gpio_ops, 3341 .avb_ops = &mv88e6390_avb_ops, 3342 .ptp_ops = &mv88e6352_ptp_ops, 3343 }; 3344 3345 static const struct mv88e6xxx_ops mv88e6350_ops = { 3346 /* MV88E6XXX_FAMILY_6351 */ 3347 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3348 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3349 .irl_init_all = mv88e6352_g2_irl_init_all, 3350 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3351 .phy_read = mv88e6xxx_g2_smi_phy_read, 3352 .phy_write = mv88e6xxx_g2_smi_phy_write, 3353 .port_set_link = mv88e6xxx_port_set_link, 3354 .port_set_duplex = mv88e6xxx_port_set_duplex, 3355 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3356 .port_set_speed = mv88e6185_port_set_speed, 3357 .port_tag_remap = mv88e6095_port_tag_remap, 3358 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3359 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3360 .port_set_ether_type = mv88e6351_port_set_ether_type, 3361 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3362 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3363 .port_pause_limit = mv88e6097_port_pause_limit, 3364 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3365 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3366 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3367 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3368 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3369 .stats_get_strings = mv88e6095_stats_get_strings, 3370 .stats_get_stats = mv88e6095_stats_get_stats, 3371 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3372 .set_egress_port = mv88e6095_g1_set_egress_port, 3373 .watchdog_ops = &mv88e6097_watchdog_ops, 3374 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3375 .pot_clear = mv88e6xxx_g2_pot_clear, 3376 .reset = mv88e6352_g1_reset, 3377 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3378 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3379 }; 3380 3381 static const struct mv88e6xxx_ops mv88e6351_ops = { 3382 /* MV88E6XXX_FAMILY_6351 */ 3383 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3384 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3385 .irl_init_all = mv88e6352_g2_irl_init_all, 3386 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3387 .phy_read = mv88e6xxx_g2_smi_phy_read, 3388 .phy_write = mv88e6xxx_g2_smi_phy_write, 3389 .port_set_link = mv88e6xxx_port_set_link, 3390 .port_set_duplex = mv88e6xxx_port_set_duplex, 3391 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3392 .port_set_speed = mv88e6185_port_set_speed, 3393 .port_tag_remap = mv88e6095_port_tag_remap, 3394 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3395 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3396 .port_set_ether_type = mv88e6351_port_set_ether_type, 3397 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3398 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3399 .port_pause_limit = mv88e6097_port_pause_limit, 3400 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3401 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3402 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3403 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3404 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3405 .stats_get_strings = mv88e6095_stats_get_strings, 3406 .stats_get_stats = mv88e6095_stats_get_stats, 3407 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3408 .set_egress_port = mv88e6095_g1_set_egress_port, 3409 .watchdog_ops = &mv88e6097_watchdog_ops, 3410 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3411 .pot_clear = mv88e6xxx_g2_pot_clear, 3412 .reset = mv88e6352_g1_reset, 3413 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3414 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3415 .avb_ops = &mv88e6352_avb_ops, 3416 .ptp_ops = &mv88e6352_ptp_ops, 3417 }; 3418 3419 static const struct mv88e6xxx_ops mv88e6352_ops = { 3420 /* MV88E6XXX_FAMILY_6352 */ 3421 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3422 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3423 .irl_init_all = mv88e6352_g2_irl_init_all, 3424 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3425 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3426 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3427 .phy_read = mv88e6xxx_g2_smi_phy_read, 3428 .phy_write = mv88e6xxx_g2_smi_phy_write, 3429 .port_set_link = mv88e6xxx_port_set_link, 3430 .port_set_duplex = mv88e6xxx_port_set_duplex, 3431 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3432 .port_set_speed = mv88e6352_port_set_speed, 3433 .port_tag_remap = mv88e6095_port_tag_remap, 3434 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3435 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3436 .port_set_ether_type = mv88e6351_port_set_ether_type, 3437 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3438 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3439 .port_pause_limit = mv88e6097_port_pause_limit, 3440 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3441 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3442 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3443 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3444 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3445 .stats_get_strings = mv88e6095_stats_get_strings, 3446 .stats_get_stats = mv88e6095_stats_get_stats, 3447 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3448 .set_egress_port = mv88e6095_g1_set_egress_port, 3449 .watchdog_ops = &mv88e6097_watchdog_ops, 3450 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3451 .pot_clear = mv88e6xxx_g2_pot_clear, 3452 .reset = mv88e6352_g1_reset, 3453 .rmu_disable = mv88e6352_g1_rmu_disable, 3454 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3455 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3456 .serdes_power = mv88e6352_serdes_power, 3457 .gpio_ops = &mv88e6352_gpio_ops, 3458 .avb_ops = &mv88e6352_avb_ops, 3459 .ptp_ops = &mv88e6352_ptp_ops, 3460 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3461 .serdes_get_strings = mv88e6352_serdes_get_strings, 3462 .serdes_get_stats = mv88e6352_serdes_get_stats, 3463 }; 3464 3465 static const struct mv88e6xxx_ops mv88e6390_ops = { 3466 /* MV88E6XXX_FAMILY_6390 */ 3467 .irl_init_all = mv88e6390_g2_irl_init_all, 3468 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3469 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3470 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3471 .phy_read = mv88e6xxx_g2_smi_phy_read, 3472 .phy_write = mv88e6xxx_g2_smi_phy_write, 3473 .port_set_link = mv88e6xxx_port_set_link, 3474 .port_set_duplex = mv88e6xxx_port_set_duplex, 3475 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3476 .port_set_speed = mv88e6390_port_set_speed, 3477 .port_tag_remap = mv88e6390_port_tag_remap, 3478 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3479 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3480 .port_set_ether_type = mv88e6351_port_set_ether_type, 3481 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3482 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3483 .port_pause_limit = mv88e6390_port_pause_limit, 3484 .port_set_cmode = mv88e6390x_port_set_cmode, 3485 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3486 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3487 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3488 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3489 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3490 .stats_get_strings = mv88e6320_stats_get_strings, 3491 .stats_get_stats = mv88e6390_stats_get_stats, 3492 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3493 .set_egress_port = mv88e6390_g1_set_egress_port, 3494 .watchdog_ops = &mv88e6390_watchdog_ops, 3495 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3496 .pot_clear = mv88e6xxx_g2_pot_clear, 3497 .reset = mv88e6352_g1_reset, 3498 .rmu_disable = mv88e6390_g1_rmu_disable, 3499 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3500 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3501 .serdes_power = mv88e6390_serdes_power, 3502 .gpio_ops = &mv88e6352_gpio_ops, 3503 .avb_ops = &mv88e6390_avb_ops, 3504 .ptp_ops = &mv88e6352_ptp_ops, 3505 }; 3506 3507 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3508 /* MV88E6XXX_FAMILY_6390 */ 3509 .irl_init_all = mv88e6390_g2_irl_init_all, 3510 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3511 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3512 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3513 .phy_read = mv88e6xxx_g2_smi_phy_read, 3514 .phy_write = mv88e6xxx_g2_smi_phy_write, 3515 .port_set_link = mv88e6xxx_port_set_link, 3516 .port_set_duplex = mv88e6xxx_port_set_duplex, 3517 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3518 .port_set_speed = mv88e6390x_port_set_speed, 3519 .port_tag_remap = mv88e6390_port_tag_remap, 3520 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3521 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3522 .port_set_ether_type = mv88e6351_port_set_ether_type, 3523 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3524 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3525 .port_pause_limit = mv88e6390_port_pause_limit, 3526 .port_set_cmode = mv88e6390x_port_set_cmode, 3527 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3528 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3529 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3530 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3531 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3532 .stats_get_strings = mv88e6320_stats_get_strings, 3533 .stats_get_stats = mv88e6390_stats_get_stats, 3534 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3535 .set_egress_port = mv88e6390_g1_set_egress_port, 3536 .watchdog_ops = &mv88e6390_watchdog_ops, 3537 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3538 .pot_clear = mv88e6xxx_g2_pot_clear, 3539 .reset = mv88e6352_g1_reset, 3540 .rmu_disable = mv88e6390_g1_rmu_disable, 3541 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3542 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3543 .serdes_power = mv88e6390_serdes_power, 3544 .gpio_ops = &mv88e6352_gpio_ops, 3545 .avb_ops = &mv88e6390_avb_ops, 3546 .ptp_ops = &mv88e6352_ptp_ops, 3547 }; 3548 3549 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3550 [MV88E6085] = { 3551 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3552 .family = MV88E6XXX_FAMILY_6097, 3553 .name = "Marvell 88E6085", 3554 .num_databases = 4096, 3555 .num_ports = 10, 3556 .num_internal_phys = 5, 3557 .max_vid = 4095, 3558 .port_base_addr = 0x10, 3559 .phy_base_addr = 0x0, 3560 .global1_addr = 0x1b, 3561 .global2_addr = 0x1c, 3562 .age_time_coeff = 15000, 3563 .g1_irqs = 8, 3564 .g2_irqs = 10, 3565 .atu_move_port_mask = 0xf, 3566 .pvt = true, 3567 .multi_chip = true, 3568 .tag_protocol = DSA_TAG_PROTO_DSA, 3569 .ops = &mv88e6085_ops, 3570 }, 3571 3572 [MV88E6095] = { 3573 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3574 .family = MV88E6XXX_FAMILY_6095, 3575 .name = "Marvell 88E6095/88E6095F", 3576 .num_databases = 256, 3577 .num_ports = 11, 3578 .num_internal_phys = 0, 3579 .max_vid = 4095, 3580 .port_base_addr = 0x10, 3581 .phy_base_addr = 0x0, 3582 .global1_addr = 0x1b, 3583 .global2_addr = 0x1c, 3584 .age_time_coeff = 15000, 3585 .g1_irqs = 8, 3586 .atu_move_port_mask = 0xf, 3587 .multi_chip = true, 3588 .tag_protocol = DSA_TAG_PROTO_DSA, 3589 .ops = &mv88e6095_ops, 3590 }, 3591 3592 [MV88E6097] = { 3593 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3594 .family = MV88E6XXX_FAMILY_6097, 3595 .name = "Marvell 88E6097/88E6097F", 3596 .num_databases = 4096, 3597 .num_ports = 11, 3598 .num_internal_phys = 8, 3599 .max_vid = 4095, 3600 .port_base_addr = 0x10, 3601 .phy_base_addr = 0x0, 3602 .global1_addr = 0x1b, 3603 .global2_addr = 0x1c, 3604 .age_time_coeff = 15000, 3605 .g1_irqs = 8, 3606 .g2_irqs = 10, 3607 .atu_move_port_mask = 0xf, 3608 .pvt = true, 3609 .multi_chip = true, 3610 .tag_protocol = DSA_TAG_PROTO_EDSA, 3611 .ops = &mv88e6097_ops, 3612 }, 3613 3614 [MV88E6123] = { 3615 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3616 .family = MV88E6XXX_FAMILY_6165, 3617 .name = "Marvell 88E6123", 3618 .num_databases = 4096, 3619 .num_ports = 3, 3620 .num_internal_phys = 5, 3621 .max_vid = 4095, 3622 .port_base_addr = 0x10, 3623 .phy_base_addr = 0x0, 3624 .global1_addr = 0x1b, 3625 .global2_addr = 0x1c, 3626 .age_time_coeff = 15000, 3627 .g1_irqs = 9, 3628 .g2_irqs = 10, 3629 .atu_move_port_mask = 0xf, 3630 .pvt = true, 3631 .multi_chip = true, 3632 .tag_protocol = DSA_TAG_PROTO_EDSA, 3633 .ops = &mv88e6123_ops, 3634 }, 3635 3636 [MV88E6131] = { 3637 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3638 .family = MV88E6XXX_FAMILY_6185, 3639 .name = "Marvell 88E6131", 3640 .num_databases = 256, 3641 .num_ports = 8, 3642 .num_internal_phys = 0, 3643 .max_vid = 4095, 3644 .port_base_addr = 0x10, 3645 .phy_base_addr = 0x0, 3646 .global1_addr = 0x1b, 3647 .global2_addr = 0x1c, 3648 .age_time_coeff = 15000, 3649 .g1_irqs = 9, 3650 .atu_move_port_mask = 0xf, 3651 .multi_chip = true, 3652 .tag_protocol = DSA_TAG_PROTO_DSA, 3653 .ops = &mv88e6131_ops, 3654 }, 3655 3656 [MV88E6141] = { 3657 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3658 .family = MV88E6XXX_FAMILY_6341, 3659 .name = "Marvell 88E6141", 3660 .num_databases = 4096, 3661 .num_ports = 6, 3662 .num_internal_phys = 5, 3663 .num_gpio = 11, 3664 .max_vid = 4095, 3665 .port_base_addr = 0x10, 3666 .phy_base_addr = 0x10, 3667 .global1_addr = 0x1b, 3668 .global2_addr = 0x1c, 3669 .age_time_coeff = 3750, 3670 .atu_move_port_mask = 0x1f, 3671 .g1_irqs = 9, 3672 .g2_irqs = 10, 3673 .pvt = true, 3674 .multi_chip = true, 3675 .tag_protocol = DSA_TAG_PROTO_EDSA, 3676 .ops = &mv88e6141_ops, 3677 }, 3678 3679 [MV88E6161] = { 3680 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3681 .family = MV88E6XXX_FAMILY_6165, 3682 .name = "Marvell 88E6161", 3683 .num_databases = 4096, 3684 .num_ports = 6, 3685 .num_internal_phys = 5, 3686 .max_vid = 4095, 3687 .port_base_addr = 0x10, 3688 .phy_base_addr = 0x0, 3689 .global1_addr = 0x1b, 3690 .global2_addr = 0x1c, 3691 .age_time_coeff = 15000, 3692 .g1_irqs = 9, 3693 .g2_irqs = 10, 3694 .atu_move_port_mask = 0xf, 3695 .pvt = true, 3696 .multi_chip = true, 3697 .tag_protocol = DSA_TAG_PROTO_EDSA, 3698 .ptp_support = true, 3699 .ops = &mv88e6161_ops, 3700 }, 3701 3702 [MV88E6165] = { 3703 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3704 .family = MV88E6XXX_FAMILY_6165, 3705 .name = "Marvell 88E6165", 3706 .num_databases = 4096, 3707 .num_ports = 6, 3708 .num_internal_phys = 0, 3709 .max_vid = 4095, 3710 .port_base_addr = 0x10, 3711 .phy_base_addr = 0x0, 3712 .global1_addr = 0x1b, 3713 .global2_addr = 0x1c, 3714 .age_time_coeff = 15000, 3715 .g1_irqs = 9, 3716 .g2_irqs = 10, 3717 .atu_move_port_mask = 0xf, 3718 .pvt = true, 3719 .multi_chip = true, 3720 .tag_protocol = DSA_TAG_PROTO_DSA, 3721 .ptp_support = true, 3722 .ops = &mv88e6165_ops, 3723 }, 3724 3725 [MV88E6171] = { 3726 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3727 .family = MV88E6XXX_FAMILY_6351, 3728 .name = "Marvell 88E6171", 3729 .num_databases = 4096, 3730 .num_ports = 7, 3731 .num_internal_phys = 5, 3732 .max_vid = 4095, 3733 .port_base_addr = 0x10, 3734 .phy_base_addr = 0x0, 3735 .global1_addr = 0x1b, 3736 .global2_addr = 0x1c, 3737 .age_time_coeff = 15000, 3738 .g1_irqs = 9, 3739 .g2_irqs = 10, 3740 .atu_move_port_mask = 0xf, 3741 .pvt = true, 3742 .multi_chip = true, 3743 .tag_protocol = DSA_TAG_PROTO_EDSA, 3744 .ops = &mv88e6171_ops, 3745 }, 3746 3747 [MV88E6172] = { 3748 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3749 .family = MV88E6XXX_FAMILY_6352, 3750 .name = "Marvell 88E6172", 3751 .num_databases = 4096, 3752 .num_ports = 7, 3753 .num_internal_phys = 5, 3754 .num_gpio = 15, 3755 .max_vid = 4095, 3756 .port_base_addr = 0x10, 3757 .phy_base_addr = 0x0, 3758 .global1_addr = 0x1b, 3759 .global2_addr = 0x1c, 3760 .age_time_coeff = 15000, 3761 .g1_irqs = 9, 3762 .g2_irqs = 10, 3763 .atu_move_port_mask = 0xf, 3764 .pvt = true, 3765 .multi_chip = true, 3766 .tag_protocol = DSA_TAG_PROTO_EDSA, 3767 .ops = &mv88e6172_ops, 3768 }, 3769 3770 [MV88E6175] = { 3771 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3772 .family = MV88E6XXX_FAMILY_6351, 3773 .name = "Marvell 88E6175", 3774 .num_databases = 4096, 3775 .num_ports = 7, 3776 .num_internal_phys = 5, 3777 .max_vid = 4095, 3778 .port_base_addr = 0x10, 3779 .phy_base_addr = 0x0, 3780 .global1_addr = 0x1b, 3781 .global2_addr = 0x1c, 3782 .age_time_coeff = 15000, 3783 .g1_irqs = 9, 3784 .g2_irqs = 10, 3785 .atu_move_port_mask = 0xf, 3786 .pvt = true, 3787 .multi_chip = true, 3788 .tag_protocol = DSA_TAG_PROTO_EDSA, 3789 .ops = &mv88e6175_ops, 3790 }, 3791 3792 [MV88E6176] = { 3793 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3794 .family = MV88E6XXX_FAMILY_6352, 3795 .name = "Marvell 88E6176", 3796 .num_databases = 4096, 3797 .num_ports = 7, 3798 .num_internal_phys = 5, 3799 .num_gpio = 15, 3800 .max_vid = 4095, 3801 .port_base_addr = 0x10, 3802 .phy_base_addr = 0x0, 3803 .global1_addr = 0x1b, 3804 .global2_addr = 0x1c, 3805 .age_time_coeff = 15000, 3806 .g1_irqs = 9, 3807 .g2_irqs = 10, 3808 .atu_move_port_mask = 0xf, 3809 .pvt = true, 3810 .multi_chip = true, 3811 .tag_protocol = DSA_TAG_PROTO_EDSA, 3812 .ops = &mv88e6176_ops, 3813 }, 3814 3815 [MV88E6185] = { 3816 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3817 .family = MV88E6XXX_FAMILY_6185, 3818 .name = "Marvell 88E6185", 3819 .num_databases = 256, 3820 .num_ports = 10, 3821 .num_internal_phys = 0, 3822 .max_vid = 4095, 3823 .port_base_addr = 0x10, 3824 .phy_base_addr = 0x0, 3825 .global1_addr = 0x1b, 3826 .global2_addr = 0x1c, 3827 .age_time_coeff = 15000, 3828 .g1_irqs = 8, 3829 .atu_move_port_mask = 0xf, 3830 .multi_chip = true, 3831 .tag_protocol = DSA_TAG_PROTO_EDSA, 3832 .ops = &mv88e6185_ops, 3833 }, 3834 3835 [MV88E6190] = { 3836 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3837 .family = MV88E6XXX_FAMILY_6390, 3838 .name = "Marvell 88E6190", 3839 .num_databases = 4096, 3840 .num_ports = 11, /* 10 + Z80 */ 3841 .num_internal_phys = 11, 3842 .num_gpio = 16, 3843 .max_vid = 8191, 3844 .port_base_addr = 0x0, 3845 .phy_base_addr = 0x0, 3846 .global1_addr = 0x1b, 3847 .global2_addr = 0x1c, 3848 .tag_protocol = DSA_TAG_PROTO_DSA, 3849 .age_time_coeff = 3750, 3850 .g1_irqs = 9, 3851 .g2_irqs = 14, 3852 .pvt = true, 3853 .multi_chip = true, 3854 .atu_move_port_mask = 0x1f, 3855 .ops = &mv88e6190_ops, 3856 }, 3857 3858 [MV88E6190X] = { 3859 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3860 .family = MV88E6XXX_FAMILY_6390, 3861 .name = "Marvell 88E6190X", 3862 .num_databases = 4096, 3863 .num_ports = 11, /* 10 + Z80 */ 3864 .num_internal_phys = 11, 3865 .num_gpio = 16, 3866 .max_vid = 8191, 3867 .port_base_addr = 0x0, 3868 .phy_base_addr = 0x0, 3869 .global1_addr = 0x1b, 3870 .global2_addr = 0x1c, 3871 .age_time_coeff = 3750, 3872 .g1_irqs = 9, 3873 .g2_irqs = 14, 3874 .atu_move_port_mask = 0x1f, 3875 .pvt = true, 3876 .multi_chip = true, 3877 .tag_protocol = DSA_TAG_PROTO_DSA, 3878 .ops = &mv88e6190x_ops, 3879 }, 3880 3881 [MV88E6191] = { 3882 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3883 .family = MV88E6XXX_FAMILY_6390, 3884 .name = "Marvell 88E6191", 3885 .num_databases = 4096, 3886 .num_ports = 11, /* 10 + Z80 */ 3887 .num_internal_phys = 11, 3888 .max_vid = 8191, 3889 .port_base_addr = 0x0, 3890 .phy_base_addr = 0x0, 3891 .global1_addr = 0x1b, 3892 .global2_addr = 0x1c, 3893 .age_time_coeff = 3750, 3894 .g1_irqs = 9, 3895 .g2_irqs = 14, 3896 .atu_move_port_mask = 0x1f, 3897 .pvt = true, 3898 .multi_chip = true, 3899 .tag_protocol = DSA_TAG_PROTO_DSA, 3900 .ptp_support = true, 3901 .ops = &mv88e6191_ops, 3902 }, 3903 3904 [MV88E6240] = { 3905 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3906 .family = MV88E6XXX_FAMILY_6352, 3907 .name = "Marvell 88E6240", 3908 .num_databases = 4096, 3909 .num_ports = 7, 3910 .num_internal_phys = 5, 3911 .num_gpio = 15, 3912 .max_vid = 4095, 3913 .port_base_addr = 0x10, 3914 .phy_base_addr = 0x0, 3915 .global1_addr = 0x1b, 3916 .global2_addr = 0x1c, 3917 .age_time_coeff = 15000, 3918 .g1_irqs = 9, 3919 .g2_irqs = 10, 3920 .atu_move_port_mask = 0xf, 3921 .pvt = true, 3922 .multi_chip = true, 3923 .tag_protocol = DSA_TAG_PROTO_EDSA, 3924 .ptp_support = true, 3925 .ops = &mv88e6240_ops, 3926 }, 3927 3928 [MV88E6290] = { 3929 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3930 .family = MV88E6XXX_FAMILY_6390, 3931 .name = "Marvell 88E6290", 3932 .num_databases = 4096, 3933 .num_ports = 11, /* 10 + Z80 */ 3934 .num_internal_phys = 11, 3935 .num_gpio = 16, 3936 .max_vid = 8191, 3937 .port_base_addr = 0x0, 3938 .phy_base_addr = 0x0, 3939 .global1_addr = 0x1b, 3940 .global2_addr = 0x1c, 3941 .age_time_coeff = 3750, 3942 .g1_irqs = 9, 3943 .g2_irqs = 14, 3944 .atu_move_port_mask = 0x1f, 3945 .pvt = true, 3946 .multi_chip = true, 3947 .tag_protocol = DSA_TAG_PROTO_DSA, 3948 .ptp_support = true, 3949 .ops = &mv88e6290_ops, 3950 }, 3951 3952 [MV88E6320] = { 3953 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3954 .family = MV88E6XXX_FAMILY_6320, 3955 .name = "Marvell 88E6320", 3956 .num_databases = 4096, 3957 .num_ports = 7, 3958 .num_internal_phys = 5, 3959 .num_gpio = 15, 3960 .max_vid = 4095, 3961 .port_base_addr = 0x10, 3962 .phy_base_addr = 0x0, 3963 .global1_addr = 0x1b, 3964 .global2_addr = 0x1c, 3965 .age_time_coeff = 15000, 3966 .g1_irqs = 8, 3967 .g2_irqs = 10, 3968 .atu_move_port_mask = 0xf, 3969 .pvt = true, 3970 .multi_chip = true, 3971 .tag_protocol = DSA_TAG_PROTO_EDSA, 3972 .ptp_support = true, 3973 .ops = &mv88e6320_ops, 3974 }, 3975 3976 [MV88E6321] = { 3977 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3978 .family = MV88E6XXX_FAMILY_6320, 3979 .name = "Marvell 88E6321", 3980 .num_databases = 4096, 3981 .num_ports = 7, 3982 .num_internal_phys = 5, 3983 .num_gpio = 15, 3984 .max_vid = 4095, 3985 .port_base_addr = 0x10, 3986 .phy_base_addr = 0x0, 3987 .global1_addr = 0x1b, 3988 .global2_addr = 0x1c, 3989 .age_time_coeff = 15000, 3990 .g1_irqs = 8, 3991 .g2_irqs = 10, 3992 .atu_move_port_mask = 0xf, 3993 .multi_chip = true, 3994 .tag_protocol = DSA_TAG_PROTO_EDSA, 3995 .ptp_support = true, 3996 .ops = &mv88e6321_ops, 3997 }, 3998 3999 [MV88E6341] = { 4000 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4001 .family = MV88E6XXX_FAMILY_6341, 4002 .name = "Marvell 88E6341", 4003 .num_databases = 4096, 4004 .num_internal_phys = 5, 4005 .num_ports = 6, 4006 .num_gpio = 11, 4007 .max_vid = 4095, 4008 .port_base_addr = 0x10, 4009 .phy_base_addr = 0x10, 4010 .global1_addr = 0x1b, 4011 .global2_addr = 0x1c, 4012 .age_time_coeff = 3750, 4013 .atu_move_port_mask = 0x1f, 4014 .g1_irqs = 9, 4015 .g2_irqs = 10, 4016 .pvt = true, 4017 .multi_chip = true, 4018 .tag_protocol = DSA_TAG_PROTO_EDSA, 4019 .ptp_support = true, 4020 .ops = &mv88e6341_ops, 4021 }, 4022 4023 [MV88E6350] = { 4024 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4025 .family = MV88E6XXX_FAMILY_6351, 4026 .name = "Marvell 88E6350", 4027 .num_databases = 4096, 4028 .num_ports = 7, 4029 .num_internal_phys = 5, 4030 .max_vid = 4095, 4031 .port_base_addr = 0x10, 4032 .phy_base_addr = 0x0, 4033 .global1_addr = 0x1b, 4034 .global2_addr = 0x1c, 4035 .age_time_coeff = 15000, 4036 .g1_irqs = 9, 4037 .g2_irqs = 10, 4038 .atu_move_port_mask = 0xf, 4039 .pvt = true, 4040 .multi_chip = true, 4041 .tag_protocol = DSA_TAG_PROTO_EDSA, 4042 .ops = &mv88e6350_ops, 4043 }, 4044 4045 [MV88E6351] = { 4046 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4047 .family = MV88E6XXX_FAMILY_6351, 4048 .name = "Marvell 88E6351", 4049 .num_databases = 4096, 4050 .num_ports = 7, 4051 .num_internal_phys = 5, 4052 .max_vid = 4095, 4053 .port_base_addr = 0x10, 4054 .phy_base_addr = 0x0, 4055 .global1_addr = 0x1b, 4056 .global2_addr = 0x1c, 4057 .age_time_coeff = 15000, 4058 .g1_irqs = 9, 4059 .g2_irqs = 10, 4060 .atu_move_port_mask = 0xf, 4061 .pvt = true, 4062 .multi_chip = true, 4063 .tag_protocol = DSA_TAG_PROTO_EDSA, 4064 .ops = &mv88e6351_ops, 4065 }, 4066 4067 [MV88E6352] = { 4068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4069 .family = MV88E6XXX_FAMILY_6352, 4070 .name = "Marvell 88E6352", 4071 .num_databases = 4096, 4072 .num_ports = 7, 4073 .num_internal_phys = 5, 4074 .num_gpio = 15, 4075 .max_vid = 4095, 4076 .port_base_addr = 0x10, 4077 .phy_base_addr = 0x0, 4078 .global1_addr = 0x1b, 4079 .global2_addr = 0x1c, 4080 .age_time_coeff = 15000, 4081 .g1_irqs = 9, 4082 .g2_irqs = 10, 4083 .atu_move_port_mask = 0xf, 4084 .pvt = true, 4085 .multi_chip = true, 4086 .tag_protocol = DSA_TAG_PROTO_EDSA, 4087 .ptp_support = true, 4088 .ops = &mv88e6352_ops, 4089 }, 4090 [MV88E6390] = { 4091 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4092 .family = MV88E6XXX_FAMILY_6390, 4093 .name = "Marvell 88E6390", 4094 .num_databases = 4096, 4095 .num_ports = 11, /* 10 + Z80 */ 4096 .num_internal_phys = 11, 4097 .num_gpio = 16, 4098 .max_vid = 8191, 4099 .port_base_addr = 0x0, 4100 .phy_base_addr = 0x0, 4101 .global1_addr = 0x1b, 4102 .global2_addr = 0x1c, 4103 .age_time_coeff = 3750, 4104 .g1_irqs = 9, 4105 .g2_irqs = 14, 4106 .atu_move_port_mask = 0x1f, 4107 .pvt = true, 4108 .multi_chip = true, 4109 .tag_protocol = DSA_TAG_PROTO_DSA, 4110 .ptp_support = true, 4111 .ops = &mv88e6390_ops, 4112 }, 4113 [MV88E6390X] = { 4114 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4115 .family = MV88E6XXX_FAMILY_6390, 4116 .name = "Marvell 88E6390X", 4117 .num_databases = 4096, 4118 .num_ports = 11, /* 10 + Z80 */ 4119 .num_internal_phys = 11, 4120 .num_gpio = 16, 4121 .max_vid = 8191, 4122 .port_base_addr = 0x0, 4123 .phy_base_addr = 0x0, 4124 .global1_addr = 0x1b, 4125 .global2_addr = 0x1c, 4126 .age_time_coeff = 3750, 4127 .g1_irqs = 9, 4128 .g2_irqs = 14, 4129 .atu_move_port_mask = 0x1f, 4130 .pvt = true, 4131 .multi_chip = true, 4132 .tag_protocol = DSA_TAG_PROTO_DSA, 4133 .ptp_support = true, 4134 .ops = &mv88e6390x_ops, 4135 }, 4136 }; 4137 4138 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4139 { 4140 int i; 4141 4142 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4143 if (mv88e6xxx_table[i].prod_num == prod_num) 4144 return &mv88e6xxx_table[i]; 4145 4146 return NULL; 4147 } 4148 4149 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4150 { 4151 const struct mv88e6xxx_info *info; 4152 unsigned int prod_num, rev; 4153 u16 id; 4154 int err; 4155 4156 mutex_lock(&chip->reg_lock); 4157 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4158 mutex_unlock(&chip->reg_lock); 4159 if (err) 4160 return err; 4161 4162 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4163 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4164 4165 info = mv88e6xxx_lookup_info(prod_num); 4166 if (!info) 4167 return -ENODEV; 4168 4169 /* Update the compatible info with the probed one */ 4170 chip->info = info; 4171 4172 err = mv88e6xxx_g2_require(chip); 4173 if (err) 4174 return err; 4175 4176 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4177 chip->info->prod_num, chip->info->name, rev); 4178 4179 return 0; 4180 } 4181 4182 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4183 { 4184 struct mv88e6xxx_chip *chip; 4185 4186 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4187 if (!chip) 4188 return NULL; 4189 4190 chip->dev = dev; 4191 4192 mutex_init(&chip->reg_lock); 4193 INIT_LIST_HEAD(&chip->mdios); 4194 4195 return chip; 4196 } 4197 4198 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4199 struct mii_bus *bus, int sw_addr) 4200 { 4201 if (sw_addr == 0) 4202 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4203 else if (chip->info->multi_chip) 4204 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4205 else 4206 return -EINVAL; 4207 4208 chip->bus = bus; 4209 chip->sw_addr = sw_addr; 4210 4211 return 0; 4212 } 4213 4214 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4215 int port) 4216 { 4217 struct mv88e6xxx_chip *chip = ds->priv; 4218 4219 return chip->info->tag_protocol; 4220 } 4221 4222 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4223 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4224 struct device *host_dev, int sw_addr, 4225 void **priv) 4226 { 4227 struct mv88e6xxx_chip *chip; 4228 struct mii_bus *bus; 4229 int err; 4230 4231 bus = dsa_host_dev_to_mii_bus(host_dev); 4232 if (!bus) 4233 return NULL; 4234 4235 chip = mv88e6xxx_alloc_chip(dsa_dev); 4236 if (!chip) 4237 return NULL; 4238 4239 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4240 chip->info = &mv88e6xxx_table[MV88E6085]; 4241 4242 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4243 if (err) 4244 goto free; 4245 4246 err = mv88e6xxx_detect(chip); 4247 if (err) 4248 goto free; 4249 4250 mutex_lock(&chip->reg_lock); 4251 err = mv88e6xxx_switch_reset(chip); 4252 mutex_unlock(&chip->reg_lock); 4253 if (err) 4254 goto free; 4255 4256 mv88e6xxx_phy_init(chip); 4257 4258 err = mv88e6xxx_mdios_register(chip, NULL); 4259 if (err) 4260 goto free; 4261 4262 *priv = chip; 4263 4264 return chip->info->name; 4265 free: 4266 devm_kfree(dsa_dev, chip); 4267 4268 return NULL; 4269 } 4270 #endif 4271 4272 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4273 const struct switchdev_obj_port_mdb *mdb) 4274 { 4275 /* We don't need any dynamic resource from the kernel (yet), 4276 * so skip the prepare phase. 4277 */ 4278 4279 return 0; 4280 } 4281 4282 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4283 const struct switchdev_obj_port_mdb *mdb) 4284 { 4285 struct mv88e6xxx_chip *chip = ds->priv; 4286 4287 mutex_lock(&chip->reg_lock); 4288 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4289 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4290 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4291 port); 4292 mutex_unlock(&chip->reg_lock); 4293 } 4294 4295 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4296 const struct switchdev_obj_port_mdb *mdb) 4297 { 4298 struct mv88e6xxx_chip *chip = ds->priv; 4299 int err; 4300 4301 mutex_lock(&chip->reg_lock); 4302 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4303 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4304 mutex_unlock(&chip->reg_lock); 4305 4306 return err; 4307 } 4308 4309 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4310 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4311 .probe = mv88e6xxx_drv_probe, 4312 #endif 4313 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4314 .setup = mv88e6xxx_setup, 4315 .adjust_link = mv88e6xxx_adjust_link, 4316 .phylink_validate = mv88e6xxx_validate, 4317 .phylink_mac_link_state = mv88e6xxx_link_state, 4318 .phylink_mac_config = mv88e6xxx_mac_config, 4319 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4320 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4321 .get_strings = mv88e6xxx_get_strings, 4322 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4323 .get_sset_count = mv88e6xxx_get_sset_count, 4324 .port_enable = mv88e6xxx_port_enable, 4325 .port_disable = mv88e6xxx_port_disable, 4326 .get_mac_eee = mv88e6xxx_get_mac_eee, 4327 .set_mac_eee = mv88e6xxx_set_mac_eee, 4328 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4329 .get_eeprom = mv88e6xxx_get_eeprom, 4330 .set_eeprom = mv88e6xxx_set_eeprom, 4331 .get_regs_len = mv88e6xxx_get_regs_len, 4332 .get_regs = mv88e6xxx_get_regs, 4333 .set_ageing_time = mv88e6xxx_set_ageing_time, 4334 .port_bridge_join = mv88e6xxx_port_bridge_join, 4335 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4336 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4337 .port_fast_age = mv88e6xxx_port_fast_age, 4338 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4339 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4340 .port_vlan_add = mv88e6xxx_port_vlan_add, 4341 .port_vlan_del = mv88e6xxx_port_vlan_del, 4342 .port_fdb_add = mv88e6xxx_port_fdb_add, 4343 .port_fdb_del = mv88e6xxx_port_fdb_del, 4344 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4345 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4346 .port_mdb_add = mv88e6xxx_port_mdb_add, 4347 .port_mdb_del = mv88e6xxx_port_mdb_del, 4348 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4349 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4350 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4351 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4352 .port_txtstamp = mv88e6xxx_port_txtstamp, 4353 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4354 .get_ts_info = mv88e6xxx_get_ts_info, 4355 }; 4356 4357 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4358 .ops = &mv88e6xxx_switch_ops, 4359 }; 4360 4361 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4362 { 4363 struct device *dev = chip->dev; 4364 struct dsa_switch *ds; 4365 4366 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4367 if (!ds) 4368 return -ENOMEM; 4369 4370 ds->priv = chip; 4371 ds->dev = dev; 4372 ds->ops = &mv88e6xxx_switch_ops; 4373 ds->ageing_time_min = chip->info->age_time_coeff; 4374 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4375 4376 dev_set_drvdata(dev, ds); 4377 4378 return dsa_register_switch(ds); 4379 } 4380 4381 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4382 { 4383 dsa_unregister_switch(chip->ds); 4384 } 4385 4386 static const void *pdata_device_get_match_data(struct device *dev) 4387 { 4388 const struct of_device_id *matches = dev->driver->of_match_table; 4389 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4390 4391 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4392 matches++) { 4393 if (!strcmp(pdata->compatible, matches->compatible)) 4394 return matches->data; 4395 } 4396 return NULL; 4397 } 4398 4399 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4400 { 4401 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4402 const struct mv88e6xxx_info *compat_info = NULL; 4403 struct device *dev = &mdiodev->dev; 4404 struct device_node *np = dev->of_node; 4405 struct mv88e6xxx_chip *chip; 4406 int port; 4407 int err; 4408 4409 if (!np && !pdata) 4410 return -EINVAL; 4411 4412 if (np) 4413 compat_info = of_device_get_match_data(dev); 4414 4415 if (pdata) { 4416 compat_info = pdata_device_get_match_data(dev); 4417 4418 if (!pdata->netdev) 4419 return -EINVAL; 4420 4421 for (port = 0; port < DSA_MAX_PORTS; port++) { 4422 if (!(pdata->enabled_ports & (1 << port))) 4423 continue; 4424 if (strcmp(pdata->cd.port_names[port], "cpu")) 4425 continue; 4426 pdata->cd.netdev[port] = &pdata->netdev->dev; 4427 break; 4428 } 4429 } 4430 4431 if (!compat_info) 4432 return -EINVAL; 4433 4434 chip = mv88e6xxx_alloc_chip(dev); 4435 if (!chip) { 4436 err = -ENOMEM; 4437 goto out; 4438 } 4439 4440 chip->info = compat_info; 4441 4442 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4443 if (err) 4444 goto out; 4445 4446 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4447 if (IS_ERR(chip->reset)) { 4448 err = PTR_ERR(chip->reset); 4449 goto out; 4450 } 4451 4452 err = mv88e6xxx_detect(chip); 4453 if (err) 4454 goto out; 4455 4456 mv88e6xxx_phy_init(chip); 4457 4458 if (chip->info->ops->get_eeprom) { 4459 if (np) 4460 of_property_read_u32(np, "eeprom-length", 4461 &chip->eeprom_len); 4462 else 4463 chip->eeprom_len = pdata->eeprom_len; 4464 } 4465 4466 mutex_lock(&chip->reg_lock); 4467 err = mv88e6xxx_switch_reset(chip); 4468 mutex_unlock(&chip->reg_lock); 4469 if (err) 4470 goto out; 4471 4472 chip->irq = of_irq_get(np, 0); 4473 if (chip->irq == -EPROBE_DEFER) { 4474 err = chip->irq; 4475 goto out; 4476 } 4477 4478 /* Has to be performed before the MDIO bus is created, because 4479 * the PHYs will link their interrupts to these interrupt 4480 * controllers 4481 */ 4482 mutex_lock(&chip->reg_lock); 4483 if (chip->irq > 0) 4484 err = mv88e6xxx_g1_irq_setup(chip); 4485 else 4486 err = mv88e6xxx_irq_poll_setup(chip); 4487 mutex_unlock(&chip->reg_lock); 4488 4489 if (err) 4490 goto out; 4491 4492 if (chip->info->g2_irqs > 0) { 4493 err = mv88e6xxx_g2_irq_setup(chip); 4494 if (err) 4495 goto out_g1_irq; 4496 } 4497 4498 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4499 if (err) 4500 goto out_g2_irq; 4501 4502 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4503 if (err) 4504 goto out_g1_atu_prob_irq; 4505 4506 err = mv88e6xxx_mdios_register(chip, np); 4507 if (err) 4508 goto out_g1_vtu_prob_irq; 4509 4510 err = mv88e6xxx_register_switch(chip); 4511 if (err) 4512 goto out_mdio; 4513 4514 return 0; 4515 4516 out_mdio: 4517 mv88e6xxx_mdios_unregister(chip); 4518 out_g1_vtu_prob_irq: 4519 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4520 out_g1_atu_prob_irq: 4521 mv88e6xxx_g1_atu_prob_irq_free(chip); 4522 out_g2_irq: 4523 if (chip->info->g2_irqs > 0) 4524 mv88e6xxx_g2_irq_free(chip); 4525 out_g1_irq: 4526 mutex_lock(&chip->reg_lock); 4527 if (chip->irq > 0) 4528 mv88e6xxx_g1_irq_free(chip); 4529 else 4530 mv88e6xxx_irq_poll_free(chip); 4531 mutex_unlock(&chip->reg_lock); 4532 out: 4533 if (pdata) 4534 dev_put(pdata->netdev); 4535 4536 return err; 4537 } 4538 4539 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4540 { 4541 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4542 struct mv88e6xxx_chip *chip = ds->priv; 4543 4544 if (chip->info->ptp_support) { 4545 mv88e6xxx_hwtstamp_free(chip); 4546 mv88e6xxx_ptp_free(chip); 4547 } 4548 4549 mv88e6xxx_phy_destroy(chip); 4550 mv88e6xxx_unregister_switch(chip); 4551 mv88e6xxx_mdios_unregister(chip); 4552 4553 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4554 mv88e6xxx_g1_atu_prob_irq_free(chip); 4555 4556 if (chip->info->g2_irqs > 0) 4557 mv88e6xxx_g2_irq_free(chip); 4558 4559 mutex_lock(&chip->reg_lock); 4560 if (chip->irq > 0) 4561 mv88e6xxx_g1_irq_free(chip); 4562 else 4563 mv88e6xxx_irq_poll_free(chip); 4564 mutex_unlock(&chip->reg_lock); 4565 } 4566 4567 static const struct of_device_id mv88e6xxx_of_match[] = { 4568 { 4569 .compatible = "marvell,mv88e6085", 4570 .data = &mv88e6xxx_table[MV88E6085], 4571 }, 4572 { 4573 .compatible = "marvell,mv88e6190", 4574 .data = &mv88e6xxx_table[MV88E6190], 4575 }, 4576 { /* sentinel */ }, 4577 }; 4578 4579 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4580 4581 static struct mdio_driver mv88e6xxx_driver = { 4582 .probe = mv88e6xxx_probe, 4583 .remove = mv88e6xxx_remove, 4584 .mdiodrv.driver = { 4585 .name = "mv88e6085", 4586 .of_match_table = mv88e6xxx_of_match, 4587 }, 4588 }; 4589 4590 static int __init mv88e6xxx_init(void) 4591 { 4592 register_switch_driver(&mv88e6xxx_switch_drv); 4593 return mdio_driver_register(&mv88e6xxx_driver); 4594 } 4595 module_init(mv88e6xxx_init); 4596 4597 static void __exit mv88e6xxx_cleanup(void) 4598 { 4599 mdio_driver_unregister(&mv88e6xxx_driver); 4600 unregister_switch_driver(&mv88e6xxx_switch_drv); 4601 } 4602 module_exit(mv88e6xxx_cleanup); 4603 4604 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4605 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4606 MODULE_LICENSE("GPL"); 4607