xref: /openbmc/linux/drivers/net/dsa/mv88e6xxx/chip.c (revision 9fb29c73)
1 /*
2  * Marvell 88e6xxx Ethernet switch single-chip support
3  *
4  * Copyright (c) 2008 Marvell Semiconductor
5  *
6  * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch>
7  *
8  * Copyright (c) 2016-2017 Savoir-faire Linux Inc.
9  *	Vivien Didelot <vivien.didelot@savoirfairelinux.com>
10  *
11  * This program is free software; you can redistribute it and/or modify
12  * it under the terms of the GNU General Public License as published by
13  * the Free Software Foundation; either version 2 of the License, or
14  * (at your option) any later version.
15  */
16 
17 #include <linux/delay.h>
18 #include <linux/etherdevice.h>
19 #include <linux/ethtool.h>
20 #include <linux/if_bridge.h>
21 #include <linux/interrupt.h>
22 #include <linux/irq.h>
23 #include <linux/irqdomain.h>
24 #include <linux/jiffies.h>
25 #include <linux/list.h>
26 #include <linux/mdio.h>
27 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_irq.h>
30 #include <linux/of_mdio.h>
31 #include <linux/platform_data/mv88e6xxx.h>
32 #include <linux/netdevice.h>
33 #include <linux/gpio/consumer.h>
34 #include <linux/phy.h>
35 #include <linux/phylink.h>
36 #include <net/dsa.h>
37 
38 #include "chip.h"
39 #include "global1.h"
40 #include "global2.h"
41 #include "hwtstamp.h"
42 #include "phy.h"
43 #include "port.h"
44 #include "ptp.h"
45 #include "serdes.h"
46 
47 static void assert_reg_lock(struct mv88e6xxx_chip *chip)
48 {
49 	if (unlikely(!mutex_is_locked(&chip->reg_lock))) {
50 		dev_err(chip->dev, "Switch registers lock not held!\n");
51 		dump_stack();
52 	}
53 }
54 
55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address
56  * (ADDR[0] is always zero, thus only even SMI addresses can be strapped).
57  *
58  * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it
59  * is the only device connected to the SMI master. In this mode it responds to
60  * all 32 possible SMI addresses, and thus maps directly the internal devices.
61  *
62  * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing
63  * multiple devices to share the SMI interface. In this mode it responds to only
64  * 2 registers, used to indirectly access the internal SMI devices.
65  */
66 
67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip,
68 			      int addr, int reg, u16 *val)
69 {
70 	if (!chip->smi_ops)
71 		return -EOPNOTSUPP;
72 
73 	return chip->smi_ops->read(chip, addr, reg, val);
74 }
75 
76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip,
77 			       int addr, int reg, u16 val)
78 {
79 	if (!chip->smi_ops)
80 		return -EOPNOTSUPP;
81 
82 	return chip->smi_ops->write(chip, addr, reg, val);
83 }
84 
85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip,
86 					  int addr, int reg, u16 *val)
87 {
88 	int ret;
89 
90 	ret = mdiobus_read_nested(chip->bus, addr, reg);
91 	if (ret < 0)
92 		return ret;
93 
94 	*val = ret & 0xffff;
95 
96 	return 0;
97 }
98 
99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip,
100 					   int addr, int reg, u16 val)
101 {
102 	int ret;
103 
104 	ret = mdiobus_write_nested(chip->bus, addr, reg, val);
105 	if (ret < 0)
106 		return ret;
107 
108 	return 0;
109 }
110 
111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = {
112 	.read = mv88e6xxx_smi_single_chip_read,
113 	.write = mv88e6xxx_smi_single_chip_write,
114 };
115 
116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip)
117 {
118 	int ret;
119 	int i;
120 
121 	for (i = 0; i < 16; i++) {
122 		ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD);
123 		if (ret < 0)
124 			return ret;
125 
126 		if ((ret & SMI_CMD_BUSY) == 0)
127 			return 0;
128 	}
129 
130 	return -ETIMEDOUT;
131 }
132 
133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip,
134 					 int addr, int reg, u16 *val)
135 {
136 	int ret;
137 
138 	/* Wait for the bus to become free. */
139 	ret = mv88e6xxx_smi_multi_chip_wait(chip);
140 	if (ret < 0)
141 		return ret;
142 
143 	/* Transmit the read command. */
144 	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
145 				   SMI_CMD_OP_22_READ | (addr << 5) | reg);
146 	if (ret < 0)
147 		return ret;
148 
149 	/* Wait for the read command to complete. */
150 	ret = mv88e6xxx_smi_multi_chip_wait(chip);
151 	if (ret < 0)
152 		return ret;
153 
154 	/* Read the data. */
155 	ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA);
156 	if (ret < 0)
157 		return ret;
158 
159 	*val = ret & 0xffff;
160 
161 	return 0;
162 }
163 
164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip,
165 					  int addr, int reg, u16 val)
166 {
167 	int ret;
168 
169 	/* Wait for the bus to become free. */
170 	ret = mv88e6xxx_smi_multi_chip_wait(chip);
171 	if (ret < 0)
172 		return ret;
173 
174 	/* Transmit the data to write. */
175 	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val);
176 	if (ret < 0)
177 		return ret;
178 
179 	/* Transmit the write command. */
180 	ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD,
181 				   SMI_CMD_OP_22_WRITE | (addr << 5) | reg);
182 	if (ret < 0)
183 		return ret;
184 
185 	/* Wait for the write command to complete. */
186 	ret = mv88e6xxx_smi_multi_chip_wait(chip);
187 	if (ret < 0)
188 		return ret;
189 
190 	return 0;
191 }
192 
193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = {
194 	.read = mv88e6xxx_smi_multi_chip_read,
195 	.write = mv88e6xxx_smi_multi_chip_write,
196 };
197 
198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val)
199 {
200 	int err;
201 
202 	assert_reg_lock(chip);
203 
204 	err = mv88e6xxx_smi_read(chip, addr, reg, val);
205 	if (err)
206 		return err;
207 
208 	dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
209 		addr, reg, *val);
210 
211 	return 0;
212 }
213 
214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val)
215 {
216 	int err;
217 
218 	assert_reg_lock(chip);
219 
220 	err = mv88e6xxx_smi_write(chip, addr, reg, val);
221 	if (err)
222 		return err;
223 
224 	dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n",
225 		addr, reg, val);
226 
227 	return 0;
228 }
229 
230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip)
231 {
232 	struct mv88e6xxx_mdio_bus *mdio_bus;
233 
234 	mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus,
235 				    list);
236 	if (!mdio_bus)
237 		return NULL;
238 
239 	return mdio_bus->bus;
240 }
241 
242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d)
243 {
244 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
245 	unsigned int n = d->hwirq;
246 
247 	chip->g1_irq.masked |= (1 << n);
248 }
249 
250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d)
251 {
252 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
253 	unsigned int n = d->hwirq;
254 
255 	chip->g1_irq.masked &= ~(1 << n);
256 }
257 
258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip)
259 {
260 	unsigned int nhandled = 0;
261 	unsigned int sub_irq;
262 	unsigned int n;
263 	u16 reg;
264 	int err;
265 
266 	mutex_lock(&chip->reg_lock);
267 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
268 	mutex_unlock(&chip->reg_lock);
269 
270 	if (err)
271 		goto out;
272 
273 	for (n = 0; n < chip->g1_irq.nirqs; ++n) {
274 		if (reg & (1 << n)) {
275 			sub_irq = irq_find_mapping(chip->g1_irq.domain, n);
276 			handle_nested_irq(sub_irq);
277 			++nhandled;
278 		}
279 	}
280 out:
281 	return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE);
282 }
283 
284 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id)
285 {
286 	struct mv88e6xxx_chip *chip = dev_id;
287 
288 	return mv88e6xxx_g1_irq_thread_work(chip);
289 }
290 
291 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d)
292 {
293 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
294 
295 	mutex_lock(&chip->reg_lock);
296 }
297 
298 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d)
299 {
300 	struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d);
301 	u16 mask = GENMASK(chip->g1_irq.nirqs, 0);
302 	u16 reg;
303 	int err;
304 
305 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &reg);
306 	if (err)
307 		goto out;
308 
309 	reg &= ~mask;
310 	reg |= (~chip->g1_irq.masked & mask);
311 
312 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg);
313 	if (err)
314 		goto out;
315 
316 out:
317 	mutex_unlock(&chip->reg_lock);
318 }
319 
320 static const struct irq_chip mv88e6xxx_g1_irq_chip = {
321 	.name			= "mv88e6xxx-g1",
322 	.irq_mask		= mv88e6xxx_g1_irq_mask,
323 	.irq_unmask		= mv88e6xxx_g1_irq_unmask,
324 	.irq_bus_lock		= mv88e6xxx_g1_irq_bus_lock,
325 	.irq_bus_sync_unlock	= mv88e6xxx_g1_irq_bus_sync_unlock,
326 };
327 
328 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d,
329 				       unsigned int irq,
330 				       irq_hw_number_t hwirq)
331 {
332 	struct mv88e6xxx_chip *chip = d->host_data;
333 
334 	irq_set_chip_data(irq, d->host_data);
335 	irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq);
336 	irq_set_noprobe(irq);
337 
338 	return 0;
339 }
340 
341 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = {
342 	.map	= mv88e6xxx_g1_irq_domain_map,
343 	.xlate	= irq_domain_xlate_twocell,
344 };
345 
346 /* To be called with reg_lock held */
347 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip)
348 {
349 	int irq, virq;
350 	u16 mask;
351 
352 	mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
353 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
354 	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
355 
356 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++) {
357 		virq = irq_find_mapping(chip->g1_irq.domain, irq);
358 		irq_dispose_mapping(virq);
359 	}
360 
361 	irq_domain_remove(chip->g1_irq.domain);
362 }
363 
364 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip)
365 {
366 	/*
367 	 * free_irq must be called without reg_lock taken because the irq
368 	 * handler takes this lock, too.
369 	 */
370 	free_irq(chip->irq, chip);
371 
372 	mutex_lock(&chip->reg_lock);
373 	mv88e6xxx_g1_irq_free_common(chip);
374 	mutex_unlock(&chip->reg_lock);
375 }
376 
377 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip)
378 {
379 	int err, irq, virq;
380 	u16 reg, mask;
381 
382 	chip->g1_irq.nirqs = chip->info->g1_irqs;
383 	chip->g1_irq.domain = irq_domain_add_simple(
384 		NULL, chip->g1_irq.nirqs, 0,
385 		&mv88e6xxx_g1_irq_domain_ops, chip);
386 	if (!chip->g1_irq.domain)
387 		return -ENOMEM;
388 
389 	for (irq = 0; irq < chip->g1_irq.nirqs; irq++)
390 		irq_create_mapping(chip->g1_irq.domain, irq);
391 
392 	chip->g1_irq.chip = mv88e6xxx_g1_irq_chip;
393 	chip->g1_irq.masked = ~0;
394 
395 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask);
396 	if (err)
397 		goto out_mapping;
398 
399 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
400 
401 	err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
402 	if (err)
403 		goto out_disable;
404 
405 	/* Reading the interrupt status clears (most of) them */
406 	err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, &reg);
407 	if (err)
408 		goto out_disable;
409 
410 	return 0;
411 
412 out_disable:
413 	mask &= ~GENMASK(chip->g1_irq.nirqs, 0);
414 	mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask);
415 
416 out_mapping:
417 	for (irq = 0; irq < 16; irq++) {
418 		virq = irq_find_mapping(chip->g1_irq.domain, irq);
419 		irq_dispose_mapping(virq);
420 	}
421 
422 	irq_domain_remove(chip->g1_irq.domain);
423 
424 	return err;
425 }
426 
427 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip)
428 {
429 	int err;
430 
431 	err = mv88e6xxx_g1_irq_setup_common(chip);
432 	if (err)
433 		return err;
434 
435 	err = request_threaded_irq(chip->irq, NULL,
436 				   mv88e6xxx_g1_irq_thread_fn,
437 				   IRQF_ONESHOT | IRQF_SHARED,
438 				   dev_name(chip->dev), chip);
439 	if (err)
440 		mv88e6xxx_g1_irq_free_common(chip);
441 
442 	return err;
443 }
444 
445 static void mv88e6xxx_irq_poll(struct kthread_work *work)
446 {
447 	struct mv88e6xxx_chip *chip = container_of(work,
448 						   struct mv88e6xxx_chip,
449 						   irq_poll_work.work);
450 	mv88e6xxx_g1_irq_thread_work(chip);
451 
452 	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
453 				   msecs_to_jiffies(100));
454 }
455 
456 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip)
457 {
458 	int err;
459 
460 	err = mv88e6xxx_g1_irq_setup_common(chip);
461 	if (err)
462 		return err;
463 
464 	kthread_init_delayed_work(&chip->irq_poll_work,
465 				  mv88e6xxx_irq_poll);
466 
467 	chip->kworker = kthread_create_worker(0, dev_name(chip->dev));
468 	if (IS_ERR(chip->kworker))
469 		return PTR_ERR(chip->kworker);
470 
471 	kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work,
472 				   msecs_to_jiffies(100));
473 
474 	return 0;
475 }
476 
477 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip)
478 {
479 	kthread_cancel_delayed_work_sync(&chip->irq_poll_work);
480 	kthread_destroy_worker(chip->kworker);
481 
482 	mutex_lock(&chip->reg_lock);
483 	mv88e6xxx_g1_irq_free_common(chip);
484 	mutex_unlock(&chip->reg_lock);
485 }
486 
487 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask)
488 {
489 	int i;
490 
491 	for (i = 0; i < 16; i++) {
492 		u16 val;
493 		int err;
494 
495 		err = mv88e6xxx_read(chip, addr, reg, &val);
496 		if (err)
497 			return err;
498 
499 		if (!(val & mask))
500 			return 0;
501 
502 		usleep_range(1000, 2000);
503 	}
504 
505 	dev_err(chip->dev, "Timeout while waiting for switch\n");
506 	return -ETIMEDOUT;
507 }
508 
509 /* Indirect write to single pointer-data register with an Update bit */
510 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update)
511 {
512 	u16 val;
513 	int err;
514 
515 	/* Wait until the previous operation is completed */
516 	err = mv88e6xxx_wait(chip, addr, reg, BIT(15));
517 	if (err)
518 		return err;
519 
520 	/* Set the Update bit to trigger a write operation */
521 	val = BIT(15) | update;
522 
523 	return mv88e6xxx_write(chip, addr, reg, val);
524 }
525 
526 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port,
527 				    int link, int speed, int duplex, int pause,
528 				    phy_interface_t mode)
529 {
530 	int err;
531 
532 	if (!chip->info->ops->port_set_link)
533 		return 0;
534 
535 	/* Port's MAC control must not be changed unless the link is down */
536 	err = chip->info->ops->port_set_link(chip, port, 0);
537 	if (err)
538 		return err;
539 
540 	if (chip->info->ops->port_set_speed) {
541 		err = chip->info->ops->port_set_speed(chip, port, speed);
542 		if (err && err != -EOPNOTSUPP)
543 			goto restore_link;
544 	}
545 
546 	if (chip->info->ops->port_set_pause) {
547 		err = chip->info->ops->port_set_pause(chip, port, pause);
548 		if (err)
549 			goto restore_link;
550 	}
551 
552 	if (chip->info->ops->port_set_duplex) {
553 		err = chip->info->ops->port_set_duplex(chip, port, duplex);
554 		if (err && err != -EOPNOTSUPP)
555 			goto restore_link;
556 	}
557 
558 	if (chip->info->ops->port_set_rgmii_delay) {
559 		err = chip->info->ops->port_set_rgmii_delay(chip, port, mode);
560 		if (err && err != -EOPNOTSUPP)
561 			goto restore_link;
562 	}
563 
564 	if (chip->info->ops->port_set_cmode) {
565 		err = chip->info->ops->port_set_cmode(chip, port, mode);
566 		if (err && err != -EOPNOTSUPP)
567 			goto restore_link;
568 	}
569 
570 	err = 0;
571 restore_link:
572 	if (chip->info->ops->port_set_link(chip, port, link))
573 		dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port);
574 
575 	return err;
576 }
577 
578 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port)
579 {
580 	struct mv88e6xxx_chip *chip = ds->priv;
581 
582 	return port < chip->info->num_internal_phys;
583 }
584 
585 /* We expect the switch to perform auto negotiation if there is a real
586  * phy. However, in the case of a fixed link phy, we force the port
587  * settings from the fixed link settings.
588  */
589 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port,
590 				  struct phy_device *phydev)
591 {
592 	struct mv88e6xxx_chip *chip = ds->priv;
593 	int err;
594 
595 	if (!phy_is_pseudo_fixed_link(phydev) &&
596 	    mv88e6xxx_phy_is_internal(ds, port))
597 		return;
598 
599 	mutex_lock(&chip->reg_lock);
600 	err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed,
601 				       phydev->duplex, phydev->pause,
602 				       phydev->interface);
603 	mutex_unlock(&chip->reg_lock);
604 
605 	if (err && err != -EOPNOTSUPP)
606 		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
607 }
608 
609 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port,
610 				       unsigned long *mask,
611 				       struct phylink_link_state *state)
612 {
613 	if (!phy_interface_mode_is_8023z(state->interface)) {
614 		/* 10M and 100M are only supported in non-802.3z mode */
615 		phylink_set(mask, 10baseT_Half);
616 		phylink_set(mask, 10baseT_Full);
617 		phylink_set(mask, 100baseT_Half);
618 		phylink_set(mask, 100baseT_Full);
619 	}
620 }
621 
622 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port,
623 				       unsigned long *mask,
624 				       struct phylink_link_state *state)
625 {
626 	/* FIXME: if the port is in 1000Base-X mode, then it only supports
627 	 * 1000M FD speeds.  In this case, CMODE will indicate 5.
628 	 */
629 	phylink_set(mask, 1000baseT_Full);
630 	phylink_set(mask, 1000baseX_Full);
631 
632 	mv88e6065_phylink_validate(chip, port, mask, state);
633 }
634 
635 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port,
636 				       unsigned long *mask,
637 				       struct phylink_link_state *state)
638 {
639 	/* No ethtool bits for 200Mbps */
640 	phylink_set(mask, 1000baseT_Full);
641 	phylink_set(mask, 1000baseX_Full);
642 
643 	mv88e6065_phylink_validate(chip, port, mask, state);
644 }
645 
646 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port,
647 				       unsigned long *mask,
648 				       struct phylink_link_state *state)
649 {
650 	if (port >= 9)
651 		phylink_set(mask, 2500baseX_Full);
652 
653 	/* No ethtool bits for 200Mbps */
654 	phylink_set(mask, 1000baseT_Full);
655 	phylink_set(mask, 1000baseX_Full);
656 
657 	mv88e6065_phylink_validate(chip, port, mask, state);
658 }
659 
660 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port,
661 					unsigned long *mask,
662 					struct phylink_link_state *state)
663 {
664 	if (port >= 9) {
665 		phylink_set(mask, 10000baseT_Full);
666 		phylink_set(mask, 10000baseKR_Full);
667 	}
668 
669 	mv88e6390_phylink_validate(chip, port, mask, state);
670 }
671 
672 static void mv88e6xxx_validate(struct dsa_switch *ds, int port,
673 			       unsigned long *supported,
674 			       struct phylink_link_state *state)
675 {
676 	__ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, };
677 	struct mv88e6xxx_chip *chip = ds->priv;
678 
679 	/* Allow all the expected bits */
680 	phylink_set(mask, Autoneg);
681 	phylink_set(mask, Pause);
682 	phylink_set_port_modes(mask);
683 
684 	if (chip->info->ops->phylink_validate)
685 		chip->info->ops->phylink_validate(chip, port, mask, state);
686 
687 	bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS);
688 	bitmap_and(state->advertising, state->advertising, mask,
689 		   __ETHTOOL_LINK_MODE_MASK_NBITS);
690 
691 	/* We can only operate at 2500BaseX or 1000BaseX.  If requested
692 	 * to advertise both, only report advertising at 2500BaseX.
693 	 */
694 	phylink_helper_basex_speed(state);
695 }
696 
697 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port,
698 				struct phylink_link_state *state)
699 {
700 	struct mv88e6xxx_chip *chip = ds->priv;
701 	int err;
702 
703 	mutex_lock(&chip->reg_lock);
704 	if (chip->info->ops->port_link_state)
705 		err = chip->info->ops->port_link_state(chip, port, state);
706 	else
707 		err = -EOPNOTSUPP;
708 	mutex_unlock(&chip->reg_lock);
709 
710 	return err;
711 }
712 
713 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port,
714 				 unsigned int mode,
715 				 const struct phylink_link_state *state)
716 {
717 	struct mv88e6xxx_chip *chip = ds->priv;
718 	int speed, duplex, link, pause, err;
719 
720 	if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port))
721 		return;
722 
723 	if (mode == MLO_AN_FIXED) {
724 		link = LINK_FORCED_UP;
725 		speed = state->speed;
726 		duplex = state->duplex;
727 	} else if (!mv88e6xxx_phy_is_internal(ds, port)) {
728 		link = state->link;
729 		speed = state->speed;
730 		duplex = state->duplex;
731 	} else {
732 		speed = SPEED_UNFORCED;
733 		duplex = DUPLEX_UNFORCED;
734 		link = LINK_UNFORCED;
735 	}
736 	pause = !!phylink_test(state->advertising, Pause);
737 
738 	mutex_lock(&chip->reg_lock);
739 	err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause,
740 				       state->interface);
741 	mutex_unlock(&chip->reg_lock);
742 
743 	if (err && err != -EOPNOTSUPP)
744 		dev_err(ds->dev, "p%d: failed to configure MAC\n", port);
745 }
746 
747 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link)
748 {
749 	struct mv88e6xxx_chip *chip = ds->priv;
750 	int err;
751 
752 	mutex_lock(&chip->reg_lock);
753 	err = chip->info->ops->port_set_link(chip, port, link);
754 	mutex_unlock(&chip->reg_lock);
755 
756 	if (err)
757 		dev_err(chip->dev, "p%d: failed to force MAC link\n", port);
758 }
759 
760 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port,
761 				    unsigned int mode,
762 				    phy_interface_t interface)
763 {
764 	if (mode == MLO_AN_FIXED)
765 		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN);
766 }
767 
768 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port,
769 				  unsigned int mode, phy_interface_t interface,
770 				  struct phy_device *phydev)
771 {
772 	if (mode == MLO_AN_FIXED)
773 		mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP);
774 }
775 
776 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port)
777 {
778 	if (!chip->info->ops->stats_snapshot)
779 		return -EOPNOTSUPP;
780 
781 	return chip->info->ops->stats_snapshot(chip, port);
782 }
783 
784 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = {
785 	{ "in_good_octets",		8, 0x00, STATS_TYPE_BANK0, },
786 	{ "in_bad_octets",		4, 0x02, STATS_TYPE_BANK0, },
787 	{ "in_unicast",			4, 0x04, STATS_TYPE_BANK0, },
788 	{ "in_broadcasts",		4, 0x06, STATS_TYPE_BANK0, },
789 	{ "in_multicasts",		4, 0x07, STATS_TYPE_BANK0, },
790 	{ "in_pause",			4, 0x16, STATS_TYPE_BANK0, },
791 	{ "in_undersize",		4, 0x18, STATS_TYPE_BANK0, },
792 	{ "in_fragments",		4, 0x19, STATS_TYPE_BANK0, },
793 	{ "in_oversize",		4, 0x1a, STATS_TYPE_BANK0, },
794 	{ "in_jabber",			4, 0x1b, STATS_TYPE_BANK0, },
795 	{ "in_rx_error",		4, 0x1c, STATS_TYPE_BANK0, },
796 	{ "in_fcs_error",		4, 0x1d, STATS_TYPE_BANK0, },
797 	{ "out_octets",			8, 0x0e, STATS_TYPE_BANK0, },
798 	{ "out_unicast",		4, 0x10, STATS_TYPE_BANK0, },
799 	{ "out_broadcasts",		4, 0x13, STATS_TYPE_BANK0, },
800 	{ "out_multicasts",		4, 0x12, STATS_TYPE_BANK0, },
801 	{ "out_pause",			4, 0x15, STATS_TYPE_BANK0, },
802 	{ "excessive",			4, 0x11, STATS_TYPE_BANK0, },
803 	{ "collisions",			4, 0x1e, STATS_TYPE_BANK0, },
804 	{ "deferred",			4, 0x05, STATS_TYPE_BANK0, },
805 	{ "single",			4, 0x14, STATS_TYPE_BANK0, },
806 	{ "multiple",			4, 0x17, STATS_TYPE_BANK0, },
807 	{ "out_fcs_error",		4, 0x03, STATS_TYPE_BANK0, },
808 	{ "late",			4, 0x1f, STATS_TYPE_BANK0, },
809 	{ "hist_64bytes",		4, 0x08, STATS_TYPE_BANK0, },
810 	{ "hist_65_127bytes",		4, 0x09, STATS_TYPE_BANK0, },
811 	{ "hist_128_255bytes",		4, 0x0a, STATS_TYPE_BANK0, },
812 	{ "hist_256_511bytes",		4, 0x0b, STATS_TYPE_BANK0, },
813 	{ "hist_512_1023bytes",		4, 0x0c, STATS_TYPE_BANK0, },
814 	{ "hist_1024_max_bytes",	4, 0x0d, STATS_TYPE_BANK0, },
815 	{ "sw_in_discards",		4, 0x10, STATS_TYPE_PORT, },
816 	{ "sw_in_filtered",		2, 0x12, STATS_TYPE_PORT, },
817 	{ "sw_out_filtered",		2, 0x13, STATS_TYPE_PORT, },
818 	{ "in_discards",		4, 0x00, STATS_TYPE_BANK1, },
819 	{ "in_filtered",		4, 0x01, STATS_TYPE_BANK1, },
820 	{ "in_accepted",		4, 0x02, STATS_TYPE_BANK1, },
821 	{ "in_bad_accepted",		4, 0x03, STATS_TYPE_BANK1, },
822 	{ "in_good_avb_class_a",	4, 0x04, STATS_TYPE_BANK1, },
823 	{ "in_good_avb_class_b",	4, 0x05, STATS_TYPE_BANK1, },
824 	{ "in_bad_avb_class_a",		4, 0x06, STATS_TYPE_BANK1, },
825 	{ "in_bad_avb_class_b",		4, 0x07, STATS_TYPE_BANK1, },
826 	{ "tcam_counter_0",		4, 0x08, STATS_TYPE_BANK1, },
827 	{ "tcam_counter_1",		4, 0x09, STATS_TYPE_BANK1, },
828 	{ "tcam_counter_2",		4, 0x0a, STATS_TYPE_BANK1, },
829 	{ "tcam_counter_3",		4, 0x0b, STATS_TYPE_BANK1, },
830 	{ "in_da_unknown",		4, 0x0e, STATS_TYPE_BANK1, },
831 	{ "in_management",		4, 0x0f, STATS_TYPE_BANK1, },
832 	{ "out_queue_0",		4, 0x10, STATS_TYPE_BANK1, },
833 	{ "out_queue_1",		4, 0x11, STATS_TYPE_BANK1, },
834 	{ "out_queue_2",		4, 0x12, STATS_TYPE_BANK1, },
835 	{ "out_queue_3",		4, 0x13, STATS_TYPE_BANK1, },
836 	{ "out_queue_4",		4, 0x14, STATS_TYPE_BANK1, },
837 	{ "out_queue_5",		4, 0x15, STATS_TYPE_BANK1, },
838 	{ "out_queue_6",		4, 0x16, STATS_TYPE_BANK1, },
839 	{ "out_queue_7",		4, 0x17, STATS_TYPE_BANK1, },
840 	{ "out_cut_through",		4, 0x18, STATS_TYPE_BANK1, },
841 	{ "out_octets_a",		4, 0x1a, STATS_TYPE_BANK1, },
842 	{ "out_octets_b",		4, 0x1b, STATS_TYPE_BANK1, },
843 	{ "out_management",		4, 0x1f, STATS_TYPE_BANK1, },
844 };
845 
846 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip,
847 					    struct mv88e6xxx_hw_stat *s,
848 					    int port, u16 bank1_select,
849 					    u16 histogram)
850 {
851 	u32 low;
852 	u32 high = 0;
853 	u16 reg = 0;
854 	int err;
855 	u64 value;
856 
857 	switch (s->type) {
858 	case STATS_TYPE_PORT:
859 		err = mv88e6xxx_port_read(chip, port, s->reg, &reg);
860 		if (err)
861 			return U64_MAX;
862 
863 		low = reg;
864 		if (s->size == 4) {
865 			err = mv88e6xxx_port_read(chip, port, s->reg + 1, &reg);
866 			if (err)
867 				return U64_MAX;
868 			high = reg;
869 		}
870 		break;
871 	case STATS_TYPE_BANK1:
872 		reg = bank1_select;
873 		/* fall through */
874 	case STATS_TYPE_BANK0:
875 		reg |= s->reg | histogram;
876 		mv88e6xxx_g1_stats_read(chip, reg, &low);
877 		if (s->size == 8)
878 			mv88e6xxx_g1_stats_read(chip, reg + 1, &high);
879 		break;
880 	default:
881 		return U64_MAX;
882 	}
883 	value = (((u64)high) << 16) | low;
884 	return value;
885 }
886 
887 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip,
888 				       uint8_t *data, int types)
889 {
890 	struct mv88e6xxx_hw_stat *stat;
891 	int i, j;
892 
893 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
894 		stat = &mv88e6xxx_hw_stats[i];
895 		if (stat->type & types) {
896 			memcpy(data + j * ETH_GSTRING_LEN, stat->string,
897 			       ETH_GSTRING_LEN);
898 			j++;
899 		}
900 	}
901 
902 	return j;
903 }
904 
905 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip,
906 				       uint8_t *data)
907 {
908 	return mv88e6xxx_stats_get_strings(chip, data,
909 					   STATS_TYPE_BANK0 | STATS_TYPE_PORT);
910 }
911 
912 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip,
913 				       uint8_t *data)
914 {
915 	return mv88e6xxx_stats_get_strings(chip, data,
916 					   STATS_TYPE_BANK0 | STATS_TYPE_BANK1);
917 }
918 
919 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = {
920 	"atu_member_violation",
921 	"atu_miss_violation",
922 	"atu_full_violation",
923 	"vtu_member_violation",
924 	"vtu_miss_violation",
925 };
926 
927 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data)
928 {
929 	unsigned int i;
930 
931 	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++)
932 		strlcpy(data + i * ETH_GSTRING_LEN,
933 			mv88e6xxx_atu_vtu_stats_strings[i],
934 			ETH_GSTRING_LEN);
935 }
936 
937 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port,
938 				  u32 stringset, uint8_t *data)
939 {
940 	struct mv88e6xxx_chip *chip = ds->priv;
941 	int count = 0;
942 
943 	if (stringset != ETH_SS_STATS)
944 		return;
945 
946 	mutex_lock(&chip->reg_lock);
947 
948 	if (chip->info->ops->stats_get_strings)
949 		count = chip->info->ops->stats_get_strings(chip, data);
950 
951 	if (chip->info->ops->serdes_get_strings) {
952 		data += count * ETH_GSTRING_LEN;
953 		count = chip->info->ops->serdes_get_strings(chip, port, data);
954 	}
955 
956 	data += count * ETH_GSTRING_LEN;
957 	mv88e6xxx_atu_vtu_get_strings(data);
958 
959 	mutex_unlock(&chip->reg_lock);
960 }
961 
962 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip,
963 					  int types)
964 {
965 	struct mv88e6xxx_hw_stat *stat;
966 	int i, j;
967 
968 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
969 		stat = &mv88e6xxx_hw_stats[i];
970 		if (stat->type & types)
971 			j++;
972 	}
973 	return j;
974 }
975 
976 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip)
977 {
978 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
979 					      STATS_TYPE_PORT);
980 }
981 
982 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip)
983 {
984 	return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 |
985 					      STATS_TYPE_BANK1);
986 }
987 
988 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset)
989 {
990 	struct mv88e6xxx_chip *chip = ds->priv;
991 	int serdes_count = 0;
992 	int count = 0;
993 
994 	if (sset != ETH_SS_STATS)
995 		return 0;
996 
997 	mutex_lock(&chip->reg_lock);
998 	if (chip->info->ops->stats_get_sset_count)
999 		count = chip->info->ops->stats_get_sset_count(chip);
1000 	if (count < 0)
1001 		goto out;
1002 
1003 	if (chip->info->ops->serdes_get_sset_count)
1004 		serdes_count = chip->info->ops->serdes_get_sset_count(chip,
1005 								      port);
1006 	if (serdes_count < 0) {
1007 		count = serdes_count;
1008 		goto out;
1009 	}
1010 	count += serdes_count;
1011 	count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings);
1012 
1013 out:
1014 	mutex_unlock(&chip->reg_lock);
1015 
1016 	return count;
1017 }
1018 
1019 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1020 				     uint64_t *data, int types,
1021 				     u16 bank1_select, u16 histogram)
1022 {
1023 	struct mv88e6xxx_hw_stat *stat;
1024 	int i, j;
1025 
1026 	for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) {
1027 		stat = &mv88e6xxx_hw_stats[i];
1028 		if (stat->type & types) {
1029 			mutex_lock(&chip->reg_lock);
1030 			data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port,
1031 							      bank1_select,
1032 							      histogram);
1033 			mutex_unlock(&chip->reg_lock);
1034 
1035 			j++;
1036 		}
1037 	}
1038 	return j;
1039 }
1040 
1041 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1042 				     uint64_t *data)
1043 {
1044 	return mv88e6xxx_stats_get_stats(chip, port, data,
1045 					 STATS_TYPE_BANK0 | STATS_TYPE_PORT,
1046 					 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1047 }
1048 
1049 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1050 				     uint64_t *data)
1051 {
1052 	return mv88e6xxx_stats_get_stats(chip, port, data,
1053 					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1054 					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9,
1055 					 MV88E6XXX_G1_STATS_OP_HIST_RX_TX);
1056 }
1057 
1058 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port,
1059 				     uint64_t *data)
1060 {
1061 	return mv88e6xxx_stats_get_stats(chip, port, data,
1062 					 STATS_TYPE_BANK0 | STATS_TYPE_BANK1,
1063 					 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10,
1064 					 0);
1065 }
1066 
1067 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port,
1068 					uint64_t *data)
1069 {
1070 	*data++ = chip->ports[port].atu_member_violation;
1071 	*data++ = chip->ports[port].atu_miss_violation;
1072 	*data++ = chip->ports[port].atu_full_violation;
1073 	*data++ = chip->ports[port].vtu_member_violation;
1074 	*data++ = chip->ports[port].vtu_miss_violation;
1075 }
1076 
1077 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port,
1078 				uint64_t *data)
1079 {
1080 	int count = 0;
1081 
1082 	if (chip->info->ops->stats_get_stats)
1083 		count = chip->info->ops->stats_get_stats(chip, port, data);
1084 
1085 	mutex_lock(&chip->reg_lock);
1086 	if (chip->info->ops->serdes_get_stats) {
1087 		data += count;
1088 		count = chip->info->ops->serdes_get_stats(chip, port, data);
1089 	}
1090 	data += count;
1091 	mv88e6xxx_atu_vtu_get_stats(chip, port, data);
1092 	mutex_unlock(&chip->reg_lock);
1093 }
1094 
1095 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port,
1096 					uint64_t *data)
1097 {
1098 	struct mv88e6xxx_chip *chip = ds->priv;
1099 	int ret;
1100 
1101 	mutex_lock(&chip->reg_lock);
1102 
1103 	ret = mv88e6xxx_stats_snapshot(chip, port);
1104 	mutex_unlock(&chip->reg_lock);
1105 
1106 	if (ret < 0)
1107 		return;
1108 
1109 	mv88e6xxx_get_stats(chip, port, data);
1110 
1111 }
1112 
1113 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port)
1114 {
1115 	return 32 * sizeof(u16);
1116 }
1117 
1118 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port,
1119 			       struct ethtool_regs *regs, void *_p)
1120 {
1121 	struct mv88e6xxx_chip *chip = ds->priv;
1122 	int err;
1123 	u16 reg;
1124 	u16 *p = _p;
1125 	int i;
1126 
1127 	regs->version = chip->info->prod_num;
1128 
1129 	memset(p, 0xff, 32 * sizeof(u16));
1130 
1131 	mutex_lock(&chip->reg_lock);
1132 
1133 	for (i = 0; i < 32; i++) {
1134 
1135 		err = mv88e6xxx_port_read(chip, port, i, &reg);
1136 		if (!err)
1137 			p[i] = reg;
1138 	}
1139 
1140 	mutex_unlock(&chip->reg_lock);
1141 }
1142 
1143 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port,
1144 				 struct ethtool_eee *e)
1145 {
1146 	/* Nothing to do on the port's MAC */
1147 	return 0;
1148 }
1149 
1150 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port,
1151 				 struct ethtool_eee *e)
1152 {
1153 	/* Nothing to do on the port's MAC */
1154 	return 0;
1155 }
1156 
1157 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port)
1158 {
1159 	struct dsa_switch *ds = NULL;
1160 	struct net_device *br;
1161 	u16 pvlan;
1162 	int i;
1163 
1164 	if (dev < DSA_MAX_SWITCHES)
1165 		ds = chip->ds->dst->ds[dev];
1166 
1167 	/* Prevent frames from unknown switch or port */
1168 	if (!ds || port >= ds->num_ports)
1169 		return 0;
1170 
1171 	/* Frames from DSA links and CPU ports can egress any local port */
1172 	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
1173 		return mv88e6xxx_port_mask(chip);
1174 
1175 	br = ds->ports[port].bridge_dev;
1176 	pvlan = 0;
1177 
1178 	/* Frames from user ports can egress any local DSA links and CPU ports,
1179 	 * as well as any local member of their bridge group.
1180 	 */
1181 	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1182 		if (dsa_is_cpu_port(chip->ds, i) ||
1183 		    dsa_is_dsa_port(chip->ds, i) ||
1184 		    (br && dsa_to_port(chip->ds, i)->bridge_dev == br))
1185 			pvlan |= BIT(i);
1186 
1187 	return pvlan;
1188 }
1189 
1190 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port)
1191 {
1192 	u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port);
1193 
1194 	/* prevent frames from going back out of the port they came in on */
1195 	output_ports &= ~BIT(port);
1196 
1197 	return mv88e6xxx_port_set_vlan_map(chip, port, output_ports);
1198 }
1199 
1200 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port,
1201 					 u8 state)
1202 {
1203 	struct mv88e6xxx_chip *chip = ds->priv;
1204 	int err;
1205 
1206 	mutex_lock(&chip->reg_lock);
1207 	err = mv88e6xxx_port_set_state(chip, port, state);
1208 	mutex_unlock(&chip->reg_lock);
1209 
1210 	if (err)
1211 		dev_err(ds->dev, "p%d: failed to update state\n", port);
1212 }
1213 
1214 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip)
1215 {
1216 	int err;
1217 
1218 	if (chip->info->ops->ieee_pri_map) {
1219 		err = chip->info->ops->ieee_pri_map(chip);
1220 		if (err)
1221 			return err;
1222 	}
1223 
1224 	if (chip->info->ops->ip_pri_map) {
1225 		err = chip->info->ops->ip_pri_map(chip);
1226 		if (err)
1227 			return err;
1228 	}
1229 
1230 	return 0;
1231 }
1232 
1233 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip)
1234 {
1235 	int target, port;
1236 	int err;
1237 
1238 	if (!chip->info->global2_addr)
1239 		return 0;
1240 
1241 	/* Initialize the routing port to the 32 possible target devices */
1242 	for (target = 0; target < 32; target++) {
1243 		port = 0x1f;
1244 		if (target < DSA_MAX_SWITCHES)
1245 			if (chip->ds->rtable[target] != DSA_RTABLE_NONE)
1246 				port = chip->ds->rtable[target];
1247 
1248 		err = mv88e6xxx_g2_device_mapping_write(chip, target, port);
1249 		if (err)
1250 			return err;
1251 	}
1252 
1253 	if (chip->info->ops->set_cascade_port) {
1254 		port = MV88E6XXX_CASCADE_PORT_MULTIPLE;
1255 		err = chip->info->ops->set_cascade_port(chip, port);
1256 		if (err)
1257 			return err;
1258 	}
1259 
1260 	err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index);
1261 	if (err)
1262 		return err;
1263 
1264 	return 0;
1265 }
1266 
1267 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip)
1268 {
1269 	/* Clear all trunk masks and mapping */
1270 	if (chip->info->global2_addr)
1271 		return mv88e6xxx_g2_trunk_clear(chip);
1272 
1273 	return 0;
1274 }
1275 
1276 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip)
1277 {
1278 	if (chip->info->ops->rmu_disable)
1279 		return chip->info->ops->rmu_disable(chip);
1280 
1281 	return 0;
1282 }
1283 
1284 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip)
1285 {
1286 	if (chip->info->ops->pot_clear)
1287 		return chip->info->ops->pot_clear(chip);
1288 
1289 	return 0;
1290 }
1291 
1292 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip)
1293 {
1294 	if (chip->info->ops->mgmt_rsvd2cpu)
1295 		return chip->info->ops->mgmt_rsvd2cpu(chip);
1296 
1297 	return 0;
1298 }
1299 
1300 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip)
1301 {
1302 	int err;
1303 
1304 	err = mv88e6xxx_g1_atu_flush(chip, 0, true);
1305 	if (err)
1306 		return err;
1307 
1308 	err = mv88e6xxx_g1_atu_set_learn2all(chip, true);
1309 	if (err)
1310 		return err;
1311 
1312 	return mv88e6xxx_g1_atu_set_age_time(chip, 300000);
1313 }
1314 
1315 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip)
1316 {
1317 	int port;
1318 	int err;
1319 
1320 	if (!chip->info->ops->irl_init_all)
1321 		return 0;
1322 
1323 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1324 		/* Disable ingress rate limiting by resetting all per port
1325 		 * ingress rate limit resources to their initial state.
1326 		 */
1327 		err = chip->info->ops->irl_init_all(chip, port);
1328 		if (err)
1329 			return err;
1330 	}
1331 
1332 	return 0;
1333 }
1334 
1335 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip)
1336 {
1337 	if (chip->info->ops->set_switch_mac) {
1338 		u8 addr[ETH_ALEN];
1339 
1340 		eth_random_addr(addr);
1341 
1342 		return chip->info->ops->set_switch_mac(chip, addr);
1343 	}
1344 
1345 	return 0;
1346 }
1347 
1348 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port)
1349 {
1350 	u16 pvlan = 0;
1351 
1352 	if (!mv88e6xxx_has_pvt(chip))
1353 		return -EOPNOTSUPP;
1354 
1355 	/* Skip the local source device, which uses in-chip port VLAN */
1356 	if (dev != chip->ds->index)
1357 		pvlan = mv88e6xxx_port_vlan(chip, dev, port);
1358 
1359 	return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan);
1360 }
1361 
1362 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip)
1363 {
1364 	int dev, port;
1365 	int err;
1366 
1367 	if (!mv88e6xxx_has_pvt(chip))
1368 		return 0;
1369 
1370 	/* Clear 5 Bit Port for usage with Marvell Link Street devices:
1371 	 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev.
1372 	 */
1373 	err = mv88e6xxx_g2_misc_4_bit_port(chip);
1374 	if (err)
1375 		return err;
1376 
1377 	for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) {
1378 		for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) {
1379 			err = mv88e6xxx_pvt_map(chip, dev, port);
1380 			if (err)
1381 				return err;
1382 		}
1383 	}
1384 
1385 	return 0;
1386 }
1387 
1388 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port)
1389 {
1390 	struct mv88e6xxx_chip *chip = ds->priv;
1391 	int err;
1392 
1393 	mutex_lock(&chip->reg_lock);
1394 	err = mv88e6xxx_g1_atu_remove(chip, 0, port, false);
1395 	mutex_unlock(&chip->reg_lock);
1396 
1397 	if (err)
1398 		dev_err(ds->dev, "p%d: failed to flush ATU\n", port);
1399 }
1400 
1401 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip)
1402 {
1403 	if (!chip->info->max_vid)
1404 		return 0;
1405 
1406 	return mv88e6xxx_g1_vtu_flush(chip);
1407 }
1408 
1409 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip,
1410 				 struct mv88e6xxx_vtu_entry *entry)
1411 {
1412 	if (!chip->info->ops->vtu_getnext)
1413 		return -EOPNOTSUPP;
1414 
1415 	return chip->info->ops->vtu_getnext(chip, entry);
1416 }
1417 
1418 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip,
1419 				   struct mv88e6xxx_vtu_entry *entry)
1420 {
1421 	if (!chip->info->ops->vtu_loadpurge)
1422 		return -EOPNOTSUPP;
1423 
1424 	return chip->info->ops->vtu_loadpurge(chip, entry);
1425 }
1426 
1427 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid)
1428 {
1429 	DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID);
1430 	struct mv88e6xxx_vtu_entry vlan = {
1431 		.vid = chip->info->max_vid,
1432 	};
1433 	int i, err;
1434 
1435 	bitmap_zero(fid_bitmap, MV88E6XXX_N_FID);
1436 
1437 	/* Set every FID bit used by the (un)bridged ports */
1438 	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1439 		err = mv88e6xxx_port_get_fid(chip, i, fid);
1440 		if (err)
1441 			return err;
1442 
1443 		set_bit(*fid, fid_bitmap);
1444 	}
1445 
1446 	/* Set every FID bit used by the VLAN entries */
1447 	do {
1448 		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1449 		if (err)
1450 			return err;
1451 
1452 		if (!vlan.valid)
1453 			break;
1454 
1455 		set_bit(vlan.fid, fid_bitmap);
1456 	} while (vlan.vid < chip->info->max_vid);
1457 
1458 	/* The reset value 0x000 is used to indicate that multiple address
1459 	 * databases are not needed. Return the next positive available.
1460 	 */
1461 	*fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1);
1462 	if (unlikely(*fid >= mv88e6xxx_num_databases(chip)))
1463 		return -ENOSPC;
1464 
1465 	/* Clear the database */
1466 	return mv88e6xxx_g1_atu_flush(chip, *fid, true);
1467 }
1468 
1469 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid,
1470 			     struct mv88e6xxx_vtu_entry *entry, bool new)
1471 {
1472 	int err;
1473 
1474 	if (!vid)
1475 		return -EINVAL;
1476 
1477 	entry->vid = vid - 1;
1478 	entry->valid = false;
1479 
1480 	err = mv88e6xxx_vtu_getnext(chip, entry);
1481 	if (err)
1482 		return err;
1483 
1484 	if (entry->vid == vid && entry->valid)
1485 		return 0;
1486 
1487 	if (new) {
1488 		int i;
1489 
1490 		/* Initialize a fresh VLAN entry */
1491 		memset(entry, 0, sizeof(*entry));
1492 		entry->valid = true;
1493 		entry->vid = vid;
1494 
1495 		/* Exclude all ports */
1496 		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i)
1497 			entry->member[i] =
1498 				MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1499 
1500 		return mv88e6xxx_atu_new(chip, &entry->fid);
1501 	}
1502 
1503 	/* switchdev expects -EOPNOTSUPP to honor software VLANs */
1504 	return -EOPNOTSUPP;
1505 }
1506 
1507 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port,
1508 					u16 vid_begin, u16 vid_end)
1509 {
1510 	struct mv88e6xxx_chip *chip = ds->priv;
1511 	struct mv88e6xxx_vtu_entry vlan = {
1512 		.vid = vid_begin - 1,
1513 	};
1514 	int i, err;
1515 
1516 	/* DSA and CPU ports have to be members of multiple vlans */
1517 	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1518 		return 0;
1519 
1520 	if (!vid_begin)
1521 		return -EOPNOTSUPP;
1522 
1523 	mutex_lock(&chip->reg_lock);
1524 
1525 	do {
1526 		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1527 		if (err)
1528 			goto unlock;
1529 
1530 		if (!vlan.valid)
1531 			break;
1532 
1533 		if (vlan.vid > vid_end)
1534 			break;
1535 
1536 		for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1537 			if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i))
1538 				continue;
1539 
1540 			if (!ds->ports[i].slave)
1541 				continue;
1542 
1543 			if (vlan.member[i] ==
1544 			    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1545 				continue;
1546 
1547 			if (dsa_to_port(ds, i)->bridge_dev ==
1548 			    ds->ports[port].bridge_dev)
1549 				break; /* same bridge, check next VLAN */
1550 
1551 			if (!dsa_to_port(ds, i)->bridge_dev)
1552 				continue;
1553 
1554 			dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n",
1555 				port, vlan.vid, i,
1556 				netdev_name(dsa_to_port(ds, i)->bridge_dev));
1557 			err = -EOPNOTSUPP;
1558 			goto unlock;
1559 		}
1560 	} while (vlan.vid < vid_end);
1561 
1562 unlock:
1563 	mutex_unlock(&chip->reg_lock);
1564 
1565 	return err;
1566 }
1567 
1568 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port,
1569 					 bool vlan_filtering)
1570 {
1571 	struct mv88e6xxx_chip *chip = ds->priv;
1572 	u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE :
1573 		MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED;
1574 	int err;
1575 
1576 	if (!chip->info->max_vid)
1577 		return -EOPNOTSUPP;
1578 
1579 	mutex_lock(&chip->reg_lock);
1580 	err = mv88e6xxx_port_set_8021q_mode(chip, port, mode);
1581 	mutex_unlock(&chip->reg_lock);
1582 
1583 	return err;
1584 }
1585 
1586 static int
1587 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port,
1588 			    const struct switchdev_obj_port_vlan *vlan)
1589 {
1590 	struct mv88e6xxx_chip *chip = ds->priv;
1591 	int err;
1592 
1593 	if (!chip->info->max_vid)
1594 		return -EOPNOTSUPP;
1595 
1596 	/* If the requested port doesn't belong to the same bridge as the VLAN
1597 	 * members, do not support it (yet) and fallback to software VLAN.
1598 	 */
1599 	err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin,
1600 					   vlan->vid_end);
1601 	if (err)
1602 		return err;
1603 
1604 	/* We don't need any dynamic resource from the kernel (yet),
1605 	 * so skip the prepare phase.
1606 	 */
1607 	return 0;
1608 }
1609 
1610 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port,
1611 					const unsigned char *addr, u16 vid,
1612 					u8 state)
1613 {
1614 	struct mv88e6xxx_vtu_entry vlan;
1615 	struct mv88e6xxx_atu_entry entry;
1616 	int err;
1617 
1618 	/* Null VLAN ID corresponds to the port private database */
1619 	if (vid == 0)
1620 		err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid);
1621 	else
1622 		err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1623 	if (err)
1624 		return err;
1625 
1626 	entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1627 	ether_addr_copy(entry.mac, addr);
1628 	eth_addr_dec(entry.mac);
1629 
1630 	err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry);
1631 	if (err)
1632 		return err;
1633 
1634 	/* Initialize a fresh ATU entry if it isn't found */
1635 	if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED ||
1636 	    !ether_addr_equal(entry.mac, addr)) {
1637 		memset(&entry, 0, sizeof(entry));
1638 		ether_addr_copy(entry.mac, addr);
1639 	}
1640 
1641 	/* Purge the ATU entry only if no port is using it anymore */
1642 	if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) {
1643 		entry.portvec &= ~BIT(port);
1644 		if (!entry.portvec)
1645 			entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1646 	} else {
1647 		entry.portvec |= BIT(port);
1648 		entry.state = state;
1649 	}
1650 
1651 	return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry);
1652 }
1653 
1654 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port,
1655 					u16 vid)
1656 {
1657 	const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
1658 	u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC;
1659 
1660 	return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state);
1661 }
1662 
1663 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid)
1664 {
1665 	int port;
1666 	int err;
1667 
1668 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
1669 		err = mv88e6xxx_port_add_broadcast(chip, port, vid);
1670 		if (err)
1671 			return err;
1672 	}
1673 
1674 	return 0;
1675 }
1676 
1677 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port,
1678 				    u16 vid, u8 member)
1679 {
1680 	struct mv88e6xxx_vtu_entry vlan;
1681 	int err;
1682 
1683 	err = mv88e6xxx_vtu_get(chip, vid, &vlan, true);
1684 	if (err)
1685 		return err;
1686 
1687 	vlan.member[port] = member;
1688 
1689 	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1690 	if (err)
1691 		return err;
1692 
1693 	return mv88e6xxx_broadcast_setup(chip, vid);
1694 }
1695 
1696 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port,
1697 				    const struct switchdev_obj_port_vlan *vlan)
1698 {
1699 	struct mv88e6xxx_chip *chip = ds->priv;
1700 	bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED;
1701 	bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID;
1702 	u8 member;
1703 	u16 vid;
1704 
1705 	if (!chip->info->max_vid)
1706 		return;
1707 
1708 	if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port))
1709 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED;
1710 	else if (untagged)
1711 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED;
1712 	else
1713 		member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED;
1714 
1715 	mutex_lock(&chip->reg_lock);
1716 
1717 	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid)
1718 		if (_mv88e6xxx_port_vlan_add(chip, port, vid, member))
1719 			dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port,
1720 				vid, untagged ? 'u' : 't');
1721 
1722 	if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end))
1723 		dev_err(ds->dev, "p%d: failed to set PVID %d\n", port,
1724 			vlan->vid_end);
1725 
1726 	mutex_unlock(&chip->reg_lock);
1727 }
1728 
1729 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip,
1730 				    int port, u16 vid)
1731 {
1732 	struct mv88e6xxx_vtu_entry vlan;
1733 	int i, err;
1734 
1735 	err = mv88e6xxx_vtu_get(chip, vid, &vlan, false);
1736 	if (err)
1737 		return err;
1738 
1739 	/* Tell switchdev if this VLAN is handled in software */
1740 	if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER)
1741 		return -EOPNOTSUPP;
1742 
1743 	vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER;
1744 
1745 	/* keep the VLAN unless all ports are excluded */
1746 	vlan.valid = false;
1747 	for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
1748 		if (vlan.member[i] !=
1749 		    MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) {
1750 			vlan.valid = true;
1751 			break;
1752 		}
1753 	}
1754 
1755 	err = mv88e6xxx_vtu_loadpurge(chip, &vlan);
1756 	if (err)
1757 		return err;
1758 
1759 	return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false);
1760 }
1761 
1762 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port,
1763 				   const struct switchdev_obj_port_vlan *vlan)
1764 {
1765 	struct mv88e6xxx_chip *chip = ds->priv;
1766 	u16 pvid, vid;
1767 	int err = 0;
1768 
1769 	if (!chip->info->max_vid)
1770 		return -EOPNOTSUPP;
1771 
1772 	mutex_lock(&chip->reg_lock);
1773 
1774 	err = mv88e6xxx_port_get_pvid(chip, port, &pvid);
1775 	if (err)
1776 		goto unlock;
1777 
1778 	for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) {
1779 		err = _mv88e6xxx_port_vlan_del(chip, port, vid);
1780 		if (err)
1781 			goto unlock;
1782 
1783 		if (vid == pvid) {
1784 			err = mv88e6xxx_port_set_pvid(chip, port, 0);
1785 			if (err)
1786 				goto unlock;
1787 		}
1788 	}
1789 
1790 unlock:
1791 	mutex_unlock(&chip->reg_lock);
1792 
1793 	return err;
1794 }
1795 
1796 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port,
1797 				  const unsigned char *addr, u16 vid)
1798 {
1799 	struct mv88e6xxx_chip *chip = ds->priv;
1800 	int err;
1801 
1802 	mutex_lock(&chip->reg_lock);
1803 	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1804 					   MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1805 	mutex_unlock(&chip->reg_lock);
1806 
1807 	return err;
1808 }
1809 
1810 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port,
1811 				  const unsigned char *addr, u16 vid)
1812 {
1813 	struct mv88e6xxx_chip *chip = ds->priv;
1814 	int err;
1815 
1816 	mutex_lock(&chip->reg_lock);
1817 	err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid,
1818 					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
1819 	mutex_unlock(&chip->reg_lock);
1820 
1821 	return err;
1822 }
1823 
1824 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip,
1825 				      u16 fid, u16 vid, int port,
1826 				      dsa_fdb_dump_cb_t *cb, void *data)
1827 {
1828 	struct mv88e6xxx_atu_entry addr;
1829 	bool is_static;
1830 	int err;
1831 
1832 	addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED;
1833 	eth_broadcast_addr(addr.mac);
1834 
1835 	do {
1836 		mutex_lock(&chip->reg_lock);
1837 		err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr);
1838 		mutex_unlock(&chip->reg_lock);
1839 		if (err)
1840 			return err;
1841 
1842 		if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED)
1843 			break;
1844 
1845 		if (addr.trunk || (addr.portvec & BIT(port)) == 0)
1846 			continue;
1847 
1848 		if (!is_unicast_ether_addr(addr.mac))
1849 			continue;
1850 
1851 		is_static = (addr.state ==
1852 			     MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC);
1853 		err = cb(addr.mac, vid, is_static, data);
1854 		if (err)
1855 			return err;
1856 	} while (!is_broadcast_ether_addr(addr.mac));
1857 
1858 	return err;
1859 }
1860 
1861 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port,
1862 				  dsa_fdb_dump_cb_t *cb, void *data)
1863 {
1864 	struct mv88e6xxx_vtu_entry vlan = {
1865 		.vid = chip->info->max_vid,
1866 	};
1867 	u16 fid;
1868 	int err;
1869 
1870 	/* Dump port's default Filtering Information Database (VLAN ID 0) */
1871 	mutex_lock(&chip->reg_lock);
1872 	err = mv88e6xxx_port_get_fid(chip, port, &fid);
1873 	mutex_unlock(&chip->reg_lock);
1874 
1875 	if (err)
1876 		return err;
1877 
1878 	err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data);
1879 	if (err)
1880 		return err;
1881 
1882 	/* Dump VLANs' Filtering Information Databases */
1883 	do {
1884 		mutex_lock(&chip->reg_lock);
1885 		err = mv88e6xxx_vtu_getnext(chip, &vlan);
1886 		mutex_unlock(&chip->reg_lock);
1887 		if (err)
1888 			return err;
1889 
1890 		if (!vlan.valid)
1891 			break;
1892 
1893 		err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port,
1894 						 cb, data);
1895 		if (err)
1896 			return err;
1897 	} while (vlan.vid < chip->info->max_vid);
1898 
1899 	return err;
1900 }
1901 
1902 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port,
1903 				   dsa_fdb_dump_cb_t *cb, void *data)
1904 {
1905 	struct mv88e6xxx_chip *chip = ds->priv;
1906 
1907 	return mv88e6xxx_port_db_dump(chip, port, cb, data);
1908 }
1909 
1910 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip,
1911 				struct net_device *br)
1912 {
1913 	struct dsa_switch *ds;
1914 	int port;
1915 	int dev;
1916 	int err;
1917 
1918 	/* Remap the Port VLAN of each local bridge group member */
1919 	for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) {
1920 		if (chip->ds->ports[port].bridge_dev == br) {
1921 			err = mv88e6xxx_port_vlan_map(chip, port);
1922 			if (err)
1923 				return err;
1924 		}
1925 	}
1926 
1927 	if (!mv88e6xxx_has_pvt(chip))
1928 		return 0;
1929 
1930 	/* Remap the Port VLAN of each cross-chip bridge group member */
1931 	for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) {
1932 		ds = chip->ds->dst->ds[dev];
1933 		if (!ds)
1934 			break;
1935 
1936 		for (port = 0; port < ds->num_ports; ++port) {
1937 			if (ds->ports[port].bridge_dev == br) {
1938 				err = mv88e6xxx_pvt_map(chip, dev, port);
1939 				if (err)
1940 					return err;
1941 			}
1942 		}
1943 	}
1944 
1945 	return 0;
1946 }
1947 
1948 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port,
1949 				      struct net_device *br)
1950 {
1951 	struct mv88e6xxx_chip *chip = ds->priv;
1952 	int err;
1953 
1954 	mutex_lock(&chip->reg_lock);
1955 	err = mv88e6xxx_bridge_map(chip, br);
1956 	mutex_unlock(&chip->reg_lock);
1957 
1958 	return err;
1959 }
1960 
1961 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port,
1962 					struct net_device *br)
1963 {
1964 	struct mv88e6xxx_chip *chip = ds->priv;
1965 
1966 	mutex_lock(&chip->reg_lock);
1967 	if (mv88e6xxx_bridge_map(chip, br) ||
1968 	    mv88e6xxx_port_vlan_map(chip, port))
1969 		dev_err(ds->dev, "failed to remap in-chip Port VLAN\n");
1970 	mutex_unlock(&chip->reg_lock);
1971 }
1972 
1973 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev,
1974 					   int port, struct net_device *br)
1975 {
1976 	struct mv88e6xxx_chip *chip = ds->priv;
1977 	int err;
1978 
1979 	if (!mv88e6xxx_has_pvt(chip))
1980 		return 0;
1981 
1982 	mutex_lock(&chip->reg_lock);
1983 	err = mv88e6xxx_pvt_map(chip, dev, port);
1984 	mutex_unlock(&chip->reg_lock);
1985 
1986 	return err;
1987 }
1988 
1989 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev,
1990 					     int port, struct net_device *br)
1991 {
1992 	struct mv88e6xxx_chip *chip = ds->priv;
1993 
1994 	if (!mv88e6xxx_has_pvt(chip))
1995 		return;
1996 
1997 	mutex_lock(&chip->reg_lock);
1998 	if (mv88e6xxx_pvt_map(chip, dev, port))
1999 		dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n");
2000 	mutex_unlock(&chip->reg_lock);
2001 }
2002 
2003 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip)
2004 {
2005 	if (chip->info->ops->reset)
2006 		return chip->info->ops->reset(chip);
2007 
2008 	return 0;
2009 }
2010 
2011 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip)
2012 {
2013 	struct gpio_desc *gpiod = chip->reset;
2014 
2015 	/* If there is a GPIO connected to the reset pin, toggle it */
2016 	if (gpiod) {
2017 		gpiod_set_value_cansleep(gpiod, 1);
2018 		usleep_range(10000, 20000);
2019 		gpiod_set_value_cansleep(gpiod, 0);
2020 		usleep_range(10000, 20000);
2021 	}
2022 }
2023 
2024 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip)
2025 {
2026 	int i, err;
2027 
2028 	/* Set all ports to the Disabled state */
2029 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2030 		err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED);
2031 		if (err)
2032 			return err;
2033 	}
2034 
2035 	/* Wait for transmit queues to drain,
2036 	 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps.
2037 	 */
2038 	usleep_range(2000, 4000);
2039 
2040 	return 0;
2041 }
2042 
2043 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip)
2044 {
2045 	int err;
2046 
2047 	err = mv88e6xxx_disable_ports(chip);
2048 	if (err)
2049 		return err;
2050 
2051 	mv88e6xxx_hardware_reset(chip);
2052 
2053 	return mv88e6xxx_software_reset(chip);
2054 }
2055 
2056 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port,
2057 				   enum mv88e6xxx_frame_mode frame,
2058 				   enum mv88e6xxx_egress_mode egress, u16 etype)
2059 {
2060 	int err;
2061 
2062 	if (!chip->info->ops->port_set_frame_mode)
2063 		return -EOPNOTSUPP;
2064 
2065 	err = mv88e6xxx_port_set_egress_mode(chip, port, egress);
2066 	if (err)
2067 		return err;
2068 
2069 	err = chip->info->ops->port_set_frame_mode(chip, port, frame);
2070 	if (err)
2071 		return err;
2072 
2073 	if (chip->info->ops->port_set_ether_type)
2074 		return chip->info->ops->port_set_ether_type(chip, port, etype);
2075 
2076 	return 0;
2077 }
2078 
2079 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port)
2080 {
2081 	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL,
2082 				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2083 				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2084 }
2085 
2086 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port)
2087 {
2088 	return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA,
2089 				       MV88E6XXX_EGRESS_MODE_UNMODIFIED,
2090 				       MV88E6XXX_PORT_ETH_TYPE_DEFAULT);
2091 }
2092 
2093 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port)
2094 {
2095 	return mv88e6xxx_set_port_mode(chip, port,
2096 				       MV88E6XXX_FRAME_MODE_ETHERTYPE,
2097 				       MV88E6XXX_EGRESS_MODE_ETHERTYPE,
2098 				       ETH_P_EDSA);
2099 }
2100 
2101 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port)
2102 {
2103 	if (dsa_is_dsa_port(chip->ds, port))
2104 		return mv88e6xxx_set_port_mode_dsa(chip, port);
2105 
2106 	if (dsa_is_user_port(chip->ds, port))
2107 		return mv88e6xxx_set_port_mode_normal(chip, port);
2108 
2109 	/* Setup CPU port mode depending on its supported tag format */
2110 	if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA)
2111 		return mv88e6xxx_set_port_mode_dsa(chip, port);
2112 
2113 	if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA)
2114 		return mv88e6xxx_set_port_mode_edsa(chip, port);
2115 
2116 	return -EINVAL;
2117 }
2118 
2119 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port)
2120 {
2121 	bool message = dsa_is_dsa_port(chip->ds, port);
2122 
2123 	return mv88e6xxx_port_set_message_port(chip, port, message);
2124 }
2125 
2126 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port)
2127 {
2128 	struct dsa_switch *ds = chip->ds;
2129 	bool flood;
2130 
2131 	/* Upstream ports flood frames with unknown unicast or multicast DA */
2132 	flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port);
2133 	if (chip->info->ops->port_set_egress_floods)
2134 		return chip->info->ops->port_set_egress_floods(chip, port,
2135 							       flood, flood);
2136 
2137 	return 0;
2138 }
2139 
2140 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port,
2141 				  bool on)
2142 {
2143 	if (chip->info->ops->serdes_power)
2144 		return chip->info->ops->serdes_power(chip, port, on);
2145 
2146 	return 0;
2147 }
2148 
2149 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port)
2150 {
2151 	struct dsa_switch *ds = chip->ds;
2152 	int upstream_port;
2153 	int err;
2154 
2155 	upstream_port = dsa_upstream_port(ds, port);
2156 	if (chip->info->ops->port_set_upstream_port) {
2157 		err = chip->info->ops->port_set_upstream_port(chip, port,
2158 							      upstream_port);
2159 		if (err)
2160 			return err;
2161 	}
2162 
2163 	if (port == upstream_port) {
2164 		if (chip->info->ops->set_cpu_port) {
2165 			err = chip->info->ops->set_cpu_port(chip,
2166 							    upstream_port);
2167 			if (err)
2168 				return err;
2169 		}
2170 
2171 		if (chip->info->ops->set_egress_port) {
2172 			err = chip->info->ops->set_egress_port(chip,
2173 							       upstream_port);
2174 			if (err)
2175 				return err;
2176 		}
2177 	}
2178 
2179 	return 0;
2180 }
2181 
2182 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port)
2183 {
2184 	struct dsa_switch *ds = chip->ds;
2185 	int err;
2186 	u16 reg;
2187 
2188 	chip->ports[port].chip = chip;
2189 	chip->ports[port].port = port;
2190 
2191 	/* MAC Forcing register: don't force link, speed, duplex or flow control
2192 	 * state to any particular values on physical ports, but force the CPU
2193 	 * port and all DSA ports to their maximum bandwidth and full duplex.
2194 	 */
2195 	if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))
2196 		err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP,
2197 					       SPEED_MAX, DUPLEX_FULL,
2198 					       PAUSE_OFF,
2199 					       PHY_INTERFACE_MODE_NA);
2200 	else
2201 		err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED,
2202 					       SPEED_UNFORCED, DUPLEX_UNFORCED,
2203 					       PAUSE_ON,
2204 					       PHY_INTERFACE_MODE_NA);
2205 	if (err)
2206 		return err;
2207 
2208 	/* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock,
2209 	 * disable Header mode, enable IGMP/MLD snooping, disable VLAN
2210 	 * tunneling, determine priority by looking at 802.1p and IP
2211 	 * priority fields (IP prio has precedence), and set STP state
2212 	 * to Forwarding.
2213 	 *
2214 	 * If this is the CPU link, use DSA or EDSA tagging depending
2215 	 * on which tagging mode was configured.
2216 	 *
2217 	 * If this is a link to another switch, use DSA tagging mode.
2218 	 *
2219 	 * If this is the upstream port for this switch, enable
2220 	 * forwarding of unknown unicasts and multicasts.
2221 	 */
2222 	reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP |
2223 		MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP |
2224 		MV88E6XXX_PORT_CTL0_STATE_FORWARDING;
2225 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg);
2226 	if (err)
2227 		return err;
2228 
2229 	err = mv88e6xxx_setup_port_mode(chip, port);
2230 	if (err)
2231 		return err;
2232 
2233 	err = mv88e6xxx_setup_egress_floods(chip, port);
2234 	if (err)
2235 		return err;
2236 
2237 	/* Enable the SERDES interface for DSA and CPU ports. Normal
2238 	 * ports SERDES are enabled when the port is enabled, thus
2239 	 * saving a bit of power.
2240 	 */
2241 	if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) {
2242 		err = mv88e6xxx_serdes_power(chip, port, true);
2243 		if (err)
2244 			return err;
2245 	}
2246 
2247 	/* Port Control 2: don't force a good FCS, set the maximum frame size to
2248 	 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or
2249 	 * untagged frames on this port, do a destination address lookup on all
2250 	 * received packets as usual, disable ARP mirroring and don't send a
2251 	 * copy of all transmitted/received frames on this port to the CPU.
2252 	 */
2253 	err = mv88e6xxx_port_set_map_da(chip, port);
2254 	if (err)
2255 		return err;
2256 
2257 	err = mv88e6xxx_setup_upstream_port(chip, port);
2258 	if (err)
2259 		return err;
2260 
2261 	err = mv88e6xxx_port_set_8021q_mode(chip, port,
2262 				MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED);
2263 	if (err)
2264 		return err;
2265 
2266 	if (chip->info->ops->port_set_jumbo_size) {
2267 		err = chip->info->ops->port_set_jumbo_size(chip, port, 10240);
2268 		if (err)
2269 			return err;
2270 	}
2271 
2272 	/* Port Association Vector: when learning source addresses
2273 	 * of packets, add the address to the address database using
2274 	 * a port bitmap that has only the bit for this port set and
2275 	 * the other bits clear.
2276 	 */
2277 	reg = 1 << port;
2278 	/* Disable learning for CPU port */
2279 	if (dsa_is_cpu_port(ds, port))
2280 		reg = 0;
2281 
2282 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR,
2283 				   reg);
2284 	if (err)
2285 		return err;
2286 
2287 	/* Egress rate control 2: disable egress rate control. */
2288 	err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2,
2289 				   0x0000);
2290 	if (err)
2291 		return err;
2292 
2293 	if (chip->info->ops->port_pause_limit) {
2294 		err = chip->info->ops->port_pause_limit(chip, port, 0, 0);
2295 		if (err)
2296 			return err;
2297 	}
2298 
2299 	if (chip->info->ops->port_disable_learn_limit) {
2300 		err = chip->info->ops->port_disable_learn_limit(chip, port);
2301 		if (err)
2302 			return err;
2303 	}
2304 
2305 	if (chip->info->ops->port_disable_pri_override) {
2306 		err = chip->info->ops->port_disable_pri_override(chip, port);
2307 		if (err)
2308 			return err;
2309 	}
2310 
2311 	if (chip->info->ops->port_tag_remap) {
2312 		err = chip->info->ops->port_tag_remap(chip, port);
2313 		if (err)
2314 			return err;
2315 	}
2316 
2317 	if (chip->info->ops->port_egress_rate_limiting) {
2318 		err = chip->info->ops->port_egress_rate_limiting(chip, port);
2319 		if (err)
2320 			return err;
2321 	}
2322 
2323 	err = mv88e6xxx_setup_message_port(chip, port);
2324 	if (err)
2325 		return err;
2326 
2327 	/* Port based VLAN map: give each port the same default address
2328 	 * database, and allow bidirectional communication between the
2329 	 * CPU and DSA port(s), and the other ports.
2330 	 */
2331 	err = mv88e6xxx_port_set_fid(chip, port, 0);
2332 	if (err)
2333 		return err;
2334 
2335 	err = mv88e6xxx_port_vlan_map(chip, port);
2336 	if (err)
2337 		return err;
2338 
2339 	/* Default VLAN ID and priority: don't set a default VLAN
2340 	 * ID, and set the default packet priority to zero.
2341 	 */
2342 	return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0);
2343 }
2344 
2345 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port,
2346 				 struct phy_device *phydev)
2347 {
2348 	struct mv88e6xxx_chip *chip = ds->priv;
2349 	int err;
2350 
2351 	mutex_lock(&chip->reg_lock);
2352 
2353 	err = mv88e6xxx_serdes_power(chip, port, true);
2354 
2355 	if (!err && chip->info->ops->serdes_irq_setup)
2356 		err = chip->info->ops->serdes_irq_setup(chip, port);
2357 
2358 	mutex_unlock(&chip->reg_lock);
2359 
2360 	return err;
2361 }
2362 
2363 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port,
2364 				   struct phy_device *phydev)
2365 {
2366 	struct mv88e6xxx_chip *chip = ds->priv;
2367 
2368 	mutex_lock(&chip->reg_lock);
2369 
2370 	if (chip->info->ops->serdes_irq_free)
2371 		chip->info->ops->serdes_irq_free(chip, port);
2372 
2373 	if (mv88e6xxx_serdes_power(chip, port, false))
2374 		dev_err(chip->dev, "failed to power off SERDES\n");
2375 
2376 	mutex_unlock(&chip->reg_lock);
2377 }
2378 
2379 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds,
2380 				     unsigned int ageing_time)
2381 {
2382 	struct mv88e6xxx_chip *chip = ds->priv;
2383 	int err;
2384 
2385 	mutex_lock(&chip->reg_lock);
2386 	err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time);
2387 	mutex_unlock(&chip->reg_lock);
2388 
2389 	return err;
2390 }
2391 
2392 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip)
2393 {
2394 	int err;
2395 
2396 	/* Initialize the statistics unit */
2397 	if (chip->info->ops->stats_set_histogram) {
2398 		err = chip->info->ops->stats_set_histogram(chip);
2399 		if (err)
2400 			return err;
2401 	}
2402 
2403 	return mv88e6xxx_g1_stats_clear(chip);
2404 }
2405 
2406 /* The mv88e6390 has some hidden registers used for debug and
2407  * development. The errata also makes use of them.
2408  */
2409 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port,
2410 				  int reg, u16 val)
2411 {
2412 	u16 ctrl;
2413 	int err;
2414 
2415 	err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT,
2416 				   PORT_RESERVED_1A, val);
2417 	if (err)
2418 		return err;
2419 
2420 	ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE |
2421 	       PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2422 	       reg;
2423 
2424 	return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2425 				    PORT_RESERVED_1A, ctrl);
2426 }
2427 
2428 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip)
2429 {
2430 	return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT,
2431 			      PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY);
2432 }
2433 
2434 
2435 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port,
2436 				  int reg, u16 *val)
2437 {
2438 	u16 ctrl;
2439 	int err;
2440 
2441 	ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ |
2442 	       PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT |
2443 	       reg;
2444 
2445 	err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT,
2446 				   PORT_RESERVED_1A, ctrl);
2447 	if (err)
2448 		return err;
2449 
2450 	err = mv88e6390_hidden_wait(chip);
2451 	if (err)
2452 		return err;
2453 
2454 	return 	mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT,
2455 				    PORT_RESERVED_1A, val);
2456 }
2457 
2458 /* Check if the errata has already been applied. */
2459 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip)
2460 {
2461 	int port;
2462 	int err;
2463 	u16 val;
2464 
2465 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2466 		err = mv88e6390_hidden_read(chip, port, 0, &val);
2467 		if (err) {
2468 			dev_err(chip->dev,
2469 				"Error reading hidden register: %d\n", err);
2470 			return false;
2471 		}
2472 		if (val != 0x01c0)
2473 			return false;
2474 	}
2475 
2476 	return true;
2477 }
2478 
2479 /* The 6390 copper ports have an errata which require poking magic
2480  * values into undocumented hidden registers and then performing a
2481  * software reset.
2482  */
2483 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip)
2484 {
2485 	int port;
2486 	int err;
2487 
2488 	if (mv88e6390_setup_errata_applied(chip))
2489 		return 0;
2490 
2491 	/* Set the ports into blocking mode */
2492 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2493 		err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED);
2494 		if (err)
2495 			return err;
2496 	}
2497 
2498 	for (port = 0; port < mv88e6xxx_num_ports(chip); port++) {
2499 		err = mv88e6390_hidden_write(chip, port, 0, 0x01c0);
2500 		if (err)
2501 			return err;
2502 	}
2503 
2504 	return mv88e6xxx_software_reset(chip);
2505 }
2506 
2507 static int mv88e6xxx_setup(struct dsa_switch *ds)
2508 {
2509 	struct mv88e6xxx_chip *chip = ds->priv;
2510 	u8 cmode;
2511 	int err;
2512 	int i;
2513 
2514 	chip->ds = ds;
2515 	ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip);
2516 
2517 	mutex_lock(&chip->reg_lock);
2518 
2519 	if (chip->info->ops->setup_errata) {
2520 		err = chip->info->ops->setup_errata(chip);
2521 		if (err)
2522 			goto unlock;
2523 	}
2524 
2525 	/* Cache the cmode of each port. */
2526 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2527 		if (chip->info->ops->port_get_cmode) {
2528 			err = chip->info->ops->port_get_cmode(chip, i, &cmode);
2529 			if (err)
2530 				goto unlock;
2531 
2532 			chip->ports[i].cmode = cmode;
2533 		}
2534 	}
2535 
2536 	/* Setup Switch Port Registers */
2537 	for (i = 0; i < mv88e6xxx_num_ports(chip); i++) {
2538 		if (dsa_is_unused_port(ds, i))
2539 			continue;
2540 
2541 		err = mv88e6xxx_setup_port(chip, i);
2542 		if (err)
2543 			goto unlock;
2544 	}
2545 
2546 	err = mv88e6xxx_irl_setup(chip);
2547 	if (err)
2548 		goto unlock;
2549 
2550 	err = mv88e6xxx_mac_setup(chip);
2551 	if (err)
2552 		goto unlock;
2553 
2554 	err = mv88e6xxx_phy_setup(chip);
2555 	if (err)
2556 		goto unlock;
2557 
2558 	err = mv88e6xxx_vtu_setup(chip);
2559 	if (err)
2560 		goto unlock;
2561 
2562 	err = mv88e6xxx_pvt_setup(chip);
2563 	if (err)
2564 		goto unlock;
2565 
2566 	err = mv88e6xxx_atu_setup(chip);
2567 	if (err)
2568 		goto unlock;
2569 
2570 	err = mv88e6xxx_broadcast_setup(chip, 0);
2571 	if (err)
2572 		goto unlock;
2573 
2574 	err = mv88e6xxx_pot_setup(chip);
2575 	if (err)
2576 		goto unlock;
2577 
2578 	err = mv88e6xxx_rmu_setup(chip);
2579 	if (err)
2580 		goto unlock;
2581 
2582 	err = mv88e6xxx_rsvd2cpu_setup(chip);
2583 	if (err)
2584 		goto unlock;
2585 
2586 	err = mv88e6xxx_trunk_setup(chip);
2587 	if (err)
2588 		goto unlock;
2589 
2590 	err = mv88e6xxx_devmap_setup(chip);
2591 	if (err)
2592 		goto unlock;
2593 
2594 	err = mv88e6xxx_pri_setup(chip);
2595 	if (err)
2596 		goto unlock;
2597 
2598 	/* Setup PTP Hardware Clock and timestamping */
2599 	if (chip->info->ptp_support) {
2600 		err = mv88e6xxx_ptp_setup(chip);
2601 		if (err)
2602 			goto unlock;
2603 
2604 		err = mv88e6xxx_hwtstamp_setup(chip);
2605 		if (err)
2606 			goto unlock;
2607 	}
2608 
2609 	err = mv88e6xxx_stats_setup(chip);
2610 	if (err)
2611 		goto unlock;
2612 
2613 unlock:
2614 	mutex_unlock(&chip->reg_lock);
2615 
2616 	return err;
2617 }
2618 
2619 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg)
2620 {
2621 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2622 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2623 	u16 val;
2624 	int err;
2625 
2626 	if (!chip->info->ops->phy_read)
2627 		return -EOPNOTSUPP;
2628 
2629 	mutex_lock(&chip->reg_lock);
2630 	err = chip->info->ops->phy_read(chip, bus, phy, reg, &val);
2631 	mutex_unlock(&chip->reg_lock);
2632 
2633 	if (reg == MII_PHYSID2) {
2634 		/* Some internal PHYs don't have a model number. */
2635 		if (chip->info->family != MV88E6XXX_FAMILY_6165)
2636 			/* Then there is the 6165 family. It gets is
2637 			 * PHYs correct. But it can also have two
2638 			 * SERDES interfaces in the PHY address
2639 			 * space. And these don't have a model
2640 			 * number. But they are not PHYs, so we don't
2641 			 * want to give them something a PHY driver
2642 			 * will recognise.
2643 			 *
2644 			 * Use the mv88e6390 family model number
2645 			 * instead, for anything which really could be
2646 			 * a PHY,
2647 			 */
2648 			if (!(val & 0x3f0))
2649 				val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4;
2650 	}
2651 
2652 	return err ? err : val;
2653 }
2654 
2655 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val)
2656 {
2657 	struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv;
2658 	struct mv88e6xxx_chip *chip = mdio_bus->chip;
2659 	int err;
2660 
2661 	if (!chip->info->ops->phy_write)
2662 		return -EOPNOTSUPP;
2663 
2664 	mutex_lock(&chip->reg_lock);
2665 	err = chip->info->ops->phy_write(chip, bus, phy, reg, val);
2666 	mutex_unlock(&chip->reg_lock);
2667 
2668 	return err;
2669 }
2670 
2671 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip,
2672 				   struct device_node *np,
2673 				   bool external)
2674 {
2675 	static int index;
2676 	struct mv88e6xxx_mdio_bus *mdio_bus;
2677 	struct mii_bus *bus;
2678 	int err;
2679 
2680 	if (external) {
2681 		mutex_lock(&chip->reg_lock);
2682 		err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true);
2683 		mutex_unlock(&chip->reg_lock);
2684 
2685 		if (err)
2686 			return err;
2687 	}
2688 
2689 	bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus));
2690 	if (!bus)
2691 		return -ENOMEM;
2692 
2693 	mdio_bus = bus->priv;
2694 	mdio_bus->bus = bus;
2695 	mdio_bus->chip = chip;
2696 	INIT_LIST_HEAD(&mdio_bus->list);
2697 	mdio_bus->external = external;
2698 
2699 	if (np) {
2700 		bus->name = np->full_name;
2701 		snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np);
2702 	} else {
2703 		bus->name = "mv88e6xxx SMI";
2704 		snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++);
2705 	}
2706 
2707 	bus->read = mv88e6xxx_mdio_read;
2708 	bus->write = mv88e6xxx_mdio_write;
2709 	bus->parent = chip->dev;
2710 
2711 	if (!external) {
2712 		err = mv88e6xxx_g2_irq_mdio_setup(chip, bus);
2713 		if (err)
2714 			return err;
2715 	}
2716 
2717 	err = of_mdiobus_register(bus, np);
2718 	if (err) {
2719 		dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err);
2720 		mv88e6xxx_g2_irq_mdio_free(chip, bus);
2721 		return err;
2722 	}
2723 
2724 	if (external)
2725 		list_add_tail(&mdio_bus->list, &chip->mdios);
2726 	else
2727 		list_add(&mdio_bus->list, &chip->mdios);
2728 
2729 	return 0;
2730 }
2731 
2732 static const struct of_device_id mv88e6xxx_mdio_external_match[] = {
2733 	{ .compatible = "marvell,mv88e6xxx-mdio-external",
2734 	  .data = (void *)true },
2735 	{ },
2736 };
2737 
2738 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip)
2739 
2740 {
2741 	struct mv88e6xxx_mdio_bus *mdio_bus;
2742 	struct mii_bus *bus;
2743 
2744 	list_for_each_entry(mdio_bus, &chip->mdios, list) {
2745 		bus = mdio_bus->bus;
2746 
2747 		if (!mdio_bus->external)
2748 			mv88e6xxx_g2_irq_mdio_free(chip, bus);
2749 
2750 		mdiobus_unregister(bus);
2751 	}
2752 }
2753 
2754 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip,
2755 				    struct device_node *np)
2756 {
2757 	const struct of_device_id *match;
2758 	struct device_node *child;
2759 	int err;
2760 
2761 	/* Always register one mdio bus for the internal/default mdio
2762 	 * bus. This maybe represented in the device tree, but is
2763 	 * optional.
2764 	 */
2765 	child = of_get_child_by_name(np, "mdio");
2766 	err = mv88e6xxx_mdio_register(chip, child, false);
2767 	if (err)
2768 		return err;
2769 
2770 	/* Walk the device tree, and see if there are any other nodes
2771 	 * which say they are compatible with the external mdio
2772 	 * bus.
2773 	 */
2774 	for_each_available_child_of_node(np, child) {
2775 		match = of_match_node(mv88e6xxx_mdio_external_match, child);
2776 		if (match) {
2777 			err = mv88e6xxx_mdio_register(chip, child, true);
2778 			if (err) {
2779 				mv88e6xxx_mdios_unregister(chip);
2780 				return err;
2781 			}
2782 		}
2783 	}
2784 
2785 	return 0;
2786 }
2787 
2788 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds)
2789 {
2790 	struct mv88e6xxx_chip *chip = ds->priv;
2791 
2792 	return chip->eeprom_len;
2793 }
2794 
2795 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds,
2796 				struct ethtool_eeprom *eeprom, u8 *data)
2797 {
2798 	struct mv88e6xxx_chip *chip = ds->priv;
2799 	int err;
2800 
2801 	if (!chip->info->ops->get_eeprom)
2802 		return -EOPNOTSUPP;
2803 
2804 	mutex_lock(&chip->reg_lock);
2805 	err = chip->info->ops->get_eeprom(chip, eeprom, data);
2806 	mutex_unlock(&chip->reg_lock);
2807 
2808 	if (err)
2809 		return err;
2810 
2811 	eeprom->magic = 0xc3ec4951;
2812 
2813 	return 0;
2814 }
2815 
2816 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds,
2817 				struct ethtool_eeprom *eeprom, u8 *data)
2818 {
2819 	struct mv88e6xxx_chip *chip = ds->priv;
2820 	int err;
2821 
2822 	if (!chip->info->ops->set_eeprom)
2823 		return -EOPNOTSUPP;
2824 
2825 	if (eeprom->magic != 0xc3ec4951)
2826 		return -EINVAL;
2827 
2828 	mutex_lock(&chip->reg_lock);
2829 	err = chip->info->ops->set_eeprom(chip, eeprom, data);
2830 	mutex_unlock(&chip->reg_lock);
2831 
2832 	return err;
2833 }
2834 
2835 static const struct mv88e6xxx_ops mv88e6085_ops = {
2836 	/* MV88E6XXX_FAMILY_6097 */
2837 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2838 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2839 	.irl_init_all = mv88e6352_g2_irl_init_all,
2840 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2841 	.phy_read = mv88e6185_phy_ppu_read,
2842 	.phy_write = mv88e6185_phy_ppu_write,
2843 	.port_set_link = mv88e6xxx_port_set_link,
2844 	.port_set_duplex = mv88e6xxx_port_set_duplex,
2845 	.port_set_speed = mv88e6185_port_set_speed,
2846 	.port_tag_remap = mv88e6095_port_tag_remap,
2847 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2848 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2849 	.port_set_ether_type = mv88e6351_port_set_ether_type,
2850 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2851 	.port_pause_limit = mv88e6097_port_pause_limit,
2852 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2853 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2854 	.port_link_state = mv88e6352_port_link_state,
2855 	.port_get_cmode = mv88e6185_port_get_cmode,
2856 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2857 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2858 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
2859 	.stats_get_strings = mv88e6095_stats_get_strings,
2860 	.stats_get_stats = mv88e6095_stats_get_stats,
2861 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
2862 	.set_egress_port = mv88e6095_g1_set_egress_port,
2863 	.watchdog_ops = &mv88e6097_watchdog_ops,
2864 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2865 	.pot_clear = mv88e6xxx_g2_pot_clear,
2866 	.ppu_enable = mv88e6185_g1_ppu_enable,
2867 	.ppu_disable = mv88e6185_g1_ppu_disable,
2868 	.reset = mv88e6185_g1_reset,
2869 	.rmu_disable = mv88e6085_g1_rmu_disable,
2870 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2871 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2872 	.phylink_validate = mv88e6185_phylink_validate,
2873 };
2874 
2875 static const struct mv88e6xxx_ops mv88e6095_ops = {
2876 	/* MV88E6XXX_FAMILY_6095 */
2877 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2878 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2879 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2880 	.phy_read = mv88e6185_phy_ppu_read,
2881 	.phy_write = mv88e6185_phy_ppu_write,
2882 	.port_set_link = mv88e6xxx_port_set_link,
2883 	.port_set_duplex = mv88e6xxx_port_set_duplex,
2884 	.port_set_speed = mv88e6185_port_set_speed,
2885 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2886 	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2887 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2888 	.port_link_state = mv88e6185_port_link_state,
2889 	.port_get_cmode = mv88e6185_port_get_cmode,
2890 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2891 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2892 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
2893 	.stats_get_strings = mv88e6095_stats_get_strings,
2894 	.stats_get_stats = mv88e6095_stats_get_stats,
2895 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
2896 	.ppu_enable = mv88e6185_g1_ppu_enable,
2897 	.ppu_disable = mv88e6185_g1_ppu_disable,
2898 	.reset = mv88e6185_g1_reset,
2899 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
2900 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
2901 	.phylink_validate = mv88e6185_phylink_validate,
2902 };
2903 
2904 static const struct mv88e6xxx_ops mv88e6097_ops = {
2905 	/* MV88E6XXX_FAMILY_6097 */
2906 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2907 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2908 	.irl_init_all = mv88e6352_g2_irl_init_all,
2909 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2910 	.phy_read = mv88e6xxx_g2_smi_phy_read,
2911 	.phy_write = mv88e6xxx_g2_smi_phy_write,
2912 	.port_set_link = mv88e6xxx_port_set_link,
2913 	.port_set_duplex = mv88e6xxx_port_set_duplex,
2914 	.port_set_speed = mv88e6185_port_set_speed,
2915 	.port_tag_remap = mv88e6095_port_tag_remap,
2916 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2917 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2918 	.port_set_ether_type = mv88e6351_port_set_ether_type,
2919 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2920 	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
2921 	.port_pause_limit = mv88e6097_port_pause_limit,
2922 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2923 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2924 	.port_link_state = mv88e6352_port_link_state,
2925 	.port_get_cmode = mv88e6185_port_get_cmode,
2926 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2927 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2928 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
2929 	.stats_get_strings = mv88e6095_stats_get_strings,
2930 	.stats_get_stats = mv88e6095_stats_get_stats,
2931 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
2932 	.set_egress_port = mv88e6095_g1_set_egress_port,
2933 	.watchdog_ops = &mv88e6097_watchdog_ops,
2934 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2935 	.pot_clear = mv88e6xxx_g2_pot_clear,
2936 	.reset = mv88e6352_g1_reset,
2937 	.rmu_disable = mv88e6085_g1_rmu_disable,
2938 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2939 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2940 	.phylink_validate = mv88e6185_phylink_validate,
2941 };
2942 
2943 static const struct mv88e6xxx_ops mv88e6123_ops = {
2944 	/* MV88E6XXX_FAMILY_6165 */
2945 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2946 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2947 	.irl_init_all = mv88e6352_g2_irl_init_all,
2948 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
2949 	.phy_read = mv88e6xxx_g2_smi_phy_read,
2950 	.phy_write = mv88e6xxx_g2_smi_phy_write,
2951 	.port_set_link = mv88e6xxx_port_set_link,
2952 	.port_set_duplex = mv88e6xxx_port_set_duplex,
2953 	.port_set_speed = mv88e6185_port_set_speed,
2954 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
2955 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
2956 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
2957 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
2958 	.port_link_state = mv88e6352_port_link_state,
2959 	.port_get_cmode = mv88e6185_port_get_cmode,
2960 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
2961 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2962 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
2963 	.stats_get_strings = mv88e6095_stats_get_strings,
2964 	.stats_get_stats = mv88e6095_stats_get_stats,
2965 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
2966 	.set_egress_port = mv88e6095_g1_set_egress_port,
2967 	.watchdog_ops = &mv88e6097_watchdog_ops,
2968 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
2969 	.pot_clear = mv88e6xxx_g2_pot_clear,
2970 	.reset = mv88e6352_g1_reset,
2971 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
2972 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
2973 	.phylink_validate = mv88e6185_phylink_validate,
2974 };
2975 
2976 static const struct mv88e6xxx_ops mv88e6131_ops = {
2977 	/* MV88E6XXX_FAMILY_6185 */
2978 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
2979 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
2980 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
2981 	.phy_read = mv88e6185_phy_ppu_read,
2982 	.phy_write = mv88e6185_phy_ppu_write,
2983 	.port_set_link = mv88e6xxx_port_set_link,
2984 	.port_set_duplex = mv88e6xxx_port_set_duplex,
2985 	.port_set_speed = mv88e6185_port_set_speed,
2986 	.port_tag_remap = mv88e6095_port_tag_remap,
2987 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
2988 	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
2989 	.port_set_ether_type = mv88e6351_port_set_ether_type,
2990 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
2991 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
2992 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
2993 	.port_pause_limit = mv88e6097_port_pause_limit,
2994 	.port_set_pause = mv88e6185_port_set_pause,
2995 	.port_link_state = mv88e6352_port_link_state,
2996 	.port_get_cmode = mv88e6185_port_get_cmode,
2997 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
2998 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
2999 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3000 	.stats_get_strings = mv88e6095_stats_get_strings,
3001 	.stats_get_stats = mv88e6095_stats_get_stats,
3002 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3003 	.set_egress_port = mv88e6095_g1_set_egress_port,
3004 	.watchdog_ops = &mv88e6097_watchdog_ops,
3005 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3006 	.ppu_enable = mv88e6185_g1_ppu_enable,
3007 	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3008 	.ppu_disable = mv88e6185_g1_ppu_disable,
3009 	.reset = mv88e6185_g1_reset,
3010 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3011 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3012 	.phylink_validate = mv88e6185_phylink_validate,
3013 };
3014 
3015 static const struct mv88e6xxx_ops mv88e6141_ops = {
3016 	/* MV88E6XXX_FAMILY_6341 */
3017 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3018 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3019 	.irl_init_all = mv88e6352_g2_irl_init_all,
3020 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3021 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3022 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3023 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3024 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3025 	.port_set_link = mv88e6xxx_port_set_link,
3026 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3027 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3028 	.port_set_speed = mv88e6341_port_set_speed,
3029 	.port_tag_remap = mv88e6095_port_tag_remap,
3030 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3031 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3032 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3033 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3034 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3035 	.port_pause_limit = mv88e6097_port_pause_limit,
3036 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3037 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3038 	.port_link_state = mv88e6352_port_link_state,
3039 	.port_get_cmode = mv88e6352_port_get_cmode,
3040 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3041 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3042 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3043 	.stats_get_strings = mv88e6320_stats_get_strings,
3044 	.stats_get_stats = mv88e6390_stats_get_stats,
3045 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3046 	.set_egress_port = mv88e6390_g1_set_egress_port,
3047 	.watchdog_ops = &mv88e6390_watchdog_ops,
3048 	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3049 	.pot_clear = mv88e6xxx_g2_pot_clear,
3050 	.reset = mv88e6352_g1_reset,
3051 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3052 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3053 	.serdes_power = mv88e6341_serdes_power,
3054 	.gpio_ops = &mv88e6352_gpio_ops,
3055 	.phylink_validate = mv88e6390_phylink_validate,
3056 };
3057 
3058 static const struct mv88e6xxx_ops mv88e6161_ops = {
3059 	/* MV88E6XXX_FAMILY_6165 */
3060 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3061 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3062 	.irl_init_all = mv88e6352_g2_irl_init_all,
3063 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3064 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3065 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3066 	.port_set_link = mv88e6xxx_port_set_link,
3067 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3068 	.port_set_speed = mv88e6185_port_set_speed,
3069 	.port_tag_remap = mv88e6095_port_tag_remap,
3070 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3071 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3072 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3073 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3074 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3075 	.port_pause_limit = mv88e6097_port_pause_limit,
3076 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3077 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3078 	.port_link_state = mv88e6352_port_link_state,
3079 	.port_get_cmode = mv88e6185_port_get_cmode,
3080 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3081 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3082 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3083 	.stats_get_strings = mv88e6095_stats_get_strings,
3084 	.stats_get_stats = mv88e6095_stats_get_stats,
3085 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3086 	.set_egress_port = mv88e6095_g1_set_egress_port,
3087 	.watchdog_ops = &mv88e6097_watchdog_ops,
3088 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3089 	.pot_clear = mv88e6xxx_g2_pot_clear,
3090 	.reset = mv88e6352_g1_reset,
3091 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3092 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3093 	.avb_ops = &mv88e6165_avb_ops,
3094 	.ptp_ops = &mv88e6165_ptp_ops,
3095 	.phylink_validate = mv88e6185_phylink_validate,
3096 };
3097 
3098 static const struct mv88e6xxx_ops mv88e6165_ops = {
3099 	/* MV88E6XXX_FAMILY_6165 */
3100 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3101 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3102 	.irl_init_all = mv88e6352_g2_irl_init_all,
3103 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3104 	.phy_read = mv88e6165_phy_read,
3105 	.phy_write = mv88e6165_phy_write,
3106 	.port_set_link = mv88e6xxx_port_set_link,
3107 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3108 	.port_set_speed = mv88e6185_port_set_speed,
3109 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3110 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3111 	.port_link_state = mv88e6352_port_link_state,
3112 	.port_get_cmode = mv88e6185_port_get_cmode,
3113 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3114 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3115 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3116 	.stats_get_strings = mv88e6095_stats_get_strings,
3117 	.stats_get_stats = mv88e6095_stats_get_stats,
3118 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3119 	.set_egress_port = mv88e6095_g1_set_egress_port,
3120 	.watchdog_ops = &mv88e6097_watchdog_ops,
3121 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3122 	.pot_clear = mv88e6xxx_g2_pot_clear,
3123 	.reset = mv88e6352_g1_reset,
3124 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3125 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3126 	.avb_ops = &mv88e6165_avb_ops,
3127 	.ptp_ops = &mv88e6165_ptp_ops,
3128 	.phylink_validate = mv88e6185_phylink_validate,
3129 };
3130 
3131 static const struct mv88e6xxx_ops mv88e6171_ops = {
3132 	/* MV88E6XXX_FAMILY_6351 */
3133 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3134 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3135 	.irl_init_all = mv88e6352_g2_irl_init_all,
3136 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3137 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3138 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3139 	.port_set_link = mv88e6xxx_port_set_link,
3140 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3141 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3142 	.port_set_speed = mv88e6185_port_set_speed,
3143 	.port_tag_remap = mv88e6095_port_tag_remap,
3144 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3145 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3146 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3147 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3148 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3149 	.port_pause_limit = mv88e6097_port_pause_limit,
3150 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3151 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3152 	.port_link_state = mv88e6352_port_link_state,
3153 	.port_get_cmode = mv88e6352_port_get_cmode,
3154 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3155 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3156 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3157 	.stats_get_strings = mv88e6095_stats_get_strings,
3158 	.stats_get_stats = mv88e6095_stats_get_stats,
3159 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3160 	.set_egress_port = mv88e6095_g1_set_egress_port,
3161 	.watchdog_ops = &mv88e6097_watchdog_ops,
3162 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3163 	.pot_clear = mv88e6xxx_g2_pot_clear,
3164 	.reset = mv88e6352_g1_reset,
3165 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3166 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3167 	.phylink_validate = mv88e6185_phylink_validate,
3168 };
3169 
3170 static const struct mv88e6xxx_ops mv88e6172_ops = {
3171 	/* MV88E6XXX_FAMILY_6352 */
3172 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3173 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3174 	.irl_init_all = mv88e6352_g2_irl_init_all,
3175 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3176 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3177 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3178 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3179 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3180 	.port_set_link = mv88e6xxx_port_set_link,
3181 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3182 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3183 	.port_set_speed = mv88e6352_port_set_speed,
3184 	.port_tag_remap = mv88e6095_port_tag_remap,
3185 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3186 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3187 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3188 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3189 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3190 	.port_pause_limit = mv88e6097_port_pause_limit,
3191 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3192 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3193 	.port_link_state = mv88e6352_port_link_state,
3194 	.port_get_cmode = mv88e6352_port_get_cmode,
3195 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3196 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3197 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3198 	.stats_get_strings = mv88e6095_stats_get_strings,
3199 	.stats_get_stats = mv88e6095_stats_get_stats,
3200 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3201 	.set_egress_port = mv88e6095_g1_set_egress_port,
3202 	.watchdog_ops = &mv88e6097_watchdog_ops,
3203 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3204 	.pot_clear = mv88e6xxx_g2_pot_clear,
3205 	.reset = mv88e6352_g1_reset,
3206 	.rmu_disable = mv88e6352_g1_rmu_disable,
3207 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3208 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3209 	.serdes_power = mv88e6352_serdes_power,
3210 	.gpio_ops = &mv88e6352_gpio_ops,
3211 	.phylink_validate = mv88e6352_phylink_validate,
3212 };
3213 
3214 static const struct mv88e6xxx_ops mv88e6175_ops = {
3215 	/* MV88E6XXX_FAMILY_6351 */
3216 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3217 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3218 	.irl_init_all = mv88e6352_g2_irl_init_all,
3219 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3220 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3221 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3222 	.port_set_link = mv88e6xxx_port_set_link,
3223 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3224 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3225 	.port_set_speed = mv88e6185_port_set_speed,
3226 	.port_tag_remap = mv88e6095_port_tag_remap,
3227 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3228 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3229 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3230 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3231 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3232 	.port_pause_limit = mv88e6097_port_pause_limit,
3233 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3234 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3235 	.port_link_state = mv88e6352_port_link_state,
3236 	.port_get_cmode = mv88e6352_port_get_cmode,
3237 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3238 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3239 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3240 	.stats_get_strings = mv88e6095_stats_get_strings,
3241 	.stats_get_stats = mv88e6095_stats_get_stats,
3242 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3243 	.set_egress_port = mv88e6095_g1_set_egress_port,
3244 	.watchdog_ops = &mv88e6097_watchdog_ops,
3245 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3246 	.pot_clear = mv88e6xxx_g2_pot_clear,
3247 	.reset = mv88e6352_g1_reset,
3248 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3249 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3250 	.phylink_validate = mv88e6185_phylink_validate,
3251 };
3252 
3253 static const struct mv88e6xxx_ops mv88e6176_ops = {
3254 	/* MV88E6XXX_FAMILY_6352 */
3255 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3256 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3257 	.irl_init_all = mv88e6352_g2_irl_init_all,
3258 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3259 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3260 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3261 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3262 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3263 	.port_set_link = mv88e6xxx_port_set_link,
3264 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3265 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3266 	.port_set_speed = mv88e6352_port_set_speed,
3267 	.port_tag_remap = mv88e6095_port_tag_remap,
3268 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3269 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3270 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3271 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3272 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3273 	.port_pause_limit = mv88e6097_port_pause_limit,
3274 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3275 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3276 	.port_link_state = mv88e6352_port_link_state,
3277 	.port_get_cmode = mv88e6352_port_get_cmode,
3278 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3279 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3280 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3281 	.stats_get_strings = mv88e6095_stats_get_strings,
3282 	.stats_get_stats = mv88e6095_stats_get_stats,
3283 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3284 	.set_egress_port = mv88e6095_g1_set_egress_port,
3285 	.watchdog_ops = &mv88e6097_watchdog_ops,
3286 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3287 	.pot_clear = mv88e6xxx_g2_pot_clear,
3288 	.reset = mv88e6352_g1_reset,
3289 	.rmu_disable = mv88e6352_g1_rmu_disable,
3290 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3291 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3292 	.serdes_power = mv88e6352_serdes_power,
3293 	.serdes_irq_setup = mv88e6352_serdes_irq_setup,
3294 	.serdes_irq_free = mv88e6352_serdes_irq_free,
3295 	.gpio_ops = &mv88e6352_gpio_ops,
3296 	.phylink_validate = mv88e6352_phylink_validate,
3297 };
3298 
3299 static const struct mv88e6xxx_ops mv88e6185_ops = {
3300 	/* MV88E6XXX_FAMILY_6185 */
3301 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3302 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3303 	.set_switch_mac = mv88e6xxx_g1_set_switch_mac,
3304 	.phy_read = mv88e6185_phy_ppu_read,
3305 	.phy_write = mv88e6185_phy_ppu_write,
3306 	.port_set_link = mv88e6xxx_port_set_link,
3307 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3308 	.port_set_speed = mv88e6185_port_set_speed,
3309 	.port_set_frame_mode = mv88e6085_port_set_frame_mode,
3310 	.port_set_egress_floods = mv88e6185_port_set_egress_floods,
3311 	.port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting,
3312 	.port_set_upstream_port = mv88e6095_port_set_upstream_port,
3313 	.port_set_pause = mv88e6185_port_set_pause,
3314 	.port_link_state = mv88e6185_port_link_state,
3315 	.port_get_cmode = mv88e6185_port_get_cmode,
3316 	.stats_snapshot = mv88e6xxx_g1_stats_snapshot,
3317 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3318 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3319 	.stats_get_strings = mv88e6095_stats_get_strings,
3320 	.stats_get_stats = mv88e6095_stats_get_stats,
3321 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3322 	.set_egress_port = mv88e6095_g1_set_egress_port,
3323 	.watchdog_ops = &mv88e6097_watchdog_ops,
3324 	.mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu,
3325 	.set_cascade_port = mv88e6185_g1_set_cascade_port,
3326 	.ppu_enable = mv88e6185_g1_ppu_enable,
3327 	.ppu_disable = mv88e6185_g1_ppu_disable,
3328 	.reset = mv88e6185_g1_reset,
3329 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3330 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3331 	.phylink_validate = mv88e6185_phylink_validate,
3332 };
3333 
3334 static const struct mv88e6xxx_ops mv88e6190_ops = {
3335 	/* MV88E6XXX_FAMILY_6390 */
3336 	.setup_errata = mv88e6390_setup_errata,
3337 	.irl_init_all = mv88e6390_g2_irl_init_all,
3338 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3339 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3340 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3341 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3342 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3343 	.port_set_link = mv88e6xxx_port_set_link,
3344 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3345 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3346 	.port_set_speed = mv88e6390_port_set_speed,
3347 	.port_tag_remap = mv88e6390_port_tag_remap,
3348 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3349 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3350 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3351 	.port_pause_limit = mv88e6390_port_pause_limit,
3352 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3353 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3354 	.port_link_state = mv88e6352_port_link_state,
3355 	.port_get_cmode = mv88e6352_port_get_cmode,
3356 	.port_set_cmode = mv88e6390_port_set_cmode,
3357 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3358 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3359 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3360 	.stats_get_strings = mv88e6320_stats_get_strings,
3361 	.stats_get_stats = mv88e6390_stats_get_stats,
3362 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3363 	.set_egress_port = mv88e6390_g1_set_egress_port,
3364 	.watchdog_ops = &mv88e6390_watchdog_ops,
3365 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3366 	.pot_clear = mv88e6xxx_g2_pot_clear,
3367 	.reset = mv88e6352_g1_reset,
3368 	.rmu_disable = mv88e6390_g1_rmu_disable,
3369 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3370 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3371 	.serdes_power = mv88e6390_serdes_power,
3372 	.serdes_irq_setup = mv88e6390_serdes_irq_setup,
3373 	.serdes_irq_free = mv88e6390_serdes_irq_free,
3374 	.gpio_ops = &mv88e6352_gpio_ops,
3375 	.phylink_validate = mv88e6390_phylink_validate,
3376 };
3377 
3378 static const struct mv88e6xxx_ops mv88e6190x_ops = {
3379 	/* MV88E6XXX_FAMILY_6390 */
3380 	.setup_errata = mv88e6390_setup_errata,
3381 	.irl_init_all = mv88e6390_g2_irl_init_all,
3382 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3383 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3384 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3385 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3386 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3387 	.port_set_link = mv88e6xxx_port_set_link,
3388 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3389 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3390 	.port_set_speed = mv88e6390x_port_set_speed,
3391 	.port_tag_remap = mv88e6390_port_tag_remap,
3392 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3393 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3394 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3395 	.port_pause_limit = mv88e6390_port_pause_limit,
3396 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3397 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3398 	.port_link_state = mv88e6352_port_link_state,
3399 	.port_get_cmode = mv88e6352_port_get_cmode,
3400 	.port_set_cmode = mv88e6390x_port_set_cmode,
3401 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3402 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3403 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3404 	.stats_get_strings = mv88e6320_stats_get_strings,
3405 	.stats_get_stats = mv88e6390_stats_get_stats,
3406 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3407 	.set_egress_port = mv88e6390_g1_set_egress_port,
3408 	.watchdog_ops = &mv88e6390_watchdog_ops,
3409 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3410 	.pot_clear = mv88e6xxx_g2_pot_clear,
3411 	.reset = mv88e6352_g1_reset,
3412 	.rmu_disable = mv88e6390_g1_rmu_disable,
3413 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3414 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3415 	.serdes_power = mv88e6390x_serdes_power,
3416 	.serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3417 	.serdes_irq_free = mv88e6390x_serdes_irq_free,
3418 	.gpio_ops = &mv88e6352_gpio_ops,
3419 	.phylink_validate = mv88e6390x_phylink_validate,
3420 };
3421 
3422 static const struct mv88e6xxx_ops mv88e6191_ops = {
3423 	/* MV88E6XXX_FAMILY_6390 */
3424 	.setup_errata = mv88e6390_setup_errata,
3425 	.irl_init_all = mv88e6390_g2_irl_init_all,
3426 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3427 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3428 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3429 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3430 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3431 	.port_set_link = mv88e6xxx_port_set_link,
3432 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3433 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3434 	.port_set_speed = mv88e6390_port_set_speed,
3435 	.port_tag_remap = mv88e6390_port_tag_remap,
3436 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3437 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3438 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3439 	.port_pause_limit = mv88e6390_port_pause_limit,
3440 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3441 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3442 	.port_link_state = mv88e6352_port_link_state,
3443 	.port_get_cmode = mv88e6352_port_get_cmode,
3444 	.port_set_cmode = mv88e6390_port_set_cmode,
3445 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3446 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3447 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3448 	.stats_get_strings = mv88e6320_stats_get_strings,
3449 	.stats_get_stats = mv88e6390_stats_get_stats,
3450 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3451 	.set_egress_port = mv88e6390_g1_set_egress_port,
3452 	.watchdog_ops = &mv88e6390_watchdog_ops,
3453 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3454 	.pot_clear = mv88e6xxx_g2_pot_clear,
3455 	.reset = mv88e6352_g1_reset,
3456 	.rmu_disable = mv88e6390_g1_rmu_disable,
3457 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3458 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3459 	.serdes_power = mv88e6390_serdes_power,
3460 	.serdes_irq_setup = mv88e6390_serdes_irq_setup,
3461 	.serdes_irq_free = mv88e6390_serdes_irq_free,
3462 	.avb_ops = &mv88e6390_avb_ops,
3463 	.ptp_ops = &mv88e6352_ptp_ops,
3464 	.phylink_validate = mv88e6390_phylink_validate,
3465 };
3466 
3467 static const struct mv88e6xxx_ops mv88e6240_ops = {
3468 	/* MV88E6XXX_FAMILY_6352 */
3469 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3470 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3471 	.irl_init_all = mv88e6352_g2_irl_init_all,
3472 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3473 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3474 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3475 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3476 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3477 	.port_set_link = mv88e6xxx_port_set_link,
3478 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3479 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3480 	.port_set_speed = mv88e6352_port_set_speed,
3481 	.port_tag_remap = mv88e6095_port_tag_remap,
3482 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3483 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3484 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3485 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3486 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3487 	.port_pause_limit = mv88e6097_port_pause_limit,
3488 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3489 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3490 	.port_link_state = mv88e6352_port_link_state,
3491 	.port_get_cmode = mv88e6352_port_get_cmode,
3492 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3493 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3494 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3495 	.stats_get_strings = mv88e6095_stats_get_strings,
3496 	.stats_get_stats = mv88e6095_stats_get_stats,
3497 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3498 	.set_egress_port = mv88e6095_g1_set_egress_port,
3499 	.watchdog_ops = &mv88e6097_watchdog_ops,
3500 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3501 	.pot_clear = mv88e6xxx_g2_pot_clear,
3502 	.reset = mv88e6352_g1_reset,
3503 	.rmu_disable = mv88e6352_g1_rmu_disable,
3504 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3505 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3506 	.serdes_power = mv88e6352_serdes_power,
3507 	.serdes_irq_setup = mv88e6352_serdes_irq_setup,
3508 	.serdes_irq_free = mv88e6352_serdes_irq_free,
3509 	.gpio_ops = &mv88e6352_gpio_ops,
3510 	.avb_ops = &mv88e6352_avb_ops,
3511 	.ptp_ops = &mv88e6352_ptp_ops,
3512 	.phylink_validate = mv88e6352_phylink_validate,
3513 };
3514 
3515 static const struct mv88e6xxx_ops mv88e6290_ops = {
3516 	/* MV88E6XXX_FAMILY_6390 */
3517 	.setup_errata = mv88e6390_setup_errata,
3518 	.irl_init_all = mv88e6390_g2_irl_init_all,
3519 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3520 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3521 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3522 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3523 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3524 	.port_set_link = mv88e6xxx_port_set_link,
3525 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3526 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3527 	.port_set_speed = mv88e6390_port_set_speed,
3528 	.port_tag_remap = mv88e6390_port_tag_remap,
3529 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3530 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3531 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3532 	.port_pause_limit = mv88e6390_port_pause_limit,
3533 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3534 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3535 	.port_link_state = mv88e6352_port_link_state,
3536 	.port_get_cmode = mv88e6352_port_get_cmode,
3537 	.port_set_cmode = mv88e6390_port_set_cmode,
3538 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3539 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3540 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3541 	.stats_get_strings = mv88e6320_stats_get_strings,
3542 	.stats_get_stats = mv88e6390_stats_get_stats,
3543 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3544 	.set_egress_port = mv88e6390_g1_set_egress_port,
3545 	.watchdog_ops = &mv88e6390_watchdog_ops,
3546 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3547 	.pot_clear = mv88e6xxx_g2_pot_clear,
3548 	.reset = mv88e6352_g1_reset,
3549 	.rmu_disable = mv88e6390_g1_rmu_disable,
3550 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3551 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3552 	.serdes_power = mv88e6390_serdes_power,
3553 	.serdes_irq_setup = mv88e6390_serdes_irq_setup,
3554 	.serdes_irq_free = mv88e6390_serdes_irq_free,
3555 	.gpio_ops = &mv88e6352_gpio_ops,
3556 	.avb_ops = &mv88e6390_avb_ops,
3557 	.ptp_ops = &mv88e6352_ptp_ops,
3558 	.phylink_validate = mv88e6390_phylink_validate,
3559 };
3560 
3561 static const struct mv88e6xxx_ops mv88e6320_ops = {
3562 	/* MV88E6XXX_FAMILY_6320 */
3563 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3564 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3565 	.irl_init_all = mv88e6352_g2_irl_init_all,
3566 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3567 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3568 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3569 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3570 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3571 	.port_set_link = mv88e6xxx_port_set_link,
3572 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3573 	.port_set_speed = mv88e6185_port_set_speed,
3574 	.port_tag_remap = mv88e6095_port_tag_remap,
3575 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3576 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3577 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3578 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3579 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3580 	.port_pause_limit = mv88e6097_port_pause_limit,
3581 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3582 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3583 	.port_link_state = mv88e6352_port_link_state,
3584 	.port_get_cmode = mv88e6352_port_get_cmode,
3585 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3586 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3587 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3588 	.stats_get_strings = mv88e6320_stats_get_strings,
3589 	.stats_get_stats = mv88e6320_stats_get_stats,
3590 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3591 	.set_egress_port = mv88e6095_g1_set_egress_port,
3592 	.watchdog_ops = &mv88e6390_watchdog_ops,
3593 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3594 	.pot_clear = mv88e6xxx_g2_pot_clear,
3595 	.reset = mv88e6352_g1_reset,
3596 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3597 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3598 	.gpio_ops = &mv88e6352_gpio_ops,
3599 	.avb_ops = &mv88e6352_avb_ops,
3600 	.ptp_ops = &mv88e6352_ptp_ops,
3601 	.phylink_validate = mv88e6185_phylink_validate,
3602 };
3603 
3604 static const struct mv88e6xxx_ops mv88e6321_ops = {
3605 	/* MV88E6XXX_FAMILY_6320 */
3606 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3607 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3608 	.irl_init_all = mv88e6352_g2_irl_init_all,
3609 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3610 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3611 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3612 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3613 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3614 	.port_set_link = mv88e6xxx_port_set_link,
3615 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3616 	.port_set_speed = mv88e6185_port_set_speed,
3617 	.port_tag_remap = mv88e6095_port_tag_remap,
3618 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3619 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3620 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3621 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3622 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3623 	.port_pause_limit = mv88e6097_port_pause_limit,
3624 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3625 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3626 	.port_link_state = mv88e6352_port_link_state,
3627 	.port_get_cmode = mv88e6352_port_get_cmode,
3628 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3629 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3630 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3631 	.stats_get_strings = mv88e6320_stats_get_strings,
3632 	.stats_get_stats = mv88e6320_stats_get_stats,
3633 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3634 	.set_egress_port = mv88e6095_g1_set_egress_port,
3635 	.watchdog_ops = &mv88e6390_watchdog_ops,
3636 	.reset = mv88e6352_g1_reset,
3637 	.vtu_getnext = mv88e6185_g1_vtu_getnext,
3638 	.vtu_loadpurge = mv88e6185_g1_vtu_loadpurge,
3639 	.gpio_ops = &mv88e6352_gpio_ops,
3640 	.avb_ops = &mv88e6352_avb_ops,
3641 	.ptp_ops = &mv88e6352_ptp_ops,
3642 	.phylink_validate = mv88e6185_phylink_validate,
3643 };
3644 
3645 static const struct mv88e6xxx_ops mv88e6341_ops = {
3646 	/* MV88E6XXX_FAMILY_6341 */
3647 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3648 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3649 	.irl_init_all = mv88e6352_g2_irl_init_all,
3650 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3651 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3652 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3653 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3654 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3655 	.port_set_link = mv88e6xxx_port_set_link,
3656 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3657 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3658 	.port_set_speed = mv88e6341_port_set_speed,
3659 	.port_tag_remap = mv88e6095_port_tag_remap,
3660 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3661 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3662 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3663 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3664 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3665 	.port_pause_limit = mv88e6097_port_pause_limit,
3666 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3667 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3668 	.port_link_state = mv88e6352_port_link_state,
3669 	.port_get_cmode = mv88e6352_port_get_cmode,
3670 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3671 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3672 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3673 	.stats_get_strings = mv88e6320_stats_get_strings,
3674 	.stats_get_stats = mv88e6390_stats_get_stats,
3675 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3676 	.set_egress_port = mv88e6390_g1_set_egress_port,
3677 	.watchdog_ops = &mv88e6390_watchdog_ops,
3678 	.mgmt_rsvd2cpu =  mv88e6390_g1_mgmt_rsvd2cpu,
3679 	.pot_clear = mv88e6xxx_g2_pot_clear,
3680 	.reset = mv88e6352_g1_reset,
3681 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3682 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3683 	.serdes_power = mv88e6341_serdes_power,
3684 	.gpio_ops = &mv88e6352_gpio_ops,
3685 	.avb_ops = &mv88e6390_avb_ops,
3686 	.ptp_ops = &mv88e6352_ptp_ops,
3687 	.phylink_validate = mv88e6390_phylink_validate,
3688 };
3689 
3690 static const struct mv88e6xxx_ops mv88e6350_ops = {
3691 	/* MV88E6XXX_FAMILY_6351 */
3692 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3693 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3694 	.irl_init_all = mv88e6352_g2_irl_init_all,
3695 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3696 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3697 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3698 	.port_set_link = mv88e6xxx_port_set_link,
3699 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3700 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3701 	.port_set_speed = mv88e6185_port_set_speed,
3702 	.port_tag_remap = mv88e6095_port_tag_remap,
3703 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3704 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3705 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3706 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3707 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3708 	.port_pause_limit = mv88e6097_port_pause_limit,
3709 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3710 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3711 	.port_link_state = mv88e6352_port_link_state,
3712 	.port_get_cmode = mv88e6352_port_get_cmode,
3713 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3714 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3715 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3716 	.stats_get_strings = mv88e6095_stats_get_strings,
3717 	.stats_get_stats = mv88e6095_stats_get_stats,
3718 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3719 	.set_egress_port = mv88e6095_g1_set_egress_port,
3720 	.watchdog_ops = &mv88e6097_watchdog_ops,
3721 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3722 	.pot_clear = mv88e6xxx_g2_pot_clear,
3723 	.reset = mv88e6352_g1_reset,
3724 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3725 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3726 	.phylink_validate = mv88e6185_phylink_validate,
3727 };
3728 
3729 static const struct mv88e6xxx_ops mv88e6351_ops = {
3730 	/* MV88E6XXX_FAMILY_6351 */
3731 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3732 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3733 	.irl_init_all = mv88e6352_g2_irl_init_all,
3734 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3735 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3736 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3737 	.port_set_link = mv88e6xxx_port_set_link,
3738 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3739 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3740 	.port_set_speed = mv88e6185_port_set_speed,
3741 	.port_tag_remap = mv88e6095_port_tag_remap,
3742 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3743 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3744 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3745 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3746 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3747 	.port_pause_limit = mv88e6097_port_pause_limit,
3748 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3749 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3750 	.port_link_state = mv88e6352_port_link_state,
3751 	.port_get_cmode = mv88e6352_port_get_cmode,
3752 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3753 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3754 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3755 	.stats_get_strings = mv88e6095_stats_get_strings,
3756 	.stats_get_stats = mv88e6095_stats_get_stats,
3757 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3758 	.set_egress_port = mv88e6095_g1_set_egress_port,
3759 	.watchdog_ops = &mv88e6097_watchdog_ops,
3760 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3761 	.pot_clear = mv88e6xxx_g2_pot_clear,
3762 	.reset = mv88e6352_g1_reset,
3763 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3764 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3765 	.avb_ops = &mv88e6352_avb_ops,
3766 	.ptp_ops = &mv88e6352_ptp_ops,
3767 	.phylink_validate = mv88e6185_phylink_validate,
3768 };
3769 
3770 static const struct mv88e6xxx_ops mv88e6352_ops = {
3771 	/* MV88E6XXX_FAMILY_6352 */
3772 	.ieee_pri_map = mv88e6085_g1_ieee_pri_map,
3773 	.ip_pri_map = mv88e6085_g1_ip_pri_map,
3774 	.irl_init_all = mv88e6352_g2_irl_init_all,
3775 	.get_eeprom = mv88e6xxx_g2_get_eeprom16,
3776 	.set_eeprom = mv88e6xxx_g2_set_eeprom16,
3777 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3778 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3779 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3780 	.port_set_link = mv88e6xxx_port_set_link,
3781 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3782 	.port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay,
3783 	.port_set_speed = mv88e6352_port_set_speed,
3784 	.port_tag_remap = mv88e6095_port_tag_remap,
3785 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3786 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3787 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3788 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3789 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3790 	.port_pause_limit = mv88e6097_port_pause_limit,
3791 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3792 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3793 	.port_link_state = mv88e6352_port_link_state,
3794 	.port_get_cmode = mv88e6352_port_get_cmode,
3795 	.stats_snapshot = mv88e6320_g1_stats_snapshot,
3796 	.stats_set_histogram = mv88e6095_g1_stats_set_histogram,
3797 	.stats_get_sset_count = mv88e6095_stats_get_sset_count,
3798 	.stats_get_strings = mv88e6095_stats_get_strings,
3799 	.stats_get_stats = mv88e6095_stats_get_stats,
3800 	.set_cpu_port = mv88e6095_g1_set_cpu_port,
3801 	.set_egress_port = mv88e6095_g1_set_egress_port,
3802 	.watchdog_ops = &mv88e6097_watchdog_ops,
3803 	.mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu,
3804 	.pot_clear = mv88e6xxx_g2_pot_clear,
3805 	.reset = mv88e6352_g1_reset,
3806 	.rmu_disable = mv88e6352_g1_rmu_disable,
3807 	.vtu_getnext = mv88e6352_g1_vtu_getnext,
3808 	.vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
3809 	.serdes_power = mv88e6352_serdes_power,
3810 	.serdes_irq_setup = mv88e6352_serdes_irq_setup,
3811 	.serdes_irq_free = mv88e6352_serdes_irq_free,
3812 	.gpio_ops = &mv88e6352_gpio_ops,
3813 	.avb_ops = &mv88e6352_avb_ops,
3814 	.ptp_ops = &mv88e6352_ptp_ops,
3815 	.serdes_get_sset_count = mv88e6352_serdes_get_sset_count,
3816 	.serdes_get_strings = mv88e6352_serdes_get_strings,
3817 	.serdes_get_stats = mv88e6352_serdes_get_stats,
3818 	.phylink_validate = mv88e6352_phylink_validate,
3819 };
3820 
3821 static const struct mv88e6xxx_ops mv88e6390_ops = {
3822 	/* MV88E6XXX_FAMILY_6390 */
3823 	.setup_errata = mv88e6390_setup_errata,
3824 	.irl_init_all = mv88e6390_g2_irl_init_all,
3825 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3826 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3827 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3828 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3829 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3830 	.port_set_link = mv88e6xxx_port_set_link,
3831 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3832 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3833 	.port_set_speed = mv88e6390_port_set_speed,
3834 	.port_tag_remap = mv88e6390_port_tag_remap,
3835 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3836 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3837 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3838 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3839 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3840 	.port_pause_limit = mv88e6390_port_pause_limit,
3841 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3842 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3843 	.port_link_state = mv88e6352_port_link_state,
3844 	.port_get_cmode = mv88e6352_port_get_cmode,
3845 	.port_set_cmode = mv88e6390_port_set_cmode,
3846 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3847 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3848 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3849 	.stats_get_strings = mv88e6320_stats_get_strings,
3850 	.stats_get_stats = mv88e6390_stats_get_stats,
3851 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3852 	.set_egress_port = mv88e6390_g1_set_egress_port,
3853 	.watchdog_ops = &mv88e6390_watchdog_ops,
3854 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3855 	.pot_clear = mv88e6xxx_g2_pot_clear,
3856 	.reset = mv88e6352_g1_reset,
3857 	.rmu_disable = mv88e6390_g1_rmu_disable,
3858 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3859 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3860 	.serdes_power = mv88e6390_serdes_power,
3861 	.serdes_irq_setup = mv88e6390_serdes_irq_setup,
3862 	.serdes_irq_free = mv88e6390_serdes_irq_free,
3863 	.gpio_ops = &mv88e6352_gpio_ops,
3864 	.avb_ops = &mv88e6390_avb_ops,
3865 	.ptp_ops = &mv88e6352_ptp_ops,
3866 	.phylink_validate = mv88e6390_phylink_validate,
3867 };
3868 
3869 static const struct mv88e6xxx_ops mv88e6390x_ops = {
3870 	/* MV88E6XXX_FAMILY_6390 */
3871 	.setup_errata = mv88e6390_setup_errata,
3872 	.irl_init_all = mv88e6390_g2_irl_init_all,
3873 	.get_eeprom = mv88e6xxx_g2_get_eeprom8,
3874 	.set_eeprom = mv88e6xxx_g2_set_eeprom8,
3875 	.set_switch_mac = mv88e6xxx_g2_set_switch_mac,
3876 	.phy_read = mv88e6xxx_g2_smi_phy_read,
3877 	.phy_write = mv88e6xxx_g2_smi_phy_write,
3878 	.port_set_link = mv88e6xxx_port_set_link,
3879 	.port_set_duplex = mv88e6xxx_port_set_duplex,
3880 	.port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay,
3881 	.port_set_speed = mv88e6390x_port_set_speed,
3882 	.port_tag_remap = mv88e6390_port_tag_remap,
3883 	.port_set_frame_mode = mv88e6351_port_set_frame_mode,
3884 	.port_set_egress_floods = mv88e6352_port_set_egress_floods,
3885 	.port_set_ether_type = mv88e6351_port_set_ether_type,
3886 	.port_set_jumbo_size = mv88e6165_port_set_jumbo_size,
3887 	.port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting,
3888 	.port_pause_limit = mv88e6390_port_pause_limit,
3889 	.port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit,
3890 	.port_disable_pri_override = mv88e6xxx_port_disable_pri_override,
3891 	.port_link_state = mv88e6352_port_link_state,
3892 	.port_get_cmode = mv88e6352_port_get_cmode,
3893 	.port_set_cmode = mv88e6390x_port_set_cmode,
3894 	.stats_snapshot = mv88e6390_g1_stats_snapshot,
3895 	.stats_set_histogram = mv88e6390_g1_stats_set_histogram,
3896 	.stats_get_sset_count = mv88e6320_stats_get_sset_count,
3897 	.stats_get_strings = mv88e6320_stats_get_strings,
3898 	.stats_get_stats = mv88e6390_stats_get_stats,
3899 	.set_cpu_port = mv88e6390_g1_set_cpu_port,
3900 	.set_egress_port = mv88e6390_g1_set_egress_port,
3901 	.watchdog_ops = &mv88e6390_watchdog_ops,
3902 	.mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu,
3903 	.pot_clear = mv88e6xxx_g2_pot_clear,
3904 	.reset = mv88e6352_g1_reset,
3905 	.rmu_disable = mv88e6390_g1_rmu_disable,
3906 	.vtu_getnext = mv88e6390_g1_vtu_getnext,
3907 	.vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
3908 	.serdes_power = mv88e6390x_serdes_power,
3909 	.serdes_irq_setup = mv88e6390x_serdes_irq_setup,
3910 	.serdes_irq_free = mv88e6390x_serdes_irq_free,
3911 	.gpio_ops = &mv88e6352_gpio_ops,
3912 	.avb_ops = &mv88e6390_avb_ops,
3913 	.ptp_ops = &mv88e6352_ptp_ops,
3914 	.phylink_validate = mv88e6390x_phylink_validate,
3915 };
3916 
3917 static const struct mv88e6xxx_info mv88e6xxx_table[] = {
3918 	[MV88E6085] = {
3919 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085,
3920 		.family = MV88E6XXX_FAMILY_6097,
3921 		.name = "Marvell 88E6085",
3922 		.num_databases = 4096,
3923 		.num_ports = 10,
3924 		.num_internal_phys = 5,
3925 		.max_vid = 4095,
3926 		.port_base_addr = 0x10,
3927 		.phy_base_addr = 0x0,
3928 		.global1_addr = 0x1b,
3929 		.global2_addr = 0x1c,
3930 		.age_time_coeff = 15000,
3931 		.g1_irqs = 8,
3932 		.g2_irqs = 10,
3933 		.atu_move_port_mask = 0xf,
3934 		.pvt = true,
3935 		.multi_chip = true,
3936 		.tag_protocol = DSA_TAG_PROTO_DSA,
3937 		.ops = &mv88e6085_ops,
3938 	},
3939 
3940 	[MV88E6095] = {
3941 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095,
3942 		.family = MV88E6XXX_FAMILY_6095,
3943 		.name = "Marvell 88E6095/88E6095F",
3944 		.num_databases = 256,
3945 		.num_ports = 11,
3946 		.num_internal_phys = 0,
3947 		.max_vid = 4095,
3948 		.port_base_addr = 0x10,
3949 		.phy_base_addr = 0x0,
3950 		.global1_addr = 0x1b,
3951 		.global2_addr = 0x1c,
3952 		.age_time_coeff = 15000,
3953 		.g1_irqs = 8,
3954 		.atu_move_port_mask = 0xf,
3955 		.multi_chip = true,
3956 		.tag_protocol = DSA_TAG_PROTO_DSA,
3957 		.ops = &mv88e6095_ops,
3958 	},
3959 
3960 	[MV88E6097] = {
3961 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097,
3962 		.family = MV88E6XXX_FAMILY_6097,
3963 		.name = "Marvell 88E6097/88E6097F",
3964 		.num_databases = 4096,
3965 		.num_ports = 11,
3966 		.num_internal_phys = 8,
3967 		.max_vid = 4095,
3968 		.port_base_addr = 0x10,
3969 		.phy_base_addr = 0x0,
3970 		.global1_addr = 0x1b,
3971 		.global2_addr = 0x1c,
3972 		.age_time_coeff = 15000,
3973 		.g1_irqs = 8,
3974 		.g2_irqs = 10,
3975 		.atu_move_port_mask = 0xf,
3976 		.pvt = true,
3977 		.multi_chip = true,
3978 		.tag_protocol = DSA_TAG_PROTO_EDSA,
3979 		.ops = &mv88e6097_ops,
3980 	},
3981 
3982 	[MV88E6123] = {
3983 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123,
3984 		.family = MV88E6XXX_FAMILY_6165,
3985 		.name = "Marvell 88E6123",
3986 		.num_databases = 4096,
3987 		.num_ports = 3,
3988 		.num_internal_phys = 5,
3989 		.max_vid = 4095,
3990 		.port_base_addr = 0x10,
3991 		.phy_base_addr = 0x0,
3992 		.global1_addr = 0x1b,
3993 		.global2_addr = 0x1c,
3994 		.age_time_coeff = 15000,
3995 		.g1_irqs = 9,
3996 		.g2_irqs = 10,
3997 		.atu_move_port_mask = 0xf,
3998 		.pvt = true,
3999 		.multi_chip = true,
4000 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4001 		.ops = &mv88e6123_ops,
4002 	},
4003 
4004 	[MV88E6131] = {
4005 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131,
4006 		.family = MV88E6XXX_FAMILY_6185,
4007 		.name = "Marvell 88E6131",
4008 		.num_databases = 256,
4009 		.num_ports = 8,
4010 		.num_internal_phys = 0,
4011 		.max_vid = 4095,
4012 		.port_base_addr = 0x10,
4013 		.phy_base_addr = 0x0,
4014 		.global1_addr = 0x1b,
4015 		.global2_addr = 0x1c,
4016 		.age_time_coeff = 15000,
4017 		.g1_irqs = 9,
4018 		.atu_move_port_mask = 0xf,
4019 		.multi_chip = true,
4020 		.tag_protocol = DSA_TAG_PROTO_DSA,
4021 		.ops = &mv88e6131_ops,
4022 	},
4023 
4024 	[MV88E6141] = {
4025 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141,
4026 		.family = MV88E6XXX_FAMILY_6341,
4027 		.name = "Marvell 88E6141",
4028 		.num_databases = 4096,
4029 		.num_ports = 6,
4030 		.num_internal_phys = 5,
4031 		.num_gpio = 11,
4032 		.max_vid = 4095,
4033 		.port_base_addr = 0x10,
4034 		.phy_base_addr = 0x10,
4035 		.global1_addr = 0x1b,
4036 		.global2_addr = 0x1c,
4037 		.age_time_coeff = 3750,
4038 		.atu_move_port_mask = 0x1f,
4039 		.g1_irqs = 9,
4040 		.g2_irqs = 10,
4041 		.pvt = true,
4042 		.multi_chip = true,
4043 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4044 		.ops = &mv88e6141_ops,
4045 	},
4046 
4047 	[MV88E6161] = {
4048 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161,
4049 		.family = MV88E6XXX_FAMILY_6165,
4050 		.name = "Marvell 88E6161",
4051 		.num_databases = 4096,
4052 		.num_ports = 6,
4053 		.num_internal_phys = 5,
4054 		.max_vid = 4095,
4055 		.port_base_addr = 0x10,
4056 		.phy_base_addr = 0x0,
4057 		.global1_addr = 0x1b,
4058 		.global2_addr = 0x1c,
4059 		.age_time_coeff = 15000,
4060 		.g1_irqs = 9,
4061 		.g2_irqs = 10,
4062 		.atu_move_port_mask = 0xf,
4063 		.pvt = true,
4064 		.multi_chip = true,
4065 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4066 		.ptp_support = true,
4067 		.ops = &mv88e6161_ops,
4068 	},
4069 
4070 	[MV88E6165] = {
4071 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165,
4072 		.family = MV88E6XXX_FAMILY_6165,
4073 		.name = "Marvell 88E6165",
4074 		.num_databases = 4096,
4075 		.num_ports = 6,
4076 		.num_internal_phys = 0,
4077 		.max_vid = 4095,
4078 		.port_base_addr = 0x10,
4079 		.phy_base_addr = 0x0,
4080 		.global1_addr = 0x1b,
4081 		.global2_addr = 0x1c,
4082 		.age_time_coeff = 15000,
4083 		.g1_irqs = 9,
4084 		.g2_irqs = 10,
4085 		.atu_move_port_mask = 0xf,
4086 		.pvt = true,
4087 		.multi_chip = true,
4088 		.tag_protocol = DSA_TAG_PROTO_DSA,
4089 		.ptp_support = true,
4090 		.ops = &mv88e6165_ops,
4091 	},
4092 
4093 	[MV88E6171] = {
4094 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171,
4095 		.family = MV88E6XXX_FAMILY_6351,
4096 		.name = "Marvell 88E6171",
4097 		.num_databases = 4096,
4098 		.num_ports = 7,
4099 		.num_internal_phys = 5,
4100 		.max_vid = 4095,
4101 		.port_base_addr = 0x10,
4102 		.phy_base_addr = 0x0,
4103 		.global1_addr = 0x1b,
4104 		.global2_addr = 0x1c,
4105 		.age_time_coeff = 15000,
4106 		.g1_irqs = 9,
4107 		.g2_irqs = 10,
4108 		.atu_move_port_mask = 0xf,
4109 		.pvt = true,
4110 		.multi_chip = true,
4111 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4112 		.ops = &mv88e6171_ops,
4113 	},
4114 
4115 	[MV88E6172] = {
4116 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172,
4117 		.family = MV88E6XXX_FAMILY_6352,
4118 		.name = "Marvell 88E6172",
4119 		.num_databases = 4096,
4120 		.num_ports = 7,
4121 		.num_internal_phys = 5,
4122 		.num_gpio = 15,
4123 		.max_vid = 4095,
4124 		.port_base_addr = 0x10,
4125 		.phy_base_addr = 0x0,
4126 		.global1_addr = 0x1b,
4127 		.global2_addr = 0x1c,
4128 		.age_time_coeff = 15000,
4129 		.g1_irqs = 9,
4130 		.g2_irqs = 10,
4131 		.atu_move_port_mask = 0xf,
4132 		.pvt = true,
4133 		.multi_chip = true,
4134 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4135 		.ops = &mv88e6172_ops,
4136 	},
4137 
4138 	[MV88E6175] = {
4139 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175,
4140 		.family = MV88E6XXX_FAMILY_6351,
4141 		.name = "Marvell 88E6175",
4142 		.num_databases = 4096,
4143 		.num_ports = 7,
4144 		.num_internal_phys = 5,
4145 		.max_vid = 4095,
4146 		.port_base_addr = 0x10,
4147 		.phy_base_addr = 0x0,
4148 		.global1_addr = 0x1b,
4149 		.global2_addr = 0x1c,
4150 		.age_time_coeff = 15000,
4151 		.g1_irqs = 9,
4152 		.g2_irqs = 10,
4153 		.atu_move_port_mask = 0xf,
4154 		.pvt = true,
4155 		.multi_chip = true,
4156 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4157 		.ops = &mv88e6175_ops,
4158 	},
4159 
4160 	[MV88E6176] = {
4161 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176,
4162 		.family = MV88E6XXX_FAMILY_6352,
4163 		.name = "Marvell 88E6176",
4164 		.num_databases = 4096,
4165 		.num_ports = 7,
4166 		.num_internal_phys = 5,
4167 		.num_gpio = 15,
4168 		.max_vid = 4095,
4169 		.port_base_addr = 0x10,
4170 		.phy_base_addr = 0x0,
4171 		.global1_addr = 0x1b,
4172 		.global2_addr = 0x1c,
4173 		.age_time_coeff = 15000,
4174 		.g1_irqs = 9,
4175 		.g2_irqs = 10,
4176 		.atu_move_port_mask = 0xf,
4177 		.pvt = true,
4178 		.multi_chip = true,
4179 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4180 		.ops = &mv88e6176_ops,
4181 	},
4182 
4183 	[MV88E6185] = {
4184 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185,
4185 		.family = MV88E6XXX_FAMILY_6185,
4186 		.name = "Marvell 88E6185",
4187 		.num_databases = 256,
4188 		.num_ports = 10,
4189 		.num_internal_phys = 0,
4190 		.max_vid = 4095,
4191 		.port_base_addr = 0x10,
4192 		.phy_base_addr = 0x0,
4193 		.global1_addr = 0x1b,
4194 		.global2_addr = 0x1c,
4195 		.age_time_coeff = 15000,
4196 		.g1_irqs = 8,
4197 		.atu_move_port_mask = 0xf,
4198 		.multi_chip = true,
4199 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4200 		.ops = &mv88e6185_ops,
4201 	},
4202 
4203 	[MV88E6190] = {
4204 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190,
4205 		.family = MV88E6XXX_FAMILY_6390,
4206 		.name = "Marvell 88E6190",
4207 		.num_databases = 4096,
4208 		.num_ports = 11,	/* 10 + Z80 */
4209 		.num_internal_phys = 11,
4210 		.num_gpio = 16,
4211 		.max_vid = 8191,
4212 		.port_base_addr = 0x0,
4213 		.phy_base_addr = 0x0,
4214 		.global1_addr = 0x1b,
4215 		.global2_addr = 0x1c,
4216 		.tag_protocol = DSA_TAG_PROTO_DSA,
4217 		.age_time_coeff = 3750,
4218 		.g1_irqs = 9,
4219 		.g2_irqs = 14,
4220 		.pvt = true,
4221 		.multi_chip = true,
4222 		.atu_move_port_mask = 0x1f,
4223 		.ops = &mv88e6190_ops,
4224 	},
4225 
4226 	[MV88E6190X] = {
4227 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X,
4228 		.family = MV88E6XXX_FAMILY_6390,
4229 		.name = "Marvell 88E6190X",
4230 		.num_databases = 4096,
4231 		.num_ports = 11,	/* 10 + Z80 */
4232 		.num_internal_phys = 11,
4233 		.num_gpio = 16,
4234 		.max_vid = 8191,
4235 		.port_base_addr = 0x0,
4236 		.phy_base_addr = 0x0,
4237 		.global1_addr = 0x1b,
4238 		.global2_addr = 0x1c,
4239 		.age_time_coeff = 3750,
4240 		.g1_irqs = 9,
4241 		.g2_irqs = 14,
4242 		.atu_move_port_mask = 0x1f,
4243 		.pvt = true,
4244 		.multi_chip = true,
4245 		.tag_protocol = DSA_TAG_PROTO_DSA,
4246 		.ops = &mv88e6190x_ops,
4247 	},
4248 
4249 	[MV88E6191] = {
4250 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191,
4251 		.family = MV88E6XXX_FAMILY_6390,
4252 		.name = "Marvell 88E6191",
4253 		.num_databases = 4096,
4254 		.num_ports = 11,	/* 10 + Z80 */
4255 		.num_internal_phys = 11,
4256 		.max_vid = 8191,
4257 		.port_base_addr = 0x0,
4258 		.phy_base_addr = 0x0,
4259 		.global1_addr = 0x1b,
4260 		.global2_addr = 0x1c,
4261 		.age_time_coeff = 3750,
4262 		.g1_irqs = 9,
4263 		.g2_irqs = 14,
4264 		.atu_move_port_mask = 0x1f,
4265 		.pvt = true,
4266 		.multi_chip = true,
4267 		.tag_protocol = DSA_TAG_PROTO_DSA,
4268 		.ptp_support = true,
4269 		.ops = &mv88e6191_ops,
4270 	},
4271 
4272 	[MV88E6240] = {
4273 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240,
4274 		.family = MV88E6XXX_FAMILY_6352,
4275 		.name = "Marvell 88E6240",
4276 		.num_databases = 4096,
4277 		.num_ports = 7,
4278 		.num_internal_phys = 5,
4279 		.num_gpio = 15,
4280 		.max_vid = 4095,
4281 		.port_base_addr = 0x10,
4282 		.phy_base_addr = 0x0,
4283 		.global1_addr = 0x1b,
4284 		.global2_addr = 0x1c,
4285 		.age_time_coeff = 15000,
4286 		.g1_irqs = 9,
4287 		.g2_irqs = 10,
4288 		.atu_move_port_mask = 0xf,
4289 		.pvt = true,
4290 		.multi_chip = true,
4291 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4292 		.ptp_support = true,
4293 		.ops = &mv88e6240_ops,
4294 	},
4295 
4296 	[MV88E6290] = {
4297 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290,
4298 		.family = MV88E6XXX_FAMILY_6390,
4299 		.name = "Marvell 88E6290",
4300 		.num_databases = 4096,
4301 		.num_ports = 11,	/* 10 + Z80 */
4302 		.num_internal_phys = 11,
4303 		.num_gpio = 16,
4304 		.max_vid = 8191,
4305 		.port_base_addr = 0x0,
4306 		.phy_base_addr = 0x0,
4307 		.global1_addr = 0x1b,
4308 		.global2_addr = 0x1c,
4309 		.age_time_coeff = 3750,
4310 		.g1_irqs = 9,
4311 		.g2_irqs = 14,
4312 		.atu_move_port_mask = 0x1f,
4313 		.pvt = true,
4314 		.multi_chip = true,
4315 		.tag_protocol = DSA_TAG_PROTO_DSA,
4316 		.ptp_support = true,
4317 		.ops = &mv88e6290_ops,
4318 	},
4319 
4320 	[MV88E6320] = {
4321 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320,
4322 		.family = MV88E6XXX_FAMILY_6320,
4323 		.name = "Marvell 88E6320",
4324 		.num_databases = 4096,
4325 		.num_ports = 7,
4326 		.num_internal_phys = 5,
4327 		.num_gpio = 15,
4328 		.max_vid = 4095,
4329 		.port_base_addr = 0x10,
4330 		.phy_base_addr = 0x0,
4331 		.global1_addr = 0x1b,
4332 		.global2_addr = 0x1c,
4333 		.age_time_coeff = 15000,
4334 		.g1_irqs = 8,
4335 		.g2_irqs = 10,
4336 		.atu_move_port_mask = 0xf,
4337 		.pvt = true,
4338 		.multi_chip = true,
4339 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4340 		.ptp_support = true,
4341 		.ops = &mv88e6320_ops,
4342 	},
4343 
4344 	[MV88E6321] = {
4345 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321,
4346 		.family = MV88E6XXX_FAMILY_6320,
4347 		.name = "Marvell 88E6321",
4348 		.num_databases = 4096,
4349 		.num_ports = 7,
4350 		.num_internal_phys = 5,
4351 		.num_gpio = 15,
4352 		.max_vid = 4095,
4353 		.port_base_addr = 0x10,
4354 		.phy_base_addr = 0x0,
4355 		.global1_addr = 0x1b,
4356 		.global2_addr = 0x1c,
4357 		.age_time_coeff = 15000,
4358 		.g1_irqs = 8,
4359 		.g2_irqs = 10,
4360 		.atu_move_port_mask = 0xf,
4361 		.multi_chip = true,
4362 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4363 		.ptp_support = true,
4364 		.ops = &mv88e6321_ops,
4365 	},
4366 
4367 	[MV88E6341] = {
4368 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341,
4369 		.family = MV88E6XXX_FAMILY_6341,
4370 		.name = "Marvell 88E6341",
4371 		.num_databases = 4096,
4372 		.num_internal_phys = 5,
4373 		.num_ports = 6,
4374 		.num_gpio = 11,
4375 		.max_vid = 4095,
4376 		.port_base_addr = 0x10,
4377 		.phy_base_addr = 0x10,
4378 		.global1_addr = 0x1b,
4379 		.global2_addr = 0x1c,
4380 		.age_time_coeff = 3750,
4381 		.atu_move_port_mask = 0x1f,
4382 		.g1_irqs = 9,
4383 		.g2_irqs = 10,
4384 		.pvt = true,
4385 		.multi_chip = true,
4386 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4387 		.ptp_support = true,
4388 		.ops = &mv88e6341_ops,
4389 	},
4390 
4391 	[MV88E6350] = {
4392 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350,
4393 		.family = MV88E6XXX_FAMILY_6351,
4394 		.name = "Marvell 88E6350",
4395 		.num_databases = 4096,
4396 		.num_ports = 7,
4397 		.num_internal_phys = 5,
4398 		.max_vid = 4095,
4399 		.port_base_addr = 0x10,
4400 		.phy_base_addr = 0x0,
4401 		.global1_addr = 0x1b,
4402 		.global2_addr = 0x1c,
4403 		.age_time_coeff = 15000,
4404 		.g1_irqs = 9,
4405 		.g2_irqs = 10,
4406 		.atu_move_port_mask = 0xf,
4407 		.pvt = true,
4408 		.multi_chip = true,
4409 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4410 		.ops = &mv88e6350_ops,
4411 	},
4412 
4413 	[MV88E6351] = {
4414 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351,
4415 		.family = MV88E6XXX_FAMILY_6351,
4416 		.name = "Marvell 88E6351",
4417 		.num_databases = 4096,
4418 		.num_ports = 7,
4419 		.num_internal_phys = 5,
4420 		.max_vid = 4095,
4421 		.port_base_addr = 0x10,
4422 		.phy_base_addr = 0x0,
4423 		.global1_addr = 0x1b,
4424 		.global2_addr = 0x1c,
4425 		.age_time_coeff = 15000,
4426 		.g1_irqs = 9,
4427 		.g2_irqs = 10,
4428 		.atu_move_port_mask = 0xf,
4429 		.pvt = true,
4430 		.multi_chip = true,
4431 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4432 		.ops = &mv88e6351_ops,
4433 	},
4434 
4435 	[MV88E6352] = {
4436 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352,
4437 		.family = MV88E6XXX_FAMILY_6352,
4438 		.name = "Marvell 88E6352",
4439 		.num_databases = 4096,
4440 		.num_ports = 7,
4441 		.num_internal_phys = 5,
4442 		.num_gpio = 15,
4443 		.max_vid = 4095,
4444 		.port_base_addr = 0x10,
4445 		.phy_base_addr = 0x0,
4446 		.global1_addr = 0x1b,
4447 		.global2_addr = 0x1c,
4448 		.age_time_coeff = 15000,
4449 		.g1_irqs = 9,
4450 		.g2_irqs = 10,
4451 		.atu_move_port_mask = 0xf,
4452 		.pvt = true,
4453 		.multi_chip = true,
4454 		.tag_protocol = DSA_TAG_PROTO_EDSA,
4455 		.ptp_support = true,
4456 		.ops = &mv88e6352_ops,
4457 	},
4458 	[MV88E6390] = {
4459 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390,
4460 		.family = MV88E6XXX_FAMILY_6390,
4461 		.name = "Marvell 88E6390",
4462 		.num_databases = 4096,
4463 		.num_ports = 11,	/* 10 + Z80 */
4464 		.num_internal_phys = 11,
4465 		.num_gpio = 16,
4466 		.max_vid = 8191,
4467 		.port_base_addr = 0x0,
4468 		.phy_base_addr = 0x0,
4469 		.global1_addr = 0x1b,
4470 		.global2_addr = 0x1c,
4471 		.age_time_coeff = 3750,
4472 		.g1_irqs = 9,
4473 		.g2_irqs = 14,
4474 		.atu_move_port_mask = 0x1f,
4475 		.pvt = true,
4476 		.multi_chip = true,
4477 		.tag_protocol = DSA_TAG_PROTO_DSA,
4478 		.ptp_support = true,
4479 		.ops = &mv88e6390_ops,
4480 	},
4481 	[MV88E6390X] = {
4482 		.prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X,
4483 		.family = MV88E6XXX_FAMILY_6390,
4484 		.name = "Marvell 88E6390X",
4485 		.num_databases = 4096,
4486 		.num_ports = 11,	/* 10 + Z80 */
4487 		.num_internal_phys = 11,
4488 		.num_gpio = 16,
4489 		.max_vid = 8191,
4490 		.port_base_addr = 0x0,
4491 		.phy_base_addr = 0x0,
4492 		.global1_addr = 0x1b,
4493 		.global2_addr = 0x1c,
4494 		.age_time_coeff = 3750,
4495 		.g1_irqs = 9,
4496 		.g2_irqs = 14,
4497 		.atu_move_port_mask = 0x1f,
4498 		.pvt = true,
4499 		.multi_chip = true,
4500 		.tag_protocol = DSA_TAG_PROTO_DSA,
4501 		.ptp_support = true,
4502 		.ops = &mv88e6390x_ops,
4503 	},
4504 };
4505 
4506 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num)
4507 {
4508 	int i;
4509 
4510 	for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i)
4511 		if (mv88e6xxx_table[i].prod_num == prod_num)
4512 			return &mv88e6xxx_table[i];
4513 
4514 	return NULL;
4515 }
4516 
4517 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip)
4518 {
4519 	const struct mv88e6xxx_info *info;
4520 	unsigned int prod_num, rev;
4521 	u16 id;
4522 	int err;
4523 
4524 	mutex_lock(&chip->reg_lock);
4525 	err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id);
4526 	mutex_unlock(&chip->reg_lock);
4527 	if (err)
4528 		return err;
4529 
4530 	prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK;
4531 	rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK;
4532 
4533 	info = mv88e6xxx_lookup_info(prod_num);
4534 	if (!info)
4535 		return -ENODEV;
4536 
4537 	/* Update the compatible info with the probed one */
4538 	chip->info = info;
4539 
4540 	err = mv88e6xxx_g2_require(chip);
4541 	if (err)
4542 		return err;
4543 
4544 	dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n",
4545 		 chip->info->prod_num, chip->info->name, rev);
4546 
4547 	return 0;
4548 }
4549 
4550 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev)
4551 {
4552 	struct mv88e6xxx_chip *chip;
4553 
4554 	chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
4555 	if (!chip)
4556 		return NULL;
4557 
4558 	chip->dev = dev;
4559 
4560 	mutex_init(&chip->reg_lock);
4561 	INIT_LIST_HEAD(&chip->mdios);
4562 
4563 	return chip;
4564 }
4565 
4566 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip,
4567 			      struct mii_bus *bus, int sw_addr)
4568 {
4569 	if (sw_addr == 0)
4570 		chip->smi_ops = &mv88e6xxx_smi_single_chip_ops;
4571 	else if (chip->info->multi_chip)
4572 		chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops;
4573 	else
4574 		return -EINVAL;
4575 
4576 	chip->bus = bus;
4577 	chip->sw_addr = sw_addr;
4578 
4579 	return 0;
4580 }
4581 
4582 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds,
4583 							int port)
4584 {
4585 	struct mv88e6xxx_chip *chip = ds->priv;
4586 
4587 	return chip->info->tag_protocol;
4588 }
4589 
4590 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4591 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev,
4592 				       struct device *host_dev, int sw_addr,
4593 				       void **priv)
4594 {
4595 	struct mv88e6xxx_chip *chip;
4596 	struct mii_bus *bus;
4597 	int err;
4598 
4599 	bus = dsa_host_dev_to_mii_bus(host_dev);
4600 	if (!bus)
4601 		return NULL;
4602 
4603 	chip = mv88e6xxx_alloc_chip(dsa_dev);
4604 	if (!chip)
4605 		return NULL;
4606 
4607 	/* Legacy SMI probing will only support chips similar to 88E6085 */
4608 	chip->info = &mv88e6xxx_table[MV88E6085];
4609 
4610 	err = mv88e6xxx_smi_init(chip, bus, sw_addr);
4611 	if (err)
4612 		goto free;
4613 
4614 	err = mv88e6xxx_detect(chip);
4615 	if (err)
4616 		goto free;
4617 
4618 	mutex_lock(&chip->reg_lock);
4619 	err = mv88e6xxx_switch_reset(chip);
4620 	mutex_unlock(&chip->reg_lock);
4621 	if (err)
4622 		goto free;
4623 
4624 	mv88e6xxx_phy_init(chip);
4625 
4626 	err = mv88e6xxx_mdios_register(chip, NULL);
4627 	if (err)
4628 		goto free;
4629 
4630 	*priv = chip;
4631 
4632 	return chip->info->name;
4633 free:
4634 	devm_kfree(dsa_dev, chip);
4635 
4636 	return NULL;
4637 }
4638 #endif
4639 
4640 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port,
4641 				      const struct switchdev_obj_port_mdb *mdb)
4642 {
4643 	/* We don't need any dynamic resource from the kernel (yet),
4644 	 * so skip the prepare phase.
4645 	 */
4646 
4647 	return 0;
4648 }
4649 
4650 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port,
4651 				   const struct switchdev_obj_port_mdb *mdb)
4652 {
4653 	struct mv88e6xxx_chip *chip = ds->priv;
4654 
4655 	mutex_lock(&chip->reg_lock);
4656 	if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4657 					 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC))
4658 		dev_err(ds->dev, "p%d: failed to load multicast MAC address\n",
4659 			port);
4660 	mutex_unlock(&chip->reg_lock);
4661 }
4662 
4663 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port,
4664 				  const struct switchdev_obj_port_mdb *mdb)
4665 {
4666 	struct mv88e6xxx_chip *chip = ds->priv;
4667 	int err;
4668 
4669 	mutex_lock(&chip->reg_lock);
4670 	err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid,
4671 					   MV88E6XXX_G1_ATU_DATA_STATE_UNUSED);
4672 	mutex_unlock(&chip->reg_lock);
4673 
4674 	return err;
4675 }
4676 
4677 static const struct dsa_switch_ops mv88e6xxx_switch_ops = {
4678 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY)
4679 	.probe			= mv88e6xxx_drv_probe,
4680 #endif
4681 	.get_tag_protocol	= mv88e6xxx_get_tag_protocol,
4682 	.setup			= mv88e6xxx_setup,
4683 	.adjust_link		= mv88e6xxx_adjust_link,
4684 	.phylink_validate	= mv88e6xxx_validate,
4685 	.phylink_mac_link_state	= mv88e6xxx_link_state,
4686 	.phylink_mac_config	= mv88e6xxx_mac_config,
4687 	.phylink_mac_link_down	= mv88e6xxx_mac_link_down,
4688 	.phylink_mac_link_up	= mv88e6xxx_mac_link_up,
4689 	.get_strings		= mv88e6xxx_get_strings,
4690 	.get_ethtool_stats	= mv88e6xxx_get_ethtool_stats,
4691 	.get_sset_count		= mv88e6xxx_get_sset_count,
4692 	.port_enable		= mv88e6xxx_port_enable,
4693 	.port_disable		= mv88e6xxx_port_disable,
4694 	.get_mac_eee		= mv88e6xxx_get_mac_eee,
4695 	.set_mac_eee		= mv88e6xxx_set_mac_eee,
4696 	.get_eeprom_len		= mv88e6xxx_get_eeprom_len,
4697 	.get_eeprom		= mv88e6xxx_get_eeprom,
4698 	.set_eeprom		= mv88e6xxx_set_eeprom,
4699 	.get_regs_len		= mv88e6xxx_get_regs_len,
4700 	.get_regs		= mv88e6xxx_get_regs,
4701 	.set_ageing_time	= mv88e6xxx_set_ageing_time,
4702 	.port_bridge_join	= mv88e6xxx_port_bridge_join,
4703 	.port_bridge_leave	= mv88e6xxx_port_bridge_leave,
4704 	.port_stp_state_set	= mv88e6xxx_port_stp_state_set,
4705 	.port_fast_age		= mv88e6xxx_port_fast_age,
4706 	.port_vlan_filtering	= mv88e6xxx_port_vlan_filtering,
4707 	.port_vlan_prepare	= mv88e6xxx_port_vlan_prepare,
4708 	.port_vlan_add		= mv88e6xxx_port_vlan_add,
4709 	.port_vlan_del		= mv88e6xxx_port_vlan_del,
4710 	.port_fdb_add           = mv88e6xxx_port_fdb_add,
4711 	.port_fdb_del           = mv88e6xxx_port_fdb_del,
4712 	.port_fdb_dump          = mv88e6xxx_port_fdb_dump,
4713 	.port_mdb_prepare       = mv88e6xxx_port_mdb_prepare,
4714 	.port_mdb_add           = mv88e6xxx_port_mdb_add,
4715 	.port_mdb_del           = mv88e6xxx_port_mdb_del,
4716 	.crosschip_bridge_join	= mv88e6xxx_crosschip_bridge_join,
4717 	.crosschip_bridge_leave	= mv88e6xxx_crosschip_bridge_leave,
4718 	.port_hwtstamp_set	= mv88e6xxx_port_hwtstamp_set,
4719 	.port_hwtstamp_get	= mv88e6xxx_port_hwtstamp_get,
4720 	.port_txtstamp		= mv88e6xxx_port_txtstamp,
4721 	.port_rxtstamp		= mv88e6xxx_port_rxtstamp,
4722 	.get_ts_info		= mv88e6xxx_get_ts_info,
4723 };
4724 
4725 static struct dsa_switch_driver mv88e6xxx_switch_drv = {
4726 	.ops			= &mv88e6xxx_switch_ops,
4727 };
4728 
4729 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip)
4730 {
4731 	struct device *dev = chip->dev;
4732 	struct dsa_switch *ds;
4733 
4734 	ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip));
4735 	if (!ds)
4736 		return -ENOMEM;
4737 
4738 	ds->priv = chip;
4739 	ds->dev = dev;
4740 	ds->ops = &mv88e6xxx_switch_ops;
4741 	ds->ageing_time_min = chip->info->age_time_coeff;
4742 	ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX;
4743 
4744 	dev_set_drvdata(dev, ds);
4745 
4746 	return dsa_register_switch(ds);
4747 }
4748 
4749 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip)
4750 {
4751 	dsa_unregister_switch(chip->ds);
4752 }
4753 
4754 static const void *pdata_device_get_match_data(struct device *dev)
4755 {
4756 	const struct of_device_id *matches = dev->driver->of_match_table;
4757 	const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data;
4758 
4759 	for (; matches->name[0] || matches->type[0] || matches->compatible[0];
4760 	     matches++) {
4761 		if (!strcmp(pdata->compatible, matches->compatible))
4762 			return matches->data;
4763 	}
4764 	return NULL;
4765 }
4766 
4767 static int mv88e6xxx_probe(struct mdio_device *mdiodev)
4768 {
4769 	struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data;
4770 	const struct mv88e6xxx_info *compat_info = NULL;
4771 	struct device *dev = &mdiodev->dev;
4772 	struct device_node *np = dev->of_node;
4773 	struct mv88e6xxx_chip *chip;
4774 	int port;
4775 	int err;
4776 
4777 	if (!np && !pdata)
4778 		return -EINVAL;
4779 
4780 	if (np)
4781 		compat_info = of_device_get_match_data(dev);
4782 
4783 	if (pdata) {
4784 		compat_info = pdata_device_get_match_data(dev);
4785 
4786 		if (!pdata->netdev)
4787 			return -EINVAL;
4788 
4789 		for (port = 0; port < DSA_MAX_PORTS; port++) {
4790 			if (!(pdata->enabled_ports & (1 << port)))
4791 				continue;
4792 			if (strcmp(pdata->cd.port_names[port], "cpu"))
4793 				continue;
4794 			pdata->cd.netdev[port] = &pdata->netdev->dev;
4795 			break;
4796 		}
4797 	}
4798 
4799 	if (!compat_info)
4800 		return -EINVAL;
4801 
4802 	chip = mv88e6xxx_alloc_chip(dev);
4803 	if (!chip) {
4804 		err = -ENOMEM;
4805 		goto out;
4806 	}
4807 
4808 	chip->info = compat_info;
4809 
4810 	err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr);
4811 	if (err)
4812 		goto out;
4813 
4814 	chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW);
4815 	if (IS_ERR(chip->reset)) {
4816 		err = PTR_ERR(chip->reset);
4817 		goto out;
4818 	}
4819 
4820 	err = mv88e6xxx_detect(chip);
4821 	if (err)
4822 		goto out;
4823 
4824 	mv88e6xxx_phy_init(chip);
4825 
4826 	if (chip->info->ops->get_eeprom) {
4827 		if (np)
4828 			of_property_read_u32(np, "eeprom-length",
4829 					     &chip->eeprom_len);
4830 		else
4831 			chip->eeprom_len = pdata->eeprom_len;
4832 	}
4833 
4834 	mutex_lock(&chip->reg_lock);
4835 	err = mv88e6xxx_switch_reset(chip);
4836 	mutex_unlock(&chip->reg_lock);
4837 	if (err)
4838 		goto out;
4839 
4840 	chip->irq = of_irq_get(np, 0);
4841 	if (chip->irq == -EPROBE_DEFER) {
4842 		err = chip->irq;
4843 		goto out;
4844 	}
4845 
4846 	/* Has to be performed before the MDIO bus is created, because
4847 	 * the PHYs will link their interrupts to these interrupt
4848 	 * controllers
4849 	 */
4850 	mutex_lock(&chip->reg_lock);
4851 	if (chip->irq > 0)
4852 		err = mv88e6xxx_g1_irq_setup(chip);
4853 	else
4854 		err = mv88e6xxx_irq_poll_setup(chip);
4855 	mutex_unlock(&chip->reg_lock);
4856 
4857 	if (err)
4858 		goto out;
4859 
4860 	if (chip->info->g2_irqs > 0) {
4861 		err = mv88e6xxx_g2_irq_setup(chip);
4862 		if (err)
4863 			goto out_g1_irq;
4864 	}
4865 
4866 	err = mv88e6xxx_g1_atu_prob_irq_setup(chip);
4867 	if (err)
4868 		goto out_g2_irq;
4869 
4870 	err = mv88e6xxx_g1_vtu_prob_irq_setup(chip);
4871 	if (err)
4872 		goto out_g1_atu_prob_irq;
4873 
4874 	err = mv88e6xxx_mdios_register(chip, np);
4875 	if (err)
4876 		goto out_g1_vtu_prob_irq;
4877 
4878 	err = mv88e6xxx_register_switch(chip);
4879 	if (err)
4880 		goto out_mdio;
4881 
4882 	return 0;
4883 
4884 out_mdio:
4885 	mv88e6xxx_mdios_unregister(chip);
4886 out_g1_vtu_prob_irq:
4887 	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4888 out_g1_atu_prob_irq:
4889 	mv88e6xxx_g1_atu_prob_irq_free(chip);
4890 out_g2_irq:
4891 	if (chip->info->g2_irqs > 0)
4892 		mv88e6xxx_g2_irq_free(chip);
4893 out_g1_irq:
4894 	if (chip->irq > 0)
4895 		mv88e6xxx_g1_irq_free(chip);
4896 	else
4897 		mv88e6xxx_irq_poll_free(chip);
4898 out:
4899 	if (pdata)
4900 		dev_put(pdata->netdev);
4901 
4902 	return err;
4903 }
4904 
4905 static void mv88e6xxx_remove(struct mdio_device *mdiodev)
4906 {
4907 	struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev);
4908 	struct mv88e6xxx_chip *chip = ds->priv;
4909 
4910 	if (chip->info->ptp_support) {
4911 		mv88e6xxx_hwtstamp_free(chip);
4912 		mv88e6xxx_ptp_free(chip);
4913 	}
4914 
4915 	mv88e6xxx_phy_destroy(chip);
4916 	mv88e6xxx_unregister_switch(chip);
4917 	mv88e6xxx_mdios_unregister(chip);
4918 
4919 	mv88e6xxx_g1_vtu_prob_irq_free(chip);
4920 	mv88e6xxx_g1_atu_prob_irq_free(chip);
4921 
4922 	if (chip->info->g2_irqs > 0)
4923 		mv88e6xxx_g2_irq_free(chip);
4924 
4925 	if (chip->irq > 0)
4926 		mv88e6xxx_g1_irq_free(chip);
4927 	else
4928 		mv88e6xxx_irq_poll_free(chip);
4929 }
4930 
4931 static const struct of_device_id mv88e6xxx_of_match[] = {
4932 	{
4933 		.compatible = "marvell,mv88e6085",
4934 		.data = &mv88e6xxx_table[MV88E6085],
4935 	},
4936 	{
4937 		.compatible = "marvell,mv88e6190",
4938 		.data = &mv88e6xxx_table[MV88E6190],
4939 	},
4940 	{ /* sentinel */ },
4941 };
4942 
4943 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match);
4944 
4945 static struct mdio_driver mv88e6xxx_driver = {
4946 	.probe	= mv88e6xxx_probe,
4947 	.remove = mv88e6xxx_remove,
4948 	.mdiodrv.driver = {
4949 		.name = "mv88e6085",
4950 		.of_match_table = mv88e6xxx_of_match,
4951 	},
4952 };
4953 
4954 static int __init mv88e6xxx_init(void)
4955 {
4956 	register_switch_driver(&mv88e6xxx_switch_drv);
4957 	return mdio_driver_register(&mv88e6xxx_driver);
4958 }
4959 module_init(mv88e6xxx_init);
4960 
4961 static void __exit mv88e6xxx_cleanup(void)
4962 {
4963 	mdio_driver_unregister(&mv88e6xxx_driver);
4964 	unregister_switch_driver(&mv88e6xxx_switch_drv);
4965 }
4966 module_exit(mv88e6xxx_cleanup);
4967 
4968 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>");
4969 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips");
4970 MODULE_LICENSE("GPL");
4971