1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/platform_data/mv88e6xxx.h> 32 #include <linux/netdevice.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/phy.h> 35 #include <linux/phylink.h> 36 #include <net/dsa.h> 37 38 #include "chip.h" 39 #include "global1.h" 40 #include "global2.h" 41 #include "hwtstamp.h" 42 #include "phy.h" 43 #include "port.h" 44 #include "ptp.h" 45 #include "serdes.h" 46 47 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 48 { 49 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 50 dev_err(chip->dev, "Switch registers lock not held!\n"); 51 dump_stack(); 52 } 53 } 54 55 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 56 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 57 * 58 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 59 * is the only device connected to the SMI master. In this mode it responds to 60 * all 32 possible SMI addresses, and thus maps directly the internal devices. 61 * 62 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 63 * multiple devices to share the SMI interface. In this mode it responds to only 64 * 2 registers, used to indirectly access the internal SMI devices. 65 */ 66 67 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 68 int addr, int reg, u16 *val) 69 { 70 if (!chip->smi_ops) 71 return -EOPNOTSUPP; 72 73 return chip->smi_ops->read(chip, addr, reg, val); 74 } 75 76 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 77 int addr, int reg, u16 val) 78 { 79 if (!chip->smi_ops) 80 return -EOPNOTSUPP; 81 82 return chip->smi_ops->write(chip, addr, reg, val); 83 } 84 85 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 86 int addr, int reg, u16 *val) 87 { 88 int ret; 89 90 ret = mdiobus_read_nested(chip->bus, addr, reg); 91 if (ret < 0) 92 return ret; 93 94 *val = ret & 0xffff; 95 96 return 0; 97 } 98 99 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 100 int addr, int reg, u16 val) 101 { 102 int ret; 103 104 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 105 if (ret < 0) 106 return ret; 107 108 return 0; 109 } 110 111 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 112 .read = mv88e6xxx_smi_single_chip_read, 113 .write = mv88e6xxx_smi_single_chip_write, 114 }; 115 116 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 117 { 118 int ret; 119 int i; 120 121 for (i = 0; i < 16; i++) { 122 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 123 if (ret < 0) 124 return ret; 125 126 if ((ret & SMI_CMD_BUSY) == 0) 127 return 0; 128 } 129 130 return -ETIMEDOUT; 131 } 132 133 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 134 int addr, int reg, u16 *val) 135 { 136 int ret; 137 138 /* Wait for the bus to become free. */ 139 ret = mv88e6xxx_smi_multi_chip_wait(chip); 140 if (ret < 0) 141 return ret; 142 143 /* Transmit the read command. */ 144 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 145 SMI_CMD_OP_22_READ | (addr << 5) | reg); 146 if (ret < 0) 147 return ret; 148 149 /* Wait for the read command to complete. */ 150 ret = mv88e6xxx_smi_multi_chip_wait(chip); 151 if (ret < 0) 152 return ret; 153 154 /* Read the data. */ 155 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 156 if (ret < 0) 157 return ret; 158 159 *val = ret & 0xffff; 160 161 return 0; 162 } 163 164 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 165 int addr, int reg, u16 val) 166 { 167 int ret; 168 169 /* Wait for the bus to become free. */ 170 ret = mv88e6xxx_smi_multi_chip_wait(chip); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the data to write. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 176 if (ret < 0) 177 return ret; 178 179 /* Transmit the write command. */ 180 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 181 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 182 if (ret < 0) 183 return ret; 184 185 /* Wait for the write command to complete. */ 186 ret = mv88e6xxx_smi_multi_chip_wait(chip); 187 if (ret < 0) 188 return ret; 189 190 return 0; 191 } 192 193 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 194 .read = mv88e6xxx_smi_multi_chip_read, 195 .write = mv88e6xxx_smi_multi_chip_write, 196 }; 197 198 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 199 { 200 int err; 201 202 assert_reg_lock(chip); 203 204 err = mv88e6xxx_smi_read(chip, addr, reg, val); 205 if (err) 206 return err; 207 208 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 209 addr, reg, *val); 210 211 return 0; 212 } 213 214 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 215 { 216 int err; 217 218 assert_reg_lock(chip); 219 220 err = mv88e6xxx_smi_write(chip, addr, reg, val); 221 if (err) 222 return err; 223 224 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 225 addr, reg, val); 226 227 return 0; 228 } 229 230 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 231 { 232 struct mv88e6xxx_mdio_bus *mdio_bus; 233 234 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 235 list); 236 if (!mdio_bus) 237 return NULL; 238 239 return mdio_bus->bus; 240 } 241 242 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 243 { 244 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 245 unsigned int n = d->hwirq; 246 247 chip->g1_irq.masked |= (1 << n); 248 } 249 250 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 251 { 252 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 253 unsigned int n = d->hwirq; 254 255 chip->g1_irq.masked &= ~(1 << n); 256 } 257 258 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 259 { 260 unsigned int nhandled = 0; 261 unsigned int sub_irq; 262 unsigned int n; 263 u16 reg; 264 u16 ctl1; 265 int err; 266 267 mutex_lock(&chip->reg_lock); 268 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 269 mutex_unlock(&chip->reg_lock); 270 271 if (err) 272 goto out; 273 274 do { 275 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 276 if (reg & (1 << n)) { 277 sub_irq = irq_find_mapping(chip->g1_irq.domain, 278 n); 279 handle_nested_irq(sub_irq); 280 ++nhandled; 281 } 282 } 283 284 mutex_lock(&chip->reg_lock); 285 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 286 if (err) 287 goto unlock; 288 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 289 unlock: 290 mutex_unlock(&chip->reg_lock); 291 if (err) 292 goto out; 293 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 294 } while (reg & ctl1); 295 296 out: 297 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 298 } 299 300 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 301 { 302 struct mv88e6xxx_chip *chip = dev_id; 303 304 return mv88e6xxx_g1_irq_thread_work(chip); 305 } 306 307 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 308 { 309 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 310 311 mutex_lock(&chip->reg_lock); 312 } 313 314 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 315 { 316 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 317 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 318 u16 reg; 319 int err; 320 321 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 322 if (err) 323 goto out; 324 325 reg &= ~mask; 326 reg |= (~chip->g1_irq.masked & mask); 327 328 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 329 if (err) 330 goto out; 331 332 out: 333 mutex_unlock(&chip->reg_lock); 334 } 335 336 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 337 .name = "mv88e6xxx-g1", 338 .irq_mask = mv88e6xxx_g1_irq_mask, 339 .irq_unmask = mv88e6xxx_g1_irq_unmask, 340 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 341 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 342 }; 343 344 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 345 unsigned int irq, 346 irq_hw_number_t hwirq) 347 { 348 struct mv88e6xxx_chip *chip = d->host_data; 349 350 irq_set_chip_data(irq, d->host_data); 351 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 352 irq_set_noprobe(irq); 353 354 return 0; 355 } 356 357 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 358 .map = mv88e6xxx_g1_irq_domain_map, 359 .xlate = irq_domain_xlate_twocell, 360 }; 361 362 /* To be called with reg_lock held */ 363 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 364 { 365 int irq, virq; 366 u16 mask; 367 368 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 369 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 370 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 371 372 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 373 virq = irq_find_mapping(chip->g1_irq.domain, irq); 374 irq_dispose_mapping(virq); 375 } 376 377 irq_domain_remove(chip->g1_irq.domain); 378 } 379 380 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 381 { 382 /* 383 * free_irq must be called without reg_lock taken because the irq 384 * handler takes this lock, too. 385 */ 386 free_irq(chip->irq, chip); 387 388 mutex_lock(&chip->reg_lock); 389 mv88e6xxx_g1_irq_free_common(chip); 390 mutex_unlock(&chip->reg_lock); 391 } 392 393 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 394 { 395 int err, irq, virq; 396 u16 reg, mask; 397 398 chip->g1_irq.nirqs = chip->info->g1_irqs; 399 chip->g1_irq.domain = irq_domain_add_simple( 400 NULL, chip->g1_irq.nirqs, 0, 401 &mv88e6xxx_g1_irq_domain_ops, chip); 402 if (!chip->g1_irq.domain) 403 return -ENOMEM; 404 405 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 406 irq_create_mapping(chip->g1_irq.domain, irq); 407 408 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 409 chip->g1_irq.masked = ~0; 410 411 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 412 if (err) 413 goto out_mapping; 414 415 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 416 417 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 418 if (err) 419 goto out_disable; 420 421 /* Reading the interrupt status clears (most of) them */ 422 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 423 if (err) 424 goto out_disable; 425 426 return 0; 427 428 out_disable: 429 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 430 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 431 432 out_mapping: 433 for (irq = 0; irq < 16; irq++) { 434 virq = irq_find_mapping(chip->g1_irq.domain, irq); 435 irq_dispose_mapping(virq); 436 } 437 438 irq_domain_remove(chip->g1_irq.domain); 439 440 return err; 441 } 442 443 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 444 { 445 static struct lock_class_key lock_key; 446 static struct lock_class_key request_key; 447 int err; 448 449 err = mv88e6xxx_g1_irq_setup_common(chip); 450 if (err) 451 return err; 452 453 /* These lock classes tells lockdep that global 1 irqs are in 454 * a different category than their parent GPIO, so it won't 455 * report false recursion. 456 */ 457 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 458 459 mutex_unlock(&chip->reg_lock); 460 err = request_threaded_irq(chip->irq, NULL, 461 mv88e6xxx_g1_irq_thread_fn, 462 IRQF_ONESHOT | IRQF_SHARED, 463 dev_name(chip->dev), chip); 464 mutex_lock(&chip->reg_lock); 465 if (err) 466 mv88e6xxx_g1_irq_free_common(chip); 467 468 return err; 469 } 470 471 static void mv88e6xxx_irq_poll(struct kthread_work *work) 472 { 473 struct mv88e6xxx_chip *chip = container_of(work, 474 struct mv88e6xxx_chip, 475 irq_poll_work.work); 476 mv88e6xxx_g1_irq_thread_work(chip); 477 478 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 479 msecs_to_jiffies(100)); 480 } 481 482 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 483 { 484 int err; 485 486 err = mv88e6xxx_g1_irq_setup_common(chip); 487 if (err) 488 return err; 489 490 kthread_init_delayed_work(&chip->irq_poll_work, 491 mv88e6xxx_irq_poll); 492 493 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 494 if (IS_ERR(chip->kworker)) 495 return PTR_ERR(chip->kworker); 496 497 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 498 msecs_to_jiffies(100)); 499 500 return 0; 501 } 502 503 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 504 { 505 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 506 kthread_destroy_worker(chip->kworker); 507 508 mutex_lock(&chip->reg_lock); 509 mv88e6xxx_g1_irq_free_common(chip); 510 mutex_unlock(&chip->reg_lock); 511 } 512 513 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 514 { 515 int i; 516 517 for (i = 0; i < 16; i++) { 518 u16 val; 519 int err; 520 521 err = mv88e6xxx_read(chip, addr, reg, &val); 522 if (err) 523 return err; 524 525 if (!(val & mask)) 526 return 0; 527 528 usleep_range(1000, 2000); 529 } 530 531 dev_err(chip->dev, "Timeout while waiting for switch\n"); 532 return -ETIMEDOUT; 533 } 534 535 /* Indirect write to single pointer-data register with an Update bit */ 536 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 537 { 538 u16 val; 539 int err; 540 541 /* Wait until the previous operation is completed */ 542 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 543 if (err) 544 return err; 545 546 /* Set the Update bit to trigger a write operation */ 547 val = BIT(15) | update; 548 549 return mv88e6xxx_write(chip, addr, reg, val); 550 } 551 552 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 553 int speed, int duplex, int pause, 554 phy_interface_t mode) 555 { 556 int err; 557 558 if (!chip->info->ops->port_set_link) 559 return 0; 560 561 /* Port's MAC control must not be changed unless the link is down */ 562 err = chip->info->ops->port_set_link(chip, port, 0); 563 if (err) 564 return err; 565 566 if (chip->info->ops->port_set_speed) { 567 err = chip->info->ops->port_set_speed(chip, port, speed); 568 if (err && err != -EOPNOTSUPP) 569 goto restore_link; 570 } 571 572 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 573 mode = chip->info->ops->port_max_speed_mode(port); 574 575 if (chip->info->ops->port_set_pause) { 576 err = chip->info->ops->port_set_pause(chip, port, pause); 577 if (err) 578 goto restore_link; 579 } 580 581 if (chip->info->ops->port_set_duplex) { 582 err = chip->info->ops->port_set_duplex(chip, port, duplex); 583 if (err && err != -EOPNOTSUPP) 584 goto restore_link; 585 } 586 587 if (chip->info->ops->port_set_rgmii_delay) { 588 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 589 if (err && err != -EOPNOTSUPP) 590 goto restore_link; 591 } 592 593 if (chip->info->ops->port_set_cmode) { 594 err = chip->info->ops->port_set_cmode(chip, port, mode); 595 if (err && err != -EOPNOTSUPP) 596 goto restore_link; 597 } 598 599 err = 0; 600 restore_link: 601 if (chip->info->ops->port_set_link(chip, port, link)) 602 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 603 604 return err; 605 } 606 607 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 608 { 609 struct mv88e6xxx_chip *chip = ds->priv; 610 611 return port < chip->info->num_internal_phys; 612 } 613 614 /* We expect the switch to perform auto negotiation if there is a real 615 * phy. However, in the case of a fixed link phy, we force the port 616 * settings from the fixed link settings. 617 */ 618 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 619 struct phy_device *phydev) 620 { 621 struct mv88e6xxx_chip *chip = ds->priv; 622 int err; 623 624 if (!phy_is_pseudo_fixed_link(phydev) && 625 mv88e6xxx_phy_is_internal(ds, port)) 626 return; 627 628 mutex_lock(&chip->reg_lock); 629 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 630 phydev->duplex, phydev->pause, 631 phydev->interface); 632 mutex_unlock(&chip->reg_lock); 633 634 if (err && err != -EOPNOTSUPP) 635 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 636 } 637 638 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 639 unsigned long *mask, 640 struct phylink_link_state *state) 641 { 642 if (!phy_interface_mode_is_8023z(state->interface)) { 643 /* 10M and 100M are only supported in non-802.3z mode */ 644 phylink_set(mask, 10baseT_Half); 645 phylink_set(mask, 10baseT_Full); 646 phylink_set(mask, 100baseT_Half); 647 phylink_set(mask, 100baseT_Full); 648 } 649 } 650 651 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 652 unsigned long *mask, 653 struct phylink_link_state *state) 654 { 655 /* FIXME: if the port is in 1000Base-X mode, then it only supports 656 * 1000M FD speeds. In this case, CMODE will indicate 5. 657 */ 658 phylink_set(mask, 1000baseT_Full); 659 phylink_set(mask, 1000baseX_Full); 660 661 mv88e6065_phylink_validate(chip, port, mask, state); 662 } 663 664 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 665 unsigned long *mask, 666 struct phylink_link_state *state) 667 { 668 if (port >= 5) 669 phylink_set(mask, 2500baseX_Full); 670 671 /* No ethtool bits for 200Mbps */ 672 phylink_set(mask, 1000baseT_Full); 673 phylink_set(mask, 1000baseX_Full); 674 675 mv88e6065_phylink_validate(chip, port, mask, state); 676 } 677 678 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 679 unsigned long *mask, 680 struct phylink_link_state *state) 681 { 682 /* No ethtool bits for 200Mbps */ 683 phylink_set(mask, 1000baseT_Full); 684 phylink_set(mask, 1000baseX_Full); 685 686 mv88e6065_phylink_validate(chip, port, mask, state); 687 } 688 689 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 690 unsigned long *mask, 691 struct phylink_link_state *state) 692 { 693 if (port >= 9) { 694 phylink_set(mask, 2500baseX_Full); 695 phylink_set(mask, 2500baseT_Full); 696 } 697 698 /* No ethtool bits for 200Mbps */ 699 phylink_set(mask, 1000baseT_Full); 700 phylink_set(mask, 1000baseX_Full); 701 702 mv88e6065_phylink_validate(chip, port, mask, state); 703 } 704 705 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 706 unsigned long *mask, 707 struct phylink_link_state *state) 708 { 709 if (port >= 9) { 710 phylink_set(mask, 10000baseT_Full); 711 phylink_set(mask, 10000baseKR_Full); 712 } 713 714 mv88e6390_phylink_validate(chip, port, mask, state); 715 } 716 717 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 718 unsigned long *supported, 719 struct phylink_link_state *state) 720 { 721 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 722 struct mv88e6xxx_chip *chip = ds->priv; 723 724 /* Allow all the expected bits */ 725 phylink_set(mask, Autoneg); 726 phylink_set(mask, Pause); 727 phylink_set_port_modes(mask); 728 729 if (chip->info->ops->phylink_validate) 730 chip->info->ops->phylink_validate(chip, port, mask, state); 731 732 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 733 bitmap_and(state->advertising, state->advertising, mask, 734 __ETHTOOL_LINK_MODE_MASK_NBITS); 735 736 /* We can only operate at 2500BaseX or 1000BaseX. If requested 737 * to advertise both, only report advertising at 2500BaseX. 738 */ 739 phylink_helper_basex_speed(state); 740 } 741 742 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 743 struct phylink_link_state *state) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 int err; 747 748 mutex_lock(&chip->reg_lock); 749 if (chip->info->ops->port_link_state) 750 err = chip->info->ops->port_link_state(chip, port, state); 751 else 752 err = -EOPNOTSUPP; 753 mutex_unlock(&chip->reg_lock); 754 755 return err; 756 } 757 758 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 759 unsigned int mode, 760 const struct phylink_link_state *state) 761 { 762 struct mv88e6xxx_chip *chip = ds->priv; 763 int speed, duplex, link, pause, err; 764 765 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 766 return; 767 768 if (mode == MLO_AN_FIXED) { 769 link = LINK_FORCED_UP; 770 speed = state->speed; 771 duplex = state->duplex; 772 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 773 link = state->link; 774 speed = state->speed; 775 duplex = state->duplex; 776 } else { 777 speed = SPEED_UNFORCED; 778 duplex = DUPLEX_UNFORCED; 779 link = LINK_UNFORCED; 780 } 781 pause = !!phylink_test(state->advertising, Pause); 782 783 mutex_lock(&chip->reg_lock); 784 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 785 state->interface); 786 mutex_unlock(&chip->reg_lock); 787 788 if (err && err != -EOPNOTSUPP) 789 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 790 } 791 792 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 793 { 794 struct mv88e6xxx_chip *chip = ds->priv; 795 int err; 796 797 mutex_lock(&chip->reg_lock); 798 err = chip->info->ops->port_set_link(chip, port, link); 799 mutex_unlock(&chip->reg_lock); 800 801 if (err) 802 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 803 } 804 805 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 806 unsigned int mode, 807 phy_interface_t interface) 808 { 809 if (mode == MLO_AN_FIXED) 810 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 811 } 812 813 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 814 unsigned int mode, phy_interface_t interface, 815 struct phy_device *phydev) 816 { 817 if (mode == MLO_AN_FIXED) 818 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 819 } 820 821 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 822 { 823 if (!chip->info->ops->stats_snapshot) 824 return -EOPNOTSUPP; 825 826 return chip->info->ops->stats_snapshot(chip, port); 827 } 828 829 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 830 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 831 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 832 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 833 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 834 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 835 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 836 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 837 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 838 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 839 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 840 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 841 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 842 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 843 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 844 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 845 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 846 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 847 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 848 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 849 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 850 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 851 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 852 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 853 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 854 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 855 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 856 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 857 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 858 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 859 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 860 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 861 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 862 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 863 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 864 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 865 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 866 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 867 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 868 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 869 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 870 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 871 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 872 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 873 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 874 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 875 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 876 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 877 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 878 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 879 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 880 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 881 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 882 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 883 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 884 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 885 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 886 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 887 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 888 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 889 }; 890 891 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 892 struct mv88e6xxx_hw_stat *s, 893 int port, u16 bank1_select, 894 u16 histogram) 895 { 896 u32 low; 897 u32 high = 0; 898 u16 reg = 0; 899 int err; 900 u64 value; 901 902 switch (s->type) { 903 case STATS_TYPE_PORT: 904 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 905 if (err) 906 return U64_MAX; 907 908 low = reg; 909 if (s->size == 4) { 910 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 911 if (err) 912 return U64_MAX; 913 high = reg; 914 } 915 break; 916 case STATS_TYPE_BANK1: 917 reg = bank1_select; 918 /* fall through */ 919 case STATS_TYPE_BANK0: 920 reg |= s->reg | histogram; 921 mv88e6xxx_g1_stats_read(chip, reg, &low); 922 if (s->size == 8) 923 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 924 break; 925 default: 926 return U64_MAX; 927 } 928 value = (((u64)high) << 32) | low; 929 return value; 930 } 931 932 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 933 uint8_t *data, int types) 934 { 935 struct mv88e6xxx_hw_stat *stat; 936 int i, j; 937 938 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 939 stat = &mv88e6xxx_hw_stats[i]; 940 if (stat->type & types) { 941 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 942 ETH_GSTRING_LEN); 943 j++; 944 } 945 } 946 947 return j; 948 } 949 950 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 951 uint8_t *data) 952 { 953 return mv88e6xxx_stats_get_strings(chip, data, 954 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 955 } 956 957 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 958 uint8_t *data) 959 { 960 return mv88e6xxx_stats_get_strings(chip, data, 961 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 962 } 963 964 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 965 "atu_member_violation", 966 "atu_miss_violation", 967 "atu_full_violation", 968 "vtu_member_violation", 969 "vtu_miss_violation", 970 }; 971 972 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 973 { 974 unsigned int i; 975 976 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 977 strlcpy(data + i * ETH_GSTRING_LEN, 978 mv88e6xxx_atu_vtu_stats_strings[i], 979 ETH_GSTRING_LEN); 980 } 981 982 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 983 u32 stringset, uint8_t *data) 984 { 985 struct mv88e6xxx_chip *chip = ds->priv; 986 int count = 0; 987 988 if (stringset != ETH_SS_STATS) 989 return; 990 991 mutex_lock(&chip->reg_lock); 992 993 if (chip->info->ops->stats_get_strings) 994 count = chip->info->ops->stats_get_strings(chip, data); 995 996 if (chip->info->ops->serdes_get_strings) { 997 data += count * ETH_GSTRING_LEN; 998 count = chip->info->ops->serdes_get_strings(chip, port, data); 999 } 1000 1001 data += count * ETH_GSTRING_LEN; 1002 mv88e6xxx_atu_vtu_get_strings(data); 1003 1004 mutex_unlock(&chip->reg_lock); 1005 } 1006 1007 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1008 int types) 1009 { 1010 struct mv88e6xxx_hw_stat *stat; 1011 int i, j; 1012 1013 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1014 stat = &mv88e6xxx_hw_stats[i]; 1015 if (stat->type & types) 1016 j++; 1017 } 1018 return j; 1019 } 1020 1021 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1022 { 1023 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1024 STATS_TYPE_PORT); 1025 } 1026 1027 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1028 { 1029 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1030 STATS_TYPE_BANK1); 1031 } 1032 1033 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1034 { 1035 struct mv88e6xxx_chip *chip = ds->priv; 1036 int serdes_count = 0; 1037 int count = 0; 1038 1039 if (sset != ETH_SS_STATS) 1040 return 0; 1041 1042 mutex_lock(&chip->reg_lock); 1043 if (chip->info->ops->stats_get_sset_count) 1044 count = chip->info->ops->stats_get_sset_count(chip); 1045 if (count < 0) 1046 goto out; 1047 1048 if (chip->info->ops->serdes_get_sset_count) 1049 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1050 port); 1051 if (serdes_count < 0) { 1052 count = serdes_count; 1053 goto out; 1054 } 1055 count += serdes_count; 1056 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1057 1058 out: 1059 mutex_unlock(&chip->reg_lock); 1060 1061 return count; 1062 } 1063 1064 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1065 uint64_t *data, int types, 1066 u16 bank1_select, u16 histogram) 1067 { 1068 struct mv88e6xxx_hw_stat *stat; 1069 int i, j; 1070 1071 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1072 stat = &mv88e6xxx_hw_stats[i]; 1073 if (stat->type & types) { 1074 mutex_lock(&chip->reg_lock); 1075 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1076 bank1_select, 1077 histogram); 1078 mutex_unlock(&chip->reg_lock); 1079 1080 j++; 1081 } 1082 } 1083 return j; 1084 } 1085 1086 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1087 uint64_t *data) 1088 { 1089 return mv88e6xxx_stats_get_stats(chip, port, data, 1090 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1091 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1092 } 1093 1094 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1095 uint64_t *data) 1096 { 1097 return mv88e6xxx_stats_get_stats(chip, port, data, 1098 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1099 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1100 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1101 } 1102 1103 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1104 uint64_t *data) 1105 { 1106 return mv88e6xxx_stats_get_stats(chip, port, data, 1107 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1108 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1109 0); 1110 } 1111 1112 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1113 uint64_t *data) 1114 { 1115 *data++ = chip->ports[port].atu_member_violation; 1116 *data++ = chip->ports[port].atu_miss_violation; 1117 *data++ = chip->ports[port].atu_full_violation; 1118 *data++ = chip->ports[port].vtu_member_violation; 1119 *data++ = chip->ports[port].vtu_miss_violation; 1120 } 1121 1122 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1123 uint64_t *data) 1124 { 1125 int count = 0; 1126 1127 if (chip->info->ops->stats_get_stats) 1128 count = chip->info->ops->stats_get_stats(chip, port, data); 1129 1130 mutex_lock(&chip->reg_lock); 1131 if (chip->info->ops->serdes_get_stats) { 1132 data += count; 1133 count = chip->info->ops->serdes_get_stats(chip, port, data); 1134 } 1135 data += count; 1136 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1137 mutex_unlock(&chip->reg_lock); 1138 } 1139 1140 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1141 uint64_t *data) 1142 { 1143 struct mv88e6xxx_chip *chip = ds->priv; 1144 int ret; 1145 1146 mutex_lock(&chip->reg_lock); 1147 1148 ret = mv88e6xxx_stats_snapshot(chip, port); 1149 mutex_unlock(&chip->reg_lock); 1150 1151 if (ret < 0) 1152 return; 1153 1154 mv88e6xxx_get_stats(chip, port, data); 1155 1156 } 1157 1158 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1159 { 1160 return 32 * sizeof(u16); 1161 } 1162 1163 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1164 struct ethtool_regs *regs, void *_p) 1165 { 1166 struct mv88e6xxx_chip *chip = ds->priv; 1167 int err; 1168 u16 reg; 1169 u16 *p = _p; 1170 int i; 1171 1172 regs->version = chip->info->prod_num; 1173 1174 memset(p, 0xff, 32 * sizeof(u16)); 1175 1176 mutex_lock(&chip->reg_lock); 1177 1178 for (i = 0; i < 32; i++) { 1179 1180 err = mv88e6xxx_port_read(chip, port, i, ®); 1181 if (!err) 1182 p[i] = reg; 1183 } 1184 1185 mutex_unlock(&chip->reg_lock); 1186 } 1187 1188 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1189 struct ethtool_eee *e) 1190 { 1191 /* Nothing to do on the port's MAC */ 1192 return 0; 1193 } 1194 1195 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1196 struct ethtool_eee *e) 1197 { 1198 /* Nothing to do on the port's MAC */ 1199 return 0; 1200 } 1201 1202 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1203 { 1204 struct dsa_switch *ds = NULL; 1205 struct net_device *br; 1206 u16 pvlan; 1207 int i; 1208 1209 if (dev < DSA_MAX_SWITCHES) 1210 ds = chip->ds->dst->ds[dev]; 1211 1212 /* Prevent frames from unknown switch or port */ 1213 if (!ds || port >= ds->num_ports) 1214 return 0; 1215 1216 /* Frames from DSA links and CPU ports can egress any local port */ 1217 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1218 return mv88e6xxx_port_mask(chip); 1219 1220 br = ds->ports[port].bridge_dev; 1221 pvlan = 0; 1222 1223 /* Frames from user ports can egress any local DSA links and CPU ports, 1224 * as well as any local member of their bridge group. 1225 */ 1226 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1227 if (dsa_is_cpu_port(chip->ds, i) || 1228 dsa_is_dsa_port(chip->ds, i) || 1229 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1230 pvlan |= BIT(i); 1231 1232 return pvlan; 1233 } 1234 1235 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1236 { 1237 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1238 1239 /* prevent frames from going back out of the port they came in on */ 1240 output_ports &= ~BIT(port); 1241 1242 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1243 } 1244 1245 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1246 u8 state) 1247 { 1248 struct mv88e6xxx_chip *chip = ds->priv; 1249 int err; 1250 1251 mutex_lock(&chip->reg_lock); 1252 err = mv88e6xxx_port_set_state(chip, port, state); 1253 mutex_unlock(&chip->reg_lock); 1254 1255 if (err) 1256 dev_err(ds->dev, "p%d: failed to update state\n", port); 1257 } 1258 1259 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1260 { 1261 int err; 1262 1263 if (chip->info->ops->ieee_pri_map) { 1264 err = chip->info->ops->ieee_pri_map(chip); 1265 if (err) 1266 return err; 1267 } 1268 1269 if (chip->info->ops->ip_pri_map) { 1270 err = chip->info->ops->ip_pri_map(chip); 1271 if (err) 1272 return err; 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1279 { 1280 int target, port; 1281 int err; 1282 1283 if (!chip->info->global2_addr) 1284 return 0; 1285 1286 /* Initialize the routing port to the 32 possible target devices */ 1287 for (target = 0; target < 32; target++) { 1288 port = 0x1f; 1289 if (target < DSA_MAX_SWITCHES) 1290 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1291 port = chip->ds->rtable[target]; 1292 1293 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1294 if (err) 1295 return err; 1296 } 1297 1298 if (chip->info->ops->set_cascade_port) { 1299 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1300 err = chip->info->ops->set_cascade_port(chip, port); 1301 if (err) 1302 return err; 1303 } 1304 1305 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1306 if (err) 1307 return err; 1308 1309 return 0; 1310 } 1311 1312 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1313 { 1314 /* Clear all trunk masks and mapping */ 1315 if (chip->info->global2_addr) 1316 return mv88e6xxx_g2_trunk_clear(chip); 1317 1318 return 0; 1319 } 1320 1321 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1322 { 1323 if (chip->info->ops->rmu_disable) 1324 return chip->info->ops->rmu_disable(chip); 1325 1326 return 0; 1327 } 1328 1329 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1330 { 1331 if (chip->info->ops->pot_clear) 1332 return chip->info->ops->pot_clear(chip); 1333 1334 return 0; 1335 } 1336 1337 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1338 { 1339 if (chip->info->ops->mgmt_rsvd2cpu) 1340 return chip->info->ops->mgmt_rsvd2cpu(chip); 1341 1342 return 0; 1343 } 1344 1345 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1346 { 1347 int err; 1348 1349 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1350 if (err) 1351 return err; 1352 1353 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1354 if (err) 1355 return err; 1356 1357 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1358 } 1359 1360 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1361 { 1362 int port; 1363 int err; 1364 1365 if (!chip->info->ops->irl_init_all) 1366 return 0; 1367 1368 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1369 /* Disable ingress rate limiting by resetting all per port 1370 * ingress rate limit resources to their initial state. 1371 */ 1372 err = chip->info->ops->irl_init_all(chip, port); 1373 if (err) 1374 return err; 1375 } 1376 1377 return 0; 1378 } 1379 1380 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1381 { 1382 if (chip->info->ops->set_switch_mac) { 1383 u8 addr[ETH_ALEN]; 1384 1385 eth_random_addr(addr); 1386 1387 return chip->info->ops->set_switch_mac(chip, addr); 1388 } 1389 1390 return 0; 1391 } 1392 1393 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1394 { 1395 u16 pvlan = 0; 1396 1397 if (!mv88e6xxx_has_pvt(chip)) 1398 return -EOPNOTSUPP; 1399 1400 /* Skip the local source device, which uses in-chip port VLAN */ 1401 if (dev != chip->ds->index) 1402 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1403 1404 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1405 } 1406 1407 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1408 { 1409 int dev, port; 1410 int err; 1411 1412 if (!mv88e6xxx_has_pvt(chip)) 1413 return 0; 1414 1415 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1416 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1417 */ 1418 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1419 if (err) 1420 return err; 1421 1422 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1423 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1424 err = mv88e6xxx_pvt_map(chip, dev, port); 1425 if (err) 1426 return err; 1427 } 1428 } 1429 1430 return 0; 1431 } 1432 1433 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1434 { 1435 struct mv88e6xxx_chip *chip = ds->priv; 1436 int err; 1437 1438 mutex_lock(&chip->reg_lock); 1439 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1440 mutex_unlock(&chip->reg_lock); 1441 1442 if (err) 1443 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1444 } 1445 1446 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1447 { 1448 if (!chip->info->max_vid) 1449 return 0; 1450 1451 return mv88e6xxx_g1_vtu_flush(chip); 1452 } 1453 1454 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1455 struct mv88e6xxx_vtu_entry *entry) 1456 { 1457 if (!chip->info->ops->vtu_getnext) 1458 return -EOPNOTSUPP; 1459 1460 return chip->info->ops->vtu_getnext(chip, entry); 1461 } 1462 1463 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1464 struct mv88e6xxx_vtu_entry *entry) 1465 { 1466 if (!chip->info->ops->vtu_loadpurge) 1467 return -EOPNOTSUPP; 1468 1469 return chip->info->ops->vtu_loadpurge(chip, entry); 1470 } 1471 1472 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1473 { 1474 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1475 struct mv88e6xxx_vtu_entry vlan = { 1476 .vid = chip->info->max_vid, 1477 }; 1478 int i, err; 1479 1480 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1481 1482 /* Set every FID bit used by the (un)bridged ports */ 1483 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1484 err = mv88e6xxx_port_get_fid(chip, i, fid); 1485 if (err) 1486 return err; 1487 1488 set_bit(*fid, fid_bitmap); 1489 } 1490 1491 /* Set every FID bit used by the VLAN entries */ 1492 do { 1493 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1494 if (err) 1495 return err; 1496 1497 if (!vlan.valid) 1498 break; 1499 1500 set_bit(vlan.fid, fid_bitmap); 1501 } while (vlan.vid < chip->info->max_vid); 1502 1503 /* The reset value 0x000 is used to indicate that multiple address 1504 * databases are not needed. Return the next positive available. 1505 */ 1506 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1507 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1508 return -ENOSPC; 1509 1510 /* Clear the database */ 1511 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1512 } 1513 1514 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1515 struct mv88e6xxx_vtu_entry *entry, bool new) 1516 { 1517 int err; 1518 1519 if (!vid) 1520 return -EINVAL; 1521 1522 entry->vid = vid - 1; 1523 entry->valid = false; 1524 1525 err = mv88e6xxx_vtu_getnext(chip, entry); 1526 if (err) 1527 return err; 1528 1529 if (entry->vid == vid && entry->valid) 1530 return 0; 1531 1532 if (new) { 1533 int i; 1534 1535 /* Initialize a fresh VLAN entry */ 1536 memset(entry, 0, sizeof(*entry)); 1537 entry->valid = true; 1538 entry->vid = vid; 1539 1540 /* Exclude all ports */ 1541 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1542 entry->member[i] = 1543 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1544 1545 return mv88e6xxx_atu_new(chip, &entry->fid); 1546 } 1547 1548 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1549 return -EOPNOTSUPP; 1550 } 1551 1552 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1553 u16 vid_begin, u16 vid_end) 1554 { 1555 struct mv88e6xxx_chip *chip = ds->priv; 1556 struct mv88e6xxx_vtu_entry vlan = { 1557 .vid = vid_begin - 1, 1558 }; 1559 int i, err; 1560 1561 /* DSA and CPU ports have to be members of multiple vlans */ 1562 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1563 return 0; 1564 1565 if (!vid_begin) 1566 return -EOPNOTSUPP; 1567 1568 mutex_lock(&chip->reg_lock); 1569 1570 do { 1571 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1572 if (err) 1573 goto unlock; 1574 1575 if (!vlan.valid) 1576 break; 1577 1578 if (vlan.vid > vid_end) 1579 break; 1580 1581 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1582 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1583 continue; 1584 1585 if (!ds->ports[i].slave) 1586 continue; 1587 1588 if (vlan.member[i] == 1589 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1590 continue; 1591 1592 if (dsa_to_port(ds, i)->bridge_dev == 1593 ds->ports[port].bridge_dev) 1594 break; /* same bridge, check next VLAN */ 1595 1596 if (!dsa_to_port(ds, i)->bridge_dev) 1597 continue; 1598 1599 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1600 port, vlan.vid, i, 1601 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1602 err = -EOPNOTSUPP; 1603 goto unlock; 1604 } 1605 } while (vlan.vid < vid_end); 1606 1607 unlock: 1608 mutex_unlock(&chip->reg_lock); 1609 1610 return err; 1611 } 1612 1613 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1614 bool vlan_filtering) 1615 { 1616 struct mv88e6xxx_chip *chip = ds->priv; 1617 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1618 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1619 int err; 1620 1621 if (!chip->info->max_vid) 1622 return -EOPNOTSUPP; 1623 1624 mutex_lock(&chip->reg_lock); 1625 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1626 mutex_unlock(&chip->reg_lock); 1627 1628 return err; 1629 } 1630 1631 static int 1632 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1633 const struct switchdev_obj_port_vlan *vlan) 1634 { 1635 struct mv88e6xxx_chip *chip = ds->priv; 1636 int err; 1637 1638 if (!chip->info->max_vid) 1639 return -EOPNOTSUPP; 1640 1641 /* If the requested port doesn't belong to the same bridge as the VLAN 1642 * members, do not support it (yet) and fallback to software VLAN. 1643 */ 1644 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1645 vlan->vid_end); 1646 if (err) 1647 return err; 1648 1649 /* We don't need any dynamic resource from the kernel (yet), 1650 * so skip the prepare phase. 1651 */ 1652 return 0; 1653 } 1654 1655 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1656 const unsigned char *addr, u16 vid, 1657 u8 state) 1658 { 1659 struct mv88e6xxx_vtu_entry vlan; 1660 struct mv88e6xxx_atu_entry entry; 1661 int err; 1662 1663 /* Null VLAN ID corresponds to the port private database */ 1664 if (vid == 0) 1665 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1666 else 1667 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1668 if (err) 1669 return err; 1670 1671 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1672 ether_addr_copy(entry.mac, addr); 1673 eth_addr_dec(entry.mac); 1674 1675 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1676 if (err) 1677 return err; 1678 1679 /* Initialize a fresh ATU entry if it isn't found */ 1680 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1681 !ether_addr_equal(entry.mac, addr)) { 1682 memset(&entry, 0, sizeof(entry)); 1683 ether_addr_copy(entry.mac, addr); 1684 } 1685 1686 /* Purge the ATU entry only if no port is using it anymore */ 1687 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1688 entry.portvec &= ~BIT(port); 1689 if (!entry.portvec) 1690 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1691 } else { 1692 entry.portvec |= BIT(port); 1693 entry.state = state; 1694 } 1695 1696 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1697 } 1698 1699 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1700 u16 vid) 1701 { 1702 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1703 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1704 1705 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1706 } 1707 1708 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1709 { 1710 int port; 1711 int err; 1712 1713 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1714 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1715 if (err) 1716 return err; 1717 } 1718 1719 return 0; 1720 } 1721 1722 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1723 u16 vid, u8 member) 1724 { 1725 struct mv88e6xxx_vtu_entry vlan; 1726 int err; 1727 1728 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1729 if (err) 1730 return err; 1731 1732 vlan.member[port] = member; 1733 1734 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1735 if (err) 1736 return err; 1737 1738 return mv88e6xxx_broadcast_setup(chip, vid); 1739 } 1740 1741 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1742 const struct switchdev_obj_port_vlan *vlan) 1743 { 1744 struct mv88e6xxx_chip *chip = ds->priv; 1745 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1746 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1747 u8 member; 1748 u16 vid; 1749 1750 if (!chip->info->max_vid) 1751 return; 1752 1753 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1754 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1755 else if (untagged) 1756 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1757 else 1758 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1759 1760 mutex_lock(&chip->reg_lock); 1761 1762 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1763 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1764 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1765 vid, untagged ? 'u' : 't'); 1766 1767 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1768 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1769 vlan->vid_end); 1770 1771 mutex_unlock(&chip->reg_lock); 1772 } 1773 1774 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1775 int port, u16 vid) 1776 { 1777 struct mv88e6xxx_vtu_entry vlan; 1778 int i, err; 1779 1780 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1781 if (err) 1782 return err; 1783 1784 /* Tell switchdev if this VLAN is handled in software */ 1785 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1786 return -EOPNOTSUPP; 1787 1788 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1789 1790 /* keep the VLAN unless all ports are excluded */ 1791 vlan.valid = false; 1792 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1793 if (vlan.member[i] != 1794 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1795 vlan.valid = true; 1796 break; 1797 } 1798 } 1799 1800 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1801 if (err) 1802 return err; 1803 1804 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1805 } 1806 1807 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1808 const struct switchdev_obj_port_vlan *vlan) 1809 { 1810 struct mv88e6xxx_chip *chip = ds->priv; 1811 u16 pvid, vid; 1812 int err = 0; 1813 1814 if (!chip->info->max_vid) 1815 return -EOPNOTSUPP; 1816 1817 mutex_lock(&chip->reg_lock); 1818 1819 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1820 if (err) 1821 goto unlock; 1822 1823 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1824 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1825 if (err) 1826 goto unlock; 1827 1828 if (vid == pvid) { 1829 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1830 if (err) 1831 goto unlock; 1832 } 1833 } 1834 1835 unlock: 1836 mutex_unlock(&chip->reg_lock); 1837 1838 return err; 1839 } 1840 1841 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1842 const unsigned char *addr, u16 vid) 1843 { 1844 struct mv88e6xxx_chip *chip = ds->priv; 1845 int err; 1846 1847 mutex_lock(&chip->reg_lock); 1848 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1849 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1850 mutex_unlock(&chip->reg_lock); 1851 1852 return err; 1853 } 1854 1855 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1856 const unsigned char *addr, u16 vid) 1857 { 1858 struct mv88e6xxx_chip *chip = ds->priv; 1859 int err; 1860 1861 mutex_lock(&chip->reg_lock); 1862 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1863 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1864 mutex_unlock(&chip->reg_lock); 1865 1866 return err; 1867 } 1868 1869 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1870 u16 fid, u16 vid, int port, 1871 dsa_fdb_dump_cb_t *cb, void *data) 1872 { 1873 struct mv88e6xxx_atu_entry addr; 1874 bool is_static; 1875 int err; 1876 1877 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1878 eth_broadcast_addr(addr.mac); 1879 1880 do { 1881 mutex_lock(&chip->reg_lock); 1882 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1883 mutex_unlock(&chip->reg_lock); 1884 if (err) 1885 return err; 1886 1887 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1888 break; 1889 1890 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1891 continue; 1892 1893 if (!is_unicast_ether_addr(addr.mac)) 1894 continue; 1895 1896 is_static = (addr.state == 1897 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1898 err = cb(addr.mac, vid, is_static, data); 1899 if (err) 1900 return err; 1901 } while (!is_broadcast_ether_addr(addr.mac)); 1902 1903 return err; 1904 } 1905 1906 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1907 dsa_fdb_dump_cb_t *cb, void *data) 1908 { 1909 struct mv88e6xxx_vtu_entry vlan = { 1910 .vid = chip->info->max_vid, 1911 }; 1912 u16 fid; 1913 int err; 1914 1915 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1916 mutex_lock(&chip->reg_lock); 1917 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1918 mutex_unlock(&chip->reg_lock); 1919 1920 if (err) 1921 return err; 1922 1923 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1924 if (err) 1925 return err; 1926 1927 /* Dump VLANs' Filtering Information Databases */ 1928 do { 1929 mutex_lock(&chip->reg_lock); 1930 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1931 mutex_unlock(&chip->reg_lock); 1932 if (err) 1933 return err; 1934 1935 if (!vlan.valid) 1936 break; 1937 1938 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1939 cb, data); 1940 if (err) 1941 return err; 1942 } while (vlan.vid < chip->info->max_vid); 1943 1944 return err; 1945 } 1946 1947 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1948 dsa_fdb_dump_cb_t *cb, void *data) 1949 { 1950 struct mv88e6xxx_chip *chip = ds->priv; 1951 1952 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1953 } 1954 1955 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1956 struct net_device *br) 1957 { 1958 struct dsa_switch *ds; 1959 int port; 1960 int dev; 1961 int err; 1962 1963 /* Remap the Port VLAN of each local bridge group member */ 1964 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1965 if (chip->ds->ports[port].bridge_dev == br) { 1966 err = mv88e6xxx_port_vlan_map(chip, port); 1967 if (err) 1968 return err; 1969 } 1970 } 1971 1972 if (!mv88e6xxx_has_pvt(chip)) 1973 return 0; 1974 1975 /* Remap the Port VLAN of each cross-chip bridge group member */ 1976 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1977 ds = chip->ds->dst->ds[dev]; 1978 if (!ds) 1979 break; 1980 1981 for (port = 0; port < ds->num_ports; ++port) { 1982 if (ds->ports[port].bridge_dev == br) { 1983 err = mv88e6xxx_pvt_map(chip, dev, port); 1984 if (err) 1985 return err; 1986 } 1987 } 1988 } 1989 1990 return 0; 1991 } 1992 1993 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1994 struct net_device *br) 1995 { 1996 struct mv88e6xxx_chip *chip = ds->priv; 1997 int err; 1998 1999 mutex_lock(&chip->reg_lock); 2000 err = mv88e6xxx_bridge_map(chip, br); 2001 mutex_unlock(&chip->reg_lock); 2002 2003 return err; 2004 } 2005 2006 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2007 struct net_device *br) 2008 { 2009 struct mv88e6xxx_chip *chip = ds->priv; 2010 2011 mutex_lock(&chip->reg_lock); 2012 if (mv88e6xxx_bridge_map(chip, br) || 2013 mv88e6xxx_port_vlan_map(chip, port)) 2014 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2015 mutex_unlock(&chip->reg_lock); 2016 } 2017 2018 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 2019 int port, struct net_device *br) 2020 { 2021 struct mv88e6xxx_chip *chip = ds->priv; 2022 int err; 2023 2024 if (!mv88e6xxx_has_pvt(chip)) 2025 return 0; 2026 2027 mutex_lock(&chip->reg_lock); 2028 err = mv88e6xxx_pvt_map(chip, dev, port); 2029 mutex_unlock(&chip->reg_lock); 2030 2031 return err; 2032 } 2033 2034 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2035 int port, struct net_device *br) 2036 { 2037 struct mv88e6xxx_chip *chip = ds->priv; 2038 2039 if (!mv88e6xxx_has_pvt(chip)) 2040 return; 2041 2042 mutex_lock(&chip->reg_lock); 2043 if (mv88e6xxx_pvt_map(chip, dev, port)) 2044 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2045 mutex_unlock(&chip->reg_lock); 2046 } 2047 2048 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2049 { 2050 if (chip->info->ops->reset) 2051 return chip->info->ops->reset(chip); 2052 2053 return 0; 2054 } 2055 2056 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2057 { 2058 struct gpio_desc *gpiod = chip->reset; 2059 2060 /* If there is a GPIO connected to the reset pin, toggle it */ 2061 if (gpiod) { 2062 gpiod_set_value_cansleep(gpiod, 1); 2063 usleep_range(10000, 20000); 2064 gpiod_set_value_cansleep(gpiod, 0); 2065 usleep_range(10000, 20000); 2066 } 2067 } 2068 2069 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2070 { 2071 int i, err; 2072 2073 /* Set all ports to the Disabled state */ 2074 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2075 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2076 if (err) 2077 return err; 2078 } 2079 2080 /* Wait for transmit queues to drain, 2081 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2082 */ 2083 usleep_range(2000, 4000); 2084 2085 return 0; 2086 } 2087 2088 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2089 { 2090 int err; 2091 2092 err = mv88e6xxx_disable_ports(chip); 2093 if (err) 2094 return err; 2095 2096 mv88e6xxx_hardware_reset(chip); 2097 2098 return mv88e6xxx_software_reset(chip); 2099 } 2100 2101 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2102 enum mv88e6xxx_frame_mode frame, 2103 enum mv88e6xxx_egress_mode egress, u16 etype) 2104 { 2105 int err; 2106 2107 if (!chip->info->ops->port_set_frame_mode) 2108 return -EOPNOTSUPP; 2109 2110 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2111 if (err) 2112 return err; 2113 2114 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2115 if (err) 2116 return err; 2117 2118 if (chip->info->ops->port_set_ether_type) 2119 return chip->info->ops->port_set_ether_type(chip, port, etype); 2120 2121 return 0; 2122 } 2123 2124 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2125 { 2126 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2127 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2128 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2129 } 2130 2131 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2132 { 2133 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2134 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2135 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2136 } 2137 2138 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2139 { 2140 return mv88e6xxx_set_port_mode(chip, port, 2141 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2142 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2143 ETH_P_EDSA); 2144 } 2145 2146 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2147 { 2148 if (dsa_is_dsa_port(chip->ds, port)) 2149 return mv88e6xxx_set_port_mode_dsa(chip, port); 2150 2151 if (dsa_is_user_port(chip->ds, port)) 2152 return mv88e6xxx_set_port_mode_normal(chip, port); 2153 2154 /* Setup CPU port mode depending on its supported tag format */ 2155 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2156 return mv88e6xxx_set_port_mode_dsa(chip, port); 2157 2158 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2159 return mv88e6xxx_set_port_mode_edsa(chip, port); 2160 2161 return -EINVAL; 2162 } 2163 2164 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2165 { 2166 bool message = dsa_is_dsa_port(chip->ds, port); 2167 2168 return mv88e6xxx_port_set_message_port(chip, port, message); 2169 } 2170 2171 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2172 { 2173 struct dsa_switch *ds = chip->ds; 2174 bool flood; 2175 2176 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2177 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2178 if (chip->info->ops->port_set_egress_floods) 2179 return chip->info->ops->port_set_egress_floods(chip, port, 2180 flood, flood); 2181 2182 return 0; 2183 } 2184 2185 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2186 bool on) 2187 { 2188 if (chip->info->ops->serdes_power) 2189 return chip->info->ops->serdes_power(chip, port, on); 2190 2191 return 0; 2192 } 2193 2194 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2195 { 2196 struct dsa_switch *ds = chip->ds; 2197 int upstream_port; 2198 int err; 2199 2200 upstream_port = dsa_upstream_port(ds, port); 2201 if (chip->info->ops->port_set_upstream_port) { 2202 err = chip->info->ops->port_set_upstream_port(chip, port, 2203 upstream_port); 2204 if (err) 2205 return err; 2206 } 2207 2208 if (port == upstream_port) { 2209 if (chip->info->ops->set_cpu_port) { 2210 err = chip->info->ops->set_cpu_port(chip, 2211 upstream_port); 2212 if (err) 2213 return err; 2214 } 2215 2216 if (chip->info->ops->set_egress_port) { 2217 err = chip->info->ops->set_egress_port(chip, 2218 upstream_port); 2219 if (err) 2220 return err; 2221 } 2222 } 2223 2224 return 0; 2225 } 2226 2227 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2228 { 2229 struct dsa_switch *ds = chip->ds; 2230 int err; 2231 u16 reg; 2232 2233 chip->ports[port].chip = chip; 2234 chip->ports[port].port = port; 2235 2236 /* MAC Forcing register: don't force link, speed, duplex or flow control 2237 * state to any particular values on physical ports, but force the CPU 2238 * port and all DSA ports to their maximum bandwidth and full duplex. 2239 */ 2240 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2241 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2242 SPEED_MAX, DUPLEX_FULL, 2243 PAUSE_OFF, 2244 PHY_INTERFACE_MODE_NA); 2245 else 2246 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2247 SPEED_UNFORCED, DUPLEX_UNFORCED, 2248 PAUSE_ON, 2249 PHY_INTERFACE_MODE_NA); 2250 if (err) 2251 return err; 2252 2253 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2254 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2255 * tunneling, determine priority by looking at 802.1p and IP 2256 * priority fields (IP prio has precedence), and set STP state 2257 * to Forwarding. 2258 * 2259 * If this is the CPU link, use DSA or EDSA tagging depending 2260 * on which tagging mode was configured. 2261 * 2262 * If this is a link to another switch, use DSA tagging mode. 2263 * 2264 * If this is the upstream port for this switch, enable 2265 * forwarding of unknown unicasts and multicasts. 2266 */ 2267 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2268 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2269 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2270 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2271 if (err) 2272 return err; 2273 2274 err = mv88e6xxx_setup_port_mode(chip, port); 2275 if (err) 2276 return err; 2277 2278 err = mv88e6xxx_setup_egress_floods(chip, port); 2279 if (err) 2280 return err; 2281 2282 /* Enable the SERDES interface for DSA and CPU ports. Normal 2283 * ports SERDES are enabled when the port is enabled, thus 2284 * saving a bit of power. 2285 */ 2286 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2287 err = mv88e6xxx_serdes_power(chip, port, true); 2288 if (err) 2289 return err; 2290 } 2291 2292 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2293 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2294 * untagged frames on this port, do a destination address lookup on all 2295 * received packets as usual, disable ARP mirroring and don't send a 2296 * copy of all transmitted/received frames on this port to the CPU. 2297 */ 2298 err = mv88e6xxx_port_set_map_da(chip, port); 2299 if (err) 2300 return err; 2301 2302 err = mv88e6xxx_setup_upstream_port(chip, port); 2303 if (err) 2304 return err; 2305 2306 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2307 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2308 if (err) 2309 return err; 2310 2311 if (chip->info->ops->port_set_jumbo_size) { 2312 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2313 if (err) 2314 return err; 2315 } 2316 2317 /* Port Association Vector: when learning source addresses 2318 * of packets, add the address to the address database using 2319 * a port bitmap that has only the bit for this port set and 2320 * the other bits clear. 2321 */ 2322 reg = 1 << port; 2323 /* Disable learning for CPU port */ 2324 if (dsa_is_cpu_port(ds, port)) 2325 reg = 0; 2326 2327 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2328 reg); 2329 if (err) 2330 return err; 2331 2332 /* Egress rate control 2: disable egress rate control. */ 2333 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2334 0x0000); 2335 if (err) 2336 return err; 2337 2338 if (chip->info->ops->port_pause_limit) { 2339 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2340 if (err) 2341 return err; 2342 } 2343 2344 if (chip->info->ops->port_disable_learn_limit) { 2345 err = chip->info->ops->port_disable_learn_limit(chip, port); 2346 if (err) 2347 return err; 2348 } 2349 2350 if (chip->info->ops->port_disable_pri_override) { 2351 err = chip->info->ops->port_disable_pri_override(chip, port); 2352 if (err) 2353 return err; 2354 } 2355 2356 if (chip->info->ops->port_tag_remap) { 2357 err = chip->info->ops->port_tag_remap(chip, port); 2358 if (err) 2359 return err; 2360 } 2361 2362 if (chip->info->ops->port_egress_rate_limiting) { 2363 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2364 if (err) 2365 return err; 2366 } 2367 2368 err = mv88e6xxx_setup_message_port(chip, port); 2369 if (err) 2370 return err; 2371 2372 /* Port based VLAN map: give each port the same default address 2373 * database, and allow bidirectional communication between the 2374 * CPU and DSA port(s), and the other ports. 2375 */ 2376 err = mv88e6xxx_port_set_fid(chip, port, 0); 2377 if (err) 2378 return err; 2379 2380 err = mv88e6xxx_port_vlan_map(chip, port); 2381 if (err) 2382 return err; 2383 2384 /* Default VLAN ID and priority: don't set a default VLAN 2385 * ID, and set the default packet priority to zero. 2386 */ 2387 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2388 } 2389 2390 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2391 struct phy_device *phydev) 2392 { 2393 struct mv88e6xxx_chip *chip = ds->priv; 2394 int err; 2395 2396 mutex_lock(&chip->reg_lock); 2397 2398 err = mv88e6xxx_serdes_power(chip, port, true); 2399 2400 if (!err && chip->info->ops->serdes_irq_setup) 2401 err = chip->info->ops->serdes_irq_setup(chip, port); 2402 2403 mutex_unlock(&chip->reg_lock); 2404 2405 return err; 2406 } 2407 2408 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2409 { 2410 struct mv88e6xxx_chip *chip = ds->priv; 2411 2412 mutex_lock(&chip->reg_lock); 2413 2414 if (chip->info->ops->serdes_irq_free) 2415 chip->info->ops->serdes_irq_free(chip, port); 2416 2417 if (mv88e6xxx_serdes_power(chip, port, false)) 2418 dev_err(chip->dev, "failed to power off SERDES\n"); 2419 2420 mutex_unlock(&chip->reg_lock); 2421 } 2422 2423 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2424 unsigned int ageing_time) 2425 { 2426 struct mv88e6xxx_chip *chip = ds->priv; 2427 int err; 2428 2429 mutex_lock(&chip->reg_lock); 2430 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2431 mutex_unlock(&chip->reg_lock); 2432 2433 return err; 2434 } 2435 2436 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2437 { 2438 int err; 2439 2440 /* Initialize the statistics unit */ 2441 if (chip->info->ops->stats_set_histogram) { 2442 err = chip->info->ops->stats_set_histogram(chip); 2443 if (err) 2444 return err; 2445 } 2446 2447 return mv88e6xxx_g1_stats_clear(chip); 2448 } 2449 2450 /* The mv88e6390 has some hidden registers used for debug and 2451 * development. The errata also makes use of them. 2452 */ 2453 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port, 2454 int reg, u16 val) 2455 { 2456 u16 ctrl; 2457 int err; 2458 2459 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT, 2460 PORT_RESERVED_1A, val); 2461 if (err) 2462 return err; 2463 2464 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE | 2465 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2466 reg; 2467 2468 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2469 PORT_RESERVED_1A, ctrl); 2470 } 2471 2472 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip) 2473 { 2474 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT, 2475 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY); 2476 } 2477 2478 2479 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port, 2480 int reg, u16 *val) 2481 { 2482 u16 ctrl; 2483 int err; 2484 2485 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ | 2486 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2487 reg; 2488 2489 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2490 PORT_RESERVED_1A, ctrl); 2491 if (err) 2492 return err; 2493 2494 err = mv88e6390_hidden_wait(chip); 2495 if (err) 2496 return err; 2497 2498 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT, 2499 PORT_RESERVED_1A, val); 2500 } 2501 2502 /* Check if the errata has already been applied. */ 2503 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2504 { 2505 int port; 2506 int err; 2507 u16 val; 2508 2509 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2510 err = mv88e6390_hidden_read(chip, port, 0, &val); 2511 if (err) { 2512 dev_err(chip->dev, 2513 "Error reading hidden register: %d\n", err); 2514 return false; 2515 } 2516 if (val != 0x01c0) 2517 return false; 2518 } 2519 2520 return true; 2521 } 2522 2523 /* The 6390 copper ports have an errata which require poking magic 2524 * values into undocumented hidden registers and then performing a 2525 * software reset. 2526 */ 2527 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2528 { 2529 int port; 2530 int err; 2531 2532 if (mv88e6390_setup_errata_applied(chip)) 2533 return 0; 2534 2535 /* Set the ports into blocking mode */ 2536 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2537 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2538 if (err) 2539 return err; 2540 } 2541 2542 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2543 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0); 2544 if (err) 2545 return err; 2546 } 2547 2548 return mv88e6xxx_software_reset(chip); 2549 } 2550 2551 static int mv88e6xxx_setup(struct dsa_switch *ds) 2552 { 2553 struct mv88e6xxx_chip *chip = ds->priv; 2554 u8 cmode; 2555 int err; 2556 int i; 2557 2558 chip->ds = ds; 2559 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2560 2561 mutex_lock(&chip->reg_lock); 2562 2563 if (chip->info->ops->setup_errata) { 2564 err = chip->info->ops->setup_errata(chip); 2565 if (err) 2566 goto unlock; 2567 } 2568 2569 /* Cache the cmode of each port. */ 2570 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2571 if (chip->info->ops->port_get_cmode) { 2572 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2573 if (err) 2574 goto unlock; 2575 2576 chip->ports[i].cmode = cmode; 2577 } 2578 } 2579 2580 /* Setup Switch Port Registers */ 2581 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2582 if (dsa_is_unused_port(ds, i)) 2583 continue; 2584 2585 err = mv88e6xxx_setup_port(chip, i); 2586 if (err) 2587 goto unlock; 2588 } 2589 2590 err = mv88e6xxx_irl_setup(chip); 2591 if (err) 2592 goto unlock; 2593 2594 err = mv88e6xxx_mac_setup(chip); 2595 if (err) 2596 goto unlock; 2597 2598 err = mv88e6xxx_phy_setup(chip); 2599 if (err) 2600 goto unlock; 2601 2602 err = mv88e6xxx_vtu_setup(chip); 2603 if (err) 2604 goto unlock; 2605 2606 err = mv88e6xxx_pvt_setup(chip); 2607 if (err) 2608 goto unlock; 2609 2610 err = mv88e6xxx_atu_setup(chip); 2611 if (err) 2612 goto unlock; 2613 2614 err = mv88e6xxx_broadcast_setup(chip, 0); 2615 if (err) 2616 goto unlock; 2617 2618 err = mv88e6xxx_pot_setup(chip); 2619 if (err) 2620 goto unlock; 2621 2622 err = mv88e6xxx_rmu_setup(chip); 2623 if (err) 2624 goto unlock; 2625 2626 err = mv88e6xxx_rsvd2cpu_setup(chip); 2627 if (err) 2628 goto unlock; 2629 2630 err = mv88e6xxx_trunk_setup(chip); 2631 if (err) 2632 goto unlock; 2633 2634 err = mv88e6xxx_devmap_setup(chip); 2635 if (err) 2636 goto unlock; 2637 2638 err = mv88e6xxx_pri_setup(chip); 2639 if (err) 2640 goto unlock; 2641 2642 /* Setup PTP Hardware Clock and timestamping */ 2643 if (chip->info->ptp_support) { 2644 err = mv88e6xxx_ptp_setup(chip); 2645 if (err) 2646 goto unlock; 2647 2648 err = mv88e6xxx_hwtstamp_setup(chip); 2649 if (err) 2650 goto unlock; 2651 } 2652 2653 err = mv88e6xxx_stats_setup(chip); 2654 if (err) 2655 goto unlock; 2656 2657 unlock: 2658 mutex_unlock(&chip->reg_lock); 2659 2660 return err; 2661 } 2662 2663 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2664 { 2665 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2666 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2667 u16 val; 2668 int err; 2669 2670 if (!chip->info->ops->phy_read) 2671 return -EOPNOTSUPP; 2672 2673 mutex_lock(&chip->reg_lock); 2674 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2675 mutex_unlock(&chip->reg_lock); 2676 2677 if (reg == MII_PHYSID2) { 2678 /* Some internal PHYs don't have a model number. */ 2679 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2680 /* Then there is the 6165 family. It gets is 2681 * PHYs correct. But it can also have two 2682 * SERDES interfaces in the PHY address 2683 * space. And these don't have a model 2684 * number. But they are not PHYs, so we don't 2685 * want to give them something a PHY driver 2686 * will recognise. 2687 * 2688 * Use the mv88e6390 family model number 2689 * instead, for anything which really could be 2690 * a PHY, 2691 */ 2692 if (!(val & 0x3f0)) 2693 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2694 } 2695 2696 return err ? err : val; 2697 } 2698 2699 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2700 { 2701 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2702 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2703 int err; 2704 2705 if (!chip->info->ops->phy_write) 2706 return -EOPNOTSUPP; 2707 2708 mutex_lock(&chip->reg_lock); 2709 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2710 mutex_unlock(&chip->reg_lock); 2711 2712 return err; 2713 } 2714 2715 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2716 struct device_node *np, 2717 bool external) 2718 { 2719 static int index; 2720 struct mv88e6xxx_mdio_bus *mdio_bus; 2721 struct mii_bus *bus; 2722 int err; 2723 2724 if (external) { 2725 mutex_lock(&chip->reg_lock); 2726 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2727 mutex_unlock(&chip->reg_lock); 2728 2729 if (err) 2730 return err; 2731 } 2732 2733 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2734 if (!bus) 2735 return -ENOMEM; 2736 2737 mdio_bus = bus->priv; 2738 mdio_bus->bus = bus; 2739 mdio_bus->chip = chip; 2740 INIT_LIST_HEAD(&mdio_bus->list); 2741 mdio_bus->external = external; 2742 2743 if (np) { 2744 bus->name = np->full_name; 2745 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2746 } else { 2747 bus->name = "mv88e6xxx SMI"; 2748 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2749 } 2750 2751 bus->read = mv88e6xxx_mdio_read; 2752 bus->write = mv88e6xxx_mdio_write; 2753 bus->parent = chip->dev; 2754 2755 if (!external) { 2756 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2757 if (err) 2758 return err; 2759 } 2760 2761 err = of_mdiobus_register(bus, np); 2762 if (err) { 2763 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2764 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2765 return err; 2766 } 2767 2768 if (external) 2769 list_add_tail(&mdio_bus->list, &chip->mdios); 2770 else 2771 list_add(&mdio_bus->list, &chip->mdios); 2772 2773 return 0; 2774 } 2775 2776 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2777 { .compatible = "marvell,mv88e6xxx-mdio-external", 2778 .data = (void *)true }, 2779 { }, 2780 }; 2781 2782 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2783 2784 { 2785 struct mv88e6xxx_mdio_bus *mdio_bus; 2786 struct mii_bus *bus; 2787 2788 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2789 bus = mdio_bus->bus; 2790 2791 if (!mdio_bus->external) 2792 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2793 2794 mdiobus_unregister(bus); 2795 } 2796 } 2797 2798 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2799 struct device_node *np) 2800 { 2801 const struct of_device_id *match; 2802 struct device_node *child; 2803 int err; 2804 2805 /* Always register one mdio bus for the internal/default mdio 2806 * bus. This maybe represented in the device tree, but is 2807 * optional. 2808 */ 2809 child = of_get_child_by_name(np, "mdio"); 2810 err = mv88e6xxx_mdio_register(chip, child, false); 2811 if (err) 2812 return err; 2813 2814 /* Walk the device tree, and see if there are any other nodes 2815 * which say they are compatible with the external mdio 2816 * bus. 2817 */ 2818 for_each_available_child_of_node(np, child) { 2819 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2820 if (match) { 2821 err = mv88e6xxx_mdio_register(chip, child, true); 2822 if (err) { 2823 mv88e6xxx_mdios_unregister(chip); 2824 return err; 2825 } 2826 } 2827 } 2828 2829 return 0; 2830 } 2831 2832 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2833 { 2834 struct mv88e6xxx_chip *chip = ds->priv; 2835 2836 return chip->eeprom_len; 2837 } 2838 2839 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2840 struct ethtool_eeprom *eeprom, u8 *data) 2841 { 2842 struct mv88e6xxx_chip *chip = ds->priv; 2843 int err; 2844 2845 if (!chip->info->ops->get_eeprom) 2846 return -EOPNOTSUPP; 2847 2848 mutex_lock(&chip->reg_lock); 2849 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2850 mutex_unlock(&chip->reg_lock); 2851 2852 if (err) 2853 return err; 2854 2855 eeprom->magic = 0xc3ec4951; 2856 2857 return 0; 2858 } 2859 2860 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2861 struct ethtool_eeprom *eeprom, u8 *data) 2862 { 2863 struct mv88e6xxx_chip *chip = ds->priv; 2864 int err; 2865 2866 if (!chip->info->ops->set_eeprom) 2867 return -EOPNOTSUPP; 2868 2869 if (eeprom->magic != 0xc3ec4951) 2870 return -EINVAL; 2871 2872 mutex_lock(&chip->reg_lock); 2873 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2874 mutex_unlock(&chip->reg_lock); 2875 2876 return err; 2877 } 2878 2879 static const struct mv88e6xxx_ops mv88e6085_ops = { 2880 /* MV88E6XXX_FAMILY_6097 */ 2881 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2882 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2883 .irl_init_all = mv88e6352_g2_irl_init_all, 2884 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2885 .phy_read = mv88e6185_phy_ppu_read, 2886 .phy_write = mv88e6185_phy_ppu_write, 2887 .port_set_link = mv88e6xxx_port_set_link, 2888 .port_set_duplex = mv88e6xxx_port_set_duplex, 2889 .port_set_speed = mv88e6185_port_set_speed, 2890 .port_tag_remap = mv88e6095_port_tag_remap, 2891 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2892 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2893 .port_set_ether_type = mv88e6351_port_set_ether_type, 2894 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2895 .port_pause_limit = mv88e6097_port_pause_limit, 2896 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2897 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2898 .port_link_state = mv88e6352_port_link_state, 2899 .port_get_cmode = mv88e6185_port_get_cmode, 2900 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2901 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2902 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2903 .stats_get_strings = mv88e6095_stats_get_strings, 2904 .stats_get_stats = mv88e6095_stats_get_stats, 2905 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2906 .set_egress_port = mv88e6095_g1_set_egress_port, 2907 .watchdog_ops = &mv88e6097_watchdog_ops, 2908 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2909 .pot_clear = mv88e6xxx_g2_pot_clear, 2910 .ppu_enable = mv88e6185_g1_ppu_enable, 2911 .ppu_disable = mv88e6185_g1_ppu_disable, 2912 .reset = mv88e6185_g1_reset, 2913 .rmu_disable = mv88e6085_g1_rmu_disable, 2914 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2915 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2916 .phylink_validate = mv88e6185_phylink_validate, 2917 }; 2918 2919 static const struct mv88e6xxx_ops mv88e6095_ops = { 2920 /* MV88E6XXX_FAMILY_6095 */ 2921 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2922 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2923 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2924 .phy_read = mv88e6185_phy_ppu_read, 2925 .phy_write = mv88e6185_phy_ppu_write, 2926 .port_set_link = mv88e6xxx_port_set_link, 2927 .port_set_duplex = mv88e6xxx_port_set_duplex, 2928 .port_set_speed = mv88e6185_port_set_speed, 2929 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2930 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2931 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2932 .port_link_state = mv88e6185_port_link_state, 2933 .port_get_cmode = mv88e6185_port_get_cmode, 2934 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2935 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2936 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2937 .stats_get_strings = mv88e6095_stats_get_strings, 2938 .stats_get_stats = mv88e6095_stats_get_stats, 2939 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2940 .ppu_enable = mv88e6185_g1_ppu_enable, 2941 .ppu_disable = mv88e6185_g1_ppu_disable, 2942 .reset = mv88e6185_g1_reset, 2943 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2944 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2945 .phylink_validate = mv88e6185_phylink_validate, 2946 }; 2947 2948 static const struct mv88e6xxx_ops mv88e6097_ops = { 2949 /* MV88E6XXX_FAMILY_6097 */ 2950 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2951 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2952 .irl_init_all = mv88e6352_g2_irl_init_all, 2953 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2954 .phy_read = mv88e6xxx_g2_smi_phy_read, 2955 .phy_write = mv88e6xxx_g2_smi_phy_write, 2956 .port_set_link = mv88e6xxx_port_set_link, 2957 .port_set_duplex = mv88e6xxx_port_set_duplex, 2958 .port_set_speed = mv88e6185_port_set_speed, 2959 .port_tag_remap = mv88e6095_port_tag_remap, 2960 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2961 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2962 .port_set_ether_type = mv88e6351_port_set_ether_type, 2963 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2964 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2965 .port_pause_limit = mv88e6097_port_pause_limit, 2966 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2967 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2968 .port_link_state = mv88e6352_port_link_state, 2969 .port_get_cmode = mv88e6185_port_get_cmode, 2970 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2971 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2972 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2973 .stats_get_strings = mv88e6095_stats_get_strings, 2974 .stats_get_stats = mv88e6095_stats_get_stats, 2975 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2976 .set_egress_port = mv88e6095_g1_set_egress_port, 2977 .watchdog_ops = &mv88e6097_watchdog_ops, 2978 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2979 .pot_clear = mv88e6xxx_g2_pot_clear, 2980 .reset = mv88e6352_g1_reset, 2981 .rmu_disable = mv88e6085_g1_rmu_disable, 2982 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2983 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2984 .phylink_validate = mv88e6185_phylink_validate, 2985 }; 2986 2987 static const struct mv88e6xxx_ops mv88e6123_ops = { 2988 /* MV88E6XXX_FAMILY_6165 */ 2989 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2990 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2991 .irl_init_all = mv88e6352_g2_irl_init_all, 2992 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2993 .phy_read = mv88e6xxx_g2_smi_phy_read, 2994 .phy_write = mv88e6xxx_g2_smi_phy_write, 2995 .port_set_link = mv88e6xxx_port_set_link, 2996 .port_set_duplex = mv88e6xxx_port_set_duplex, 2997 .port_set_speed = mv88e6185_port_set_speed, 2998 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2999 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3000 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3001 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3002 .port_link_state = mv88e6352_port_link_state, 3003 .port_get_cmode = mv88e6185_port_get_cmode, 3004 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3005 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3006 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3007 .stats_get_strings = mv88e6095_stats_get_strings, 3008 .stats_get_stats = mv88e6095_stats_get_stats, 3009 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3010 .set_egress_port = mv88e6095_g1_set_egress_port, 3011 .watchdog_ops = &mv88e6097_watchdog_ops, 3012 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3013 .pot_clear = mv88e6xxx_g2_pot_clear, 3014 .reset = mv88e6352_g1_reset, 3015 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3016 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3017 .phylink_validate = mv88e6185_phylink_validate, 3018 }; 3019 3020 static const struct mv88e6xxx_ops mv88e6131_ops = { 3021 /* MV88E6XXX_FAMILY_6185 */ 3022 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3023 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3024 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3025 .phy_read = mv88e6185_phy_ppu_read, 3026 .phy_write = mv88e6185_phy_ppu_write, 3027 .port_set_link = mv88e6xxx_port_set_link, 3028 .port_set_duplex = mv88e6xxx_port_set_duplex, 3029 .port_set_speed = mv88e6185_port_set_speed, 3030 .port_tag_remap = mv88e6095_port_tag_remap, 3031 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3032 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3033 .port_set_ether_type = mv88e6351_port_set_ether_type, 3034 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3035 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3036 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3037 .port_pause_limit = mv88e6097_port_pause_limit, 3038 .port_set_pause = mv88e6185_port_set_pause, 3039 .port_link_state = mv88e6352_port_link_state, 3040 .port_get_cmode = mv88e6185_port_get_cmode, 3041 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3042 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3043 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3044 .stats_get_strings = mv88e6095_stats_get_strings, 3045 .stats_get_stats = mv88e6095_stats_get_stats, 3046 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3047 .set_egress_port = mv88e6095_g1_set_egress_port, 3048 .watchdog_ops = &mv88e6097_watchdog_ops, 3049 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3050 .ppu_enable = mv88e6185_g1_ppu_enable, 3051 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3052 .ppu_disable = mv88e6185_g1_ppu_disable, 3053 .reset = mv88e6185_g1_reset, 3054 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3055 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3056 .phylink_validate = mv88e6185_phylink_validate, 3057 }; 3058 3059 static const struct mv88e6xxx_ops mv88e6141_ops = { 3060 /* MV88E6XXX_FAMILY_6341 */ 3061 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3062 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3063 .irl_init_all = mv88e6352_g2_irl_init_all, 3064 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3065 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3066 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3067 .phy_read = mv88e6xxx_g2_smi_phy_read, 3068 .phy_write = mv88e6xxx_g2_smi_phy_write, 3069 .port_set_link = mv88e6xxx_port_set_link, 3070 .port_set_duplex = mv88e6xxx_port_set_duplex, 3071 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3072 .port_set_speed = mv88e6341_port_set_speed, 3073 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3074 .port_tag_remap = mv88e6095_port_tag_remap, 3075 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3076 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3077 .port_set_ether_type = mv88e6351_port_set_ether_type, 3078 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3079 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3080 .port_pause_limit = mv88e6097_port_pause_limit, 3081 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3082 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3083 .port_link_state = mv88e6352_port_link_state, 3084 .port_get_cmode = mv88e6352_port_get_cmode, 3085 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3086 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3087 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3088 .stats_get_strings = mv88e6320_stats_get_strings, 3089 .stats_get_stats = mv88e6390_stats_get_stats, 3090 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3091 .set_egress_port = mv88e6390_g1_set_egress_port, 3092 .watchdog_ops = &mv88e6390_watchdog_ops, 3093 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3094 .pot_clear = mv88e6xxx_g2_pot_clear, 3095 .reset = mv88e6352_g1_reset, 3096 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3097 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3098 .serdes_power = mv88e6341_serdes_power, 3099 .gpio_ops = &mv88e6352_gpio_ops, 3100 .phylink_validate = mv88e6341_phylink_validate, 3101 }; 3102 3103 static const struct mv88e6xxx_ops mv88e6161_ops = { 3104 /* MV88E6XXX_FAMILY_6165 */ 3105 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3106 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3107 .irl_init_all = mv88e6352_g2_irl_init_all, 3108 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3109 .phy_read = mv88e6xxx_g2_smi_phy_read, 3110 .phy_write = mv88e6xxx_g2_smi_phy_write, 3111 .port_set_link = mv88e6xxx_port_set_link, 3112 .port_set_duplex = mv88e6xxx_port_set_duplex, 3113 .port_set_speed = mv88e6185_port_set_speed, 3114 .port_tag_remap = mv88e6095_port_tag_remap, 3115 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3116 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3117 .port_set_ether_type = mv88e6351_port_set_ether_type, 3118 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3119 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3120 .port_pause_limit = mv88e6097_port_pause_limit, 3121 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3122 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3123 .port_link_state = mv88e6352_port_link_state, 3124 .port_get_cmode = mv88e6185_port_get_cmode, 3125 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3126 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3127 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3128 .stats_get_strings = mv88e6095_stats_get_strings, 3129 .stats_get_stats = mv88e6095_stats_get_stats, 3130 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3131 .set_egress_port = mv88e6095_g1_set_egress_port, 3132 .watchdog_ops = &mv88e6097_watchdog_ops, 3133 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3134 .pot_clear = mv88e6xxx_g2_pot_clear, 3135 .reset = mv88e6352_g1_reset, 3136 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3137 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3138 .avb_ops = &mv88e6165_avb_ops, 3139 .ptp_ops = &mv88e6165_ptp_ops, 3140 .phylink_validate = mv88e6185_phylink_validate, 3141 }; 3142 3143 static const struct mv88e6xxx_ops mv88e6165_ops = { 3144 /* MV88E6XXX_FAMILY_6165 */ 3145 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3146 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3147 .irl_init_all = mv88e6352_g2_irl_init_all, 3148 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3149 .phy_read = mv88e6165_phy_read, 3150 .phy_write = mv88e6165_phy_write, 3151 .port_set_link = mv88e6xxx_port_set_link, 3152 .port_set_duplex = mv88e6xxx_port_set_duplex, 3153 .port_set_speed = mv88e6185_port_set_speed, 3154 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3155 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3156 .port_link_state = mv88e6352_port_link_state, 3157 .port_get_cmode = mv88e6185_port_get_cmode, 3158 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3159 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3160 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3161 .stats_get_strings = mv88e6095_stats_get_strings, 3162 .stats_get_stats = mv88e6095_stats_get_stats, 3163 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3164 .set_egress_port = mv88e6095_g1_set_egress_port, 3165 .watchdog_ops = &mv88e6097_watchdog_ops, 3166 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3167 .pot_clear = mv88e6xxx_g2_pot_clear, 3168 .reset = mv88e6352_g1_reset, 3169 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3170 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3171 .avb_ops = &mv88e6165_avb_ops, 3172 .ptp_ops = &mv88e6165_ptp_ops, 3173 .phylink_validate = mv88e6185_phylink_validate, 3174 }; 3175 3176 static const struct mv88e6xxx_ops mv88e6171_ops = { 3177 /* MV88E6XXX_FAMILY_6351 */ 3178 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3179 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3180 .irl_init_all = mv88e6352_g2_irl_init_all, 3181 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3182 .phy_read = mv88e6xxx_g2_smi_phy_read, 3183 .phy_write = mv88e6xxx_g2_smi_phy_write, 3184 .port_set_link = mv88e6xxx_port_set_link, 3185 .port_set_duplex = mv88e6xxx_port_set_duplex, 3186 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3187 .port_set_speed = mv88e6185_port_set_speed, 3188 .port_tag_remap = mv88e6095_port_tag_remap, 3189 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3190 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3191 .port_set_ether_type = mv88e6351_port_set_ether_type, 3192 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3193 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3194 .port_pause_limit = mv88e6097_port_pause_limit, 3195 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3196 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3197 .port_link_state = mv88e6352_port_link_state, 3198 .port_get_cmode = mv88e6352_port_get_cmode, 3199 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3200 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3201 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3202 .stats_get_strings = mv88e6095_stats_get_strings, 3203 .stats_get_stats = mv88e6095_stats_get_stats, 3204 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3205 .set_egress_port = mv88e6095_g1_set_egress_port, 3206 .watchdog_ops = &mv88e6097_watchdog_ops, 3207 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3208 .pot_clear = mv88e6xxx_g2_pot_clear, 3209 .reset = mv88e6352_g1_reset, 3210 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3211 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3212 .phylink_validate = mv88e6185_phylink_validate, 3213 }; 3214 3215 static const struct mv88e6xxx_ops mv88e6172_ops = { 3216 /* MV88E6XXX_FAMILY_6352 */ 3217 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3218 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3219 .irl_init_all = mv88e6352_g2_irl_init_all, 3220 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3221 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3222 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3223 .phy_read = mv88e6xxx_g2_smi_phy_read, 3224 .phy_write = mv88e6xxx_g2_smi_phy_write, 3225 .port_set_link = mv88e6xxx_port_set_link, 3226 .port_set_duplex = mv88e6xxx_port_set_duplex, 3227 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3228 .port_set_speed = mv88e6352_port_set_speed, 3229 .port_tag_remap = mv88e6095_port_tag_remap, 3230 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3231 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3232 .port_set_ether_type = mv88e6351_port_set_ether_type, 3233 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3234 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3235 .port_pause_limit = mv88e6097_port_pause_limit, 3236 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3237 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3238 .port_link_state = mv88e6352_port_link_state, 3239 .port_get_cmode = mv88e6352_port_get_cmode, 3240 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3241 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3242 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3243 .stats_get_strings = mv88e6095_stats_get_strings, 3244 .stats_get_stats = mv88e6095_stats_get_stats, 3245 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3246 .set_egress_port = mv88e6095_g1_set_egress_port, 3247 .watchdog_ops = &mv88e6097_watchdog_ops, 3248 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3249 .pot_clear = mv88e6xxx_g2_pot_clear, 3250 .reset = mv88e6352_g1_reset, 3251 .rmu_disable = mv88e6352_g1_rmu_disable, 3252 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3253 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3254 .serdes_power = mv88e6352_serdes_power, 3255 .gpio_ops = &mv88e6352_gpio_ops, 3256 .phylink_validate = mv88e6352_phylink_validate, 3257 }; 3258 3259 static const struct mv88e6xxx_ops mv88e6175_ops = { 3260 /* MV88E6XXX_FAMILY_6351 */ 3261 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3262 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3263 .irl_init_all = mv88e6352_g2_irl_init_all, 3264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3265 .phy_read = mv88e6xxx_g2_smi_phy_read, 3266 .phy_write = mv88e6xxx_g2_smi_phy_write, 3267 .port_set_link = mv88e6xxx_port_set_link, 3268 .port_set_duplex = mv88e6xxx_port_set_duplex, 3269 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3270 .port_set_speed = mv88e6185_port_set_speed, 3271 .port_tag_remap = mv88e6095_port_tag_remap, 3272 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3273 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3274 .port_set_ether_type = mv88e6351_port_set_ether_type, 3275 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3276 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3277 .port_pause_limit = mv88e6097_port_pause_limit, 3278 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3279 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3280 .port_link_state = mv88e6352_port_link_state, 3281 .port_get_cmode = mv88e6352_port_get_cmode, 3282 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3283 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3284 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3285 .stats_get_strings = mv88e6095_stats_get_strings, 3286 .stats_get_stats = mv88e6095_stats_get_stats, 3287 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3288 .set_egress_port = mv88e6095_g1_set_egress_port, 3289 .watchdog_ops = &mv88e6097_watchdog_ops, 3290 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3291 .pot_clear = mv88e6xxx_g2_pot_clear, 3292 .reset = mv88e6352_g1_reset, 3293 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3294 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3295 .phylink_validate = mv88e6185_phylink_validate, 3296 }; 3297 3298 static const struct mv88e6xxx_ops mv88e6176_ops = { 3299 /* MV88E6XXX_FAMILY_6352 */ 3300 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3301 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3302 .irl_init_all = mv88e6352_g2_irl_init_all, 3303 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3304 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3305 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3306 .phy_read = mv88e6xxx_g2_smi_phy_read, 3307 .phy_write = mv88e6xxx_g2_smi_phy_write, 3308 .port_set_link = mv88e6xxx_port_set_link, 3309 .port_set_duplex = mv88e6xxx_port_set_duplex, 3310 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3311 .port_set_speed = mv88e6352_port_set_speed, 3312 .port_tag_remap = mv88e6095_port_tag_remap, 3313 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3314 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3315 .port_set_ether_type = mv88e6351_port_set_ether_type, 3316 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3317 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3318 .port_pause_limit = mv88e6097_port_pause_limit, 3319 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3320 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3321 .port_link_state = mv88e6352_port_link_state, 3322 .port_get_cmode = mv88e6352_port_get_cmode, 3323 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3324 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3325 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3326 .stats_get_strings = mv88e6095_stats_get_strings, 3327 .stats_get_stats = mv88e6095_stats_get_stats, 3328 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3329 .set_egress_port = mv88e6095_g1_set_egress_port, 3330 .watchdog_ops = &mv88e6097_watchdog_ops, 3331 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3332 .pot_clear = mv88e6xxx_g2_pot_clear, 3333 .reset = mv88e6352_g1_reset, 3334 .rmu_disable = mv88e6352_g1_rmu_disable, 3335 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3336 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3337 .serdes_power = mv88e6352_serdes_power, 3338 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3339 .serdes_irq_free = mv88e6352_serdes_irq_free, 3340 .gpio_ops = &mv88e6352_gpio_ops, 3341 .phylink_validate = mv88e6352_phylink_validate, 3342 }; 3343 3344 static const struct mv88e6xxx_ops mv88e6185_ops = { 3345 /* MV88E6XXX_FAMILY_6185 */ 3346 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3347 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3348 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3349 .phy_read = mv88e6185_phy_ppu_read, 3350 .phy_write = mv88e6185_phy_ppu_write, 3351 .port_set_link = mv88e6xxx_port_set_link, 3352 .port_set_duplex = mv88e6xxx_port_set_duplex, 3353 .port_set_speed = mv88e6185_port_set_speed, 3354 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3355 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3356 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3357 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3358 .port_set_pause = mv88e6185_port_set_pause, 3359 .port_link_state = mv88e6185_port_link_state, 3360 .port_get_cmode = mv88e6185_port_get_cmode, 3361 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3362 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3363 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3364 .stats_get_strings = mv88e6095_stats_get_strings, 3365 .stats_get_stats = mv88e6095_stats_get_stats, 3366 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3367 .set_egress_port = mv88e6095_g1_set_egress_port, 3368 .watchdog_ops = &mv88e6097_watchdog_ops, 3369 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3370 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3371 .ppu_enable = mv88e6185_g1_ppu_enable, 3372 .ppu_disable = mv88e6185_g1_ppu_disable, 3373 .reset = mv88e6185_g1_reset, 3374 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3375 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3376 .phylink_validate = mv88e6185_phylink_validate, 3377 }; 3378 3379 static const struct mv88e6xxx_ops mv88e6190_ops = { 3380 /* MV88E6XXX_FAMILY_6390 */ 3381 .setup_errata = mv88e6390_setup_errata, 3382 .irl_init_all = mv88e6390_g2_irl_init_all, 3383 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3384 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3385 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3386 .phy_read = mv88e6xxx_g2_smi_phy_read, 3387 .phy_write = mv88e6xxx_g2_smi_phy_write, 3388 .port_set_link = mv88e6xxx_port_set_link, 3389 .port_set_duplex = mv88e6xxx_port_set_duplex, 3390 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3391 .port_set_speed = mv88e6390_port_set_speed, 3392 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3393 .port_tag_remap = mv88e6390_port_tag_remap, 3394 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3395 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3396 .port_set_ether_type = mv88e6351_port_set_ether_type, 3397 .port_pause_limit = mv88e6390_port_pause_limit, 3398 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3400 .port_link_state = mv88e6352_port_link_state, 3401 .port_get_cmode = mv88e6352_port_get_cmode, 3402 .port_set_cmode = mv88e6390_port_set_cmode, 3403 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3404 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3405 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3406 .stats_get_strings = mv88e6320_stats_get_strings, 3407 .stats_get_stats = mv88e6390_stats_get_stats, 3408 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3409 .set_egress_port = mv88e6390_g1_set_egress_port, 3410 .watchdog_ops = &mv88e6390_watchdog_ops, 3411 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3412 .pot_clear = mv88e6xxx_g2_pot_clear, 3413 .reset = mv88e6352_g1_reset, 3414 .rmu_disable = mv88e6390_g1_rmu_disable, 3415 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3416 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3417 .serdes_power = mv88e6390_serdes_power, 3418 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3419 .serdes_irq_free = mv88e6390_serdes_irq_free, 3420 .gpio_ops = &mv88e6352_gpio_ops, 3421 .phylink_validate = mv88e6390_phylink_validate, 3422 }; 3423 3424 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3425 /* MV88E6XXX_FAMILY_6390 */ 3426 .setup_errata = mv88e6390_setup_errata, 3427 .irl_init_all = mv88e6390_g2_irl_init_all, 3428 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3429 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3430 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3431 .phy_read = mv88e6xxx_g2_smi_phy_read, 3432 .phy_write = mv88e6xxx_g2_smi_phy_write, 3433 .port_set_link = mv88e6xxx_port_set_link, 3434 .port_set_duplex = mv88e6xxx_port_set_duplex, 3435 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3436 .port_set_speed = mv88e6390x_port_set_speed, 3437 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3438 .port_tag_remap = mv88e6390_port_tag_remap, 3439 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3440 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3441 .port_set_ether_type = mv88e6351_port_set_ether_type, 3442 .port_pause_limit = mv88e6390_port_pause_limit, 3443 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3444 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3445 .port_link_state = mv88e6352_port_link_state, 3446 .port_get_cmode = mv88e6352_port_get_cmode, 3447 .port_set_cmode = mv88e6390x_port_set_cmode, 3448 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3449 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3450 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3451 .stats_get_strings = mv88e6320_stats_get_strings, 3452 .stats_get_stats = mv88e6390_stats_get_stats, 3453 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3454 .set_egress_port = mv88e6390_g1_set_egress_port, 3455 .watchdog_ops = &mv88e6390_watchdog_ops, 3456 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3457 .pot_clear = mv88e6xxx_g2_pot_clear, 3458 .reset = mv88e6352_g1_reset, 3459 .rmu_disable = mv88e6390_g1_rmu_disable, 3460 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3461 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3462 .serdes_power = mv88e6390x_serdes_power, 3463 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3464 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3465 .gpio_ops = &mv88e6352_gpio_ops, 3466 .phylink_validate = mv88e6390x_phylink_validate, 3467 }; 3468 3469 static const struct mv88e6xxx_ops mv88e6191_ops = { 3470 /* MV88E6XXX_FAMILY_6390 */ 3471 .setup_errata = mv88e6390_setup_errata, 3472 .irl_init_all = mv88e6390_g2_irl_init_all, 3473 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3474 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3475 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3476 .phy_read = mv88e6xxx_g2_smi_phy_read, 3477 .phy_write = mv88e6xxx_g2_smi_phy_write, 3478 .port_set_link = mv88e6xxx_port_set_link, 3479 .port_set_duplex = mv88e6xxx_port_set_duplex, 3480 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3481 .port_set_speed = mv88e6390_port_set_speed, 3482 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3483 .port_tag_remap = mv88e6390_port_tag_remap, 3484 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3485 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3486 .port_set_ether_type = mv88e6351_port_set_ether_type, 3487 .port_pause_limit = mv88e6390_port_pause_limit, 3488 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3489 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3490 .port_link_state = mv88e6352_port_link_state, 3491 .port_get_cmode = mv88e6352_port_get_cmode, 3492 .port_set_cmode = mv88e6390_port_set_cmode, 3493 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3494 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3495 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3496 .stats_get_strings = mv88e6320_stats_get_strings, 3497 .stats_get_stats = mv88e6390_stats_get_stats, 3498 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3499 .set_egress_port = mv88e6390_g1_set_egress_port, 3500 .watchdog_ops = &mv88e6390_watchdog_ops, 3501 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3502 .pot_clear = mv88e6xxx_g2_pot_clear, 3503 .reset = mv88e6352_g1_reset, 3504 .rmu_disable = mv88e6390_g1_rmu_disable, 3505 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3506 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3507 .serdes_power = mv88e6390_serdes_power, 3508 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3509 .serdes_irq_free = mv88e6390_serdes_irq_free, 3510 .avb_ops = &mv88e6390_avb_ops, 3511 .ptp_ops = &mv88e6352_ptp_ops, 3512 .phylink_validate = mv88e6390_phylink_validate, 3513 }; 3514 3515 static const struct mv88e6xxx_ops mv88e6240_ops = { 3516 /* MV88E6XXX_FAMILY_6352 */ 3517 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3518 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3519 .irl_init_all = mv88e6352_g2_irl_init_all, 3520 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3521 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3522 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3523 .phy_read = mv88e6xxx_g2_smi_phy_read, 3524 .phy_write = mv88e6xxx_g2_smi_phy_write, 3525 .port_set_link = mv88e6xxx_port_set_link, 3526 .port_set_duplex = mv88e6xxx_port_set_duplex, 3527 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3528 .port_set_speed = mv88e6352_port_set_speed, 3529 .port_tag_remap = mv88e6095_port_tag_remap, 3530 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3531 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3532 .port_set_ether_type = mv88e6351_port_set_ether_type, 3533 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3534 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3535 .port_pause_limit = mv88e6097_port_pause_limit, 3536 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3537 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3538 .port_link_state = mv88e6352_port_link_state, 3539 .port_get_cmode = mv88e6352_port_get_cmode, 3540 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3541 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3542 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3543 .stats_get_strings = mv88e6095_stats_get_strings, 3544 .stats_get_stats = mv88e6095_stats_get_stats, 3545 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3546 .set_egress_port = mv88e6095_g1_set_egress_port, 3547 .watchdog_ops = &mv88e6097_watchdog_ops, 3548 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3549 .pot_clear = mv88e6xxx_g2_pot_clear, 3550 .reset = mv88e6352_g1_reset, 3551 .rmu_disable = mv88e6352_g1_rmu_disable, 3552 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3553 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3554 .serdes_power = mv88e6352_serdes_power, 3555 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3556 .serdes_irq_free = mv88e6352_serdes_irq_free, 3557 .gpio_ops = &mv88e6352_gpio_ops, 3558 .avb_ops = &mv88e6352_avb_ops, 3559 .ptp_ops = &mv88e6352_ptp_ops, 3560 .phylink_validate = mv88e6352_phylink_validate, 3561 }; 3562 3563 static const struct mv88e6xxx_ops mv88e6290_ops = { 3564 /* MV88E6XXX_FAMILY_6390 */ 3565 .setup_errata = mv88e6390_setup_errata, 3566 .irl_init_all = mv88e6390_g2_irl_init_all, 3567 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3568 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3569 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3570 .phy_read = mv88e6xxx_g2_smi_phy_read, 3571 .phy_write = mv88e6xxx_g2_smi_phy_write, 3572 .port_set_link = mv88e6xxx_port_set_link, 3573 .port_set_duplex = mv88e6xxx_port_set_duplex, 3574 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3575 .port_set_speed = mv88e6390_port_set_speed, 3576 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3577 .port_tag_remap = mv88e6390_port_tag_remap, 3578 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3579 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3580 .port_set_ether_type = mv88e6351_port_set_ether_type, 3581 .port_pause_limit = mv88e6390_port_pause_limit, 3582 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3583 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3584 .port_link_state = mv88e6352_port_link_state, 3585 .port_get_cmode = mv88e6352_port_get_cmode, 3586 .port_set_cmode = mv88e6390_port_set_cmode, 3587 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3588 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3589 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3590 .stats_get_strings = mv88e6320_stats_get_strings, 3591 .stats_get_stats = mv88e6390_stats_get_stats, 3592 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3593 .set_egress_port = mv88e6390_g1_set_egress_port, 3594 .watchdog_ops = &mv88e6390_watchdog_ops, 3595 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3596 .pot_clear = mv88e6xxx_g2_pot_clear, 3597 .reset = mv88e6352_g1_reset, 3598 .rmu_disable = mv88e6390_g1_rmu_disable, 3599 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3600 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3601 .serdes_power = mv88e6390_serdes_power, 3602 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3603 .serdes_irq_free = mv88e6390_serdes_irq_free, 3604 .gpio_ops = &mv88e6352_gpio_ops, 3605 .avb_ops = &mv88e6390_avb_ops, 3606 .ptp_ops = &mv88e6352_ptp_ops, 3607 .phylink_validate = mv88e6390_phylink_validate, 3608 }; 3609 3610 static const struct mv88e6xxx_ops mv88e6320_ops = { 3611 /* MV88E6XXX_FAMILY_6320 */ 3612 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3613 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3614 .irl_init_all = mv88e6352_g2_irl_init_all, 3615 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3616 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3617 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3618 .phy_read = mv88e6xxx_g2_smi_phy_read, 3619 .phy_write = mv88e6xxx_g2_smi_phy_write, 3620 .port_set_link = mv88e6xxx_port_set_link, 3621 .port_set_duplex = mv88e6xxx_port_set_duplex, 3622 .port_set_speed = mv88e6185_port_set_speed, 3623 .port_tag_remap = mv88e6095_port_tag_remap, 3624 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3625 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3626 .port_set_ether_type = mv88e6351_port_set_ether_type, 3627 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3628 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3629 .port_pause_limit = mv88e6097_port_pause_limit, 3630 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3631 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3632 .port_link_state = mv88e6352_port_link_state, 3633 .port_get_cmode = mv88e6352_port_get_cmode, 3634 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3635 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3636 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3637 .stats_get_strings = mv88e6320_stats_get_strings, 3638 .stats_get_stats = mv88e6320_stats_get_stats, 3639 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3640 .set_egress_port = mv88e6095_g1_set_egress_port, 3641 .watchdog_ops = &mv88e6390_watchdog_ops, 3642 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3643 .pot_clear = mv88e6xxx_g2_pot_clear, 3644 .reset = mv88e6352_g1_reset, 3645 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3646 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3647 .gpio_ops = &mv88e6352_gpio_ops, 3648 .avb_ops = &mv88e6352_avb_ops, 3649 .ptp_ops = &mv88e6352_ptp_ops, 3650 .phylink_validate = mv88e6185_phylink_validate, 3651 }; 3652 3653 static const struct mv88e6xxx_ops mv88e6321_ops = { 3654 /* MV88E6XXX_FAMILY_6320 */ 3655 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3656 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3657 .irl_init_all = mv88e6352_g2_irl_init_all, 3658 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3659 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3660 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3661 .phy_read = mv88e6xxx_g2_smi_phy_read, 3662 .phy_write = mv88e6xxx_g2_smi_phy_write, 3663 .port_set_link = mv88e6xxx_port_set_link, 3664 .port_set_duplex = mv88e6xxx_port_set_duplex, 3665 .port_set_speed = mv88e6185_port_set_speed, 3666 .port_tag_remap = mv88e6095_port_tag_remap, 3667 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3668 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3669 .port_set_ether_type = mv88e6351_port_set_ether_type, 3670 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3671 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3672 .port_pause_limit = mv88e6097_port_pause_limit, 3673 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3674 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3675 .port_link_state = mv88e6352_port_link_state, 3676 .port_get_cmode = mv88e6352_port_get_cmode, 3677 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3678 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3679 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3680 .stats_get_strings = mv88e6320_stats_get_strings, 3681 .stats_get_stats = mv88e6320_stats_get_stats, 3682 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3683 .set_egress_port = mv88e6095_g1_set_egress_port, 3684 .watchdog_ops = &mv88e6390_watchdog_ops, 3685 .reset = mv88e6352_g1_reset, 3686 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3687 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3688 .gpio_ops = &mv88e6352_gpio_ops, 3689 .avb_ops = &mv88e6352_avb_ops, 3690 .ptp_ops = &mv88e6352_ptp_ops, 3691 .phylink_validate = mv88e6185_phylink_validate, 3692 }; 3693 3694 static const struct mv88e6xxx_ops mv88e6341_ops = { 3695 /* MV88E6XXX_FAMILY_6341 */ 3696 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3697 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3698 .irl_init_all = mv88e6352_g2_irl_init_all, 3699 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3700 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3701 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3702 .phy_read = mv88e6xxx_g2_smi_phy_read, 3703 .phy_write = mv88e6xxx_g2_smi_phy_write, 3704 .port_set_link = mv88e6xxx_port_set_link, 3705 .port_set_duplex = mv88e6xxx_port_set_duplex, 3706 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3707 .port_set_speed = mv88e6341_port_set_speed, 3708 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3709 .port_tag_remap = mv88e6095_port_tag_remap, 3710 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3711 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3712 .port_set_ether_type = mv88e6351_port_set_ether_type, 3713 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3714 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3715 .port_pause_limit = mv88e6097_port_pause_limit, 3716 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3717 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3718 .port_link_state = mv88e6352_port_link_state, 3719 .port_get_cmode = mv88e6352_port_get_cmode, 3720 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3721 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3722 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3723 .stats_get_strings = mv88e6320_stats_get_strings, 3724 .stats_get_stats = mv88e6390_stats_get_stats, 3725 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3726 .set_egress_port = mv88e6390_g1_set_egress_port, 3727 .watchdog_ops = &mv88e6390_watchdog_ops, 3728 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3729 .pot_clear = mv88e6xxx_g2_pot_clear, 3730 .reset = mv88e6352_g1_reset, 3731 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3732 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3733 .serdes_power = mv88e6341_serdes_power, 3734 .gpio_ops = &mv88e6352_gpio_ops, 3735 .avb_ops = &mv88e6390_avb_ops, 3736 .ptp_ops = &mv88e6352_ptp_ops, 3737 .phylink_validate = mv88e6341_phylink_validate, 3738 }; 3739 3740 static const struct mv88e6xxx_ops mv88e6350_ops = { 3741 /* MV88E6XXX_FAMILY_6351 */ 3742 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3743 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3744 .irl_init_all = mv88e6352_g2_irl_init_all, 3745 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3746 .phy_read = mv88e6xxx_g2_smi_phy_read, 3747 .phy_write = mv88e6xxx_g2_smi_phy_write, 3748 .port_set_link = mv88e6xxx_port_set_link, 3749 .port_set_duplex = mv88e6xxx_port_set_duplex, 3750 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3751 .port_set_speed = mv88e6185_port_set_speed, 3752 .port_tag_remap = mv88e6095_port_tag_remap, 3753 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3754 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3755 .port_set_ether_type = mv88e6351_port_set_ether_type, 3756 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3757 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3758 .port_pause_limit = mv88e6097_port_pause_limit, 3759 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3760 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3761 .port_link_state = mv88e6352_port_link_state, 3762 .port_get_cmode = mv88e6352_port_get_cmode, 3763 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3764 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3765 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3766 .stats_get_strings = mv88e6095_stats_get_strings, 3767 .stats_get_stats = mv88e6095_stats_get_stats, 3768 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3769 .set_egress_port = mv88e6095_g1_set_egress_port, 3770 .watchdog_ops = &mv88e6097_watchdog_ops, 3771 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3772 .pot_clear = mv88e6xxx_g2_pot_clear, 3773 .reset = mv88e6352_g1_reset, 3774 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3775 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3776 .phylink_validate = mv88e6185_phylink_validate, 3777 }; 3778 3779 static const struct mv88e6xxx_ops mv88e6351_ops = { 3780 /* MV88E6XXX_FAMILY_6351 */ 3781 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3782 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3783 .irl_init_all = mv88e6352_g2_irl_init_all, 3784 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3785 .phy_read = mv88e6xxx_g2_smi_phy_read, 3786 .phy_write = mv88e6xxx_g2_smi_phy_write, 3787 .port_set_link = mv88e6xxx_port_set_link, 3788 .port_set_duplex = mv88e6xxx_port_set_duplex, 3789 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3790 .port_set_speed = mv88e6185_port_set_speed, 3791 .port_tag_remap = mv88e6095_port_tag_remap, 3792 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3793 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3794 .port_set_ether_type = mv88e6351_port_set_ether_type, 3795 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3796 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3797 .port_pause_limit = mv88e6097_port_pause_limit, 3798 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3799 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3800 .port_link_state = mv88e6352_port_link_state, 3801 .port_get_cmode = mv88e6352_port_get_cmode, 3802 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3803 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3804 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3805 .stats_get_strings = mv88e6095_stats_get_strings, 3806 .stats_get_stats = mv88e6095_stats_get_stats, 3807 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3808 .set_egress_port = mv88e6095_g1_set_egress_port, 3809 .watchdog_ops = &mv88e6097_watchdog_ops, 3810 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3811 .pot_clear = mv88e6xxx_g2_pot_clear, 3812 .reset = mv88e6352_g1_reset, 3813 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3814 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3815 .avb_ops = &mv88e6352_avb_ops, 3816 .ptp_ops = &mv88e6352_ptp_ops, 3817 .phylink_validate = mv88e6185_phylink_validate, 3818 }; 3819 3820 static const struct mv88e6xxx_ops mv88e6352_ops = { 3821 /* MV88E6XXX_FAMILY_6352 */ 3822 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3823 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3824 .irl_init_all = mv88e6352_g2_irl_init_all, 3825 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3826 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3827 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3828 .phy_read = mv88e6xxx_g2_smi_phy_read, 3829 .phy_write = mv88e6xxx_g2_smi_phy_write, 3830 .port_set_link = mv88e6xxx_port_set_link, 3831 .port_set_duplex = mv88e6xxx_port_set_duplex, 3832 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3833 .port_set_speed = mv88e6352_port_set_speed, 3834 .port_tag_remap = mv88e6095_port_tag_remap, 3835 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3836 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3837 .port_set_ether_type = mv88e6351_port_set_ether_type, 3838 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3839 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3840 .port_pause_limit = mv88e6097_port_pause_limit, 3841 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3842 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3843 .port_link_state = mv88e6352_port_link_state, 3844 .port_get_cmode = mv88e6352_port_get_cmode, 3845 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3846 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3847 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3848 .stats_get_strings = mv88e6095_stats_get_strings, 3849 .stats_get_stats = mv88e6095_stats_get_stats, 3850 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3851 .set_egress_port = mv88e6095_g1_set_egress_port, 3852 .watchdog_ops = &mv88e6097_watchdog_ops, 3853 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3854 .pot_clear = mv88e6xxx_g2_pot_clear, 3855 .reset = mv88e6352_g1_reset, 3856 .rmu_disable = mv88e6352_g1_rmu_disable, 3857 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3858 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3859 .serdes_power = mv88e6352_serdes_power, 3860 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3861 .serdes_irq_free = mv88e6352_serdes_irq_free, 3862 .gpio_ops = &mv88e6352_gpio_ops, 3863 .avb_ops = &mv88e6352_avb_ops, 3864 .ptp_ops = &mv88e6352_ptp_ops, 3865 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3866 .serdes_get_strings = mv88e6352_serdes_get_strings, 3867 .serdes_get_stats = mv88e6352_serdes_get_stats, 3868 .phylink_validate = mv88e6352_phylink_validate, 3869 }; 3870 3871 static const struct mv88e6xxx_ops mv88e6390_ops = { 3872 /* MV88E6XXX_FAMILY_6390 */ 3873 .setup_errata = mv88e6390_setup_errata, 3874 .irl_init_all = mv88e6390_g2_irl_init_all, 3875 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3876 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3877 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3878 .phy_read = mv88e6xxx_g2_smi_phy_read, 3879 .phy_write = mv88e6xxx_g2_smi_phy_write, 3880 .port_set_link = mv88e6xxx_port_set_link, 3881 .port_set_duplex = mv88e6xxx_port_set_duplex, 3882 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3883 .port_set_speed = mv88e6390_port_set_speed, 3884 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3885 .port_tag_remap = mv88e6390_port_tag_remap, 3886 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3887 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3888 .port_set_ether_type = mv88e6351_port_set_ether_type, 3889 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3890 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3891 .port_pause_limit = mv88e6390_port_pause_limit, 3892 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3893 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3894 .port_link_state = mv88e6352_port_link_state, 3895 .port_get_cmode = mv88e6352_port_get_cmode, 3896 .port_set_cmode = mv88e6390_port_set_cmode, 3897 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3898 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3899 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3900 .stats_get_strings = mv88e6320_stats_get_strings, 3901 .stats_get_stats = mv88e6390_stats_get_stats, 3902 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3903 .set_egress_port = mv88e6390_g1_set_egress_port, 3904 .watchdog_ops = &mv88e6390_watchdog_ops, 3905 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3906 .pot_clear = mv88e6xxx_g2_pot_clear, 3907 .reset = mv88e6352_g1_reset, 3908 .rmu_disable = mv88e6390_g1_rmu_disable, 3909 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3910 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3911 .serdes_power = mv88e6390_serdes_power, 3912 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3913 .serdes_irq_free = mv88e6390_serdes_irq_free, 3914 .gpio_ops = &mv88e6352_gpio_ops, 3915 .avb_ops = &mv88e6390_avb_ops, 3916 .ptp_ops = &mv88e6352_ptp_ops, 3917 .phylink_validate = mv88e6390_phylink_validate, 3918 }; 3919 3920 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3921 /* MV88E6XXX_FAMILY_6390 */ 3922 .setup_errata = mv88e6390_setup_errata, 3923 .irl_init_all = mv88e6390_g2_irl_init_all, 3924 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3925 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3926 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3927 .phy_read = mv88e6xxx_g2_smi_phy_read, 3928 .phy_write = mv88e6xxx_g2_smi_phy_write, 3929 .port_set_link = mv88e6xxx_port_set_link, 3930 .port_set_duplex = mv88e6xxx_port_set_duplex, 3931 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3932 .port_set_speed = mv88e6390x_port_set_speed, 3933 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3934 .port_tag_remap = mv88e6390_port_tag_remap, 3935 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3936 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3937 .port_set_ether_type = mv88e6351_port_set_ether_type, 3938 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3939 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3940 .port_pause_limit = mv88e6390_port_pause_limit, 3941 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3942 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3943 .port_link_state = mv88e6352_port_link_state, 3944 .port_get_cmode = mv88e6352_port_get_cmode, 3945 .port_set_cmode = mv88e6390x_port_set_cmode, 3946 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3947 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3948 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3949 .stats_get_strings = mv88e6320_stats_get_strings, 3950 .stats_get_stats = mv88e6390_stats_get_stats, 3951 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3952 .set_egress_port = mv88e6390_g1_set_egress_port, 3953 .watchdog_ops = &mv88e6390_watchdog_ops, 3954 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3955 .pot_clear = mv88e6xxx_g2_pot_clear, 3956 .reset = mv88e6352_g1_reset, 3957 .rmu_disable = mv88e6390_g1_rmu_disable, 3958 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3959 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3960 .serdes_power = mv88e6390x_serdes_power, 3961 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3962 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3963 .gpio_ops = &mv88e6352_gpio_ops, 3964 .avb_ops = &mv88e6390_avb_ops, 3965 .ptp_ops = &mv88e6352_ptp_ops, 3966 .phylink_validate = mv88e6390x_phylink_validate, 3967 }; 3968 3969 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3970 [MV88E6085] = { 3971 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3972 .family = MV88E6XXX_FAMILY_6097, 3973 .name = "Marvell 88E6085", 3974 .num_databases = 4096, 3975 .num_ports = 10, 3976 .num_internal_phys = 5, 3977 .max_vid = 4095, 3978 .port_base_addr = 0x10, 3979 .phy_base_addr = 0x0, 3980 .global1_addr = 0x1b, 3981 .global2_addr = 0x1c, 3982 .age_time_coeff = 15000, 3983 .g1_irqs = 8, 3984 .g2_irqs = 10, 3985 .atu_move_port_mask = 0xf, 3986 .pvt = true, 3987 .multi_chip = true, 3988 .tag_protocol = DSA_TAG_PROTO_DSA, 3989 .ops = &mv88e6085_ops, 3990 }, 3991 3992 [MV88E6095] = { 3993 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3994 .family = MV88E6XXX_FAMILY_6095, 3995 .name = "Marvell 88E6095/88E6095F", 3996 .num_databases = 256, 3997 .num_ports = 11, 3998 .num_internal_phys = 0, 3999 .max_vid = 4095, 4000 .port_base_addr = 0x10, 4001 .phy_base_addr = 0x0, 4002 .global1_addr = 0x1b, 4003 .global2_addr = 0x1c, 4004 .age_time_coeff = 15000, 4005 .g1_irqs = 8, 4006 .atu_move_port_mask = 0xf, 4007 .multi_chip = true, 4008 .tag_protocol = DSA_TAG_PROTO_DSA, 4009 .ops = &mv88e6095_ops, 4010 }, 4011 4012 [MV88E6097] = { 4013 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4014 .family = MV88E6XXX_FAMILY_6097, 4015 .name = "Marvell 88E6097/88E6097F", 4016 .num_databases = 4096, 4017 .num_ports = 11, 4018 .num_internal_phys = 8, 4019 .max_vid = 4095, 4020 .port_base_addr = 0x10, 4021 .phy_base_addr = 0x0, 4022 .global1_addr = 0x1b, 4023 .global2_addr = 0x1c, 4024 .age_time_coeff = 15000, 4025 .g1_irqs = 8, 4026 .g2_irqs = 10, 4027 .atu_move_port_mask = 0xf, 4028 .pvt = true, 4029 .multi_chip = true, 4030 .tag_protocol = DSA_TAG_PROTO_EDSA, 4031 .ops = &mv88e6097_ops, 4032 }, 4033 4034 [MV88E6123] = { 4035 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4036 .family = MV88E6XXX_FAMILY_6165, 4037 .name = "Marvell 88E6123", 4038 .num_databases = 4096, 4039 .num_ports = 3, 4040 .num_internal_phys = 5, 4041 .max_vid = 4095, 4042 .port_base_addr = 0x10, 4043 .phy_base_addr = 0x0, 4044 .global1_addr = 0x1b, 4045 .global2_addr = 0x1c, 4046 .age_time_coeff = 15000, 4047 .g1_irqs = 9, 4048 .g2_irqs = 10, 4049 .atu_move_port_mask = 0xf, 4050 .pvt = true, 4051 .multi_chip = true, 4052 .tag_protocol = DSA_TAG_PROTO_EDSA, 4053 .ops = &mv88e6123_ops, 4054 }, 4055 4056 [MV88E6131] = { 4057 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4058 .family = MV88E6XXX_FAMILY_6185, 4059 .name = "Marvell 88E6131", 4060 .num_databases = 256, 4061 .num_ports = 8, 4062 .num_internal_phys = 0, 4063 .max_vid = 4095, 4064 .port_base_addr = 0x10, 4065 .phy_base_addr = 0x0, 4066 .global1_addr = 0x1b, 4067 .global2_addr = 0x1c, 4068 .age_time_coeff = 15000, 4069 .g1_irqs = 9, 4070 .atu_move_port_mask = 0xf, 4071 .multi_chip = true, 4072 .tag_protocol = DSA_TAG_PROTO_DSA, 4073 .ops = &mv88e6131_ops, 4074 }, 4075 4076 [MV88E6141] = { 4077 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4078 .family = MV88E6XXX_FAMILY_6341, 4079 .name = "Marvell 88E6141", 4080 .num_databases = 4096, 4081 .num_ports = 6, 4082 .num_internal_phys = 5, 4083 .num_gpio = 11, 4084 .max_vid = 4095, 4085 .port_base_addr = 0x10, 4086 .phy_base_addr = 0x10, 4087 .global1_addr = 0x1b, 4088 .global2_addr = 0x1c, 4089 .age_time_coeff = 3750, 4090 .atu_move_port_mask = 0x1f, 4091 .g1_irqs = 9, 4092 .g2_irqs = 10, 4093 .pvt = true, 4094 .multi_chip = true, 4095 .tag_protocol = DSA_TAG_PROTO_EDSA, 4096 .ops = &mv88e6141_ops, 4097 }, 4098 4099 [MV88E6161] = { 4100 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4101 .family = MV88E6XXX_FAMILY_6165, 4102 .name = "Marvell 88E6161", 4103 .num_databases = 4096, 4104 .num_ports = 6, 4105 .num_internal_phys = 5, 4106 .max_vid = 4095, 4107 .port_base_addr = 0x10, 4108 .phy_base_addr = 0x0, 4109 .global1_addr = 0x1b, 4110 .global2_addr = 0x1c, 4111 .age_time_coeff = 15000, 4112 .g1_irqs = 9, 4113 .g2_irqs = 10, 4114 .atu_move_port_mask = 0xf, 4115 .pvt = true, 4116 .multi_chip = true, 4117 .tag_protocol = DSA_TAG_PROTO_EDSA, 4118 .ptp_support = true, 4119 .ops = &mv88e6161_ops, 4120 }, 4121 4122 [MV88E6165] = { 4123 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4124 .family = MV88E6XXX_FAMILY_6165, 4125 .name = "Marvell 88E6165", 4126 .num_databases = 4096, 4127 .num_ports = 6, 4128 .num_internal_phys = 0, 4129 .max_vid = 4095, 4130 .port_base_addr = 0x10, 4131 .phy_base_addr = 0x0, 4132 .global1_addr = 0x1b, 4133 .global2_addr = 0x1c, 4134 .age_time_coeff = 15000, 4135 .g1_irqs = 9, 4136 .g2_irqs = 10, 4137 .atu_move_port_mask = 0xf, 4138 .pvt = true, 4139 .multi_chip = true, 4140 .tag_protocol = DSA_TAG_PROTO_DSA, 4141 .ptp_support = true, 4142 .ops = &mv88e6165_ops, 4143 }, 4144 4145 [MV88E6171] = { 4146 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4147 .family = MV88E6XXX_FAMILY_6351, 4148 .name = "Marvell 88E6171", 4149 .num_databases = 4096, 4150 .num_ports = 7, 4151 .num_internal_phys = 5, 4152 .max_vid = 4095, 4153 .port_base_addr = 0x10, 4154 .phy_base_addr = 0x0, 4155 .global1_addr = 0x1b, 4156 .global2_addr = 0x1c, 4157 .age_time_coeff = 15000, 4158 .g1_irqs = 9, 4159 .g2_irqs = 10, 4160 .atu_move_port_mask = 0xf, 4161 .pvt = true, 4162 .multi_chip = true, 4163 .tag_protocol = DSA_TAG_PROTO_EDSA, 4164 .ops = &mv88e6171_ops, 4165 }, 4166 4167 [MV88E6172] = { 4168 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4169 .family = MV88E6XXX_FAMILY_6352, 4170 .name = "Marvell 88E6172", 4171 .num_databases = 4096, 4172 .num_ports = 7, 4173 .num_internal_phys = 5, 4174 .num_gpio = 15, 4175 .max_vid = 4095, 4176 .port_base_addr = 0x10, 4177 .phy_base_addr = 0x0, 4178 .global1_addr = 0x1b, 4179 .global2_addr = 0x1c, 4180 .age_time_coeff = 15000, 4181 .g1_irqs = 9, 4182 .g2_irqs = 10, 4183 .atu_move_port_mask = 0xf, 4184 .pvt = true, 4185 .multi_chip = true, 4186 .tag_protocol = DSA_TAG_PROTO_EDSA, 4187 .ops = &mv88e6172_ops, 4188 }, 4189 4190 [MV88E6175] = { 4191 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4192 .family = MV88E6XXX_FAMILY_6351, 4193 .name = "Marvell 88E6175", 4194 .num_databases = 4096, 4195 .num_ports = 7, 4196 .num_internal_phys = 5, 4197 .max_vid = 4095, 4198 .port_base_addr = 0x10, 4199 .phy_base_addr = 0x0, 4200 .global1_addr = 0x1b, 4201 .global2_addr = 0x1c, 4202 .age_time_coeff = 15000, 4203 .g1_irqs = 9, 4204 .g2_irqs = 10, 4205 .atu_move_port_mask = 0xf, 4206 .pvt = true, 4207 .multi_chip = true, 4208 .tag_protocol = DSA_TAG_PROTO_EDSA, 4209 .ops = &mv88e6175_ops, 4210 }, 4211 4212 [MV88E6176] = { 4213 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4214 .family = MV88E6XXX_FAMILY_6352, 4215 .name = "Marvell 88E6176", 4216 .num_databases = 4096, 4217 .num_ports = 7, 4218 .num_internal_phys = 5, 4219 .num_gpio = 15, 4220 .max_vid = 4095, 4221 .port_base_addr = 0x10, 4222 .phy_base_addr = 0x0, 4223 .global1_addr = 0x1b, 4224 .global2_addr = 0x1c, 4225 .age_time_coeff = 15000, 4226 .g1_irqs = 9, 4227 .g2_irqs = 10, 4228 .atu_move_port_mask = 0xf, 4229 .pvt = true, 4230 .multi_chip = true, 4231 .tag_protocol = DSA_TAG_PROTO_EDSA, 4232 .ops = &mv88e6176_ops, 4233 }, 4234 4235 [MV88E6185] = { 4236 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4237 .family = MV88E6XXX_FAMILY_6185, 4238 .name = "Marvell 88E6185", 4239 .num_databases = 256, 4240 .num_ports = 10, 4241 .num_internal_phys = 0, 4242 .max_vid = 4095, 4243 .port_base_addr = 0x10, 4244 .phy_base_addr = 0x0, 4245 .global1_addr = 0x1b, 4246 .global2_addr = 0x1c, 4247 .age_time_coeff = 15000, 4248 .g1_irqs = 8, 4249 .atu_move_port_mask = 0xf, 4250 .multi_chip = true, 4251 .tag_protocol = DSA_TAG_PROTO_EDSA, 4252 .ops = &mv88e6185_ops, 4253 }, 4254 4255 [MV88E6190] = { 4256 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4257 .family = MV88E6XXX_FAMILY_6390, 4258 .name = "Marvell 88E6190", 4259 .num_databases = 4096, 4260 .num_ports = 11, /* 10 + Z80 */ 4261 .num_internal_phys = 9, 4262 .num_gpio = 16, 4263 .max_vid = 8191, 4264 .port_base_addr = 0x0, 4265 .phy_base_addr = 0x0, 4266 .global1_addr = 0x1b, 4267 .global2_addr = 0x1c, 4268 .tag_protocol = DSA_TAG_PROTO_DSA, 4269 .age_time_coeff = 3750, 4270 .g1_irqs = 9, 4271 .g2_irqs = 14, 4272 .pvt = true, 4273 .multi_chip = true, 4274 .atu_move_port_mask = 0x1f, 4275 .ops = &mv88e6190_ops, 4276 }, 4277 4278 [MV88E6190X] = { 4279 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4280 .family = MV88E6XXX_FAMILY_6390, 4281 .name = "Marvell 88E6190X", 4282 .num_databases = 4096, 4283 .num_ports = 11, /* 10 + Z80 */ 4284 .num_internal_phys = 9, 4285 .num_gpio = 16, 4286 .max_vid = 8191, 4287 .port_base_addr = 0x0, 4288 .phy_base_addr = 0x0, 4289 .global1_addr = 0x1b, 4290 .global2_addr = 0x1c, 4291 .age_time_coeff = 3750, 4292 .g1_irqs = 9, 4293 .g2_irqs = 14, 4294 .atu_move_port_mask = 0x1f, 4295 .pvt = true, 4296 .multi_chip = true, 4297 .tag_protocol = DSA_TAG_PROTO_DSA, 4298 .ops = &mv88e6190x_ops, 4299 }, 4300 4301 [MV88E6191] = { 4302 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4303 .family = MV88E6XXX_FAMILY_6390, 4304 .name = "Marvell 88E6191", 4305 .num_databases = 4096, 4306 .num_ports = 11, /* 10 + Z80 */ 4307 .num_internal_phys = 9, 4308 .max_vid = 8191, 4309 .port_base_addr = 0x0, 4310 .phy_base_addr = 0x0, 4311 .global1_addr = 0x1b, 4312 .global2_addr = 0x1c, 4313 .age_time_coeff = 3750, 4314 .g1_irqs = 9, 4315 .g2_irqs = 14, 4316 .atu_move_port_mask = 0x1f, 4317 .pvt = true, 4318 .multi_chip = true, 4319 .tag_protocol = DSA_TAG_PROTO_DSA, 4320 .ptp_support = true, 4321 .ops = &mv88e6191_ops, 4322 }, 4323 4324 [MV88E6240] = { 4325 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4326 .family = MV88E6XXX_FAMILY_6352, 4327 .name = "Marvell 88E6240", 4328 .num_databases = 4096, 4329 .num_ports = 7, 4330 .num_internal_phys = 5, 4331 .num_gpio = 15, 4332 .max_vid = 4095, 4333 .port_base_addr = 0x10, 4334 .phy_base_addr = 0x0, 4335 .global1_addr = 0x1b, 4336 .global2_addr = 0x1c, 4337 .age_time_coeff = 15000, 4338 .g1_irqs = 9, 4339 .g2_irqs = 10, 4340 .atu_move_port_mask = 0xf, 4341 .pvt = true, 4342 .multi_chip = true, 4343 .tag_protocol = DSA_TAG_PROTO_EDSA, 4344 .ptp_support = true, 4345 .ops = &mv88e6240_ops, 4346 }, 4347 4348 [MV88E6290] = { 4349 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4350 .family = MV88E6XXX_FAMILY_6390, 4351 .name = "Marvell 88E6290", 4352 .num_databases = 4096, 4353 .num_ports = 11, /* 10 + Z80 */ 4354 .num_internal_phys = 9, 4355 .num_gpio = 16, 4356 .max_vid = 8191, 4357 .port_base_addr = 0x0, 4358 .phy_base_addr = 0x0, 4359 .global1_addr = 0x1b, 4360 .global2_addr = 0x1c, 4361 .age_time_coeff = 3750, 4362 .g1_irqs = 9, 4363 .g2_irqs = 14, 4364 .atu_move_port_mask = 0x1f, 4365 .pvt = true, 4366 .multi_chip = true, 4367 .tag_protocol = DSA_TAG_PROTO_DSA, 4368 .ptp_support = true, 4369 .ops = &mv88e6290_ops, 4370 }, 4371 4372 [MV88E6320] = { 4373 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4374 .family = MV88E6XXX_FAMILY_6320, 4375 .name = "Marvell 88E6320", 4376 .num_databases = 4096, 4377 .num_ports = 7, 4378 .num_internal_phys = 5, 4379 .num_gpio = 15, 4380 .max_vid = 4095, 4381 .port_base_addr = 0x10, 4382 .phy_base_addr = 0x0, 4383 .global1_addr = 0x1b, 4384 .global2_addr = 0x1c, 4385 .age_time_coeff = 15000, 4386 .g1_irqs = 8, 4387 .g2_irqs = 10, 4388 .atu_move_port_mask = 0xf, 4389 .pvt = true, 4390 .multi_chip = true, 4391 .tag_protocol = DSA_TAG_PROTO_EDSA, 4392 .ptp_support = true, 4393 .ops = &mv88e6320_ops, 4394 }, 4395 4396 [MV88E6321] = { 4397 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4398 .family = MV88E6XXX_FAMILY_6320, 4399 .name = "Marvell 88E6321", 4400 .num_databases = 4096, 4401 .num_ports = 7, 4402 .num_internal_phys = 5, 4403 .num_gpio = 15, 4404 .max_vid = 4095, 4405 .port_base_addr = 0x10, 4406 .phy_base_addr = 0x0, 4407 .global1_addr = 0x1b, 4408 .global2_addr = 0x1c, 4409 .age_time_coeff = 15000, 4410 .g1_irqs = 8, 4411 .g2_irqs = 10, 4412 .atu_move_port_mask = 0xf, 4413 .multi_chip = true, 4414 .tag_protocol = DSA_TAG_PROTO_EDSA, 4415 .ptp_support = true, 4416 .ops = &mv88e6321_ops, 4417 }, 4418 4419 [MV88E6341] = { 4420 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4421 .family = MV88E6XXX_FAMILY_6341, 4422 .name = "Marvell 88E6341", 4423 .num_databases = 4096, 4424 .num_internal_phys = 5, 4425 .num_ports = 6, 4426 .num_gpio = 11, 4427 .max_vid = 4095, 4428 .port_base_addr = 0x10, 4429 .phy_base_addr = 0x10, 4430 .global1_addr = 0x1b, 4431 .global2_addr = 0x1c, 4432 .age_time_coeff = 3750, 4433 .atu_move_port_mask = 0x1f, 4434 .g1_irqs = 9, 4435 .g2_irqs = 10, 4436 .pvt = true, 4437 .multi_chip = true, 4438 .tag_protocol = DSA_TAG_PROTO_EDSA, 4439 .ptp_support = true, 4440 .ops = &mv88e6341_ops, 4441 }, 4442 4443 [MV88E6350] = { 4444 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4445 .family = MV88E6XXX_FAMILY_6351, 4446 .name = "Marvell 88E6350", 4447 .num_databases = 4096, 4448 .num_ports = 7, 4449 .num_internal_phys = 5, 4450 .max_vid = 4095, 4451 .port_base_addr = 0x10, 4452 .phy_base_addr = 0x0, 4453 .global1_addr = 0x1b, 4454 .global2_addr = 0x1c, 4455 .age_time_coeff = 15000, 4456 .g1_irqs = 9, 4457 .g2_irqs = 10, 4458 .atu_move_port_mask = 0xf, 4459 .pvt = true, 4460 .multi_chip = true, 4461 .tag_protocol = DSA_TAG_PROTO_EDSA, 4462 .ops = &mv88e6350_ops, 4463 }, 4464 4465 [MV88E6351] = { 4466 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4467 .family = MV88E6XXX_FAMILY_6351, 4468 .name = "Marvell 88E6351", 4469 .num_databases = 4096, 4470 .num_ports = 7, 4471 .num_internal_phys = 5, 4472 .max_vid = 4095, 4473 .port_base_addr = 0x10, 4474 .phy_base_addr = 0x0, 4475 .global1_addr = 0x1b, 4476 .global2_addr = 0x1c, 4477 .age_time_coeff = 15000, 4478 .g1_irqs = 9, 4479 .g2_irqs = 10, 4480 .atu_move_port_mask = 0xf, 4481 .pvt = true, 4482 .multi_chip = true, 4483 .tag_protocol = DSA_TAG_PROTO_EDSA, 4484 .ops = &mv88e6351_ops, 4485 }, 4486 4487 [MV88E6352] = { 4488 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4489 .family = MV88E6XXX_FAMILY_6352, 4490 .name = "Marvell 88E6352", 4491 .num_databases = 4096, 4492 .num_ports = 7, 4493 .num_internal_phys = 5, 4494 .num_gpio = 15, 4495 .max_vid = 4095, 4496 .port_base_addr = 0x10, 4497 .phy_base_addr = 0x0, 4498 .global1_addr = 0x1b, 4499 .global2_addr = 0x1c, 4500 .age_time_coeff = 15000, 4501 .g1_irqs = 9, 4502 .g2_irqs = 10, 4503 .atu_move_port_mask = 0xf, 4504 .pvt = true, 4505 .multi_chip = true, 4506 .tag_protocol = DSA_TAG_PROTO_EDSA, 4507 .ptp_support = true, 4508 .ops = &mv88e6352_ops, 4509 }, 4510 [MV88E6390] = { 4511 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4512 .family = MV88E6XXX_FAMILY_6390, 4513 .name = "Marvell 88E6390", 4514 .num_databases = 4096, 4515 .num_ports = 11, /* 10 + Z80 */ 4516 .num_internal_phys = 9, 4517 .num_gpio = 16, 4518 .max_vid = 8191, 4519 .port_base_addr = 0x0, 4520 .phy_base_addr = 0x0, 4521 .global1_addr = 0x1b, 4522 .global2_addr = 0x1c, 4523 .age_time_coeff = 3750, 4524 .g1_irqs = 9, 4525 .g2_irqs = 14, 4526 .atu_move_port_mask = 0x1f, 4527 .pvt = true, 4528 .multi_chip = true, 4529 .tag_protocol = DSA_TAG_PROTO_DSA, 4530 .ptp_support = true, 4531 .ops = &mv88e6390_ops, 4532 }, 4533 [MV88E6390X] = { 4534 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4535 .family = MV88E6XXX_FAMILY_6390, 4536 .name = "Marvell 88E6390X", 4537 .num_databases = 4096, 4538 .num_ports = 11, /* 10 + Z80 */ 4539 .num_internal_phys = 9, 4540 .num_gpio = 16, 4541 .max_vid = 8191, 4542 .port_base_addr = 0x0, 4543 .phy_base_addr = 0x0, 4544 .global1_addr = 0x1b, 4545 .global2_addr = 0x1c, 4546 .age_time_coeff = 3750, 4547 .g1_irqs = 9, 4548 .g2_irqs = 14, 4549 .atu_move_port_mask = 0x1f, 4550 .pvt = true, 4551 .multi_chip = true, 4552 .tag_protocol = DSA_TAG_PROTO_DSA, 4553 .ptp_support = true, 4554 .ops = &mv88e6390x_ops, 4555 }, 4556 }; 4557 4558 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4559 { 4560 int i; 4561 4562 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4563 if (mv88e6xxx_table[i].prod_num == prod_num) 4564 return &mv88e6xxx_table[i]; 4565 4566 return NULL; 4567 } 4568 4569 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4570 { 4571 const struct mv88e6xxx_info *info; 4572 unsigned int prod_num, rev; 4573 u16 id; 4574 int err; 4575 4576 mutex_lock(&chip->reg_lock); 4577 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4578 mutex_unlock(&chip->reg_lock); 4579 if (err) 4580 return err; 4581 4582 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4583 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4584 4585 info = mv88e6xxx_lookup_info(prod_num); 4586 if (!info) 4587 return -ENODEV; 4588 4589 /* Update the compatible info with the probed one */ 4590 chip->info = info; 4591 4592 err = mv88e6xxx_g2_require(chip); 4593 if (err) 4594 return err; 4595 4596 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4597 chip->info->prod_num, chip->info->name, rev); 4598 4599 return 0; 4600 } 4601 4602 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4603 { 4604 struct mv88e6xxx_chip *chip; 4605 4606 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4607 if (!chip) 4608 return NULL; 4609 4610 chip->dev = dev; 4611 4612 mutex_init(&chip->reg_lock); 4613 INIT_LIST_HEAD(&chip->mdios); 4614 4615 return chip; 4616 } 4617 4618 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4619 struct mii_bus *bus, int sw_addr) 4620 { 4621 if (sw_addr == 0) 4622 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4623 else if (chip->info->multi_chip) 4624 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4625 else 4626 return -EINVAL; 4627 4628 chip->bus = bus; 4629 chip->sw_addr = sw_addr; 4630 4631 return 0; 4632 } 4633 4634 static void mv88e6xxx_ports_cmode_init(struct mv88e6xxx_chip *chip) 4635 { 4636 int i; 4637 4638 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 4639 chip->ports[i].cmode = MV88E6XXX_PORT_STS_CMODE_INVALID; 4640 } 4641 4642 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4643 int port) 4644 { 4645 struct mv88e6xxx_chip *chip = ds->priv; 4646 4647 return chip->info->tag_protocol; 4648 } 4649 4650 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4651 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4652 struct device *host_dev, int sw_addr, 4653 void **priv) 4654 { 4655 struct mv88e6xxx_chip *chip; 4656 struct mii_bus *bus; 4657 int err; 4658 4659 bus = dsa_host_dev_to_mii_bus(host_dev); 4660 if (!bus) 4661 return NULL; 4662 4663 chip = mv88e6xxx_alloc_chip(dsa_dev); 4664 if (!chip) 4665 return NULL; 4666 4667 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4668 chip->info = &mv88e6xxx_table[MV88E6085]; 4669 4670 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4671 if (err) 4672 goto free; 4673 4674 err = mv88e6xxx_detect(chip); 4675 if (err) 4676 goto free; 4677 4678 mv88e6xxx_ports_cmode_init(chip); 4679 4680 mutex_lock(&chip->reg_lock); 4681 err = mv88e6xxx_switch_reset(chip); 4682 mutex_unlock(&chip->reg_lock); 4683 if (err) 4684 goto free; 4685 4686 mv88e6xxx_phy_init(chip); 4687 4688 err = mv88e6xxx_mdios_register(chip, NULL); 4689 if (err) 4690 goto free; 4691 4692 *priv = chip; 4693 4694 return chip->info->name; 4695 free: 4696 devm_kfree(dsa_dev, chip); 4697 4698 return NULL; 4699 } 4700 #endif 4701 4702 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4703 const struct switchdev_obj_port_mdb *mdb) 4704 { 4705 /* We don't need any dynamic resource from the kernel (yet), 4706 * so skip the prepare phase. 4707 */ 4708 4709 return 0; 4710 } 4711 4712 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4713 const struct switchdev_obj_port_mdb *mdb) 4714 { 4715 struct mv88e6xxx_chip *chip = ds->priv; 4716 4717 mutex_lock(&chip->reg_lock); 4718 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4719 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4720 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4721 port); 4722 mutex_unlock(&chip->reg_lock); 4723 } 4724 4725 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4726 const struct switchdev_obj_port_mdb *mdb) 4727 { 4728 struct mv88e6xxx_chip *chip = ds->priv; 4729 int err; 4730 4731 mutex_lock(&chip->reg_lock); 4732 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4733 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4734 mutex_unlock(&chip->reg_lock); 4735 4736 return err; 4737 } 4738 4739 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 4740 bool unicast, bool multicast) 4741 { 4742 struct mv88e6xxx_chip *chip = ds->priv; 4743 int err = -EOPNOTSUPP; 4744 4745 mutex_lock(&chip->reg_lock); 4746 if (chip->info->ops->port_set_egress_floods) 4747 err = chip->info->ops->port_set_egress_floods(chip, port, 4748 unicast, 4749 multicast); 4750 mutex_unlock(&chip->reg_lock); 4751 4752 return err; 4753 } 4754 4755 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4756 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 4757 .probe = mv88e6xxx_drv_probe, 4758 #endif 4759 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4760 .setup = mv88e6xxx_setup, 4761 .adjust_link = mv88e6xxx_adjust_link, 4762 .phylink_validate = mv88e6xxx_validate, 4763 .phylink_mac_link_state = mv88e6xxx_link_state, 4764 .phylink_mac_config = mv88e6xxx_mac_config, 4765 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4766 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4767 .get_strings = mv88e6xxx_get_strings, 4768 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4769 .get_sset_count = mv88e6xxx_get_sset_count, 4770 .port_enable = mv88e6xxx_port_enable, 4771 .port_disable = mv88e6xxx_port_disable, 4772 .get_mac_eee = mv88e6xxx_get_mac_eee, 4773 .set_mac_eee = mv88e6xxx_set_mac_eee, 4774 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4775 .get_eeprom = mv88e6xxx_get_eeprom, 4776 .set_eeprom = mv88e6xxx_set_eeprom, 4777 .get_regs_len = mv88e6xxx_get_regs_len, 4778 .get_regs = mv88e6xxx_get_regs, 4779 .set_ageing_time = mv88e6xxx_set_ageing_time, 4780 .port_bridge_join = mv88e6xxx_port_bridge_join, 4781 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4782 .port_egress_floods = mv88e6xxx_port_egress_floods, 4783 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4784 .port_fast_age = mv88e6xxx_port_fast_age, 4785 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4786 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4787 .port_vlan_add = mv88e6xxx_port_vlan_add, 4788 .port_vlan_del = mv88e6xxx_port_vlan_del, 4789 .port_fdb_add = mv88e6xxx_port_fdb_add, 4790 .port_fdb_del = mv88e6xxx_port_fdb_del, 4791 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4792 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4793 .port_mdb_add = mv88e6xxx_port_mdb_add, 4794 .port_mdb_del = mv88e6xxx_port_mdb_del, 4795 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4796 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4797 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4798 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4799 .port_txtstamp = mv88e6xxx_port_txtstamp, 4800 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4801 .get_ts_info = mv88e6xxx_get_ts_info, 4802 }; 4803 4804 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4805 .ops = &mv88e6xxx_switch_ops, 4806 }; 4807 4808 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4809 { 4810 struct device *dev = chip->dev; 4811 struct dsa_switch *ds; 4812 4813 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4814 if (!ds) 4815 return -ENOMEM; 4816 4817 ds->priv = chip; 4818 ds->dev = dev; 4819 ds->ops = &mv88e6xxx_switch_ops; 4820 ds->ageing_time_min = chip->info->age_time_coeff; 4821 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4822 4823 dev_set_drvdata(dev, ds); 4824 4825 return dsa_register_switch(ds); 4826 } 4827 4828 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4829 { 4830 dsa_unregister_switch(chip->ds); 4831 } 4832 4833 static const void *pdata_device_get_match_data(struct device *dev) 4834 { 4835 const struct of_device_id *matches = dev->driver->of_match_table; 4836 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4837 4838 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4839 matches++) { 4840 if (!strcmp(pdata->compatible, matches->compatible)) 4841 return matches->data; 4842 } 4843 return NULL; 4844 } 4845 4846 /* There is no suspend to RAM support at DSA level yet, the switch configuration 4847 * would be lost after a power cycle so prevent it to be suspended. 4848 */ 4849 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 4850 { 4851 return -EOPNOTSUPP; 4852 } 4853 4854 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 4855 { 4856 return 0; 4857 } 4858 4859 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 4860 4861 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4862 { 4863 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4864 const struct mv88e6xxx_info *compat_info = NULL; 4865 struct device *dev = &mdiodev->dev; 4866 struct device_node *np = dev->of_node; 4867 struct mv88e6xxx_chip *chip; 4868 int port; 4869 int err; 4870 4871 if (!np && !pdata) 4872 return -EINVAL; 4873 4874 if (np) 4875 compat_info = of_device_get_match_data(dev); 4876 4877 if (pdata) { 4878 compat_info = pdata_device_get_match_data(dev); 4879 4880 if (!pdata->netdev) 4881 return -EINVAL; 4882 4883 for (port = 0; port < DSA_MAX_PORTS; port++) { 4884 if (!(pdata->enabled_ports & (1 << port))) 4885 continue; 4886 if (strcmp(pdata->cd.port_names[port], "cpu")) 4887 continue; 4888 pdata->cd.netdev[port] = &pdata->netdev->dev; 4889 break; 4890 } 4891 } 4892 4893 if (!compat_info) 4894 return -EINVAL; 4895 4896 chip = mv88e6xxx_alloc_chip(dev); 4897 if (!chip) { 4898 err = -ENOMEM; 4899 goto out; 4900 } 4901 4902 chip->info = compat_info; 4903 4904 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4905 if (err) 4906 goto out; 4907 4908 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4909 if (IS_ERR(chip->reset)) { 4910 err = PTR_ERR(chip->reset); 4911 goto out; 4912 } 4913 4914 err = mv88e6xxx_detect(chip); 4915 if (err) 4916 goto out; 4917 4918 mv88e6xxx_ports_cmode_init(chip); 4919 mv88e6xxx_phy_init(chip); 4920 4921 if (chip->info->ops->get_eeprom) { 4922 if (np) 4923 of_property_read_u32(np, "eeprom-length", 4924 &chip->eeprom_len); 4925 else 4926 chip->eeprom_len = pdata->eeprom_len; 4927 } 4928 4929 mutex_lock(&chip->reg_lock); 4930 err = mv88e6xxx_switch_reset(chip); 4931 mutex_unlock(&chip->reg_lock); 4932 if (err) 4933 goto out; 4934 4935 chip->irq = of_irq_get(np, 0); 4936 if (chip->irq == -EPROBE_DEFER) { 4937 err = chip->irq; 4938 goto out; 4939 } 4940 4941 /* Has to be performed before the MDIO bus is created, because 4942 * the PHYs will link their interrupts to these interrupt 4943 * controllers 4944 */ 4945 mutex_lock(&chip->reg_lock); 4946 if (chip->irq > 0) 4947 err = mv88e6xxx_g1_irq_setup(chip); 4948 else 4949 err = mv88e6xxx_irq_poll_setup(chip); 4950 mutex_unlock(&chip->reg_lock); 4951 4952 if (err) 4953 goto out; 4954 4955 if (chip->info->g2_irqs > 0) { 4956 err = mv88e6xxx_g2_irq_setup(chip); 4957 if (err) 4958 goto out_g1_irq; 4959 } 4960 4961 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4962 if (err) 4963 goto out_g2_irq; 4964 4965 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4966 if (err) 4967 goto out_g1_atu_prob_irq; 4968 4969 err = mv88e6xxx_mdios_register(chip, np); 4970 if (err) 4971 goto out_g1_vtu_prob_irq; 4972 4973 err = mv88e6xxx_register_switch(chip); 4974 if (err) 4975 goto out_mdio; 4976 4977 return 0; 4978 4979 out_mdio: 4980 mv88e6xxx_mdios_unregister(chip); 4981 out_g1_vtu_prob_irq: 4982 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4983 out_g1_atu_prob_irq: 4984 mv88e6xxx_g1_atu_prob_irq_free(chip); 4985 out_g2_irq: 4986 if (chip->info->g2_irqs > 0) 4987 mv88e6xxx_g2_irq_free(chip); 4988 out_g1_irq: 4989 if (chip->irq > 0) 4990 mv88e6xxx_g1_irq_free(chip); 4991 else 4992 mv88e6xxx_irq_poll_free(chip); 4993 out: 4994 if (pdata) 4995 dev_put(pdata->netdev); 4996 4997 return err; 4998 } 4999 5000 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5001 { 5002 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5003 struct mv88e6xxx_chip *chip = ds->priv; 5004 5005 if (chip->info->ptp_support) { 5006 mv88e6xxx_hwtstamp_free(chip); 5007 mv88e6xxx_ptp_free(chip); 5008 } 5009 5010 mv88e6xxx_phy_destroy(chip); 5011 mv88e6xxx_unregister_switch(chip); 5012 mv88e6xxx_mdios_unregister(chip); 5013 5014 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5015 mv88e6xxx_g1_atu_prob_irq_free(chip); 5016 5017 if (chip->info->g2_irqs > 0) 5018 mv88e6xxx_g2_irq_free(chip); 5019 5020 if (chip->irq > 0) 5021 mv88e6xxx_g1_irq_free(chip); 5022 else 5023 mv88e6xxx_irq_poll_free(chip); 5024 } 5025 5026 static const struct of_device_id mv88e6xxx_of_match[] = { 5027 { 5028 .compatible = "marvell,mv88e6085", 5029 .data = &mv88e6xxx_table[MV88E6085], 5030 }, 5031 { 5032 .compatible = "marvell,mv88e6190", 5033 .data = &mv88e6xxx_table[MV88E6190], 5034 }, 5035 { /* sentinel */ }, 5036 }; 5037 5038 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5039 5040 static struct mdio_driver mv88e6xxx_driver = { 5041 .probe = mv88e6xxx_probe, 5042 .remove = mv88e6xxx_remove, 5043 .mdiodrv.driver = { 5044 .name = "mv88e6085", 5045 .of_match_table = mv88e6xxx_of_match, 5046 .pm = &mv88e6xxx_pm_ops, 5047 }, 5048 }; 5049 5050 static int __init mv88e6xxx_init(void) 5051 { 5052 register_switch_driver(&mv88e6xxx_switch_drv); 5053 return mdio_driver_register(&mv88e6xxx_driver); 5054 } 5055 module_init(mv88e6xxx_init); 5056 5057 static void __exit mv88e6xxx_cleanup(void) 5058 { 5059 mdio_driver_unregister(&mv88e6xxx_driver); 5060 unregister_switch_driver(&mv88e6xxx_switch_drv); 5061 } 5062 module_exit(mv88e6xxx_cleanup); 5063 5064 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5065 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5066 MODULE_LICENSE("GPL"); 5067