1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "serdes.h" 42 43 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 44 { 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 46 dev_err(chip->dev, "Switch registers lock not held!\n"); 47 dump_stack(); 48 } 49 } 50 51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 53 * 54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 55 * is the only device connected to the SMI master. In this mode it responds to 56 * all 32 possible SMI addresses, and thus maps directly the internal devices. 57 * 58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 59 * multiple devices to share the SMI interface. In this mode it responds to only 60 * 2 registers, used to indirectly access the internal SMI devices. 61 */ 62 63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 *val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->read(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 val) 74 { 75 if (!chip->smi_ops) 76 return -EOPNOTSUPP; 77 78 return chip->smi_ops->write(chip, addr, reg, val); 79 } 80 81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 82 int addr, int reg, u16 *val) 83 { 84 int ret; 85 86 ret = mdiobus_read_nested(chip->bus, addr, reg); 87 if (ret < 0) 88 return ret; 89 90 *val = ret & 0xffff; 91 92 return 0; 93 } 94 95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 96 int addr, int reg, u16 val) 97 { 98 int ret; 99 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 101 if (ret < 0) 102 return ret; 103 104 return 0; 105 } 106 107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 108 .read = mv88e6xxx_smi_single_chip_read, 109 .write = mv88e6xxx_smi_single_chip_write, 110 }; 111 112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 113 { 114 int ret; 115 int i; 116 117 for (i = 0; i < 16; i++) { 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 119 if (ret < 0) 120 return ret; 121 122 if ((ret & SMI_CMD_BUSY) == 0) 123 return 0; 124 } 125 126 return -ETIMEDOUT; 127 } 128 129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 130 int addr, int reg, u16 *val) 131 { 132 int ret; 133 134 /* Wait for the bus to become free. */ 135 ret = mv88e6xxx_smi_multi_chip_wait(chip); 136 if (ret < 0) 137 return ret; 138 139 /* Transmit the read command. */ 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 141 SMI_CMD_OP_22_READ | (addr << 5) | reg); 142 if (ret < 0) 143 return ret; 144 145 /* Wait for the read command to complete. */ 146 ret = mv88e6xxx_smi_multi_chip_wait(chip); 147 if (ret < 0) 148 return ret; 149 150 /* Read the data. */ 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 152 if (ret < 0) 153 return ret; 154 155 *val = ret & 0xffff; 156 157 return 0; 158 } 159 160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 161 int addr, int reg, u16 val) 162 { 163 int ret; 164 165 /* Wait for the bus to become free. */ 166 ret = mv88e6xxx_smi_multi_chip_wait(chip); 167 if (ret < 0) 168 return ret; 169 170 /* Transmit the data to write. */ 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 172 if (ret < 0) 173 return ret; 174 175 /* Transmit the write command. */ 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 178 if (ret < 0) 179 return ret; 180 181 /* Wait for the write command to complete. */ 182 ret = mv88e6xxx_smi_multi_chip_wait(chip); 183 if (ret < 0) 184 return ret; 185 186 return 0; 187 } 188 189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 190 .read = mv88e6xxx_smi_multi_chip_read, 191 .write = mv88e6xxx_smi_multi_chip_write, 192 }; 193 194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 195 { 196 int err; 197 198 assert_reg_lock(chip); 199 200 err = mv88e6xxx_smi_read(chip, addr, reg, val); 201 if (err) 202 return err; 203 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 205 addr, reg, *val); 206 207 return 0; 208 } 209 210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 211 { 212 int err; 213 214 assert_reg_lock(chip); 215 216 err = mv88e6xxx_smi_write(chip, addr, reg, val); 217 if (err) 218 return err; 219 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 221 addr, reg, val); 222 223 return 0; 224 } 225 226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 227 { 228 struct mv88e6xxx_mdio_bus *mdio_bus; 229 230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 231 list); 232 if (!mdio_bus) 233 return NULL; 234 235 return mdio_bus->bus; 236 } 237 238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 239 { 240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 241 unsigned int n = d->hwirq; 242 243 chip->g1_irq.masked |= (1 << n); 244 } 245 246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 247 { 248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 249 unsigned int n = d->hwirq; 250 251 chip->g1_irq.masked &= ~(1 << n); 252 } 253 254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 255 { 256 struct mv88e6xxx_chip *chip = dev_id; 257 unsigned int nhandled = 0; 258 unsigned int sub_irq; 259 unsigned int n; 260 u16 reg; 261 int err; 262 263 mutex_lock(&chip->reg_lock); 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 265 mutex_unlock(&chip->reg_lock); 266 267 if (err) 268 goto out; 269 270 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 271 if (reg & (1 << n)) { 272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 273 handle_nested_irq(sub_irq); 274 ++nhandled; 275 } 276 } 277 out: 278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 279 } 280 281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 282 { 283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 284 285 mutex_lock(&chip->reg_lock); 286 } 287 288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 289 { 290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 292 u16 reg; 293 int err; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 296 if (err) 297 goto out; 298 299 reg &= ~mask; 300 reg |= (~chip->g1_irq.masked & mask); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 303 if (err) 304 goto out; 305 306 out: 307 mutex_unlock(&chip->reg_lock); 308 } 309 310 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 311 .name = "mv88e6xxx-g1", 312 .irq_mask = mv88e6xxx_g1_irq_mask, 313 .irq_unmask = mv88e6xxx_g1_irq_unmask, 314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 316 }; 317 318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 319 unsigned int irq, 320 irq_hw_number_t hwirq) 321 { 322 struct mv88e6xxx_chip *chip = d->host_data; 323 324 irq_set_chip_data(irq, d->host_data); 325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 326 irq_set_noprobe(irq); 327 328 return 0; 329 } 330 331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 332 .map = mv88e6xxx_g1_irq_domain_map, 333 .xlate = irq_domain_xlate_twocell, 334 }; 335 336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 337 { 338 int irq, virq; 339 u16 mask; 340 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 342 mask |= GENMASK(chip->g1_irq.nirqs, 0); 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 344 345 free_irq(chip->irq, chip); 346 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 348 virq = irq_find_mapping(chip->g1_irq.domain, irq); 349 irq_dispose_mapping(virq); 350 } 351 352 irq_domain_remove(chip->g1_irq.domain); 353 } 354 355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 356 { 357 int err, irq, virq; 358 u16 reg, mask; 359 360 chip->g1_irq.nirqs = chip->info->g1_irqs; 361 chip->g1_irq.domain = irq_domain_add_simple( 362 NULL, chip->g1_irq.nirqs, 0, 363 &mv88e6xxx_g1_irq_domain_ops, chip); 364 if (!chip->g1_irq.domain) 365 return -ENOMEM; 366 367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 368 irq_create_mapping(chip->g1_irq.domain, irq); 369 370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 371 chip->g1_irq.masked = ~0; 372 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 374 if (err) 375 goto out_mapping; 376 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 378 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 380 if (err) 381 goto out_disable; 382 383 /* Reading the interrupt status clears (most of) them */ 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 385 if (err) 386 goto out_disable; 387 388 err = request_threaded_irq(chip->irq, NULL, 389 mv88e6xxx_g1_irq_thread_fn, 390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 391 dev_name(chip->dev), chip); 392 if (err) 393 goto out_disable; 394 395 return 0; 396 397 out_disable: 398 mask |= GENMASK(chip->g1_irq.nirqs, 0); 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 400 401 out_mapping: 402 for (irq = 0; irq < 16; irq++) { 403 virq = irq_find_mapping(chip->g1_irq.domain, irq); 404 irq_dispose_mapping(virq); 405 } 406 407 irq_domain_remove(chip->g1_irq.domain); 408 409 return err; 410 } 411 412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 413 { 414 int i; 415 416 for (i = 0; i < 16; i++) { 417 u16 val; 418 int err; 419 420 err = mv88e6xxx_read(chip, addr, reg, &val); 421 if (err) 422 return err; 423 424 if (!(val & mask)) 425 return 0; 426 427 usleep_range(1000, 2000); 428 } 429 430 dev_err(chip->dev, "Timeout while waiting for switch\n"); 431 return -ETIMEDOUT; 432 } 433 434 /* Indirect write to single pointer-data register with an Update bit */ 435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 436 { 437 u16 val; 438 int err; 439 440 /* Wait until the previous operation is completed */ 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 442 if (err) 443 return err; 444 445 /* Set the Update bit to trigger a write operation */ 446 val = BIT(15) | update; 447 448 return mv88e6xxx_write(chip, addr, reg, val); 449 } 450 451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 452 int link, int speed, int duplex, 453 phy_interface_t mode) 454 { 455 int err; 456 457 if (!chip->info->ops->port_set_link) 458 return 0; 459 460 /* Port's MAC control must not be changed unless the link is down */ 461 err = chip->info->ops->port_set_link(chip, port, 0); 462 if (err) 463 return err; 464 465 if (chip->info->ops->port_set_speed) { 466 err = chip->info->ops->port_set_speed(chip, port, speed); 467 if (err && err != -EOPNOTSUPP) 468 goto restore_link; 469 } 470 471 if (chip->info->ops->port_set_duplex) { 472 err = chip->info->ops->port_set_duplex(chip, port, duplex); 473 if (err && err != -EOPNOTSUPP) 474 goto restore_link; 475 } 476 477 if (chip->info->ops->port_set_rgmii_delay) { 478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 479 if (err && err != -EOPNOTSUPP) 480 goto restore_link; 481 } 482 483 if (chip->info->ops->port_set_cmode) { 484 err = chip->info->ops->port_set_cmode(chip, port, mode); 485 if (err && err != -EOPNOTSUPP) 486 goto restore_link; 487 } 488 489 err = 0; 490 restore_link: 491 if (chip->info->ops->port_set_link(chip, port, link)) 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 493 494 return err; 495 } 496 497 /* We expect the switch to perform auto negotiation if there is a real 498 * phy. However, in the case of a fixed link phy, we force the port 499 * settings from the fixed link settings. 500 */ 501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 502 struct phy_device *phydev) 503 { 504 struct mv88e6xxx_chip *chip = ds->priv; 505 int err; 506 507 if (!phy_is_pseudo_fixed_link(phydev)) 508 return; 509 510 mutex_lock(&chip->reg_lock); 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 512 phydev->duplex, phydev->interface); 513 mutex_unlock(&chip->reg_lock); 514 515 if (err && err != -EOPNOTSUPP) 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 517 } 518 519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 if (!chip->info->ops->stats_snapshot) 522 return -EOPNOTSUPP; 523 524 return chip->info->ops->stats_snapshot(chip, port); 525 } 526 527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 548 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 551 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 587 }; 588 589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 590 struct mv88e6xxx_hw_stat *s, 591 int port, u16 bank1_select, 592 u16 histogram) 593 { 594 u32 low; 595 u32 high = 0; 596 u16 reg = 0; 597 int err; 598 u64 value; 599 600 switch (s->type) { 601 case STATS_TYPE_PORT: 602 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 603 if (err) 604 return UINT64_MAX; 605 606 low = reg; 607 if (s->sizeof_stat == 4) { 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 609 if (err) 610 return UINT64_MAX; 611 high = reg; 612 } 613 break; 614 case STATS_TYPE_BANK1: 615 reg = bank1_select; 616 /* fall through */ 617 case STATS_TYPE_BANK0: 618 reg |= s->reg | histogram; 619 mv88e6xxx_g1_stats_read(chip, reg, &low); 620 if (s->sizeof_stat == 8) 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 622 break; 623 default: 624 return UINT64_MAX; 625 } 626 value = (((u64)high) << 16) | low; 627 return value; 628 } 629 630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 631 uint8_t *data, int types) 632 { 633 struct mv88e6xxx_hw_stat *stat; 634 int i, j; 635 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 637 stat = &mv88e6xxx_hw_stats[i]; 638 if (stat->type & types) { 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 640 ETH_GSTRING_LEN); 641 j++; 642 } 643 } 644 } 645 646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 647 uint8_t *data) 648 { 649 mv88e6xxx_stats_get_strings(chip, data, 650 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 651 } 652 653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 654 uint8_t *data) 655 { 656 mv88e6xxx_stats_get_strings(chip, data, 657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 658 } 659 660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 661 uint8_t *data) 662 { 663 struct mv88e6xxx_chip *chip = ds->priv; 664 665 if (chip->info->ops->stats_get_strings) 666 chip->info->ops->stats_get_strings(chip, data); 667 } 668 669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 670 int types) 671 { 672 struct mv88e6xxx_hw_stat *stat; 673 int i, j; 674 675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 676 stat = &mv88e6xxx_hw_stats[i]; 677 if (stat->type & types) 678 j++; 679 } 680 return j; 681 } 682 683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 684 { 685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 686 STATS_TYPE_PORT); 687 } 688 689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 692 STATS_TYPE_BANK1); 693 } 694 695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 696 { 697 struct mv88e6xxx_chip *chip = ds->priv; 698 699 if (chip->info->ops->stats_get_sset_count) 700 return chip->info->ops->stats_get_sset_count(chip); 701 702 return 0; 703 } 704 705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 706 uint64_t *data, int types, 707 u16 bank1_select, u16 histogram) 708 { 709 struct mv88e6xxx_hw_stat *stat; 710 int i, j; 711 712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 713 stat = &mv88e6xxx_hw_stats[i]; 714 if (stat->type & types) { 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 716 bank1_select, 717 histogram); 718 j++; 719 } 720 } 721 } 722 723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 724 uint64_t *data) 725 { 726 return mv88e6xxx_stats_get_stats(chip, port, data, 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 729 } 730 731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 732 uint64_t *data) 733 { 734 return mv88e6xxx_stats_get_stats(chip, port, data, 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 738 } 739 740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 741 uint64_t *data) 742 { 743 return mv88e6xxx_stats_get_stats(chip, port, data, 744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 746 0); 747 } 748 749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 750 uint64_t *data) 751 { 752 if (chip->info->ops->stats_get_stats) 753 chip->info->ops->stats_get_stats(chip, port, data); 754 } 755 756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 757 uint64_t *data) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 int ret; 761 762 mutex_lock(&chip->reg_lock); 763 764 ret = mv88e6xxx_stats_snapshot(chip, port); 765 if (ret < 0) { 766 mutex_unlock(&chip->reg_lock); 767 return; 768 } 769 770 mv88e6xxx_get_stats(chip, port, data); 771 772 mutex_unlock(&chip->reg_lock); 773 } 774 775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 776 { 777 if (chip->info->ops->stats_set_histogram) 778 return chip->info->ops->stats_set_histogram(chip); 779 780 return 0; 781 } 782 783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 784 { 785 return 32 * sizeof(u16); 786 } 787 788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 789 struct ethtool_regs *regs, void *_p) 790 { 791 struct mv88e6xxx_chip *chip = ds->priv; 792 int err; 793 u16 reg; 794 u16 *p = _p; 795 int i; 796 797 regs->version = 0; 798 799 memset(p, 0xff, 32 * sizeof(u16)); 800 801 mutex_lock(&chip->reg_lock); 802 803 for (i = 0; i < 32; i++) { 804 805 err = mv88e6xxx_port_read(chip, port, i, ®); 806 if (!err) 807 p[i] = reg; 808 } 809 810 mutex_unlock(&chip->reg_lock); 811 } 812 813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 814 struct ethtool_eee *e) 815 { 816 /* Nothing to do on the port's MAC */ 817 return 0; 818 } 819 820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 821 struct ethtool_eee *e) 822 { 823 /* Nothing to do on the port's MAC */ 824 return 0; 825 } 826 827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 828 { 829 struct dsa_switch *ds = NULL; 830 struct net_device *br; 831 u16 pvlan; 832 int i; 833 834 if (dev < DSA_MAX_SWITCHES) 835 ds = chip->ds->dst->ds[dev]; 836 837 /* Prevent frames from unknown switch or port */ 838 if (!ds || port >= ds->num_ports) 839 return 0; 840 841 /* Frames from DSA links and CPU ports can egress any local port */ 842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 843 return mv88e6xxx_port_mask(chip); 844 845 br = ds->ports[port].bridge_dev; 846 pvlan = 0; 847 848 /* Frames from user ports can egress any local DSA links and CPU ports, 849 * as well as any local member of their bridge group. 850 */ 851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 852 if (dsa_is_cpu_port(chip->ds, i) || 853 dsa_is_dsa_port(chip->ds, i) || 854 (br && chip->ds->ports[i].bridge_dev == br)) 855 pvlan |= BIT(i); 856 857 return pvlan; 858 } 859 860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 861 { 862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 863 864 /* prevent frames from going back out of the port they came in on */ 865 output_ports &= ~BIT(port); 866 867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 868 } 869 870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 871 u8 state) 872 { 873 struct mv88e6xxx_chip *chip = ds->priv; 874 int err; 875 876 mutex_lock(&chip->reg_lock); 877 err = mv88e6xxx_port_set_state(chip, port, state); 878 mutex_unlock(&chip->reg_lock); 879 880 if (err) 881 dev_err(ds->dev, "p%d: failed to update state\n", port); 882 } 883 884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 885 { 886 if (chip->info->ops->pot_clear) 887 return chip->info->ops->pot_clear(chip); 888 889 return 0; 890 } 891 892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 893 { 894 if (chip->info->ops->mgmt_rsvd2cpu) 895 return chip->info->ops->mgmt_rsvd2cpu(chip); 896 897 return 0; 898 } 899 900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 901 { 902 int err; 903 904 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 905 if (err) 906 return err; 907 908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 909 if (err) 910 return err; 911 912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 913 } 914 915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 916 { 917 int port; 918 int err; 919 920 if (!chip->info->ops->irl_init_all) 921 return 0; 922 923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 924 /* Disable ingress rate limiting by resetting all per port 925 * ingress rate limit resources to their initial state. 926 */ 927 err = chip->info->ops->irl_init_all(chip, port); 928 if (err) 929 return err; 930 } 931 932 return 0; 933 } 934 935 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 936 { 937 u16 pvlan = 0; 938 939 if (!mv88e6xxx_has_pvt(chip)) 940 return -EOPNOTSUPP; 941 942 /* Skip the local source device, which uses in-chip port VLAN */ 943 if (dev != chip->ds->index) 944 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 945 946 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 947 } 948 949 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 950 { 951 int dev, port; 952 int err; 953 954 if (!mv88e6xxx_has_pvt(chip)) 955 return 0; 956 957 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 958 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 959 */ 960 err = mv88e6xxx_g2_misc_4_bit_port(chip); 961 if (err) 962 return err; 963 964 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 965 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 966 err = mv88e6xxx_pvt_map(chip, dev, port); 967 if (err) 968 return err; 969 } 970 } 971 972 return 0; 973 } 974 975 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 976 { 977 struct mv88e6xxx_chip *chip = ds->priv; 978 int err; 979 980 mutex_lock(&chip->reg_lock); 981 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 982 mutex_unlock(&chip->reg_lock); 983 984 if (err) 985 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 986 } 987 988 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 989 { 990 if (!chip->info->max_vid) 991 return 0; 992 993 return mv88e6xxx_g1_vtu_flush(chip); 994 } 995 996 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 997 struct mv88e6xxx_vtu_entry *entry) 998 { 999 if (!chip->info->ops->vtu_getnext) 1000 return -EOPNOTSUPP; 1001 1002 return chip->info->ops->vtu_getnext(chip, entry); 1003 } 1004 1005 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1006 struct mv88e6xxx_vtu_entry *entry) 1007 { 1008 if (!chip->info->ops->vtu_loadpurge) 1009 return -EOPNOTSUPP; 1010 1011 return chip->info->ops->vtu_loadpurge(chip, entry); 1012 } 1013 1014 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1015 { 1016 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1017 struct mv88e6xxx_vtu_entry vlan = { 1018 .vid = chip->info->max_vid, 1019 }; 1020 int i, err; 1021 1022 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1023 1024 /* Set every FID bit used by the (un)bridged ports */ 1025 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1026 err = mv88e6xxx_port_get_fid(chip, i, fid); 1027 if (err) 1028 return err; 1029 1030 set_bit(*fid, fid_bitmap); 1031 } 1032 1033 /* Set every FID bit used by the VLAN entries */ 1034 do { 1035 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1036 if (err) 1037 return err; 1038 1039 if (!vlan.valid) 1040 break; 1041 1042 set_bit(vlan.fid, fid_bitmap); 1043 } while (vlan.vid < chip->info->max_vid); 1044 1045 /* The reset value 0x000 is used to indicate that multiple address 1046 * databases are not needed. Return the next positive available. 1047 */ 1048 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1049 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1050 return -ENOSPC; 1051 1052 /* Clear the database */ 1053 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1054 } 1055 1056 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1057 struct mv88e6xxx_vtu_entry *entry, bool new) 1058 { 1059 int err; 1060 1061 if (!vid) 1062 return -EINVAL; 1063 1064 entry->vid = vid - 1; 1065 entry->valid = false; 1066 1067 err = mv88e6xxx_vtu_getnext(chip, entry); 1068 if (err) 1069 return err; 1070 1071 if (entry->vid == vid && entry->valid) 1072 return 0; 1073 1074 if (new) { 1075 int i; 1076 1077 /* Initialize a fresh VLAN entry */ 1078 memset(entry, 0, sizeof(*entry)); 1079 entry->valid = true; 1080 entry->vid = vid; 1081 1082 /* Exclude all ports */ 1083 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1084 entry->member[i] = 1085 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1086 1087 return mv88e6xxx_atu_new(chip, &entry->fid); 1088 } 1089 1090 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1091 return -EOPNOTSUPP; 1092 } 1093 1094 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1095 u16 vid_begin, u16 vid_end) 1096 { 1097 struct mv88e6xxx_chip *chip = ds->priv; 1098 struct mv88e6xxx_vtu_entry vlan = { 1099 .vid = vid_begin - 1, 1100 }; 1101 int i, err; 1102 1103 /* DSA and CPU ports have to be members of multiple vlans */ 1104 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1105 return 0; 1106 1107 if (!vid_begin) 1108 return -EOPNOTSUPP; 1109 1110 mutex_lock(&chip->reg_lock); 1111 1112 do { 1113 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1114 if (err) 1115 goto unlock; 1116 1117 if (!vlan.valid) 1118 break; 1119 1120 if (vlan.vid > vid_end) 1121 break; 1122 1123 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1124 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1125 continue; 1126 1127 if (!ds->ports[port].netdev) 1128 continue; 1129 1130 if (vlan.member[i] == 1131 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1132 continue; 1133 1134 if (ds->ports[i].bridge_dev == 1135 ds->ports[port].bridge_dev) 1136 break; /* same bridge, check next VLAN */ 1137 1138 if (!ds->ports[i].bridge_dev) 1139 continue; 1140 1141 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n", 1142 port, vlan.vid, 1143 netdev_name(ds->ports[i].bridge_dev)); 1144 err = -EOPNOTSUPP; 1145 goto unlock; 1146 } 1147 } while (vlan.vid < vid_end); 1148 1149 unlock: 1150 mutex_unlock(&chip->reg_lock); 1151 1152 return err; 1153 } 1154 1155 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1156 bool vlan_filtering) 1157 { 1158 struct mv88e6xxx_chip *chip = ds->priv; 1159 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1160 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1161 int err; 1162 1163 if (!chip->info->max_vid) 1164 return -EOPNOTSUPP; 1165 1166 mutex_lock(&chip->reg_lock); 1167 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1168 mutex_unlock(&chip->reg_lock); 1169 1170 return err; 1171 } 1172 1173 static int 1174 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1175 const struct switchdev_obj_port_vlan *vlan, 1176 struct switchdev_trans *trans) 1177 { 1178 struct mv88e6xxx_chip *chip = ds->priv; 1179 int err; 1180 1181 if (!chip->info->max_vid) 1182 return -EOPNOTSUPP; 1183 1184 /* If the requested port doesn't belong to the same bridge as the VLAN 1185 * members, do not support it (yet) and fallback to software VLAN. 1186 */ 1187 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1188 vlan->vid_end); 1189 if (err) 1190 return err; 1191 1192 /* We don't need any dynamic resource from the kernel (yet), 1193 * so skip the prepare phase. 1194 */ 1195 return 0; 1196 } 1197 1198 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1199 u16 vid, u8 member) 1200 { 1201 struct mv88e6xxx_vtu_entry vlan; 1202 int err; 1203 1204 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1205 if (err) 1206 return err; 1207 1208 vlan.member[port] = member; 1209 1210 return mv88e6xxx_vtu_loadpurge(chip, &vlan); 1211 } 1212 1213 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1214 const struct switchdev_obj_port_vlan *vlan, 1215 struct switchdev_trans *trans) 1216 { 1217 struct mv88e6xxx_chip *chip = ds->priv; 1218 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1219 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1220 u8 member; 1221 u16 vid; 1222 1223 if (!chip->info->max_vid) 1224 return; 1225 1226 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1227 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1228 else if (untagged) 1229 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1230 else 1231 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1232 1233 mutex_lock(&chip->reg_lock); 1234 1235 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1236 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1237 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1238 vid, untagged ? 'u' : 't'); 1239 1240 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1241 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1242 vlan->vid_end); 1243 1244 mutex_unlock(&chip->reg_lock); 1245 } 1246 1247 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1248 int port, u16 vid) 1249 { 1250 struct mv88e6xxx_vtu_entry vlan; 1251 int i, err; 1252 1253 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1254 if (err) 1255 return err; 1256 1257 /* Tell switchdev if this VLAN is handled in software */ 1258 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1259 return -EOPNOTSUPP; 1260 1261 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1262 1263 /* keep the VLAN unless all ports are excluded */ 1264 vlan.valid = false; 1265 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1266 if (vlan.member[i] != 1267 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1268 vlan.valid = true; 1269 break; 1270 } 1271 } 1272 1273 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1274 if (err) 1275 return err; 1276 1277 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1278 } 1279 1280 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1281 const struct switchdev_obj_port_vlan *vlan) 1282 { 1283 struct mv88e6xxx_chip *chip = ds->priv; 1284 u16 pvid, vid; 1285 int err = 0; 1286 1287 if (!chip->info->max_vid) 1288 return -EOPNOTSUPP; 1289 1290 mutex_lock(&chip->reg_lock); 1291 1292 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1293 if (err) 1294 goto unlock; 1295 1296 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1297 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1298 if (err) 1299 goto unlock; 1300 1301 if (vid == pvid) { 1302 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1303 if (err) 1304 goto unlock; 1305 } 1306 } 1307 1308 unlock: 1309 mutex_unlock(&chip->reg_lock); 1310 1311 return err; 1312 } 1313 1314 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1315 const unsigned char *addr, u16 vid, 1316 u8 state) 1317 { 1318 struct mv88e6xxx_vtu_entry vlan; 1319 struct mv88e6xxx_atu_entry entry; 1320 int err; 1321 1322 /* Null VLAN ID corresponds to the port private database */ 1323 if (vid == 0) 1324 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1325 else 1326 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1327 if (err) 1328 return err; 1329 1330 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1331 ether_addr_copy(entry.mac, addr); 1332 eth_addr_dec(entry.mac); 1333 1334 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1335 if (err) 1336 return err; 1337 1338 /* Initialize a fresh ATU entry if it isn't found */ 1339 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1340 !ether_addr_equal(entry.mac, addr)) { 1341 memset(&entry, 0, sizeof(entry)); 1342 ether_addr_copy(entry.mac, addr); 1343 } 1344 1345 /* Purge the ATU entry only if no port is using it anymore */ 1346 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1347 entry.portvec &= ~BIT(port); 1348 if (!entry.portvec) 1349 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1350 } else { 1351 entry.portvec |= BIT(port); 1352 entry.state = state; 1353 } 1354 1355 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1356 } 1357 1358 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1359 const unsigned char *addr, u16 vid) 1360 { 1361 struct mv88e6xxx_chip *chip = ds->priv; 1362 int err; 1363 1364 mutex_lock(&chip->reg_lock); 1365 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1366 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1367 mutex_unlock(&chip->reg_lock); 1368 1369 return err; 1370 } 1371 1372 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1373 const unsigned char *addr, u16 vid) 1374 { 1375 struct mv88e6xxx_chip *chip = ds->priv; 1376 int err; 1377 1378 mutex_lock(&chip->reg_lock); 1379 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1380 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1381 mutex_unlock(&chip->reg_lock); 1382 1383 return err; 1384 } 1385 1386 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1387 u16 fid, u16 vid, int port, 1388 dsa_fdb_dump_cb_t *cb, void *data) 1389 { 1390 struct mv88e6xxx_atu_entry addr; 1391 bool is_static; 1392 int err; 1393 1394 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1395 eth_broadcast_addr(addr.mac); 1396 1397 do { 1398 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1399 if (err) 1400 return err; 1401 1402 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1403 break; 1404 1405 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1406 continue; 1407 1408 if (!is_unicast_ether_addr(addr.mac)) 1409 continue; 1410 1411 is_static = (addr.state == 1412 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1413 err = cb(addr.mac, vid, is_static, data); 1414 if (err) 1415 return err; 1416 } while (!is_broadcast_ether_addr(addr.mac)); 1417 1418 return err; 1419 } 1420 1421 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1422 dsa_fdb_dump_cb_t *cb, void *data) 1423 { 1424 struct mv88e6xxx_vtu_entry vlan = { 1425 .vid = chip->info->max_vid, 1426 }; 1427 u16 fid; 1428 int err; 1429 1430 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1431 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1432 if (err) 1433 return err; 1434 1435 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1436 if (err) 1437 return err; 1438 1439 /* Dump VLANs' Filtering Information Databases */ 1440 do { 1441 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1442 if (err) 1443 return err; 1444 1445 if (!vlan.valid) 1446 break; 1447 1448 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1449 cb, data); 1450 if (err) 1451 return err; 1452 } while (vlan.vid < chip->info->max_vid); 1453 1454 return err; 1455 } 1456 1457 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1458 dsa_fdb_dump_cb_t *cb, void *data) 1459 { 1460 struct mv88e6xxx_chip *chip = ds->priv; 1461 int err; 1462 1463 mutex_lock(&chip->reg_lock); 1464 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1465 mutex_unlock(&chip->reg_lock); 1466 1467 return err; 1468 } 1469 1470 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1471 struct net_device *br) 1472 { 1473 struct dsa_switch *ds; 1474 int port; 1475 int dev; 1476 int err; 1477 1478 /* Remap the Port VLAN of each local bridge group member */ 1479 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1480 if (chip->ds->ports[port].bridge_dev == br) { 1481 err = mv88e6xxx_port_vlan_map(chip, port); 1482 if (err) 1483 return err; 1484 } 1485 } 1486 1487 if (!mv88e6xxx_has_pvt(chip)) 1488 return 0; 1489 1490 /* Remap the Port VLAN of each cross-chip bridge group member */ 1491 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1492 ds = chip->ds->dst->ds[dev]; 1493 if (!ds) 1494 break; 1495 1496 for (port = 0; port < ds->num_ports; ++port) { 1497 if (ds->ports[port].bridge_dev == br) { 1498 err = mv88e6xxx_pvt_map(chip, dev, port); 1499 if (err) 1500 return err; 1501 } 1502 } 1503 } 1504 1505 return 0; 1506 } 1507 1508 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1509 struct net_device *br) 1510 { 1511 struct mv88e6xxx_chip *chip = ds->priv; 1512 int err; 1513 1514 mutex_lock(&chip->reg_lock); 1515 err = mv88e6xxx_bridge_map(chip, br); 1516 mutex_unlock(&chip->reg_lock); 1517 1518 return err; 1519 } 1520 1521 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1522 struct net_device *br) 1523 { 1524 struct mv88e6xxx_chip *chip = ds->priv; 1525 1526 mutex_lock(&chip->reg_lock); 1527 if (mv88e6xxx_bridge_map(chip, br) || 1528 mv88e6xxx_port_vlan_map(chip, port)) 1529 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1530 mutex_unlock(&chip->reg_lock); 1531 } 1532 1533 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1534 int port, struct net_device *br) 1535 { 1536 struct mv88e6xxx_chip *chip = ds->priv; 1537 int err; 1538 1539 if (!mv88e6xxx_has_pvt(chip)) 1540 return 0; 1541 1542 mutex_lock(&chip->reg_lock); 1543 err = mv88e6xxx_pvt_map(chip, dev, port); 1544 mutex_unlock(&chip->reg_lock); 1545 1546 return err; 1547 } 1548 1549 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1550 int port, struct net_device *br) 1551 { 1552 struct mv88e6xxx_chip *chip = ds->priv; 1553 1554 if (!mv88e6xxx_has_pvt(chip)) 1555 return; 1556 1557 mutex_lock(&chip->reg_lock); 1558 if (mv88e6xxx_pvt_map(chip, dev, port)) 1559 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1560 mutex_unlock(&chip->reg_lock); 1561 } 1562 1563 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1564 { 1565 if (chip->info->ops->reset) 1566 return chip->info->ops->reset(chip); 1567 1568 return 0; 1569 } 1570 1571 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1572 { 1573 struct gpio_desc *gpiod = chip->reset; 1574 1575 /* If there is a GPIO connected to the reset pin, toggle it */ 1576 if (gpiod) { 1577 gpiod_set_value_cansleep(gpiod, 1); 1578 usleep_range(10000, 20000); 1579 gpiod_set_value_cansleep(gpiod, 0); 1580 usleep_range(10000, 20000); 1581 } 1582 } 1583 1584 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1585 { 1586 int i, err; 1587 1588 /* Set all ports to the Disabled state */ 1589 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1590 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1591 if (err) 1592 return err; 1593 } 1594 1595 /* Wait for transmit queues to drain, 1596 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1597 */ 1598 usleep_range(2000, 4000); 1599 1600 return 0; 1601 } 1602 1603 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1604 { 1605 int err; 1606 1607 err = mv88e6xxx_disable_ports(chip); 1608 if (err) 1609 return err; 1610 1611 mv88e6xxx_hardware_reset(chip); 1612 1613 return mv88e6xxx_software_reset(chip); 1614 } 1615 1616 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1617 enum mv88e6xxx_frame_mode frame, 1618 enum mv88e6xxx_egress_mode egress, u16 etype) 1619 { 1620 int err; 1621 1622 if (!chip->info->ops->port_set_frame_mode) 1623 return -EOPNOTSUPP; 1624 1625 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1626 if (err) 1627 return err; 1628 1629 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1630 if (err) 1631 return err; 1632 1633 if (chip->info->ops->port_set_ether_type) 1634 return chip->info->ops->port_set_ether_type(chip, port, etype); 1635 1636 return 0; 1637 } 1638 1639 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1640 { 1641 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1642 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1643 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1644 } 1645 1646 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1647 { 1648 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1649 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1650 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1651 } 1652 1653 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1654 { 1655 return mv88e6xxx_set_port_mode(chip, port, 1656 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1657 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1658 ETH_P_EDSA); 1659 } 1660 1661 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1662 { 1663 if (dsa_is_dsa_port(chip->ds, port)) 1664 return mv88e6xxx_set_port_mode_dsa(chip, port); 1665 1666 if (dsa_is_normal_port(chip->ds, port)) 1667 return mv88e6xxx_set_port_mode_normal(chip, port); 1668 1669 /* Setup CPU port mode depending on its supported tag format */ 1670 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1671 return mv88e6xxx_set_port_mode_dsa(chip, port); 1672 1673 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1674 return mv88e6xxx_set_port_mode_edsa(chip, port); 1675 1676 return -EINVAL; 1677 } 1678 1679 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1680 { 1681 bool message = dsa_is_dsa_port(chip->ds, port); 1682 1683 return mv88e6xxx_port_set_message_port(chip, port, message); 1684 } 1685 1686 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1687 { 1688 bool flood = port == dsa_upstream_port(chip->ds); 1689 1690 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1691 if (chip->info->ops->port_set_egress_floods) 1692 return chip->info->ops->port_set_egress_floods(chip, port, 1693 flood, flood); 1694 1695 return 0; 1696 } 1697 1698 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1699 bool on) 1700 { 1701 if (chip->info->ops->serdes_power) 1702 return chip->info->ops->serdes_power(chip, port, on); 1703 1704 return 0; 1705 } 1706 1707 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1708 { 1709 struct dsa_switch *ds = chip->ds; 1710 int err; 1711 u16 reg; 1712 1713 /* MAC Forcing register: don't force link, speed, duplex or flow control 1714 * state to any particular values on physical ports, but force the CPU 1715 * port and all DSA ports to their maximum bandwidth and full duplex. 1716 */ 1717 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1718 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1719 SPEED_MAX, DUPLEX_FULL, 1720 PHY_INTERFACE_MODE_NA); 1721 else 1722 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1723 SPEED_UNFORCED, DUPLEX_UNFORCED, 1724 PHY_INTERFACE_MODE_NA); 1725 if (err) 1726 return err; 1727 1728 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1729 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1730 * tunneling, determine priority by looking at 802.1p and IP 1731 * priority fields (IP prio has precedence), and set STP state 1732 * to Forwarding. 1733 * 1734 * If this is the CPU link, use DSA or EDSA tagging depending 1735 * on which tagging mode was configured. 1736 * 1737 * If this is a link to another switch, use DSA tagging mode. 1738 * 1739 * If this is the upstream port for this switch, enable 1740 * forwarding of unknown unicasts and multicasts. 1741 */ 1742 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1743 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1744 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1745 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1746 if (err) 1747 return err; 1748 1749 err = mv88e6xxx_setup_port_mode(chip, port); 1750 if (err) 1751 return err; 1752 1753 err = mv88e6xxx_setup_egress_floods(chip, port); 1754 if (err) 1755 return err; 1756 1757 /* Enable the SERDES interface for DSA and CPU ports. Normal 1758 * ports SERDES are enabled when the port is enabled, thus 1759 * saving a bit of power. 1760 */ 1761 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1762 err = mv88e6xxx_serdes_power(chip, port, true); 1763 if (err) 1764 return err; 1765 } 1766 1767 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1768 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1769 * untagged frames on this port, do a destination address lookup on all 1770 * received packets as usual, disable ARP mirroring and don't send a 1771 * copy of all transmitted/received frames on this port to the CPU. 1772 */ 1773 err = mv88e6xxx_port_set_map_da(chip, port); 1774 if (err) 1775 return err; 1776 1777 reg = 0; 1778 if (chip->info->ops->port_set_upstream_port) { 1779 err = chip->info->ops->port_set_upstream_port( 1780 chip, port, dsa_upstream_port(ds)); 1781 if (err) 1782 return err; 1783 } 1784 1785 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1786 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1787 if (err) 1788 return err; 1789 1790 if (chip->info->ops->port_set_jumbo_size) { 1791 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1792 if (err) 1793 return err; 1794 } 1795 1796 /* Port Association Vector: when learning source addresses 1797 * of packets, add the address to the address database using 1798 * a port bitmap that has only the bit for this port set and 1799 * the other bits clear. 1800 */ 1801 reg = 1 << port; 1802 /* Disable learning for CPU port */ 1803 if (dsa_is_cpu_port(ds, port)) 1804 reg = 0; 1805 1806 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1807 reg); 1808 if (err) 1809 return err; 1810 1811 /* Egress rate control 2: disable egress rate control. */ 1812 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1813 0x0000); 1814 if (err) 1815 return err; 1816 1817 if (chip->info->ops->port_pause_limit) { 1818 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1819 if (err) 1820 return err; 1821 } 1822 1823 if (chip->info->ops->port_disable_learn_limit) { 1824 err = chip->info->ops->port_disable_learn_limit(chip, port); 1825 if (err) 1826 return err; 1827 } 1828 1829 if (chip->info->ops->port_disable_pri_override) { 1830 err = chip->info->ops->port_disable_pri_override(chip, port); 1831 if (err) 1832 return err; 1833 } 1834 1835 if (chip->info->ops->port_tag_remap) { 1836 err = chip->info->ops->port_tag_remap(chip, port); 1837 if (err) 1838 return err; 1839 } 1840 1841 if (chip->info->ops->port_egress_rate_limiting) { 1842 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1843 if (err) 1844 return err; 1845 } 1846 1847 err = mv88e6xxx_setup_message_port(chip, port); 1848 if (err) 1849 return err; 1850 1851 /* Port based VLAN map: give each port the same default address 1852 * database, and allow bidirectional communication between the 1853 * CPU and DSA port(s), and the other ports. 1854 */ 1855 err = mv88e6xxx_port_set_fid(chip, port, 0); 1856 if (err) 1857 return err; 1858 1859 err = mv88e6xxx_port_vlan_map(chip, port); 1860 if (err) 1861 return err; 1862 1863 /* Default VLAN ID and priority: don't set a default VLAN 1864 * ID, and set the default packet priority to zero. 1865 */ 1866 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 1867 } 1868 1869 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 1870 struct phy_device *phydev) 1871 { 1872 struct mv88e6xxx_chip *chip = ds->priv; 1873 int err; 1874 1875 mutex_lock(&chip->reg_lock); 1876 err = mv88e6xxx_serdes_power(chip, port, true); 1877 mutex_unlock(&chip->reg_lock); 1878 1879 return err; 1880 } 1881 1882 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 1883 struct phy_device *phydev) 1884 { 1885 struct mv88e6xxx_chip *chip = ds->priv; 1886 1887 mutex_lock(&chip->reg_lock); 1888 if (mv88e6xxx_serdes_power(chip, port, false)) 1889 dev_err(chip->dev, "failed to power off SERDES\n"); 1890 mutex_unlock(&chip->reg_lock); 1891 } 1892 1893 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 1894 unsigned int ageing_time) 1895 { 1896 struct mv88e6xxx_chip *chip = ds->priv; 1897 int err; 1898 1899 mutex_lock(&chip->reg_lock); 1900 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 1901 mutex_unlock(&chip->reg_lock); 1902 1903 return err; 1904 } 1905 1906 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 1907 { 1908 struct dsa_switch *ds = chip->ds; 1909 u32 upstream_port = dsa_upstream_port(ds); 1910 int err; 1911 1912 if (chip->info->ops->set_cpu_port) { 1913 err = chip->info->ops->set_cpu_port(chip, upstream_port); 1914 if (err) 1915 return err; 1916 } 1917 1918 if (chip->info->ops->set_egress_port) { 1919 err = chip->info->ops->set_egress_port(chip, upstream_port); 1920 if (err) 1921 return err; 1922 } 1923 1924 /* Disable remote management, and set the switch's DSA device number. */ 1925 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 1926 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 1927 (ds->index & 0x1f)); 1928 if (err) 1929 return err; 1930 1931 /* Configure the IP ToS mapping registers. */ 1932 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 1933 if (err) 1934 return err; 1935 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 1936 if (err) 1937 return err; 1938 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 1939 if (err) 1940 return err; 1941 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 1942 if (err) 1943 return err; 1944 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 1945 if (err) 1946 return err; 1947 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 1948 if (err) 1949 return err; 1950 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 1951 if (err) 1952 return err; 1953 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 1954 if (err) 1955 return err; 1956 1957 /* Configure the IEEE 802.1p priority mapping register. */ 1958 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 1959 if (err) 1960 return err; 1961 1962 /* Initialize the statistics unit */ 1963 err = mv88e6xxx_stats_set_histogram(chip); 1964 if (err) 1965 return err; 1966 1967 /* Clear the statistics counters for all ports */ 1968 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 1969 MV88E6XXX_G1_STATS_OP_BUSY | 1970 MV88E6XXX_G1_STATS_OP_FLUSH_ALL); 1971 if (err) 1972 return err; 1973 1974 /* Wait for the flush to complete. */ 1975 err = mv88e6xxx_g1_stats_wait(chip); 1976 if (err) 1977 return err; 1978 1979 return 0; 1980 } 1981 1982 static int mv88e6xxx_setup(struct dsa_switch *ds) 1983 { 1984 struct mv88e6xxx_chip *chip = ds->priv; 1985 int err; 1986 int i; 1987 1988 chip->ds = ds; 1989 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 1990 1991 mutex_lock(&chip->reg_lock); 1992 1993 /* Setup Switch Port Registers */ 1994 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1995 err = mv88e6xxx_setup_port(chip, i); 1996 if (err) 1997 goto unlock; 1998 } 1999 2000 /* Setup Switch Global 1 Registers */ 2001 err = mv88e6xxx_g1_setup(chip); 2002 if (err) 2003 goto unlock; 2004 2005 /* Setup Switch Global 2 Registers */ 2006 if (chip->info->global2_addr) { 2007 err = mv88e6xxx_g2_setup(chip); 2008 if (err) 2009 goto unlock; 2010 } 2011 2012 err = mv88e6xxx_irl_setup(chip); 2013 if (err) 2014 goto unlock; 2015 2016 err = mv88e6xxx_phy_setup(chip); 2017 if (err) 2018 goto unlock; 2019 2020 err = mv88e6xxx_vtu_setup(chip); 2021 if (err) 2022 goto unlock; 2023 2024 err = mv88e6xxx_pvt_setup(chip); 2025 if (err) 2026 goto unlock; 2027 2028 err = mv88e6xxx_atu_setup(chip); 2029 if (err) 2030 goto unlock; 2031 2032 err = mv88e6xxx_pot_setup(chip); 2033 if (err) 2034 goto unlock; 2035 2036 err = mv88e6xxx_rsvd2cpu_setup(chip); 2037 if (err) 2038 goto unlock; 2039 2040 unlock: 2041 mutex_unlock(&chip->reg_lock); 2042 2043 return err; 2044 } 2045 2046 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2047 { 2048 struct mv88e6xxx_chip *chip = ds->priv; 2049 int err; 2050 2051 if (!chip->info->ops->set_switch_mac) 2052 return -EOPNOTSUPP; 2053 2054 mutex_lock(&chip->reg_lock); 2055 err = chip->info->ops->set_switch_mac(chip, addr); 2056 mutex_unlock(&chip->reg_lock); 2057 2058 return err; 2059 } 2060 2061 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2062 { 2063 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2064 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2065 u16 val; 2066 int err; 2067 2068 if (!chip->info->ops->phy_read) 2069 return -EOPNOTSUPP; 2070 2071 mutex_lock(&chip->reg_lock); 2072 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2073 mutex_unlock(&chip->reg_lock); 2074 2075 if (reg == MII_PHYSID2) { 2076 /* Some internal PHYS don't have a model number. Use 2077 * the mv88e6390 family model number instead. 2078 */ 2079 if (!(val & 0x3f0)) 2080 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2081 } 2082 2083 return err ? err : val; 2084 } 2085 2086 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2087 { 2088 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2089 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2090 int err; 2091 2092 if (!chip->info->ops->phy_write) 2093 return -EOPNOTSUPP; 2094 2095 mutex_lock(&chip->reg_lock); 2096 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2097 mutex_unlock(&chip->reg_lock); 2098 2099 return err; 2100 } 2101 2102 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2103 struct device_node *np, 2104 bool external) 2105 { 2106 static int index; 2107 struct mv88e6xxx_mdio_bus *mdio_bus; 2108 struct mii_bus *bus; 2109 int err; 2110 2111 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2112 if (!bus) 2113 return -ENOMEM; 2114 2115 mdio_bus = bus->priv; 2116 mdio_bus->bus = bus; 2117 mdio_bus->chip = chip; 2118 INIT_LIST_HEAD(&mdio_bus->list); 2119 mdio_bus->external = external; 2120 2121 if (np) { 2122 bus->name = np->full_name; 2123 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2124 } else { 2125 bus->name = "mv88e6xxx SMI"; 2126 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2127 } 2128 2129 bus->read = mv88e6xxx_mdio_read; 2130 bus->write = mv88e6xxx_mdio_write; 2131 bus->parent = chip->dev; 2132 2133 if (np) 2134 err = of_mdiobus_register(bus, np); 2135 else 2136 err = mdiobus_register(bus); 2137 if (err) { 2138 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2139 return err; 2140 } 2141 2142 if (external) 2143 list_add_tail(&mdio_bus->list, &chip->mdios); 2144 else 2145 list_add(&mdio_bus->list, &chip->mdios); 2146 2147 return 0; 2148 } 2149 2150 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2151 { .compatible = "marvell,mv88e6xxx-mdio-external", 2152 .data = (void *)true }, 2153 { }, 2154 }; 2155 2156 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2157 struct device_node *np) 2158 { 2159 const struct of_device_id *match; 2160 struct device_node *child; 2161 int err; 2162 2163 /* Always register one mdio bus for the internal/default mdio 2164 * bus. This maybe represented in the device tree, but is 2165 * optional. 2166 */ 2167 child = of_get_child_by_name(np, "mdio"); 2168 err = mv88e6xxx_mdio_register(chip, child, false); 2169 if (err) 2170 return err; 2171 2172 /* Walk the device tree, and see if there are any other nodes 2173 * which say they are compatible with the external mdio 2174 * bus. 2175 */ 2176 for_each_available_child_of_node(np, child) { 2177 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2178 if (match) { 2179 err = mv88e6xxx_mdio_register(chip, child, true); 2180 if (err) 2181 return err; 2182 } 2183 } 2184 2185 return 0; 2186 } 2187 2188 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2189 2190 { 2191 struct mv88e6xxx_mdio_bus *mdio_bus; 2192 struct mii_bus *bus; 2193 2194 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2195 bus = mdio_bus->bus; 2196 2197 mdiobus_unregister(bus); 2198 } 2199 } 2200 2201 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2202 { 2203 struct mv88e6xxx_chip *chip = ds->priv; 2204 2205 return chip->eeprom_len; 2206 } 2207 2208 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2209 struct ethtool_eeprom *eeprom, u8 *data) 2210 { 2211 struct mv88e6xxx_chip *chip = ds->priv; 2212 int err; 2213 2214 if (!chip->info->ops->get_eeprom) 2215 return -EOPNOTSUPP; 2216 2217 mutex_lock(&chip->reg_lock); 2218 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2219 mutex_unlock(&chip->reg_lock); 2220 2221 if (err) 2222 return err; 2223 2224 eeprom->magic = 0xc3ec4951; 2225 2226 return 0; 2227 } 2228 2229 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2230 struct ethtool_eeprom *eeprom, u8 *data) 2231 { 2232 struct mv88e6xxx_chip *chip = ds->priv; 2233 int err; 2234 2235 if (!chip->info->ops->set_eeprom) 2236 return -EOPNOTSUPP; 2237 2238 if (eeprom->magic != 0xc3ec4951) 2239 return -EINVAL; 2240 2241 mutex_lock(&chip->reg_lock); 2242 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2243 mutex_unlock(&chip->reg_lock); 2244 2245 return err; 2246 } 2247 2248 static const struct mv88e6xxx_ops mv88e6085_ops = { 2249 /* MV88E6XXX_FAMILY_6097 */ 2250 .irl_init_all = mv88e6352_g2_irl_init_all, 2251 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2252 .phy_read = mv88e6185_phy_ppu_read, 2253 .phy_write = mv88e6185_phy_ppu_write, 2254 .port_set_link = mv88e6xxx_port_set_link, 2255 .port_set_duplex = mv88e6xxx_port_set_duplex, 2256 .port_set_speed = mv88e6185_port_set_speed, 2257 .port_tag_remap = mv88e6095_port_tag_remap, 2258 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2259 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2260 .port_set_ether_type = mv88e6351_port_set_ether_type, 2261 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2262 .port_pause_limit = mv88e6097_port_pause_limit, 2263 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2264 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2265 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2266 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2267 .stats_get_strings = mv88e6095_stats_get_strings, 2268 .stats_get_stats = mv88e6095_stats_get_stats, 2269 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2270 .set_egress_port = mv88e6095_g1_set_egress_port, 2271 .watchdog_ops = &mv88e6097_watchdog_ops, 2272 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2273 .pot_clear = mv88e6xxx_g2_pot_clear, 2274 .ppu_enable = mv88e6185_g1_ppu_enable, 2275 .ppu_disable = mv88e6185_g1_ppu_disable, 2276 .reset = mv88e6185_g1_reset, 2277 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2278 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2279 }; 2280 2281 static const struct mv88e6xxx_ops mv88e6095_ops = { 2282 /* MV88E6XXX_FAMILY_6095 */ 2283 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2284 .phy_read = mv88e6185_phy_ppu_read, 2285 .phy_write = mv88e6185_phy_ppu_write, 2286 .port_set_link = mv88e6xxx_port_set_link, 2287 .port_set_duplex = mv88e6xxx_port_set_duplex, 2288 .port_set_speed = mv88e6185_port_set_speed, 2289 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2290 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2291 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2292 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2293 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2294 .stats_get_strings = mv88e6095_stats_get_strings, 2295 .stats_get_stats = mv88e6095_stats_get_stats, 2296 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2297 .ppu_enable = mv88e6185_g1_ppu_enable, 2298 .ppu_disable = mv88e6185_g1_ppu_disable, 2299 .reset = mv88e6185_g1_reset, 2300 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2301 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2302 }; 2303 2304 static const struct mv88e6xxx_ops mv88e6097_ops = { 2305 /* MV88E6XXX_FAMILY_6097 */ 2306 .irl_init_all = mv88e6352_g2_irl_init_all, 2307 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2308 .phy_read = mv88e6xxx_g2_smi_phy_read, 2309 .phy_write = mv88e6xxx_g2_smi_phy_write, 2310 .port_set_link = mv88e6xxx_port_set_link, 2311 .port_set_duplex = mv88e6xxx_port_set_duplex, 2312 .port_set_speed = mv88e6185_port_set_speed, 2313 .port_tag_remap = mv88e6095_port_tag_remap, 2314 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2315 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2316 .port_set_ether_type = mv88e6351_port_set_ether_type, 2317 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2318 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2319 .port_pause_limit = mv88e6097_port_pause_limit, 2320 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2321 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2322 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2323 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2324 .stats_get_strings = mv88e6095_stats_get_strings, 2325 .stats_get_stats = mv88e6095_stats_get_stats, 2326 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2327 .set_egress_port = mv88e6095_g1_set_egress_port, 2328 .watchdog_ops = &mv88e6097_watchdog_ops, 2329 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2330 .pot_clear = mv88e6xxx_g2_pot_clear, 2331 .reset = mv88e6352_g1_reset, 2332 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2333 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2334 }; 2335 2336 static const struct mv88e6xxx_ops mv88e6123_ops = { 2337 /* MV88E6XXX_FAMILY_6165 */ 2338 .irl_init_all = mv88e6352_g2_irl_init_all, 2339 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2340 .phy_read = mv88e6xxx_g2_smi_phy_read, 2341 .phy_write = mv88e6xxx_g2_smi_phy_write, 2342 .port_set_link = mv88e6xxx_port_set_link, 2343 .port_set_duplex = mv88e6xxx_port_set_duplex, 2344 .port_set_speed = mv88e6185_port_set_speed, 2345 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2346 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2347 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2348 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2349 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2350 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2351 .stats_get_strings = mv88e6095_stats_get_strings, 2352 .stats_get_stats = mv88e6095_stats_get_stats, 2353 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2354 .set_egress_port = mv88e6095_g1_set_egress_port, 2355 .watchdog_ops = &mv88e6097_watchdog_ops, 2356 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2357 .pot_clear = mv88e6xxx_g2_pot_clear, 2358 .reset = mv88e6352_g1_reset, 2359 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2360 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2361 }; 2362 2363 static const struct mv88e6xxx_ops mv88e6131_ops = { 2364 /* MV88E6XXX_FAMILY_6185 */ 2365 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2366 .phy_read = mv88e6185_phy_ppu_read, 2367 .phy_write = mv88e6185_phy_ppu_write, 2368 .port_set_link = mv88e6xxx_port_set_link, 2369 .port_set_duplex = mv88e6xxx_port_set_duplex, 2370 .port_set_speed = mv88e6185_port_set_speed, 2371 .port_tag_remap = mv88e6095_port_tag_remap, 2372 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2373 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2374 .port_set_ether_type = mv88e6351_port_set_ether_type, 2375 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2376 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2377 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2378 .port_pause_limit = mv88e6097_port_pause_limit, 2379 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2380 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2381 .stats_get_strings = mv88e6095_stats_get_strings, 2382 .stats_get_stats = mv88e6095_stats_get_stats, 2383 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2384 .set_egress_port = mv88e6095_g1_set_egress_port, 2385 .watchdog_ops = &mv88e6097_watchdog_ops, 2386 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2387 .ppu_enable = mv88e6185_g1_ppu_enable, 2388 .ppu_disable = mv88e6185_g1_ppu_disable, 2389 .reset = mv88e6185_g1_reset, 2390 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2391 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2392 }; 2393 2394 static const struct mv88e6xxx_ops mv88e6141_ops = { 2395 /* MV88E6XXX_FAMILY_6341 */ 2396 .irl_init_all = mv88e6352_g2_irl_init_all, 2397 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2398 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2399 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2400 .phy_read = mv88e6xxx_g2_smi_phy_read, 2401 .phy_write = mv88e6xxx_g2_smi_phy_write, 2402 .port_set_link = mv88e6xxx_port_set_link, 2403 .port_set_duplex = mv88e6xxx_port_set_duplex, 2404 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2405 .port_set_speed = mv88e6390_port_set_speed, 2406 .port_tag_remap = mv88e6095_port_tag_remap, 2407 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2408 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2409 .port_set_ether_type = mv88e6351_port_set_ether_type, 2410 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2411 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2412 .port_pause_limit = mv88e6097_port_pause_limit, 2413 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2414 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2415 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2416 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2417 .stats_get_strings = mv88e6320_stats_get_strings, 2418 .stats_get_stats = mv88e6390_stats_get_stats, 2419 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2420 .set_egress_port = mv88e6390_g1_set_egress_port, 2421 .watchdog_ops = &mv88e6390_watchdog_ops, 2422 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2423 .pot_clear = mv88e6xxx_g2_pot_clear, 2424 .reset = mv88e6352_g1_reset, 2425 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2426 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2427 }; 2428 2429 static const struct mv88e6xxx_ops mv88e6161_ops = { 2430 /* MV88E6XXX_FAMILY_6165 */ 2431 .irl_init_all = mv88e6352_g2_irl_init_all, 2432 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2433 .phy_read = mv88e6xxx_g2_smi_phy_read, 2434 .phy_write = mv88e6xxx_g2_smi_phy_write, 2435 .port_set_link = mv88e6xxx_port_set_link, 2436 .port_set_duplex = mv88e6xxx_port_set_duplex, 2437 .port_set_speed = mv88e6185_port_set_speed, 2438 .port_tag_remap = mv88e6095_port_tag_remap, 2439 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2440 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2441 .port_set_ether_type = mv88e6351_port_set_ether_type, 2442 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2443 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2444 .port_pause_limit = mv88e6097_port_pause_limit, 2445 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2446 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2447 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2448 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2449 .stats_get_strings = mv88e6095_stats_get_strings, 2450 .stats_get_stats = mv88e6095_stats_get_stats, 2451 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2452 .set_egress_port = mv88e6095_g1_set_egress_port, 2453 .watchdog_ops = &mv88e6097_watchdog_ops, 2454 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2455 .pot_clear = mv88e6xxx_g2_pot_clear, 2456 .reset = mv88e6352_g1_reset, 2457 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2458 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2459 }; 2460 2461 static const struct mv88e6xxx_ops mv88e6165_ops = { 2462 /* MV88E6XXX_FAMILY_6165 */ 2463 .irl_init_all = mv88e6352_g2_irl_init_all, 2464 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2465 .phy_read = mv88e6165_phy_read, 2466 .phy_write = mv88e6165_phy_write, 2467 .port_set_link = mv88e6xxx_port_set_link, 2468 .port_set_duplex = mv88e6xxx_port_set_duplex, 2469 .port_set_speed = mv88e6185_port_set_speed, 2470 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2471 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2472 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2473 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2474 .stats_get_strings = mv88e6095_stats_get_strings, 2475 .stats_get_stats = mv88e6095_stats_get_stats, 2476 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2477 .set_egress_port = mv88e6095_g1_set_egress_port, 2478 .watchdog_ops = &mv88e6097_watchdog_ops, 2479 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2480 .pot_clear = mv88e6xxx_g2_pot_clear, 2481 .reset = mv88e6352_g1_reset, 2482 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2483 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2484 }; 2485 2486 static const struct mv88e6xxx_ops mv88e6171_ops = { 2487 /* MV88E6XXX_FAMILY_6351 */ 2488 .irl_init_all = mv88e6352_g2_irl_init_all, 2489 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2490 .phy_read = mv88e6xxx_g2_smi_phy_read, 2491 .phy_write = mv88e6xxx_g2_smi_phy_write, 2492 .port_set_link = mv88e6xxx_port_set_link, 2493 .port_set_duplex = mv88e6xxx_port_set_duplex, 2494 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2495 .port_set_speed = mv88e6185_port_set_speed, 2496 .port_tag_remap = mv88e6095_port_tag_remap, 2497 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2498 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2499 .port_set_ether_type = mv88e6351_port_set_ether_type, 2500 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2501 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2502 .port_pause_limit = mv88e6097_port_pause_limit, 2503 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2504 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2505 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2506 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2507 .stats_get_strings = mv88e6095_stats_get_strings, 2508 .stats_get_stats = mv88e6095_stats_get_stats, 2509 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2510 .set_egress_port = mv88e6095_g1_set_egress_port, 2511 .watchdog_ops = &mv88e6097_watchdog_ops, 2512 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2513 .pot_clear = mv88e6xxx_g2_pot_clear, 2514 .reset = mv88e6352_g1_reset, 2515 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2516 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2517 }; 2518 2519 static const struct mv88e6xxx_ops mv88e6172_ops = { 2520 /* MV88E6XXX_FAMILY_6352 */ 2521 .irl_init_all = mv88e6352_g2_irl_init_all, 2522 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2523 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2524 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2525 .phy_read = mv88e6xxx_g2_smi_phy_read, 2526 .phy_write = mv88e6xxx_g2_smi_phy_write, 2527 .port_set_link = mv88e6xxx_port_set_link, 2528 .port_set_duplex = mv88e6xxx_port_set_duplex, 2529 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2530 .port_set_speed = mv88e6352_port_set_speed, 2531 .port_tag_remap = mv88e6095_port_tag_remap, 2532 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2533 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2534 .port_set_ether_type = mv88e6351_port_set_ether_type, 2535 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2536 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2537 .port_pause_limit = mv88e6097_port_pause_limit, 2538 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2539 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2540 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2541 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2542 .stats_get_strings = mv88e6095_stats_get_strings, 2543 .stats_get_stats = mv88e6095_stats_get_stats, 2544 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2545 .set_egress_port = mv88e6095_g1_set_egress_port, 2546 .watchdog_ops = &mv88e6097_watchdog_ops, 2547 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2548 .pot_clear = mv88e6xxx_g2_pot_clear, 2549 .reset = mv88e6352_g1_reset, 2550 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2551 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2552 .serdes_power = mv88e6352_serdes_power, 2553 }; 2554 2555 static const struct mv88e6xxx_ops mv88e6175_ops = { 2556 /* MV88E6XXX_FAMILY_6351 */ 2557 .irl_init_all = mv88e6352_g2_irl_init_all, 2558 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2559 .phy_read = mv88e6xxx_g2_smi_phy_read, 2560 .phy_write = mv88e6xxx_g2_smi_phy_write, 2561 .port_set_link = mv88e6xxx_port_set_link, 2562 .port_set_duplex = mv88e6xxx_port_set_duplex, 2563 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2564 .port_set_speed = mv88e6185_port_set_speed, 2565 .port_tag_remap = mv88e6095_port_tag_remap, 2566 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2567 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2568 .port_set_ether_type = mv88e6351_port_set_ether_type, 2569 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2570 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2571 .port_pause_limit = mv88e6097_port_pause_limit, 2572 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2573 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2574 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2575 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2576 .stats_get_strings = mv88e6095_stats_get_strings, 2577 .stats_get_stats = mv88e6095_stats_get_stats, 2578 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2579 .set_egress_port = mv88e6095_g1_set_egress_port, 2580 .watchdog_ops = &mv88e6097_watchdog_ops, 2581 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2582 .pot_clear = mv88e6xxx_g2_pot_clear, 2583 .reset = mv88e6352_g1_reset, 2584 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2585 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2586 }; 2587 2588 static const struct mv88e6xxx_ops mv88e6176_ops = { 2589 /* MV88E6XXX_FAMILY_6352 */ 2590 .irl_init_all = mv88e6352_g2_irl_init_all, 2591 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2592 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2593 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2594 .phy_read = mv88e6xxx_g2_smi_phy_read, 2595 .phy_write = mv88e6xxx_g2_smi_phy_write, 2596 .port_set_link = mv88e6xxx_port_set_link, 2597 .port_set_duplex = mv88e6xxx_port_set_duplex, 2598 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2599 .port_set_speed = mv88e6352_port_set_speed, 2600 .port_tag_remap = mv88e6095_port_tag_remap, 2601 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2602 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2603 .port_set_ether_type = mv88e6351_port_set_ether_type, 2604 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2605 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2606 .port_pause_limit = mv88e6097_port_pause_limit, 2607 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2608 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2609 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2610 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2611 .stats_get_strings = mv88e6095_stats_get_strings, 2612 .stats_get_stats = mv88e6095_stats_get_stats, 2613 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2614 .set_egress_port = mv88e6095_g1_set_egress_port, 2615 .watchdog_ops = &mv88e6097_watchdog_ops, 2616 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2617 .pot_clear = mv88e6xxx_g2_pot_clear, 2618 .reset = mv88e6352_g1_reset, 2619 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2620 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2621 .serdes_power = mv88e6352_serdes_power, 2622 }; 2623 2624 static const struct mv88e6xxx_ops mv88e6185_ops = { 2625 /* MV88E6XXX_FAMILY_6185 */ 2626 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2627 .phy_read = mv88e6185_phy_ppu_read, 2628 .phy_write = mv88e6185_phy_ppu_write, 2629 .port_set_link = mv88e6xxx_port_set_link, 2630 .port_set_duplex = mv88e6xxx_port_set_duplex, 2631 .port_set_speed = mv88e6185_port_set_speed, 2632 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2633 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2634 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2635 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2636 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2637 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2638 .stats_get_strings = mv88e6095_stats_get_strings, 2639 .stats_get_stats = mv88e6095_stats_get_stats, 2640 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2641 .set_egress_port = mv88e6095_g1_set_egress_port, 2642 .watchdog_ops = &mv88e6097_watchdog_ops, 2643 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2644 .ppu_enable = mv88e6185_g1_ppu_enable, 2645 .ppu_disable = mv88e6185_g1_ppu_disable, 2646 .reset = mv88e6185_g1_reset, 2647 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2648 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2649 }; 2650 2651 static const struct mv88e6xxx_ops mv88e6190_ops = { 2652 /* MV88E6XXX_FAMILY_6390 */ 2653 .irl_init_all = mv88e6390_g2_irl_init_all, 2654 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2655 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2656 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2657 .phy_read = mv88e6xxx_g2_smi_phy_read, 2658 .phy_write = mv88e6xxx_g2_smi_phy_write, 2659 .port_set_link = mv88e6xxx_port_set_link, 2660 .port_set_duplex = mv88e6xxx_port_set_duplex, 2661 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2662 .port_set_speed = mv88e6390_port_set_speed, 2663 .port_tag_remap = mv88e6390_port_tag_remap, 2664 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2665 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2666 .port_set_ether_type = mv88e6351_port_set_ether_type, 2667 .port_pause_limit = mv88e6390_port_pause_limit, 2668 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2669 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2670 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2671 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2672 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2673 .stats_get_strings = mv88e6320_stats_get_strings, 2674 .stats_get_stats = mv88e6390_stats_get_stats, 2675 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2676 .set_egress_port = mv88e6390_g1_set_egress_port, 2677 .watchdog_ops = &mv88e6390_watchdog_ops, 2678 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2679 .pot_clear = mv88e6xxx_g2_pot_clear, 2680 .reset = mv88e6352_g1_reset, 2681 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2682 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2683 .serdes_power = mv88e6390_serdes_power, 2684 }; 2685 2686 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2687 /* MV88E6XXX_FAMILY_6390 */ 2688 .irl_init_all = mv88e6390_g2_irl_init_all, 2689 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2690 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2691 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2692 .phy_read = mv88e6xxx_g2_smi_phy_read, 2693 .phy_write = mv88e6xxx_g2_smi_phy_write, 2694 .port_set_link = mv88e6xxx_port_set_link, 2695 .port_set_duplex = mv88e6xxx_port_set_duplex, 2696 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2697 .port_set_speed = mv88e6390x_port_set_speed, 2698 .port_tag_remap = mv88e6390_port_tag_remap, 2699 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2700 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2701 .port_set_ether_type = mv88e6351_port_set_ether_type, 2702 .port_pause_limit = mv88e6390_port_pause_limit, 2703 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2704 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2705 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2706 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2707 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2708 .stats_get_strings = mv88e6320_stats_get_strings, 2709 .stats_get_stats = mv88e6390_stats_get_stats, 2710 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2711 .set_egress_port = mv88e6390_g1_set_egress_port, 2712 .watchdog_ops = &mv88e6390_watchdog_ops, 2713 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2714 .pot_clear = mv88e6xxx_g2_pot_clear, 2715 .reset = mv88e6352_g1_reset, 2716 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2717 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2718 .serdes_power = mv88e6390_serdes_power, 2719 }; 2720 2721 static const struct mv88e6xxx_ops mv88e6191_ops = { 2722 /* MV88E6XXX_FAMILY_6390 */ 2723 .irl_init_all = mv88e6390_g2_irl_init_all, 2724 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2725 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2726 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2727 .phy_read = mv88e6xxx_g2_smi_phy_read, 2728 .phy_write = mv88e6xxx_g2_smi_phy_write, 2729 .port_set_link = mv88e6xxx_port_set_link, 2730 .port_set_duplex = mv88e6xxx_port_set_duplex, 2731 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2732 .port_set_speed = mv88e6390_port_set_speed, 2733 .port_tag_remap = mv88e6390_port_tag_remap, 2734 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2735 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2736 .port_set_ether_type = mv88e6351_port_set_ether_type, 2737 .port_pause_limit = mv88e6390_port_pause_limit, 2738 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2739 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2740 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2741 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2742 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2743 .stats_get_strings = mv88e6320_stats_get_strings, 2744 .stats_get_stats = mv88e6390_stats_get_stats, 2745 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2746 .set_egress_port = mv88e6390_g1_set_egress_port, 2747 .watchdog_ops = &mv88e6390_watchdog_ops, 2748 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2749 .pot_clear = mv88e6xxx_g2_pot_clear, 2750 .reset = mv88e6352_g1_reset, 2751 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2752 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2753 .serdes_power = mv88e6390_serdes_power, 2754 }; 2755 2756 static const struct mv88e6xxx_ops mv88e6240_ops = { 2757 /* MV88E6XXX_FAMILY_6352 */ 2758 .irl_init_all = mv88e6352_g2_irl_init_all, 2759 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2760 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2761 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2762 .phy_read = mv88e6xxx_g2_smi_phy_read, 2763 .phy_write = mv88e6xxx_g2_smi_phy_write, 2764 .port_set_link = mv88e6xxx_port_set_link, 2765 .port_set_duplex = mv88e6xxx_port_set_duplex, 2766 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2767 .port_set_speed = mv88e6352_port_set_speed, 2768 .port_tag_remap = mv88e6095_port_tag_remap, 2769 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2770 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2771 .port_set_ether_type = mv88e6351_port_set_ether_type, 2772 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2773 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2774 .port_pause_limit = mv88e6097_port_pause_limit, 2775 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2776 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2777 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2778 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2779 .stats_get_strings = mv88e6095_stats_get_strings, 2780 .stats_get_stats = mv88e6095_stats_get_stats, 2781 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2782 .set_egress_port = mv88e6095_g1_set_egress_port, 2783 .watchdog_ops = &mv88e6097_watchdog_ops, 2784 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2785 .pot_clear = mv88e6xxx_g2_pot_clear, 2786 .reset = mv88e6352_g1_reset, 2787 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2788 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2789 .serdes_power = mv88e6352_serdes_power, 2790 }; 2791 2792 static const struct mv88e6xxx_ops mv88e6290_ops = { 2793 /* MV88E6XXX_FAMILY_6390 */ 2794 .irl_init_all = mv88e6390_g2_irl_init_all, 2795 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2796 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2797 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2798 .phy_read = mv88e6xxx_g2_smi_phy_read, 2799 .phy_write = mv88e6xxx_g2_smi_phy_write, 2800 .port_set_link = mv88e6xxx_port_set_link, 2801 .port_set_duplex = mv88e6xxx_port_set_duplex, 2802 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2803 .port_set_speed = mv88e6390_port_set_speed, 2804 .port_tag_remap = mv88e6390_port_tag_remap, 2805 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2806 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2807 .port_set_ether_type = mv88e6351_port_set_ether_type, 2808 .port_pause_limit = mv88e6390_port_pause_limit, 2809 .port_set_cmode = mv88e6390x_port_set_cmode, 2810 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2811 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2812 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2813 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2814 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2815 .stats_get_strings = mv88e6320_stats_get_strings, 2816 .stats_get_stats = mv88e6390_stats_get_stats, 2817 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2818 .set_egress_port = mv88e6390_g1_set_egress_port, 2819 .watchdog_ops = &mv88e6390_watchdog_ops, 2820 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2821 .pot_clear = mv88e6xxx_g2_pot_clear, 2822 .reset = mv88e6352_g1_reset, 2823 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2824 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2825 .serdes_power = mv88e6390_serdes_power, 2826 }; 2827 2828 static const struct mv88e6xxx_ops mv88e6320_ops = { 2829 /* MV88E6XXX_FAMILY_6320 */ 2830 .irl_init_all = mv88e6352_g2_irl_init_all, 2831 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2832 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2833 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2834 .phy_read = mv88e6xxx_g2_smi_phy_read, 2835 .phy_write = mv88e6xxx_g2_smi_phy_write, 2836 .port_set_link = mv88e6xxx_port_set_link, 2837 .port_set_duplex = mv88e6xxx_port_set_duplex, 2838 .port_set_speed = mv88e6185_port_set_speed, 2839 .port_tag_remap = mv88e6095_port_tag_remap, 2840 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2841 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2842 .port_set_ether_type = mv88e6351_port_set_ether_type, 2843 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2844 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2845 .port_pause_limit = mv88e6097_port_pause_limit, 2846 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2847 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2848 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2849 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2850 .stats_get_strings = mv88e6320_stats_get_strings, 2851 .stats_get_stats = mv88e6320_stats_get_stats, 2852 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2853 .set_egress_port = mv88e6095_g1_set_egress_port, 2854 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2855 .pot_clear = mv88e6xxx_g2_pot_clear, 2856 .reset = mv88e6352_g1_reset, 2857 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2858 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2859 }; 2860 2861 static const struct mv88e6xxx_ops mv88e6321_ops = { 2862 /* MV88E6XXX_FAMILY_6320 */ 2863 .irl_init_all = mv88e6352_g2_irl_init_all, 2864 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2865 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2866 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2867 .phy_read = mv88e6xxx_g2_smi_phy_read, 2868 .phy_write = mv88e6xxx_g2_smi_phy_write, 2869 .port_set_link = mv88e6xxx_port_set_link, 2870 .port_set_duplex = mv88e6xxx_port_set_duplex, 2871 .port_set_speed = mv88e6185_port_set_speed, 2872 .port_tag_remap = mv88e6095_port_tag_remap, 2873 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2874 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2875 .port_set_ether_type = mv88e6351_port_set_ether_type, 2876 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2877 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2878 .port_pause_limit = mv88e6097_port_pause_limit, 2879 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2880 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2881 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2882 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2883 .stats_get_strings = mv88e6320_stats_get_strings, 2884 .stats_get_stats = mv88e6320_stats_get_stats, 2885 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2886 .set_egress_port = mv88e6095_g1_set_egress_port, 2887 .reset = mv88e6352_g1_reset, 2888 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2889 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2890 }; 2891 2892 static const struct mv88e6xxx_ops mv88e6341_ops = { 2893 /* MV88E6XXX_FAMILY_6341 */ 2894 .irl_init_all = mv88e6352_g2_irl_init_all, 2895 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2896 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2897 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2898 .phy_read = mv88e6xxx_g2_smi_phy_read, 2899 .phy_write = mv88e6xxx_g2_smi_phy_write, 2900 .port_set_link = mv88e6xxx_port_set_link, 2901 .port_set_duplex = mv88e6xxx_port_set_duplex, 2902 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2903 .port_set_speed = mv88e6390_port_set_speed, 2904 .port_tag_remap = mv88e6095_port_tag_remap, 2905 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2906 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2907 .port_set_ether_type = mv88e6351_port_set_ether_type, 2908 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2909 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2910 .port_pause_limit = mv88e6097_port_pause_limit, 2911 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2912 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2913 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2914 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2915 .stats_get_strings = mv88e6320_stats_get_strings, 2916 .stats_get_stats = mv88e6390_stats_get_stats, 2917 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2918 .set_egress_port = mv88e6390_g1_set_egress_port, 2919 .watchdog_ops = &mv88e6390_watchdog_ops, 2920 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2921 .pot_clear = mv88e6xxx_g2_pot_clear, 2922 .reset = mv88e6352_g1_reset, 2923 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2924 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2925 }; 2926 2927 static const struct mv88e6xxx_ops mv88e6350_ops = { 2928 /* MV88E6XXX_FAMILY_6351 */ 2929 .irl_init_all = mv88e6352_g2_irl_init_all, 2930 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2931 .phy_read = mv88e6xxx_g2_smi_phy_read, 2932 .phy_write = mv88e6xxx_g2_smi_phy_write, 2933 .port_set_link = mv88e6xxx_port_set_link, 2934 .port_set_duplex = mv88e6xxx_port_set_duplex, 2935 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2936 .port_set_speed = mv88e6185_port_set_speed, 2937 .port_tag_remap = mv88e6095_port_tag_remap, 2938 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2939 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2940 .port_set_ether_type = mv88e6351_port_set_ether_type, 2941 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2942 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2943 .port_pause_limit = mv88e6097_port_pause_limit, 2944 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2945 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2946 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2947 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2948 .stats_get_strings = mv88e6095_stats_get_strings, 2949 .stats_get_stats = mv88e6095_stats_get_stats, 2950 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2951 .set_egress_port = mv88e6095_g1_set_egress_port, 2952 .watchdog_ops = &mv88e6097_watchdog_ops, 2953 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2954 .pot_clear = mv88e6xxx_g2_pot_clear, 2955 .reset = mv88e6352_g1_reset, 2956 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2957 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2958 }; 2959 2960 static const struct mv88e6xxx_ops mv88e6351_ops = { 2961 /* MV88E6XXX_FAMILY_6351 */ 2962 .irl_init_all = mv88e6352_g2_irl_init_all, 2963 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2964 .phy_read = mv88e6xxx_g2_smi_phy_read, 2965 .phy_write = mv88e6xxx_g2_smi_phy_write, 2966 .port_set_link = mv88e6xxx_port_set_link, 2967 .port_set_duplex = mv88e6xxx_port_set_duplex, 2968 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2969 .port_set_speed = mv88e6185_port_set_speed, 2970 .port_tag_remap = mv88e6095_port_tag_remap, 2971 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2972 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2973 .port_set_ether_type = mv88e6351_port_set_ether_type, 2974 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2975 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2976 .port_pause_limit = mv88e6097_port_pause_limit, 2977 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2978 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2979 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2980 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2981 .stats_get_strings = mv88e6095_stats_get_strings, 2982 .stats_get_stats = mv88e6095_stats_get_stats, 2983 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2984 .set_egress_port = mv88e6095_g1_set_egress_port, 2985 .watchdog_ops = &mv88e6097_watchdog_ops, 2986 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2987 .pot_clear = mv88e6xxx_g2_pot_clear, 2988 .reset = mv88e6352_g1_reset, 2989 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2990 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2991 }; 2992 2993 static const struct mv88e6xxx_ops mv88e6352_ops = { 2994 /* MV88E6XXX_FAMILY_6352 */ 2995 .irl_init_all = mv88e6352_g2_irl_init_all, 2996 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2997 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2998 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2999 .phy_read = mv88e6xxx_g2_smi_phy_read, 3000 .phy_write = mv88e6xxx_g2_smi_phy_write, 3001 .port_set_link = mv88e6xxx_port_set_link, 3002 .port_set_duplex = mv88e6xxx_port_set_duplex, 3003 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3004 .port_set_speed = mv88e6352_port_set_speed, 3005 .port_tag_remap = mv88e6095_port_tag_remap, 3006 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3007 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3008 .port_set_ether_type = mv88e6351_port_set_ether_type, 3009 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3010 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3011 .port_pause_limit = mv88e6097_port_pause_limit, 3012 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3013 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3014 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3015 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3016 .stats_get_strings = mv88e6095_stats_get_strings, 3017 .stats_get_stats = mv88e6095_stats_get_stats, 3018 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3019 .set_egress_port = mv88e6095_g1_set_egress_port, 3020 .watchdog_ops = &mv88e6097_watchdog_ops, 3021 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3022 .pot_clear = mv88e6xxx_g2_pot_clear, 3023 .reset = mv88e6352_g1_reset, 3024 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3025 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3026 .serdes_power = mv88e6352_serdes_power, 3027 }; 3028 3029 static const struct mv88e6xxx_ops mv88e6390_ops = { 3030 /* MV88E6XXX_FAMILY_6390 */ 3031 .irl_init_all = mv88e6390_g2_irl_init_all, 3032 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3033 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3034 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3035 .phy_read = mv88e6xxx_g2_smi_phy_read, 3036 .phy_write = mv88e6xxx_g2_smi_phy_write, 3037 .port_set_link = mv88e6xxx_port_set_link, 3038 .port_set_duplex = mv88e6xxx_port_set_duplex, 3039 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3040 .port_set_speed = mv88e6390_port_set_speed, 3041 .port_tag_remap = mv88e6390_port_tag_remap, 3042 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3043 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3044 .port_set_ether_type = mv88e6351_port_set_ether_type, 3045 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3046 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3047 .port_pause_limit = mv88e6390_port_pause_limit, 3048 .port_set_cmode = mv88e6390x_port_set_cmode, 3049 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3050 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3051 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3052 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3053 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3054 .stats_get_strings = mv88e6320_stats_get_strings, 3055 .stats_get_stats = mv88e6390_stats_get_stats, 3056 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3057 .set_egress_port = mv88e6390_g1_set_egress_port, 3058 .watchdog_ops = &mv88e6390_watchdog_ops, 3059 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3060 .pot_clear = mv88e6xxx_g2_pot_clear, 3061 .reset = mv88e6352_g1_reset, 3062 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3063 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3064 .serdes_power = mv88e6390_serdes_power, 3065 }; 3066 3067 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3068 /* MV88E6XXX_FAMILY_6390 */ 3069 .irl_init_all = mv88e6390_g2_irl_init_all, 3070 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3071 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3072 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3073 .phy_read = mv88e6xxx_g2_smi_phy_read, 3074 .phy_write = mv88e6xxx_g2_smi_phy_write, 3075 .port_set_link = mv88e6xxx_port_set_link, 3076 .port_set_duplex = mv88e6xxx_port_set_duplex, 3077 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3078 .port_set_speed = mv88e6390x_port_set_speed, 3079 .port_tag_remap = mv88e6390_port_tag_remap, 3080 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3081 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3082 .port_set_ether_type = mv88e6351_port_set_ether_type, 3083 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3084 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3085 .port_pause_limit = mv88e6390_port_pause_limit, 3086 .port_set_cmode = mv88e6390x_port_set_cmode, 3087 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3088 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3089 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3090 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3091 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3092 .stats_get_strings = mv88e6320_stats_get_strings, 3093 .stats_get_stats = mv88e6390_stats_get_stats, 3094 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3095 .set_egress_port = mv88e6390_g1_set_egress_port, 3096 .watchdog_ops = &mv88e6390_watchdog_ops, 3097 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3098 .pot_clear = mv88e6xxx_g2_pot_clear, 3099 .reset = mv88e6352_g1_reset, 3100 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3101 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3102 .serdes_power = mv88e6390_serdes_power, 3103 }; 3104 3105 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3106 [MV88E6085] = { 3107 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3108 .family = MV88E6XXX_FAMILY_6097, 3109 .name = "Marvell 88E6085", 3110 .num_databases = 4096, 3111 .num_ports = 10, 3112 .max_vid = 4095, 3113 .port_base_addr = 0x10, 3114 .global1_addr = 0x1b, 3115 .global2_addr = 0x1c, 3116 .age_time_coeff = 15000, 3117 .g1_irqs = 8, 3118 .g2_irqs = 10, 3119 .atu_move_port_mask = 0xf, 3120 .pvt = true, 3121 .multi_chip = true, 3122 .tag_protocol = DSA_TAG_PROTO_DSA, 3123 .ops = &mv88e6085_ops, 3124 }, 3125 3126 [MV88E6095] = { 3127 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3128 .family = MV88E6XXX_FAMILY_6095, 3129 .name = "Marvell 88E6095/88E6095F", 3130 .num_databases = 256, 3131 .num_ports = 11, 3132 .max_vid = 4095, 3133 .port_base_addr = 0x10, 3134 .global1_addr = 0x1b, 3135 .global2_addr = 0x1c, 3136 .age_time_coeff = 15000, 3137 .g1_irqs = 8, 3138 .atu_move_port_mask = 0xf, 3139 .multi_chip = true, 3140 .tag_protocol = DSA_TAG_PROTO_DSA, 3141 .ops = &mv88e6095_ops, 3142 }, 3143 3144 [MV88E6097] = { 3145 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3146 .family = MV88E6XXX_FAMILY_6097, 3147 .name = "Marvell 88E6097/88E6097F", 3148 .num_databases = 4096, 3149 .num_ports = 11, 3150 .max_vid = 4095, 3151 .port_base_addr = 0x10, 3152 .global1_addr = 0x1b, 3153 .global2_addr = 0x1c, 3154 .age_time_coeff = 15000, 3155 .g1_irqs = 8, 3156 .g2_irqs = 10, 3157 .atu_move_port_mask = 0xf, 3158 .pvt = true, 3159 .multi_chip = true, 3160 .tag_protocol = DSA_TAG_PROTO_EDSA, 3161 .ops = &mv88e6097_ops, 3162 }, 3163 3164 [MV88E6123] = { 3165 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3166 .family = MV88E6XXX_FAMILY_6165, 3167 .name = "Marvell 88E6123", 3168 .num_databases = 4096, 3169 .num_ports = 3, 3170 .max_vid = 4095, 3171 .port_base_addr = 0x10, 3172 .global1_addr = 0x1b, 3173 .global2_addr = 0x1c, 3174 .age_time_coeff = 15000, 3175 .g1_irqs = 9, 3176 .g2_irqs = 10, 3177 .atu_move_port_mask = 0xf, 3178 .pvt = true, 3179 .multi_chip = true, 3180 .tag_protocol = DSA_TAG_PROTO_EDSA, 3181 .ops = &mv88e6123_ops, 3182 }, 3183 3184 [MV88E6131] = { 3185 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3186 .family = MV88E6XXX_FAMILY_6185, 3187 .name = "Marvell 88E6131", 3188 .num_databases = 256, 3189 .num_ports = 8, 3190 .max_vid = 4095, 3191 .port_base_addr = 0x10, 3192 .global1_addr = 0x1b, 3193 .global2_addr = 0x1c, 3194 .age_time_coeff = 15000, 3195 .g1_irqs = 9, 3196 .atu_move_port_mask = 0xf, 3197 .multi_chip = true, 3198 .tag_protocol = DSA_TAG_PROTO_DSA, 3199 .ops = &mv88e6131_ops, 3200 }, 3201 3202 [MV88E6141] = { 3203 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3204 .family = MV88E6XXX_FAMILY_6341, 3205 .name = "Marvell 88E6341", 3206 .num_databases = 4096, 3207 .num_ports = 6, 3208 .max_vid = 4095, 3209 .port_base_addr = 0x10, 3210 .global1_addr = 0x1b, 3211 .global2_addr = 0x1c, 3212 .age_time_coeff = 3750, 3213 .atu_move_port_mask = 0x1f, 3214 .g2_irqs = 10, 3215 .pvt = true, 3216 .multi_chip = true, 3217 .tag_protocol = DSA_TAG_PROTO_EDSA, 3218 .ops = &mv88e6141_ops, 3219 }, 3220 3221 [MV88E6161] = { 3222 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3223 .family = MV88E6XXX_FAMILY_6165, 3224 .name = "Marvell 88E6161", 3225 .num_databases = 4096, 3226 .num_ports = 6, 3227 .max_vid = 4095, 3228 .port_base_addr = 0x10, 3229 .global1_addr = 0x1b, 3230 .global2_addr = 0x1c, 3231 .age_time_coeff = 15000, 3232 .g1_irqs = 9, 3233 .g2_irqs = 10, 3234 .atu_move_port_mask = 0xf, 3235 .pvt = true, 3236 .multi_chip = true, 3237 .tag_protocol = DSA_TAG_PROTO_EDSA, 3238 .ops = &mv88e6161_ops, 3239 }, 3240 3241 [MV88E6165] = { 3242 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3243 .family = MV88E6XXX_FAMILY_6165, 3244 .name = "Marvell 88E6165", 3245 .num_databases = 4096, 3246 .num_ports = 6, 3247 .max_vid = 4095, 3248 .port_base_addr = 0x10, 3249 .global1_addr = 0x1b, 3250 .global2_addr = 0x1c, 3251 .age_time_coeff = 15000, 3252 .g1_irqs = 9, 3253 .g2_irqs = 10, 3254 .atu_move_port_mask = 0xf, 3255 .pvt = true, 3256 .multi_chip = true, 3257 .tag_protocol = DSA_TAG_PROTO_DSA, 3258 .ops = &mv88e6165_ops, 3259 }, 3260 3261 [MV88E6171] = { 3262 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3263 .family = MV88E6XXX_FAMILY_6351, 3264 .name = "Marvell 88E6171", 3265 .num_databases = 4096, 3266 .num_ports = 7, 3267 .max_vid = 4095, 3268 .port_base_addr = 0x10, 3269 .global1_addr = 0x1b, 3270 .global2_addr = 0x1c, 3271 .age_time_coeff = 15000, 3272 .g1_irqs = 9, 3273 .g2_irqs = 10, 3274 .atu_move_port_mask = 0xf, 3275 .pvt = true, 3276 .multi_chip = true, 3277 .tag_protocol = DSA_TAG_PROTO_EDSA, 3278 .ops = &mv88e6171_ops, 3279 }, 3280 3281 [MV88E6172] = { 3282 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3283 .family = MV88E6XXX_FAMILY_6352, 3284 .name = "Marvell 88E6172", 3285 .num_databases = 4096, 3286 .num_ports = 7, 3287 .max_vid = 4095, 3288 .port_base_addr = 0x10, 3289 .global1_addr = 0x1b, 3290 .global2_addr = 0x1c, 3291 .age_time_coeff = 15000, 3292 .g1_irqs = 9, 3293 .g2_irqs = 10, 3294 .atu_move_port_mask = 0xf, 3295 .pvt = true, 3296 .multi_chip = true, 3297 .tag_protocol = DSA_TAG_PROTO_EDSA, 3298 .ops = &mv88e6172_ops, 3299 }, 3300 3301 [MV88E6175] = { 3302 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3303 .family = MV88E6XXX_FAMILY_6351, 3304 .name = "Marvell 88E6175", 3305 .num_databases = 4096, 3306 .num_ports = 7, 3307 .max_vid = 4095, 3308 .port_base_addr = 0x10, 3309 .global1_addr = 0x1b, 3310 .global2_addr = 0x1c, 3311 .age_time_coeff = 15000, 3312 .g1_irqs = 9, 3313 .g2_irqs = 10, 3314 .atu_move_port_mask = 0xf, 3315 .pvt = true, 3316 .multi_chip = true, 3317 .tag_protocol = DSA_TAG_PROTO_EDSA, 3318 .ops = &mv88e6175_ops, 3319 }, 3320 3321 [MV88E6176] = { 3322 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3323 .family = MV88E6XXX_FAMILY_6352, 3324 .name = "Marvell 88E6176", 3325 .num_databases = 4096, 3326 .num_ports = 7, 3327 .max_vid = 4095, 3328 .port_base_addr = 0x10, 3329 .global1_addr = 0x1b, 3330 .global2_addr = 0x1c, 3331 .age_time_coeff = 15000, 3332 .g1_irqs = 9, 3333 .g2_irqs = 10, 3334 .atu_move_port_mask = 0xf, 3335 .pvt = true, 3336 .multi_chip = true, 3337 .tag_protocol = DSA_TAG_PROTO_EDSA, 3338 .ops = &mv88e6176_ops, 3339 }, 3340 3341 [MV88E6185] = { 3342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3343 .family = MV88E6XXX_FAMILY_6185, 3344 .name = "Marvell 88E6185", 3345 .num_databases = 256, 3346 .num_ports = 10, 3347 .max_vid = 4095, 3348 .port_base_addr = 0x10, 3349 .global1_addr = 0x1b, 3350 .global2_addr = 0x1c, 3351 .age_time_coeff = 15000, 3352 .g1_irqs = 8, 3353 .atu_move_port_mask = 0xf, 3354 .multi_chip = true, 3355 .tag_protocol = DSA_TAG_PROTO_EDSA, 3356 .ops = &mv88e6185_ops, 3357 }, 3358 3359 [MV88E6190] = { 3360 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3361 .family = MV88E6XXX_FAMILY_6390, 3362 .name = "Marvell 88E6190", 3363 .num_databases = 4096, 3364 .num_ports = 11, /* 10 + Z80 */ 3365 .max_vid = 8191, 3366 .port_base_addr = 0x0, 3367 .global1_addr = 0x1b, 3368 .global2_addr = 0x1c, 3369 .tag_protocol = DSA_TAG_PROTO_DSA, 3370 .age_time_coeff = 3750, 3371 .g1_irqs = 9, 3372 .g2_irqs = 14, 3373 .pvt = true, 3374 .multi_chip = true, 3375 .atu_move_port_mask = 0x1f, 3376 .ops = &mv88e6190_ops, 3377 }, 3378 3379 [MV88E6190X] = { 3380 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3381 .family = MV88E6XXX_FAMILY_6390, 3382 .name = "Marvell 88E6190X", 3383 .num_databases = 4096, 3384 .num_ports = 11, /* 10 + Z80 */ 3385 .max_vid = 8191, 3386 .port_base_addr = 0x0, 3387 .global1_addr = 0x1b, 3388 .global2_addr = 0x1c, 3389 .age_time_coeff = 3750, 3390 .g1_irqs = 9, 3391 .g2_irqs = 14, 3392 .atu_move_port_mask = 0x1f, 3393 .pvt = true, 3394 .multi_chip = true, 3395 .tag_protocol = DSA_TAG_PROTO_DSA, 3396 .ops = &mv88e6190x_ops, 3397 }, 3398 3399 [MV88E6191] = { 3400 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3401 .family = MV88E6XXX_FAMILY_6390, 3402 .name = "Marvell 88E6191", 3403 .num_databases = 4096, 3404 .num_ports = 11, /* 10 + Z80 */ 3405 .max_vid = 8191, 3406 .port_base_addr = 0x0, 3407 .global1_addr = 0x1b, 3408 .global2_addr = 0x1c, 3409 .age_time_coeff = 3750, 3410 .g1_irqs = 9, 3411 .g2_irqs = 14, 3412 .atu_move_port_mask = 0x1f, 3413 .pvt = true, 3414 .multi_chip = true, 3415 .tag_protocol = DSA_TAG_PROTO_DSA, 3416 .ops = &mv88e6191_ops, 3417 }, 3418 3419 [MV88E6240] = { 3420 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3421 .family = MV88E6XXX_FAMILY_6352, 3422 .name = "Marvell 88E6240", 3423 .num_databases = 4096, 3424 .num_ports = 7, 3425 .max_vid = 4095, 3426 .port_base_addr = 0x10, 3427 .global1_addr = 0x1b, 3428 .global2_addr = 0x1c, 3429 .age_time_coeff = 15000, 3430 .g1_irqs = 9, 3431 .g2_irqs = 10, 3432 .atu_move_port_mask = 0xf, 3433 .pvt = true, 3434 .multi_chip = true, 3435 .tag_protocol = DSA_TAG_PROTO_EDSA, 3436 .ops = &mv88e6240_ops, 3437 }, 3438 3439 [MV88E6290] = { 3440 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3441 .family = MV88E6XXX_FAMILY_6390, 3442 .name = "Marvell 88E6290", 3443 .num_databases = 4096, 3444 .num_ports = 11, /* 10 + Z80 */ 3445 .max_vid = 8191, 3446 .port_base_addr = 0x0, 3447 .global1_addr = 0x1b, 3448 .global2_addr = 0x1c, 3449 .age_time_coeff = 3750, 3450 .g1_irqs = 9, 3451 .g2_irqs = 14, 3452 .atu_move_port_mask = 0x1f, 3453 .pvt = true, 3454 .multi_chip = true, 3455 .tag_protocol = DSA_TAG_PROTO_DSA, 3456 .ops = &mv88e6290_ops, 3457 }, 3458 3459 [MV88E6320] = { 3460 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3461 .family = MV88E6XXX_FAMILY_6320, 3462 .name = "Marvell 88E6320", 3463 .num_databases = 4096, 3464 .num_ports = 7, 3465 .max_vid = 4095, 3466 .port_base_addr = 0x10, 3467 .global1_addr = 0x1b, 3468 .global2_addr = 0x1c, 3469 .age_time_coeff = 15000, 3470 .g1_irqs = 8, 3471 .atu_move_port_mask = 0xf, 3472 .pvt = true, 3473 .multi_chip = true, 3474 .tag_protocol = DSA_TAG_PROTO_EDSA, 3475 .ops = &mv88e6320_ops, 3476 }, 3477 3478 [MV88E6321] = { 3479 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3480 .family = MV88E6XXX_FAMILY_6320, 3481 .name = "Marvell 88E6321", 3482 .num_databases = 4096, 3483 .num_ports = 7, 3484 .max_vid = 4095, 3485 .port_base_addr = 0x10, 3486 .global1_addr = 0x1b, 3487 .global2_addr = 0x1c, 3488 .age_time_coeff = 15000, 3489 .g1_irqs = 8, 3490 .atu_move_port_mask = 0xf, 3491 .multi_chip = true, 3492 .tag_protocol = DSA_TAG_PROTO_EDSA, 3493 .ops = &mv88e6321_ops, 3494 }, 3495 3496 [MV88E6341] = { 3497 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3498 .family = MV88E6XXX_FAMILY_6341, 3499 .name = "Marvell 88E6341", 3500 .num_databases = 4096, 3501 .num_ports = 6, 3502 .max_vid = 4095, 3503 .port_base_addr = 0x10, 3504 .global1_addr = 0x1b, 3505 .global2_addr = 0x1c, 3506 .age_time_coeff = 3750, 3507 .atu_move_port_mask = 0x1f, 3508 .g2_irqs = 10, 3509 .pvt = true, 3510 .multi_chip = true, 3511 .tag_protocol = DSA_TAG_PROTO_EDSA, 3512 .ops = &mv88e6341_ops, 3513 }, 3514 3515 [MV88E6350] = { 3516 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3517 .family = MV88E6XXX_FAMILY_6351, 3518 .name = "Marvell 88E6350", 3519 .num_databases = 4096, 3520 .num_ports = 7, 3521 .max_vid = 4095, 3522 .port_base_addr = 0x10, 3523 .global1_addr = 0x1b, 3524 .global2_addr = 0x1c, 3525 .age_time_coeff = 15000, 3526 .g1_irqs = 9, 3527 .g2_irqs = 10, 3528 .atu_move_port_mask = 0xf, 3529 .pvt = true, 3530 .multi_chip = true, 3531 .tag_protocol = DSA_TAG_PROTO_EDSA, 3532 .ops = &mv88e6350_ops, 3533 }, 3534 3535 [MV88E6351] = { 3536 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3537 .family = MV88E6XXX_FAMILY_6351, 3538 .name = "Marvell 88E6351", 3539 .num_databases = 4096, 3540 .num_ports = 7, 3541 .max_vid = 4095, 3542 .port_base_addr = 0x10, 3543 .global1_addr = 0x1b, 3544 .global2_addr = 0x1c, 3545 .age_time_coeff = 15000, 3546 .g1_irqs = 9, 3547 .g2_irqs = 10, 3548 .atu_move_port_mask = 0xf, 3549 .pvt = true, 3550 .multi_chip = true, 3551 .tag_protocol = DSA_TAG_PROTO_EDSA, 3552 .ops = &mv88e6351_ops, 3553 }, 3554 3555 [MV88E6352] = { 3556 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3557 .family = MV88E6XXX_FAMILY_6352, 3558 .name = "Marvell 88E6352", 3559 .num_databases = 4096, 3560 .num_ports = 7, 3561 .max_vid = 4095, 3562 .port_base_addr = 0x10, 3563 .global1_addr = 0x1b, 3564 .global2_addr = 0x1c, 3565 .age_time_coeff = 15000, 3566 .g1_irqs = 9, 3567 .g2_irqs = 10, 3568 .atu_move_port_mask = 0xf, 3569 .pvt = true, 3570 .multi_chip = true, 3571 .tag_protocol = DSA_TAG_PROTO_EDSA, 3572 .ops = &mv88e6352_ops, 3573 }, 3574 [MV88E6390] = { 3575 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3576 .family = MV88E6XXX_FAMILY_6390, 3577 .name = "Marvell 88E6390", 3578 .num_databases = 4096, 3579 .num_ports = 11, /* 10 + Z80 */ 3580 .max_vid = 8191, 3581 .port_base_addr = 0x0, 3582 .global1_addr = 0x1b, 3583 .global2_addr = 0x1c, 3584 .age_time_coeff = 3750, 3585 .g1_irqs = 9, 3586 .g2_irqs = 14, 3587 .atu_move_port_mask = 0x1f, 3588 .pvt = true, 3589 .multi_chip = true, 3590 .tag_protocol = DSA_TAG_PROTO_DSA, 3591 .ops = &mv88e6390_ops, 3592 }, 3593 [MV88E6390X] = { 3594 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3595 .family = MV88E6XXX_FAMILY_6390, 3596 .name = "Marvell 88E6390X", 3597 .num_databases = 4096, 3598 .num_ports = 11, /* 10 + Z80 */ 3599 .max_vid = 8191, 3600 .port_base_addr = 0x0, 3601 .global1_addr = 0x1b, 3602 .global2_addr = 0x1c, 3603 .age_time_coeff = 3750, 3604 .g1_irqs = 9, 3605 .g2_irqs = 14, 3606 .atu_move_port_mask = 0x1f, 3607 .pvt = true, 3608 .multi_chip = true, 3609 .tag_protocol = DSA_TAG_PROTO_DSA, 3610 .ops = &mv88e6390x_ops, 3611 }, 3612 }; 3613 3614 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3615 { 3616 int i; 3617 3618 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3619 if (mv88e6xxx_table[i].prod_num == prod_num) 3620 return &mv88e6xxx_table[i]; 3621 3622 return NULL; 3623 } 3624 3625 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3626 { 3627 const struct mv88e6xxx_info *info; 3628 unsigned int prod_num, rev; 3629 u16 id; 3630 int err; 3631 3632 mutex_lock(&chip->reg_lock); 3633 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3634 mutex_unlock(&chip->reg_lock); 3635 if (err) 3636 return err; 3637 3638 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3639 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3640 3641 info = mv88e6xxx_lookup_info(prod_num); 3642 if (!info) 3643 return -ENODEV; 3644 3645 /* Update the compatible info with the probed one */ 3646 chip->info = info; 3647 3648 err = mv88e6xxx_g2_require(chip); 3649 if (err) 3650 return err; 3651 3652 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3653 chip->info->prod_num, chip->info->name, rev); 3654 3655 return 0; 3656 } 3657 3658 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3659 { 3660 struct mv88e6xxx_chip *chip; 3661 3662 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3663 if (!chip) 3664 return NULL; 3665 3666 chip->dev = dev; 3667 3668 mutex_init(&chip->reg_lock); 3669 INIT_LIST_HEAD(&chip->mdios); 3670 3671 return chip; 3672 } 3673 3674 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3675 struct mii_bus *bus, int sw_addr) 3676 { 3677 if (sw_addr == 0) 3678 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3679 else if (chip->info->multi_chip) 3680 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3681 else 3682 return -EINVAL; 3683 3684 chip->bus = bus; 3685 chip->sw_addr = sw_addr; 3686 3687 return 0; 3688 } 3689 3690 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 3691 { 3692 struct mv88e6xxx_chip *chip = ds->priv; 3693 3694 return chip->info->tag_protocol; 3695 } 3696 3697 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3698 struct device *host_dev, int sw_addr, 3699 void **priv) 3700 { 3701 struct mv88e6xxx_chip *chip; 3702 struct mii_bus *bus; 3703 int err; 3704 3705 bus = dsa_host_dev_to_mii_bus(host_dev); 3706 if (!bus) 3707 return NULL; 3708 3709 chip = mv88e6xxx_alloc_chip(dsa_dev); 3710 if (!chip) 3711 return NULL; 3712 3713 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3714 chip->info = &mv88e6xxx_table[MV88E6085]; 3715 3716 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3717 if (err) 3718 goto free; 3719 3720 err = mv88e6xxx_detect(chip); 3721 if (err) 3722 goto free; 3723 3724 mutex_lock(&chip->reg_lock); 3725 err = mv88e6xxx_switch_reset(chip); 3726 mutex_unlock(&chip->reg_lock); 3727 if (err) 3728 goto free; 3729 3730 mv88e6xxx_phy_init(chip); 3731 3732 err = mv88e6xxx_mdios_register(chip, NULL); 3733 if (err) 3734 goto free; 3735 3736 *priv = chip; 3737 3738 return chip->info->name; 3739 free: 3740 devm_kfree(dsa_dev, chip); 3741 3742 return NULL; 3743 } 3744 3745 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3746 const struct switchdev_obj_port_mdb *mdb, 3747 struct switchdev_trans *trans) 3748 { 3749 /* We don't need any dynamic resource from the kernel (yet), 3750 * so skip the prepare phase. 3751 */ 3752 3753 return 0; 3754 } 3755 3756 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3757 const struct switchdev_obj_port_mdb *mdb, 3758 struct switchdev_trans *trans) 3759 { 3760 struct mv88e6xxx_chip *chip = ds->priv; 3761 3762 mutex_lock(&chip->reg_lock); 3763 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3764 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3765 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3766 port); 3767 mutex_unlock(&chip->reg_lock); 3768 } 3769 3770 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3771 const struct switchdev_obj_port_mdb *mdb) 3772 { 3773 struct mv88e6xxx_chip *chip = ds->priv; 3774 int err; 3775 3776 mutex_lock(&chip->reg_lock); 3777 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3778 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3779 mutex_unlock(&chip->reg_lock); 3780 3781 return err; 3782 } 3783 3784 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3785 .probe = mv88e6xxx_drv_probe, 3786 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3787 .setup = mv88e6xxx_setup, 3788 .set_addr = mv88e6xxx_set_addr, 3789 .adjust_link = mv88e6xxx_adjust_link, 3790 .get_strings = mv88e6xxx_get_strings, 3791 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3792 .get_sset_count = mv88e6xxx_get_sset_count, 3793 .port_enable = mv88e6xxx_port_enable, 3794 .port_disable = mv88e6xxx_port_disable, 3795 .get_mac_eee = mv88e6xxx_get_mac_eee, 3796 .set_mac_eee = mv88e6xxx_set_mac_eee, 3797 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3798 .get_eeprom = mv88e6xxx_get_eeprom, 3799 .set_eeprom = mv88e6xxx_set_eeprom, 3800 .get_regs_len = mv88e6xxx_get_regs_len, 3801 .get_regs = mv88e6xxx_get_regs, 3802 .set_ageing_time = mv88e6xxx_set_ageing_time, 3803 .port_bridge_join = mv88e6xxx_port_bridge_join, 3804 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3805 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3806 .port_fast_age = mv88e6xxx_port_fast_age, 3807 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3808 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3809 .port_vlan_add = mv88e6xxx_port_vlan_add, 3810 .port_vlan_del = mv88e6xxx_port_vlan_del, 3811 .port_fdb_add = mv88e6xxx_port_fdb_add, 3812 .port_fdb_del = mv88e6xxx_port_fdb_del, 3813 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3814 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3815 .port_mdb_add = mv88e6xxx_port_mdb_add, 3816 .port_mdb_del = mv88e6xxx_port_mdb_del, 3817 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 3818 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 3819 }; 3820 3821 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 3822 .ops = &mv88e6xxx_switch_ops, 3823 }; 3824 3825 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 3826 { 3827 struct device *dev = chip->dev; 3828 struct dsa_switch *ds; 3829 3830 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 3831 if (!ds) 3832 return -ENOMEM; 3833 3834 ds->priv = chip; 3835 ds->ops = &mv88e6xxx_switch_ops; 3836 ds->ageing_time_min = chip->info->age_time_coeff; 3837 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 3838 3839 dev_set_drvdata(dev, ds); 3840 3841 return dsa_register_switch(ds); 3842 } 3843 3844 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3845 { 3846 dsa_unregister_switch(chip->ds); 3847 } 3848 3849 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3850 { 3851 struct device *dev = &mdiodev->dev; 3852 struct device_node *np = dev->of_node; 3853 const struct mv88e6xxx_info *compat_info; 3854 struct mv88e6xxx_chip *chip; 3855 u32 eeprom_len; 3856 int err; 3857 3858 compat_info = of_device_get_match_data(dev); 3859 if (!compat_info) 3860 return -EINVAL; 3861 3862 chip = mv88e6xxx_alloc_chip(dev); 3863 if (!chip) 3864 return -ENOMEM; 3865 3866 chip->info = compat_info; 3867 3868 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3869 if (err) 3870 return err; 3871 3872 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 3873 if (IS_ERR(chip->reset)) 3874 return PTR_ERR(chip->reset); 3875 3876 err = mv88e6xxx_detect(chip); 3877 if (err) 3878 return err; 3879 3880 mv88e6xxx_phy_init(chip); 3881 3882 if (chip->info->ops->get_eeprom && 3883 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3884 chip->eeprom_len = eeprom_len; 3885 3886 mutex_lock(&chip->reg_lock); 3887 err = mv88e6xxx_switch_reset(chip); 3888 mutex_unlock(&chip->reg_lock); 3889 if (err) 3890 goto out; 3891 3892 chip->irq = of_irq_get(np, 0); 3893 if (chip->irq == -EPROBE_DEFER) { 3894 err = chip->irq; 3895 goto out; 3896 } 3897 3898 if (chip->irq > 0) { 3899 /* Has to be performed before the MDIO bus is created, 3900 * because the PHYs will link there interrupts to these 3901 * interrupt controllers 3902 */ 3903 mutex_lock(&chip->reg_lock); 3904 err = mv88e6xxx_g1_irq_setup(chip); 3905 mutex_unlock(&chip->reg_lock); 3906 3907 if (err) 3908 goto out; 3909 3910 if (chip->info->g2_irqs > 0) { 3911 err = mv88e6xxx_g2_irq_setup(chip); 3912 if (err) 3913 goto out_g1_irq; 3914 } 3915 } 3916 3917 err = mv88e6xxx_mdios_register(chip, np); 3918 if (err) 3919 goto out_g2_irq; 3920 3921 err = mv88e6xxx_register_switch(chip); 3922 if (err) 3923 goto out_mdio; 3924 3925 return 0; 3926 3927 out_mdio: 3928 mv88e6xxx_mdios_unregister(chip); 3929 out_g2_irq: 3930 if (chip->info->g2_irqs > 0 && chip->irq > 0) 3931 mv88e6xxx_g2_irq_free(chip); 3932 out_g1_irq: 3933 if (chip->irq > 0) { 3934 mutex_lock(&chip->reg_lock); 3935 mv88e6xxx_g1_irq_free(chip); 3936 mutex_unlock(&chip->reg_lock); 3937 } 3938 out: 3939 return err; 3940 } 3941 3942 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 3943 { 3944 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 3945 struct mv88e6xxx_chip *chip = ds->priv; 3946 3947 mv88e6xxx_phy_destroy(chip); 3948 mv88e6xxx_unregister_switch(chip); 3949 mv88e6xxx_mdios_unregister(chip); 3950 3951 if (chip->irq > 0) { 3952 if (chip->info->g2_irqs > 0) 3953 mv88e6xxx_g2_irq_free(chip); 3954 mutex_lock(&chip->reg_lock); 3955 mv88e6xxx_g1_irq_free(chip); 3956 mutex_unlock(&chip->reg_lock); 3957 } 3958 } 3959 3960 static const struct of_device_id mv88e6xxx_of_match[] = { 3961 { 3962 .compatible = "marvell,mv88e6085", 3963 .data = &mv88e6xxx_table[MV88E6085], 3964 }, 3965 { 3966 .compatible = "marvell,mv88e6190", 3967 .data = &mv88e6xxx_table[MV88E6190], 3968 }, 3969 { /* sentinel */ }, 3970 }; 3971 3972 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 3973 3974 static struct mdio_driver mv88e6xxx_driver = { 3975 .probe = mv88e6xxx_probe, 3976 .remove = mv88e6xxx_remove, 3977 .mdiodrv.driver = { 3978 .name = "mv88e6085", 3979 .of_match_table = mv88e6xxx_of_match, 3980 }, 3981 }; 3982 3983 static int __init mv88e6xxx_init(void) 3984 { 3985 register_switch_driver(&mv88e6xxx_switch_drv); 3986 return mdio_driver_register(&mv88e6xxx_driver); 3987 } 3988 module_init(mv88e6xxx_init); 3989 3990 static void __exit mv88e6xxx_cleanup(void) 3991 { 3992 mdio_driver_unregister(&mv88e6xxx_driver); 3993 unregister_switch_driver(&mv88e6xxx_switch_drv); 3994 } 3995 module_exit(mv88e6xxx_cleanup); 3996 3997 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 3998 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 3999 MODULE_LICENSE("GPL"); 4000