1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "serdes.h" 42 43 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 44 { 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 46 dev_err(chip->dev, "Switch registers lock not held!\n"); 47 dump_stack(); 48 } 49 } 50 51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 53 * 54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 55 * is the only device connected to the SMI master. In this mode it responds to 56 * all 32 possible SMI addresses, and thus maps directly the internal devices. 57 * 58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 59 * multiple devices to share the SMI interface. In this mode it responds to only 60 * 2 registers, used to indirectly access the internal SMI devices. 61 */ 62 63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 *val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->read(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 val) 74 { 75 if (!chip->smi_ops) 76 return -EOPNOTSUPP; 77 78 return chip->smi_ops->write(chip, addr, reg, val); 79 } 80 81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 82 int addr, int reg, u16 *val) 83 { 84 int ret; 85 86 ret = mdiobus_read_nested(chip->bus, addr, reg); 87 if (ret < 0) 88 return ret; 89 90 *val = ret & 0xffff; 91 92 return 0; 93 } 94 95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 96 int addr, int reg, u16 val) 97 { 98 int ret; 99 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 101 if (ret < 0) 102 return ret; 103 104 return 0; 105 } 106 107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 108 .read = mv88e6xxx_smi_single_chip_read, 109 .write = mv88e6xxx_smi_single_chip_write, 110 }; 111 112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 113 { 114 int ret; 115 int i; 116 117 for (i = 0; i < 16; i++) { 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 119 if (ret < 0) 120 return ret; 121 122 if ((ret & SMI_CMD_BUSY) == 0) 123 return 0; 124 } 125 126 return -ETIMEDOUT; 127 } 128 129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 130 int addr, int reg, u16 *val) 131 { 132 int ret; 133 134 /* Wait for the bus to become free. */ 135 ret = mv88e6xxx_smi_multi_chip_wait(chip); 136 if (ret < 0) 137 return ret; 138 139 /* Transmit the read command. */ 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 141 SMI_CMD_OP_22_READ | (addr << 5) | reg); 142 if (ret < 0) 143 return ret; 144 145 /* Wait for the read command to complete. */ 146 ret = mv88e6xxx_smi_multi_chip_wait(chip); 147 if (ret < 0) 148 return ret; 149 150 /* Read the data. */ 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 152 if (ret < 0) 153 return ret; 154 155 *val = ret & 0xffff; 156 157 return 0; 158 } 159 160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 161 int addr, int reg, u16 val) 162 { 163 int ret; 164 165 /* Wait for the bus to become free. */ 166 ret = mv88e6xxx_smi_multi_chip_wait(chip); 167 if (ret < 0) 168 return ret; 169 170 /* Transmit the data to write. */ 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 172 if (ret < 0) 173 return ret; 174 175 /* Transmit the write command. */ 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 178 if (ret < 0) 179 return ret; 180 181 /* Wait for the write command to complete. */ 182 ret = mv88e6xxx_smi_multi_chip_wait(chip); 183 if (ret < 0) 184 return ret; 185 186 return 0; 187 } 188 189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 190 .read = mv88e6xxx_smi_multi_chip_read, 191 .write = mv88e6xxx_smi_multi_chip_write, 192 }; 193 194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 195 { 196 int err; 197 198 assert_reg_lock(chip); 199 200 err = mv88e6xxx_smi_read(chip, addr, reg, val); 201 if (err) 202 return err; 203 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 205 addr, reg, *val); 206 207 return 0; 208 } 209 210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 211 { 212 int err; 213 214 assert_reg_lock(chip); 215 216 err = mv88e6xxx_smi_write(chip, addr, reg, val); 217 if (err) 218 return err; 219 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 221 addr, reg, val); 222 223 return 0; 224 } 225 226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 227 { 228 struct mv88e6xxx_mdio_bus *mdio_bus; 229 230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 231 list); 232 if (!mdio_bus) 233 return NULL; 234 235 return mdio_bus->bus; 236 } 237 238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 239 { 240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 241 unsigned int n = d->hwirq; 242 243 chip->g1_irq.masked |= (1 << n); 244 } 245 246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 247 { 248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 249 unsigned int n = d->hwirq; 250 251 chip->g1_irq.masked &= ~(1 << n); 252 } 253 254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 255 { 256 struct mv88e6xxx_chip *chip = dev_id; 257 unsigned int nhandled = 0; 258 unsigned int sub_irq; 259 unsigned int n; 260 u16 reg; 261 int err; 262 263 mutex_lock(&chip->reg_lock); 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 265 mutex_unlock(&chip->reg_lock); 266 267 if (err) 268 goto out; 269 270 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 271 if (reg & (1 << n)) { 272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 273 handle_nested_irq(sub_irq); 274 ++nhandled; 275 } 276 } 277 out: 278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 279 } 280 281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 282 { 283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 284 285 mutex_lock(&chip->reg_lock); 286 } 287 288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 289 { 290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 292 u16 reg; 293 int err; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 296 if (err) 297 goto out; 298 299 reg &= ~mask; 300 reg |= (~chip->g1_irq.masked & mask); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 303 if (err) 304 goto out; 305 306 out: 307 mutex_unlock(&chip->reg_lock); 308 } 309 310 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 311 .name = "mv88e6xxx-g1", 312 .irq_mask = mv88e6xxx_g1_irq_mask, 313 .irq_unmask = mv88e6xxx_g1_irq_unmask, 314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 316 }; 317 318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 319 unsigned int irq, 320 irq_hw_number_t hwirq) 321 { 322 struct mv88e6xxx_chip *chip = d->host_data; 323 324 irq_set_chip_data(irq, d->host_data); 325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 326 irq_set_noprobe(irq); 327 328 return 0; 329 } 330 331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 332 .map = mv88e6xxx_g1_irq_domain_map, 333 .xlate = irq_domain_xlate_twocell, 334 }; 335 336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 337 { 338 int irq, virq; 339 u16 mask; 340 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 342 mask |= GENMASK(chip->g1_irq.nirqs, 0); 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 344 345 free_irq(chip->irq, chip); 346 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 348 virq = irq_find_mapping(chip->g1_irq.domain, irq); 349 irq_dispose_mapping(virq); 350 } 351 352 irq_domain_remove(chip->g1_irq.domain); 353 } 354 355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 356 { 357 int err, irq, virq; 358 u16 reg, mask; 359 360 chip->g1_irq.nirqs = chip->info->g1_irqs; 361 chip->g1_irq.domain = irq_domain_add_simple( 362 NULL, chip->g1_irq.nirqs, 0, 363 &mv88e6xxx_g1_irq_domain_ops, chip); 364 if (!chip->g1_irq.domain) 365 return -ENOMEM; 366 367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 368 irq_create_mapping(chip->g1_irq.domain, irq); 369 370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 371 chip->g1_irq.masked = ~0; 372 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 374 if (err) 375 goto out_mapping; 376 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 378 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 380 if (err) 381 goto out_disable; 382 383 /* Reading the interrupt status clears (most of) them */ 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 385 if (err) 386 goto out_disable; 387 388 err = request_threaded_irq(chip->irq, NULL, 389 mv88e6xxx_g1_irq_thread_fn, 390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 391 dev_name(chip->dev), chip); 392 if (err) 393 goto out_disable; 394 395 return 0; 396 397 out_disable: 398 mask |= GENMASK(chip->g1_irq.nirqs, 0); 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 400 401 out_mapping: 402 for (irq = 0; irq < 16; irq++) { 403 virq = irq_find_mapping(chip->g1_irq.domain, irq); 404 irq_dispose_mapping(virq); 405 } 406 407 irq_domain_remove(chip->g1_irq.domain); 408 409 return err; 410 } 411 412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 413 { 414 int i; 415 416 for (i = 0; i < 16; i++) { 417 u16 val; 418 int err; 419 420 err = mv88e6xxx_read(chip, addr, reg, &val); 421 if (err) 422 return err; 423 424 if (!(val & mask)) 425 return 0; 426 427 usleep_range(1000, 2000); 428 } 429 430 dev_err(chip->dev, "Timeout while waiting for switch\n"); 431 return -ETIMEDOUT; 432 } 433 434 /* Indirect write to single pointer-data register with an Update bit */ 435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 436 { 437 u16 val; 438 int err; 439 440 /* Wait until the previous operation is completed */ 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 442 if (err) 443 return err; 444 445 /* Set the Update bit to trigger a write operation */ 446 val = BIT(15) | update; 447 448 return mv88e6xxx_write(chip, addr, reg, val); 449 } 450 451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 452 int link, int speed, int duplex, 453 phy_interface_t mode) 454 { 455 int err; 456 457 if (!chip->info->ops->port_set_link) 458 return 0; 459 460 /* Port's MAC control must not be changed unless the link is down */ 461 err = chip->info->ops->port_set_link(chip, port, 0); 462 if (err) 463 return err; 464 465 if (chip->info->ops->port_set_speed) { 466 err = chip->info->ops->port_set_speed(chip, port, speed); 467 if (err && err != -EOPNOTSUPP) 468 goto restore_link; 469 } 470 471 if (chip->info->ops->port_set_duplex) { 472 err = chip->info->ops->port_set_duplex(chip, port, duplex); 473 if (err && err != -EOPNOTSUPP) 474 goto restore_link; 475 } 476 477 if (chip->info->ops->port_set_rgmii_delay) { 478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 479 if (err && err != -EOPNOTSUPP) 480 goto restore_link; 481 } 482 483 if (chip->info->ops->port_set_cmode) { 484 err = chip->info->ops->port_set_cmode(chip, port, mode); 485 if (err && err != -EOPNOTSUPP) 486 goto restore_link; 487 } 488 489 err = 0; 490 restore_link: 491 if (chip->info->ops->port_set_link(chip, port, link)) 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 493 494 return err; 495 } 496 497 /* We expect the switch to perform auto negotiation if there is a real 498 * phy. However, in the case of a fixed link phy, we force the port 499 * settings from the fixed link settings. 500 */ 501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 502 struct phy_device *phydev) 503 { 504 struct mv88e6xxx_chip *chip = ds->priv; 505 int err; 506 507 if (!phy_is_pseudo_fixed_link(phydev)) 508 return; 509 510 mutex_lock(&chip->reg_lock); 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 512 phydev->duplex, phydev->interface); 513 mutex_unlock(&chip->reg_lock); 514 515 if (err && err != -EOPNOTSUPP) 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 517 } 518 519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 if (!chip->info->ops->stats_snapshot) 522 return -EOPNOTSUPP; 523 524 return chip->info->ops->stats_snapshot(chip, port); 525 } 526 527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 548 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 551 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 587 }; 588 589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 590 struct mv88e6xxx_hw_stat *s, 591 int port, u16 bank1_select, 592 u16 histogram) 593 { 594 u32 low; 595 u32 high = 0; 596 u16 reg = 0; 597 int err; 598 u64 value; 599 600 switch (s->type) { 601 case STATS_TYPE_PORT: 602 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 603 if (err) 604 return UINT64_MAX; 605 606 low = reg; 607 if (s->sizeof_stat == 4) { 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 609 if (err) 610 return UINT64_MAX; 611 high = reg; 612 } 613 break; 614 case STATS_TYPE_BANK1: 615 reg = bank1_select; 616 /* fall through */ 617 case STATS_TYPE_BANK0: 618 reg |= s->reg | histogram; 619 mv88e6xxx_g1_stats_read(chip, reg, &low); 620 if (s->sizeof_stat == 8) 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 622 break; 623 default: 624 return UINT64_MAX; 625 } 626 value = (((u64)high) << 16) | low; 627 return value; 628 } 629 630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 631 uint8_t *data, int types) 632 { 633 struct mv88e6xxx_hw_stat *stat; 634 int i, j; 635 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 637 stat = &mv88e6xxx_hw_stats[i]; 638 if (stat->type & types) { 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 640 ETH_GSTRING_LEN); 641 j++; 642 } 643 } 644 } 645 646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 647 uint8_t *data) 648 { 649 mv88e6xxx_stats_get_strings(chip, data, 650 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 651 } 652 653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 654 uint8_t *data) 655 { 656 mv88e6xxx_stats_get_strings(chip, data, 657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 658 } 659 660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 661 uint8_t *data) 662 { 663 struct mv88e6xxx_chip *chip = ds->priv; 664 665 if (chip->info->ops->stats_get_strings) 666 chip->info->ops->stats_get_strings(chip, data); 667 } 668 669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 670 int types) 671 { 672 struct mv88e6xxx_hw_stat *stat; 673 int i, j; 674 675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 676 stat = &mv88e6xxx_hw_stats[i]; 677 if (stat->type & types) 678 j++; 679 } 680 return j; 681 } 682 683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 684 { 685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 686 STATS_TYPE_PORT); 687 } 688 689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 692 STATS_TYPE_BANK1); 693 } 694 695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 696 { 697 struct mv88e6xxx_chip *chip = ds->priv; 698 699 if (chip->info->ops->stats_get_sset_count) 700 return chip->info->ops->stats_get_sset_count(chip); 701 702 return 0; 703 } 704 705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 706 uint64_t *data, int types, 707 u16 bank1_select, u16 histogram) 708 { 709 struct mv88e6xxx_hw_stat *stat; 710 int i, j; 711 712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 713 stat = &mv88e6xxx_hw_stats[i]; 714 if (stat->type & types) { 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 716 bank1_select, 717 histogram); 718 j++; 719 } 720 } 721 } 722 723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 724 uint64_t *data) 725 { 726 return mv88e6xxx_stats_get_stats(chip, port, data, 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 729 } 730 731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 732 uint64_t *data) 733 { 734 return mv88e6xxx_stats_get_stats(chip, port, data, 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 738 } 739 740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 741 uint64_t *data) 742 { 743 return mv88e6xxx_stats_get_stats(chip, port, data, 744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 746 0); 747 } 748 749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 750 uint64_t *data) 751 { 752 if (chip->info->ops->stats_get_stats) 753 chip->info->ops->stats_get_stats(chip, port, data); 754 } 755 756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 757 uint64_t *data) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 int ret; 761 762 mutex_lock(&chip->reg_lock); 763 764 ret = mv88e6xxx_stats_snapshot(chip, port); 765 if (ret < 0) { 766 mutex_unlock(&chip->reg_lock); 767 return; 768 } 769 770 mv88e6xxx_get_stats(chip, port, data); 771 772 mutex_unlock(&chip->reg_lock); 773 } 774 775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 776 { 777 if (chip->info->ops->stats_set_histogram) 778 return chip->info->ops->stats_set_histogram(chip); 779 780 return 0; 781 } 782 783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 784 { 785 return 32 * sizeof(u16); 786 } 787 788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 789 struct ethtool_regs *regs, void *_p) 790 { 791 struct mv88e6xxx_chip *chip = ds->priv; 792 int err; 793 u16 reg; 794 u16 *p = _p; 795 int i; 796 797 regs->version = 0; 798 799 memset(p, 0xff, 32 * sizeof(u16)); 800 801 mutex_lock(&chip->reg_lock); 802 803 for (i = 0; i < 32; i++) { 804 805 err = mv88e6xxx_port_read(chip, port, i, ®); 806 if (!err) 807 p[i] = reg; 808 } 809 810 mutex_unlock(&chip->reg_lock); 811 } 812 813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 814 struct ethtool_eee *e) 815 { 816 /* Nothing to do on the port's MAC */ 817 return 0; 818 } 819 820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 821 struct ethtool_eee *e) 822 { 823 /* Nothing to do on the port's MAC */ 824 return 0; 825 } 826 827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 828 { 829 struct dsa_switch *ds = NULL; 830 struct net_device *br; 831 u16 pvlan; 832 int i; 833 834 if (dev < DSA_MAX_SWITCHES) 835 ds = chip->ds->dst->ds[dev]; 836 837 /* Prevent frames from unknown switch or port */ 838 if (!ds || port >= ds->num_ports) 839 return 0; 840 841 /* Frames from DSA links and CPU ports can egress any local port */ 842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 843 return mv88e6xxx_port_mask(chip); 844 845 br = ds->ports[port].bridge_dev; 846 pvlan = 0; 847 848 /* Frames from user ports can egress any local DSA links and CPU ports, 849 * as well as any local member of their bridge group. 850 */ 851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 852 if (dsa_is_cpu_port(chip->ds, i) || 853 dsa_is_dsa_port(chip->ds, i) || 854 (br && chip->ds->ports[i].bridge_dev == br)) 855 pvlan |= BIT(i); 856 857 return pvlan; 858 } 859 860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 861 { 862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 863 864 /* prevent frames from going back out of the port they came in on */ 865 output_ports &= ~BIT(port); 866 867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 868 } 869 870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 871 u8 state) 872 { 873 struct mv88e6xxx_chip *chip = ds->priv; 874 int err; 875 876 mutex_lock(&chip->reg_lock); 877 err = mv88e6xxx_port_set_state(chip, port, state); 878 mutex_unlock(&chip->reg_lock); 879 880 if (err) 881 dev_err(ds->dev, "p%d: failed to update state\n", port); 882 } 883 884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 885 { 886 if (chip->info->ops->pot_clear) 887 return chip->info->ops->pot_clear(chip); 888 889 return 0; 890 } 891 892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 893 { 894 if (chip->info->ops->mgmt_rsvd2cpu) 895 return chip->info->ops->mgmt_rsvd2cpu(chip); 896 897 return 0; 898 } 899 900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 901 { 902 int err; 903 904 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 905 if (err) 906 return err; 907 908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 909 if (err) 910 return err; 911 912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 913 } 914 915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 916 { 917 int port; 918 int err; 919 920 if (!chip->info->ops->irl_init_all) 921 return 0; 922 923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 924 /* Disable ingress rate limiting by resetting all per port 925 * ingress rate limit resources to their initial state. 926 */ 927 err = chip->info->ops->irl_init_all(chip, port); 928 if (err) 929 return err; 930 } 931 932 return 0; 933 } 934 935 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 936 { 937 u16 pvlan = 0; 938 939 if (!mv88e6xxx_has_pvt(chip)) 940 return -EOPNOTSUPP; 941 942 /* Skip the local source device, which uses in-chip port VLAN */ 943 if (dev != chip->ds->index) 944 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 945 946 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 947 } 948 949 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 950 { 951 int dev, port; 952 int err; 953 954 if (!mv88e6xxx_has_pvt(chip)) 955 return 0; 956 957 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 958 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 959 */ 960 err = mv88e6xxx_g2_misc_4_bit_port(chip); 961 if (err) 962 return err; 963 964 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 965 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 966 err = mv88e6xxx_pvt_map(chip, dev, port); 967 if (err) 968 return err; 969 } 970 } 971 972 return 0; 973 } 974 975 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 976 { 977 struct mv88e6xxx_chip *chip = ds->priv; 978 int err; 979 980 mutex_lock(&chip->reg_lock); 981 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 982 mutex_unlock(&chip->reg_lock); 983 984 if (err) 985 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 986 } 987 988 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 989 { 990 if (!chip->info->max_vid) 991 return 0; 992 993 return mv88e6xxx_g1_vtu_flush(chip); 994 } 995 996 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 997 struct mv88e6xxx_vtu_entry *entry) 998 { 999 if (!chip->info->ops->vtu_getnext) 1000 return -EOPNOTSUPP; 1001 1002 return chip->info->ops->vtu_getnext(chip, entry); 1003 } 1004 1005 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1006 struct mv88e6xxx_vtu_entry *entry) 1007 { 1008 if (!chip->info->ops->vtu_loadpurge) 1009 return -EOPNOTSUPP; 1010 1011 return chip->info->ops->vtu_loadpurge(chip, entry); 1012 } 1013 1014 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1015 { 1016 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1017 struct mv88e6xxx_vtu_entry vlan = { 1018 .vid = chip->info->max_vid, 1019 }; 1020 int i, err; 1021 1022 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1023 1024 /* Set every FID bit used by the (un)bridged ports */ 1025 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1026 err = mv88e6xxx_port_get_fid(chip, i, fid); 1027 if (err) 1028 return err; 1029 1030 set_bit(*fid, fid_bitmap); 1031 } 1032 1033 /* Set every FID bit used by the VLAN entries */ 1034 do { 1035 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1036 if (err) 1037 return err; 1038 1039 if (!vlan.valid) 1040 break; 1041 1042 set_bit(vlan.fid, fid_bitmap); 1043 } while (vlan.vid < chip->info->max_vid); 1044 1045 /* The reset value 0x000 is used to indicate that multiple address 1046 * databases are not needed. Return the next positive available. 1047 */ 1048 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1049 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1050 return -ENOSPC; 1051 1052 /* Clear the database */ 1053 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1054 } 1055 1056 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1057 struct mv88e6xxx_vtu_entry *entry, bool new) 1058 { 1059 int err; 1060 1061 if (!vid) 1062 return -EINVAL; 1063 1064 entry->vid = vid - 1; 1065 entry->valid = false; 1066 1067 err = mv88e6xxx_vtu_getnext(chip, entry); 1068 if (err) 1069 return err; 1070 1071 if (entry->vid == vid && entry->valid) 1072 return 0; 1073 1074 if (new) { 1075 int i; 1076 1077 /* Initialize a fresh VLAN entry */ 1078 memset(entry, 0, sizeof(*entry)); 1079 entry->valid = true; 1080 entry->vid = vid; 1081 1082 /* Exclude all ports */ 1083 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1084 entry->member[i] = 1085 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1086 1087 return mv88e6xxx_atu_new(chip, &entry->fid); 1088 } 1089 1090 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1091 return -EOPNOTSUPP; 1092 } 1093 1094 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1095 u16 vid_begin, u16 vid_end) 1096 { 1097 struct mv88e6xxx_chip *chip = ds->priv; 1098 struct mv88e6xxx_vtu_entry vlan = { 1099 .vid = vid_begin - 1, 1100 }; 1101 int i, err; 1102 1103 if (!vid_begin) 1104 return -EOPNOTSUPP; 1105 1106 mutex_lock(&chip->reg_lock); 1107 1108 do { 1109 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1110 if (err) 1111 goto unlock; 1112 1113 if (!vlan.valid) 1114 break; 1115 1116 if (vlan.vid > vid_end) 1117 break; 1118 1119 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1120 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1121 continue; 1122 1123 if (!ds->ports[port].netdev) 1124 continue; 1125 1126 if (vlan.member[i] == 1127 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1128 continue; 1129 1130 if (ds->ports[i].bridge_dev == 1131 ds->ports[port].bridge_dev) 1132 break; /* same bridge, check next VLAN */ 1133 1134 if (!ds->ports[i].bridge_dev) 1135 continue; 1136 1137 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n", 1138 port, vlan.vid, 1139 netdev_name(ds->ports[i].bridge_dev)); 1140 err = -EOPNOTSUPP; 1141 goto unlock; 1142 } 1143 } while (vlan.vid < vid_end); 1144 1145 unlock: 1146 mutex_unlock(&chip->reg_lock); 1147 1148 return err; 1149 } 1150 1151 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1152 bool vlan_filtering) 1153 { 1154 struct mv88e6xxx_chip *chip = ds->priv; 1155 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1156 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1157 int err; 1158 1159 if (!chip->info->max_vid) 1160 return -EOPNOTSUPP; 1161 1162 mutex_lock(&chip->reg_lock); 1163 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1164 mutex_unlock(&chip->reg_lock); 1165 1166 return err; 1167 } 1168 1169 static int 1170 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1171 const struct switchdev_obj_port_vlan *vlan, 1172 struct switchdev_trans *trans) 1173 { 1174 struct mv88e6xxx_chip *chip = ds->priv; 1175 int err; 1176 1177 if (!chip->info->max_vid) 1178 return -EOPNOTSUPP; 1179 1180 /* If the requested port doesn't belong to the same bridge as the VLAN 1181 * members, do not support it (yet) and fallback to software VLAN. 1182 */ 1183 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1184 vlan->vid_end); 1185 if (err) 1186 return err; 1187 1188 /* We don't need any dynamic resource from the kernel (yet), 1189 * so skip the prepare phase. 1190 */ 1191 return 0; 1192 } 1193 1194 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1195 u16 vid, u8 member) 1196 { 1197 struct mv88e6xxx_vtu_entry vlan; 1198 int err; 1199 1200 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1201 if (err) 1202 return err; 1203 1204 vlan.member[port] = member; 1205 1206 return mv88e6xxx_vtu_loadpurge(chip, &vlan); 1207 } 1208 1209 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1210 const struct switchdev_obj_port_vlan *vlan, 1211 struct switchdev_trans *trans) 1212 { 1213 struct mv88e6xxx_chip *chip = ds->priv; 1214 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1215 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1216 u8 member; 1217 u16 vid; 1218 1219 if (!chip->info->max_vid) 1220 return; 1221 1222 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1223 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1224 else if (untagged) 1225 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1226 else 1227 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1228 1229 mutex_lock(&chip->reg_lock); 1230 1231 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1232 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1233 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1234 vid, untagged ? 'u' : 't'); 1235 1236 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1237 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1238 vlan->vid_end); 1239 1240 mutex_unlock(&chip->reg_lock); 1241 } 1242 1243 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1244 int port, u16 vid) 1245 { 1246 struct mv88e6xxx_vtu_entry vlan; 1247 int i, err; 1248 1249 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1250 if (err) 1251 return err; 1252 1253 /* Tell switchdev if this VLAN is handled in software */ 1254 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1255 return -EOPNOTSUPP; 1256 1257 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1258 1259 /* keep the VLAN unless all ports are excluded */ 1260 vlan.valid = false; 1261 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1262 if (vlan.member[i] != 1263 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1264 vlan.valid = true; 1265 break; 1266 } 1267 } 1268 1269 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1270 if (err) 1271 return err; 1272 1273 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1274 } 1275 1276 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1277 const struct switchdev_obj_port_vlan *vlan) 1278 { 1279 struct mv88e6xxx_chip *chip = ds->priv; 1280 u16 pvid, vid; 1281 int err = 0; 1282 1283 if (!chip->info->max_vid) 1284 return -EOPNOTSUPP; 1285 1286 mutex_lock(&chip->reg_lock); 1287 1288 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1289 if (err) 1290 goto unlock; 1291 1292 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1293 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1294 if (err) 1295 goto unlock; 1296 1297 if (vid == pvid) { 1298 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1299 if (err) 1300 goto unlock; 1301 } 1302 } 1303 1304 unlock: 1305 mutex_unlock(&chip->reg_lock); 1306 1307 return err; 1308 } 1309 1310 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1311 const unsigned char *addr, u16 vid, 1312 u8 state) 1313 { 1314 struct mv88e6xxx_vtu_entry vlan; 1315 struct mv88e6xxx_atu_entry entry; 1316 int err; 1317 1318 /* Null VLAN ID corresponds to the port private database */ 1319 if (vid == 0) 1320 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1321 else 1322 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1323 if (err) 1324 return err; 1325 1326 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1327 ether_addr_copy(entry.mac, addr); 1328 eth_addr_dec(entry.mac); 1329 1330 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1331 if (err) 1332 return err; 1333 1334 /* Initialize a fresh ATU entry if it isn't found */ 1335 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1336 !ether_addr_equal(entry.mac, addr)) { 1337 memset(&entry, 0, sizeof(entry)); 1338 ether_addr_copy(entry.mac, addr); 1339 } 1340 1341 /* Purge the ATU entry only if no port is using it anymore */ 1342 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1343 entry.portvec &= ~BIT(port); 1344 if (!entry.portvec) 1345 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1346 } else { 1347 entry.portvec |= BIT(port); 1348 entry.state = state; 1349 } 1350 1351 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1352 } 1353 1354 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1355 const unsigned char *addr, u16 vid) 1356 { 1357 struct mv88e6xxx_chip *chip = ds->priv; 1358 int err; 1359 1360 mutex_lock(&chip->reg_lock); 1361 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1362 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1363 mutex_unlock(&chip->reg_lock); 1364 1365 return err; 1366 } 1367 1368 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1369 const unsigned char *addr, u16 vid) 1370 { 1371 struct mv88e6xxx_chip *chip = ds->priv; 1372 int err; 1373 1374 mutex_lock(&chip->reg_lock); 1375 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1376 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1377 mutex_unlock(&chip->reg_lock); 1378 1379 return err; 1380 } 1381 1382 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1383 u16 fid, u16 vid, int port, 1384 dsa_fdb_dump_cb_t *cb, void *data) 1385 { 1386 struct mv88e6xxx_atu_entry addr; 1387 bool is_static; 1388 int err; 1389 1390 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1391 eth_broadcast_addr(addr.mac); 1392 1393 do { 1394 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1395 if (err) 1396 return err; 1397 1398 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1399 break; 1400 1401 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1402 continue; 1403 1404 if (!is_unicast_ether_addr(addr.mac)) 1405 continue; 1406 1407 is_static = (addr.state == 1408 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1409 err = cb(addr.mac, vid, is_static, data); 1410 if (err) 1411 return err; 1412 } while (!is_broadcast_ether_addr(addr.mac)); 1413 1414 return err; 1415 } 1416 1417 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1418 dsa_fdb_dump_cb_t *cb, void *data) 1419 { 1420 struct mv88e6xxx_vtu_entry vlan = { 1421 .vid = chip->info->max_vid, 1422 }; 1423 u16 fid; 1424 int err; 1425 1426 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1427 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1428 if (err) 1429 return err; 1430 1431 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1432 if (err) 1433 return err; 1434 1435 /* Dump VLANs' Filtering Information Databases */ 1436 do { 1437 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1438 if (err) 1439 return err; 1440 1441 if (!vlan.valid) 1442 break; 1443 1444 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1445 cb, data); 1446 if (err) 1447 return err; 1448 } while (vlan.vid < chip->info->max_vid); 1449 1450 return err; 1451 } 1452 1453 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1454 dsa_fdb_dump_cb_t *cb, void *data) 1455 { 1456 struct mv88e6xxx_chip *chip = ds->priv; 1457 int err; 1458 1459 mutex_lock(&chip->reg_lock); 1460 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1461 mutex_unlock(&chip->reg_lock); 1462 1463 return err; 1464 } 1465 1466 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1467 struct net_device *br) 1468 { 1469 struct dsa_switch *ds; 1470 int port; 1471 int dev; 1472 int err; 1473 1474 /* Remap the Port VLAN of each local bridge group member */ 1475 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1476 if (chip->ds->ports[port].bridge_dev == br) { 1477 err = mv88e6xxx_port_vlan_map(chip, port); 1478 if (err) 1479 return err; 1480 } 1481 } 1482 1483 if (!mv88e6xxx_has_pvt(chip)) 1484 return 0; 1485 1486 /* Remap the Port VLAN of each cross-chip bridge group member */ 1487 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1488 ds = chip->ds->dst->ds[dev]; 1489 if (!ds) 1490 break; 1491 1492 for (port = 0; port < ds->num_ports; ++port) { 1493 if (ds->ports[port].bridge_dev == br) { 1494 err = mv88e6xxx_pvt_map(chip, dev, port); 1495 if (err) 1496 return err; 1497 } 1498 } 1499 } 1500 1501 return 0; 1502 } 1503 1504 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1505 struct net_device *br) 1506 { 1507 struct mv88e6xxx_chip *chip = ds->priv; 1508 int err; 1509 1510 mutex_lock(&chip->reg_lock); 1511 err = mv88e6xxx_bridge_map(chip, br); 1512 mutex_unlock(&chip->reg_lock); 1513 1514 return err; 1515 } 1516 1517 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1518 struct net_device *br) 1519 { 1520 struct mv88e6xxx_chip *chip = ds->priv; 1521 1522 mutex_lock(&chip->reg_lock); 1523 if (mv88e6xxx_bridge_map(chip, br) || 1524 mv88e6xxx_port_vlan_map(chip, port)) 1525 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1526 mutex_unlock(&chip->reg_lock); 1527 } 1528 1529 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1530 int port, struct net_device *br) 1531 { 1532 struct mv88e6xxx_chip *chip = ds->priv; 1533 int err; 1534 1535 if (!mv88e6xxx_has_pvt(chip)) 1536 return 0; 1537 1538 mutex_lock(&chip->reg_lock); 1539 err = mv88e6xxx_pvt_map(chip, dev, port); 1540 mutex_unlock(&chip->reg_lock); 1541 1542 return err; 1543 } 1544 1545 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1546 int port, struct net_device *br) 1547 { 1548 struct mv88e6xxx_chip *chip = ds->priv; 1549 1550 if (!mv88e6xxx_has_pvt(chip)) 1551 return; 1552 1553 mutex_lock(&chip->reg_lock); 1554 if (mv88e6xxx_pvt_map(chip, dev, port)) 1555 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1556 mutex_unlock(&chip->reg_lock); 1557 } 1558 1559 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1560 { 1561 if (chip->info->ops->reset) 1562 return chip->info->ops->reset(chip); 1563 1564 return 0; 1565 } 1566 1567 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1568 { 1569 struct gpio_desc *gpiod = chip->reset; 1570 1571 /* If there is a GPIO connected to the reset pin, toggle it */ 1572 if (gpiod) { 1573 gpiod_set_value_cansleep(gpiod, 1); 1574 usleep_range(10000, 20000); 1575 gpiod_set_value_cansleep(gpiod, 0); 1576 usleep_range(10000, 20000); 1577 } 1578 } 1579 1580 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1581 { 1582 int i, err; 1583 1584 /* Set all ports to the Disabled state */ 1585 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1586 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1587 if (err) 1588 return err; 1589 } 1590 1591 /* Wait for transmit queues to drain, 1592 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1593 */ 1594 usleep_range(2000, 4000); 1595 1596 return 0; 1597 } 1598 1599 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1600 { 1601 int err; 1602 1603 err = mv88e6xxx_disable_ports(chip); 1604 if (err) 1605 return err; 1606 1607 mv88e6xxx_hardware_reset(chip); 1608 1609 return mv88e6xxx_software_reset(chip); 1610 } 1611 1612 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1613 enum mv88e6xxx_frame_mode frame, 1614 enum mv88e6xxx_egress_mode egress, u16 etype) 1615 { 1616 int err; 1617 1618 if (!chip->info->ops->port_set_frame_mode) 1619 return -EOPNOTSUPP; 1620 1621 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1622 if (err) 1623 return err; 1624 1625 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1626 if (err) 1627 return err; 1628 1629 if (chip->info->ops->port_set_ether_type) 1630 return chip->info->ops->port_set_ether_type(chip, port, etype); 1631 1632 return 0; 1633 } 1634 1635 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1636 { 1637 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1638 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1639 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1640 } 1641 1642 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1643 { 1644 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1645 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1646 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1647 } 1648 1649 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1650 { 1651 return mv88e6xxx_set_port_mode(chip, port, 1652 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1653 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1654 ETH_P_EDSA); 1655 } 1656 1657 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1658 { 1659 if (dsa_is_dsa_port(chip->ds, port)) 1660 return mv88e6xxx_set_port_mode_dsa(chip, port); 1661 1662 if (dsa_is_normal_port(chip->ds, port)) 1663 return mv88e6xxx_set_port_mode_normal(chip, port); 1664 1665 /* Setup CPU port mode depending on its supported tag format */ 1666 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1667 return mv88e6xxx_set_port_mode_dsa(chip, port); 1668 1669 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1670 return mv88e6xxx_set_port_mode_edsa(chip, port); 1671 1672 return -EINVAL; 1673 } 1674 1675 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1676 { 1677 bool message = dsa_is_dsa_port(chip->ds, port); 1678 1679 return mv88e6xxx_port_set_message_port(chip, port, message); 1680 } 1681 1682 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1683 { 1684 bool flood = port == dsa_upstream_port(chip->ds); 1685 1686 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1687 if (chip->info->ops->port_set_egress_floods) 1688 return chip->info->ops->port_set_egress_floods(chip, port, 1689 flood, flood); 1690 1691 return 0; 1692 } 1693 1694 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1695 bool on) 1696 { 1697 if (chip->info->ops->serdes_power) 1698 return chip->info->ops->serdes_power(chip, port, on); 1699 1700 return 0; 1701 } 1702 1703 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1704 { 1705 struct dsa_switch *ds = chip->ds; 1706 int err; 1707 u16 reg; 1708 1709 /* MAC Forcing register: don't force link, speed, duplex or flow control 1710 * state to any particular values on physical ports, but force the CPU 1711 * port and all DSA ports to their maximum bandwidth and full duplex. 1712 */ 1713 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1714 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1715 SPEED_MAX, DUPLEX_FULL, 1716 PHY_INTERFACE_MODE_NA); 1717 else 1718 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1719 SPEED_UNFORCED, DUPLEX_UNFORCED, 1720 PHY_INTERFACE_MODE_NA); 1721 if (err) 1722 return err; 1723 1724 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1725 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1726 * tunneling, determine priority by looking at 802.1p and IP 1727 * priority fields (IP prio has precedence), and set STP state 1728 * to Forwarding. 1729 * 1730 * If this is the CPU link, use DSA or EDSA tagging depending 1731 * on which tagging mode was configured. 1732 * 1733 * If this is a link to another switch, use DSA tagging mode. 1734 * 1735 * If this is the upstream port for this switch, enable 1736 * forwarding of unknown unicasts and multicasts. 1737 */ 1738 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1739 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1740 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1741 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1742 if (err) 1743 return err; 1744 1745 err = mv88e6xxx_setup_port_mode(chip, port); 1746 if (err) 1747 return err; 1748 1749 err = mv88e6xxx_setup_egress_floods(chip, port); 1750 if (err) 1751 return err; 1752 1753 /* Enable the SERDES interface for DSA and CPU ports. Normal 1754 * ports SERDES are enabled when the port is enabled, thus 1755 * saving a bit of power. 1756 */ 1757 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1758 err = mv88e6xxx_serdes_power(chip, port, true); 1759 if (err) 1760 return err; 1761 } 1762 1763 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1764 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1765 * untagged frames on this port, do a destination address lookup on all 1766 * received packets as usual, disable ARP mirroring and don't send a 1767 * copy of all transmitted/received frames on this port to the CPU. 1768 */ 1769 err = mv88e6xxx_port_set_map_da(chip, port); 1770 if (err) 1771 return err; 1772 1773 reg = 0; 1774 if (chip->info->ops->port_set_upstream_port) { 1775 err = chip->info->ops->port_set_upstream_port( 1776 chip, port, dsa_upstream_port(ds)); 1777 if (err) 1778 return err; 1779 } 1780 1781 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1782 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1783 if (err) 1784 return err; 1785 1786 if (chip->info->ops->port_set_jumbo_size) { 1787 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1788 if (err) 1789 return err; 1790 } 1791 1792 /* Port Association Vector: when learning source addresses 1793 * of packets, add the address to the address database using 1794 * a port bitmap that has only the bit for this port set and 1795 * the other bits clear. 1796 */ 1797 reg = 1 << port; 1798 /* Disable learning for CPU port */ 1799 if (dsa_is_cpu_port(ds, port)) 1800 reg = 0; 1801 1802 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1803 reg); 1804 if (err) 1805 return err; 1806 1807 /* Egress rate control 2: disable egress rate control. */ 1808 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1809 0x0000); 1810 if (err) 1811 return err; 1812 1813 if (chip->info->ops->port_pause_limit) { 1814 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1815 if (err) 1816 return err; 1817 } 1818 1819 if (chip->info->ops->port_disable_learn_limit) { 1820 err = chip->info->ops->port_disable_learn_limit(chip, port); 1821 if (err) 1822 return err; 1823 } 1824 1825 if (chip->info->ops->port_disable_pri_override) { 1826 err = chip->info->ops->port_disable_pri_override(chip, port); 1827 if (err) 1828 return err; 1829 } 1830 1831 if (chip->info->ops->port_tag_remap) { 1832 err = chip->info->ops->port_tag_remap(chip, port); 1833 if (err) 1834 return err; 1835 } 1836 1837 if (chip->info->ops->port_egress_rate_limiting) { 1838 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1839 if (err) 1840 return err; 1841 } 1842 1843 err = mv88e6xxx_setup_message_port(chip, port); 1844 if (err) 1845 return err; 1846 1847 /* Port based VLAN map: give each port the same default address 1848 * database, and allow bidirectional communication between the 1849 * CPU and DSA port(s), and the other ports. 1850 */ 1851 err = mv88e6xxx_port_set_fid(chip, port, 0); 1852 if (err) 1853 return err; 1854 1855 err = mv88e6xxx_port_vlan_map(chip, port); 1856 if (err) 1857 return err; 1858 1859 /* Default VLAN ID and priority: don't set a default VLAN 1860 * ID, and set the default packet priority to zero. 1861 */ 1862 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 1863 } 1864 1865 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 1866 struct phy_device *phydev) 1867 { 1868 struct mv88e6xxx_chip *chip = ds->priv; 1869 int err; 1870 1871 mutex_lock(&chip->reg_lock); 1872 err = mv88e6xxx_serdes_power(chip, port, true); 1873 mutex_unlock(&chip->reg_lock); 1874 1875 return err; 1876 } 1877 1878 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 1879 struct phy_device *phydev) 1880 { 1881 struct mv88e6xxx_chip *chip = ds->priv; 1882 1883 mutex_lock(&chip->reg_lock); 1884 if (mv88e6xxx_serdes_power(chip, port, false)) 1885 dev_err(chip->dev, "failed to power off SERDES\n"); 1886 mutex_unlock(&chip->reg_lock); 1887 } 1888 1889 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 1890 unsigned int ageing_time) 1891 { 1892 struct mv88e6xxx_chip *chip = ds->priv; 1893 int err; 1894 1895 mutex_lock(&chip->reg_lock); 1896 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 1897 mutex_unlock(&chip->reg_lock); 1898 1899 return err; 1900 } 1901 1902 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 1903 { 1904 struct dsa_switch *ds = chip->ds; 1905 u32 upstream_port = dsa_upstream_port(ds); 1906 int err; 1907 1908 if (chip->info->ops->set_cpu_port) { 1909 err = chip->info->ops->set_cpu_port(chip, upstream_port); 1910 if (err) 1911 return err; 1912 } 1913 1914 if (chip->info->ops->set_egress_port) { 1915 err = chip->info->ops->set_egress_port(chip, upstream_port); 1916 if (err) 1917 return err; 1918 } 1919 1920 /* Disable remote management, and set the switch's DSA device number. */ 1921 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 1922 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 1923 (ds->index & 0x1f)); 1924 if (err) 1925 return err; 1926 1927 /* Configure the IP ToS mapping registers. */ 1928 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 1929 if (err) 1930 return err; 1931 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 1932 if (err) 1933 return err; 1934 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 1935 if (err) 1936 return err; 1937 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 1938 if (err) 1939 return err; 1940 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 1941 if (err) 1942 return err; 1943 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 1944 if (err) 1945 return err; 1946 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 1947 if (err) 1948 return err; 1949 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 1950 if (err) 1951 return err; 1952 1953 /* Configure the IEEE 802.1p priority mapping register. */ 1954 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 1955 if (err) 1956 return err; 1957 1958 /* Initialize the statistics unit */ 1959 err = mv88e6xxx_stats_set_histogram(chip); 1960 if (err) 1961 return err; 1962 1963 /* Clear the statistics counters for all ports */ 1964 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 1965 MV88E6XXX_G1_STATS_OP_BUSY | 1966 MV88E6XXX_G1_STATS_OP_FLUSH_ALL); 1967 if (err) 1968 return err; 1969 1970 /* Wait for the flush to complete. */ 1971 err = mv88e6xxx_g1_stats_wait(chip); 1972 if (err) 1973 return err; 1974 1975 return 0; 1976 } 1977 1978 static int mv88e6xxx_setup(struct dsa_switch *ds) 1979 { 1980 struct mv88e6xxx_chip *chip = ds->priv; 1981 int err; 1982 int i; 1983 1984 chip->ds = ds; 1985 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 1986 1987 mutex_lock(&chip->reg_lock); 1988 1989 /* Setup Switch Port Registers */ 1990 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1991 err = mv88e6xxx_setup_port(chip, i); 1992 if (err) 1993 goto unlock; 1994 } 1995 1996 /* Setup Switch Global 1 Registers */ 1997 err = mv88e6xxx_g1_setup(chip); 1998 if (err) 1999 goto unlock; 2000 2001 /* Setup Switch Global 2 Registers */ 2002 if (chip->info->global2_addr) { 2003 err = mv88e6xxx_g2_setup(chip); 2004 if (err) 2005 goto unlock; 2006 } 2007 2008 err = mv88e6xxx_irl_setup(chip); 2009 if (err) 2010 goto unlock; 2011 2012 err = mv88e6xxx_phy_setup(chip); 2013 if (err) 2014 goto unlock; 2015 2016 err = mv88e6xxx_vtu_setup(chip); 2017 if (err) 2018 goto unlock; 2019 2020 err = mv88e6xxx_pvt_setup(chip); 2021 if (err) 2022 goto unlock; 2023 2024 err = mv88e6xxx_atu_setup(chip); 2025 if (err) 2026 goto unlock; 2027 2028 err = mv88e6xxx_pot_setup(chip); 2029 if (err) 2030 goto unlock; 2031 2032 err = mv88e6xxx_rsvd2cpu_setup(chip); 2033 if (err) 2034 goto unlock; 2035 2036 unlock: 2037 mutex_unlock(&chip->reg_lock); 2038 2039 return err; 2040 } 2041 2042 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2043 { 2044 struct mv88e6xxx_chip *chip = ds->priv; 2045 int err; 2046 2047 if (!chip->info->ops->set_switch_mac) 2048 return -EOPNOTSUPP; 2049 2050 mutex_lock(&chip->reg_lock); 2051 err = chip->info->ops->set_switch_mac(chip, addr); 2052 mutex_unlock(&chip->reg_lock); 2053 2054 return err; 2055 } 2056 2057 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2058 { 2059 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2060 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2061 u16 val; 2062 int err; 2063 2064 if (!chip->info->ops->phy_read) 2065 return -EOPNOTSUPP; 2066 2067 mutex_lock(&chip->reg_lock); 2068 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2069 mutex_unlock(&chip->reg_lock); 2070 2071 if (reg == MII_PHYSID2) { 2072 /* Some internal PHYS don't have a model number. Use 2073 * the mv88e6390 family model number instead. 2074 */ 2075 if (!(val & 0x3f0)) 2076 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2077 } 2078 2079 return err ? err : val; 2080 } 2081 2082 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2083 { 2084 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2085 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2086 int err; 2087 2088 if (!chip->info->ops->phy_write) 2089 return -EOPNOTSUPP; 2090 2091 mutex_lock(&chip->reg_lock); 2092 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2093 mutex_unlock(&chip->reg_lock); 2094 2095 return err; 2096 } 2097 2098 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2099 struct device_node *np, 2100 bool external) 2101 { 2102 static int index; 2103 struct mv88e6xxx_mdio_bus *mdio_bus; 2104 struct mii_bus *bus; 2105 int err; 2106 2107 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2108 if (!bus) 2109 return -ENOMEM; 2110 2111 mdio_bus = bus->priv; 2112 mdio_bus->bus = bus; 2113 mdio_bus->chip = chip; 2114 INIT_LIST_HEAD(&mdio_bus->list); 2115 mdio_bus->external = external; 2116 2117 if (np) { 2118 bus->name = np->full_name; 2119 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2120 } else { 2121 bus->name = "mv88e6xxx SMI"; 2122 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2123 } 2124 2125 bus->read = mv88e6xxx_mdio_read; 2126 bus->write = mv88e6xxx_mdio_write; 2127 bus->parent = chip->dev; 2128 2129 if (np) 2130 err = of_mdiobus_register(bus, np); 2131 else 2132 err = mdiobus_register(bus); 2133 if (err) { 2134 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2135 return err; 2136 } 2137 2138 if (external) 2139 list_add_tail(&mdio_bus->list, &chip->mdios); 2140 else 2141 list_add(&mdio_bus->list, &chip->mdios); 2142 2143 return 0; 2144 } 2145 2146 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2147 { .compatible = "marvell,mv88e6xxx-mdio-external", 2148 .data = (void *)true }, 2149 { }, 2150 }; 2151 2152 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2153 struct device_node *np) 2154 { 2155 const struct of_device_id *match; 2156 struct device_node *child; 2157 int err; 2158 2159 /* Always register one mdio bus for the internal/default mdio 2160 * bus. This maybe represented in the device tree, but is 2161 * optional. 2162 */ 2163 child = of_get_child_by_name(np, "mdio"); 2164 err = mv88e6xxx_mdio_register(chip, child, false); 2165 if (err) 2166 return err; 2167 2168 /* Walk the device tree, and see if there are any other nodes 2169 * which say they are compatible with the external mdio 2170 * bus. 2171 */ 2172 for_each_available_child_of_node(np, child) { 2173 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2174 if (match) { 2175 err = mv88e6xxx_mdio_register(chip, child, true); 2176 if (err) 2177 return err; 2178 } 2179 } 2180 2181 return 0; 2182 } 2183 2184 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2185 2186 { 2187 struct mv88e6xxx_mdio_bus *mdio_bus; 2188 struct mii_bus *bus; 2189 2190 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2191 bus = mdio_bus->bus; 2192 2193 mdiobus_unregister(bus); 2194 } 2195 } 2196 2197 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2198 { 2199 struct mv88e6xxx_chip *chip = ds->priv; 2200 2201 return chip->eeprom_len; 2202 } 2203 2204 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2205 struct ethtool_eeprom *eeprom, u8 *data) 2206 { 2207 struct mv88e6xxx_chip *chip = ds->priv; 2208 int err; 2209 2210 if (!chip->info->ops->get_eeprom) 2211 return -EOPNOTSUPP; 2212 2213 mutex_lock(&chip->reg_lock); 2214 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2215 mutex_unlock(&chip->reg_lock); 2216 2217 if (err) 2218 return err; 2219 2220 eeprom->magic = 0xc3ec4951; 2221 2222 return 0; 2223 } 2224 2225 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2226 struct ethtool_eeprom *eeprom, u8 *data) 2227 { 2228 struct mv88e6xxx_chip *chip = ds->priv; 2229 int err; 2230 2231 if (!chip->info->ops->set_eeprom) 2232 return -EOPNOTSUPP; 2233 2234 if (eeprom->magic != 0xc3ec4951) 2235 return -EINVAL; 2236 2237 mutex_lock(&chip->reg_lock); 2238 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2239 mutex_unlock(&chip->reg_lock); 2240 2241 return err; 2242 } 2243 2244 static const struct mv88e6xxx_ops mv88e6085_ops = { 2245 /* MV88E6XXX_FAMILY_6097 */ 2246 .irl_init_all = mv88e6352_g2_irl_init_all, 2247 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2248 .phy_read = mv88e6185_phy_ppu_read, 2249 .phy_write = mv88e6185_phy_ppu_write, 2250 .port_set_link = mv88e6xxx_port_set_link, 2251 .port_set_duplex = mv88e6xxx_port_set_duplex, 2252 .port_set_speed = mv88e6185_port_set_speed, 2253 .port_tag_remap = mv88e6095_port_tag_remap, 2254 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2255 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2256 .port_set_ether_type = mv88e6351_port_set_ether_type, 2257 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2258 .port_pause_limit = mv88e6097_port_pause_limit, 2259 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2260 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2261 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2262 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2263 .stats_get_strings = mv88e6095_stats_get_strings, 2264 .stats_get_stats = mv88e6095_stats_get_stats, 2265 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2266 .set_egress_port = mv88e6095_g1_set_egress_port, 2267 .watchdog_ops = &mv88e6097_watchdog_ops, 2268 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2269 .pot_clear = mv88e6xxx_g2_pot_clear, 2270 .ppu_enable = mv88e6185_g1_ppu_enable, 2271 .ppu_disable = mv88e6185_g1_ppu_disable, 2272 .reset = mv88e6185_g1_reset, 2273 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2274 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2275 }; 2276 2277 static const struct mv88e6xxx_ops mv88e6095_ops = { 2278 /* MV88E6XXX_FAMILY_6095 */ 2279 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2280 .phy_read = mv88e6185_phy_ppu_read, 2281 .phy_write = mv88e6185_phy_ppu_write, 2282 .port_set_link = mv88e6xxx_port_set_link, 2283 .port_set_duplex = mv88e6xxx_port_set_duplex, 2284 .port_set_speed = mv88e6185_port_set_speed, 2285 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2286 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2287 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2288 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2289 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2290 .stats_get_strings = mv88e6095_stats_get_strings, 2291 .stats_get_stats = mv88e6095_stats_get_stats, 2292 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2293 .ppu_enable = mv88e6185_g1_ppu_enable, 2294 .ppu_disable = mv88e6185_g1_ppu_disable, 2295 .reset = mv88e6185_g1_reset, 2296 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2297 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2298 }; 2299 2300 static const struct mv88e6xxx_ops mv88e6097_ops = { 2301 /* MV88E6XXX_FAMILY_6097 */ 2302 .irl_init_all = mv88e6352_g2_irl_init_all, 2303 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2304 .phy_read = mv88e6xxx_g2_smi_phy_read, 2305 .phy_write = mv88e6xxx_g2_smi_phy_write, 2306 .port_set_link = mv88e6xxx_port_set_link, 2307 .port_set_duplex = mv88e6xxx_port_set_duplex, 2308 .port_set_speed = mv88e6185_port_set_speed, 2309 .port_tag_remap = mv88e6095_port_tag_remap, 2310 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2311 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2312 .port_set_ether_type = mv88e6351_port_set_ether_type, 2313 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2314 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2315 .port_pause_limit = mv88e6097_port_pause_limit, 2316 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2317 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2318 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2319 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2320 .stats_get_strings = mv88e6095_stats_get_strings, 2321 .stats_get_stats = mv88e6095_stats_get_stats, 2322 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2323 .set_egress_port = mv88e6095_g1_set_egress_port, 2324 .watchdog_ops = &mv88e6097_watchdog_ops, 2325 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2326 .pot_clear = mv88e6xxx_g2_pot_clear, 2327 .reset = mv88e6352_g1_reset, 2328 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2329 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2330 }; 2331 2332 static const struct mv88e6xxx_ops mv88e6123_ops = { 2333 /* MV88E6XXX_FAMILY_6165 */ 2334 .irl_init_all = mv88e6352_g2_irl_init_all, 2335 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2336 .phy_read = mv88e6xxx_g2_smi_phy_read, 2337 .phy_write = mv88e6xxx_g2_smi_phy_write, 2338 .port_set_link = mv88e6xxx_port_set_link, 2339 .port_set_duplex = mv88e6xxx_port_set_duplex, 2340 .port_set_speed = mv88e6185_port_set_speed, 2341 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2342 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2343 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2344 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2345 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2346 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2347 .stats_get_strings = mv88e6095_stats_get_strings, 2348 .stats_get_stats = mv88e6095_stats_get_stats, 2349 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2350 .set_egress_port = mv88e6095_g1_set_egress_port, 2351 .watchdog_ops = &mv88e6097_watchdog_ops, 2352 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2353 .pot_clear = mv88e6xxx_g2_pot_clear, 2354 .reset = mv88e6352_g1_reset, 2355 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2356 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2357 }; 2358 2359 static const struct mv88e6xxx_ops mv88e6131_ops = { 2360 /* MV88E6XXX_FAMILY_6185 */ 2361 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2362 .phy_read = mv88e6185_phy_ppu_read, 2363 .phy_write = mv88e6185_phy_ppu_write, 2364 .port_set_link = mv88e6xxx_port_set_link, 2365 .port_set_duplex = mv88e6xxx_port_set_duplex, 2366 .port_set_speed = mv88e6185_port_set_speed, 2367 .port_tag_remap = mv88e6095_port_tag_remap, 2368 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2369 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2370 .port_set_ether_type = mv88e6351_port_set_ether_type, 2371 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2372 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2373 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2374 .port_pause_limit = mv88e6097_port_pause_limit, 2375 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2376 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2377 .stats_get_strings = mv88e6095_stats_get_strings, 2378 .stats_get_stats = mv88e6095_stats_get_stats, 2379 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2380 .set_egress_port = mv88e6095_g1_set_egress_port, 2381 .watchdog_ops = &mv88e6097_watchdog_ops, 2382 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2383 .ppu_enable = mv88e6185_g1_ppu_enable, 2384 .ppu_disable = mv88e6185_g1_ppu_disable, 2385 .reset = mv88e6185_g1_reset, 2386 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2387 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2388 }; 2389 2390 static const struct mv88e6xxx_ops mv88e6141_ops = { 2391 /* MV88E6XXX_FAMILY_6341 */ 2392 .irl_init_all = mv88e6352_g2_irl_init_all, 2393 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2394 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2395 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2396 .phy_read = mv88e6xxx_g2_smi_phy_read, 2397 .phy_write = mv88e6xxx_g2_smi_phy_write, 2398 .port_set_link = mv88e6xxx_port_set_link, 2399 .port_set_duplex = mv88e6xxx_port_set_duplex, 2400 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2401 .port_set_speed = mv88e6390_port_set_speed, 2402 .port_tag_remap = mv88e6095_port_tag_remap, 2403 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2404 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2405 .port_set_ether_type = mv88e6351_port_set_ether_type, 2406 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2407 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2408 .port_pause_limit = mv88e6097_port_pause_limit, 2409 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2410 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2411 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2412 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2413 .stats_get_strings = mv88e6320_stats_get_strings, 2414 .stats_get_stats = mv88e6390_stats_get_stats, 2415 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2416 .set_egress_port = mv88e6390_g1_set_egress_port, 2417 .watchdog_ops = &mv88e6390_watchdog_ops, 2418 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2419 .pot_clear = mv88e6xxx_g2_pot_clear, 2420 .reset = mv88e6352_g1_reset, 2421 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2422 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2423 }; 2424 2425 static const struct mv88e6xxx_ops mv88e6161_ops = { 2426 /* MV88E6XXX_FAMILY_6165 */ 2427 .irl_init_all = mv88e6352_g2_irl_init_all, 2428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2429 .phy_read = mv88e6xxx_g2_smi_phy_read, 2430 .phy_write = mv88e6xxx_g2_smi_phy_write, 2431 .port_set_link = mv88e6xxx_port_set_link, 2432 .port_set_duplex = mv88e6xxx_port_set_duplex, 2433 .port_set_speed = mv88e6185_port_set_speed, 2434 .port_tag_remap = mv88e6095_port_tag_remap, 2435 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2436 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2437 .port_set_ether_type = mv88e6351_port_set_ether_type, 2438 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2439 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2440 .port_pause_limit = mv88e6097_port_pause_limit, 2441 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2442 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2443 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2444 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2445 .stats_get_strings = mv88e6095_stats_get_strings, 2446 .stats_get_stats = mv88e6095_stats_get_stats, 2447 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2448 .set_egress_port = mv88e6095_g1_set_egress_port, 2449 .watchdog_ops = &mv88e6097_watchdog_ops, 2450 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2451 .pot_clear = mv88e6xxx_g2_pot_clear, 2452 .reset = mv88e6352_g1_reset, 2453 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2454 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2455 }; 2456 2457 static const struct mv88e6xxx_ops mv88e6165_ops = { 2458 /* MV88E6XXX_FAMILY_6165 */ 2459 .irl_init_all = mv88e6352_g2_irl_init_all, 2460 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2461 .phy_read = mv88e6165_phy_read, 2462 .phy_write = mv88e6165_phy_write, 2463 .port_set_link = mv88e6xxx_port_set_link, 2464 .port_set_duplex = mv88e6xxx_port_set_duplex, 2465 .port_set_speed = mv88e6185_port_set_speed, 2466 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2467 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2468 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2469 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2470 .stats_get_strings = mv88e6095_stats_get_strings, 2471 .stats_get_stats = mv88e6095_stats_get_stats, 2472 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2473 .set_egress_port = mv88e6095_g1_set_egress_port, 2474 .watchdog_ops = &mv88e6097_watchdog_ops, 2475 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2476 .pot_clear = mv88e6xxx_g2_pot_clear, 2477 .reset = mv88e6352_g1_reset, 2478 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2479 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2480 }; 2481 2482 static const struct mv88e6xxx_ops mv88e6171_ops = { 2483 /* MV88E6XXX_FAMILY_6351 */ 2484 .irl_init_all = mv88e6352_g2_irl_init_all, 2485 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2486 .phy_read = mv88e6xxx_g2_smi_phy_read, 2487 .phy_write = mv88e6xxx_g2_smi_phy_write, 2488 .port_set_link = mv88e6xxx_port_set_link, 2489 .port_set_duplex = mv88e6xxx_port_set_duplex, 2490 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2491 .port_set_speed = mv88e6185_port_set_speed, 2492 .port_tag_remap = mv88e6095_port_tag_remap, 2493 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2494 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2495 .port_set_ether_type = mv88e6351_port_set_ether_type, 2496 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2497 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2498 .port_pause_limit = mv88e6097_port_pause_limit, 2499 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2500 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2501 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2502 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2503 .stats_get_strings = mv88e6095_stats_get_strings, 2504 .stats_get_stats = mv88e6095_stats_get_stats, 2505 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2506 .set_egress_port = mv88e6095_g1_set_egress_port, 2507 .watchdog_ops = &mv88e6097_watchdog_ops, 2508 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2509 .pot_clear = mv88e6xxx_g2_pot_clear, 2510 .reset = mv88e6352_g1_reset, 2511 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2512 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2513 }; 2514 2515 static const struct mv88e6xxx_ops mv88e6172_ops = { 2516 /* MV88E6XXX_FAMILY_6352 */ 2517 .irl_init_all = mv88e6352_g2_irl_init_all, 2518 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2519 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2520 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2521 .phy_read = mv88e6xxx_g2_smi_phy_read, 2522 .phy_write = mv88e6xxx_g2_smi_phy_write, 2523 .port_set_link = mv88e6xxx_port_set_link, 2524 .port_set_duplex = mv88e6xxx_port_set_duplex, 2525 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2526 .port_set_speed = mv88e6352_port_set_speed, 2527 .port_tag_remap = mv88e6095_port_tag_remap, 2528 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2529 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2530 .port_set_ether_type = mv88e6351_port_set_ether_type, 2531 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2532 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2533 .port_pause_limit = mv88e6097_port_pause_limit, 2534 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2535 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2536 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2537 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2538 .stats_get_strings = mv88e6095_stats_get_strings, 2539 .stats_get_stats = mv88e6095_stats_get_stats, 2540 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2541 .set_egress_port = mv88e6095_g1_set_egress_port, 2542 .watchdog_ops = &mv88e6097_watchdog_ops, 2543 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2544 .pot_clear = mv88e6xxx_g2_pot_clear, 2545 .reset = mv88e6352_g1_reset, 2546 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2547 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2548 .serdes_power = mv88e6352_serdes_power, 2549 }; 2550 2551 static const struct mv88e6xxx_ops mv88e6175_ops = { 2552 /* MV88E6XXX_FAMILY_6351 */ 2553 .irl_init_all = mv88e6352_g2_irl_init_all, 2554 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2555 .phy_read = mv88e6xxx_g2_smi_phy_read, 2556 .phy_write = mv88e6xxx_g2_smi_phy_write, 2557 .port_set_link = mv88e6xxx_port_set_link, 2558 .port_set_duplex = mv88e6xxx_port_set_duplex, 2559 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2560 .port_set_speed = mv88e6185_port_set_speed, 2561 .port_tag_remap = mv88e6095_port_tag_remap, 2562 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2563 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2564 .port_set_ether_type = mv88e6351_port_set_ether_type, 2565 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2566 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2567 .port_pause_limit = mv88e6097_port_pause_limit, 2568 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2569 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2570 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2571 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2572 .stats_get_strings = mv88e6095_stats_get_strings, 2573 .stats_get_stats = mv88e6095_stats_get_stats, 2574 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2575 .set_egress_port = mv88e6095_g1_set_egress_port, 2576 .watchdog_ops = &mv88e6097_watchdog_ops, 2577 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2578 .pot_clear = mv88e6xxx_g2_pot_clear, 2579 .reset = mv88e6352_g1_reset, 2580 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2581 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2582 }; 2583 2584 static const struct mv88e6xxx_ops mv88e6176_ops = { 2585 /* MV88E6XXX_FAMILY_6352 */ 2586 .irl_init_all = mv88e6352_g2_irl_init_all, 2587 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2588 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2589 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2590 .phy_read = mv88e6xxx_g2_smi_phy_read, 2591 .phy_write = mv88e6xxx_g2_smi_phy_write, 2592 .port_set_link = mv88e6xxx_port_set_link, 2593 .port_set_duplex = mv88e6xxx_port_set_duplex, 2594 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2595 .port_set_speed = mv88e6352_port_set_speed, 2596 .port_tag_remap = mv88e6095_port_tag_remap, 2597 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2598 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2599 .port_set_ether_type = mv88e6351_port_set_ether_type, 2600 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2601 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2602 .port_pause_limit = mv88e6097_port_pause_limit, 2603 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2604 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2605 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2606 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2607 .stats_get_strings = mv88e6095_stats_get_strings, 2608 .stats_get_stats = mv88e6095_stats_get_stats, 2609 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2610 .set_egress_port = mv88e6095_g1_set_egress_port, 2611 .watchdog_ops = &mv88e6097_watchdog_ops, 2612 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2613 .pot_clear = mv88e6xxx_g2_pot_clear, 2614 .reset = mv88e6352_g1_reset, 2615 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2616 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2617 .serdes_power = mv88e6352_serdes_power, 2618 }; 2619 2620 static const struct mv88e6xxx_ops mv88e6185_ops = { 2621 /* MV88E6XXX_FAMILY_6185 */ 2622 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2623 .phy_read = mv88e6185_phy_ppu_read, 2624 .phy_write = mv88e6185_phy_ppu_write, 2625 .port_set_link = mv88e6xxx_port_set_link, 2626 .port_set_duplex = mv88e6xxx_port_set_duplex, 2627 .port_set_speed = mv88e6185_port_set_speed, 2628 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2629 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2630 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2631 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2632 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2633 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2634 .stats_get_strings = mv88e6095_stats_get_strings, 2635 .stats_get_stats = mv88e6095_stats_get_stats, 2636 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2637 .set_egress_port = mv88e6095_g1_set_egress_port, 2638 .watchdog_ops = &mv88e6097_watchdog_ops, 2639 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2640 .ppu_enable = mv88e6185_g1_ppu_enable, 2641 .ppu_disable = mv88e6185_g1_ppu_disable, 2642 .reset = mv88e6185_g1_reset, 2643 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2644 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2645 }; 2646 2647 static const struct mv88e6xxx_ops mv88e6190_ops = { 2648 /* MV88E6XXX_FAMILY_6390 */ 2649 .irl_init_all = mv88e6390_g2_irl_init_all, 2650 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2651 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2652 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2653 .phy_read = mv88e6xxx_g2_smi_phy_read, 2654 .phy_write = mv88e6xxx_g2_smi_phy_write, 2655 .port_set_link = mv88e6xxx_port_set_link, 2656 .port_set_duplex = mv88e6xxx_port_set_duplex, 2657 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2658 .port_set_speed = mv88e6390_port_set_speed, 2659 .port_tag_remap = mv88e6390_port_tag_remap, 2660 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2661 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2662 .port_set_ether_type = mv88e6351_port_set_ether_type, 2663 .port_pause_limit = mv88e6390_port_pause_limit, 2664 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2665 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2666 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2667 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2668 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2669 .stats_get_strings = mv88e6320_stats_get_strings, 2670 .stats_get_stats = mv88e6390_stats_get_stats, 2671 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2672 .set_egress_port = mv88e6390_g1_set_egress_port, 2673 .watchdog_ops = &mv88e6390_watchdog_ops, 2674 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2675 .pot_clear = mv88e6xxx_g2_pot_clear, 2676 .reset = mv88e6352_g1_reset, 2677 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2678 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2679 .serdes_power = mv88e6390_serdes_power, 2680 }; 2681 2682 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2683 /* MV88E6XXX_FAMILY_6390 */ 2684 .irl_init_all = mv88e6390_g2_irl_init_all, 2685 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2686 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2687 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2688 .phy_read = mv88e6xxx_g2_smi_phy_read, 2689 .phy_write = mv88e6xxx_g2_smi_phy_write, 2690 .port_set_link = mv88e6xxx_port_set_link, 2691 .port_set_duplex = mv88e6xxx_port_set_duplex, 2692 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2693 .port_set_speed = mv88e6390x_port_set_speed, 2694 .port_tag_remap = mv88e6390_port_tag_remap, 2695 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2696 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2697 .port_set_ether_type = mv88e6351_port_set_ether_type, 2698 .port_pause_limit = mv88e6390_port_pause_limit, 2699 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2700 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2701 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2702 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2703 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2704 .stats_get_strings = mv88e6320_stats_get_strings, 2705 .stats_get_stats = mv88e6390_stats_get_stats, 2706 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2707 .set_egress_port = mv88e6390_g1_set_egress_port, 2708 .watchdog_ops = &mv88e6390_watchdog_ops, 2709 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2710 .pot_clear = mv88e6xxx_g2_pot_clear, 2711 .reset = mv88e6352_g1_reset, 2712 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2713 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2714 .serdes_power = mv88e6390_serdes_power, 2715 }; 2716 2717 static const struct mv88e6xxx_ops mv88e6191_ops = { 2718 /* MV88E6XXX_FAMILY_6390 */ 2719 .irl_init_all = mv88e6390_g2_irl_init_all, 2720 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2721 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2722 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2723 .phy_read = mv88e6xxx_g2_smi_phy_read, 2724 .phy_write = mv88e6xxx_g2_smi_phy_write, 2725 .port_set_link = mv88e6xxx_port_set_link, 2726 .port_set_duplex = mv88e6xxx_port_set_duplex, 2727 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2728 .port_set_speed = mv88e6390_port_set_speed, 2729 .port_tag_remap = mv88e6390_port_tag_remap, 2730 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2731 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2732 .port_set_ether_type = mv88e6351_port_set_ether_type, 2733 .port_pause_limit = mv88e6390_port_pause_limit, 2734 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2735 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2736 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2737 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2738 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2739 .stats_get_strings = mv88e6320_stats_get_strings, 2740 .stats_get_stats = mv88e6390_stats_get_stats, 2741 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2742 .set_egress_port = mv88e6390_g1_set_egress_port, 2743 .watchdog_ops = &mv88e6390_watchdog_ops, 2744 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2745 .pot_clear = mv88e6xxx_g2_pot_clear, 2746 .reset = mv88e6352_g1_reset, 2747 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2748 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2749 .serdes_power = mv88e6390_serdes_power, 2750 }; 2751 2752 static const struct mv88e6xxx_ops mv88e6240_ops = { 2753 /* MV88E6XXX_FAMILY_6352 */ 2754 .irl_init_all = mv88e6352_g2_irl_init_all, 2755 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2756 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2757 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2758 .phy_read = mv88e6xxx_g2_smi_phy_read, 2759 .phy_write = mv88e6xxx_g2_smi_phy_write, 2760 .port_set_link = mv88e6xxx_port_set_link, 2761 .port_set_duplex = mv88e6xxx_port_set_duplex, 2762 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2763 .port_set_speed = mv88e6352_port_set_speed, 2764 .port_tag_remap = mv88e6095_port_tag_remap, 2765 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2766 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2767 .port_set_ether_type = mv88e6351_port_set_ether_type, 2768 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2769 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2770 .port_pause_limit = mv88e6097_port_pause_limit, 2771 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2772 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2773 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2774 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2775 .stats_get_strings = mv88e6095_stats_get_strings, 2776 .stats_get_stats = mv88e6095_stats_get_stats, 2777 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2778 .set_egress_port = mv88e6095_g1_set_egress_port, 2779 .watchdog_ops = &mv88e6097_watchdog_ops, 2780 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2781 .pot_clear = mv88e6xxx_g2_pot_clear, 2782 .reset = mv88e6352_g1_reset, 2783 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2784 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2785 .serdes_power = mv88e6352_serdes_power, 2786 }; 2787 2788 static const struct mv88e6xxx_ops mv88e6290_ops = { 2789 /* MV88E6XXX_FAMILY_6390 */ 2790 .irl_init_all = mv88e6390_g2_irl_init_all, 2791 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2792 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2793 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2794 .phy_read = mv88e6xxx_g2_smi_phy_read, 2795 .phy_write = mv88e6xxx_g2_smi_phy_write, 2796 .port_set_link = mv88e6xxx_port_set_link, 2797 .port_set_duplex = mv88e6xxx_port_set_duplex, 2798 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2799 .port_set_speed = mv88e6390_port_set_speed, 2800 .port_tag_remap = mv88e6390_port_tag_remap, 2801 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2802 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2803 .port_set_ether_type = mv88e6351_port_set_ether_type, 2804 .port_pause_limit = mv88e6390_port_pause_limit, 2805 .port_set_cmode = mv88e6390x_port_set_cmode, 2806 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2807 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2808 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2809 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2810 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2811 .stats_get_strings = mv88e6320_stats_get_strings, 2812 .stats_get_stats = mv88e6390_stats_get_stats, 2813 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2814 .set_egress_port = mv88e6390_g1_set_egress_port, 2815 .watchdog_ops = &mv88e6390_watchdog_ops, 2816 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2817 .pot_clear = mv88e6xxx_g2_pot_clear, 2818 .reset = mv88e6352_g1_reset, 2819 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2820 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2821 .serdes_power = mv88e6390_serdes_power, 2822 }; 2823 2824 static const struct mv88e6xxx_ops mv88e6320_ops = { 2825 /* MV88E6XXX_FAMILY_6320 */ 2826 .irl_init_all = mv88e6352_g2_irl_init_all, 2827 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2828 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2829 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2830 .phy_read = mv88e6xxx_g2_smi_phy_read, 2831 .phy_write = mv88e6xxx_g2_smi_phy_write, 2832 .port_set_link = mv88e6xxx_port_set_link, 2833 .port_set_duplex = mv88e6xxx_port_set_duplex, 2834 .port_set_speed = mv88e6185_port_set_speed, 2835 .port_tag_remap = mv88e6095_port_tag_remap, 2836 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2837 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2838 .port_set_ether_type = mv88e6351_port_set_ether_type, 2839 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2840 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2841 .port_pause_limit = mv88e6097_port_pause_limit, 2842 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2843 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2844 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2845 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2846 .stats_get_strings = mv88e6320_stats_get_strings, 2847 .stats_get_stats = mv88e6320_stats_get_stats, 2848 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2849 .set_egress_port = mv88e6095_g1_set_egress_port, 2850 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2851 .pot_clear = mv88e6xxx_g2_pot_clear, 2852 .reset = mv88e6352_g1_reset, 2853 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2854 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2855 }; 2856 2857 static const struct mv88e6xxx_ops mv88e6321_ops = { 2858 /* MV88E6XXX_FAMILY_6320 */ 2859 .irl_init_all = mv88e6352_g2_irl_init_all, 2860 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2861 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2862 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2863 .phy_read = mv88e6xxx_g2_smi_phy_read, 2864 .phy_write = mv88e6xxx_g2_smi_phy_write, 2865 .port_set_link = mv88e6xxx_port_set_link, 2866 .port_set_duplex = mv88e6xxx_port_set_duplex, 2867 .port_set_speed = mv88e6185_port_set_speed, 2868 .port_tag_remap = mv88e6095_port_tag_remap, 2869 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2870 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2871 .port_set_ether_type = mv88e6351_port_set_ether_type, 2872 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2873 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2874 .port_pause_limit = mv88e6097_port_pause_limit, 2875 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2876 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2877 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2878 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2879 .stats_get_strings = mv88e6320_stats_get_strings, 2880 .stats_get_stats = mv88e6320_stats_get_stats, 2881 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2882 .set_egress_port = mv88e6095_g1_set_egress_port, 2883 .reset = mv88e6352_g1_reset, 2884 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2885 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2886 }; 2887 2888 static const struct mv88e6xxx_ops mv88e6341_ops = { 2889 /* MV88E6XXX_FAMILY_6341 */ 2890 .irl_init_all = mv88e6352_g2_irl_init_all, 2891 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2892 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2893 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2894 .phy_read = mv88e6xxx_g2_smi_phy_read, 2895 .phy_write = mv88e6xxx_g2_smi_phy_write, 2896 .port_set_link = mv88e6xxx_port_set_link, 2897 .port_set_duplex = mv88e6xxx_port_set_duplex, 2898 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2899 .port_set_speed = mv88e6390_port_set_speed, 2900 .port_tag_remap = mv88e6095_port_tag_remap, 2901 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2902 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2903 .port_set_ether_type = mv88e6351_port_set_ether_type, 2904 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2905 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2906 .port_pause_limit = mv88e6097_port_pause_limit, 2907 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2908 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2909 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2910 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2911 .stats_get_strings = mv88e6320_stats_get_strings, 2912 .stats_get_stats = mv88e6390_stats_get_stats, 2913 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2914 .set_egress_port = mv88e6390_g1_set_egress_port, 2915 .watchdog_ops = &mv88e6390_watchdog_ops, 2916 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2917 .pot_clear = mv88e6xxx_g2_pot_clear, 2918 .reset = mv88e6352_g1_reset, 2919 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2920 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2921 }; 2922 2923 static const struct mv88e6xxx_ops mv88e6350_ops = { 2924 /* MV88E6XXX_FAMILY_6351 */ 2925 .irl_init_all = mv88e6352_g2_irl_init_all, 2926 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2927 .phy_read = mv88e6xxx_g2_smi_phy_read, 2928 .phy_write = mv88e6xxx_g2_smi_phy_write, 2929 .port_set_link = mv88e6xxx_port_set_link, 2930 .port_set_duplex = mv88e6xxx_port_set_duplex, 2931 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2932 .port_set_speed = mv88e6185_port_set_speed, 2933 .port_tag_remap = mv88e6095_port_tag_remap, 2934 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2935 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2936 .port_set_ether_type = mv88e6351_port_set_ether_type, 2937 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2938 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2939 .port_pause_limit = mv88e6097_port_pause_limit, 2940 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2941 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2942 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2943 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2944 .stats_get_strings = mv88e6095_stats_get_strings, 2945 .stats_get_stats = mv88e6095_stats_get_stats, 2946 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2947 .set_egress_port = mv88e6095_g1_set_egress_port, 2948 .watchdog_ops = &mv88e6097_watchdog_ops, 2949 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2950 .pot_clear = mv88e6xxx_g2_pot_clear, 2951 .reset = mv88e6352_g1_reset, 2952 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2953 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2954 }; 2955 2956 static const struct mv88e6xxx_ops mv88e6351_ops = { 2957 /* MV88E6XXX_FAMILY_6351 */ 2958 .irl_init_all = mv88e6352_g2_irl_init_all, 2959 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2960 .phy_read = mv88e6xxx_g2_smi_phy_read, 2961 .phy_write = mv88e6xxx_g2_smi_phy_write, 2962 .port_set_link = mv88e6xxx_port_set_link, 2963 .port_set_duplex = mv88e6xxx_port_set_duplex, 2964 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2965 .port_set_speed = mv88e6185_port_set_speed, 2966 .port_tag_remap = mv88e6095_port_tag_remap, 2967 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2968 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2969 .port_set_ether_type = mv88e6351_port_set_ether_type, 2970 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2971 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2972 .port_pause_limit = mv88e6097_port_pause_limit, 2973 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2974 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2975 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2976 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2977 .stats_get_strings = mv88e6095_stats_get_strings, 2978 .stats_get_stats = mv88e6095_stats_get_stats, 2979 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2980 .set_egress_port = mv88e6095_g1_set_egress_port, 2981 .watchdog_ops = &mv88e6097_watchdog_ops, 2982 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2983 .pot_clear = mv88e6xxx_g2_pot_clear, 2984 .reset = mv88e6352_g1_reset, 2985 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2986 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2987 }; 2988 2989 static const struct mv88e6xxx_ops mv88e6352_ops = { 2990 /* MV88E6XXX_FAMILY_6352 */ 2991 .irl_init_all = mv88e6352_g2_irl_init_all, 2992 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2993 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2994 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2995 .phy_read = mv88e6xxx_g2_smi_phy_read, 2996 .phy_write = mv88e6xxx_g2_smi_phy_write, 2997 .port_set_link = mv88e6xxx_port_set_link, 2998 .port_set_duplex = mv88e6xxx_port_set_duplex, 2999 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3000 .port_set_speed = mv88e6352_port_set_speed, 3001 .port_tag_remap = mv88e6095_port_tag_remap, 3002 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3003 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3004 .port_set_ether_type = mv88e6351_port_set_ether_type, 3005 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3006 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3007 .port_pause_limit = mv88e6097_port_pause_limit, 3008 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3009 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3010 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3011 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3012 .stats_get_strings = mv88e6095_stats_get_strings, 3013 .stats_get_stats = mv88e6095_stats_get_stats, 3014 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3015 .set_egress_port = mv88e6095_g1_set_egress_port, 3016 .watchdog_ops = &mv88e6097_watchdog_ops, 3017 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3018 .pot_clear = mv88e6xxx_g2_pot_clear, 3019 .reset = mv88e6352_g1_reset, 3020 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3021 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3022 .serdes_power = mv88e6352_serdes_power, 3023 }; 3024 3025 static const struct mv88e6xxx_ops mv88e6390_ops = { 3026 /* MV88E6XXX_FAMILY_6390 */ 3027 .irl_init_all = mv88e6390_g2_irl_init_all, 3028 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3029 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3030 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3031 .phy_read = mv88e6xxx_g2_smi_phy_read, 3032 .phy_write = mv88e6xxx_g2_smi_phy_write, 3033 .port_set_link = mv88e6xxx_port_set_link, 3034 .port_set_duplex = mv88e6xxx_port_set_duplex, 3035 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3036 .port_set_speed = mv88e6390_port_set_speed, 3037 .port_tag_remap = mv88e6390_port_tag_remap, 3038 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3039 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3040 .port_set_ether_type = mv88e6351_port_set_ether_type, 3041 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3042 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3043 .port_pause_limit = mv88e6390_port_pause_limit, 3044 .port_set_cmode = mv88e6390x_port_set_cmode, 3045 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3046 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3047 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3048 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3049 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3050 .stats_get_strings = mv88e6320_stats_get_strings, 3051 .stats_get_stats = mv88e6390_stats_get_stats, 3052 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3053 .set_egress_port = mv88e6390_g1_set_egress_port, 3054 .watchdog_ops = &mv88e6390_watchdog_ops, 3055 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3056 .pot_clear = mv88e6xxx_g2_pot_clear, 3057 .reset = mv88e6352_g1_reset, 3058 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3059 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3060 .serdes_power = mv88e6390_serdes_power, 3061 }; 3062 3063 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3064 /* MV88E6XXX_FAMILY_6390 */ 3065 .irl_init_all = mv88e6390_g2_irl_init_all, 3066 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3067 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3068 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3069 .phy_read = mv88e6xxx_g2_smi_phy_read, 3070 .phy_write = mv88e6xxx_g2_smi_phy_write, 3071 .port_set_link = mv88e6xxx_port_set_link, 3072 .port_set_duplex = mv88e6xxx_port_set_duplex, 3073 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3074 .port_set_speed = mv88e6390x_port_set_speed, 3075 .port_tag_remap = mv88e6390_port_tag_remap, 3076 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3077 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3078 .port_set_ether_type = mv88e6351_port_set_ether_type, 3079 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3080 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3081 .port_pause_limit = mv88e6390_port_pause_limit, 3082 .port_set_cmode = mv88e6390x_port_set_cmode, 3083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3085 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3086 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3087 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3088 .stats_get_strings = mv88e6320_stats_get_strings, 3089 .stats_get_stats = mv88e6390_stats_get_stats, 3090 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3091 .set_egress_port = mv88e6390_g1_set_egress_port, 3092 .watchdog_ops = &mv88e6390_watchdog_ops, 3093 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3094 .pot_clear = mv88e6xxx_g2_pot_clear, 3095 .reset = mv88e6352_g1_reset, 3096 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3097 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3098 .serdes_power = mv88e6390_serdes_power, 3099 }; 3100 3101 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3102 [MV88E6085] = { 3103 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3104 .family = MV88E6XXX_FAMILY_6097, 3105 .name = "Marvell 88E6085", 3106 .num_databases = 4096, 3107 .num_ports = 10, 3108 .max_vid = 4095, 3109 .port_base_addr = 0x10, 3110 .global1_addr = 0x1b, 3111 .global2_addr = 0x1c, 3112 .age_time_coeff = 15000, 3113 .g1_irqs = 8, 3114 .g2_irqs = 10, 3115 .atu_move_port_mask = 0xf, 3116 .pvt = true, 3117 .multi_chip = true, 3118 .tag_protocol = DSA_TAG_PROTO_DSA, 3119 .ops = &mv88e6085_ops, 3120 }, 3121 3122 [MV88E6095] = { 3123 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3124 .family = MV88E6XXX_FAMILY_6095, 3125 .name = "Marvell 88E6095/88E6095F", 3126 .num_databases = 256, 3127 .num_ports = 11, 3128 .max_vid = 4095, 3129 .port_base_addr = 0x10, 3130 .global1_addr = 0x1b, 3131 .global2_addr = 0x1c, 3132 .age_time_coeff = 15000, 3133 .g1_irqs = 8, 3134 .atu_move_port_mask = 0xf, 3135 .multi_chip = true, 3136 .tag_protocol = DSA_TAG_PROTO_DSA, 3137 .ops = &mv88e6095_ops, 3138 }, 3139 3140 [MV88E6097] = { 3141 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3142 .family = MV88E6XXX_FAMILY_6097, 3143 .name = "Marvell 88E6097/88E6097F", 3144 .num_databases = 4096, 3145 .num_ports = 11, 3146 .max_vid = 4095, 3147 .port_base_addr = 0x10, 3148 .global1_addr = 0x1b, 3149 .global2_addr = 0x1c, 3150 .age_time_coeff = 15000, 3151 .g1_irqs = 8, 3152 .g2_irqs = 10, 3153 .atu_move_port_mask = 0xf, 3154 .pvt = true, 3155 .multi_chip = true, 3156 .tag_protocol = DSA_TAG_PROTO_EDSA, 3157 .ops = &mv88e6097_ops, 3158 }, 3159 3160 [MV88E6123] = { 3161 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3162 .family = MV88E6XXX_FAMILY_6165, 3163 .name = "Marvell 88E6123", 3164 .num_databases = 4096, 3165 .num_ports = 3, 3166 .max_vid = 4095, 3167 .port_base_addr = 0x10, 3168 .global1_addr = 0x1b, 3169 .global2_addr = 0x1c, 3170 .age_time_coeff = 15000, 3171 .g1_irqs = 9, 3172 .g2_irqs = 10, 3173 .atu_move_port_mask = 0xf, 3174 .pvt = true, 3175 .multi_chip = true, 3176 .tag_protocol = DSA_TAG_PROTO_EDSA, 3177 .ops = &mv88e6123_ops, 3178 }, 3179 3180 [MV88E6131] = { 3181 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3182 .family = MV88E6XXX_FAMILY_6185, 3183 .name = "Marvell 88E6131", 3184 .num_databases = 256, 3185 .num_ports = 8, 3186 .max_vid = 4095, 3187 .port_base_addr = 0x10, 3188 .global1_addr = 0x1b, 3189 .global2_addr = 0x1c, 3190 .age_time_coeff = 15000, 3191 .g1_irqs = 9, 3192 .atu_move_port_mask = 0xf, 3193 .multi_chip = true, 3194 .tag_protocol = DSA_TAG_PROTO_DSA, 3195 .ops = &mv88e6131_ops, 3196 }, 3197 3198 [MV88E6141] = { 3199 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3200 .family = MV88E6XXX_FAMILY_6341, 3201 .name = "Marvell 88E6341", 3202 .num_databases = 4096, 3203 .num_ports = 6, 3204 .max_vid = 4095, 3205 .port_base_addr = 0x10, 3206 .global1_addr = 0x1b, 3207 .global2_addr = 0x1c, 3208 .age_time_coeff = 3750, 3209 .atu_move_port_mask = 0x1f, 3210 .g2_irqs = 10, 3211 .pvt = true, 3212 .multi_chip = true, 3213 .tag_protocol = DSA_TAG_PROTO_EDSA, 3214 .ops = &mv88e6141_ops, 3215 }, 3216 3217 [MV88E6161] = { 3218 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3219 .family = MV88E6XXX_FAMILY_6165, 3220 .name = "Marvell 88E6161", 3221 .num_databases = 4096, 3222 .num_ports = 6, 3223 .max_vid = 4095, 3224 .port_base_addr = 0x10, 3225 .global1_addr = 0x1b, 3226 .global2_addr = 0x1c, 3227 .age_time_coeff = 15000, 3228 .g1_irqs = 9, 3229 .g2_irqs = 10, 3230 .atu_move_port_mask = 0xf, 3231 .pvt = true, 3232 .multi_chip = true, 3233 .tag_protocol = DSA_TAG_PROTO_EDSA, 3234 .ops = &mv88e6161_ops, 3235 }, 3236 3237 [MV88E6165] = { 3238 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3239 .family = MV88E6XXX_FAMILY_6165, 3240 .name = "Marvell 88E6165", 3241 .num_databases = 4096, 3242 .num_ports = 6, 3243 .max_vid = 4095, 3244 .port_base_addr = 0x10, 3245 .global1_addr = 0x1b, 3246 .global2_addr = 0x1c, 3247 .age_time_coeff = 15000, 3248 .g1_irqs = 9, 3249 .g2_irqs = 10, 3250 .atu_move_port_mask = 0xf, 3251 .pvt = true, 3252 .multi_chip = true, 3253 .tag_protocol = DSA_TAG_PROTO_DSA, 3254 .ops = &mv88e6165_ops, 3255 }, 3256 3257 [MV88E6171] = { 3258 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3259 .family = MV88E6XXX_FAMILY_6351, 3260 .name = "Marvell 88E6171", 3261 .num_databases = 4096, 3262 .num_ports = 7, 3263 .max_vid = 4095, 3264 .port_base_addr = 0x10, 3265 .global1_addr = 0x1b, 3266 .global2_addr = 0x1c, 3267 .age_time_coeff = 15000, 3268 .g1_irqs = 9, 3269 .g2_irqs = 10, 3270 .atu_move_port_mask = 0xf, 3271 .pvt = true, 3272 .multi_chip = true, 3273 .tag_protocol = DSA_TAG_PROTO_EDSA, 3274 .ops = &mv88e6171_ops, 3275 }, 3276 3277 [MV88E6172] = { 3278 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3279 .family = MV88E6XXX_FAMILY_6352, 3280 .name = "Marvell 88E6172", 3281 .num_databases = 4096, 3282 .num_ports = 7, 3283 .max_vid = 4095, 3284 .port_base_addr = 0x10, 3285 .global1_addr = 0x1b, 3286 .global2_addr = 0x1c, 3287 .age_time_coeff = 15000, 3288 .g1_irqs = 9, 3289 .g2_irqs = 10, 3290 .atu_move_port_mask = 0xf, 3291 .pvt = true, 3292 .multi_chip = true, 3293 .tag_protocol = DSA_TAG_PROTO_EDSA, 3294 .ops = &mv88e6172_ops, 3295 }, 3296 3297 [MV88E6175] = { 3298 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3299 .family = MV88E6XXX_FAMILY_6351, 3300 .name = "Marvell 88E6175", 3301 .num_databases = 4096, 3302 .num_ports = 7, 3303 .max_vid = 4095, 3304 .port_base_addr = 0x10, 3305 .global1_addr = 0x1b, 3306 .global2_addr = 0x1c, 3307 .age_time_coeff = 15000, 3308 .g1_irqs = 9, 3309 .g2_irqs = 10, 3310 .atu_move_port_mask = 0xf, 3311 .pvt = true, 3312 .multi_chip = true, 3313 .tag_protocol = DSA_TAG_PROTO_EDSA, 3314 .ops = &mv88e6175_ops, 3315 }, 3316 3317 [MV88E6176] = { 3318 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3319 .family = MV88E6XXX_FAMILY_6352, 3320 .name = "Marvell 88E6176", 3321 .num_databases = 4096, 3322 .num_ports = 7, 3323 .max_vid = 4095, 3324 .port_base_addr = 0x10, 3325 .global1_addr = 0x1b, 3326 .global2_addr = 0x1c, 3327 .age_time_coeff = 15000, 3328 .g1_irqs = 9, 3329 .g2_irqs = 10, 3330 .atu_move_port_mask = 0xf, 3331 .pvt = true, 3332 .multi_chip = true, 3333 .tag_protocol = DSA_TAG_PROTO_EDSA, 3334 .ops = &mv88e6176_ops, 3335 }, 3336 3337 [MV88E6185] = { 3338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3339 .family = MV88E6XXX_FAMILY_6185, 3340 .name = "Marvell 88E6185", 3341 .num_databases = 256, 3342 .num_ports = 10, 3343 .max_vid = 4095, 3344 .port_base_addr = 0x10, 3345 .global1_addr = 0x1b, 3346 .global2_addr = 0x1c, 3347 .age_time_coeff = 15000, 3348 .g1_irqs = 8, 3349 .atu_move_port_mask = 0xf, 3350 .multi_chip = true, 3351 .tag_protocol = DSA_TAG_PROTO_EDSA, 3352 .ops = &mv88e6185_ops, 3353 }, 3354 3355 [MV88E6190] = { 3356 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3357 .family = MV88E6XXX_FAMILY_6390, 3358 .name = "Marvell 88E6190", 3359 .num_databases = 4096, 3360 .num_ports = 11, /* 10 + Z80 */ 3361 .max_vid = 8191, 3362 .port_base_addr = 0x0, 3363 .global1_addr = 0x1b, 3364 .global2_addr = 0x1c, 3365 .tag_protocol = DSA_TAG_PROTO_DSA, 3366 .age_time_coeff = 3750, 3367 .g1_irqs = 9, 3368 .g2_irqs = 14, 3369 .pvt = true, 3370 .multi_chip = true, 3371 .atu_move_port_mask = 0x1f, 3372 .ops = &mv88e6190_ops, 3373 }, 3374 3375 [MV88E6190X] = { 3376 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3377 .family = MV88E6XXX_FAMILY_6390, 3378 .name = "Marvell 88E6190X", 3379 .num_databases = 4096, 3380 .num_ports = 11, /* 10 + Z80 */ 3381 .max_vid = 8191, 3382 .port_base_addr = 0x0, 3383 .global1_addr = 0x1b, 3384 .global2_addr = 0x1c, 3385 .age_time_coeff = 3750, 3386 .g1_irqs = 9, 3387 .g2_irqs = 14, 3388 .atu_move_port_mask = 0x1f, 3389 .pvt = true, 3390 .multi_chip = true, 3391 .tag_protocol = DSA_TAG_PROTO_DSA, 3392 .ops = &mv88e6190x_ops, 3393 }, 3394 3395 [MV88E6191] = { 3396 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3397 .family = MV88E6XXX_FAMILY_6390, 3398 .name = "Marvell 88E6191", 3399 .num_databases = 4096, 3400 .num_ports = 11, /* 10 + Z80 */ 3401 .max_vid = 8191, 3402 .port_base_addr = 0x0, 3403 .global1_addr = 0x1b, 3404 .global2_addr = 0x1c, 3405 .age_time_coeff = 3750, 3406 .g1_irqs = 9, 3407 .g2_irqs = 14, 3408 .atu_move_port_mask = 0x1f, 3409 .pvt = true, 3410 .multi_chip = true, 3411 .tag_protocol = DSA_TAG_PROTO_DSA, 3412 .ops = &mv88e6191_ops, 3413 }, 3414 3415 [MV88E6240] = { 3416 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3417 .family = MV88E6XXX_FAMILY_6352, 3418 .name = "Marvell 88E6240", 3419 .num_databases = 4096, 3420 .num_ports = 7, 3421 .max_vid = 4095, 3422 .port_base_addr = 0x10, 3423 .global1_addr = 0x1b, 3424 .global2_addr = 0x1c, 3425 .age_time_coeff = 15000, 3426 .g1_irqs = 9, 3427 .g2_irqs = 10, 3428 .atu_move_port_mask = 0xf, 3429 .pvt = true, 3430 .multi_chip = true, 3431 .tag_protocol = DSA_TAG_PROTO_EDSA, 3432 .ops = &mv88e6240_ops, 3433 }, 3434 3435 [MV88E6290] = { 3436 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3437 .family = MV88E6XXX_FAMILY_6390, 3438 .name = "Marvell 88E6290", 3439 .num_databases = 4096, 3440 .num_ports = 11, /* 10 + Z80 */ 3441 .max_vid = 8191, 3442 .port_base_addr = 0x0, 3443 .global1_addr = 0x1b, 3444 .global2_addr = 0x1c, 3445 .age_time_coeff = 3750, 3446 .g1_irqs = 9, 3447 .g2_irqs = 14, 3448 .atu_move_port_mask = 0x1f, 3449 .pvt = true, 3450 .multi_chip = true, 3451 .tag_protocol = DSA_TAG_PROTO_DSA, 3452 .ops = &mv88e6290_ops, 3453 }, 3454 3455 [MV88E6320] = { 3456 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3457 .family = MV88E6XXX_FAMILY_6320, 3458 .name = "Marvell 88E6320", 3459 .num_databases = 4096, 3460 .num_ports = 7, 3461 .max_vid = 4095, 3462 .port_base_addr = 0x10, 3463 .global1_addr = 0x1b, 3464 .global2_addr = 0x1c, 3465 .age_time_coeff = 15000, 3466 .g1_irqs = 8, 3467 .atu_move_port_mask = 0xf, 3468 .pvt = true, 3469 .multi_chip = true, 3470 .tag_protocol = DSA_TAG_PROTO_EDSA, 3471 .ops = &mv88e6320_ops, 3472 }, 3473 3474 [MV88E6321] = { 3475 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3476 .family = MV88E6XXX_FAMILY_6320, 3477 .name = "Marvell 88E6321", 3478 .num_databases = 4096, 3479 .num_ports = 7, 3480 .max_vid = 4095, 3481 .port_base_addr = 0x10, 3482 .global1_addr = 0x1b, 3483 .global2_addr = 0x1c, 3484 .age_time_coeff = 15000, 3485 .g1_irqs = 8, 3486 .atu_move_port_mask = 0xf, 3487 .multi_chip = true, 3488 .tag_protocol = DSA_TAG_PROTO_EDSA, 3489 .ops = &mv88e6321_ops, 3490 }, 3491 3492 [MV88E6341] = { 3493 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3494 .family = MV88E6XXX_FAMILY_6341, 3495 .name = "Marvell 88E6341", 3496 .num_databases = 4096, 3497 .num_ports = 6, 3498 .max_vid = 4095, 3499 .port_base_addr = 0x10, 3500 .global1_addr = 0x1b, 3501 .global2_addr = 0x1c, 3502 .age_time_coeff = 3750, 3503 .atu_move_port_mask = 0x1f, 3504 .g2_irqs = 10, 3505 .pvt = true, 3506 .multi_chip = true, 3507 .tag_protocol = DSA_TAG_PROTO_EDSA, 3508 .ops = &mv88e6341_ops, 3509 }, 3510 3511 [MV88E6350] = { 3512 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3513 .family = MV88E6XXX_FAMILY_6351, 3514 .name = "Marvell 88E6350", 3515 .num_databases = 4096, 3516 .num_ports = 7, 3517 .max_vid = 4095, 3518 .port_base_addr = 0x10, 3519 .global1_addr = 0x1b, 3520 .global2_addr = 0x1c, 3521 .age_time_coeff = 15000, 3522 .g1_irqs = 9, 3523 .g2_irqs = 10, 3524 .atu_move_port_mask = 0xf, 3525 .pvt = true, 3526 .multi_chip = true, 3527 .tag_protocol = DSA_TAG_PROTO_EDSA, 3528 .ops = &mv88e6350_ops, 3529 }, 3530 3531 [MV88E6351] = { 3532 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3533 .family = MV88E6XXX_FAMILY_6351, 3534 .name = "Marvell 88E6351", 3535 .num_databases = 4096, 3536 .num_ports = 7, 3537 .max_vid = 4095, 3538 .port_base_addr = 0x10, 3539 .global1_addr = 0x1b, 3540 .global2_addr = 0x1c, 3541 .age_time_coeff = 15000, 3542 .g1_irqs = 9, 3543 .g2_irqs = 10, 3544 .atu_move_port_mask = 0xf, 3545 .pvt = true, 3546 .multi_chip = true, 3547 .tag_protocol = DSA_TAG_PROTO_EDSA, 3548 .ops = &mv88e6351_ops, 3549 }, 3550 3551 [MV88E6352] = { 3552 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3553 .family = MV88E6XXX_FAMILY_6352, 3554 .name = "Marvell 88E6352", 3555 .num_databases = 4096, 3556 .num_ports = 7, 3557 .max_vid = 4095, 3558 .port_base_addr = 0x10, 3559 .global1_addr = 0x1b, 3560 .global2_addr = 0x1c, 3561 .age_time_coeff = 15000, 3562 .g1_irqs = 9, 3563 .g2_irqs = 10, 3564 .atu_move_port_mask = 0xf, 3565 .pvt = true, 3566 .multi_chip = true, 3567 .tag_protocol = DSA_TAG_PROTO_EDSA, 3568 .ops = &mv88e6352_ops, 3569 }, 3570 [MV88E6390] = { 3571 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3572 .family = MV88E6XXX_FAMILY_6390, 3573 .name = "Marvell 88E6390", 3574 .num_databases = 4096, 3575 .num_ports = 11, /* 10 + Z80 */ 3576 .max_vid = 8191, 3577 .port_base_addr = 0x0, 3578 .global1_addr = 0x1b, 3579 .global2_addr = 0x1c, 3580 .age_time_coeff = 3750, 3581 .g1_irqs = 9, 3582 .g2_irqs = 14, 3583 .atu_move_port_mask = 0x1f, 3584 .pvt = true, 3585 .multi_chip = true, 3586 .tag_protocol = DSA_TAG_PROTO_DSA, 3587 .ops = &mv88e6390_ops, 3588 }, 3589 [MV88E6390X] = { 3590 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3591 .family = MV88E6XXX_FAMILY_6390, 3592 .name = "Marvell 88E6390X", 3593 .num_databases = 4096, 3594 .num_ports = 11, /* 10 + Z80 */ 3595 .max_vid = 8191, 3596 .port_base_addr = 0x0, 3597 .global1_addr = 0x1b, 3598 .global2_addr = 0x1c, 3599 .age_time_coeff = 3750, 3600 .g1_irqs = 9, 3601 .g2_irqs = 14, 3602 .atu_move_port_mask = 0x1f, 3603 .pvt = true, 3604 .multi_chip = true, 3605 .tag_protocol = DSA_TAG_PROTO_DSA, 3606 .ops = &mv88e6390x_ops, 3607 }, 3608 }; 3609 3610 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3611 { 3612 int i; 3613 3614 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3615 if (mv88e6xxx_table[i].prod_num == prod_num) 3616 return &mv88e6xxx_table[i]; 3617 3618 return NULL; 3619 } 3620 3621 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3622 { 3623 const struct mv88e6xxx_info *info; 3624 unsigned int prod_num, rev; 3625 u16 id; 3626 int err; 3627 3628 mutex_lock(&chip->reg_lock); 3629 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3630 mutex_unlock(&chip->reg_lock); 3631 if (err) 3632 return err; 3633 3634 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3635 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3636 3637 info = mv88e6xxx_lookup_info(prod_num); 3638 if (!info) 3639 return -ENODEV; 3640 3641 /* Update the compatible info with the probed one */ 3642 chip->info = info; 3643 3644 err = mv88e6xxx_g2_require(chip); 3645 if (err) 3646 return err; 3647 3648 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3649 chip->info->prod_num, chip->info->name, rev); 3650 3651 return 0; 3652 } 3653 3654 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3655 { 3656 struct mv88e6xxx_chip *chip; 3657 3658 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3659 if (!chip) 3660 return NULL; 3661 3662 chip->dev = dev; 3663 3664 mutex_init(&chip->reg_lock); 3665 INIT_LIST_HEAD(&chip->mdios); 3666 3667 return chip; 3668 } 3669 3670 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3671 struct mii_bus *bus, int sw_addr) 3672 { 3673 if (sw_addr == 0) 3674 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3675 else if (chip->info->multi_chip) 3676 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3677 else 3678 return -EINVAL; 3679 3680 chip->bus = bus; 3681 chip->sw_addr = sw_addr; 3682 3683 return 0; 3684 } 3685 3686 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 3687 { 3688 struct mv88e6xxx_chip *chip = ds->priv; 3689 3690 return chip->info->tag_protocol; 3691 } 3692 3693 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3694 struct device *host_dev, int sw_addr, 3695 void **priv) 3696 { 3697 struct mv88e6xxx_chip *chip; 3698 struct mii_bus *bus; 3699 int err; 3700 3701 bus = dsa_host_dev_to_mii_bus(host_dev); 3702 if (!bus) 3703 return NULL; 3704 3705 chip = mv88e6xxx_alloc_chip(dsa_dev); 3706 if (!chip) 3707 return NULL; 3708 3709 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3710 chip->info = &mv88e6xxx_table[MV88E6085]; 3711 3712 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3713 if (err) 3714 goto free; 3715 3716 err = mv88e6xxx_detect(chip); 3717 if (err) 3718 goto free; 3719 3720 mutex_lock(&chip->reg_lock); 3721 err = mv88e6xxx_switch_reset(chip); 3722 mutex_unlock(&chip->reg_lock); 3723 if (err) 3724 goto free; 3725 3726 mv88e6xxx_phy_init(chip); 3727 3728 err = mv88e6xxx_mdios_register(chip, NULL); 3729 if (err) 3730 goto free; 3731 3732 *priv = chip; 3733 3734 return chip->info->name; 3735 free: 3736 devm_kfree(dsa_dev, chip); 3737 3738 return NULL; 3739 } 3740 3741 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3742 const struct switchdev_obj_port_mdb *mdb, 3743 struct switchdev_trans *trans) 3744 { 3745 /* We don't need any dynamic resource from the kernel (yet), 3746 * so skip the prepare phase. 3747 */ 3748 3749 return 0; 3750 } 3751 3752 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3753 const struct switchdev_obj_port_mdb *mdb, 3754 struct switchdev_trans *trans) 3755 { 3756 struct mv88e6xxx_chip *chip = ds->priv; 3757 3758 mutex_lock(&chip->reg_lock); 3759 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3760 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3761 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3762 port); 3763 mutex_unlock(&chip->reg_lock); 3764 } 3765 3766 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3767 const struct switchdev_obj_port_mdb *mdb) 3768 { 3769 struct mv88e6xxx_chip *chip = ds->priv; 3770 int err; 3771 3772 mutex_lock(&chip->reg_lock); 3773 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3774 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3775 mutex_unlock(&chip->reg_lock); 3776 3777 return err; 3778 } 3779 3780 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3781 .probe = mv88e6xxx_drv_probe, 3782 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3783 .setup = mv88e6xxx_setup, 3784 .set_addr = mv88e6xxx_set_addr, 3785 .adjust_link = mv88e6xxx_adjust_link, 3786 .get_strings = mv88e6xxx_get_strings, 3787 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3788 .get_sset_count = mv88e6xxx_get_sset_count, 3789 .port_enable = mv88e6xxx_port_enable, 3790 .port_disable = mv88e6xxx_port_disable, 3791 .get_mac_eee = mv88e6xxx_get_mac_eee, 3792 .set_mac_eee = mv88e6xxx_set_mac_eee, 3793 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3794 .get_eeprom = mv88e6xxx_get_eeprom, 3795 .set_eeprom = mv88e6xxx_set_eeprom, 3796 .get_regs_len = mv88e6xxx_get_regs_len, 3797 .get_regs = mv88e6xxx_get_regs, 3798 .set_ageing_time = mv88e6xxx_set_ageing_time, 3799 .port_bridge_join = mv88e6xxx_port_bridge_join, 3800 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3801 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3802 .port_fast_age = mv88e6xxx_port_fast_age, 3803 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3804 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3805 .port_vlan_add = mv88e6xxx_port_vlan_add, 3806 .port_vlan_del = mv88e6xxx_port_vlan_del, 3807 .port_fdb_add = mv88e6xxx_port_fdb_add, 3808 .port_fdb_del = mv88e6xxx_port_fdb_del, 3809 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3810 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3811 .port_mdb_add = mv88e6xxx_port_mdb_add, 3812 .port_mdb_del = mv88e6xxx_port_mdb_del, 3813 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 3814 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 3815 }; 3816 3817 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 3818 .ops = &mv88e6xxx_switch_ops, 3819 }; 3820 3821 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 3822 { 3823 struct device *dev = chip->dev; 3824 struct dsa_switch *ds; 3825 3826 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 3827 if (!ds) 3828 return -ENOMEM; 3829 3830 ds->priv = chip; 3831 ds->ops = &mv88e6xxx_switch_ops; 3832 ds->ageing_time_min = chip->info->age_time_coeff; 3833 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 3834 3835 dev_set_drvdata(dev, ds); 3836 3837 return dsa_register_switch(ds); 3838 } 3839 3840 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3841 { 3842 dsa_unregister_switch(chip->ds); 3843 } 3844 3845 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3846 { 3847 struct device *dev = &mdiodev->dev; 3848 struct device_node *np = dev->of_node; 3849 const struct mv88e6xxx_info *compat_info; 3850 struct mv88e6xxx_chip *chip; 3851 u32 eeprom_len; 3852 int err; 3853 3854 compat_info = of_device_get_match_data(dev); 3855 if (!compat_info) 3856 return -EINVAL; 3857 3858 chip = mv88e6xxx_alloc_chip(dev); 3859 if (!chip) 3860 return -ENOMEM; 3861 3862 chip->info = compat_info; 3863 3864 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3865 if (err) 3866 return err; 3867 3868 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 3869 if (IS_ERR(chip->reset)) 3870 return PTR_ERR(chip->reset); 3871 3872 err = mv88e6xxx_detect(chip); 3873 if (err) 3874 return err; 3875 3876 mv88e6xxx_phy_init(chip); 3877 3878 if (chip->info->ops->get_eeprom && 3879 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3880 chip->eeprom_len = eeprom_len; 3881 3882 mutex_lock(&chip->reg_lock); 3883 err = mv88e6xxx_switch_reset(chip); 3884 mutex_unlock(&chip->reg_lock); 3885 if (err) 3886 goto out; 3887 3888 chip->irq = of_irq_get(np, 0); 3889 if (chip->irq == -EPROBE_DEFER) { 3890 err = chip->irq; 3891 goto out; 3892 } 3893 3894 if (chip->irq > 0) { 3895 /* Has to be performed before the MDIO bus is created, 3896 * because the PHYs will link there interrupts to these 3897 * interrupt controllers 3898 */ 3899 mutex_lock(&chip->reg_lock); 3900 err = mv88e6xxx_g1_irq_setup(chip); 3901 mutex_unlock(&chip->reg_lock); 3902 3903 if (err) 3904 goto out; 3905 3906 if (chip->info->g2_irqs > 0) { 3907 err = mv88e6xxx_g2_irq_setup(chip); 3908 if (err) 3909 goto out_g1_irq; 3910 } 3911 } 3912 3913 err = mv88e6xxx_mdios_register(chip, np); 3914 if (err) 3915 goto out_g2_irq; 3916 3917 err = mv88e6xxx_register_switch(chip); 3918 if (err) 3919 goto out_mdio; 3920 3921 return 0; 3922 3923 out_mdio: 3924 mv88e6xxx_mdios_unregister(chip); 3925 out_g2_irq: 3926 if (chip->info->g2_irqs > 0 && chip->irq > 0) 3927 mv88e6xxx_g2_irq_free(chip); 3928 out_g1_irq: 3929 if (chip->irq > 0) { 3930 mutex_lock(&chip->reg_lock); 3931 mv88e6xxx_g1_irq_free(chip); 3932 mutex_unlock(&chip->reg_lock); 3933 } 3934 out: 3935 return err; 3936 } 3937 3938 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 3939 { 3940 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 3941 struct mv88e6xxx_chip *chip = ds->priv; 3942 3943 mv88e6xxx_phy_destroy(chip); 3944 mv88e6xxx_unregister_switch(chip); 3945 mv88e6xxx_mdios_unregister(chip); 3946 3947 if (chip->irq > 0) { 3948 if (chip->info->g2_irqs > 0) 3949 mv88e6xxx_g2_irq_free(chip); 3950 mv88e6xxx_g1_irq_free(chip); 3951 } 3952 } 3953 3954 static const struct of_device_id mv88e6xxx_of_match[] = { 3955 { 3956 .compatible = "marvell,mv88e6085", 3957 .data = &mv88e6xxx_table[MV88E6085], 3958 }, 3959 { 3960 .compatible = "marvell,mv88e6190", 3961 .data = &mv88e6xxx_table[MV88E6190], 3962 }, 3963 { /* sentinel */ }, 3964 }; 3965 3966 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 3967 3968 static struct mdio_driver mv88e6xxx_driver = { 3969 .probe = mv88e6xxx_probe, 3970 .remove = mv88e6xxx_remove, 3971 .mdiodrv.driver = { 3972 .name = "mv88e6085", 3973 .of_match_table = mv88e6xxx_of_match, 3974 }, 3975 }; 3976 3977 static int __init mv88e6xxx_init(void) 3978 { 3979 register_switch_driver(&mv88e6xxx_switch_drv); 3980 return mdio_driver_register(&mv88e6xxx_driver); 3981 } 3982 module_init(mv88e6xxx_init); 3983 3984 static void __exit mv88e6xxx_cleanup(void) 3985 { 3986 mdio_driver_unregister(&mv88e6xxx_driver); 3987 unregister_switch_driver(&mv88e6xxx_switch_drv); 3988 } 3989 module_exit(mv88e6xxx_cleanup); 3990 3991 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 3992 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 3993 MODULE_LICENSE("GPL"); 3994