1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 /* The 88e6250 family does not have the PHY detect bit. Instead, 475 * report whether the port is internal. 476 */ 477 if (chip->info->family == MV88E6XXX_FAMILY_6250) 478 return port < chip->info->num_internal_phys; 479 480 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 481 if (err) { 482 dev_err(chip->dev, 483 "p%d: %s: failed to read port status\n", 484 port, __func__); 485 return err; 486 } 487 488 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 489 } 490 491 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 492 struct phylink_link_state *state) 493 { 494 struct mv88e6xxx_chip *chip = ds->priv; 495 int lane; 496 int err; 497 498 mv88e6xxx_reg_lock(chip); 499 lane = mv88e6xxx_serdes_get_lane(chip, port); 500 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 501 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 502 state); 503 else 504 err = -EOPNOTSUPP; 505 mv88e6xxx_reg_unlock(chip); 506 507 return err; 508 } 509 510 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 511 unsigned int mode, 512 phy_interface_t interface, 513 const unsigned long *advertise) 514 { 515 const struct mv88e6xxx_ops *ops = chip->info->ops; 516 int lane; 517 518 if (ops->serdes_pcs_config) { 519 lane = mv88e6xxx_serdes_get_lane(chip, port); 520 if (lane >= 0) 521 return ops->serdes_pcs_config(chip, port, lane, mode, 522 interface, advertise); 523 } 524 525 return 0; 526 } 527 528 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 529 { 530 struct mv88e6xxx_chip *chip = ds->priv; 531 const struct mv88e6xxx_ops *ops; 532 int err = 0; 533 int lane; 534 535 ops = chip->info->ops; 536 537 if (ops->serdes_pcs_an_restart) { 538 mv88e6xxx_reg_lock(chip); 539 lane = mv88e6xxx_serdes_get_lane(chip, port); 540 if (lane >= 0) 541 err = ops->serdes_pcs_an_restart(chip, port, lane); 542 mv88e6xxx_reg_unlock(chip); 543 544 if (err) 545 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 546 } 547 } 548 549 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 550 unsigned int mode, 551 int speed, int duplex) 552 { 553 const struct mv88e6xxx_ops *ops = chip->info->ops; 554 int lane; 555 556 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 557 lane = mv88e6xxx_serdes_get_lane(chip, port); 558 if (lane >= 0) 559 return ops->serdes_pcs_link_up(chip, port, lane, 560 speed, duplex); 561 } 562 563 return 0; 564 } 565 566 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 567 unsigned long *mask, 568 struct phylink_link_state *state) 569 { 570 if (!phy_interface_mode_is_8023z(state->interface)) { 571 /* 10M and 100M are only supported in non-802.3z mode */ 572 phylink_set(mask, 10baseT_Half); 573 phylink_set(mask, 10baseT_Full); 574 phylink_set(mask, 100baseT_Half); 575 phylink_set(mask, 100baseT_Full); 576 } 577 } 578 579 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 580 unsigned long *mask, 581 struct phylink_link_state *state) 582 { 583 /* FIXME: if the port is in 1000Base-X mode, then it only supports 584 * 1000M FD speeds. In this case, CMODE will indicate 5. 585 */ 586 phylink_set(mask, 1000baseT_Full); 587 phylink_set(mask, 1000baseX_Full); 588 589 mv88e6065_phylink_validate(chip, port, mask, state); 590 } 591 592 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 593 unsigned long *mask, 594 struct phylink_link_state *state) 595 { 596 if (port >= 5) 597 phylink_set(mask, 2500baseX_Full); 598 599 /* No ethtool bits for 200Mbps */ 600 phylink_set(mask, 1000baseT_Full); 601 phylink_set(mask, 1000baseX_Full); 602 603 mv88e6065_phylink_validate(chip, port, mask, state); 604 } 605 606 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 607 unsigned long *mask, 608 struct phylink_link_state *state) 609 { 610 /* No ethtool bits for 200Mbps */ 611 phylink_set(mask, 1000baseT_Full); 612 phylink_set(mask, 1000baseX_Full); 613 614 mv88e6065_phylink_validate(chip, port, mask, state); 615 } 616 617 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 618 unsigned long *mask, 619 struct phylink_link_state *state) 620 { 621 if (port >= 9) { 622 phylink_set(mask, 2500baseX_Full); 623 phylink_set(mask, 2500baseT_Full); 624 } 625 626 /* No ethtool bits for 200Mbps */ 627 phylink_set(mask, 1000baseT_Full); 628 phylink_set(mask, 1000baseX_Full); 629 630 mv88e6065_phylink_validate(chip, port, mask, state); 631 } 632 633 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 634 unsigned long *mask, 635 struct phylink_link_state *state) 636 { 637 if (port >= 9) { 638 phylink_set(mask, 10000baseT_Full); 639 phylink_set(mask, 10000baseKR_Full); 640 } 641 642 mv88e6390_phylink_validate(chip, port, mask, state); 643 } 644 645 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 646 unsigned long *mask, 647 struct phylink_link_state *state) 648 { 649 bool is_6191x = 650 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 651 652 if (((port == 0 || port == 9) && !is_6191x) || port == 10) { 653 phylink_set(mask, 10000baseT_Full); 654 phylink_set(mask, 10000baseKR_Full); 655 phylink_set(mask, 10000baseCR_Full); 656 phylink_set(mask, 10000baseSR_Full); 657 phylink_set(mask, 10000baseLR_Full); 658 phylink_set(mask, 10000baseLRM_Full); 659 phylink_set(mask, 10000baseER_Full); 660 phylink_set(mask, 5000baseT_Full); 661 phylink_set(mask, 2500baseX_Full); 662 phylink_set(mask, 2500baseT_Full); 663 } 664 665 phylink_set(mask, 1000baseT_Full); 666 phylink_set(mask, 1000baseX_Full); 667 668 mv88e6065_phylink_validate(chip, port, mask, state); 669 } 670 671 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 672 unsigned long *supported, 673 struct phylink_link_state *state) 674 { 675 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 676 struct mv88e6xxx_chip *chip = ds->priv; 677 678 /* Allow all the expected bits */ 679 phylink_set(mask, Autoneg); 680 phylink_set(mask, Pause); 681 phylink_set_port_modes(mask); 682 683 if (chip->info->ops->phylink_validate) 684 chip->info->ops->phylink_validate(chip, port, mask, state); 685 686 linkmode_and(supported, supported, mask); 687 linkmode_and(state->advertising, state->advertising, mask); 688 689 /* We can only operate at 2500BaseX or 1000BaseX. If requested 690 * to advertise both, only report advertising at 2500BaseX. 691 */ 692 phylink_helper_basex_speed(state); 693 } 694 695 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 696 unsigned int mode, 697 const struct phylink_link_state *state) 698 { 699 struct mv88e6xxx_chip *chip = ds->priv; 700 struct mv88e6xxx_port *p; 701 int err = 0; 702 703 p = &chip->ports[port]; 704 705 mv88e6xxx_reg_lock(chip); 706 707 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 708 /* In inband mode, the link may come up at any time while the 709 * link is not forced down. Force the link down while we 710 * reconfigure the interface mode. 711 */ 712 if (mode == MLO_AN_INBAND && 713 p->interface != state->interface && 714 chip->info->ops->port_set_link) 715 chip->info->ops->port_set_link(chip, port, 716 LINK_FORCED_DOWN); 717 718 err = mv88e6xxx_port_config_interface(chip, port, 719 state->interface); 720 if (err && err != -EOPNOTSUPP) 721 goto err_unlock; 722 723 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 724 state->interface, 725 state->advertising); 726 /* FIXME: we should restart negotiation if something changed - 727 * which is something we get if we convert to using phylinks 728 * PCS operations. 729 */ 730 if (err > 0) 731 err = 0; 732 } 733 734 /* Undo the forced down state above after completing configuration 735 * irrespective of its state on entry, which allows the link to come 736 * up in the in-band case where there is no separate SERDES. Also 737 * ensure that the link can come up if the PPU is in use and we are 738 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 739 */ 740 if (chip->info->ops->port_set_link && 741 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 742 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 743 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 744 745 p->interface = state->interface; 746 747 err_unlock: 748 mv88e6xxx_reg_unlock(chip); 749 750 if (err && err != -EOPNOTSUPP) 751 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 752 } 753 754 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 755 unsigned int mode, 756 phy_interface_t interface) 757 { 758 struct mv88e6xxx_chip *chip = ds->priv; 759 const struct mv88e6xxx_ops *ops; 760 int err = 0; 761 762 ops = chip->info->ops; 763 764 mv88e6xxx_reg_lock(chip); 765 /* Force the link down if we know the port may not be automatically 766 * updated by the switch or if we are using fixed-link mode. 767 */ 768 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 769 mode == MLO_AN_FIXED) && ops->port_sync_link) 770 err = ops->port_sync_link(chip, port, mode, false); 771 772 if (!err && ops->port_set_speed_duplex) 773 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 774 DUPLEX_UNFORCED); 775 mv88e6xxx_reg_unlock(chip); 776 777 if (err) 778 dev_err(chip->dev, 779 "p%d: failed to force MAC link down\n", port); 780 } 781 782 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 783 unsigned int mode, phy_interface_t interface, 784 struct phy_device *phydev, 785 int speed, int duplex, 786 bool tx_pause, bool rx_pause) 787 { 788 struct mv88e6xxx_chip *chip = ds->priv; 789 const struct mv88e6xxx_ops *ops; 790 int err = 0; 791 792 ops = chip->info->ops; 793 794 mv88e6xxx_reg_lock(chip); 795 /* Configure and force the link up if we know that the port may not 796 * automatically updated by the switch or if we are using fixed-link 797 * mode. 798 */ 799 if (!mv88e6xxx_port_ppu_updates(chip, port) || 800 mode == MLO_AN_FIXED) { 801 /* FIXME: for an automedia port, should we force the link 802 * down here - what if the link comes up due to "other" media 803 * while we're bringing the port up, how is the exclusivity 804 * handled in the Marvell hardware? E.g. port 2 on 88E6390 805 * shared between internal PHY and Serdes. 806 */ 807 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 808 duplex); 809 if (err) 810 goto error; 811 812 if (ops->port_set_speed_duplex) { 813 err = ops->port_set_speed_duplex(chip, port, 814 speed, duplex); 815 if (err && err != -EOPNOTSUPP) 816 goto error; 817 } 818 819 if (ops->port_sync_link) 820 err = ops->port_sync_link(chip, port, mode, true); 821 } 822 error: 823 mv88e6xxx_reg_unlock(chip); 824 825 if (err && err != -EOPNOTSUPP) 826 dev_err(ds->dev, 827 "p%d: failed to configure MAC link up\n", port); 828 } 829 830 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 831 { 832 if (!chip->info->ops->stats_snapshot) 833 return -EOPNOTSUPP; 834 835 return chip->info->ops->stats_snapshot(chip, port); 836 } 837 838 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 839 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 840 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 841 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 842 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 843 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 844 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 845 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 846 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 847 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 848 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 849 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 850 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 851 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 852 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 853 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 854 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 855 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 856 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 857 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 858 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 859 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 860 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 861 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 862 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 863 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 864 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 865 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 866 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 867 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 868 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 869 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 870 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 871 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 872 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 873 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 874 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 875 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 876 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 877 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 878 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 879 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 880 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 881 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 882 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 883 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 884 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 885 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 886 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 887 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 888 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 889 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 890 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 891 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 892 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 893 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 894 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 895 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 896 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 897 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 898 }; 899 900 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 901 struct mv88e6xxx_hw_stat *s, 902 int port, u16 bank1_select, 903 u16 histogram) 904 { 905 u32 low; 906 u32 high = 0; 907 u16 reg = 0; 908 int err; 909 u64 value; 910 911 switch (s->type) { 912 case STATS_TYPE_PORT: 913 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 914 if (err) 915 return U64_MAX; 916 917 low = reg; 918 if (s->size == 4) { 919 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 920 if (err) 921 return U64_MAX; 922 low |= ((u32)reg) << 16; 923 } 924 break; 925 case STATS_TYPE_BANK1: 926 reg = bank1_select; 927 fallthrough; 928 case STATS_TYPE_BANK0: 929 reg |= s->reg | histogram; 930 mv88e6xxx_g1_stats_read(chip, reg, &low); 931 if (s->size == 8) 932 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 933 break; 934 default: 935 return U64_MAX; 936 } 937 value = (((u64)high) << 32) | low; 938 return value; 939 } 940 941 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 942 uint8_t *data, int types) 943 { 944 struct mv88e6xxx_hw_stat *stat; 945 int i, j; 946 947 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 948 stat = &mv88e6xxx_hw_stats[i]; 949 if (stat->type & types) { 950 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 951 ETH_GSTRING_LEN); 952 j++; 953 } 954 } 955 956 return j; 957 } 958 959 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 960 uint8_t *data) 961 { 962 return mv88e6xxx_stats_get_strings(chip, data, 963 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 964 } 965 966 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 967 uint8_t *data) 968 { 969 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 970 } 971 972 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 973 uint8_t *data) 974 { 975 return mv88e6xxx_stats_get_strings(chip, data, 976 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 977 } 978 979 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 980 "atu_member_violation", 981 "atu_miss_violation", 982 "atu_full_violation", 983 "vtu_member_violation", 984 "vtu_miss_violation", 985 }; 986 987 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 988 { 989 unsigned int i; 990 991 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 992 strlcpy(data + i * ETH_GSTRING_LEN, 993 mv88e6xxx_atu_vtu_stats_strings[i], 994 ETH_GSTRING_LEN); 995 } 996 997 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 998 u32 stringset, uint8_t *data) 999 { 1000 struct mv88e6xxx_chip *chip = ds->priv; 1001 int count = 0; 1002 1003 if (stringset != ETH_SS_STATS) 1004 return; 1005 1006 mv88e6xxx_reg_lock(chip); 1007 1008 if (chip->info->ops->stats_get_strings) 1009 count = chip->info->ops->stats_get_strings(chip, data); 1010 1011 if (chip->info->ops->serdes_get_strings) { 1012 data += count * ETH_GSTRING_LEN; 1013 count = chip->info->ops->serdes_get_strings(chip, port, data); 1014 } 1015 1016 data += count * ETH_GSTRING_LEN; 1017 mv88e6xxx_atu_vtu_get_strings(data); 1018 1019 mv88e6xxx_reg_unlock(chip); 1020 } 1021 1022 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1023 int types) 1024 { 1025 struct mv88e6xxx_hw_stat *stat; 1026 int i, j; 1027 1028 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1029 stat = &mv88e6xxx_hw_stats[i]; 1030 if (stat->type & types) 1031 j++; 1032 } 1033 return j; 1034 } 1035 1036 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1037 { 1038 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1039 STATS_TYPE_PORT); 1040 } 1041 1042 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1043 { 1044 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1045 } 1046 1047 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1048 { 1049 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1050 STATS_TYPE_BANK1); 1051 } 1052 1053 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1054 { 1055 struct mv88e6xxx_chip *chip = ds->priv; 1056 int serdes_count = 0; 1057 int count = 0; 1058 1059 if (sset != ETH_SS_STATS) 1060 return 0; 1061 1062 mv88e6xxx_reg_lock(chip); 1063 if (chip->info->ops->stats_get_sset_count) 1064 count = chip->info->ops->stats_get_sset_count(chip); 1065 if (count < 0) 1066 goto out; 1067 1068 if (chip->info->ops->serdes_get_sset_count) 1069 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1070 port); 1071 if (serdes_count < 0) { 1072 count = serdes_count; 1073 goto out; 1074 } 1075 count += serdes_count; 1076 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1077 1078 out: 1079 mv88e6xxx_reg_unlock(chip); 1080 1081 return count; 1082 } 1083 1084 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1085 uint64_t *data, int types, 1086 u16 bank1_select, u16 histogram) 1087 { 1088 struct mv88e6xxx_hw_stat *stat; 1089 int i, j; 1090 1091 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1092 stat = &mv88e6xxx_hw_stats[i]; 1093 if (stat->type & types) { 1094 mv88e6xxx_reg_lock(chip); 1095 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1096 bank1_select, 1097 histogram); 1098 mv88e6xxx_reg_unlock(chip); 1099 1100 j++; 1101 } 1102 } 1103 return j; 1104 } 1105 1106 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1107 uint64_t *data) 1108 { 1109 return mv88e6xxx_stats_get_stats(chip, port, data, 1110 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1111 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1112 } 1113 1114 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1115 uint64_t *data) 1116 { 1117 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1118 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1119 } 1120 1121 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1122 uint64_t *data) 1123 { 1124 return mv88e6xxx_stats_get_stats(chip, port, data, 1125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1126 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1127 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1128 } 1129 1130 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1131 uint64_t *data) 1132 { 1133 return mv88e6xxx_stats_get_stats(chip, port, data, 1134 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1135 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1136 0); 1137 } 1138 1139 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1140 uint64_t *data) 1141 { 1142 *data++ = chip->ports[port].atu_member_violation; 1143 *data++ = chip->ports[port].atu_miss_violation; 1144 *data++ = chip->ports[port].atu_full_violation; 1145 *data++ = chip->ports[port].vtu_member_violation; 1146 *data++ = chip->ports[port].vtu_miss_violation; 1147 } 1148 1149 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1150 uint64_t *data) 1151 { 1152 int count = 0; 1153 1154 if (chip->info->ops->stats_get_stats) 1155 count = chip->info->ops->stats_get_stats(chip, port, data); 1156 1157 mv88e6xxx_reg_lock(chip); 1158 if (chip->info->ops->serdes_get_stats) { 1159 data += count; 1160 count = chip->info->ops->serdes_get_stats(chip, port, data); 1161 } 1162 data += count; 1163 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1164 mv88e6xxx_reg_unlock(chip); 1165 } 1166 1167 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1168 uint64_t *data) 1169 { 1170 struct mv88e6xxx_chip *chip = ds->priv; 1171 int ret; 1172 1173 mv88e6xxx_reg_lock(chip); 1174 1175 ret = mv88e6xxx_stats_snapshot(chip, port); 1176 mv88e6xxx_reg_unlock(chip); 1177 1178 if (ret < 0) 1179 return; 1180 1181 mv88e6xxx_get_stats(chip, port, data); 1182 1183 } 1184 1185 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1186 { 1187 struct mv88e6xxx_chip *chip = ds->priv; 1188 int len; 1189 1190 len = 32 * sizeof(u16); 1191 if (chip->info->ops->serdes_get_regs_len) 1192 len += chip->info->ops->serdes_get_regs_len(chip, port); 1193 1194 return len; 1195 } 1196 1197 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1198 struct ethtool_regs *regs, void *_p) 1199 { 1200 struct mv88e6xxx_chip *chip = ds->priv; 1201 int err; 1202 u16 reg; 1203 u16 *p = _p; 1204 int i; 1205 1206 regs->version = chip->info->prod_num; 1207 1208 memset(p, 0xff, 32 * sizeof(u16)); 1209 1210 mv88e6xxx_reg_lock(chip); 1211 1212 for (i = 0; i < 32; i++) { 1213 1214 err = mv88e6xxx_port_read(chip, port, i, ®); 1215 if (!err) 1216 p[i] = reg; 1217 } 1218 1219 if (chip->info->ops->serdes_get_regs) 1220 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1221 1222 mv88e6xxx_reg_unlock(chip); 1223 } 1224 1225 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1226 struct ethtool_eee *e) 1227 { 1228 /* Nothing to do on the port's MAC */ 1229 return 0; 1230 } 1231 1232 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1233 struct ethtool_eee *e) 1234 { 1235 /* Nothing to do on the port's MAC */ 1236 return 0; 1237 } 1238 1239 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1240 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1241 { 1242 struct dsa_switch *ds = chip->ds; 1243 struct dsa_switch_tree *dst = ds->dst; 1244 struct dsa_port *dp, *other_dp; 1245 bool found = false; 1246 u16 pvlan; 1247 1248 /* dev is a physical switch */ 1249 if (dev <= dst->last_switch) { 1250 list_for_each_entry(dp, &dst->ports, list) { 1251 if (dp->ds->index == dev && dp->index == port) { 1252 /* dp might be a DSA link or a user port, so it 1253 * might or might not have a bridge. 1254 * Use the "found" variable for both cases. 1255 */ 1256 found = true; 1257 break; 1258 } 1259 } 1260 /* dev is a virtual bridge */ 1261 } else { 1262 list_for_each_entry(dp, &dst->ports, list) { 1263 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1264 1265 if (!bridge_num) 1266 continue; 1267 1268 if (bridge_num + dst->last_switch != dev) 1269 continue; 1270 1271 found = true; 1272 break; 1273 } 1274 } 1275 1276 /* Prevent frames from unknown switch or virtual bridge */ 1277 if (!found) 1278 return 0; 1279 1280 /* Frames from DSA links and CPU ports can egress any local port */ 1281 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1282 return mv88e6xxx_port_mask(chip); 1283 1284 pvlan = 0; 1285 1286 /* Frames from user ports can egress any local DSA links and CPU ports, 1287 * as well as any local member of their bridge group. 1288 */ 1289 dsa_switch_for_each_port(other_dp, ds) 1290 if (other_dp->type == DSA_PORT_TYPE_CPU || 1291 other_dp->type == DSA_PORT_TYPE_DSA || 1292 dsa_port_bridge_same(dp, other_dp)) 1293 pvlan |= BIT(other_dp->index); 1294 1295 return pvlan; 1296 } 1297 1298 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1299 { 1300 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1301 1302 /* prevent frames from going back out of the port they came in on */ 1303 output_ports &= ~BIT(port); 1304 1305 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1306 } 1307 1308 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1309 u8 state) 1310 { 1311 struct mv88e6xxx_chip *chip = ds->priv; 1312 int err; 1313 1314 mv88e6xxx_reg_lock(chip); 1315 err = mv88e6xxx_port_set_state(chip, port, state); 1316 mv88e6xxx_reg_unlock(chip); 1317 1318 if (err) 1319 dev_err(ds->dev, "p%d: failed to update state\n", port); 1320 } 1321 1322 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1323 { 1324 int err; 1325 1326 if (chip->info->ops->ieee_pri_map) { 1327 err = chip->info->ops->ieee_pri_map(chip); 1328 if (err) 1329 return err; 1330 } 1331 1332 if (chip->info->ops->ip_pri_map) { 1333 err = chip->info->ops->ip_pri_map(chip); 1334 if (err) 1335 return err; 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1342 { 1343 struct dsa_switch *ds = chip->ds; 1344 int target, port; 1345 int err; 1346 1347 if (!chip->info->global2_addr) 1348 return 0; 1349 1350 /* Initialize the routing port to the 32 possible target devices */ 1351 for (target = 0; target < 32; target++) { 1352 port = dsa_routing_port(ds, target); 1353 if (port == ds->num_ports) 1354 port = 0x1f; 1355 1356 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1357 if (err) 1358 return err; 1359 } 1360 1361 if (chip->info->ops->set_cascade_port) { 1362 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1363 err = chip->info->ops->set_cascade_port(chip, port); 1364 if (err) 1365 return err; 1366 } 1367 1368 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1369 if (err) 1370 return err; 1371 1372 return 0; 1373 } 1374 1375 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1376 { 1377 /* Clear all trunk masks and mapping */ 1378 if (chip->info->global2_addr) 1379 return mv88e6xxx_g2_trunk_clear(chip); 1380 1381 return 0; 1382 } 1383 1384 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1385 { 1386 if (chip->info->ops->rmu_disable) 1387 return chip->info->ops->rmu_disable(chip); 1388 1389 return 0; 1390 } 1391 1392 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1393 { 1394 if (chip->info->ops->pot_clear) 1395 return chip->info->ops->pot_clear(chip); 1396 1397 return 0; 1398 } 1399 1400 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1401 { 1402 if (chip->info->ops->mgmt_rsvd2cpu) 1403 return chip->info->ops->mgmt_rsvd2cpu(chip); 1404 1405 return 0; 1406 } 1407 1408 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1409 { 1410 int err; 1411 1412 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1413 if (err) 1414 return err; 1415 1416 /* The chips that have a "learn2all" bit in Global1, ATU 1417 * Control are precisely those whose port registers have a 1418 * Message Port bit in Port Control 1 and hence implement 1419 * ->port_setup_message_port. 1420 */ 1421 if (chip->info->ops->port_setup_message_port) { 1422 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1423 if (err) 1424 return err; 1425 } 1426 1427 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1428 } 1429 1430 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1431 { 1432 int port; 1433 int err; 1434 1435 if (!chip->info->ops->irl_init_all) 1436 return 0; 1437 1438 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1439 /* Disable ingress rate limiting by resetting all per port 1440 * ingress rate limit resources to their initial state. 1441 */ 1442 err = chip->info->ops->irl_init_all(chip, port); 1443 if (err) 1444 return err; 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1451 { 1452 if (chip->info->ops->set_switch_mac) { 1453 u8 addr[ETH_ALEN]; 1454 1455 eth_random_addr(addr); 1456 1457 return chip->info->ops->set_switch_mac(chip, addr); 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1464 { 1465 struct dsa_switch_tree *dst = chip->ds->dst; 1466 struct dsa_switch *ds; 1467 struct dsa_port *dp; 1468 u16 pvlan = 0; 1469 1470 if (!mv88e6xxx_has_pvt(chip)) 1471 return 0; 1472 1473 /* Skip the local source device, which uses in-chip port VLAN */ 1474 if (dev != chip->ds->index) { 1475 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1476 1477 ds = dsa_switch_find(dst->index, dev); 1478 dp = ds ? dsa_to_port(ds, port) : NULL; 1479 if (dp && dp->lag_dev) { 1480 /* As the PVT is used to limit flooding of 1481 * FORWARD frames, which use the LAG ID as the 1482 * source port, we must translate dev/port to 1483 * the special "LAG device" in the PVT, using 1484 * the LAG ID as the port number. 1485 */ 1486 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1487 port = dsa_lag_id(dst, dp->lag_dev); 1488 } 1489 } 1490 1491 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1492 } 1493 1494 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1495 { 1496 int dev, port; 1497 int err; 1498 1499 if (!mv88e6xxx_has_pvt(chip)) 1500 return 0; 1501 1502 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1503 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1504 */ 1505 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1506 if (err) 1507 return err; 1508 1509 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1510 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1511 err = mv88e6xxx_pvt_map(chip, dev, port); 1512 if (err) 1513 return err; 1514 } 1515 } 1516 1517 return 0; 1518 } 1519 1520 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1521 { 1522 struct mv88e6xxx_chip *chip = ds->priv; 1523 int err; 1524 1525 if (dsa_to_port(ds, port)->lag_dev) 1526 /* Hardware is incapable of fast-aging a LAG through a 1527 * regular ATU move operation. Until we have something 1528 * more fancy in place this is a no-op. 1529 */ 1530 return; 1531 1532 mv88e6xxx_reg_lock(chip); 1533 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1534 mv88e6xxx_reg_unlock(chip); 1535 1536 if (err) 1537 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1538 } 1539 1540 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1541 { 1542 if (!mv88e6xxx_max_vid(chip)) 1543 return 0; 1544 1545 return mv88e6xxx_g1_vtu_flush(chip); 1546 } 1547 1548 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1549 struct mv88e6xxx_vtu_entry *entry) 1550 { 1551 int err; 1552 1553 if (!chip->info->ops->vtu_getnext) 1554 return -EOPNOTSUPP; 1555 1556 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1557 entry->valid = false; 1558 1559 err = chip->info->ops->vtu_getnext(chip, entry); 1560 1561 if (entry->vid != vid) 1562 entry->valid = false; 1563 1564 return err; 1565 } 1566 1567 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1568 int (*cb)(struct mv88e6xxx_chip *chip, 1569 const struct mv88e6xxx_vtu_entry *entry, 1570 void *priv), 1571 void *priv) 1572 { 1573 struct mv88e6xxx_vtu_entry entry = { 1574 .vid = mv88e6xxx_max_vid(chip), 1575 .valid = false, 1576 }; 1577 int err; 1578 1579 if (!chip->info->ops->vtu_getnext) 1580 return -EOPNOTSUPP; 1581 1582 do { 1583 err = chip->info->ops->vtu_getnext(chip, &entry); 1584 if (err) 1585 return err; 1586 1587 if (!entry.valid) 1588 break; 1589 1590 err = cb(chip, &entry, priv); 1591 if (err) 1592 return err; 1593 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1594 1595 return 0; 1596 } 1597 1598 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1599 struct mv88e6xxx_vtu_entry *entry) 1600 { 1601 if (!chip->info->ops->vtu_loadpurge) 1602 return -EOPNOTSUPP; 1603 1604 return chip->info->ops->vtu_loadpurge(chip, entry); 1605 } 1606 1607 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1608 const struct mv88e6xxx_vtu_entry *entry, 1609 void *_fid_bitmap) 1610 { 1611 unsigned long *fid_bitmap = _fid_bitmap; 1612 1613 set_bit(entry->fid, fid_bitmap); 1614 return 0; 1615 } 1616 1617 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1618 { 1619 int i, err; 1620 u16 fid; 1621 1622 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1623 1624 /* Set every FID bit used by the (un)bridged ports */ 1625 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1626 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1627 if (err) 1628 return err; 1629 1630 set_bit(fid, fid_bitmap); 1631 } 1632 1633 /* Set every FID bit used by the VLAN entries */ 1634 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1635 } 1636 1637 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1638 { 1639 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1640 int err; 1641 1642 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1643 if (err) 1644 return err; 1645 1646 /* The reset value 0x000 is used to indicate that multiple address 1647 * databases are not needed. Return the next positive available. 1648 */ 1649 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1650 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1651 return -ENOSPC; 1652 1653 /* Clear the database */ 1654 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1655 } 1656 1657 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1658 u16 vid) 1659 { 1660 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1661 struct mv88e6xxx_chip *chip = ds->priv; 1662 struct mv88e6xxx_vtu_entry vlan; 1663 int err; 1664 1665 /* DSA and CPU ports have to be members of multiple vlans */ 1666 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1667 return 0; 1668 1669 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1670 if (err) 1671 return err; 1672 1673 if (!vlan.valid) 1674 return 0; 1675 1676 dsa_switch_for_each_user_port(other_dp, ds) { 1677 struct net_device *other_br; 1678 1679 if (vlan.member[other_dp->index] == 1680 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1681 continue; 1682 1683 if (dsa_port_bridge_same(dp, other_dp)) 1684 break; /* same bridge, check next VLAN */ 1685 1686 other_br = dsa_port_bridge_dev_get(other_dp); 1687 if (!other_br) 1688 continue; 1689 1690 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1691 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1692 return -EOPNOTSUPP; 1693 } 1694 1695 return 0; 1696 } 1697 1698 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1699 { 1700 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1701 struct net_device *br = dsa_port_bridge_dev_get(dp); 1702 struct mv88e6xxx_port *p = &chip->ports[port]; 1703 u16 pvid = MV88E6XXX_VID_STANDALONE; 1704 bool drop_untagged = false; 1705 int err; 1706 1707 if (br) { 1708 if (br_vlan_enabled(br)) { 1709 pvid = p->bridge_pvid.vid; 1710 drop_untagged = !p->bridge_pvid.valid; 1711 } else { 1712 pvid = MV88E6XXX_VID_BRIDGED; 1713 } 1714 } 1715 1716 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1717 if (err) 1718 return err; 1719 1720 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1721 } 1722 1723 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1724 bool vlan_filtering, 1725 struct netlink_ext_ack *extack) 1726 { 1727 struct mv88e6xxx_chip *chip = ds->priv; 1728 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1729 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1730 int err; 1731 1732 if (!mv88e6xxx_max_vid(chip)) 1733 return -EOPNOTSUPP; 1734 1735 mv88e6xxx_reg_lock(chip); 1736 1737 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1738 if (err) 1739 goto unlock; 1740 1741 err = mv88e6xxx_port_commit_pvid(chip, port); 1742 if (err) 1743 goto unlock; 1744 1745 unlock: 1746 mv88e6xxx_reg_unlock(chip); 1747 1748 return err; 1749 } 1750 1751 static int 1752 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1753 const struct switchdev_obj_port_vlan *vlan) 1754 { 1755 struct mv88e6xxx_chip *chip = ds->priv; 1756 int err; 1757 1758 if (!mv88e6xxx_max_vid(chip)) 1759 return -EOPNOTSUPP; 1760 1761 /* If the requested port doesn't belong to the same bridge as the VLAN 1762 * members, do not support it (yet) and fallback to software VLAN. 1763 */ 1764 mv88e6xxx_reg_lock(chip); 1765 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1766 mv88e6xxx_reg_unlock(chip); 1767 1768 return err; 1769 } 1770 1771 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1772 const unsigned char *addr, u16 vid, 1773 u8 state) 1774 { 1775 struct mv88e6xxx_atu_entry entry; 1776 struct mv88e6xxx_vtu_entry vlan; 1777 u16 fid; 1778 int err; 1779 1780 /* Ports have two private address databases: one for when the port is 1781 * standalone and one for when the port is under a bridge and the 1782 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1783 * address database to remain 100% empty, so we never load an ATU entry 1784 * into a standalone port's database. Therefore, translate the null 1785 * VLAN ID into the port's database used for VLAN-unaware bridging. 1786 */ 1787 if (vid == 0) { 1788 fid = MV88E6XXX_FID_BRIDGED; 1789 } else { 1790 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1791 if (err) 1792 return err; 1793 1794 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1795 if (!vlan.valid) 1796 return -EOPNOTSUPP; 1797 1798 fid = vlan.fid; 1799 } 1800 1801 entry.state = 0; 1802 ether_addr_copy(entry.mac, addr); 1803 eth_addr_dec(entry.mac); 1804 1805 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1806 if (err) 1807 return err; 1808 1809 /* Initialize a fresh ATU entry if it isn't found */ 1810 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1811 memset(&entry, 0, sizeof(entry)); 1812 ether_addr_copy(entry.mac, addr); 1813 } 1814 1815 /* Purge the ATU entry only if no port is using it anymore */ 1816 if (!state) { 1817 entry.portvec &= ~BIT(port); 1818 if (!entry.portvec) 1819 entry.state = 0; 1820 } else { 1821 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1822 entry.portvec = BIT(port); 1823 else 1824 entry.portvec |= BIT(port); 1825 1826 entry.state = state; 1827 } 1828 1829 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1830 } 1831 1832 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1833 const struct mv88e6xxx_policy *policy) 1834 { 1835 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1836 enum mv88e6xxx_policy_action action = policy->action; 1837 const u8 *addr = policy->addr; 1838 u16 vid = policy->vid; 1839 u8 state; 1840 int err; 1841 int id; 1842 1843 if (!chip->info->ops->port_set_policy) 1844 return -EOPNOTSUPP; 1845 1846 switch (mapping) { 1847 case MV88E6XXX_POLICY_MAPPING_DA: 1848 case MV88E6XXX_POLICY_MAPPING_SA: 1849 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1850 state = 0; /* Dissociate the port and address */ 1851 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1852 is_multicast_ether_addr(addr)) 1853 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1854 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1855 is_unicast_ether_addr(addr)) 1856 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1857 else 1858 return -EOPNOTSUPP; 1859 1860 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1861 state); 1862 if (err) 1863 return err; 1864 break; 1865 default: 1866 return -EOPNOTSUPP; 1867 } 1868 1869 /* Skip the port's policy clearing if the mapping is still in use */ 1870 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1871 idr_for_each_entry(&chip->policies, policy, id) 1872 if (policy->port == port && 1873 policy->mapping == mapping && 1874 policy->action != action) 1875 return 0; 1876 1877 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1878 } 1879 1880 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1881 struct ethtool_rx_flow_spec *fs) 1882 { 1883 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1884 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1885 enum mv88e6xxx_policy_mapping mapping; 1886 enum mv88e6xxx_policy_action action; 1887 struct mv88e6xxx_policy *policy; 1888 u16 vid = 0; 1889 u8 *addr; 1890 int err; 1891 int id; 1892 1893 if (fs->location != RX_CLS_LOC_ANY) 1894 return -EINVAL; 1895 1896 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1897 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1898 else 1899 return -EOPNOTSUPP; 1900 1901 switch (fs->flow_type & ~FLOW_EXT) { 1902 case ETHER_FLOW: 1903 if (!is_zero_ether_addr(mac_mask->h_dest) && 1904 is_zero_ether_addr(mac_mask->h_source)) { 1905 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1906 addr = mac_entry->h_dest; 1907 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1908 !is_zero_ether_addr(mac_mask->h_source)) { 1909 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1910 addr = mac_entry->h_source; 1911 } else { 1912 /* Cannot support DA and SA mapping in the same rule */ 1913 return -EOPNOTSUPP; 1914 } 1915 break; 1916 default: 1917 return -EOPNOTSUPP; 1918 } 1919 1920 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1921 if (fs->m_ext.vlan_tci != htons(0xffff)) 1922 return -EOPNOTSUPP; 1923 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1924 } 1925 1926 idr_for_each_entry(&chip->policies, policy, id) { 1927 if (policy->port == port && policy->mapping == mapping && 1928 policy->action == action && policy->vid == vid && 1929 ether_addr_equal(policy->addr, addr)) 1930 return -EEXIST; 1931 } 1932 1933 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1934 if (!policy) 1935 return -ENOMEM; 1936 1937 fs->location = 0; 1938 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1939 GFP_KERNEL); 1940 if (err) { 1941 devm_kfree(chip->dev, policy); 1942 return err; 1943 } 1944 1945 memcpy(&policy->fs, fs, sizeof(*fs)); 1946 ether_addr_copy(policy->addr, addr); 1947 policy->mapping = mapping; 1948 policy->action = action; 1949 policy->port = port; 1950 policy->vid = vid; 1951 1952 err = mv88e6xxx_policy_apply(chip, port, policy); 1953 if (err) { 1954 idr_remove(&chip->policies, fs->location); 1955 devm_kfree(chip->dev, policy); 1956 return err; 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1963 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1964 { 1965 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1966 struct mv88e6xxx_chip *chip = ds->priv; 1967 struct mv88e6xxx_policy *policy; 1968 int err; 1969 int id; 1970 1971 mv88e6xxx_reg_lock(chip); 1972 1973 switch (rxnfc->cmd) { 1974 case ETHTOOL_GRXCLSRLCNT: 1975 rxnfc->data = 0; 1976 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1977 rxnfc->rule_cnt = 0; 1978 idr_for_each_entry(&chip->policies, policy, id) 1979 if (policy->port == port) 1980 rxnfc->rule_cnt++; 1981 err = 0; 1982 break; 1983 case ETHTOOL_GRXCLSRULE: 1984 err = -ENOENT; 1985 policy = idr_find(&chip->policies, fs->location); 1986 if (policy) { 1987 memcpy(fs, &policy->fs, sizeof(*fs)); 1988 err = 0; 1989 } 1990 break; 1991 case ETHTOOL_GRXCLSRLALL: 1992 rxnfc->data = 0; 1993 rxnfc->rule_cnt = 0; 1994 idr_for_each_entry(&chip->policies, policy, id) 1995 if (policy->port == port) 1996 rule_locs[rxnfc->rule_cnt++] = id; 1997 err = 0; 1998 break; 1999 default: 2000 err = -EOPNOTSUPP; 2001 break; 2002 } 2003 2004 mv88e6xxx_reg_unlock(chip); 2005 2006 return err; 2007 } 2008 2009 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2010 struct ethtool_rxnfc *rxnfc) 2011 { 2012 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2013 struct mv88e6xxx_chip *chip = ds->priv; 2014 struct mv88e6xxx_policy *policy; 2015 int err; 2016 2017 mv88e6xxx_reg_lock(chip); 2018 2019 switch (rxnfc->cmd) { 2020 case ETHTOOL_SRXCLSRLINS: 2021 err = mv88e6xxx_policy_insert(chip, port, fs); 2022 break; 2023 case ETHTOOL_SRXCLSRLDEL: 2024 err = -ENOENT; 2025 policy = idr_remove(&chip->policies, fs->location); 2026 if (policy) { 2027 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2028 err = mv88e6xxx_policy_apply(chip, port, policy); 2029 devm_kfree(chip->dev, policy); 2030 } 2031 break; 2032 default: 2033 err = -EOPNOTSUPP; 2034 break; 2035 } 2036 2037 mv88e6xxx_reg_unlock(chip); 2038 2039 return err; 2040 } 2041 2042 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2043 u16 vid) 2044 { 2045 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2046 u8 broadcast[ETH_ALEN]; 2047 2048 eth_broadcast_addr(broadcast); 2049 2050 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2051 } 2052 2053 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2054 { 2055 int port; 2056 int err; 2057 2058 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2059 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2060 struct net_device *brport; 2061 2062 if (dsa_is_unused_port(chip->ds, port)) 2063 continue; 2064 2065 brport = dsa_port_to_bridge_port(dp); 2066 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2067 /* Skip bridged user ports where broadcast 2068 * flooding is disabled. 2069 */ 2070 continue; 2071 2072 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2073 if (err) 2074 return err; 2075 } 2076 2077 return 0; 2078 } 2079 2080 struct mv88e6xxx_port_broadcast_sync_ctx { 2081 int port; 2082 bool flood; 2083 }; 2084 2085 static int 2086 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2087 const struct mv88e6xxx_vtu_entry *vlan, 2088 void *_ctx) 2089 { 2090 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2091 u8 broadcast[ETH_ALEN]; 2092 u8 state; 2093 2094 if (ctx->flood) 2095 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2096 else 2097 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2098 2099 eth_broadcast_addr(broadcast); 2100 2101 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2102 vlan->vid, state); 2103 } 2104 2105 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2106 bool flood) 2107 { 2108 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2109 .port = port, 2110 .flood = flood, 2111 }; 2112 struct mv88e6xxx_vtu_entry vid0 = { 2113 .vid = 0, 2114 }; 2115 int err; 2116 2117 /* Update the port's private database... */ 2118 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2119 if (err) 2120 return err; 2121 2122 /* ...and the database for all VLANs. */ 2123 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2124 &ctx); 2125 } 2126 2127 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2128 u16 vid, u8 member, bool warn) 2129 { 2130 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2131 struct mv88e6xxx_vtu_entry vlan; 2132 int i, err; 2133 2134 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2135 if (err) 2136 return err; 2137 2138 if (!vlan.valid) { 2139 memset(&vlan, 0, sizeof(vlan)); 2140 2141 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2142 if (err) 2143 return err; 2144 2145 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2146 if (i == port) 2147 vlan.member[i] = member; 2148 else 2149 vlan.member[i] = non_member; 2150 2151 vlan.vid = vid; 2152 vlan.valid = true; 2153 2154 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2155 if (err) 2156 return err; 2157 2158 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2159 if (err) 2160 return err; 2161 } else if (vlan.member[port] != member) { 2162 vlan.member[port] = member; 2163 2164 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2165 if (err) 2166 return err; 2167 } else if (warn) { 2168 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2169 port, vid); 2170 } 2171 2172 return 0; 2173 } 2174 2175 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2176 const struct switchdev_obj_port_vlan *vlan, 2177 struct netlink_ext_ack *extack) 2178 { 2179 struct mv88e6xxx_chip *chip = ds->priv; 2180 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2181 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2182 struct mv88e6xxx_port *p = &chip->ports[port]; 2183 bool warn; 2184 u8 member; 2185 int err; 2186 2187 if (!vlan->vid) 2188 return 0; 2189 2190 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2191 if (err) 2192 return err; 2193 2194 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2195 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2196 else if (untagged) 2197 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2198 else 2199 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2200 2201 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2202 * and then the CPU port. Do not warn for duplicates for the CPU port. 2203 */ 2204 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2205 2206 mv88e6xxx_reg_lock(chip); 2207 2208 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2209 if (err) { 2210 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2211 vlan->vid, untagged ? 'u' : 't'); 2212 goto out; 2213 } 2214 2215 if (pvid) { 2216 p->bridge_pvid.vid = vlan->vid; 2217 p->bridge_pvid.valid = true; 2218 2219 err = mv88e6xxx_port_commit_pvid(chip, port); 2220 if (err) 2221 goto out; 2222 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2223 /* The old pvid was reinstalled as a non-pvid VLAN */ 2224 p->bridge_pvid.valid = false; 2225 2226 err = mv88e6xxx_port_commit_pvid(chip, port); 2227 if (err) 2228 goto out; 2229 } 2230 2231 out: 2232 mv88e6xxx_reg_unlock(chip); 2233 2234 return err; 2235 } 2236 2237 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2238 int port, u16 vid) 2239 { 2240 struct mv88e6xxx_vtu_entry vlan; 2241 int i, err; 2242 2243 if (!vid) 2244 return 0; 2245 2246 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2247 if (err) 2248 return err; 2249 2250 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2251 * tell switchdev that this VLAN is likely handled in software. 2252 */ 2253 if (!vlan.valid || 2254 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2255 return -EOPNOTSUPP; 2256 2257 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2258 2259 /* keep the VLAN unless all ports are excluded */ 2260 vlan.valid = false; 2261 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2262 if (vlan.member[i] != 2263 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2264 vlan.valid = true; 2265 break; 2266 } 2267 } 2268 2269 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2270 if (err) 2271 return err; 2272 2273 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2274 } 2275 2276 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2277 const struct switchdev_obj_port_vlan *vlan) 2278 { 2279 struct mv88e6xxx_chip *chip = ds->priv; 2280 struct mv88e6xxx_port *p = &chip->ports[port]; 2281 int err = 0; 2282 u16 pvid; 2283 2284 if (!mv88e6xxx_max_vid(chip)) 2285 return -EOPNOTSUPP; 2286 2287 mv88e6xxx_reg_lock(chip); 2288 2289 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2290 if (err) 2291 goto unlock; 2292 2293 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2294 if (err) 2295 goto unlock; 2296 2297 if (vlan->vid == pvid) { 2298 p->bridge_pvid.valid = false; 2299 2300 err = mv88e6xxx_port_commit_pvid(chip, port); 2301 if (err) 2302 goto unlock; 2303 } 2304 2305 unlock: 2306 mv88e6xxx_reg_unlock(chip); 2307 2308 return err; 2309 } 2310 2311 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2312 const unsigned char *addr, u16 vid) 2313 { 2314 struct mv88e6xxx_chip *chip = ds->priv; 2315 int err; 2316 2317 mv88e6xxx_reg_lock(chip); 2318 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2319 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2320 mv88e6xxx_reg_unlock(chip); 2321 2322 return err; 2323 } 2324 2325 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2326 const unsigned char *addr, u16 vid) 2327 { 2328 struct mv88e6xxx_chip *chip = ds->priv; 2329 int err; 2330 2331 mv88e6xxx_reg_lock(chip); 2332 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2333 mv88e6xxx_reg_unlock(chip); 2334 2335 return err; 2336 } 2337 2338 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2339 u16 fid, u16 vid, int port, 2340 dsa_fdb_dump_cb_t *cb, void *data) 2341 { 2342 struct mv88e6xxx_atu_entry addr; 2343 bool is_static; 2344 int err; 2345 2346 addr.state = 0; 2347 eth_broadcast_addr(addr.mac); 2348 2349 do { 2350 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2351 if (err) 2352 return err; 2353 2354 if (!addr.state) 2355 break; 2356 2357 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2358 continue; 2359 2360 if (!is_unicast_ether_addr(addr.mac)) 2361 continue; 2362 2363 is_static = (addr.state == 2364 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2365 err = cb(addr.mac, vid, is_static, data); 2366 if (err) 2367 return err; 2368 } while (!is_broadcast_ether_addr(addr.mac)); 2369 2370 return err; 2371 } 2372 2373 struct mv88e6xxx_port_db_dump_vlan_ctx { 2374 int port; 2375 dsa_fdb_dump_cb_t *cb; 2376 void *data; 2377 }; 2378 2379 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2380 const struct mv88e6xxx_vtu_entry *entry, 2381 void *_data) 2382 { 2383 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2384 2385 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2386 ctx->port, ctx->cb, ctx->data); 2387 } 2388 2389 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2390 dsa_fdb_dump_cb_t *cb, void *data) 2391 { 2392 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2393 .port = port, 2394 .cb = cb, 2395 .data = data, 2396 }; 2397 u16 fid; 2398 int err; 2399 2400 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2401 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2402 if (err) 2403 return err; 2404 2405 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2406 if (err) 2407 return err; 2408 2409 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2410 } 2411 2412 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2413 dsa_fdb_dump_cb_t *cb, void *data) 2414 { 2415 struct mv88e6xxx_chip *chip = ds->priv; 2416 int err; 2417 2418 mv88e6xxx_reg_lock(chip); 2419 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2420 mv88e6xxx_reg_unlock(chip); 2421 2422 return err; 2423 } 2424 2425 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2426 struct dsa_bridge bridge) 2427 { 2428 struct dsa_switch *ds = chip->ds; 2429 struct dsa_switch_tree *dst = ds->dst; 2430 struct dsa_port *dp; 2431 int err; 2432 2433 list_for_each_entry(dp, &dst->ports, list) { 2434 if (dsa_port_offloads_bridge(dp, &bridge)) { 2435 if (dp->ds == ds) { 2436 /* This is a local bridge group member, 2437 * remap its Port VLAN Map. 2438 */ 2439 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2440 if (err) 2441 return err; 2442 } else { 2443 /* This is an external bridge group member, 2444 * remap its cross-chip Port VLAN Table entry. 2445 */ 2446 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2447 dp->index); 2448 if (err) 2449 return err; 2450 } 2451 } 2452 } 2453 2454 return 0; 2455 } 2456 2457 /* Treat the software bridge as a virtual single-port switch behind the 2458 * CPU and map in the PVT. First dst->last_switch elements are taken by 2459 * physical switches, so start from beyond that range. 2460 */ 2461 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2462 unsigned int bridge_num) 2463 { 2464 u8 dev = bridge_num + ds->dst->last_switch; 2465 struct mv88e6xxx_chip *chip = ds->priv; 2466 2467 return mv88e6xxx_pvt_map(chip, dev, 0); 2468 } 2469 2470 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2471 struct dsa_bridge bridge, 2472 bool *tx_fwd_offload) 2473 { 2474 struct mv88e6xxx_chip *chip = ds->priv; 2475 int err; 2476 2477 mv88e6xxx_reg_lock(chip); 2478 2479 err = mv88e6xxx_bridge_map(chip, bridge); 2480 if (err) 2481 goto unlock; 2482 2483 err = mv88e6xxx_port_commit_pvid(chip, port); 2484 if (err) 2485 goto unlock; 2486 2487 if (mv88e6xxx_has_pvt(chip)) { 2488 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2489 if (err) 2490 goto unlock; 2491 2492 *tx_fwd_offload = true; 2493 } 2494 2495 unlock: 2496 mv88e6xxx_reg_unlock(chip); 2497 2498 return err; 2499 } 2500 2501 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2502 struct dsa_bridge bridge) 2503 { 2504 struct mv88e6xxx_chip *chip = ds->priv; 2505 int err; 2506 2507 mv88e6xxx_reg_lock(chip); 2508 2509 if (bridge.tx_fwd_offload && 2510 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2511 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2512 2513 if (mv88e6xxx_bridge_map(chip, bridge) || 2514 mv88e6xxx_port_vlan_map(chip, port)) 2515 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2516 2517 err = mv88e6xxx_port_commit_pvid(chip, port); 2518 if (err) 2519 dev_err(ds->dev, 2520 "port %d failed to restore standalone pvid: %pe\n", 2521 port, ERR_PTR(err)); 2522 2523 mv88e6xxx_reg_unlock(chip); 2524 } 2525 2526 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2527 int tree_index, int sw_index, 2528 int port, struct dsa_bridge bridge) 2529 { 2530 struct mv88e6xxx_chip *chip = ds->priv; 2531 int err; 2532 2533 if (tree_index != ds->dst->index) 2534 return 0; 2535 2536 mv88e6xxx_reg_lock(chip); 2537 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2538 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2539 mv88e6xxx_reg_unlock(chip); 2540 2541 return err; 2542 } 2543 2544 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2545 int tree_index, int sw_index, 2546 int port, struct dsa_bridge bridge) 2547 { 2548 struct mv88e6xxx_chip *chip = ds->priv; 2549 2550 if (tree_index != ds->dst->index) 2551 return; 2552 2553 mv88e6xxx_reg_lock(chip); 2554 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2555 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2556 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2557 mv88e6xxx_reg_unlock(chip); 2558 } 2559 2560 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2561 { 2562 if (chip->info->ops->reset) 2563 return chip->info->ops->reset(chip); 2564 2565 return 0; 2566 } 2567 2568 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2569 { 2570 struct gpio_desc *gpiod = chip->reset; 2571 2572 /* If there is a GPIO connected to the reset pin, toggle it */ 2573 if (gpiod) { 2574 gpiod_set_value_cansleep(gpiod, 1); 2575 usleep_range(10000, 20000); 2576 gpiod_set_value_cansleep(gpiod, 0); 2577 usleep_range(10000, 20000); 2578 2579 mv88e6xxx_g1_wait_eeprom_done(chip); 2580 } 2581 } 2582 2583 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2584 { 2585 int i, err; 2586 2587 /* Set all ports to the Disabled state */ 2588 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2589 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2590 if (err) 2591 return err; 2592 } 2593 2594 /* Wait for transmit queues to drain, 2595 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2596 */ 2597 usleep_range(2000, 4000); 2598 2599 return 0; 2600 } 2601 2602 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2603 { 2604 int err; 2605 2606 err = mv88e6xxx_disable_ports(chip); 2607 if (err) 2608 return err; 2609 2610 mv88e6xxx_hardware_reset(chip); 2611 2612 return mv88e6xxx_software_reset(chip); 2613 } 2614 2615 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2616 enum mv88e6xxx_frame_mode frame, 2617 enum mv88e6xxx_egress_mode egress, u16 etype) 2618 { 2619 int err; 2620 2621 if (!chip->info->ops->port_set_frame_mode) 2622 return -EOPNOTSUPP; 2623 2624 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2625 if (err) 2626 return err; 2627 2628 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2629 if (err) 2630 return err; 2631 2632 if (chip->info->ops->port_set_ether_type) 2633 return chip->info->ops->port_set_ether_type(chip, port, etype); 2634 2635 return 0; 2636 } 2637 2638 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2639 { 2640 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2641 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2642 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2643 } 2644 2645 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2646 { 2647 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2648 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2649 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2650 } 2651 2652 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2653 { 2654 return mv88e6xxx_set_port_mode(chip, port, 2655 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2656 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2657 ETH_P_EDSA); 2658 } 2659 2660 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2661 { 2662 if (dsa_is_dsa_port(chip->ds, port)) 2663 return mv88e6xxx_set_port_mode_dsa(chip, port); 2664 2665 if (dsa_is_user_port(chip->ds, port)) 2666 return mv88e6xxx_set_port_mode_normal(chip, port); 2667 2668 /* Setup CPU port mode depending on its supported tag format */ 2669 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2670 return mv88e6xxx_set_port_mode_dsa(chip, port); 2671 2672 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2673 return mv88e6xxx_set_port_mode_edsa(chip, port); 2674 2675 return -EINVAL; 2676 } 2677 2678 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2679 { 2680 bool message = dsa_is_dsa_port(chip->ds, port); 2681 2682 return mv88e6xxx_port_set_message_port(chip, port, message); 2683 } 2684 2685 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2686 { 2687 int err; 2688 2689 if (chip->info->ops->port_set_ucast_flood) { 2690 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2691 if (err) 2692 return err; 2693 } 2694 if (chip->info->ops->port_set_mcast_flood) { 2695 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2696 if (err) 2697 return err; 2698 } 2699 2700 return 0; 2701 } 2702 2703 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2704 { 2705 struct mv88e6xxx_port *mvp = dev_id; 2706 struct mv88e6xxx_chip *chip = mvp->chip; 2707 irqreturn_t ret = IRQ_NONE; 2708 int port = mvp->port; 2709 int lane; 2710 2711 mv88e6xxx_reg_lock(chip); 2712 lane = mv88e6xxx_serdes_get_lane(chip, port); 2713 if (lane >= 0) 2714 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2715 mv88e6xxx_reg_unlock(chip); 2716 2717 return ret; 2718 } 2719 2720 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2721 int lane) 2722 { 2723 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2724 unsigned int irq; 2725 int err; 2726 2727 /* Nothing to request if this SERDES port has no IRQ */ 2728 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2729 if (!irq) 2730 return 0; 2731 2732 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2733 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2734 2735 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2736 mv88e6xxx_reg_unlock(chip); 2737 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2738 IRQF_ONESHOT, dev_id->serdes_irq_name, 2739 dev_id); 2740 mv88e6xxx_reg_lock(chip); 2741 if (err) 2742 return err; 2743 2744 dev_id->serdes_irq = irq; 2745 2746 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2747 } 2748 2749 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2750 int lane) 2751 { 2752 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2753 unsigned int irq = dev_id->serdes_irq; 2754 int err; 2755 2756 /* Nothing to free if no IRQ has been requested */ 2757 if (!irq) 2758 return 0; 2759 2760 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2761 2762 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2763 mv88e6xxx_reg_unlock(chip); 2764 free_irq(irq, dev_id); 2765 mv88e6xxx_reg_lock(chip); 2766 2767 dev_id->serdes_irq = 0; 2768 2769 return err; 2770 } 2771 2772 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2773 bool on) 2774 { 2775 int lane; 2776 int err; 2777 2778 lane = mv88e6xxx_serdes_get_lane(chip, port); 2779 if (lane < 0) 2780 return 0; 2781 2782 if (on) { 2783 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2784 if (err) 2785 return err; 2786 2787 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2788 } else { 2789 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2790 if (err) 2791 return err; 2792 2793 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2794 } 2795 2796 return err; 2797 } 2798 2799 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2800 enum mv88e6xxx_egress_direction direction, 2801 int port) 2802 { 2803 int err; 2804 2805 if (!chip->info->ops->set_egress_port) 2806 return -EOPNOTSUPP; 2807 2808 err = chip->info->ops->set_egress_port(chip, direction, port); 2809 if (err) 2810 return err; 2811 2812 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2813 chip->ingress_dest_port = port; 2814 else 2815 chip->egress_dest_port = port; 2816 2817 return 0; 2818 } 2819 2820 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2821 { 2822 struct dsa_switch *ds = chip->ds; 2823 int upstream_port; 2824 int err; 2825 2826 upstream_port = dsa_upstream_port(ds, port); 2827 if (chip->info->ops->port_set_upstream_port) { 2828 err = chip->info->ops->port_set_upstream_port(chip, port, 2829 upstream_port); 2830 if (err) 2831 return err; 2832 } 2833 2834 if (port == upstream_port) { 2835 if (chip->info->ops->set_cpu_port) { 2836 err = chip->info->ops->set_cpu_port(chip, 2837 upstream_port); 2838 if (err) 2839 return err; 2840 } 2841 2842 err = mv88e6xxx_set_egress_port(chip, 2843 MV88E6XXX_EGRESS_DIR_INGRESS, 2844 upstream_port); 2845 if (err && err != -EOPNOTSUPP) 2846 return err; 2847 2848 err = mv88e6xxx_set_egress_port(chip, 2849 MV88E6XXX_EGRESS_DIR_EGRESS, 2850 upstream_port); 2851 if (err && err != -EOPNOTSUPP) 2852 return err; 2853 } 2854 2855 return 0; 2856 } 2857 2858 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2859 { 2860 struct dsa_switch *ds = chip->ds; 2861 int err; 2862 u16 reg; 2863 2864 chip->ports[port].chip = chip; 2865 chip->ports[port].port = port; 2866 2867 /* MAC Forcing register: don't force link, speed, duplex or flow control 2868 * state to any particular values on physical ports, but force the CPU 2869 * port and all DSA ports to their maximum bandwidth and full duplex. 2870 */ 2871 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2872 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2873 SPEED_MAX, DUPLEX_FULL, 2874 PAUSE_OFF, 2875 PHY_INTERFACE_MODE_NA); 2876 else 2877 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2878 SPEED_UNFORCED, DUPLEX_UNFORCED, 2879 PAUSE_ON, 2880 PHY_INTERFACE_MODE_NA); 2881 if (err) 2882 return err; 2883 2884 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2885 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2886 * tunneling, determine priority by looking at 802.1p and IP 2887 * priority fields (IP prio has precedence), and set STP state 2888 * to Forwarding. 2889 * 2890 * If this is the CPU link, use DSA or EDSA tagging depending 2891 * on which tagging mode was configured. 2892 * 2893 * If this is a link to another switch, use DSA tagging mode. 2894 * 2895 * If this is the upstream port for this switch, enable 2896 * forwarding of unknown unicasts and multicasts. 2897 */ 2898 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2899 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2900 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2901 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2902 if (err) 2903 return err; 2904 2905 err = mv88e6xxx_setup_port_mode(chip, port); 2906 if (err) 2907 return err; 2908 2909 err = mv88e6xxx_setup_egress_floods(chip, port); 2910 if (err) 2911 return err; 2912 2913 /* Port Control 2: don't force a good FCS, set the MTU size to 2914 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2915 * untagged frames on this port, do a destination address lookup on all 2916 * received packets as usual, disable ARP mirroring and don't send a 2917 * copy of all transmitted/received frames on this port to the CPU. 2918 */ 2919 err = mv88e6xxx_port_set_map_da(chip, port); 2920 if (err) 2921 return err; 2922 2923 err = mv88e6xxx_setup_upstream_port(chip, port); 2924 if (err) 2925 return err; 2926 2927 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2928 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2929 if (err) 2930 return err; 2931 2932 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2933 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2934 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2935 * as the private PVID on ports under a VLAN-unaware bridge. 2936 * Shared (DSA and CPU) ports must also be members of it, to translate 2937 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2938 * relying on their port default FID. 2939 */ 2940 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2941 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2942 false); 2943 if (err) 2944 return err; 2945 2946 if (chip->info->ops->port_set_jumbo_size) { 2947 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2948 if (err) 2949 return err; 2950 } 2951 2952 /* Port Association Vector: disable automatic address learning 2953 * on all user ports since they start out in standalone 2954 * mode. When joining a bridge, learning will be configured to 2955 * match the bridge port settings. Enable learning on all 2956 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2957 * learning process. 2958 * 2959 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2960 * and RefreshLocked. I.e. setup standard automatic learning. 2961 */ 2962 if (dsa_is_user_port(ds, port)) 2963 reg = 0; 2964 else 2965 reg = 1 << port; 2966 2967 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2968 reg); 2969 if (err) 2970 return err; 2971 2972 /* Egress rate control 2: disable egress rate control. */ 2973 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2974 0x0000); 2975 if (err) 2976 return err; 2977 2978 if (chip->info->ops->port_pause_limit) { 2979 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2980 if (err) 2981 return err; 2982 } 2983 2984 if (chip->info->ops->port_disable_learn_limit) { 2985 err = chip->info->ops->port_disable_learn_limit(chip, port); 2986 if (err) 2987 return err; 2988 } 2989 2990 if (chip->info->ops->port_disable_pri_override) { 2991 err = chip->info->ops->port_disable_pri_override(chip, port); 2992 if (err) 2993 return err; 2994 } 2995 2996 if (chip->info->ops->port_tag_remap) { 2997 err = chip->info->ops->port_tag_remap(chip, port); 2998 if (err) 2999 return err; 3000 } 3001 3002 if (chip->info->ops->port_egress_rate_limiting) { 3003 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3004 if (err) 3005 return err; 3006 } 3007 3008 if (chip->info->ops->port_setup_message_port) { 3009 err = chip->info->ops->port_setup_message_port(chip, port); 3010 if (err) 3011 return err; 3012 } 3013 3014 /* Port based VLAN map: give each port the same default address 3015 * database, and allow bidirectional communication between the 3016 * CPU and DSA port(s), and the other ports. 3017 */ 3018 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3019 if (err) 3020 return err; 3021 3022 err = mv88e6xxx_port_vlan_map(chip, port); 3023 if (err) 3024 return err; 3025 3026 /* Default VLAN ID and priority: don't set a default VLAN 3027 * ID, and set the default packet priority to zero. 3028 */ 3029 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3030 } 3031 3032 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3033 { 3034 struct mv88e6xxx_chip *chip = ds->priv; 3035 3036 if (chip->info->ops->port_set_jumbo_size) 3037 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3038 else if (chip->info->ops->set_max_frame_size) 3039 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3040 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3041 } 3042 3043 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3044 { 3045 struct mv88e6xxx_chip *chip = ds->priv; 3046 int ret = 0; 3047 3048 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3049 new_mtu += EDSA_HLEN; 3050 3051 mv88e6xxx_reg_lock(chip); 3052 if (chip->info->ops->port_set_jumbo_size) 3053 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3054 else if (chip->info->ops->set_max_frame_size) 3055 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3056 else 3057 if (new_mtu > 1522) 3058 ret = -EINVAL; 3059 mv88e6xxx_reg_unlock(chip); 3060 3061 return ret; 3062 } 3063 3064 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3065 struct phy_device *phydev) 3066 { 3067 struct mv88e6xxx_chip *chip = ds->priv; 3068 int err; 3069 3070 mv88e6xxx_reg_lock(chip); 3071 err = mv88e6xxx_serdes_power(chip, port, true); 3072 mv88e6xxx_reg_unlock(chip); 3073 3074 return err; 3075 } 3076 3077 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3078 { 3079 struct mv88e6xxx_chip *chip = ds->priv; 3080 3081 mv88e6xxx_reg_lock(chip); 3082 if (mv88e6xxx_serdes_power(chip, port, false)) 3083 dev_err(chip->dev, "failed to power off SERDES\n"); 3084 mv88e6xxx_reg_unlock(chip); 3085 } 3086 3087 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3088 unsigned int ageing_time) 3089 { 3090 struct mv88e6xxx_chip *chip = ds->priv; 3091 int err; 3092 3093 mv88e6xxx_reg_lock(chip); 3094 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3095 mv88e6xxx_reg_unlock(chip); 3096 3097 return err; 3098 } 3099 3100 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3101 { 3102 int err; 3103 3104 /* Initialize the statistics unit */ 3105 if (chip->info->ops->stats_set_histogram) { 3106 err = chip->info->ops->stats_set_histogram(chip); 3107 if (err) 3108 return err; 3109 } 3110 3111 return mv88e6xxx_g1_stats_clear(chip); 3112 } 3113 3114 /* Check if the errata has already been applied. */ 3115 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3116 { 3117 int port; 3118 int err; 3119 u16 val; 3120 3121 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3122 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3123 if (err) { 3124 dev_err(chip->dev, 3125 "Error reading hidden register: %d\n", err); 3126 return false; 3127 } 3128 if (val != 0x01c0) 3129 return false; 3130 } 3131 3132 return true; 3133 } 3134 3135 /* The 6390 copper ports have an errata which require poking magic 3136 * values into undocumented hidden registers and then performing a 3137 * software reset. 3138 */ 3139 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3140 { 3141 int port; 3142 int err; 3143 3144 if (mv88e6390_setup_errata_applied(chip)) 3145 return 0; 3146 3147 /* Set the ports into blocking mode */ 3148 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3149 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3150 if (err) 3151 return err; 3152 } 3153 3154 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3155 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3156 if (err) 3157 return err; 3158 } 3159 3160 return mv88e6xxx_software_reset(chip); 3161 } 3162 3163 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3164 { 3165 mv88e6xxx_teardown_devlink_params(ds); 3166 dsa_devlink_resources_unregister(ds); 3167 mv88e6xxx_teardown_devlink_regions_global(ds); 3168 } 3169 3170 static int mv88e6xxx_setup(struct dsa_switch *ds) 3171 { 3172 struct mv88e6xxx_chip *chip = ds->priv; 3173 u8 cmode; 3174 int err; 3175 int i; 3176 3177 chip->ds = ds; 3178 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3179 3180 /* Since virtual bridges are mapped in the PVT, the number we support 3181 * depends on the physical switch topology. We need to let DSA figure 3182 * that out and therefore we cannot set this at dsa_register_switch() 3183 * time. 3184 */ 3185 if (mv88e6xxx_has_pvt(chip)) 3186 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3187 ds->dst->last_switch - 1; 3188 3189 mv88e6xxx_reg_lock(chip); 3190 3191 if (chip->info->ops->setup_errata) { 3192 err = chip->info->ops->setup_errata(chip); 3193 if (err) 3194 goto unlock; 3195 } 3196 3197 /* Cache the cmode of each port. */ 3198 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3199 if (chip->info->ops->port_get_cmode) { 3200 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3201 if (err) 3202 goto unlock; 3203 3204 chip->ports[i].cmode = cmode; 3205 } 3206 } 3207 3208 err = mv88e6xxx_vtu_setup(chip); 3209 if (err) 3210 goto unlock; 3211 3212 /* Setup Switch Port Registers */ 3213 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3214 if (dsa_is_unused_port(ds, i)) 3215 continue; 3216 3217 /* Prevent the use of an invalid port. */ 3218 if (mv88e6xxx_is_invalid_port(chip, i)) { 3219 dev_err(chip->dev, "port %d is invalid\n", i); 3220 err = -EINVAL; 3221 goto unlock; 3222 } 3223 3224 err = mv88e6xxx_setup_port(chip, i); 3225 if (err) 3226 goto unlock; 3227 } 3228 3229 err = mv88e6xxx_irl_setup(chip); 3230 if (err) 3231 goto unlock; 3232 3233 err = mv88e6xxx_mac_setup(chip); 3234 if (err) 3235 goto unlock; 3236 3237 err = mv88e6xxx_phy_setup(chip); 3238 if (err) 3239 goto unlock; 3240 3241 err = mv88e6xxx_pvt_setup(chip); 3242 if (err) 3243 goto unlock; 3244 3245 err = mv88e6xxx_atu_setup(chip); 3246 if (err) 3247 goto unlock; 3248 3249 err = mv88e6xxx_broadcast_setup(chip, 0); 3250 if (err) 3251 goto unlock; 3252 3253 err = mv88e6xxx_pot_setup(chip); 3254 if (err) 3255 goto unlock; 3256 3257 err = mv88e6xxx_rmu_setup(chip); 3258 if (err) 3259 goto unlock; 3260 3261 err = mv88e6xxx_rsvd2cpu_setup(chip); 3262 if (err) 3263 goto unlock; 3264 3265 err = mv88e6xxx_trunk_setup(chip); 3266 if (err) 3267 goto unlock; 3268 3269 err = mv88e6xxx_devmap_setup(chip); 3270 if (err) 3271 goto unlock; 3272 3273 err = mv88e6xxx_pri_setup(chip); 3274 if (err) 3275 goto unlock; 3276 3277 /* Setup PTP Hardware Clock and timestamping */ 3278 if (chip->info->ptp_support) { 3279 err = mv88e6xxx_ptp_setup(chip); 3280 if (err) 3281 goto unlock; 3282 3283 err = mv88e6xxx_hwtstamp_setup(chip); 3284 if (err) 3285 goto unlock; 3286 } 3287 3288 err = mv88e6xxx_stats_setup(chip); 3289 if (err) 3290 goto unlock; 3291 3292 unlock: 3293 mv88e6xxx_reg_unlock(chip); 3294 3295 if (err) 3296 return err; 3297 3298 /* Have to be called without holding the register lock, since 3299 * they take the devlink lock, and we later take the locks in 3300 * the reverse order when getting/setting parameters or 3301 * resource occupancy. 3302 */ 3303 err = mv88e6xxx_setup_devlink_resources(ds); 3304 if (err) 3305 return err; 3306 3307 err = mv88e6xxx_setup_devlink_params(ds); 3308 if (err) 3309 goto out_resources; 3310 3311 err = mv88e6xxx_setup_devlink_regions_global(ds); 3312 if (err) 3313 goto out_params; 3314 3315 return 0; 3316 3317 out_params: 3318 mv88e6xxx_teardown_devlink_params(ds); 3319 out_resources: 3320 dsa_devlink_resources_unregister(ds); 3321 3322 return err; 3323 } 3324 3325 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3326 { 3327 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3328 } 3329 3330 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3331 { 3332 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3333 } 3334 3335 /* prod_id for switch families which do not have a PHY model number */ 3336 static const u16 family_prod_id_table[] = { 3337 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3338 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3339 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3340 }; 3341 3342 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3343 { 3344 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3345 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3346 u16 prod_id; 3347 u16 val; 3348 int err; 3349 3350 if (!chip->info->ops->phy_read) 3351 return -EOPNOTSUPP; 3352 3353 mv88e6xxx_reg_lock(chip); 3354 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3355 mv88e6xxx_reg_unlock(chip); 3356 3357 /* Some internal PHYs don't have a model number. */ 3358 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3359 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3360 prod_id = family_prod_id_table[chip->info->family]; 3361 if (prod_id) 3362 val |= prod_id >> 4; 3363 } 3364 3365 return err ? err : val; 3366 } 3367 3368 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3369 { 3370 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3371 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3372 int err; 3373 3374 if (!chip->info->ops->phy_write) 3375 return -EOPNOTSUPP; 3376 3377 mv88e6xxx_reg_lock(chip); 3378 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3379 mv88e6xxx_reg_unlock(chip); 3380 3381 return err; 3382 } 3383 3384 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3385 struct device_node *np, 3386 bool external) 3387 { 3388 static int index; 3389 struct mv88e6xxx_mdio_bus *mdio_bus; 3390 struct mii_bus *bus; 3391 int err; 3392 3393 if (external) { 3394 mv88e6xxx_reg_lock(chip); 3395 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3396 mv88e6xxx_reg_unlock(chip); 3397 3398 if (err) 3399 return err; 3400 } 3401 3402 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3403 if (!bus) 3404 return -ENOMEM; 3405 3406 mdio_bus = bus->priv; 3407 mdio_bus->bus = bus; 3408 mdio_bus->chip = chip; 3409 INIT_LIST_HEAD(&mdio_bus->list); 3410 mdio_bus->external = external; 3411 3412 if (np) { 3413 bus->name = np->full_name; 3414 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3415 } else { 3416 bus->name = "mv88e6xxx SMI"; 3417 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3418 } 3419 3420 bus->read = mv88e6xxx_mdio_read; 3421 bus->write = mv88e6xxx_mdio_write; 3422 bus->parent = chip->dev; 3423 3424 if (!external) { 3425 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3426 if (err) 3427 return err; 3428 } 3429 3430 err = of_mdiobus_register(bus, np); 3431 if (err) { 3432 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3433 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3434 return err; 3435 } 3436 3437 if (external) 3438 list_add_tail(&mdio_bus->list, &chip->mdios); 3439 else 3440 list_add(&mdio_bus->list, &chip->mdios); 3441 3442 return 0; 3443 } 3444 3445 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3446 3447 { 3448 struct mv88e6xxx_mdio_bus *mdio_bus; 3449 struct mii_bus *bus; 3450 3451 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3452 bus = mdio_bus->bus; 3453 3454 if (!mdio_bus->external) 3455 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3456 3457 mdiobus_unregister(bus); 3458 } 3459 } 3460 3461 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3462 struct device_node *np) 3463 { 3464 struct device_node *child; 3465 int err; 3466 3467 /* Always register one mdio bus for the internal/default mdio 3468 * bus. This maybe represented in the device tree, but is 3469 * optional. 3470 */ 3471 child = of_get_child_by_name(np, "mdio"); 3472 err = mv88e6xxx_mdio_register(chip, child, false); 3473 if (err) 3474 return err; 3475 3476 /* Walk the device tree, and see if there are any other nodes 3477 * which say they are compatible with the external mdio 3478 * bus. 3479 */ 3480 for_each_available_child_of_node(np, child) { 3481 if (of_device_is_compatible( 3482 child, "marvell,mv88e6xxx-mdio-external")) { 3483 err = mv88e6xxx_mdio_register(chip, child, true); 3484 if (err) { 3485 mv88e6xxx_mdios_unregister(chip); 3486 of_node_put(child); 3487 return err; 3488 } 3489 } 3490 } 3491 3492 return 0; 3493 } 3494 3495 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3496 { 3497 struct mv88e6xxx_chip *chip = ds->priv; 3498 3499 return chip->eeprom_len; 3500 } 3501 3502 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3503 struct ethtool_eeprom *eeprom, u8 *data) 3504 { 3505 struct mv88e6xxx_chip *chip = ds->priv; 3506 int err; 3507 3508 if (!chip->info->ops->get_eeprom) 3509 return -EOPNOTSUPP; 3510 3511 mv88e6xxx_reg_lock(chip); 3512 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3513 mv88e6xxx_reg_unlock(chip); 3514 3515 if (err) 3516 return err; 3517 3518 eeprom->magic = 0xc3ec4951; 3519 3520 return 0; 3521 } 3522 3523 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3524 struct ethtool_eeprom *eeprom, u8 *data) 3525 { 3526 struct mv88e6xxx_chip *chip = ds->priv; 3527 int err; 3528 3529 if (!chip->info->ops->set_eeprom) 3530 return -EOPNOTSUPP; 3531 3532 if (eeprom->magic != 0xc3ec4951) 3533 return -EINVAL; 3534 3535 mv88e6xxx_reg_lock(chip); 3536 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3537 mv88e6xxx_reg_unlock(chip); 3538 3539 return err; 3540 } 3541 3542 static const struct mv88e6xxx_ops mv88e6085_ops = { 3543 /* MV88E6XXX_FAMILY_6097 */ 3544 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3545 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3546 .irl_init_all = mv88e6352_g2_irl_init_all, 3547 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3548 .phy_read = mv88e6185_phy_ppu_read, 3549 .phy_write = mv88e6185_phy_ppu_write, 3550 .port_set_link = mv88e6xxx_port_set_link, 3551 .port_sync_link = mv88e6xxx_port_sync_link, 3552 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3553 .port_tag_remap = mv88e6095_port_tag_remap, 3554 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3555 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3556 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3557 .port_set_ether_type = mv88e6351_port_set_ether_type, 3558 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3559 .port_pause_limit = mv88e6097_port_pause_limit, 3560 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3561 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3562 .port_get_cmode = mv88e6185_port_get_cmode, 3563 .port_setup_message_port = mv88e6xxx_setup_message_port, 3564 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3565 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3566 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3567 .stats_get_strings = mv88e6095_stats_get_strings, 3568 .stats_get_stats = mv88e6095_stats_get_stats, 3569 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3570 .set_egress_port = mv88e6095_g1_set_egress_port, 3571 .watchdog_ops = &mv88e6097_watchdog_ops, 3572 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3573 .pot_clear = mv88e6xxx_g2_pot_clear, 3574 .ppu_enable = mv88e6185_g1_ppu_enable, 3575 .ppu_disable = mv88e6185_g1_ppu_disable, 3576 .reset = mv88e6185_g1_reset, 3577 .rmu_disable = mv88e6085_g1_rmu_disable, 3578 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3579 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3580 .phylink_validate = mv88e6185_phylink_validate, 3581 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3582 }; 3583 3584 static const struct mv88e6xxx_ops mv88e6095_ops = { 3585 /* MV88E6XXX_FAMILY_6095 */ 3586 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3587 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3588 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3589 .phy_read = mv88e6185_phy_ppu_read, 3590 .phy_write = mv88e6185_phy_ppu_write, 3591 .port_set_link = mv88e6xxx_port_set_link, 3592 .port_sync_link = mv88e6185_port_sync_link, 3593 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3594 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3595 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3596 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3597 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3598 .port_get_cmode = mv88e6185_port_get_cmode, 3599 .port_setup_message_port = mv88e6xxx_setup_message_port, 3600 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3601 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3602 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3603 .stats_get_strings = mv88e6095_stats_get_strings, 3604 .stats_get_stats = mv88e6095_stats_get_stats, 3605 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3606 .serdes_power = mv88e6185_serdes_power, 3607 .serdes_get_lane = mv88e6185_serdes_get_lane, 3608 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3609 .ppu_enable = mv88e6185_g1_ppu_enable, 3610 .ppu_disable = mv88e6185_g1_ppu_disable, 3611 .reset = mv88e6185_g1_reset, 3612 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3613 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3614 .phylink_validate = mv88e6185_phylink_validate, 3615 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3616 }; 3617 3618 static const struct mv88e6xxx_ops mv88e6097_ops = { 3619 /* MV88E6XXX_FAMILY_6097 */ 3620 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3621 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3622 .irl_init_all = mv88e6352_g2_irl_init_all, 3623 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3624 .phy_read = mv88e6xxx_g2_smi_phy_read, 3625 .phy_write = mv88e6xxx_g2_smi_phy_write, 3626 .port_set_link = mv88e6xxx_port_set_link, 3627 .port_sync_link = mv88e6185_port_sync_link, 3628 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3629 .port_tag_remap = mv88e6095_port_tag_remap, 3630 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3631 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3632 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3633 .port_set_ether_type = mv88e6351_port_set_ether_type, 3634 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3635 .port_pause_limit = mv88e6097_port_pause_limit, 3636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3638 .port_get_cmode = mv88e6185_port_get_cmode, 3639 .port_setup_message_port = mv88e6xxx_setup_message_port, 3640 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3641 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3642 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3643 .stats_get_strings = mv88e6095_stats_get_strings, 3644 .stats_get_stats = mv88e6095_stats_get_stats, 3645 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3646 .set_egress_port = mv88e6095_g1_set_egress_port, 3647 .watchdog_ops = &mv88e6097_watchdog_ops, 3648 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3649 .serdes_power = mv88e6185_serdes_power, 3650 .serdes_get_lane = mv88e6185_serdes_get_lane, 3651 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3652 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3653 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3654 .serdes_irq_status = mv88e6097_serdes_irq_status, 3655 .pot_clear = mv88e6xxx_g2_pot_clear, 3656 .reset = mv88e6352_g1_reset, 3657 .rmu_disable = mv88e6085_g1_rmu_disable, 3658 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3660 .phylink_validate = mv88e6185_phylink_validate, 3661 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3662 }; 3663 3664 static const struct mv88e6xxx_ops mv88e6123_ops = { 3665 /* MV88E6XXX_FAMILY_6165 */ 3666 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3667 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3668 .irl_init_all = mv88e6352_g2_irl_init_all, 3669 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3670 .phy_read = mv88e6xxx_g2_smi_phy_read, 3671 .phy_write = mv88e6xxx_g2_smi_phy_write, 3672 .port_set_link = mv88e6xxx_port_set_link, 3673 .port_sync_link = mv88e6xxx_port_sync_link, 3674 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3675 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3676 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3677 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3678 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3679 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3680 .port_get_cmode = mv88e6185_port_get_cmode, 3681 .port_setup_message_port = mv88e6xxx_setup_message_port, 3682 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3683 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3684 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3685 .stats_get_strings = mv88e6095_stats_get_strings, 3686 .stats_get_stats = mv88e6095_stats_get_stats, 3687 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3688 .set_egress_port = mv88e6095_g1_set_egress_port, 3689 .watchdog_ops = &mv88e6097_watchdog_ops, 3690 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3691 .pot_clear = mv88e6xxx_g2_pot_clear, 3692 .reset = mv88e6352_g1_reset, 3693 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3694 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3695 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3696 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3697 .phylink_validate = mv88e6185_phylink_validate, 3698 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3699 }; 3700 3701 static const struct mv88e6xxx_ops mv88e6131_ops = { 3702 /* MV88E6XXX_FAMILY_6185 */ 3703 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3704 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3705 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3706 .phy_read = mv88e6185_phy_ppu_read, 3707 .phy_write = mv88e6185_phy_ppu_write, 3708 .port_set_link = mv88e6xxx_port_set_link, 3709 .port_sync_link = mv88e6xxx_port_sync_link, 3710 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3711 .port_tag_remap = mv88e6095_port_tag_remap, 3712 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3713 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3714 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3715 .port_set_ether_type = mv88e6351_port_set_ether_type, 3716 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3717 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3718 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3719 .port_pause_limit = mv88e6097_port_pause_limit, 3720 .port_set_pause = mv88e6185_port_set_pause, 3721 .port_get_cmode = mv88e6185_port_get_cmode, 3722 .port_setup_message_port = mv88e6xxx_setup_message_port, 3723 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3724 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3725 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3726 .stats_get_strings = mv88e6095_stats_get_strings, 3727 .stats_get_stats = mv88e6095_stats_get_stats, 3728 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3729 .set_egress_port = mv88e6095_g1_set_egress_port, 3730 .watchdog_ops = &mv88e6097_watchdog_ops, 3731 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3732 .ppu_enable = mv88e6185_g1_ppu_enable, 3733 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3734 .ppu_disable = mv88e6185_g1_ppu_disable, 3735 .reset = mv88e6185_g1_reset, 3736 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3737 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3738 .phylink_validate = mv88e6185_phylink_validate, 3739 }; 3740 3741 static const struct mv88e6xxx_ops mv88e6141_ops = { 3742 /* MV88E6XXX_FAMILY_6341 */ 3743 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3744 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3745 .irl_init_all = mv88e6352_g2_irl_init_all, 3746 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3747 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3748 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3749 .phy_read = mv88e6xxx_g2_smi_phy_read, 3750 .phy_write = mv88e6xxx_g2_smi_phy_write, 3751 .port_set_link = mv88e6xxx_port_set_link, 3752 .port_sync_link = mv88e6xxx_port_sync_link, 3753 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3754 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3755 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3756 .port_tag_remap = mv88e6095_port_tag_remap, 3757 .port_set_policy = mv88e6352_port_set_policy, 3758 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3759 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3760 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3761 .port_set_ether_type = mv88e6351_port_set_ether_type, 3762 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3763 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3764 .port_pause_limit = mv88e6097_port_pause_limit, 3765 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3766 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3767 .port_get_cmode = mv88e6352_port_get_cmode, 3768 .port_set_cmode = mv88e6341_port_set_cmode, 3769 .port_setup_message_port = mv88e6xxx_setup_message_port, 3770 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3771 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3772 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3773 .stats_get_strings = mv88e6320_stats_get_strings, 3774 .stats_get_stats = mv88e6390_stats_get_stats, 3775 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3776 .set_egress_port = mv88e6390_g1_set_egress_port, 3777 .watchdog_ops = &mv88e6390_watchdog_ops, 3778 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3779 .pot_clear = mv88e6xxx_g2_pot_clear, 3780 .reset = mv88e6352_g1_reset, 3781 .rmu_disable = mv88e6390_g1_rmu_disable, 3782 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3783 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3784 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3785 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3786 .serdes_power = mv88e6390_serdes_power, 3787 .serdes_get_lane = mv88e6341_serdes_get_lane, 3788 /* Check status register pause & lpa register */ 3789 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3790 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3791 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3792 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3793 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3794 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3795 .serdes_irq_status = mv88e6390_serdes_irq_status, 3796 .gpio_ops = &mv88e6352_gpio_ops, 3797 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3798 .serdes_get_strings = mv88e6390_serdes_get_strings, 3799 .serdes_get_stats = mv88e6390_serdes_get_stats, 3800 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3801 .serdes_get_regs = mv88e6390_serdes_get_regs, 3802 .phylink_validate = mv88e6341_phylink_validate, 3803 }; 3804 3805 static const struct mv88e6xxx_ops mv88e6161_ops = { 3806 /* MV88E6XXX_FAMILY_6165 */ 3807 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3808 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3809 .irl_init_all = mv88e6352_g2_irl_init_all, 3810 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3811 .phy_read = mv88e6xxx_g2_smi_phy_read, 3812 .phy_write = mv88e6xxx_g2_smi_phy_write, 3813 .port_set_link = mv88e6xxx_port_set_link, 3814 .port_sync_link = mv88e6xxx_port_sync_link, 3815 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3816 .port_tag_remap = mv88e6095_port_tag_remap, 3817 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3818 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3819 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3820 .port_set_ether_type = mv88e6351_port_set_ether_type, 3821 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3822 .port_pause_limit = mv88e6097_port_pause_limit, 3823 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3824 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3825 .port_get_cmode = mv88e6185_port_get_cmode, 3826 .port_setup_message_port = mv88e6xxx_setup_message_port, 3827 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3828 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3829 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3830 .stats_get_strings = mv88e6095_stats_get_strings, 3831 .stats_get_stats = mv88e6095_stats_get_stats, 3832 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3833 .set_egress_port = mv88e6095_g1_set_egress_port, 3834 .watchdog_ops = &mv88e6097_watchdog_ops, 3835 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3836 .pot_clear = mv88e6xxx_g2_pot_clear, 3837 .reset = mv88e6352_g1_reset, 3838 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3839 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3840 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3841 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3842 .avb_ops = &mv88e6165_avb_ops, 3843 .ptp_ops = &mv88e6165_ptp_ops, 3844 .phylink_validate = mv88e6185_phylink_validate, 3845 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3846 }; 3847 3848 static const struct mv88e6xxx_ops mv88e6165_ops = { 3849 /* MV88E6XXX_FAMILY_6165 */ 3850 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3851 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3852 .irl_init_all = mv88e6352_g2_irl_init_all, 3853 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3854 .phy_read = mv88e6165_phy_read, 3855 .phy_write = mv88e6165_phy_write, 3856 .port_set_link = mv88e6xxx_port_set_link, 3857 .port_sync_link = mv88e6xxx_port_sync_link, 3858 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3859 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3860 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3861 .port_get_cmode = mv88e6185_port_get_cmode, 3862 .port_setup_message_port = mv88e6xxx_setup_message_port, 3863 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3864 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3865 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3866 .stats_get_strings = mv88e6095_stats_get_strings, 3867 .stats_get_stats = mv88e6095_stats_get_stats, 3868 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3869 .set_egress_port = mv88e6095_g1_set_egress_port, 3870 .watchdog_ops = &mv88e6097_watchdog_ops, 3871 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3872 .pot_clear = mv88e6xxx_g2_pot_clear, 3873 .reset = mv88e6352_g1_reset, 3874 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3875 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3876 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3877 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3878 .avb_ops = &mv88e6165_avb_ops, 3879 .ptp_ops = &mv88e6165_ptp_ops, 3880 .phylink_validate = mv88e6185_phylink_validate, 3881 }; 3882 3883 static const struct mv88e6xxx_ops mv88e6171_ops = { 3884 /* MV88E6XXX_FAMILY_6351 */ 3885 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3886 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3887 .irl_init_all = mv88e6352_g2_irl_init_all, 3888 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3889 .phy_read = mv88e6xxx_g2_smi_phy_read, 3890 .phy_write = mv88e6xxx_g2_smi_phy_write, 3891 .port_set_link = mv88e6xxx_port_set_link, 3892 .port_sync_link = mv88e6xxx_port_sync_link, 3893 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3894 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3895 .port_tag_remap = mv88e6095_port_tag_remap, 3896 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3897 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3898 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3899 .port_set_ether_type = mv88e6351_port_set_ether_type, 3900 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3901 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3902 .port_pause_limit = mv88e6097_port_pause_limit, 3903 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3904 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3905 .port_get_cmode = mv88e6352_port_get_cmode, 3906 .port_setup_message_port = mv88e6xxx_setup_message_port, 3907 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3908 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3909 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3910 .stats_get_strings = mv88e6095_stats_get_strings, 3911 .stats_get_stats = mv88e6095_stats_get_stats, 3912 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3913 .set_egress_port = mv88e6095_g1_set_egress_port, 3914 .watchdog_ops = &mv88e6097_watchdog_ops, 3915 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3916 .pot_clear = mv88e6xxx_g2_pot_clear, 3917 .reset = mv88e6352_g1_reset, 3918 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3919 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3920 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3921 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3922 .phylink_validate = mv88e6185_phylink_validate, 3923 }; 3924 3925 static const struct mv88e6xxx_ops mv88e6172_ops = { 3926 /* MV88E6XXX_FAMILY_6352 */ 3927 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3928 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3929 .irl_init_all = mv88e6352_g2_irl_init_all, 3930 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3931 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3932 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3933 .phy_read = mv88e6xxx_g2_smi_phy_read, 3934 .phy_write = mv88e6xxx_g2_smi_phy_write, 3935 .port_set_link = mv88e6xxx_port_set_link, 3936 .port_sync_link = mv88e6xxx_port_sync_link, 3937 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3938 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3939 .port_tag_remap = mv88e6095_port_tag_remap, 3940 .port_set_policy = mv88e6352_port_set_policy, 3941 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3942 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3943 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3944 .port_set_ether_type = mv88e6351_port_set_ether_type, 3945 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3946 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3947 .port_pause_limit = mv88e6097_port_pause_limit, 3948 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3949 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3950 .port_get_cmode = mv88e6352_port_get_cmode, 3951 .port_setup_message_port = mv88e6xxx_setup_message_port, 3952 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3953 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3954 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3955 .stats_get_strings = mv88e6095_stats_get_strings, 3956 .stats_get_stats = mv88e6095_stats_get_stats, 3957 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3958 .set_egress_port = mv88e6095_g1_set_egress_port, 3959 .watchdog_ops = &mv88e6097_watchdog_ops, 3960 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3961 .pot_clear = mv88e6xxx_g2_pot_clear, 3962 .reset = mv88e6352_g1_reset, 3963 .rmu_disable = mv88e6352_g1_rmu_disable, 3964 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3965 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3966 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3967 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3968 .serdes_get_lane = mv88e6352_serdes_get_lane, 3969 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3970 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3971 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3972 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3973 .serdes_power = mv88e6352_serdes_power, 3974 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3975 .serdes_get_regs = mv88e6352_serdes_get_regs, 3976 .gpio_ops = &mv88e6352_gpio_ops, 3977 .phylink_validate = mv88e6352_phylink_validate, 3978 }; 3979 3980 static const struct mv88e6xxx_ops mv88e6175_ops = { 3981 /* MV88E6XXX_FAMILY_6351 */ 3982 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3983 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3984 .irl_init_all = mv88e6352_g2_irl_init_all, 3985 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3986 .phy_read = mv88e6xxx_g2_smi_phy_read, 3987 .phy_write = mv88e6xxx_g2_smi_phy_write, 3988 .port_set_link = mv88e6xxx_port_set_link, 3989 .port_sync_link = mv88e6xxx_port_sync_link, 3990 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3991 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3992 .port_tag_remap = mv88e6095_port_tag_remap, 3993 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3994 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3995 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3996 .port_set_ether_type = mv88e6351_port_set_ether_type, 3997 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3998 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3999 .port_pause_limit = mv88e6097_port_pause_limit, 4000 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4001 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4002 .port_get_cmode = mv88e6352_port_get_cmode, 4003 .port_setup_message_port = mv88e6xxx_setup_message_port, 4004 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4005 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4006 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4007 .stats_get_strings = mv88e6095_stats_get_strings, 4008 .stats_get_stats = mv88e6095_stats_get_stats, 4009 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4010 .set_egress_port = mv88e6095_g1_set_egress_port, 4011 .watchdog_ops = &mv88e6097_watchdog_ops, 4012 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4013 .pot_clear = mv88e6xxx_g2_pot_clear, 4014 .reset = mv88e6352_g1_reset, 4015 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4016 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4017 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4018 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4019 .phylink_validate = mv88e6185_phylink_validate, 4020 }; 4021 4022 static const struct mv88e6xxx_ops mv88e6176_ops = { 4023 /* MV88E6XXX_FAMILY_6352 */ 4024 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4025 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4026 .irl_init_all = mv88e6352_g2_irl_init_all, 4027 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4028 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4030 .phy_read = mv88e6xxx_g2_smi_phy_read, 4031 .phy_write = mv88e6xxx_g2_smi_phy_write, 4032 .port_set_link = mv88e6xxx_port_set_link, 4033 .port_sync_link = mv88e6xxx_port_sync_link, 4034 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4035 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4036 .port_tag_remap = mv88e6095_port_tag_remap, 4037 .port_set_policy = mv88e6352_port_set_policy, 4038 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4039 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4040 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4041 .port_set_ether_type = mv88e6351_port_set_ether_type, 4042 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4043 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4044 .port_pause_limit = mv88e6097_port_pause_limit, 4045 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4046 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4047 .port_get_cmode = mv88e6352_port_get_cmode, 4048 .port_setup_message_port = mv88e6xxx_setup_message_port, 4049 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4050 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4051 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4052 .stats_get_strings = mv88e6095_stats_get_strings, 4053 .stats_get_stats = mv88e6095_stats_get_stats, 4054 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4055 .set_egress_port = mv88e6095_g1_set_egress_port, 4056 .watchdog_ops = &mv88e6097_watchdog_ops, 4057 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4058 .pot_clear = mv88e6xxx_g2_pot_clear, 4059 .reset = mv88e6352_g1_reset, 4060 .rmu_disable = mv88e6352_g1_rmu_disable, 4061 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4062 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4063 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4064 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4065 .serdes_get_lane = mv88e6352_serdes_get_lane, 4066 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4067 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4068 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4069 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4070 .serdes_power = mv88e6352_serdes_power, 4071 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4072 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4073 .serdes_irq_status = mv88e6352_serdes_irq_status, 4074 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4075 .serdes_get_regs = mv88e6352_serdes_get_regs, 4076 .gpio_ops = &mv88e6352_gpio_ops, 4077 .phylink_validate = mv88e6352_phylink_validate, 4078 }; 4079 4080 static const struct mv88e6xxx_ops mv88e6185_ops = { 4081 /* MV88E6XXX_FAMILY_6185 */ 4082 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4083 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4084 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4085 .phy_read = mv88e6185_phy_ppu_read, 4086 .phy_write = mv88e6185_phy_ppu_write, 4087 .port_set_link = mv88e6xxx_port_set_link, 4088 .port_sync_link = mv88e6185_port_sync_link, 4089 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4090 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4091 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4092 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4093 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4094 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4095 .port_set_pause = mv88e6185_port_set_pause, 4096 .port_get_cmode = mv88e6185_port_get_cmode, 4097 .port_setup_message_port = mv88e6xxx_setup_message_port, 4098 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4099 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4100 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4101 .stats_get_strings = mv88e6095_stats_get_strings, 4102 .stats_get_stats = mv88e6095_stats_get_stats, 4103 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4104 .set_egress_port = mv88e6095_g1_set_egress_port, 4105 .watchdog_ops = &mv88e6097_watchdog_ops, 4106 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4107 .serdes_power = mv88e6185_serdes_power, 4108 .serdes_get_lane = mv88e6185_serdes_get_lane, 4109 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4110 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4111 .ppu_enable = mv88e6185_g1_ppu_enable, 4112 .ppu_disable = mv88e6185_g1_ppu_disable, 4113 .reset = mv88e6185_g1_reset, 4114 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4115 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4116 .phylink_validate = mv88e6185_phylink_validate, 4117 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4118 }; 4119 4120 static const struct mv88e6xxx_ops mv88e6190_ops = { 4121 /* MV88E6XXX_FAMILY_6390 */ 4122 .setup_errata = mv88e6390_setup_errata, 4123 .irl_init_all = mv88e6390_g2_irl_init_all, 4124 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4125 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4126 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4127 .phy_read = mv88e6xxx_g2_smi_phy_read, 4128 .phy_write = mv88e6xxx_g2_smi_phy_write, 4129 .port_set_link = mv88e6xxx_port_set_link, 4130 .port_sync_link = mv88e6xxx_port_sync_link, 4131 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4132 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4133 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4134 .port_tag_remap = mv88e6390_port_tag_remap, 4135 .port_set_policy = mv88e6352_port_set_policy, 4136 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4137 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4138 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4139 .port_set_ether_type = mv88e6351_port_set_ether_type, 4140 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4141 .port_pause_limit = mv88e6390_port_pause_limit, 4142 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4143 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4144 .port_get_cmode = mv88e6352_port_get_cmode, 4145 .port_set_cmode = mv88e6390_port_set_cmode, 4146 .port_setup_message_port = mv88e6xxx_setup_message_port, 4147 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4148 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4149 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4150 .stats_get_strings = mv88e6320_stats_get_strings, 4151 .stats_get_stats = mv88e6390_stats_get_stats, 4152 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4153 .set_egress_port = mv88e6390_g1_set_egress_port, 4154 .watchdog_ops = &mv88e6390_watchdog_ops, 4155 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4156 .pot_clear = mv88e6xxx_g2_pot_clear, 4157 .reset = mv88e6352_g1_reset, 4158 .rmu_disable = mv88e6390_g1_rmu_disable, 4159 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4160 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4161 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4162 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4163 .serdes_power = mv88e6390_serdes_power, 4164 .serdes_get_lane = mv88e6390_serdes_get_lane, 4165 /* Check status register pause & lpa register */ 4166 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4167 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4168 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4169 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4170 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4171 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4172 .serdes_irq_status = mv88e6390_serdes_irq_status, 4173 .serdes_get_strings = mv88e6390_serdes_get_strings, 4174 .serdes_get_stats = mv88e6390_serdes_get_stats, 4175 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4176 .serdes_get_regs = mv88e6390_serdes_get_regs, 4177 .gpio_ops = &mv88e6352_gpio_ops, 4178 .phylink_validate = mv88e6390_phylink_validate, 4179 }; 4180 4181 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4182 /* MV88E6XXX_FAMILY_6390 */ 4183 .setup_errata = mv88e6390_setup_errata, 4184 .irl_init_all = mv88e6390_g2_irl_init_all, 4185 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4186 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4187 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4188 .phy_read = mv88e6xxx_g2_smi_phy_read, 4189 .phy_write = mv88e6xxx_g2_smi_phy_write, 4190 .port_set_link = mv88e6xxx_port_set_link, 4191 .port_sync_link = mv88e6xxx_port_sync_link, 4192 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4193 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4194 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4195 .port_tag_remap = mv88e6390_port_tag_remap, 4196 .port_set_policy = mv88e6352_port_set_policy, 4197 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4198 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4199 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4200 .port_set_ether_type = mv88e6351_port_set_ether_type, 4201 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4202 .port_pause_limit = mv88e6390_port_pause_limit, 4203 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4204 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4205 .port_get_cmode = mv88e6352_port_get_cmode, 4206 .port_set_cmode = mv88e6390x_port_set_cmode, 4207 .port_setup_message_port = mv88e6xxx_setup_message_port, 4208 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4209 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4210 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4211 .stats_get_strings = mv88e6320_stats_get_strings, 4212 .stats_get_stats = mv88e6390_stats_get_stats, 4213 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4214 .set_egress_port = mv88e6390_g1_set_egress_port, 4215 .watchdog_ops = &mv88e6390_watchdog_ops, 4216 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4217 .pot_clear = mv88e6xxx_g2_pot_clear, 4218 .reset = mv88e6352_g1_reset, 4219 .rmu_disable = mv88e6390_g1_rmu_disable, 4220 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4221 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4222 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4223 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4224 .serdes_power = mv88e6390_serdes_power, 4225 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4226 /* Check status register pause & lpa register */ 4227 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4228 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4229 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4230 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4231 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4232 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4233 .serdes_irq_status = mv88e6390_serdes_irq_status, 4234 .serdes_get_strings = mv88e6390_serdes_get_strings, 4235 .serdes_get_stats = mv88e6390_serdes_get_stats, 4236 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4237 .serdes_get_regs = mv88e6390_serdes_get_regs, 4238 .gpio_ops = &mv88e6352_gpio_ops, 4239 .phylink_validate = mv88e6390x_phylink_validate, 4240 }; 4241 4242 static const struct mv88e6xxx_ops mv88e6191_ops = { 4243 /* MV88E6XXX_FAMILY_6390 */ 4244 .setup_errata = mv88e6390_setup_errata, 4245 .irl_init_all = mv88e6390_g2_irl_init_all, 4246 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4247 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4248 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4249 .phy_read = mv88e6xxx_g2_smi_phy_read, 4250 .phy_write = mv88e6xxx_g2_smi_phy_write, 4251 .port_set_link = mv88e6xxx_port_set_link, 4252 .port_sync_link = mv88e6xxx_port_sync_link, 4253 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4254 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4255 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4256 .port_tag_remap = mv88e6390_port_tag_remap, 4257 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4258 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4259 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4260 .port_set_ether_type = mv88e6351_port_set_ether_type, 4261 .port_pause_limit = mv88e6390_port_pause_limit, 4262 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4263 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4264 .port_get_cmode = mv88e6352_port_get_cmode, 4265 .port_set_cmode = mv88e6390_port_set_cmode, 4266 .port_setup_message_port = mv88e6xxx_setup_message_port, 4267 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4268 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4269 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4270 .stats_get_strings = mv88e6320_stats_get_strings, 4271 .stats_get_stats = mv88e6390_stats_get_stats, 4272 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4273 .set_egress_port = mv88e6390_g1_set_egress_port, 4274 .watchdog_ops = &mv88e6390_watchdog_ops, 4275 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4276 .pot_clear = mv88e6xxx_g2_pot_clear, 4277 .reset = mv88e6352_g1_reset, 4278 .rmu_disable = mv88e6390_g1_rmu_disable, 4279 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4280 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4281 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4282 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4283 .serdes_power = mv88e6390_serdes_power, 4284 .serdes_get_lane = mv88e6390_serdes_get_lane, 4285 /* Check status register pause & lpa register */ 4286 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4287 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4288 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4289 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4290 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4291 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4292 .serdes_irq_status = mv88e6390_serdes_irq_status, 4293 .serdes_get_strings = mv88e6390_serdes_get_strings, 4294 .serdes_get_stats = mv88e6390_serdes_get_stats, 4295 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4296 .serdes_get_regs = mv88e6390_serdes_get_regs, 4297 .avb_ops = &mv88e6390_avb_ops, 4298 .ptp_ops = &mv88e6352_ptp_ops, 4299 .phylink_validate = mv88e6390_phylink_validate, 4300 }; 4301 4302 static const struct mv88e6xxx_ops mv88e6240_ops = { 4303 /* MV88E6XXX_FAMILY_6352 */ 4304 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4305 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4306 .irl_init_all = mv88e6352_g2_irl_init_all, 4307 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4308 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4309 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4310 .phy_read = mv88e6xxx_g2_smi_phy_read, 4311 .phy_write = mv88e6xxx_g2_smi_phy_write, 4312 .port_set_link = mv88e6xxx_port_set_link, 4313 .port_sync_link = mv88e6xxx_port_sync_link, 4314 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4315 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4316 .port_tag_remap = mv88e6095_port_tag_remap, 4317 .port_set_policy = mv88e6352_port_set_policy, 4318 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4319 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4320 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4321 .port_set_ether_type = mv88e6351_port_set_ether_type, 4322 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4323 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4324 .port_pause_limit = mv88e6097_port_pause_limit, 4325 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4326 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4327 .port_get_cmode = mv88e6352_port_get_cmode, 4328 .port_setup_message_port = mv88e6xxx_setup_message_port, 4329 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4330 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4331 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4332 .stats_get_strings = mv88e6095_stats_get_strings, 4333 .stats_get_stats = mv88e6095_stats_get_stats, 4334 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4335 .set_egress_port = mv88e6095_g1_set_egress_port, 4336 .watchdog_ops = &mv88e6097_watchdog_ops, 4337 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4338 .pot_clear = mv88e6xxx_g2_pot_clear, 4339 .reset = mv88e6352_g1_reset, 4340 .rmu_disable = mv88e6352_g1_rmu_disable, 4341 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4342 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4343 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4344 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4345 .serdes_get_lane = mv88e6352_serdes_get_lane, 4346 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4347 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4348 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4349 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4350 .serdes_power = mv88e6352_serdes_power, 4351 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4352 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4353 .serdes_irq_status = mv88e6352_serdes_irq_status, 4354 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4355 .serdes_get_regs = mv88e6352_serdes_get_regs, 4356 .gpio_ops = &mv88e6352_gpio_ops, 4357 .avb_ops = &mv88e6352_avb_ops, 4358 .ptp_ops = &mv88e6352_ptp_ops, 4359 .phylink_validate = mv88e6352_phylink_validate, 4360 }; 4361 4362 static const struct mv88e6xxx_ops mv88e6250_ops = { 4363 /* MV88E6XXX_FAMILY_6250 */ 4364 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4365 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4366 .irl_init_all = mv88e6352_g2_irl_init_all, 4367 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4368 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4369 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4370 .phy_read = mv88e6xxx_g2_smi_phy_read, 4371 .phy_write = mv88e6xxx_g2_smi_phy_write, 4372 .port_set_link = mv88e6xxx_port_set_link, 4373 .port_sync_link = mv88e6xxx_port_sync_link, 4374 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4375 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4376 .port_tag_remap = mv88e6095_port_tag_remap, 4377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4378 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4379 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4380 .port_set_ether_type = mv88e6351_port_set_ether_type, 4381 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4382 .port_pause_limit = mv88e6097_port_pause_limit, 4383 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4384 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4385 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4386 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4387 .stats_get_strings = mv88e6250_stats_get_strings, 4388 .stats_get_stats = mv88e6250_stats_get_stats, 4389 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4390 .set_egress_port = mv88e6095_g1_set_egress_port, 4391 .watchdog_ops = &mv88e6250_watchdog_ops, 4392 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4393 .pot_clear = mv88e6xxx_g2_pot_clear, 4394 .reset = mv88e6250_g1_reset, 4395 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4396 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4397 .avb_ops = &mv88e6352_avb_ops, 4398 .ptp_ops = &mv88e6250_ptp_ops, 4399 .phylink_validate = mv88e6065_phylink_validate, 4400 }; 4401 4402 static const struct mv88e6xxx_ops mv88e6290_ops = { 4403 /* MV88E6XXX_FAMILY_6390 */ 4404 .setup_errata = mv88e6390_setup_errata, 4405 .irl_init_all = mv88e6390_g2_irl_init_all, 4406 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4407 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4408 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4409 .phy_read = mv88e6xxx_g2_smi_phy_read, 4410 .phy_write = mv88e6xxx_g2_smi_phy_write, 4411 .port_set_link = mv88e6xxx_port_set_link, 4412 .port_sync_link = mv88e6xxx_port_sync_link, 4413 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4414 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4415 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4416 .port_tag_remap = mv88e6390_port_tag_remap, 4417 .port_set_policy = mv88e6352_port_set_policy, 4418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4419 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4420 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4421 .port_set_ether_type = mv88e6351_port_set_ether_type, 4422 .port_pause_limit = mv88e6390_port_pause_limit, 4423 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4424 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4425 .port_get_cmode = mv88e6352_port_get_cmode, 4426 .port_set_cmode = mv88e6390_port_set_cmode, 4427 .port_setup_message_port = mv88e6xxx_setup_message_port, 4428 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4429 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4430 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4431 .stats_get_strings = mv88e6320_stats_get_strings, 4432 .stats_get_stats = mv88e6390_stats_get_stats, 4433 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4434 .set_egress_port = mv88e6390_g1_set_egress_port, 4435 .watchdog_ops = &mv88e6390_watchdog_ops, 4436 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4437 .pot_clear = mv88e6xxx_g2_pot_clear, 4438 .reset = mv88e6352_g1_reset, 4439 .rmu_disable = mv88e6390_g1_rmu_disable, 4440 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4441 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4442 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4443 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4444 .serdes_power = mv88e6390_serdes_power, 4445 .serdes_get_lane = mv88e6390_serdes_get_lane, 4446 /* Check status register pause & lpa register */ 4447 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4448 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4449 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4450 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4451 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4452 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4453 .serdes_irq_status = mv88e6390_serdes_irq_status, 4454 .serdes_get_strings = mv88e6390_serdes_get_strings, 4455 .serdes_get_stats = mv88e6390_serdes_get_stats, 4456 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4457 .serdes_get_regs = mv88e6390_serdes_get_regs, 4458 .gpio_ops = &mv88e6352_gpio_ops, 4459 .avb_ops = &mv88e6390_avb_ops, 4460 .ptp_ops = &mv88e6352_ptp_ops, 4461 .phylink_validate = mv88e6390_phylink_validate, 4462 }; 4463 4464 static const struct mv88e6xxx_ops mv88e6320_ops = { 4465 /* MV88E6XXX_FAMILY_6320 */ 4466 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4467 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4468 .irl_init_all = mv88e6352_g2_irl_init_all, 4469 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4470 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4471 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4472 .phy_read = mv88e6xxx_g2_smi_phy_read, 4473 .phy_write = mv88e6xxx_g2_smi_phy_write, 4474 .port_set_link = mv88e6xxx_port_set_link, 4475 .port_sync_link = mv88e6xxx_port_sync_link, 4476 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4477 .port_tag_remap = mv88e6095_port_tag_remap, 4478 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4479 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4480 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4481 .port_set_ether_type = mv88e6351_port_set_ether_type, 4482 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4483 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4484 .port_pause_limit = mv88e6097_port_pause_limit, 4485 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4486 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4487 .port_get_cmode = mv88e6352_port_get_cmode, 4488 .port_setup_message_port = mv88e6xxx_setup_message_port, 4489 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4490 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4491 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4492 .stats_get_strings = mv88e6320_stats_get_strings, 4493 .stats_get_stats = mv88e6320_stats_get_stats, 4494 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4495 .set_egress_port = mv88e6095_g1_set_egress_port, 4496 .watchdog_ops = &mv88e6390_watchdog_ops, 4497 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4498 .pot_clear = mv88e6xxx_g2_pot_clear, 4499 .reset = mv88e6352_g1_reset, 4500 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4501 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4502 .gpio_ops = &mv88e6352_gpio_ops, 4503 .avb_ops = &mv88e6352_avb_ops, 4504 .ptp_ops = &mv88e6352_ptp_ops, 4505 .phylink_validate = mv88e6185_phylink_validate, 4506 }; 4507 4508 static const struct mv88e6xxx_ops mv88e6321_ops = { 4509 /* MV88E6XXX_FAMILY_6320 */ 4510 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4511 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4512 .irl_init_all = mv88e6352_g2_irl_init_all, 4513 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4514 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4516 .phy_read = mv88e6xxx_g2_smi_phy_read, 4517 .phy_write = mv88e6xxx_g2_smi_phy_write, 4518 .port_set_link = mv88e6xxx_port_set_link, 4519 .port_sync_link = mv88e6xxx_port_sync_link, 4520 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4521 .port_tag_remap = mv88e6095_port_tag_remap, 4522 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4523 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4524 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4525 .port_set_ether_type = mv88e6351_port_set_ether_type, 4526 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4527 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4528 .port_pause_limit = mv88e6097_port_pause_limit, 4529 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4530 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4531 .port_get_cmode = mv88e6352_port_get_cmode, 4532 .port_setup_message_port = mv88e6xxx_setup_message_port, 4533 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4534 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4535 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4536 .stats_get_strings = mv88e6320_stats_get_strings, 4537 .stats_get_stats = mv88e6320_stats_get_stats, 4538 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4539 .set_egress_port = mv88e6095_g1_set_egress_port, 4540 .watchdog_ops = &mv88e6390_watchdog_ops, 4541 .reset = mv88e6352_g1_reset, 4542 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4543 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4544 .gpio_ops = &mv88e6352_gpio_ops, 4545 .avb_ops = &mv88e6352_avb_ops, 4546 .ptp_ops = &mv88e6352_ptp_ops, 4547 .phylink_validate = mv88e6185_phylink_validate, 4548 }; 4549 4550 static const struct mv88e6xxx_ops mv88e6341_ops = { 4551 /* MV88E6XXX_FAMILY_6341 */ 4552 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4553 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4554 .irl_init_all = mv88e6352_g2_irl_init_all, 4555 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4556 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4557 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4558 .phy_read = mv88e6xxx_g2_smi_phy_read, 4559 .phy_write = mv88e6xxx_g2_smi_phy_write, 4560 .port_set_link = mv88e6xxx_port_set_link, 4561 .port_sync_link = mv88e6xxx_port_sync_link, 4562 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4563 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4564 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4565 .port_tag_remap = mv88e6095_port_tag_remap, 4566 .port_set_policy = mv88e6352_port_set_policy, 4567 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4568 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4569 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4570 .port_set_ether_type = mv88e6351_port_set_ether_type, 4571 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4572 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4573 .port_pause_limit = mv88e6097_port_pause_limit, 4574 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4575 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4576 .port_get_cmode = mv88e6352_port_get_cmode, 4577 .port_set_cmode = mv88e6341_port_set_cmode, 4578 .port_setup_message_port = mv88e6xxx_setup_message_port, 4579 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4580 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4581 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4582 .stats_get_strings = mv88e6320_stats_get_strings, 4583 .stats_get_stats = mv88e6390_stats_get_stats, 4584 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4585 .set_egress_port = mv88e6390_g1_set_egress_port, 4586 .watchdog_ops = &mv88e6390_watchdog_ops, 4587 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4588 .pot_clear = mv88e6xxx_g2_pot_clear, 4589 .reset = mv88e6352_g1_reset, 4590 .rmu_disable = mv88e6390_g1_rmu_disable, 4591 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4592 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4593 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4594 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4595 .serdes_power = mv88e6390_serdes_power, 4596 .serdes_get_lane = mv88e6341_serdes_get_lane, 4597 /* Check status register pause & lpa register */ 4598 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4599 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4600 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4601 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4602 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4603 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4604 .serdes_irq_status = mv88e6390_serdes_irq_status, 4605 .gpio_ops = &mv88e6352_gpio_ops, 4606 .avb_ops = &mv88e6390_avb_ops, 4607 .ptp_ops = &mv88e6352_ptp_ops, 4608 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4609 .serdes_get_strings = mv88e6390_serdes_get_strings, 4610 .serdes_get_stats = mv88e6390_serdes_get_stats, 4611 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4612 .serdes_get_regs = mv88e6390_serdes_get_regs, 4613 .phylink_validate = mv88e6341_phylink_validate, 4614 }; 4615 4616 static const struct mv88e6xxx_ops mv88e6350_ops = { 4617 /* MV88E6XXX_FAMILY_6351 */ 4618 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4619 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4620 .irl_init_all = mv88e6352_g2_irl_init_all, 4621 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4622 .phy_read = mv88e6xxx_g2_smi_phy_read, 4623 .phy_write = mv88e6xxx_g2_smi_phy_write, 4624 .port_set_link = mv88e6xxx_port_set_link, 4625 .port_sync_link = mv88e6xxx_port_sync_link, 4626 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4627 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4628 .port_tag_remap = mv88e6095_port_tag_remap, 4629 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4630 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4631 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4632 .port_set_ether_type = mv88e6351_port_set_ether_type, 4633 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4634 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4635 .port_pause_limit = mv88e6097_port_pause_limit, 4636 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4637 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4638 .port_get_cmode = mv88e6352_port_get_cmode, 4639 .port_setup_message_port = mv88e6xxx_setup_message_port, 4640 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4641 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4642 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4643 .stats_get_strings = mv88e6095_stats_get_strings, 4644 .stats_get_stats = mv88e6095_stats_get_stats, 4645 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4646 .set_egress_port = mv88e6095_g1_set_egress_port, 4647 .watchdog_ops = &mv88e6097_watchdog_ops, 4648 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4649 .pot_clear = mv88e6xxx_g2_pot_clear, 4650 .reset = mv88e6352_g1_reset, 4651 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4652 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4653 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4654 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4655 .phylink_validate = mv88e6185_phylink_validate, 4656 }; 4657 4658 static const struct mv88e6xxx_ops mv88e6351_ops = { 4659 /* MV88E6XXX_FAMILY_6351 */ 4660 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4661 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4662 .irl_init_all = mv88e6352_g2_irl_init_all, 4663 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4664 .phy_read = mv88e6xxx_g2_smi_phy_read, 4665 .phy_write = mv88e6xxx_g2_smi_phy_write, 4666 .port_set_link = mv88e6xxx_port_set_link, 4667 .port_sync_link = mv88e6xxx_port_sync_link, 4668 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4669 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4670 .port_tag_remap = mv88e6095_port_tag_remap, 4671 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4672 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4673 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4674 .port_set_ether_type = mv88e6351_port_set_ether_type, 4675 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4676 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4677 .port_pause_limit = mv88e6097_port_pause_limit, 4678 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4679 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4680 .port_get_cmode = mv88e6352_port_get_cmode, 4681 .port_setup_message_port = mv88e6xxx_setup_message_port, 4682 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4683 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4684 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4685 .stats_get_strings = mv88e6095_stats_get_strings, 4686 .stats_get_stats = mv88e6095_stats_get_stats, 4687 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4688 .set_egress_port = mv88e6095_g1_set_egress_port, 4689 .watchdog_ops = &mv88e6097_watchdog_ops, 4690 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4691 .pot_clear = mv88e6xxx_g2_pot_clear, 4692 .reset = mv88e6352_g1_reset, 4693 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4694 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4695 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4696 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4697 .avb_ops = &mv88e6352_avb_ops, 4698 .ptp_ops = &mv88e6352_ptp_ops, 4699 .phylink_validate = mv88e6185_phylink_validate, 4700 }; 4701 4702 static const struct mv88e6xxx_ops mv88e6352_ops = { 4703 /* MV88E6XXX_FAMILY_6352 */ 4704 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4705 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4706 .irl_init_all = mv88e6352_g2_irl_init_all, 4707 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4708 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4709 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4710 .phy_read = mv88e6xxx_g2_smi_phy_read, 4711 .phy_write = mv88e6xxx_g2_smi_phy_write, 4712 .port_set_link = mv88e6xxx_port_set_link, 4713 .port_sync_link = mv88e6xxx_port_sync_link, 4714 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4715 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4716 .port_tag_remap = mv88e6095_port_tag_remap, 4717 .port_set_policy = mv88e6352_port_set_policy, 4718 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4719 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4720 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4721 .port_set_ether_type = mv88e6351_port_set_ether_type, 4722 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4723 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4724 .port_pause_limit = mv88e6097_port_pause_limit, 4725 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4726 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4727 .port_get_cmode = mv88e6352_port_get_cmode, 4728 .port_setup_message_port = mv88e6xxx_setup_message_port, 4729 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4730 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4731 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4732 .stats_get_strings = mv88e6095_stats_get_strings, 4733 .stats_get_stats = mv88e6095_stats_get_stats, 4734 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4735 .set_egress_port = mv88e6095_g1_set_egress_port, 4736 .watchdog_ops = &mv88e6097_watchdog_ops, 4737 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4738 .pot_clear = mv88e6xxx_g2_pot_clear, 4739 .reset = mv88e6352_g1_reset, 4740 .rmu_disable = mv88e6352_g1_rmu_disable, 4741 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4742 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4743 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4744 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4745 .serdes_get_lane = mv88e6352_serdes_get_lane, 4746 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4747 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4748 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4749 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4750 .serdes_power = mv88e6352_serdes_power, 4751 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4752 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4753 .serdes_irq_status = mv88e6352_serdes_irq_status, 4754 .gpio_ops = &mv88e6352_gpio_ops, 4755 .avb_ops = &mv88e6352_avb_ops, 4756 .ptp_ops = &mv88e6352_ptp_ops, 4757 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4758 .serdes_get_strings = mv88e6352_serdes_get_strings, 4759 .serdes_get_stats = mv88e6352_serdes_get_stats, 4760 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4761 .serdes_get_regs = mv88e6352_serdes_get_regs, 4762 .phylink_validate = mv88e6352_phylink_validate, 4763 }; 4764 4765 static const struct mv88e6xxx_ops mv88e6390_ops = { 4766 /* MV88E6XXX_FAMILY_6390 */ 4767 .setup_errata = mv88e6390_setup_errata, 4768 .irl_init_all = mv88e6390_g2_irl_init_all, 4769 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4770 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4771 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4772 .phy_read = mv88e6xxx_g2_smi_phy_read, 4773 .phy_write = mv88e6xxx_g2_smi_phy_write, 4774 .port_set_link = mv88e6xxx_port_set_link, 4775 .port_sync_link = mv88e6xxx_port_sync_link, 4776 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4777 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4778 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4779 .port_tag_remap = mv88e6390_port_tag_remap, 4780 .port_set_policy = mv88e6352_port_set_policy, 4781 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4782 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4783 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4784 .port_set_ether_type = mv88e6351_port_set_ether_type, 4785 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4786 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4787 .port_pause_limit = mv88e6390_port_pause_limit, 4788 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4789 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4790 .port_get_cmode = mv88e6352_port_get_cmode, 4791 .port_set_cmode = mv88e6390_port_set_cmode, 4792 .port_setup_message_port = mv88e6xxx_setup_message_port, 4793 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4794 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4795 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4796 .stats_get_strings = mv88e6320_stats_get_strings, 4797 .stats_get_stats = mv88e6390_stats_get_stats, 4798 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4799 .set_egress_port = mv88e6390_g1_set_egress_port, 4800 .watchdog_ops = &mv88e6390_watchdog_ops, 4801 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4802 .pot_clear = mv88e6xxx_g2_pot_clear, 4803 .reset = mv88e6352_g1_reset, 4804 .rmu_disable = mv88e6390_g1_rmu_disable, 4805 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4806 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4807 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4808 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4809 .serdes_power = mv88e6390_serdes_power, 4810 .serdes_get_lane = mv88e6390_serdes_get_lane, 4811 /* Check status register pause & lpa register */ 4812 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4813 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4814 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4815 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4816 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4817 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4818 .serdes_irq_status = mv88e6390_serdes_irq_status, 4819 .gpio_ops = &mv88e6352_gpio_ops, 4820 .avb_ops = &mv88e6390_avb_ops, 4821 .ptp_ops = &mv88e6352_ptp_ops, 4822 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4823 .serdes_get_strings = mv88e6390_serdes_get_strings, 4824 .serdes_get_stats = mv88e6390_serdes_get_stats, 4825 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4826 .serdes_get_regs = mv88e6390_serdes_get_regs, 4827 .phylink_validate = mv88e6390_phylink_validate, 4828 }; 4829 4830 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4831 /* MV88E6XXX_FAMILY_6390 */ 4832 .setup_errata = mv88e6390_setup_errata, 4833 .irl_init_all = mv88e6390_g2_irl_init_all, 4834 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4835 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4836 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4837 .phy_read = mv88e6xxx_g2_smi_phy_read, 4838 .phy_write = mv88e6xxx_g2_smi_phy_write, 4839 .port_set_link = mv88e6xxx_port_set_link, 4840 .port_sync_link = mv88e6xxx_port_sync_link, 4841 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4842 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4843 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4844 .port_tag_remap = mv88e6390_port_tag_remap, 4845 .port_set_policy = mv88e6352_port_set_policy, 4846 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4847 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4848 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4849 .port_set_ether_type = mv88e6351_port_set_ether_type, 4850 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4851 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4852 .port_pause_limit = mv88e6390_port_pause_limit, 4853 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4854 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4855 .port_get_cmode = mv88e6352_port_get_cmode, 4856 .port_set_cmode = mv88e6390x_port_set_cmode, 4857 .port_setup_message_port = mv88e6xxx_setup_message_port, 4858 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4859 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4860 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4861 .stats_get_strings = mv88e6320_stats_get_strings, 4862 .stats_get_stats = mv88e6390_stats_get_stats, 4863 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4864 .set_egress_port = mv88e6390_g1_set_egress_port, 4865 .watchdog_ops = &mv88e6390_watchdog_ops, 4866 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4867 .pot_clear = mv88e6xxx_g2_pot_clear, 4868 .reset = mv88e6352_g1_reset, 4869 .rmu_disable = mv88e6390_g1_rmu_disable, 4870 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4871 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4872 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4873 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4874 .serdes_power = mv88e6390_serdes_power, 4875 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4876 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4877 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4878 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4879 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4880 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4881 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4882 .serdes_irq_status = mv88e6390_serdes_irq_status, 4883 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4884 .serdes_get_strings = mv88e6390_serdes_get_strings, 4885 .serdes_get_stats = mv88e6390_serdes_get_stats, 4886 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4887 .serdes_get_regs = mv88e6390_serdes_get_regs, 4888 .gpio_ops = &mv88e6352_gpio_ops, 4889 .avb_ops = &mv88e6390_avb_ops, 4890 .ptp_ops = &mv88e6352_ptp_ops, 4891 .phylink_validate = mv88e6390x_phylink_validate, 4892 }; 4893 4894 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4895 /* MV88E6XXX_FAMILY_6393 */ 4896 .setup_errata = mv88e6393x_serdes_setup_errata, 4897 .irl_init_all = mv88e6390_g2_irl_init_all, 4898 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4899 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4900 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4901 .phy_read = mv88e6xxx_g2_smi_phy_read, 4902 .phy_write = mv88e6xxx_g2_smi_phy_write, 4903 .port_set_link = mv88e6xxx_port_set_link, 4904 .port_sync_link = mv88e6xxx_port_sync_link, 4905 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4906 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4907 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4908 .port_tag_remap = mv88e6390_port_tag_remap, 4909 .port_set_policy = mv88e6393x_port_set_policy, 4910 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4911 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4912 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4913 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4914 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4915 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4916 .port_pause_limit = mv88e6390_port_pause_limit, 4917 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4918 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4919 .port_get_cmode = mv88e6352_port_get_cmode, 4920 .port_set_cmode = mv88e6393x_port_set_cmode, 4921 .port_setup_message_port = mv88e6xxx_setup_message_port, 4922 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4923 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4924 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4925 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4926 .stats_get_strings = mv88e6320_stats_get_strings, 4927 .stats_get_stats = mv88e6390_stats_get_stats, 4928 /* .set_cpu_port is missing because this family does not support a global 4929 * CPU port, only per port CPU port which is set via 4930 * .port_set_upstream_port method. 4931 */ 4932 .set_egress_port = mv88e6393x_set_egress_port, 4933 .watchdog_ops = &mv88e6390_watchdog_ops, 4934 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4935 .pot_clear = mv88e6xxx_g2_pot_clear, 4936 .reset = mv88e6352_g1_reset, 4937 .rmu_disable = mv88e6390_g1_rmu_disable, 4938 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4939 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4940 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4941 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4942 .serdes_power = mv88e6393x_serdes_power, 4943 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4944 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4945 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4946 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4947 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4948 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4949 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4950 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4951 /* TODO: serdes stats */ 4952 .gpio_ops = &mv88e6352_gpio_ops, 4953 .avb_ops = &mv88e6390_avb_ops, 4954 .ptp_ops = &mv88e6352_ptp_ops, 4955 .phylink_validate = mv88e6393x_phylink_validate, 4956 }; 4957 4958 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4959 [MV88E6085] = { 4960 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4961 .family = MV88E6XXX_FAMILY_6097, 4962 .name = "Marvell 88E6085", 4963 .num_databases = 4096, 4964 .num_macs = 8192, 4965 .num_ports = 10, 4966 .num_internal_phys = 5, 4967 .max_vid = 4095, 4968 .port_base_addr = 0x10, 4969 .phy_base_addr = 0x0, 4970 .global1_addr = 0x1b, 4971 .global2_addr = 0x1c, 4972 .age_time_coeff = 15000, 4973 .g1_irqs = 8, 4974 .g2_irqs = 10, 4975 .atu_move_port_mask = 0xf, 4976 .pvt = true, 4977 .multi_chip = true, 4978 .ops = &mv88e6085_ops, 4979 }, 4980 4981 [MV88E6095] = { 4982 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4983 .family = MV88E6XXX_FAMILY_6095, 4984 .name = "Marvell 88E6095/88E6095F", 4985 .num_databases = 256, 4986 .num_macs = 8192, 4987 .num_ports = 11, 4988 .num_internal_phys = 0, 4989 .max_vid = 4095, 4990 .port_base_addr = 0x10, 4991 .phy_base_addr = 0x0, 4992 .global1_addr = 0x1b, 4993 .global2_addr = 0x1c, 4994 .age_time_coeff = 15000, 4995 .g1_irqs = 8, 4996 .atu_move_port_mask = 0xf, 4997 .multi_chip = true, 4998 .ops = &mv88e6095_ops, 4999 }, 5000 5001 [MV88E6097] = { 5002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5003 .family = MV88E6XXX_FAMILY_6097, 5004 .name = "Marvell 88E6097/88E6097F", 5005 .num_databases = 4096, 5006 .num_macs = 8192, 5007 .num_ports = 11, 5008 .num_internal_phys = 8, 5009 .max_vid = 4095, 5010 .port_base_addr = 0x10, 5011 .phy_base_addr = 0x0, 5012 .global1_addr = 0x1b, 5013 .global2_addr = 0x1c, 5014 .age_time_coeff = 15000, 5015 .g1_irqs = 8, 5016 .g2_irqs = 10, 5017 .atu_move_port_mask = 0xf, 5018 .pvt = true, 5019 .multi_chip = true, 5020 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5021 .ops = &mv88e6097_ops, 5022 }, 5023 5024 [MV88E6123] = { 5025 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5026 .family = MV88E6XXX_FAMILY_6165, 5027 .name = "Marvell 88E6123", 5028 .num_databases = 4096, 5029 .num_macs = 1024, 5030 .num_ports = 3, 5031 .num_internal_phys = 5, 5032 .max_vid = 4095, 5033 .port_base_addr = 0x10, 5034 .phy_base_addr = 0x0, 5035 .global1_addr = 0x1b, 5036 .global2_addr = 0x1c, 5037 .age_time_coeff = 15000, 5038 .g1_irqs = 9, 5039 .g2_irqs = 10, 5040 .atu_move_port_mask = 0xf, 5041 .pvt = true, 5042 .multi_chip = true, 5043 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5044 .ops = &mv88e6123_ops, 5045 }, 5046 5047 [MV88E6131] = { 5048 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5049 .family = MV88E6XXX_FAMILY_6185, 5050 .name = "Marvell 88E6131", 5051 .num_databases = 256, 5052 .num_macs = 8192, 5053 .num_ports = 8, 5054 .num_internal_phys = 0, 5055 .max_vid = 4095, 5056 .port_base_addr = 0x10, 5057 .phy_base_addr = 0x0, 5058 .global1_addr = 0x1b, 5059 .global2_addr = 0x1c, 5060 .age_time_coeff = 15000, 5061 .g1_irqs = 9, 5062 .atu_move_port_mask = 0xf, 5063 .multi_chip = true, 5064 .ops = &mv88e6131_ops, 5065 }, 5066 5067 [MV88E6141] = { 5068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5069 .family = MV88E6XXX_FAMILY_6341, 5070 .name = "Marvell 88E6141", 5071 .num_databases = 4096, 5072 .num_macs = 2048, 5073 .num_ports = 6, 5074 .num_internal_phys = 5, 5075 .num_gpio = 11, 5076 .max_vid = 4095, 5077 .port_base_addr = 0x10, 5078 .phy_base_addr = 0x10, 5079 .global1_addr = 0x1b, 5080 .global2_addr = 0x1c, 5081 .age_time_coeff = 3750, 5082 .atu_move_port_mask = 0x1f, 5083 .g1_irqs = 9, 5084 .g2_irqs = 10, 5085 .pvt = true, 5086 .multi_chip = true, 5087 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5088 .ops = &mv88e6141_ops, 5089 }, 5090 5091 [MV88E6161] = { 5092 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5093 .family = MV88E6XXX_FAMILY_6165, 5094 .name = "Marvell 88E6161", 5095 .num_databases = 4096, 5096 .num_macs = 1024, 5097 .num_ports = 6, 5098 .num_internal_phys = 5, 5099 .max_vid = 4095, 5100 .port_base_addr = 0x10, 5101 .phy_base_addr = 0x0, 5102 .global1_addr = 0x1b, 5103 .global2_addr = 0x1c, 5104 .age_time_coeff = 15000, 5105 .g1_irqs = 9, 5106 .g2_irqs = 10, 5107 .atu_move_port_mask = 0xf, 5108 .pvt = true, 5109 .multi_chip = true, 5110 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5111 .ptp_support = true, 5112 .ops = &mv88e6161_ops, 5113 }, 5114 5115 [MV88E6165] = { 5116 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5117 .family = MV88E6XXX_FAMILY_6165, 5118 .name = "Marvell 88E6165", 5119 .num_databases = 4096, 5120 .num_macs = 8192, 5121 .num_ports = 6, 5122 .num_internal_phys = 0, 5123 .max_vid = 4095, 5124 .port_base_addr = 0x10, 5125 .phy_base_addr = 0x0, 5126 .global1_addr = 0x1b, 5127 .global2_addr = 0x1c, 5128 .age_time_coeff = 15000, 5129 .g1_irqs = 9, 5130 .g2_irqs = 10, 5131 .atu_move_port_mask = 0xf, 5132 .pvt = true, 5133 .multi_chip = true, 5134 .ptp_support = true, 5135 .ops = &mv88e6165_ops, 5136 }, 5137 5138 [MV88E6171] = { 5139 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5140 .family = MV88E6XXX_FAMILY_6351, 5141 .name = "Marvell 88E6171", 5142 .num_databases = 4096, 5143 .num_macs = 8192, 5144 .num_ports = 7, 5145 .num_internal_phys = 5, 5146 .max_vid = 4095, 5147 .port_base_addr = 0x10, 5148 .phy_base_addr = 0x0, 5149 .global1_addr = 0x1b, 5150 .global2_addr = 0x1c, 5151 .age_time_coeff = 15000, 5152 .g1_irqs = 9, 5153 .g2_irqs = 10, 5154 .atu_move_port_mask = 0xf, 5155 .pvt = true, 5156 .multi_chip = true, 5157 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5158 .ops = &mv88e6171_ops, 5159 }, 5160 5161 [MV88E6172] = { 5162 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5163 .family = MV88E6XXX_FAMILY_6352, 5164 .name = "Marvell 88E6172", 5165 .num_databases = 4096, 5166 .num_macs = 8192, 5167 .num_ports = 7, 5168 .num_internal_phys = 5, 5169 .num_gpio = 15, 5170 .max_vid = 4095, 5171 .port_base_addr = 0x10, 5172 .phy_base_addr = 0x0, 5173 .global1_addr = 0x1b, 5174 .global2_addr = 0x1c, 5175 .age_time_coeff = 15000, 5176 .g1_irqs = 9, 5177 .g2_irqs = 10, 5178 .atu_move_port_mask = 0xf, 5179 .pvt = true, 5180 .multi_chip = true, 5181 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5182 .ops = &mv88e6172_ops, 5183 }, 5184 5185 [MV88E6175] = { 5186 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5187 .family = MV88E6XXX_FAMILY_6351, 5188 .name = "Marvell 88E6175", 5189 .num_databases = 4096, 5190 .num_macs = 8192, 5191 .num_ports = 7, 5192 .num_internal_phys = 5, 5193 .max_vid = 4095, 5194 .port_base_addr = 0x10, 5195 .phy_base_addr = 0x0, 5196 .global1_addr = 0x1b, 5197 .global2_addr = 0x1c, 5198 .age_time_coeff = 15000, 5199 .g1_irqs = 9, 5200 .g2_irqs = 10, 5201 .atu_move_port_mask = 0xf, 5202 .pvt = true, 5203 .multi_chip = true, 5204 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5205 .ops = &mv88e6175_ops, 5206 }, 5207 5208 [MV88E6176] = { 5209 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5210 .family = MV88E6XXX_FAMILY_6352, 5211 .name = "Marvell 88E6176", 5212 .num_databases = 4096, 5213 .num_macs = 8192, 5214 .num_ports = 7, 5215 .num_internal_phys = 5, 5216 .num_gpio = 15, 5217 .max_vid = 4095, 5218 .port_base_addr = 0x10, 5219 .phy_base_addr = 0x0, 5220 .global1_addr = 0x1b, 5221 .global2_addr = 0x1c, 5222 .age_time_coeff = 15000, 5223 .g1_irqs = 9, 5224 .g2_irqs = 10, 5225 .atu_move_port_mask = 0xf, 5226 .pvt = true, 5227 .multi_chip = true, 5228 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5229 .ops = &mv88e6176_ops, 5230 }, 5231 5232 [MV88E6185] = { 5233 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5234 .family = MV88E6XXX_FAMILY_6185, 5235 .name = "Marvell 88E6185", 5236 .num_databases = 256, 5237 .num_macs = 8192, 5238 .num_ports = 10, 5239 .num_internal_phys = 0, 5240 .max_vid = 4095, 5241 .port_base_addr = 0x10, 5242 .phy_base_addr = 0x0, 5243 .global1_addr = 0x1b, 5244 .global2_addr = 0x1c, 5245 .age_time_coeff = 15000, 5246 .g1_irqs = 8, 5247 .atu_move_port_mask = 0xf, 5248 .multi_chip = true, 5249 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5250 .ops = &mv88e6185_ops, 5251 }, 5252 5253 [MV88E6190] = { 5254 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5255 .family = MV88E6XXX_FAMILY_6390, 5256 .name = "Marvell 88E6190", 5257 .num_databases = 4096, 5258 .num_macs = 16384, 5259 .num_ports = 11, /* 10 + Z80 */ 5260 .num_internal_phys = 9, 5261 .num_gpio = 16, 5262 .max_vid = 8191, 5263 .port_base_addr = 0x0, 5264 .phy_base_addr = 0x0, 5265 .global1_addr = 0x1b, 5266 .global2_addr = 0x1c, 5267 .age_time_coeff = 3750, 5268 .g1_irqs = 9, 5269 .g2_irqs = 14, 5270 .pvt = true, 5271 .multi_chip = true, 5272 .atu_move_port_mask = 0x1f, 5273 .ops = &mv88e6190_ops, 5274 }, 5275 5276 [MV88E6190X] = { 5277 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5278 .family = MV88E6XXX_FAMILY_6390, 5279 .name = "Marvell 88E6190X", 5280 .num_databases = 4096, 5281 .num_macs = 16384, 5282 .num_ports = 11, /* 10 + Z80 */ 5283 .num_internal_phys = 9, 5284 .num_gpio = 16, 5285 .max_vid = 8191, 5286 .port_base_addr = 0x0, 5287 .phy_base_addr = 0x0, 5288 .global1_addr = 0x1b, 5289 .global2_addr = 0x1c, 5290 .age_time_coeff = 3750, 5291 .g1_irqs = 9, 5292 .g2_irqs = 14, 5293 .atu_move_port_mask = 0x1f, 5294 .pvt = true, 5295 .multi_chip = true, 5296 .ops = &mv88e6190x_ops, 5297 }, 5298 5299 [MV88E6191] = { 5300 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5301 .family = MV88E6XXX_FAMILY_6390, 5302 .name = "Marvell 88E6191", 5303 .num_databases = 4096, 5304 .num_macs = 16384, 5305 .num_ports = 11, /* 10 + Z80 */ 5306 .num_internal_phys = 9, 5307 .max_vid = 8191, 5308 .port_base_addr = 0x0, 5309 .phy_base_addr = 0x0, 5310 .global1_addr = 0x1b, 5311 .global2_addr = 0x1c, 5312 .age_time_coeff = 3750, 5313 .g1_irqs = 9, 5314 .g2_irqs = 14, 5315 .atu_move_port_mask = 0x1f, 5316 .pvt = true, 5317 .multi_chip = true, 5318 .ptp_support = true, 5319 .ops = &mv88e6191_ops, 5320 }, 5321 5322 [MV88E6191X] = { 5323 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5324 .family = MV88E6XXX_FAMILY_6393, 5325 .name = "Marvell 88E6191X", 5326 .num_databases = 4096, 5327 .num_ports = 11, /* 10 + Z80 */ 5328 .num_internal_phys = 9, 5329 .max_vid = 8191, 5330 .port_base_addr = 0x0, 5331 .phy_base_addr = 0x0, 5332 .global1_addr = 0x1b, 5333 .global2_addr = 0x1c, 5334 .age_time_coeff = 3750, 5335 .g1_irqs = 10, 5336 .g2_irqs = 14, 5337 .atu_move_port_mask = 0x1f, 5338 .pvt = true, 5339 .multi_chip = true, 5340 .ptp_support = true, 5341 .ops = &mv88e6393x_ops, 5342 }, 5343 5344 [MV88E6193X] = { 5345 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5346 .family = MV88E6XXX_FAMILY_6393, 5347 .name = "Marvell 88E6193X", 5348 .num_databases = 4096, 5349 .num_ports = 11, /* 10 + Z80 */ 5350 .num_internal_phys = 9, 5351 .max_vid = 8191, 5352 .port_base_addr = 0x0, 5353 .phy_base_addr = 0x0, 5354 .global1_addr = 0x1b, 5355 .global2_addr = 0x1c, 5356 .age_time_coeff = 3750, 5357 .g1_irqs = 10, 5358 .g2_irqs = 14, 5359 .atu_move_port_mask = 0x1f, 5360 .pvt = true, 5361 .multi_chip = true, 5362 .ptp_support = true, 5363 .ops = &mv88e6393x_ops, 5364 }, 5365 5366 [MV88E6220] = { 5367 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5368 .family = MV88E6XXX_FAMILY_6250, 5369 .name = "Marvell 88E6220", 5370 .num_databases = 64, 5371 5372 /* Ports 2-4 are not routed to pins 5373 * => usable ports 0, 1, 5, 6 5374 */ 5375 .num_ports = 7, 5376 .num_internal_phys = 2, 5377 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5378 .max_vid = 4095, 5379 .port_base_addr = 0x08, 5380 .phy_base_addr = 0x00, 5381 .global1_addr = 0x0f, 5382 .global2_addr = 0x07, 5383 .age_time_coeff = 15000, 5384 .g1_irqs = 9, 5385 .g2_irqs = 10, 5386 .atu_move_port_mask = 0xf, 5387 .dual_chip = true, 5388 .ptp_support = true, 5389 .ops = &mv88e6250_ops, 5390 }, 5391 5392 [MV88E6240] = { 5393 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5394 .family = MV88E6XXX_FAMILY_6352, 5395 .name = "Marvell 88E6240", 5396 .num_databases = 4096, 5397 .num_macs = 8192, 5398 .num_ports = 7, 5399 .num_internal_phys = 5, 5400 .num_gpio = 15, 5401 .max_vid = 4095, 5402 .port_base_addr = 0x10, 5403 .phy_base_addr = 0x0, 5404 .global1_addr = 0x1b, 5405 .global2_addr = 0x1c, 5406 .age_time_coeff = 15000, 5407 .g1_irqs = 9, 5408 .g2_irqs = 10, 5409 .atu_move_port_mask = 0xf, 5410 .pvt = true, 5411 .multi_chip = true, 5412 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5413 .ptp_support = true, 5414 .ops = &mv88e6240_ops, 5415 }, 5416 5417 [MV88E6250] = { 5418 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5419 .family = MV88E6XXX_FAMILY_6250, 5420 .name = "Marvell 88E6250", 5421 .num_databases = 64, 5422 .num_ports = 7, 5423 .num_internal_phys = 5, 5424 .max_vid = 4095, 5425 .port_base_addr = 0x08, 5426 .phy_base_addr = 0x00, 5427 .global1_addr = 0x0f, 5428 .global2_addr = 0x07, 5429 .age_time_coeff = 15000, 5430 .g1_irqs = 9, 5431 .g2_irqs = 10, 5432 .atu_move_port_mask = 0xf, 5433 .dual_chip = true, 5434 .ptp_support = true, 5435 .ops = &mv88e6250_ops, 5436 }, 5437 5438 [MV88E6290] = { 5439 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5440 .family = MV88E6XXX_FAMILY_6390, 5441 .name = "Marvell 88E6290", 5442 .num_databases = 4096, 5443 .num_ports = 11, /* 10 + Z80 */ 5444 .num_internal_phys = 9, 5445 .num_gpio = 16, 5446 .max_vid = 8191, 5447 .port_base_addr = 0x0, 5448 .phy_base_addr = 0x0, 5449 .global1_addr = 0x1b, 5450 .global2_addr = 0x1c, 5451 .age_time_coeff = 3750, 5452 .g1_irqs = 9, 5453 .g2_irqs = 14, 5454 .atu_move_port_mask = 0x1f, 5455 .pvt = true, 5456 .multi_chip = true, 5457 .ptp_support = true, 5458 .ops = &mv88e6290_ops, 5459 }, 5460 5461 [MV88E6320] = { 5462 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5463 .family = MV88E6XXX_FAMILY_6320, 5464 .name = "Marvell 88E6320", 5465 .num_databases = 4096, 5466 .num_macs = 8192, 5467 .num_ports = 7, 5468 .num_internal_phys = 5, 5469 .num_gpio = 15, 5470 .max_vid = 4095, 5471 .port_base_addr = 0x10, 5472 .phy_base_addr = 0x0, 5473 .global1_addr = 0x1b, 5474 .global2_addr = 0x1c, 5475 .age_time_coeff = 15000, 5476 .g1_irqs = 8, 5477 .g2_irqs = 10, 5478 .atu_move_port_mask = 0xf, 5479 .pvt = true, 5480 .multi_chip = true, 5481 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5482 .ptp_support = true, 5483 .ops = &mv88e6320_ops, 5484 }, 5485 5486 [MV88E6321] = { 5487 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5488 .family = MV88E6XXX_FAMILY_6320, 5489 .name = "Marvell 88E6321", 5490 .num_databases = 4096, 5491 .num_macs = 8192, 5492 .num_ports = 7, 5493 .num_internal_phys = 5, 5494 .num_gpio = 15, 5495 .max_vid = 4095, 5496 .port_base_addr = 0x10, 5497 .phy_base_addr = 0x0, 5498 .global1_addr = 0x1b, 5499 .global2_addr = 0x1c, 5500 .age_time_coeff = 15000, 5501 .g1_irqs = 8, 5502 .g2_irqs = 10, 5503 .atu_move_port_mask = 0xf, 5504 .multi_chip = true, 5505 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5506 .ptp_support = true, 5507 .ops = &mv88e6321_ops, 5508 }, 5509 5510 [MV88E6341] = { 5511 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5512 .family = MV88E6XXX_FAMILY_6341, 5513 .name = "Marvell 88E6341", 5514 .num_databases = 4096, 5515 .num_macs = 2048, 5516 .num_internal_phys = 5, 5517 .num_ports = 6, 5518 .num_gpio = 11, 5519 .max_vid = 4095, 5520 .port_base_addr = 0x10, 5521 .phy_base_addr = 0x10, 5522 .global1_addr = 0x1b, 5523 .global2_addr = 0x1c, 5524 .age_time_coeff = 3750, 5525 .atu_move_port_mask = 0x1f, 5526 .g1_irqs = 9, 5527 .g2_irqs = 10, 5528 .pvt = true, 5529 .multi_chip = true, 5530 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5531 .ptp_support = true, 5532 .ops = &mv88e6341_ops, 5533 }, 5534 5535 [MV88E6350] = { 5536 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5537 .family = MV88E6XXX_FAMILY_6351, 5538 .name = "Marvell 88E6350", 5539 .num_databases = 4096, 5540 .num_macs = 8192, 5541 .num_ports = 7, 5542 .num_internal_phys = 5, 5543 .max_vid = 4095, 5544 .port_base_addr = 0x10, 5545 .phy_base_addr = 0x0, 5546 .global1_addr = 0x1b, 5547 .global2_addr = 0x1c, 5548 .age_time_coeff = 15000, 5549 .g1_irqs = 9, 5550 .g2_irqs = 10, 5551 .atu_move_port_mask = 0xf, 5552 .pvt = true, 5553 .multi_chip = true, 5554 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5555 .ops = &mv88e6350_ops, 5556 }, 5557 5558 [MV88E6351] = { 5559 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5560 .family = MV88E6XXX_FAMILY_6351, 5561 .name = "Marvell 88E6351", 5562 .num_databases = 4096, 5563 .num_macs = 8192, 5564 .num_ports = 7, 5565 .num_internal_phys = 5, 5566 .max_vid = 4095, 5567 .port_base_addr = 0x10, 5568 .phy_base_addr = 0x0, 5569 .global1_addr = 0x1b, 5570 .global2_addr = 0x1c, 5571 .age_time_coeff = 15000, 5572 .g1_irqs = 9, 5573 .g2_irqs = 10, 5574 .atu_move_port_mask = 0xf, 5575 .pvt = true, 5576 .multi_chip = true, 5577 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5578 .ops = &mv88e6351_ops, 5579 }, 5580 5581 [MV88E6352] = { 5582 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5583 .family = MV88E6XXX_FAMILY_6352, 5584 .name = "Marvell 88E6352", 5585 .num_databases = 4096, 5586 .num_macs = 8192, 5587 .num_ports = 7, 5588 .num_internal_phys = 5, 5589 .num_gpio = 15, 5590 .max_vid = 4095, 5591 .port_base_addr = 0x10, 5592 .phy_base_addr = 0x0, 5593 .global1_addr = 0x1b, 5594 .global2_addr = 0x1c, 5595 .age_time_coeff = 15000, 5596 .g1_irqs = 9, 5597 .g2_irqs = 10, 5598 .atu_move_port_mask = 0xf, 5599 .pvt = true, 5600 .multi_chip = true, 5601 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5602 .ptp_support = true, 5603 .ops = &mv88e6352_ops, 5604 }, 5605 [MV88E6390] = { 5606 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5607 .family = MV88E6XXX_FAMILY_6390, 5608 .name = "Marvell 88E6390", 5609 .num_databases = 4096, 5610 .num_macs = 16384, 5611 .num_ports = 11, /* 10 + Z80 */ 5612 .num_internal_phys = 9, 5613 .num_gpio = 16, 5614 .max_vid = 8191, 5615 .port_base_addr = 0x0, 5616 .phy_base_addr = 0x0, 5617 .global1_addr = 0x1b, 5618 .global2_addr = 0x1c, 5619 .age_time_coeff = 3750, 5620 .g1_irqs = 9, 5621 .g2_irqs = 14, 5622 .atu_move_port_mask = 0x1f, 5623 .pvt = true, 5624 .multi_chip = true, 5625 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5626 .ptp_support = true, 5627 .ops = &mv88e6390_ops, 5628 }, 5629 [MV88E6390X] = { 5630 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5631 .family = MV88E6XXX_FAMILY_6390, 5632 .name = "Marvell 88E6390X", 5633 .num_databases = 4096, 5634 .num_macs = 16384, 5635 .num_ports = 11, /* 10 + Z80 */ 5636 .num_internal_phys = 9, 5637 .num_gpio = 16, 5638 .max_vid = 8191, 5639 .port_base_addr = 0x0, 5640 .phy_base_addr = 0x0, 5641 .global1_addr = 0x1b, 5642 .global2_addr = 0x1c, 5643 .age_time_coeff = 3750, 5644 .g1_irqs = 9, 5645 .g2_irqs = 14, 5646 .atu_move_port_mask = 0x1f, 5647 .pvt = true, 5648 .multi_chip = true, 5649 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5650 .ptp_support = true, 5651 .ops = &mv88e6390x_ops, 5652 }, 5653 5654 [MV88E6393X] = { 5655 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5656 .family = MV88E6XXX_FAMILY_6393, 5657 .name = "Marvell 88E6393X", 5658 .num_databases = 4096, 5659 .num_ports = 11, /* 10 + Z80 */ 5660 .num_internal_phys = 9, 5661 .max_vid = 8191, 5662 .port_base_addr = 0x0, 5663 .phy_base_addr = 0x0, 5664 .global1_addr = 0x1b, 5665 .global2_addr = 0x1c, 5666 .age_time_coeff = 3750, 5667 .g1_irqs = 10, 5668 .g2_irqs = 14, 5669 .atu_move_port_mask = 0x1f, 5670 .pvt = true, 5671 .multi_chip = true, 5672 .ptp_support = true, 5673 .ops = &mv88e6393x_ops, 5674 }, 5675 }; 5676 5677 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5678 { 5679 int i; 5680 5681 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5682 if (mv88e6xxx_table[i].prod_num == prod_num) 5683 return &mv88e6xxx_table[i]; 5684 5685 return NULL; 5686 } 5687 5688 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5689 { 5690 const struct mv88e6xxx_info *info; 5691 unsigned int prod_num, rev; 5692 u16 id; 5693 int err; 5694 5695 mv88e6xxx_reg_lock(chip); 5696 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5697 mv88e6xxx_reg_unlock(chip); 5698 if (err) 5699 return err; 5700 5701 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5702 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5703 5704 info = mv88e6xxx_lookup_info(prod_num); 5705 if (!info) 5706 return -ENODEV; 5707 5708 /* Update the compatible info with the probed one */ 5709 chip->info = info; 5710 5711 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5712 chip->info->prod_num, chip->info->name, rev); 5713 5714 return 0; 5715 } 5716 5717 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5718 { 5719 struct mv88e6xxx_chip *chip; 5720 5721 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5722 if (!chip) 5723 return NULL; 5724 5725 chip->dev = dev; 5726 5727 mutex_init(&chip->reg_lock); 5728 INIT_LIST_HEAD(&chip->mdios); 5729 idr_init(&chip->policies); 5730 5731 return chip; 5732 } 5733 5734 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5735 int port, 5736 enum dsa_tag_protocol m) 5737 { 5738 struct mv88e6xxx_chip *chip = ds->priv; 5739 5740 return chip->tag_protocol; 5741 } 5742 5743 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5744 enum dsa_tag_protocol proto) 5745 { 5746 struct mv88e6xxx_chip *chip = ds->priv; 5747 enum dsa_tag_protocol old_protocol; 5748 int err; 5749 5750 switch (proto) { 5751 case DSA_TAG_PROTO_EDSA: 5752 switch (chip->info->edsa_support) { 5753 case MV88E6XXX_EDSA_UNSUPPORTED: 5754 return -EPROTONOSUPPORT; 5755 case MV88E6XXX_EDSA_UNDOCUMENTED: 5756 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5757 fallthrough; 5758 case MV88E6XXX_EDSA_SUPPORTED: 5759 break; 5760 } 5761 break; 5762 case DSA_TAG_PROTO_DSA: 5763 break; 5764 default: 5765 return -EPROTONOSUPPORT; 5766 } 5767 5768 old_protocol = chip->tag_protocol; 5769 chip->tag_protocol = proto; 5770 5771 mv88e6xxx_reg_lock(chip); 5772 err = mv88e6xxx_setup_port_mode(chip, port); 5773 mv88e6xxx_reg_unlock(chip); 5774 5775 if (err) 5776 chip->tag_protocol = old_protocol; 5777 5778 return err; 5779 } 5780 5781 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5782 const struct switchdev_obj_port_mdb *mdb) 5783 { 5784 struct mv88e6xxx_chip *chip = ds->priv; 5785 int err; 5786 5787 mv88e6xxx_reg_lock(chip); 5788 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5789 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5790 mv88e6xxx_reg_unlock(chip); 5791 5792 return err; 5793 } 5794 5795 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5796 const struct switchdev_obj_port_mdb *mdb) 5797 { 5798 struct mv88e6xxx_chip *chip = ds->priv; 5799 int err; 5800 5801 mv88e6xxx_reg_lock(chip); 5802 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5803 mv88e6xxx_reg_unlock(chip); 5804 5805 return err; 5806 } 5807 5808 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5809 struct dsa_mall_mirror_tc_entry *mirror, 5810 bool ingress) 5811 { 5812 enum mv88e6xxx_egress_direction direction = ingress ? 5813 MV88E6XXX_EGRESS_DIR_INGRESS : 5814 MV88E6XXX_EGRESS_DIR_EGRESS; 5815 struct mv88e6xxx_chip *chip = ds->priv; 5816 bool other_mirrors = false; 5817 int i; 5818 int err; 5819 5820 mutex_lock(&chip->reg_lock); 5821 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5822 mirror->to_local_port) { 5823 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5824 other_mirrors |= ingress ? 5825 chip->ports[i].mirror_ingress : 5826 chip->ports[i].mirror_egress; 5827 5828 /* Can't change egress port when other mirror is active */ 5829 if (other_mirrors) { 5830 err = -EBUSY; 5831 goto out; 5832 } 5833 5834 err = mv88e6xxx_set_egress_port(chip, direction, 5835 mirror->to_local_port); 5836 if (err) 5837 goto out; 5838 } 5839 5840 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5841 out: 5842 mutex_unlock(&chip->reg_lock); 5843 5844 return err; 5845 } 5846 5847 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5848 struct dsa_mall_mirror_tc_entry *mirror) 5849 { 5850 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5851 MV88E6XXX_EGRESS_DIR_INGRESS : 5852 MV88E6XXX_EGRESS_DIR_EGRESS; 5853 struct mv88e6xxx_chip *chip = ds->priv; 5854 bool other_mirrors = false; 5855 int i; 5856 5857 mutex_lock(&chip->reg_lock); 5858 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5859 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5860 5861 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5862 other_mirrors |= mirror->ingress ? 5863 chip->ports[i].mirror_ingress : 5864 chip->ports[i].mirror_egress; 5865 5866 /* Reset egress port when no other mirror is active */ 5867 if (!other_mirrors) { 5868 if (mv88e6xxx_set_egress_port(chip, direction, 5869 dsa_upstream_port(ds, port))) 5870 dev_err(ds->dev, "failed to set egress port\n"); 5871 } 5872 5873 mutex_unlock(&chip->reg_lock); 5874 } 5875 5876 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5877 struct switchdev_brport_flags flags, 5878 struct netlink_ext_ack *extack) 5879 { 5880 struct mv88e6xxx_chip *chip = ds->priv; 5881 const struct mv88e6xxx_ops *ops; 5882 5883 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5884 BR_BCAST_FLOOD)) 5885 return -EINVAL; 5886 5887 ops = chip->info->ops; 5888 5889 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5890 return -EINVAL; 5891 5892 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5893 return -EINVAL; 5894 5895 return 0; 5896 } 5897 5898 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5899 struct switchdev_brport_flags flags, 5900 struct netlink_ext_ack *extack) 5901 { 5902 struct mv88e6xxx_chip *chip = ds->priv; 5903 int err = -EOPNOTSUPP; 5904 5905 mv88e6xxx_reg_lock(chip); 5906 5907 if (flags.mask & BR_LEARNING) { 5908 bool learning = !!(flags.val & BR_LEARNING); 5909 u16 pav = learning ? (1 << port) : 0; 5910 5911 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5912 if (err) 5913 goto out; 5914 } 5915 5916 if (flags.mask & BR_FLOOD) { 5917 bool unicast = !!(flags.val & BR_FLOOD); 5918 5919 err = chip->info->ops->port_set_ucast_flood(chip, port, 5920 unicast); 5921 if (err) 5922 goto out; 5923 } 5924 5925 if (flags.mask & BR_MCAST_FLOOD) { 5926 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5927 5928 err = chip->info->ops->port_set_mcast_flood(chip, port, 5929 multicast); 5930 if (err) 5931 goto out; 5932 } 5933 5934 if (flags.mask & BR_BCAST_FLOOD) { 5935 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5936 5937 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5938 if (err) 5939 goto out; 5940 } 5941 5942 out: 5943 mv88e6xxx_reg_unlock(chip); 5944 5945 return err; 5946 } 5947 5948 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5949 struct net_device *lag, 5950 struct netdev_lag_upper_info *info) 5951 { 5952 struct mv88e6xxx_chip *chip = ds->priv; 5953 struct dsa_port *dp; 5954 int id, members = 0; 5955 5956 if (!mv88e6xxx_has_lag(chip)) 5957 return false; 5958 5959 id = dsa_lag_id(ds->dst, lag); 5960 if (id < 0 || id >= ds->num_lag_ids) 5961 return false; 5962 5963 dsa_lag_foreach_port(dp, ds->dst, lag) 5964 /* Includes the port joining the LAG */ 5965 members++; 5966 5967 if (members > 8) 5968 return false; 5969 5970 /* We could potentially relax this to include active 5971 * backup in the future. 5972 */ 5973 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5974 return false; 5975 5976 /* Ideally we would also validate that the hash type matches 5977 * the hardware. Alas, this is always set to unknown on team 5978 * interfaces. 5979 */ 5980 return true; 5981 } 5982 5983 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5984 { 5985 struct mv88e6xxx_chip *chip = ds->priv; 5986 struct dsa_port *dp; 5987 u16 map = 0; 5988 int id; 5989 5990 id = dsa_lag_id(ds->dst, lag); 5991 5992 /* Build the map of all ports to distribute flows destined for 5993 * this LAG. This can be either a local user port, or a DSA 5994 * port if the LAG port is on a remote chip. 5995 */ 5996 dsa_lag_foreach_port(dp, ds->dst, lag) 5997 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 5998 5999 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6000 } 6001 6002 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6003 /* Row number corresponds to the number of active members in a 6004 * LAG. Each column states which of the eight hash buckets are 6005 * mapped to the column:th port in the LAG. 6006 * 6007 * Example: In a LAG with three active ports, the second port 6008 * ([2][1]) would be selected for traffic mapped to buckets 6009 * 3,4,5 (0x38). 6010 */ 6011 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6012 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6013 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6014 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6015 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6016 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6017 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6018 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6019 }; 6020 6021 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6022 int num_tx, int nth) 6023 { 6024 u8 active = 0; 6025 int i; 6026 6027 num_tx = num_tx <= 8 ? num_tx : 8; 6028 if (nth < num_tx) 6029 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6030 6031 for (i = 0; i < 8; i++) { 6032 if (BIT(i) & active) 6033 mask[i] |= BIT(port); 6034 } 6035 } 6036 6037 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6038 { 6039 struct mv88e6xxx_chip *chip = ds->priv; 6040 unsigned int id, num_tx; 6041 struct net_device *lag; 6042 struct dsa_port *dp; 6043 int i, err, nth; 6044 u16 mask[8]; 6045 u16 ivec; 6046 6047 /* Assume no port is a member of any LAG. */ 6048 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6049 6050 /* Disable all masks for ports that _are_ members of a LAG. */ 6051 list_for_each_entry(dp, &ds->dst->ports, list) { 6052 if (!dp->lag_dev || dp->ds != ds) 6053 continue; 6054 6055 ivec &= ~BIT(dp->index); 6056 } 6057 6058 for (i = 0; i < 8; i++) 6059 mask[i] = ivec; 6060 6061 /* Enable the correct subset of masks for all LAG ports that 6062 * are in the Tx set. 6063 */ 6064 dsa_lags_foreach_id(id, ds->dst) { 6065 lag = dsa_lag_dev(ds->dst, id); 6066 if (!lag) 6067 continue; 6068 6069 num_tx = 0; 6070 dsa_lag_foreach_port(dp, ds->dst, lag) { 6071 if (dp->lag_tx_enabled) 6072 num_tx++; 6073 } 6074 6075 if (!num_tx) 6076 continue; 6077 6078 nth = 0; 6079 dsa_lag_foreach_port(dp, ds->dst, lag) { 6080 if (!dp->lag_tx_enabled) 6081 continue; 6082 6083 if (dp->ds == ds) 6084 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6085 num_tx, nth); 6086 6087 nth++; 6088 } 6089 } 6090 6091 for (i = 0; i < 8; i++) { 6092 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6093 if (err) 6094 return err; 6095 } 6096 6097 return 0; 6098 } 6099 6100 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6101 struct net_device *lag) 6102 { 6103 int err; 6104 6105 err = mv88e6xxx_lag_sync_masks(ds); 6106 6107 if (!err) 6108 err = mv88e6xxx_lag_sync_map(ds, lag); 6109 6110 return err; 6111 } 6112 6113 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6114 { 6115 struct mv88e6xxx_chip *chip = ds->priv; 6116 int err; 6117 6118 mv88e6xxx_reg_lock(chip); 6119 err = mv88e6xxx_lag_sync_masks(ds); 6120 mv88e6xxx_reg_unlock(chip); 6121 return err; 6122 } 6123 6124 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6125 struct net_device *lag, 6126 struct netdev_lag_upper_info *info) 6127 { 6128 struct mv88e6xxx_chip *chip = ds->priv; 6129 int err, id; 6130 6131 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6132 return -EOPNOTSUPP; 6133 6134 id = dsa_lag_id(ds->dst, lag); 6135 6136 mv88e6xxx_reg_lock(chip); 6137 6138 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6139 if (err) 6140 goto err_unlock; 6141 6142 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6143 if (err) 6144 goto err_clear_trunk; 6145 6146 mv88e6xxx_reg_unlock(chip); 6147 return 0; 6148 6149 err_clear_trunk: 6150 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6151 err_unlock: 6152 mv88e6xxx_reg_unlock(chip); 6153 return err; 6154 } 6155 6156 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6157 struct net_device *lag) 6158 { 6159 struct mv88e6xxx_chip *chip = ds->priv; 6160 int err_sync, err_trunk; 6161 6162 mv88e6xxx_reg_lock(chip); 6163 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6164 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6165 mv88e6xxx_reg_unlock(chip); 6166 return err_sync ? : err_trunk; 6167 } 6168 6169 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6170 int port) 6171 { 6172 struct mv88e6xxx_chip *chip = ds->priv; 6173 int err; 6174 6175 mv88e6xxx_reg_lock(chip); 6176 err = mv88e6xxx_lag_sync_masks(ds); 6177 mv88e6xxx_reg_unlock(chip); 6178 return err; 6179 } 6180 6181 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6182 int port, struct net_device *lag, 6183 struct netdev_lag_upper_info *info) 6184 { 6185 struct mv88e6xxx_chip *chip = ds->priv; 6186 int err; 6187 6188 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6189 return -EOPNOTSUPP; 6190 6191 mv88e6xxx_reg_lock(chip); 6192 6193 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6194 if (err) 6195 goto unlock; 6196 6197 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6198 6199 unlock: 6200 mv88e6xxx_reg_unlock(chip); 6201 return err; 6202 } 6203 6204 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6205 int port, struct net_device *lag) 6206 { 6207 struct mv88e6xxx_chip *chip = ds->priv; 6208 int err_sync, err_pvt; 6209 6210 mv88e6xxx_reg_lock(chip); 6211 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6212 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6213 mv88e6xxx_reg_unlock(chip); 6214 return err_sync ? : err_pvt; 6215 } 6216 6217 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6218 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6219 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6220 .setup = mv88e6xxx_setup, 6221 .teardown = mv88e6xxx_teardown, 6222 .port_setup = mv88e6xxx_port_setup, 6223 .port_teardown = mv88e6xxx_port_teardown, 6224 .phylink_validate = mv88e6xxx_validate, 6225 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6226 .phylink_mac_config = mv88e6xxx_mac_config, 6227 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6228 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6229 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6230 .get_strings = mv88e6xxx_get_strings, 6231 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6232 .get_sset_count = mv88e6xxx_get_sset_count, 6233 .port_enable = mv88e6xxx_port_enable, 6234 .port_disable = mv88e6xxx_port_disable, 6235 .port_max_mtu = mv88e6xxx_get_max_mtu, 6236 .port_change_mtu = mv88e6xxx_change_mtu, 6237 .get_mac_eee = mv88e6xxx_get_mac_eee, 6238 .set_mac_eee = mv88e6xxx_set_mac_eee, 6239 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6240 .get_eeprom = mv88e6xxx_get_eeprom, 6241 .set_eeprom = mv88e6xxx_set_eeprom, 6242 .get_regs_len = mv88e6xxx_get_regs_len, 6243 .get_regs = mv88e6xxx_get_regs, 6244 .get_rxnfc = mv88e6xxx_get_rxnfc, 6245 .set_rxnfc = mv88e6xxx_set_rxnfc, 6246 .set_ageing_time = mv88e6xxx_set_ageing_time, 6247 .port_bridge_join = mv88e6xxx_port_bridge_join, 6248 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6249 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6250 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6251 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6252 .port_fast_age = mv88e6xxx_port_fast_age, 6253 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6254 .port_vlan_add = mv88e6xxx_port_vlan_add, 6255 .port_vlan_del = mv88e6xxx_port_vlan_del, 6256 .port_fdb_add = mv88e6xxx_port_fdb_add, 6257 .port_fdb_del = mv88e6xxx_port_fdb_del, 6258 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6259 .port_mdb_add = mv88e6xxx_port_mdb_add, 6260 .port_mdb_del = mv88e6xxx_port_mdb_del, 6261 .port_mirror_add = mv88e6xxx_port_mirror_add, 6262 .port_mirror_del = mv88e6xxx_port_mirror_del, 6263 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6264 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6265 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6266 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6267 .port_txtstamp = mv88e6xxx_port_txtstamp, 6268 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6269 .get_ts_info = mv88e6xxx_get_ts_info, 6270 .devlink_param_get = mv88e6xxx_devlink_param_get, 6271 .devlink_param_set = mv88e6xxx_devlink_param_set, 6272 .devlink_info_get = mv88e6xxx_devlink_info_get, 6273 .port_lag_change = mv88e6xxx_port_lag_change, 6274 .port_lag_join = mv88e6xxx_port_lag_join, 6275 .port_lag_leave = mv88e6xxx_port_lag_leave, 6276 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6277 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6278 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6279 }; 6280 6281 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6282 { 6283 struct device *dev = chip->dev; 6284 struct dsa_switch *ds; 6285 6286 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6287 if (!ds) 6288 return -ENOMEM; 6289 6290 ds->dev = dev; 6291 ds->num_ports = mv88e6xxx_num_ports(chip); 6292 ds->priv = chip; 6293 ds->dev = dev; 6294 ds->ops = &mv88e6xxx_switch_ops; 6295 ds->ageing_time_min = chip->info->age_time_coeff; 6296 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6297 6298 /* Some chips support up to 32, but that requires enabling the 6299 * 5-bit port mode, which we do not support. 640k^W16 ought to 6300 * be enough for anyone. 6301 */ 6302 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6303 6304 dev_set_drvdata(dev, ds); 6305 6306 return dsa_register_switch(ds); 6307 } 6308 6309 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6310 { 6311 dsa_unregister_switch(chip->ds); 6312 } 6313 6314 static const void *pdata_device_get_match_data(struct device *dev) 6315 { 6316 const struct of_device_id *matches = dev->driver->of_match_table; 6317 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6318 6319 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6320 matches++) { 6321 if (!strcmp(pdata->compatible, matches->compatible)) 6322 return matches->data; 6323 } 6324 return NULL; 6325 } 6326 6327 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6328 * would be lost after a power cycle so prevent it to be suspended. 6329 */ 6330 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6331 { 6332 return -EOPNOTSUPP; 6333 } 6334 6335 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6336 { 6337 return 0; 6338 } 6339 6340 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6341 6342 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6343 { 6344 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6345 const struct mv88e6xxx_info *compat_info = NULL; 6346 struct device *dev = &mdiodev->dev; 6347 struct device_node *np = dev->of_node; 6348 struct mv88e6xxx_chip *chip; 6349 int port; 6350 int err; 6351 6352 if (!np && !pdata) 6353 return -EINVAL; 6354 6355 if (np) 6356 compat_info = of_device_get_match_data(dev); 6357 6358 if (pdata) { 6359 compat_info = pdata_device_get_match_data(dev); 6360 6361 if (!pdata->netdev) 6362 return -EINVAL; 6363 6364 for (port = 0; port < DSA_MAX_PORTS; port++) { 6365 if (!(pdata->enabled_ports & (1 << port))) 6366 continue; 6367 if (strcmp(pdata->cd.port_names[port], "cpu")) 6368 continue; 6369 pdata->cd.netdev[port] = &pdata->netdev->dev; 6370 break; 6371 } 6372 } 6373 6374 if (!compat_info) 6375 return -EINVAL; 6376 6377 chip = mv88e6xxx_alloc_chip(dev); 6378 if (!chip) { 6379 err = -ENOMEM; 6380 goto out; 6381 } 6382 6383 chip->info = compat_info; 6384 6385 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6386 if (err) 6387 goto out; 6388 6389 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6390 if (IS_ERR(chip->reset)) { 6391 err = PTR_ERR(chip->reset); 6392 goto out; 6393 } 6394 if (chip->reset) 6395 usleep_range(1000, 2000); 6396 6397 err = mv88e6xxx_detect(chip); 6398 if (err) 6399 goto out; 6400 6401 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6402 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6403 else 6404 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6405 6406 mv88e6xxx_phy_init(chip); 6407 6408 if (chip->info->ops->get_eeprom) { 6409 if (np) 6410 of_property_read_u32(np, "eeprom-length", 6411 &chip->eeprom_len); 6412 else 6413 chip->eeprom_len = pdata->eeprom_len; 6414 } 6415 6416 mv88e6xxx_reg_lock(chip); 6417 err = mv88e6xxx_switch_reset(chip); 6418 mv88e6xxx_reg_unlock(chip); 6419 if (err) 6420 goto out; 6421 6422 if (np) { 6423 chip->irq = of_irq_get(np, 0); 6424 if (chip->irq == -EPROBE_DEFER) { 6425 err = chip->irq; 6426 goto out; 6427 } 6428 } 6429 6430 if (pdata) 6431 chip->irq = pdata->irq; 6432 6433 /* Has to be performed before the MDIO bus is created, because 6434 * the PHYs will link their interrupts to these interrupt 6435 * controllers 6436 */ 6437 mv88e6xxx_reg_lock(chip); 6438 if (chip->irq > 0) 6439 err = mv88e6xxx_g1_irq_setup(chip); 6440 else 6441 err = mv88e6xxx_irq_poll_setup(chip); 6442 mv88e6xxx_reg_unlock(chip); 6443 6444 if (err) 6445 goto out; 6446 6447 if (chip->info->g2_irqs > 0) { 6448 err = mv88e6xxx_g2_irq_setup(chip); 6449 if (err) 6450 goto out_g1_irq; 6451 } 6452 6453 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6454 if (err) 6455 goto out_g2_irq; 6456 6457 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6458 if (err) 6459 goto out_g1_atu_prob_irq; 6460 6461 err = mv88e6xxx_mdios_register(chip, np); 6462 if (err) 6463 goto out_g1_vtu_prob_irq; 6464 6465 err = mv88e6xxx_register_switch(chip); 6466 if (err) 6467 goto out_mdio; 6468 6469 return 0; 6470 6471 out_mdio: 6472 mv88e6xxx_mdios_unregister(chip); 6473 out_g1_vtu_prob_irq: 6474 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6475 out_g1_atu_prob_irq: 6476 mv88e6xxx_g1_atu_prob_irq_free(chip); 6477 out_g2_irq: 6478 if (chip->info->g2_irqs > 0) 6479 mv88e6xxx_g2_irq_free(chip); 6480 out_g1_irq: 6481 if (chip->irq > 0) 6482 mv88e6xxx_g1_irq_free(chip); 6483 else 6484 mv88e6xxx_irq_poll_free(chip); 6485 out: 6486 if (pdata) 6487 dev_put(pdata->netdev); 6488 6489 return err; 6490 } 6491 6492 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6493 { 6494 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6495 struct mv88e6xxx_chip *chip; 6496 6497 if (!ds) 6498 return; 6499 6500 chip = ds->priv; 6501 6502 if (chip->info->ptp_support) { 6503 mv88e6xxx_hwtstamp_free(chip); 6504 mv88e6xxx_ptp_free(chip); 6505 } 6506 6507 mv88e6xxx_phy_destroy(chip); 6508 mv88e6xxx_unregister_switch(chip); 6509 mv88e6xxx_mdios_unregister(chip); 6510 6511 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6512 mv88e6xxx_g1_atu_prob_irq_free(chip); 6513 6514 if (chip->info->g2_irqs > 0) 6515 mv88e6xxx_g2_irq_free(chip); 6516 6517 if (chip->irq > 0) 6518 mv88e6xxx_g1_irq_free(chip); 6519 else 6520 mv88e6xxx_irq_poll_free(chip); 6521 6522 dev_set_drvdata(&mdiodev->dev, NULL); 6523 } 6524 6525 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6526 { 6527 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6528 6529 if (!ds) 6530 return; 6531 6532 dsa_switch_shutdown(ds); 6533 6534 dev_set_drvdata(&mdiodev->dev, NULL); 6535 } 6536 6537 static const struct of_device_id mv88e6xxx_of_match[] = { 6538 { 6539 .compatible = "marvell,mv88e6085", 6540 .data = &mv88e6xxx_table[MV88E6085], 6541 }, 6542 { 6543 .compatible = "marvell,mv88e6190", 6544 .data = &mv88e6xxx_table[MV88E6190], 6545 }, 6546 { 6547 .compatible = "marvell,mv88e6250", 6548 .data = &mv88e6xxx_table[MV88E6250], 6549 }, 6550 { /* sentinel */ }, 6551 }; 6552 6553 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6554 6555 static struct mdio_driver mv88e6xxx_driver = { 6556 .probe = mv88e6xxx_probe, 6557 .remove = mv88e6xxx_remove, 6558 .shutdown = mv88e6xxx_shutdown, 6559 .mdiodrv.driver = { 6560 .name = "mv88e6085", 6561 .of_match_table = mv88e6xxx_of_match, 6562 .pm = &mv88e6xxx_pm_ops, 6563 }, 6564 }; 6565 6566 mdio_module_driver(mv88e6xxx_driver); 6567 6568 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6569 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6570 MODULE_LICENSE("GPL"); 6571