1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2015 CMC Electronics, Inc. 7 * Added support for VLAN Table Unit operations 8 * 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 #include <net/switchdev.h> 36 37 #include "mv88e6xxx.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "port.h" 41 42 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 43 { 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 45 dev_err(chip->dev, "Switch registers lock not held!\n"); 46 dump_stack(); 47 } 48 } 49 50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 52 * 53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 54 * is the only device connected to the SMI master. In this mode it responds to 55 * all 32 possible SMI addresses, and thus maps directly the internal devices. 56 * 57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 58 * multiple devices to share the SMI interface. In this mode it responds to only 59 * 2 registers, used to indirectly access the internal SMI devices. 60 */ 61 62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 63 int addr, int reg, u16 *val) 64 { 65 if (!chip->smi_ops) 66 return -EOPNOTSUPP; 67 68 return chip->smi_ops->read(chip, addr, reg, val); 69 } 70 71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 72 int addr, int reg, u16 val) 73 { 74 if (!chip->smi_ops) 75 return -EOPNOTSUPP; 76 77 return chip->smi_ops->write(chip, addr, reg, val); 78 } 79 80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 81 int addr, int reg, u16 *val) 82 { 83 int ret; 84 85 ret = mdiobus_read_nested(chip->bus, addr, reg); 86 if (ret < 0) 87 return ret; 88 89 *val = ret & 0xffff; 90 91 return 0; 92 } 93 94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 95 int addr, int reg, u16 val) 96 { 97 int ret; 98 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 100 if (ret < 0) 101 return ret; 102 103 return 0; 104 } 105 106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 107 .read = mv88e6xxx_smi_single_chip_read, 108 .write = mv88e6xxx_smi_single_chip_write, 109 }; 110 111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 112 { 113 int ret; 114 int i; 115 116 for (i = 0; i < 16; i++) { 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 118 if (ret < 0) 119 return ret; 120 121 if ((ret & SMI_CMD_BUSY) == 0) 122 return 0; 123 } 124 125 return -ETIMEDOUT; 126 } 127 128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 129 int addr, int reg, u16 *val) 130 { 131 int ret; 132 133 /* Wait for the bus to become free. */ 134 ret = mv88e6xxx_smi_multi_chip_wait(chip); 135 if (ret < 0) 136 return ret; 137 138 /* Transmit the read command. */ 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 140 SMI_CMD_OP_22_READ | (addr << 5) | reg); 141 if (ret < 0) 142 return ret; 143 144 /* Wait for the read command to complete. */ 145 ret = mv88e6xxx_smi_multi_chip_wait(chip); 146 if (ret < 0) 147 return ret; 148 149 /* Read the data. */ 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 151 if (ret < 0) 152 return ret; 153 154 *val = ret & 0xffff; 155 156 return 0; 157 } 158 159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 160 int addr, int reg, u16 val) 161 { 162 int ret; 163 164 /* Wait for the bus to become free. */ 165 ret = mv88e6xxx_smi_multi_chip_wait(chip); 166 if (ret < 0) 167 return ret; 168 169 /* Transmit the data to write. */ 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the write command. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 177 if (ret < 0) 178 return ret; 179 180 /* Wait for the write command to complete. */ 181 ret = mv88e6xxx_smi_multi_chip_wait(chip); 182 if (ret < 0) 183 return ret; 184 185 return 0; 186 } 187 188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 189 .read = mv88e6xxx_smi_multi_chip_read, 190 .write = mv88e6xxx_smi_multi_chip_write, 191 }; 192 193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 194 { 195 int err; 196 197 assert_reg_lock(chip); 198 199 err = mv88e6xxx_smi_read(chip, addr, reg, val); 200 if (err) 201 return err; 202 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 204 addr, reg, *val); 205 206 return 0; 207 } 208 209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 210 { 211 int err; 212 213 assert_reg_lock(chip); 214 215 err = mv88e6xxx_smi_write(chip, addr, reg, val); 216 if (err) 217 return err; 218 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 220 addr, reg, val); 221 222 return 0; 223 } 224 225 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, 226 int reg, u16 *val) 227 { 228 int addr = phy; /* PHY devices addresses start at 0x0 */ 229 230 if (!chip->info->ops->phy_read) 231 return -EOPNOTSUPP; 232 233 return chip->info->ops->phy_read(chip, addr, reg, val); 234 } 235 236 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 237 int reg, u16 val) 238 { 239 int addr = phy; /* PHY devices addresses start at 0x0 */ 240 241 if (!chip->info->ops->phy_write) 242 return -EOPNOTSUPP; 243 244 return chip->info->ops->phy_write(chip, addr, reg, val); 245 } 246 247 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) 248 { 249 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) 250 return -EOPNOTSUPP; 251 252 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 253 } 254 255 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) 256 { 257 int err; 258 259 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ 260 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); 261 if (unlikely(err)) { 262 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", 263 phy, err); 264 } 265 } 266 267 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 268 u8 page, int reg, u16 *val) 269 { 270 int err; 271 272 /* There is no paging for registers 22 */ 273 if (reg == PHY_PAGE) 274 return -EINVAL; 275 276 err = mv88e6xxx_phy_page_get(chip, phy, page); 277 if (!err) { 278 err = mv88e6xxx_phy_read(chip, phy, reg, val); 279 mv88e6xxx_phy_page_put(chip, phy); 280 } 281 282 return err; 283 } 284 285 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, 286 u8 page, int reg, u16 val) 287 { 288 int err; 289 290 /* There is no paging for registers 22 */ 291 if (reg == PHY_PAGE) 292 return -EINVAL; 293 294 err = mv88e6xxx_phy_page_get(chip, phy, page); 295 if (!err) { 296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 297 mv88e6xxx_phy_page_put(chip, phy); 298 } 299 300 return err; 301 } 302 303 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 304 { 305 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 306 reg, val); 307 } 308 309 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 310 { 311 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 312 reg, val); 313 } 314 315 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 316 { 317 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 318 unsigned int n = d->hwirq; 319 320 chip->g1_irq.masked |= (1 << n); 321 } 322 323 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 324 { 325 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 326 unsigned int n = d->hwirq; 327 328 chip->g1_irq.masked &= ~(1 << n); 329 } 330 331 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 332 { 333 struct mv88e6xxx_chip *chip = dev_id; 334 unsigned int nhandled = 0; 335 unsigned int sub_irq; 336 unsigned int n; 337 u16 reg; 338 int err; 339 340 mutex_lock(&chip->reg_lock); 341 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 342 mutex_unlock(&chip->reg_lock); 343 344 if (err) 345 goto out; 346 347 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 348 if (reg & (1 << n)) { 349 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 350 handle_nested_irq(sub_irq); 351 ++nhandled; 352 } 353 } 354 out: 355 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 356 } 357 358 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 359 { 360 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 361 362 mutex_lock(&chip->reg_lock); 363 } 364 365 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 366 { 367 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 368 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 369 u16 reg; 370 int err; 371 372 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); 373 if (err) 374 goto out; 375 376 reg &= ~mask; 377 reg |= (~chip->g1_irq.masked & mask); 378 379 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); 380 if (err) 381 goto out; 382 383 out: 384 mutex_unlock(&chip->reg_lock); 385 } 386 387 static struct irq_chip mv88e6xxx_g1_irq_chip = { 388 .name = "mv88e6xxx-g1", 389 .irq_mask = mv88e6xxx_g1_irq_mask, 390 .irq_unmask = mv88e6xxx_g1_irq_unmask, 391 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 392 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 393 }; 394 395 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 396 unsigned int irq, 397 irq_hw_number_t hwirq) 398 { 399 struct mv88e6xxx_chip *chip = d->host_data; 400 401 irq_set_chip_data(irq, d->host_data); 402 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 403 irq_set_noprobe(irq); 404 405 return 0; 406 } 407 408 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 409 .map = mv88e6xxx_g1_irq_domain_map, 410 .xlate = irq_domain_xlate_twocell, 411 }; 412 413 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 414 { 415 int irq, virq; 416 u16 mask; 417 418 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 419 mask |= GENMASK(chip->g1_irq.nirqs, 0); 420 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 421 422 free_irq(chip->irq, chip); 423 424 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 425 virq = irq_find_mapping(chip->g1_irq.domain, irq); 426 irq_dispose_mapping(virq); 427 } 428 429 irq_domain_remove(chip->g1_irq.domain); 430 } 431 432 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 433 { 434 int err, irq, virq; 435 u16 reg, mask; 436 437 chip->g1_irq.nirqs = chip->info->g1_irqs; 438 chip->g1_irq.domain = irq_domain_add_simple( 439 NULL, chip->g1_irq.nirqs, 0, 440 &mv88e6xxx_g1_irq_domain_ops, chip); 441 if (!chip->g1_irq.domain) 442 return -ENOMEM; 443 444 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 445 irq_create_mapping(chip->g1_irq.domain, irq); 446 447 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 448 chip->g1_irq.masked = ~0; 449 450 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 451 if (err) 452 goto out_mapping; 453 454 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 455 456 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 457 if (err) 458 goto out_disable; 459 460 /* Reading the interrupt status clears (most of) them */ 461 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 462 if (err) 463 goto out_disable; 464 465 err = request_threaded_irq(chip->irq, NULL, 466 mv88e6xxx_g1_irq_thread_fn, 467 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 468 dev_name(chip->dev), chip); 469 if (err) 470 goto out_disable; 471 472 return 0; 473 474 out_disable: 475 mask |= GENMASK(chip->g1_irq.nirqs, 0); 476 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 477 478 out_mapping: 479 for (irq = 0; irq < 16; irq++) { 480 virq = irq_find_mapping(chip->g1_irq.domain, irq); 481 irq_dispose_mapping(virq); 482 } 483 484 irq_domain_remove(chip->g1_irq.domain); 485 486 return err; 487 } 488 489 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 490 { 491 int i; 492 493 for (i = 0; i < 16; i++) { 494 u16 val; 495 int err; 496 497 err = mv88e6xxx_read(chip, addr, reg, &val); 498 if (err) 499 return err; 500 501 if (!(val & mask)) 502 return 0; 503 504 usleep_range(1000, 2000); 505 } 506 507 dev_err(chip->dev, "Timeout while waiting for switch\n"); 508 return -ETIMEDOUT; 509 } 510 511 /* Indirect write to single pointer-data register with an Update bit */ 512 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 513 { 514 u16 val; 515 int err; 516 517 /* Wait until the previous operation is completed */ 518 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 519 if (err) 520 return err; 521 522 /* Set the Update bit to trigger a write operation */ 523 val = BIT(15) | update; 524 525 return mv88e6xxx_write(chip, addr, reg, val); 526 } 527 528 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) 529 { 530 if (!chip->info->ops->ppu_disable) 531 return 0; 532 533 return chip->info->ops->ppu_disable(chip); 534 } 535 536 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) 537 { 538 if (!chip->info->ops->ppu_enable) 539 return 0; 540 541 return chip->info->ops->ppu_enable(chip); 542 } 543 544 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) 545 { 546 struct mv88e6xxx_chip *chip; 547 548 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); 549 550 mutex_lock(&chip->reg_lock); 551 552 if (mutex_trylock(&chip->ppu_mutex)) { 553 if (mv88e6xxx_ppu_enable(chip) == 0) 554 chip->ppu_disabled = 0; 555 mutex_unlock(&chip->ppu_mutex); 556 } 557 558 mutex_unlock(&chip->reg_lock); 559 } 560 561 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) 562 { 563 struct mv88e6xxx_chip *chip = (void *)_ps; 564 565 schedule_work(&chip->ppu_work); 566 } 567 568 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) 569 { 570 int ret; 571 572 mutex_lock(&chip->ppu_mutex); 573 574 /* If the PHY polling unit is enabled, disable it so that 575 * we can access the PHY registers. If it was already 576 * disabled, cancel the timer that is going to re-enable 577 * it. 578 */ 579 if (!chip->ppu_disabled) { 580 ret = mv88e6xxx_ppu_disable(chip); 581 if (ret < 0) { 582 mutex_unlock(&chip->ppu_mutex); 583 return ret; 584 } 585 chip->ppu_disabled = 1; 586 } else { 587 del_timer(&chip->ppu_timer); 588 ret = 0; 589 } 590 591 return ret; 592 } 593 594 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) 595 { 596 /* Schedule a timer to re-enable the PHY polling unit. */ 597 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); 598 mutex_unlock(&chip->ppu_mutex); 599 } 600 601 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) 602 { 603 mutex_init(&chip->ppu_mutex); 604 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); 605 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer, 606 (unsigned long)chip); 607 } 608 609 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) 610 { 611 del_timer_sync(&chip->ppu_timer); 612 } 613 614 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, 615 int reg, u16 *val) 616 { 617 int err; 618 619 err = mv88e6xxx_ppu_access_get(chip); 620 if (!err) { 621 err = mv88e6xxx_read(chip, addr, reg, val); 622 mv88e6xxx_ppu_access_put(chip); 623 } 624 625 return err; 626 } 627 628 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, 629 int reg, u16 val) 630 { 631 int err; 632 633 err = mv88e6xxx_ppu_access_get(chip); 634 if (!err) { 635 err = mv88e6xxx_write(chip, addr, reg, val); 636 mv88e6xxx_ppu_access_put(chip); 637 } 638 639 return err; 640 } 641 642 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) 643 { 644 return chip->info->family == MV88E6XXX_FAMILY_6095; 645 } 646 647 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) 648 { 649 return chip->info->family == MV88E6XXX_FAMILY_6097; 650 } 651 652 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) 653 { 654 return chip->info->family == MV88E6XXX_FAMILY_6165; 655 } 656 657 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) 658 { 659 return chip->info->family == MV88E6XXX_FAMILY_6185; 660 } 661 662 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) 663 { 664 return chip->info->family == MV88E6XXX_FAMILY_6320; 665 } 666 667 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) 668 { 669 return chip->info->family == MV88E6XXX_FAMILY_6351; 670 } 671 672 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) 673 { 674 return chip->info->family == MV88E6XXX_FAMILY_6352; 675 } 676 677 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 678 int link, int speed, int duplex, 679 phy_interface_t mode) 680 { 681 int err; 682 683 if (!chip->info->ops->port_set_link) 684 return 0; 685 686 /* Port's MAC control must not be changed unless the link is down */ 687 err = chip->info->ops->port_set_link(chip, port, 0); 688 if (err) 689 return err; 690 691 if (chip->info->ops->port_set_speed) { 692 err = chip->info->ops->port_set_speed(chip, port, speed); 693 if (err && err != -EOPNOTSUPP) 694 goto restore_link; 695 } 696 697 if (chip->info->ops->port_set_duplex) { 698 err = chip->info->ops->port_set_duplex(chip, port, duplex); 699 if (err && err != -EOPNOTSUPP) 700 goto restore_link; 701 } 702 703 if (chip->info->ops->port_set_rgmii_delay) { 704 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 705 if (err && err != -EOPNOTSUPP) 706 goto restore_link; 707 } 708 709 err = 0; 710 restore_link: 711 if (chip->info->ops->port_set_link(chip, port, link)) 712 netdev_err(chip->ds->ports[port].netdev, 713 "failed to restore MAC's link\n"); 714 715 return err; 716 } 717 718 /* We expect the switch to perform auto negotiation if there is a real 719 * phy. However, in the case of a fixed link phy, we force the port 720 * settings from the fixed link settings. 721 */ 722 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 723 struct phy_device *phydev) 724 { 725 struct mv88e6xxx_chip *chip = ds->priv; 726 int err; 727 728 if (!phy_is_pseudo_fixed_link(phydev)) 729 return; 730 731 mutex_lock(&chip->reg_lock); 732 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 733 phydev->duplex, phydev->interface); 734 mutex_unlock(&chip->reg_lock); 735 736 if (err && err != -EOPNOTSUPP) 737 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n"); 738 } 739 740 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 741 { 742 if (!chip->info->ops->stats_snapshot) 743 return -EOPNOTSUPP; 744 745 return chip->info->ops->stats_snapshot(chip, port); 746 } 747 748 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 749 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 750 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 751 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 752 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 753 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 754 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 755 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 756 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 757 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 758 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 759 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 760 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 761 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 762 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 763 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 764 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 765 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 766 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 767 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 768 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 769 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 770 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 771 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 772 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 773 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 774 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 775 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 776 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 777 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 778 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 779 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 780 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 781 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 782 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 783 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 784 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 785 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 786 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 787 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 788 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 789 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 790 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 791 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 792 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 793 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 794 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 795 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 796 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 797 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 798 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 799 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 800 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 801 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 802 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 803 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 804 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 805 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 806 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 807 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 808 }; 809 810 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 811 struct mv88e6xxx_hw_stat *s, 812 int port, u16 bank1_select, 813 u16 histogram) 814 { 815 u32 low; 816 u32 high = 0; 817 u16 reg = 0; 818 int err; 819 u64 value; 820 821 switch (s->type) { 822 case STATS_TYPE_PORT: 823 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 824 if (err) 825 return UINT64_MAX; 826 827 low = reg; 828 if (s->sizeof_stat == 4) { 829 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 830 if (err) 831 return UINT64_MAX; 832 high = reg; 833 } 834 break; 835 case STATS_TYPE_BANK1: 836 reg = bank1_select; 837 /* fall through */ 838 case STATS_TYPE_BANK0: 839 reg |= s->reg | histogram; 840 mv88e6xxx_g1_stats_read(chip, reg, &low); 841 if (s->sizeof_stat == 8) 842 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 843 } 844 value = (((u64)high) << 16) | low; 845 return value; 846 } 847 848 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 849 uint8_t *data, int types) 850 { 851 struct mv88e6xxx_hw_stat *stat; 852 int i, j; 853 854 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 855 stat = &mv88e6xxx_hw_stats[i]; 856 if (stat->type & types) { 857 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 858 ETH_GSTRING_LEN); 859 j++; 860 } 861 } 862 } 863 864 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 865 uint8_t *data) 866 { 867 mv88e6xxx_stats_get_strings(chip, data, 868 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 869 } 870 871 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 872 uint8_t *data) 873 { 874 mv88e6xxx_stats_get_strings(chip, data, 875 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 876 } 877 878 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 879 uint8_t *data) 880 { 881 struct mv88e6xxx_chip *chip = ds->priv; 882 883 if (chip->info->ops->stats_get_strings) 884 chip->info->ops->stats_get_strings(chip, data); 885 } 886 887 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 888 int types) 889 { 890 struct mv88e6xxx_hw_stat *stat; 891 int i, j; 892 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 894 stat = &mv88e6xxx_hw_stats[i]; 895 if (stat->type & types) 896 j++; 897 } 898 return j; 899 } 900 901 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 902 { 903 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 904 STATS_TYPE_PORT); 905 } 906 907 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 908 { 909 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 910 STATS_TYPE_BANK1); 911 } 912 913 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 914 { 915 struct mv88e6xxx_chip *chip = ds->priv; 916 917 if (chip->info->ops->stats_get_sset_count) 918 return chip->info->ops->stats_get_sset_count(chip); 919 920 return 0; 921 } 922 923 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 924 uint64_t *data, int types, 925 u16 bank1_select, u16 histogram) 926 { 927 struct mv88e6xxx_hw_stat *stat; 928 int i, j; 929 930 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 931 stat = &mv88e6xxx_hw_stats[i]; 932 if (stat->type & types) { 933 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 934 bank1_select, 935 histogram); 936 j++; 937 } 938 } 939 } 940 941 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 942 uint64_t *data) 943 { 944 return mv88e6xxx_stats_get_stats(chip, port, data, 945 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 946 0, GLOBAL_STATS_OP_HIST_RX_TX); 947 } 948 949 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 950 uint64_t *data) 951 { 952 return mv88e6xxx_stats_get_stats(chip, port, data, 953 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 954 GLOBAL_STATS_OP_BANK_1_BIT_9, 955 GLOBAL_STATS_OP_HIST_RX_TX); 956 } 957 958 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 959 uint64_t *data) 960 { 961 return mv88e6xxx_stats_get_stats(chip, port, data, 962 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 963 GLOBAL_STATS_OP_BANK_1_BIT_10, 0); 964 } 965 966 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 967 uint64_t *data) 968 { 969 if (chip->info->ops->stats_get_stats) 970 chip->info->ops->stats_get_stats(chip, port, data); 971 } 972 973 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 974 uint64_t *data) 975 { 976 struct mv88e6xxx_chip *chip = ds->priv; 977 int ret; 978 979 mutex_lock(&chip->reg_lock); 980 981 ret = mv88e6xxx_stats_snapshot(chip, port); 982 if (ret < 0) { 983 mutex_unlock(&chip->reg_lock); 984 return; 985 } 986 987 mv88e6xxx_get_stats(chip, port, data); 988 989 mutex_unlock(&chip->reg_lock); 990 } 991 992 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 993 { 994 if (chip->info->ops->stats_set_histogram) 995 return chip->info->ops->stats_set_histogram(chip); 996 997 return 0; 998 } 999 1000 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1001 { 1002 return 32 * sizeof(u16); 1003 } 1004 1005 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1006 struct ethtool_regs *regs, void *_p) 1007 { 1008 struct mv88e6xxx_chip *chip = ds->priv; 1009 int err; 1010 u16 reg; 1011 u16 *p = _p; 1012 int i; 1013 1014 regs->version = 0; 1015 1016 memset(p, 0xff, 32 * sizeof(u16)); 1017 1018 mutex_lock(&chip->reg_lock); 1019 1020 for (i = 0; i < 32; i++) { 1021 1022 err = mv88e6xxx_port_read(chip, port, i, ®); 1023 if (!err) 1024 p[i] = reg; 1025 } 1026 1027 mutex_unlock(&chip->reg_lock); 1028 } 1029 1030 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) 1031 { 1032 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); 1033 } 1034 1035 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 1036 struct ethtool_eee *e) 1037 { 1038 struct mv88e6xxx_chip *chip = ds->priv; 1039 u16 reg; 1040 int err; 1041 1042 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1043 return -EOPNOTSUPP; 1044 1045 mutex_lock(&chip->reg_lock); 1046 1047 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1048 if (err) 1049 goto out; 1050 1051 e->eee_enabled = !!(reg & 0x0200); 1052 e->tx_lpi_enabled = !!(reg & 0x0100); 1053 1054 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 1055 if (err) 1056 goto out; 1057 1058 e->eee_active = !!(reg & PORT_STATUS_EEE); 1059 out: 1060 mutex_unlock(&chip->reg_lock); 1061 1062 return err; 1063 } 1064 1065 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 1066 struct phy_device *phydev, struct ethtool_eee *e) 1067 { 1068 struct mv88e6xxx_chip *chip = ds->priv; 1069 u16 reg; 1070 int err; 1071 1072 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1073 return -EOPNOTSUPP; 1074 1075 mutex_lock(&chip->reg_lock); 1076 1077 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1078 if (err) 1079 goto out; 1080 1081 reg &= ~0x0300; 1082 if (e->eee_enabled) 1083 reg |= 0x0200; 1084 if (e->tx_lpi_enabled) 1085 reg |= 0x0100; 1086 1087 err = mv88e6xxx_phy_write(chip, port, 16, reg); 1088 out: 1089 mutex_unlock(&chip->reg_lock); 1090 1091 return err; 1092 } 1093 1094 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) 1095 { 1096 u16 val; 1097 int err; 1098 1099 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { 1100 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); 1101 if (err) 1102 return err; 1103 } else if (mv88e6xxx_num_databases(chip) == 256) { 1104 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 1105 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 1106 if (err) 1107 return err; 1108 1109 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 1110 (val & 0xfff) | ((fid << 8) & 0xf000)); 1111 if (err) 1112 return err; 1113 1114 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1115 cmd |= fid & 0xf; 1116 } 1117 1118 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); 1119 if (err) 1120 return err; 1121 1122 return _mv88e6xxx_atu_wait(chip); 1123 } 1124 1125 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, 1126 struct mv88e6xxx_atu_entry *entry) 1127 { 1128 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; 1129 1130 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { 1131 unsigned int mask, shift; 1132 1133 if (entry->trunk) { 1134 data |= GLOBAL_ATU_DATA_TRUNK; 1135 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 1136 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 1137 } else { 1138 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 1139 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 1140 } 1141 1142 data |= (entry->portv_trunkid << shift) & mask; 1143 } 1144 1145 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); 1146 } 1147 1148 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, 1149 struct mv88e6xxx_atu_entry *entry, 1150 bool static_too) 1151 { 1152 int op; 1153 int err; 1154 1155 err = _mv88e6xxx_atu_wait(chip); 1156 if (err) 1157 return err; 1158 1159 err = _mv88e6xxx_atu_data_write(chip, entry); 1160 if (err) 1161 return err; 1162 1163 if (entry->fid) { 1164 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : 1165 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 1166 } else { 1167 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : 1168 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; 1169 } 1170 1171 return _mv88e6xxx_atu_cmd(chip, entry->fid, op); 1172 } 1173 1174 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, 1175 u16 fid, bool static_too) 1176 { 1177 struct mv88e6xxx_atu_entry entry = { 1178 .fid = fid, 1179 .state = 0, /* EntryState bits must be 0 */ 1180 }; 1181 1182 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1183 } 1184 1185 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 1186 int from_port, int to_port, bool static_too) 1187 { 1188 struct mv88e6xxx_atu_entry entry = { 1189 .trunk = false, 1190 .fid = fid, 1191 }; 1192 1193 /* EntryState bits must be 0xF */ 1194 entry.state = GLOBAL_ATU_DATA_STATE_MASK; 1195 1196 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ 1197 entry.portv_trunkid = (to_port & 0x0f) << 4; 1198 entry.portv_trunkid |= from_port & 0x0f; 1199 1200 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1201 } 1202 1203 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, 1204 int port, bool static_too) 1205 { 1206 /* Destination port 0xF means remove the entries */ 1207 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); 1208 } 1209 1210 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) 1211 { 1212 struct net_device *bridge = chip->ports[port].bridge_dev; 1213 struct dsa_switch *ds = chip->ds; 1214 u16 output_ports = 0; 1215 int i; 1216 1217 /* allow CPU port or DSA link(s) to send frames to every port */ 1218 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 1219 output_ports = ~0; 1220 } else { 1221 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1222 /* allow sending frames to every group member */ 1223 if (bridge && chip->ports[i].bridge_dev == bridge) 1224 output_ports |= BIT(i); 1225 1226 /* allow sending frames to CPU port and DSA link(s) */ 1227 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1228 output_ports |= BIT(i); 1229 } 1230 } 1231 1232 /* prevent frames from going back out of the port they came in on */ 1233 output_ports &= ~BIT(port); 1234 1235 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1236 } 1237 1238 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1239 u8 state) 1240 { 1241 struct mv88e6xxx_chip *chip = ds->priv; 1242 int stp_state; 1243 int err; 1244 1245 switch (state) { 1246 case BR_STATE_DISABLED: 1247 stp_state = PORT_CONTROL_STATE_DISABLED; 1248 break; 1249 case BR_STATE_BLOCKING: 1250 case BR_STATE_LISTENING: 1251 stp_state = PORT_CONTROL_STATE_BLOCKING; 1252 break; 1253 case BR_STATE_LEARNING: 1254 stp_state = PORT_CONTROL_STATE_LEARNING; 1255 break; 1256 case BR_STATE_FORWARDING: 1257 default: 1258 stp_state = PORT_CONTROL_STATE_FORWARDING; 1259 break; 1260 } 1261 1262 mutex_lock(&chip->reg_lock); 1263 err = mv88e6xxx_port_set_state(chip, port, stp_state); 1264 mutex_unlock(&chip->reg_lock); 1265 1266 if (err) 1267 netdev_err(ds->ports[port].netdev, "failed to update state\n"); 1268 } 1269 1270 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1271 { 1272 struct mv88e6xxx_chip *chip = ds->priv; 1273 int err; 1274 1275 mutex_lock(&chip->reg_lock); 1276 err = _mv88e6xxx_atu_remove(chip, 0, port, false); 1277 mutex_unlock(&chip->reg_lock); 1278 1279 if (err) 1280 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); 1281 } 1282 1283 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) 1284 { 1285 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); 1286 } 1287 1288 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) 1289 { 1290 int err; 1291 1292 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); 1293 if (err) 1294 return err; 1295 1296 return _mv88e6xxx_vtu_wait(chip); 1297 } 1298 1299 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) 1300 { 1301 int ret; 1302 1303 ret = _mv88e6xxx_vtu_wait(chip); 1304 if (ret < 0) 1305 return ret; 1306 1307 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); 1308 } 1309 1310 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, 1311 struct mv88e6xxx_vtu_entry *entry, 1312 unsigned int nibble_offset) 1313 { 1314 u16 regs[3]; 1315 int i, err; 1316 1317 for (i = 0; i < 3; ++i) { 1318 u16 *reg = ®s[i]; 1319 1320 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1321 if (err) 1322 return err; 1323 } 1324 1325 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1326 unsigned int shift = (i % 4) * 4 + nibble_offset; 1327 u16 reg = regs[i / 4]; 1328 1329 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; 1330 } 1331 1332 return 0; 1333 } 1334 1335 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, 1336 struct mv88e6xxx_vtu_entry *entry) 1337 { 1338 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); 1339 } 1340 1341 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, 1342 struct mv88e6xxx_vtu_entry *entry) 1343 { 1344 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); 1345 } 1346 1347 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, 1348 struct mv88e6xxx_vtu_entry *entry, 1349 unsigned int nibble_offset) 1350 { 1351 u16 regs[3] = { 0 }; 1352 int i, err; 1353 1354 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1355 unsigned int shift = (i % 4) * 4 + nibble_offset; 1356 u8 data = entry->data[i]; 1357 1358 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; 1359 } 1360 1361 for (i = 0; i < 3; ++i) { 1362 u16 reg = regs[i]; 1363 1364 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1365 if (err) 1366 return err; 1367 } 1368 1369 return 0; 1370 } 1371 1372 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, 1373 struct mv88e6xxx_vtu_entry *entry) 1374 { 1375 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); 1376 } 1377 1378 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, 1379 struct mv88e6xxx_vtu_entry *entry) 1380 { 1381 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); 1382 } 1383 1384 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) 1385 { 1386 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, 1387 vid & GLOBAL_VTU_VID_MASK); 1388 } 1389 1390 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1391 struct mv88e6xxx_vtu_entry *entry) 1392 { 1393 struct mv88e6xxx_vtu_entry next = { 0 }; 1394 u16 val; 1395 int err; 1396 1397 err = _mv88e6xxx_vtu_wait(chip); 1398 if (err) 1399 return err; 1400 1401 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); 1402 if (err) 1403 return err; 1404 1405 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1406 if (err) 1407 return err; 1408 1409 next.vid = val & GLOBAL_VTU_VID_MASK; 1410 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1411 1412 if (next.valid) { 1413 err = mv88e6xxx_vtu_data_read(chip, &next); 1414 if (err) 1415 return err; 1416 1417 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1418 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); 1419 if (err) 1420 return err; 1421 1422 next.fid = val & GLOBAL_VTU_FID_MASK; 1423 } else if (mv88e6xxx_num_databases(chip) == 256) { 1424 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1425 * VTU DBNum[3:0] are located in VTU Operation 3:0 1426 */ 1427 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); 1428 if (err) 1429 return err; 1430 1431 next.fid = (val & 0xf00) >> 4; 1432 next.fid |= val & 0xf; 1433 } 1434 1435 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1436 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1437 if (err) 1438 return err; 1439 1440 next.sid = val & GLOBAL_VTU_SID_MASK; 1441 } 1442 } 1443 1444 *entry = next; 1445 return 0; 1446 } 1447 1448 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, 1449 struct switchdev_obj_port_vlan *vlan, 1450 int (*cb)(struct switchdev_obj *obj)) 1451 { 1452 struct mv88e6xxx_chip *chip = ds->priv; 1453 struct mv88e6xxx_vtu_entry next; 1454 u16 pvid; 1455 int err; 1456 1457 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1458 return -EOPNOTSUPP; 1459 1460 mutex_lock(&chip->reg_lock); 1461 1462 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1463 if (err) 1464 goto unlock; 1465 1466 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1467 if (err) 1468 goto unlock; 1469 1470 do { 1471 err = _mv88e6xxx_vtu_getnext(chip, &next); 1472 if (err) 1473 break; 1474 1475 if (!next.valid) 1476 break; 1477 1478 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1479 continue; 1480 1481 /* reinit and dump this VLAN obj */ 1482 vlan->vid_begin = next.vid; 1483 vlan->vid_end = next.vid; 1484 vlan->flags = 0; 1485 1486 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) 1487 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1488 1489 if (next.vid == pvid) 1490 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1491 1492 err = cb(&vlan->obj); 1493 if (err) 1494 break; 1495 } while (next.vid < GLOBAL_VTU_VID_MASK); 1496 1497 unlock: 1498 mutex_unlock(&chip->reg_lock); 1499 1500 return err; 1501 } 1502 1503 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1504 struct mv88e6xxx_vtu_entry *entry) 1505 { 1506 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; 1507 u16 reg = 0; 1508 int err; 1509 1510 err = _mv88e6xxx_vtu_wait(chip); 1511 if (err) 1512 return err; 1513 1514 if (!entry->valid) 1515 goto loadpurge; 1516 1517 /* Write port member tags */ 1518 err = mv88e6xxx_vtu_data_write(chip, entry); 1519 if (err) 1520 return err; 1521 1522 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1523 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1524 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1525 if (err) 1526 return err; 1527 } 1528 1529 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1530 reg = entry->fid & GLOBAL_VTU_FID_MASK; 1531 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); 1532 if (err) 1533 return err; 1534 } else if (mv88e6xxx_num_databases(chip) == 256) { 1535 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1536 * VTU DBNum[3:0] are located in VTU Operation 3:0 1537 */ 1538 op |= (entry->fid & 0xf0) << 8; 1539 op |= entry->fid & 0xf; 1540 } 1541 1542 reg = GLOBAL_VTU_VID_VALID; 1543 loadpurge: 1544 reg |= entry->vid & GLOBAL_VTU_VID_MASK; 1545 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1546 if (err) 1547 return err; 1548 1549 return _mv88e6xxx_vtu_cmd(chip, op); 1550 } 1551 1552 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, 1553 struct mv88e6xxx_vtu_entry *entry) 1554 { 1555 struct mv88e6xxx_vtu_entry next = { 0 }; 1556 u16 val; 1557 int err; 1558 1559 err = _mv88e6xxx_vtu_wait(chip); 1560 if (err) 1561 return err; 1562 1563 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, 1564 sid & GLOBAL_VTU_SID_MASK); 1565 if (err) 1566 return err; 1567 1568 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); 1569 if (err) 1570 return err; 1571 1572 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1573 if (err) 1574 return err; 1575 1576 next.sid = val & GLOBAL_VTU_SID_MASK; 1577 1578 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1579 if (err) 1580 return err; 1581 1582 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1583 1584 if (next.valid) { 1585 err = mv88e6xxx_stu_data_read(chip, &next); 1586 if (err) 1587 return err; 1588 } 1589 1590 *entry = next; 1591 return 0; 1592 } 1593 1594 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1595 struct mv88e6xxx_vtu_entry *entry) 1596 { 1597 u16 reg = 0; 1598 int err; 1599 1600 err = _mv88e6xxx_vtu_wait(chip); 1601 if (err) 1602 return err; 1603 1604 if (!entry->valid) 1605 goto loadpurge; 1606 1607 /* Write port states */ 1608 err = mv88e6xxx_stu_data_write(chip, entry); 1609 if (err) 1610 return err; 1611 1612 reg = GLOBAL_VTU_VID_VALID; 1613 loadpurge: 1614 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1615 if (err) 1616 return err; 1617 1618 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1619 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1620 if (err) 1621 return err; 1622 1623 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); 1624 } 1625 1626 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) 1627 { 1628 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1629 struct mv88e6xxx_vtu_entry vlan; 1630 int i, err; 1631 1632 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1633 1634 /* Set every FID bit used by the (un)bridged ports */ 1635 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1636 err = mv88e6xxx_port_get_fid(chip, i, fid); 1637 if (err) 1638 return err; 1639 1640 set_bit(*fid, fid_bitmap); 1641 } 1642 1643 /* Set every FID bit used by the VLAN entries */ 1644 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1645 if (err) 1646 return err; 1647 1648 do { 1649 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1650 if (err) 1651 return err; 1652 1653 if (!vlan.valid) 1654 break; 1655 1656 set_bit(vlan.fid, fid_bitmap); 1657 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 1658 1659 /* The reset value 0x000 is used to indicate that multiple address 1660 * databases are not needed. Return the next positive available. 1661 */ 1662 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1663 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1664 return -ENOSPC; 1665 1666 /* Clear the database */ 1667 return _mv88e6xxx_atu_flush(chip, *fid, true); 1668 } 1669 1670 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, 1671 struct mv88e6xxx_vtu_entry *entry) 1672 { 1673 struct dsa_switch *ds = chip->ds; 1674 struct mv88e6xxx_vtu_entry vlan = { 1675 .valid = true, 1676 .vid = vid, 1677 }; 1678 int i, err; 1679 1680 err = _mv88e6xxx_fid_new(chip, &vlan.fid); 1681 if (err) 1682 return err; 1683 1684 /* exclude all ports except the CPU and DSA ports */ 1685 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1686 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) 1687 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 1688 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1689 1690 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || 1691 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { 1692 struct mv88e6xxx_vtu_entry vstp; 1693 1694 /* Adding a VTU entry requires a valid STU entry. As VSTP is not 1695 * implemented, only one STU entry is needed to cover all VTU 1696 * entries. Thus, validate the SID 0. 1697 */ 1698 vlan.sid = 0; 1699 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); 1700 if (err) 1701 return err; 1702 1703 if (vstp.sid != vlan.sid || !vstp.valid) { 1704 memset(&vstp, 0, sizeof(vstp)); 1705 vstp.valid = true; 1706 vstp.sid = vlan.sid; 1707 1708 err = _mv88e6xxx_stu_loadpurge(chip, &vstp); 1709 if (err) 1710 return err; 1711 } 1712 } 1713 1714 *entry = vlan; 1715 return 0; 1716 } 1717 1718 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1719 struct mv88e6xxx_vtu_entry *entry, bool creat) 1720 { 1721 int err; 1722 1723 if (!vid) 1724 return -EINVAL; 1725 1726 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); 1727 if (err) 1728 return err; 1729 1730 err = _mv88e6xxx_vtu_getnext(chip, entry); 1731 if (err) 1732 return err; 1733 1734 if (entry->vid != vid || !entry->valid) { 1735 if (!creat) 1736 return -EOPNOTSUPP; 1737 /* -ENOENT would've been more appropriate, but switchdev expects 1738 * -EOPNOTSUPP to inform bridge about an eventual software VLAN. 1739 */ 1740 1741 err = _mv88e6xxx_vtu_new(chip, vid, entry); 1742 } 1743 1744 return err; 1745 } 1746 1747 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1748 u16 vid_begin, u16 vid_end) 1749 { 1750 struct mv88e6xxx_chip *chip = ds->priv; 1751 struct mv88e6xxx_vtu_entry vlan; 1752 int i, err; 1753 1754 if (!vid_begin) 1755 return -EOPNOTSUPP; 1756 1757 mutex_lock(&chip->reg_lock); 1758 1759 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); 1760 if (err) 1761 goto unlock; 1762 1763 do { 1764 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1765 if (err) 1766 goto unlock; 1767 1768 if (!vlan.valid) 1769 break; 1770 1771 if (vlan.vid > vid_end) 1772 break; 1773 1774 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1775 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1776 continue; 1777 1778 if (!ds->ports[port].netdev) 1779 continue; 1780 1781 if (vlan.data[i] == 1782 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1783 continue; 1784 1785 if (chip->ports[i].bridge_dev == 1786 chip->ports[port].bridge_dev) 1787 break; /* same bridge, check next VLAN */ 1788 1789 if (!chip->ports[i].bridge_dev) 1790 continue; 1791 1792 netdev_warn(ds->ports[port].netdev, 1793 "hardware VLAN %d already used by %s\n", 1794 vlan.vid, 1795 netdev_name(chip->ports[i].bridge_dev)); 1796 err = -EOPNOTSUPP; 1797 goto unlock; 1798 } 1799 } while (vlan.vid < vid_end); 1800 1801 unlock: 1802 mutex_unlock(&chip->reg_lock); 1803 1804 return err; 1805 } 1806 1807 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1808 bool vlan_filtering) 1809 { 1810 struct mv88e6xxx_chip *chip = ds->priv; 1811 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : 1812 PORT_CONTROL_2_8021Q_DISABLED; 1813 int err; 1814 1815 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1816 return -EOPNOTSUPP; 1817 1818 mutex_lock(&chip->reg_lock); 1819 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1820 mutex_unlock(&chip->reg_lock); 1821 1822 return err; 1823 } 1824 1825 static int 1826 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1827 const struct switchdev_obj_port_vlan *vlan, 1828 struct switchdev_trans *trans) 1829 { 1830 struct mv88e6xxx_chip *chip = ds->priv; 1831 int err; 1832 1833 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1834 return -EOPNOTSUPP; 1835 1836 /* If the requested port doesn't belong to the same bridge as the VLAN 1837 * members, do not support it (yet) and fallback to software VLAN. 1838 */ 1839 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1840 vlan->vid_end); 1841 if (err) 1842 return err; 1843 1844 /* We don't need any dynamic resource from the kernel (yet), 1845 * so skip the prepare phase. 1846 */ 1847 return 0; 1848 } 1849 1850 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1851 u16 vid, bool untagged) 1852 { 1853 struct mv88e6xxx_vtu_entry vlan; 1854 int err; 1855 1856 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1857 if (err) 1858 return err; 1859 1860 vlan.data[port] = untagged ? 1861 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : 1862 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; 1863 1864 return _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1865 } 1866 1867 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1868 const struct switchdev_obj_port_vlan *vlan, 1869 struct switchdev_trans *trans) 1870 { 1871 struct mv88e6xxx_chip *chip = ds->priv; 1872 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1873 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1874 u16 vid; 1875 1876 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1877 return; 1878 1879 mutex_lock(&chip->reg_lock); 1880 1881 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1882 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) 1883 netdev_err(ds->ports[port].netdev, 1884 "failed to add VLAN %d%c\n", 1885 vid, untagged ? 'u' : 't'); 1886 1887 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1888 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", 1889 vlan->vid_end); 1890 1891 mutex_unlock(&chip->reg_lock); 1892 } 1893 1894 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1895 int port, u16 vid) 1896 { 1897 struct dsa_switch *ds = chip->ds; 1898 struct mv88e6xxx_vtu_entry vlan; 1899 int i, err; 1900 1901 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1902 if (err) 1903 return err; 1904 1905 /* Tell switchdev if this VLAN is handled in software */ 1906 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1907 return -EOPNOTSUPP; 1908 1909 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1910 1911 /* keep the VLAN unless all ports are excluded */ 1912 vlan.valid = false; 1913 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1914 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1915 continue; 1916 1917 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1918 vlan.valid = true; 1919 break; 1920 } 1921 } 1922 1923 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1924 if (err) 1925 return err; 1926 1927 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); 1928 } 1929 1930 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1931 const struct switchdev_obj_port_vlan *vlan) 1932 { 1933 struct mv88e6xxx_chip *chip = ds->priv; 1934 u16 pvid, vid; 1935 int err = 0; 1936 1937 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1938 return -EOPNOTSUPP; 1939 1940 mutex_lock(&chip->reg_lock); 1941 1942 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1943 if (err) 1944 goto unlock; 1945 1946 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1947 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1948 if (err) 1949 goto unlock; 1950 1951 if (vid == pvid) { 1952 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1953 if (err) 1954 goto unlock; 1955 } 1956 } 1957 1958 unlock: 1959 mutex_unlock(&chip->reg_lock); 1960 1961 return err; 1962 } 1963 1964 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, 1965 const unsigned char *addr) 1966 { 1967 int i, err; 1968 1969 for (i = 0; i < 3; i++) { 1970 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, 1971 (addr[i * 2] << 8) | addr[i * 2 + 1]); 1972 if (err) 1973 return err; 1974 } 1975 1976 return 0; 1977 } 1978 1979 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, 1980 unsigned char *addr) 1981 { 1982 u16 val; 1983 int i, err; 1984 1985 for (i = 0; i < 3; i++) { 1986 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); 1987 if (err) 1988 return err; 1989 1990 addr[i * 2] = val >> 8; 1991 addr[i * 2 + 1] = val & 0xff; 1992 } 1993 1994 return 0; 1995 } 1996 1997 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, 1998 struct mv88e6xxx_atu_entry *entry) 1999 { 2000 int ret; 2001 2002 ret = _mv88e6xxx_atu_wait(chip); 2003 if (ret < 0) 2004 return ret; 2005 2006 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); 2007 if (ret < 0) 2008 return ret; 2009 2010 ret = _mv88e6xxx_atu_data_write(chip, entry); 2011 if (ret < 0) 2012 return ret; 2013 2014 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); 2015 } 2016 2017 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2018 struct mv88e6xxx_atu_entry *entry); 2019 2020 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, 2021 const u8 *addr, struct mv88e6xxx_atu_entry *entry) 2022 { 2023 struct mv88e6xxx_atu_entry next; 2024 int err; 2025 2026 eth_broadcast_addr(next.mac); 2027 2028 err = _mv88e6xxx_atu_mac_write(chip, next.mac); 2029 if (err) 2030 return err; 2031 2032 do { 2033 err = _mv88e6xxx_atu_getnext(chip, fid, &next); 2034 if (err) 2035 return err; 2036 2037 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2038 break; 2039 2040 if (ether_addr_equal(next.mac, addr)) { 2041 *entry = next; 2042 return 0; 2043 } 2044 } while (!is_broadcast_ether_addr(next.mac)); 2045 2046 memset(entry, 0, sizeof(*entry)); 2047 entry->fid = fid; 2048 ether_addr_copy(entry->mac, addr); 2049 2050 return 0; 2051 } 2052 2053 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2054 const unsigned char *addr, u16 vid, 2055 u8 state) 2056 { 2057 struct mv88e6xxx_vtu_entry vlan; 2058 struct mv88e6xxx_atu_entry entry; 2059 int err; 2060 2061 /* Null VLAN ID corresponds to the port private database */ 2062 if (vid == 0) 2063 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 2064 else 2065 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 2066 if (err) 2067 return err; 2068 2069 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); 2070 if (err) 2071 return err; 2072 2073 /* Purge the ATU entry only if no port is using it anymore */ 2074 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { 2075 entry.portv_trunkid &= ~BIT(port); 2076 if (!entry.portv_trunkid) 2077 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; 2078 } else { 2079 entry.portv_trunkid |= BIT(port); 2080 entry.state = state; 2081 } 2082 2083 return _mv88e6xxx_atu_load(chip, &entry); 2084 } 2085 2086 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 2087 const struct switchdev_obj_port_fdb *fdb, 2088 struct switchdev_trans *trans) 2089 { 2090 /* We don't need any dynamic resource from the kernel (yet), 2091 * so skip the prepare phase. 2092 */ 2093 return 0; 2094 } 2095 2096 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2097 const struct switchdev_obj_port_fdb *fdb, 2098 struct switchdev_trans *trans) 2099 { 2100 struct mv88e6xxx_chip *chip = ds->priv; 2101 2102 mutex_lock(&chip->reg_lock); 2103 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2104 GLOBAL_ATU_DATA_STATE_UC_STATIC)) 2105 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); 2106 mutex_unlock(&chip->reg_lock); 2107 } 2108 2109 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2110 const struct switchdev_obj_port_fdb *fdb) 2111 { 2112 struct mv88e6xxx_chip *chip = ds->priv; 2113 int err; 2114 2115 mutex_lock(&chip->reg_lock); 2116 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2117 GLOBAL_ATU_DATA_STATE_UNUSED); 2118 mutex_unlock(&chip->reg_lock); 2119 2120 return err; 2121 } 2122 2123 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2124 struct mv88e6xxx_atu_entry *entry) 2125 { 2126 struct mv88e6xxx_atu_entry next = { 0 }; 2127 u16 val; 2128 int err; 2129 2130 next.fid = fid; 2131 2132 err = _mv88e6xxx_atu_wait(chip); 2133 if (err) 2134 return err; 2135 2136 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); 2137 if (err) 2138 return err; 2139 2140 err = _mv88e6xxx_atu_mac_read(chip, next.mac); 2141 if (err) 2142 return err; 2143 2144 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); 2145 if (err) 2146 return err; 2147 2148 next.state = val & GLOBAL_ATU_DATA_STATE_MASK; 2149 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { 2150 unsigned int mask, shift; 2151 2152 if (val & GLOBAL_ATU_DATA_TRUNK) { 2153 next.trunk = true; 2154 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 2155 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 2156 } else { 2157 next.trunk = false; 2158 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 2159 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 2160 } 2161 2162 next.portv_trunkid = (val & mask) >> shift; 2163 } 2164 2165 *entry = next; 2166 return 0; 2167 } 2168 2169 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2170 u16 fid, u16 vid, int port, 2171 struct switchdev_obj *obj, 2172 int (*cb)(struct switchdev_obj *obj)) 2173 { 2174 struct mv88e6xxx_atu_entry addr = { 2175 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 2176 }; 2177 int err; 2178 2179 err = _mv88e6xxx_atu_mac_write(chip, addr.mac); 2180 if (err) 2181 return err; 2182 2183 do { 2184 err = _mv88e6xxx_atu_getnext(chip, fid, &addr); 2185 if (err) 2186 return err; 2187 2188 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2189 break; 2190 2191 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) 2192 continue; 2193 2194 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { 2195 struct switchdev_obj_port_fdb *fdb; 2196 2197 if (!is_unicast_ether_addr(addr.mac)) 2198 continue; 2199 2200 fdb = SWITCHDEV_OBJ_PORT_FDB(obj); 2201 fdb->vid = vid; 2202 ether_addr_copy(fdb->addr, addr.mac); 2203 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) 2204 fdb->ndm_state = NUD_NOARP; 2205 else 2206 fdb->ndm_state = NUD_REACHABLE; 2207 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { 2208 struct switchdev_obj_port_mdb *mdb; 2209 2210 if (!is_multicast_ether_addr(addr.mac)) 2211 continue; 2212 2213 mdb = SWITCHDEV_OBJ_PORT_MDB(obj); 2214 mdb->vid = vid; 2215 ether_addr_copy(mdb->addr, addr.mac); 2216 } else { 2217 return -EOPNOTSUPP; 2218 } 2219 2220 err = cb(obj); 2221 if (err) 2222 return err; 2223 } while (!is_broadcast_ether_addr(addr.mac)); 2224 2225 return err; 2226 } 2227 2228 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2229 struct switchdev_obj *obj, 2230 int (*cb)(struct switchdev_obj *obj)) 2231 { 2232 struct mv88e6xxx_vtu_entry vlan = { 2233 .vid = GLOBAL_VTU_VID_MASK, /* all ones */ 2234 }; 2235 u16 fid; 2236 int err; 2237 2238 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2239 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2240 if (err) 2241 return err; 2242 2243 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); 2244 if (err) 2245 return err; 2246 2247 /* Dump VLANs' Filtering Information Databases */ 2248 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); 2249 if (err) 2250 return err; 2251 2252 do { 2253 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 2254 if (err) 2255 return err; 2256 2257 if (!vlan.valid) 2258 break; 2259 2260 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2261 obj, cb); 2262 if (err) 2263 return err; 2264 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 2265 2266 return err; 2267 } 2268 2269 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2270 struct switchdev_obj_port_fdb *fdb, 2271 int (*cb)(struct switchdev_obj *obj)) 2272 { 2273 struct mv88e6xxx_chip *chip = ds->priv; 2274 int err; 2275 2276 mutex_lock(&chip->reg_lock); 2277 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); 2278 mutex_unlock(&chip->reg_lock); 2279 2280 return err; 2281 } 2282 2283 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2284 struct net_device *bridge) 2285 { 2286 struct mv88e6xxx_chip *chip = ds->priv; 2287 int i, err = 0; 2288 2289 mutex_lock(&chip->reg_lock); 2290 2291 /* Assign the bridge and remap each port's VLANTable */ 2292 chip->ports[port].bridge_dev = bridge; 2293 2294 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2295 if (chip->ports[i].bridge_dev == bridge) { 2296 err = _mv88e6xxx_port_based_vlan_map(chip, i); 2297 if (err) 2298 break; 2299 } 2300 } 2301 2302 mutex_unlock(&chip->reg_lock); 2303 2304 return err; 2305 } 2306 2307 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) 2308 { 2309 struct mv88e6xxx_chip *chip = ds->priv; 2310 struct net_device *bridge = chip->ports[port].bridge_dev; 2311 int i; 2312 2313 mutex_lock(&chip->reg_lock); 2314 2315 /* Unassign the bridge and remap each port's VLANTable */ 2316 chip->ports[port].bridge_dev = NULL; 2317 2318 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2319 if (i == port || chip->ports[i].bridge_dev == bridge) 2320 if (_mv88e6xxx_port_based_vlan_map(chip, i)) 2321 netdev_warn(ds->ports[i].netdev, 2322 "failed to remap\n"); 2323 2324 mutex_unlock(&chip->reg_lock); 2325 } 2326 2327 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2328 { 2329 if (chip->info->ops->reset) 2330 return chip->info->ops->reset(chip); 2331 2332 return 0; 2333 } 2334 2335 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2336 { 2337 struct gpio_desc *gpiod = chip->reset; 2338 2339 /* If there is a GPIO connected to the reset pin, toggle it */ 2340 if (gpiod) { 2341 gpiod_set_value_cansleep(gpiod, 1); 2342 usleep_range(10000, 20000); 2343 gpiod_set_value_cansleep(gpiod, 0); 2344 usleep_range(10000, 20000); 2345 } 2346 } 2347 2348 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2349 { 2350 int i, err; 2351 2352 /* Set all ports to the Disabled state */ 2353 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2354 err = mv88e6xxx_port_set_state(chip, i, 2355 PORT_CONTROL_STATE_DISABLED); 2356 if (err) 2357 return err; 2358 } 2359 2360 /* Wait for transmit queues to drain, 2361 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2362 */ 2363 usleep_range(2000, 4000); 2364 2365 return 0; 2366 } 2367 2368 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2369 { 2370 int err; 2371 2372 err = mv88e6xxx_disable_ports(chip); 2373 if (err) 2374 return err; 2375 2376 mv88e6xxx_hardware_reset(chip); 2377 2378 return mv88e6xxx_software_reset(chip); 2379 } 2380 2381 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) 2382 { 2383 u16 val; 2384 int err; 2385 2386 /* Clear Power Down bit */ 2387 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); 2388 if (err) 2389 return err; 2390 2391 if (val & BMCR_PDOWN) { 2392 val &= ~BMCR_PDOWN; 2393 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); 2394 } 2395 2396 return err; 2397 } 2398 2399 static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port, 2400 int upstream_port) 2401 { 2402 int err; 2403 2404 err = chip->info->ops->port_set_frame_mode( 2405 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2406 if (err) 2407 return err; 2408 2409 return chip->info->ops->port_set_egress_unknowns( 2410 chip, port, port == upstream_port); 2411 } 2412 2413 static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port) 2414 { 2415 int err; 2416 2417 switch (chip->info->tag_protocol) { 2418 case DSA_TAG_PROTO_EDSA: 2419 err = chip->info->ops->port_set_frame_mode( 2420 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE); 2421 if (err) 2422 return err; 2423 2424 err = mv88e6xxx_port_set_egress_mode( 2425 chip, port, PORT_CONTROL_EGRESS_ADD_TAG); 2426 if (err) 2427 return err; 2428 2429 if (chip->info->ops->port_set_ether_type) 2430 err = chip->info->ops->port_set_ether_type( 2431 chip, port, ETH_P_EDSA); 2432 break; 2433 2434 case DSA_TAG_PROTO_DSA: 2435 err = chip->info->ops->port_set_frame_mode( 2436 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2437 if (err) 2438 return err; 2439 2440 err = mv88e6xxx_port_set_egress_mode( 2441 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED); 2442 break; 2443 default: 2444 err = -EINVAL; 2445 } 2446 2447 if (err) 2448 return err; 2449 2450 return chip->info->ops->port_set_egress_unknowns(chip, port, true); 2451 } 2452 2453 static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port) 2454 { 2455 int err; 2456 2457 err = chip->info->ops->port_set_frame_mode( 2458 chip, port, MV88E6XXX_FRAME_MODE_NORMAL); 2459 if (err) 2460 return err; 2461 2462 return chip->info->ops->port_set_egress_unknowns(chip, port, false); 2463 } 2464 2465 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2466 { 2467 struct dsa_switch *ds = chip->ds; 2468 int err; 2469 u16 reg; 2470 2471 /* MAC Forcing register: don't force link, speed, duplex or flow control 2472 * state to any particular values on physical ports, but force the CPU 2473 * port and all DSA ports to their maximum bandwidth and full duplex. 2474 */ 2475 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2476 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2477 SPEED_MAX, DUPLEX_FULL, 2478 PHY_INTERFACE_MODE_NA); 2479 else 2480 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2481 SPEED_UNFORCED, DUPLEX_UNFORCED, 2482 PHY_INTERFACE_MODE_NA); 2483 if (err) 2484 return err; 2485 2486 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2487 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2488 * tunneling, determine priority by looking at 802.1p and IP 2489 * priority fields (IP prio has precedence), and set STP state 2490 * to Forwarding. 2491 * 2492 * If this is the CPU link, use DSA or EDSA tagging depending 2493 * on which tagging mode was configured. 2494 * 2495 * If this is a link to another switch, use DSA tagging mode. 2496 * 2497 * If this is the upstream port for this switch, enable 2498 * forwarding of unknown unicasts and multicasts. 2499 */ 2500 reg = PORT_CONTROL_IGMP_MLD_SNOOP | 2501 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | 2502 PORT_CONTROL_STATE_FORWARDING; 2503 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 2504 if (err) 2505 return err; 2506 2507 if (dsa_is_cpu_port(ds, port)) { 2508 err = mv88e6xxx_setup_port_cpu(chip, port); 2509 } else if (dsa_is_dsa_port(ds, port)) { 2510 err = mv88e6xxx_setup_port_dsa(chip, port, 2511 dsa_upstream_port(ds)); 2512 } else { 2513 err = mv88e6xxx_setup_port_normal(chip, port); 2514 } 2515 if (err) 2516 return err; 2517 2518 /* If this port is connected to a SerDes, make sure the SerDes is not 2519 * powered down. 2520 */ 2521 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { 2522 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 2523 if (err) 2524 return err; 2525 reg &= PORT_STATUS_CMODE_MASK; 2526 if ((reg == PORT_STATUS_CMODE_100BASE_X) || 2527 (reg == PORT_STATUS_CMODE_1000BASE_X) || 2528 (reg == PORT_STATUS_CMODE_SGMII)) { 2529 err = mv88e6xxx_serdes_power_on(chip); 2530 if (err < 0) 2531 return err; 2532 } 2533 } 2534 2535 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2536 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2537 * untagged frames on this port, do a destination address lookup on all 2538 * received packets as usual, disable ARP mirroring and don't send a 2539 * copy of all transmitted/received frames on this port to the CPU. 2540 */ 2541 reg = 0; 2542 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2543 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2544 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || 2545 mv88e6xxx_6185_family(chip)) 2546 reg = PORT_CONTROL_2_MAP_DA; 2547 2548 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { 2549 /* Set the upstream port this port should use */ 2550 reg |= dsa_upstream_port(ds); 2551 /* enable forwarding of unknown multicast addresses to 2552 * the upstream port 2553 */ 2554 if (port == dsa_upstream_port(ds)) 2555 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; 2556 } 2557 2558 reg |= PORT_CONTROL_2_8021Q_DISABLED; 2559 2560 if (reg) { 2561 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); 2562 if (err) 2563 return err; 2564 } 2565 2566 if (chip->info->ops->port_jumbo_config) { 2567 err = chip->info->ops->port_jumbo_config(chip, port); 2568 if (err) 2569 return err; 2570 } 2571 2572 /* Port Association Vector: when learning source addresses 2573 * of packets, add the address to the address database using 2574 * a port bitmap that has only the bit for this port set and 2575 * the other bits clear. 2576 */ 2577 reg = 1 << port; 2578 /* Disable learning for CPU port */ 2579 if (dsa_is_cpu_port(ds, port)) 2580 reg = 0; 2581 2582 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); 2583 if (err) 2584 return err; 2585 2586 /* Egress rate control 2: disable egress rate control. */ 2587 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); 2588 if (err) 2589 return err; 2590 2591 if (chip->info->ops->port_pause_config) { 2592 err = chip->info->ops->port_pause_config(chip, port); 2593 if (err) 2594 return err; 2595 } 2596 2597 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2598 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2599 mv88e6xxx_6320_family(chip)) { 2600 /* Port ATU control: disable limiting the number of 2601 * address database entries that this port is allowed 2602 * to use. 2603 */ 2604 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 2605 0x0000); 2606 /* Priority Override: disable DA, SA and VTU priority 2607 * override. 2608 */ 2609 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 2610 0x0000); 2611 if (err) 2612 return err; 2613 } 2614 2615 if (chip->info->ops->port_tag_remap) { 2616 err = chip->info->ops->port_tag_remap(chip, port); 2617 if (err) 2618 return err; 2619 } 2620 2621 if (chip->info->ops->port_egress_rate_limiting) { 2622 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2623 if (err) 2624 return err; 2625 } 2626 2627 /* Port Control 1: disable trunking, disable sending 2628 * learning messages to this port. 2629 */ 2630 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); 2631 if (err) 2632 return err; 2633 2634 /* Port based VLAN map: give each port the same default address 2635 * database, and allow bidirectional communication between the 2636 * CPU and DSA port(s), and the other ports. 2637 */ 2638 err = mv88e6xxx_port_set_fid(chip, port, 0); 2639 if (err) 2640 return err; 2641 2642 err = _mv88e6xxx_port_based_vlan_map(chip, port); 2643 if (err) 2644 return err; 2645 2646 /* Default VLAN ID and priority: don't set a default VLAN 2647 * ID, and set the default packet priority to zero. 2648 */ 2649 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); 2650 } 2651 2652 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 2653 { 2654 int err; 2655 2656 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); 2657 if (err) 2658 return err; 2659 2660 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); 2661 if (err) 2662 return err; 2663 2664 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); 2665 if (err) 2666 return err; 2667 2668 return 0; 2669 } 2670 2671 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, 2672 unsigned int msecs) 2673 { 2674 const unsigned int coeff = chip->info->age_time_coeff; 2675 const unsigned int min = 0x01 * coeff; 2676 const unsigned int max = 0xff * coeff; 2677 u8 age_time; 2678 u16 val; 2679 int err; 2680 2681 if (msecs < min || msecs > max) 2682 return -ERANGE; 2683 2684 /* Round to nearest multiple of coeff */ 2685 age_time = (msecs + coeff / 2) / coeff; 2686 2687 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 2688 if (err) 2689 return err; 2690 2691 /* AgeTime is 11:4 bits */ 2692 val &= ~0xff0; 2693 val |= age_time << 4; 2694 2695 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); 2696 } 2697 2698 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2699 unsigned int ageing_time) 2700 { 2701 struct mv88e6xxx_chip *chip = ds->priv; 2702 int err; 2703 2704 mutex_lock(&chip->reg_lock); 2705 err = mv88e6xxx_g1_set_age_time(chip, ageing_time); 2706 mutex_unlock(&chip->reg_lock); 2707 2708 return err; 2709 } 2710 2711 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2712 { 2713 struct dsa_switch *ds = chip->ds; 2714 u32 upstream_port = dsa_upstream_port(ds); 2715 int err; 2716 2717 /* Enable the PHY Polling Unit if present, don't discard any packets, 2718 * and mask all interrupt sources. 2719 */ 2720 err = mv88e6xxx_ppu_enable(chip); 2721 if (err) 2722 return err; 2723 2724 if (chip->info->ops->g1_set_cpu_port) { 2725 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port); 2726 if (err) 2727 return err; 2728 } 2729 2730 if (chip->info->ops->g1_set_egress_port) { 2731 err = chip->info->ops->g1_set_egress_port(chip, upstream_port); 2732 if (err) 2733 return err; 2734 } 2735 2736 /* Disable remote management, and set the switch's DSA device number. */ 2737 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, 2738 GLOBAL_CONTROL_2_MULTIPLE_CASCADE | 2739 (ds->index & 0x1f)); 2740 if (err) 2741 return err; 2742 2743 /* Clear all the VTU and STU entries */ 2744 err = _mv88e6xxx_vtu_stu_flush(chip); 2745 if (err < 0) 2746 return err; 2747 2748 /* Set the default address aging time to 5 minutes, and 2749 * enable address learn messages to be sent to all message 2750 * ports. 2751 */ 2752 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 2753 GLOBAL_ATU_CONTROL_LEARN2ALL); 2754 if (err) 2755 return err; 2756 2757 err = mv88e6xxx_g1_set_age_time(chip, 300000); 2758 if (err) 2759 return err; 2760 2761 /* Clear all ATU entries */ 2762 err = _mv88e6xxx_atu_flush(chip, 0, true); 2763 if (err) 2764 return err; 2765 2766 /* Configure the IP ToS mapping registers. */ 2767 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); 2768 if (err) 2769 return err; 2770 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); 2771 if (err) 2772 return err; 2773 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); 2774 if (err) 2775 return err; 2776 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); 2777 if (err) 2778 return err; 2779 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); 2780 if (err) 2781 return err; 2782 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); 2783 if (err) 2784 return err; 2785 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); 2786 if (err) 2787 return err; 2788 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); 2789 if (err) 2790 return err; 2791 2792 /* Configure the IEEE 802.1p priority mapping register. */ 2793 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); 2794 if (err) 2795 return err; 2796 2797 /* Initialize the statistics unit */ 2798 err = mv88e6xxx_stats_set_histogram(chip); 2799 if (err) 2800 return err; 2801 2802 /* Clear the statistics counters for all ports */ 2803 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 2804 GLOBAL_STATS_OP_FLUSH_ALL); 2805 if (err) 2806 return err; 2807 2808 /* Wait for the flush to complete. */ 2809 err = mv88e6xxx_g1_stats_wait(chip); 2810 if (err) 2811 return err; 2812 2813 return 0; 2814 } 2815 2816 static int mv88e6xxx_setup(struct dsa_switch *ds) 2817 { 2818 struct mv88e6xxx_chip *chip = ds->priv; 2819 int err; 2820 int i; 2821 2822 chip->ds = ds; 2823 ds->slave_mii_bus = chip->mdio_bus; 2824 2825 mutex_lock(&chip->reg_lock); 2826 2827 /* Setup Switch Port Registers */ 2828 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2829 err = mv88e6xxx_setup_port(chip, i); 2830 if (err) 2831 goto unlock; 2832 } 2833 2834 /* Setup Switch Global 1 Registers */ 2835 err = mv88e6xxx_g1_setup(chip); 2836 if (err) 2837 goto unlock; 2838 2839 /* Setup Switch Global 2 Registers */ 2840 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 2841 err = mv88e6xxx_g2_setup(chip); 2842 if (err) 2843 goto unlock; 2844 } 2845 2846 /* Some generations have the configuration of sending reserved 2847 * management frames to the CPU in global2, others in 2848 * global1. Hence it does not fit the two setup functions 2849 * above. 2850 */ 2851 if (chip->info->ops->mgmt_rsvd2cpu) { 2852 err = chip->info->ops->mgmt_rsvd2cpu(chip); 2853 if (err) 2854 goto unlock; 2855 } 2856 2857 unlock: 2858 mutex_unlock(&chip->reg_lock); 2859 2860 return err; 2861 } 2862 2863 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2864 { 2865 struct mv88e6xxx_chip *chip = ds->priv; 2866 int err; 2867 2868 if (!chip->info->ops->set_switch_mac) 2869 return -EOPNOTSUPP; 2870 2871 mutex_lock(&chip->reg_lock); 2872 err = chip->info->ops->set_switch_mac(chip, addr); 2873 mutex_unlock(&chip->reg_lock); 2874 2875 return err; 2876 } 2877 2878 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2879 { 2880 struct mv88e6xxx_chip *chip = bus->priv; 2881 u16 val; 2882 int err; 2883 2884 if (phy >= mv88e6xxx_num_ports(chip)) 2885 return 0xffff; 2886 2887 mutex_lock(&chip->reg_lock); 2888 err = mv88e6xxx_phy_read(chip, phy, reg, &val); 2889 mutex_unlock(&chip->reg_lock); 2890 2891 return err ? err : val; 2892 } 2893 2894 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2895 { 2896 struct mv88e6xxx_chip *chip = bus->priv; 2897 int err; 2898 2899 if (phy >= mv88e6xxx_num_ports(chip)) 2900 return 0xffff; 2901 2902 mutex_lock(&chip->reg_lock); 2903 err = mv88e6xxx_phy_write(chip, phy, reg, val); 2904 mutex_unlock(&chip->reg_lock); 2905 2906 return err; 2907 } 2908 2909 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2910 struct device_node *np) 2911 { 2912 static int index; 2913 struct mii_bus *bus; 2914 int err; 2915 2916 if (np) 2917 chip->mdio_np = of_get_child_by_name(np, "mdio"); 2918 2919 bus = devm_mdiobus_alloc(chip->dev); 2920 if (!bus) 2921 return -ENOMEM; 2922 2923 bus->priv = (void *)chip; 2924 if (np) { 2925 bus->name = np->full_name; 2926 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 2927 } else { 2928 bus->name = "mv88e6xxx SMI"; 2929 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2930 } 2931 2932 bus->read = mv88e6xxx_mdio_read; 2933 bus->write = mv88e6xxx_mdio_write; 2934 bus->parent = chip->dev; 2935 2936 if (chip->mdio_np) 2937 err = of_mdiobus_register(bus, chip->mdio_np); 2938 else 2939 err = mdiobus_register(bus); 2940 if (err) { 2941 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2942 goto out; 2943 } 2944 chip->mdio_bus = bus; 2945 2946 return 0; 2947 2948 out: 2949 if (chip->mdio_np) 2950 of_node_put(chip->mdio_np); 2951 2952 return err; 2953 } 2954 2955 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) 2956 2957 { 2958 struct mii_bus *bus = chip->mdio_bus; 2959 2960 mdiobus_unregister(bus); 2961 2962 if (chip->mdio_np) 2963 of_node_put(chip->mdio_np); 2964 } 2965 2966 #ifdef CONFIG_NET_DSA_HWMON 2967 2968 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) 2969 { 2970 struct mv88e6xxx_chip *chip = ds->priv; 2971 u16 val; 2972 int ret; 2973 2974 *temp = 0; 2975 2976 mutex_lock(&chip->reg_lock); 2977 2978 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); 2979 if (ret < 0) 2980 goto error; 2981 2982 /* Enable temperature sensor */ 2983 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 2984 if (ret < 0) 2985 goto error; 2986 2987 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); 2988 if (ret < 0) 2989 goto error; 2990 2991 /* Wait for temperature to stabilize */ 2992 usleep_range(10000, 12000); 2993 2994 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 2995 if (ret < 0) 2996 goto error; 2997 2998 /* Disable temperature sensor */ 2999 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); 3000 if (ret < 0) 3001 goto error; 3002 3003 *temp = ((val & 0x1f) - 5) * 5; 3004 3005 error: 3006 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); 3007 mutex_unlock(&chip->reg_lock); 3008 return ret; 3009 } 3010 3011 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) 3012 { 3013 struct mv88e6xxx_chip *chip = ds->priv; 3014 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3015 u16 val; 3016 int ret; 3017 3018 *temp = 0; 3019 3020 mutex_lock(&chip->reg_lock); 3021 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); 3022 mutex_unlock(&chip->reg_lock); 3023 if (ret < 0) 3024 return ret; 3025 3026 *temp = (val & 0xff) - 25; 3027 3028 return 0; 3029 } 3030 3031 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) 3032 { 3033 struct mv88e6xxx_chip *chip = ds->priv; 3034 3035 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) 3036 return -EOPNOTSUPP; 3037 3038 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) 3039 return mv88e63xx_get_temp(ds, temp); 3040 3041 return mv88e61xx_get_temp(ds, temp); 3042 } 3043 3044 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) 3045 { 3046 struct mv88e6xxx_chip *chip = ds->priv; 3047 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3048 u16 val; 3049 int ret; 3050 3051 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3052 return -EOPNOTSUPP; 3053 3054 *temp = 0; 3055 3056 mutex_lock(&chip->reg_lock); 3057 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3058 mutex_unlock(&chip->reg_lock); 3059 if (ret < 0) 3060 return ret; 3061 3062 *temp = (((val >> 8) & 0x1f) * 5) - 25; 3063 3064 return 0; 3065 } 3066 3067 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) 3068 { 3069 struct mv88e6xxx_chip *chip = ds->priv; 3070 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3071 u16 val; 3072 int err; 3073 3074 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3075 return -EOPNOTSUPP; 3076 3077 mutex_lock(&chip->reg_lock); 3078 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3079 if (err) 3080 goto unlock; 3081 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); 3082 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, 3083 (val & 0xe0ff) | (temp << 8)); 3084 unlock: 3085 mutex_unlock(&chip->reg_lock); 3086 3087 return err; 3088 } 3089 3090 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) 3091 { 3092 struct mv88e6xxx_chip *chip = ds->priv; 3093 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3094 u16 val; 3095 int ret; 3096 3097 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3098 return -EOPNOTSUPP; 3099 3100 *alarm = false; 3101 3102 mutex_lock(&chip->reg_lock); 3103 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3104 mutex_unlock(&chip->reg_lock); 3105 if (ret < 0) 3106 return ret; 3107 3108 *alarm = !!(val & 0x40); 3109 3110 return 0; 3111 } 3112 #endif /* CONFIG_NET_DSA_HWMON */ 3113 3114 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3115 { 3116 struct mv88e6xxx_chip *chip = ds->priv; 3117 3118 return chip->eeprom_len; 3119 } 3120 3121 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3122 struct ethtool_eeprom *eeprom, u8 *data) 3123 { 3124 struct mv88e6xxx_chip *chip = ds->priv; 3125 int err; 3126 3127 if (!chip->info->ops->get_eeprom) 3128 return -EOPNOTSUPP; 3129 3130 mutex_lock(&chip->reg_lock); 3131 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3132 mutex_unlock(&chip->reg_lock); 3133 3134 if (err) 3135 return err; 3136 3137 eeprom->magic = 0xc3ec4951; 3138 3139 return 0; 3140 } 3141 3142 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3143 struct ethtool_eeprom *eeprom, u8 *data) 3144 { 3145 struct mv88e6xxx_chip *chip = ds->priv; 3146 int err; 3147 3148 if (!chip->info->ops->set_eeprom) 3149 return -EOPNOTSUPP; 3150 3151 if (eeprom->magic != 0xc3ec4951) 3152 return -EINVAL; 3153 3154 mutex_lock(&chip->reg_lock); 3155 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3156 mutex_unlock(&chip->reg_lock); 3157 3158 return err; 3159 } 3160 3161 static const struct mv88e6xxx_ops mv88e6085_ops = { 3162 /* MV88E6XXX_FAMILY_6097 */ 3163 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3164 .phy_read = mv88e6xxx_phy_ppu_read, 3165 .phy_write = mv88e6xxx_phy_ppu_write, 3166 .port_set_link = mv88e6xxx_port_set_link, 3167 .port_set_duplex = mv88e6xxx_port_set_duplex, 3168 .port_set_speed = mv88e6185_port_set_speed, 3169 .port_tag_remap = mv88e6095_port_tag_remap, 3170 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3171 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3172 .port_set_ether_type = mv88e6351_port_set_ether_type, 3173 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3174 .port_pause_config = mv88e6097_port_pause_config, 3175 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3176 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3177 .stats_get_strings = mv88e6095_stats_get_strings, 3178 .stats_get_stats = mv88e6095_stats_get_stats, 3179 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3180 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3181 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3182 .ppu_enable = mv88e6185_g1_ppu_enable, 3183 .ppu_disable = mv88e6185_g1_ppu_disable, 3184 .reset = mv88e6185_g1_reset, 3185 }; 3186 3187 static const struct mv88e6xxx_ops mv88e6095_ops = { 3188 /* MV88E6XXX_FAMILY_6095 */ 3189 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3190 .phy_read = mv88e6xxx_phy_ppu_read, 3191 .phy_write = mv88e6xxx_phy_ppu_write, 3192 .port_set_link = mv88e6xxx_port_set_link, 3193 .port_set_duplex = mv88e6xxx_port_set_duplex, 3194 .port_set_speed = mv88e6185_port_set_speed, 3195 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3196 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3197 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3198 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3199 .stats_get_strings = mv88e6095_stats_get_strings, 3200 .stats_get_stats = mv88e6095_stats_get_stats, 3201 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3202 .ppu_enable = mv88e6185_g1_ppu_enable, 3203 .ppu_disable = mv88e6185_g1_ppu_disable, 3204 .reset = mv88e6185_g1_reset, 3205 }; 3206 3207 static const struct mv88e6xxx_ops mv88e6097_ops = { 3208 /* MV88E6XXX_FAMILY_6097 */ 3209 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3210 .phy_read = mv88e6xxx_g2_smi_phy_read, 3211 .phy_write = mv88e6xxx_g2_smi_phy_write, 3212 .port_set_link = mv88e6xxx_port_set_link, 3213 .port_set_duplex = mv88e6xxx_port_set_duplex, 3214 .port_set_speed = mv88e6185_port_set_speed, 3215 .port_tag_remap = mv88e6095_port_tag_remap, 3216 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3217 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3218 .port_set_ether_type = mv88e6351_port_set_ether_type, 3219 .port_jumbo_config = mv88e6165_port_jumbo_config, 3220 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3221 .port_pause_config = mv88e6097_port_pause_config, 3222 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3223 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3224 .stats_get_strings = mv88e6095_stats_get_strings, 3225 .stats_get_stats = mv88e6095_stats_get_stats, 3226 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3227 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3228 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3229 .reset = mv88e6352_g1_reset, 3230 }; 3231 3232 static const struct mv88e6xxx_ops mv88e6123_ops = { 3233 /* MV88E6XXX_FAMILY_6165 */ 3234 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3235 .phy_read = mv88e6xxx_read, 3236 .phy_write = mv88e6xxx_write, 3237 .port_set_link = mv88e6xxx_port_set_link, 3238 .port_set_duplex = mv88e6xxx_port_set_duplex, 3239 .port_set_speed = mv88e6185_port_set_speed, 3240 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3241 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3242 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3243 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3244 .stats_get_strings = mv88e6095_stats_get_strings, 3245 .stats_get_stats = mv88e6095_stats_get_stats, 3246 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3247 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3248 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3249 .reset = mv88e6352_g1_reset, 3250 }; 3251 3252 static const struct mv88e6xxx_ops mv88e6131_ops = { 3253 /* MV88E6XXX_FAMILY_6185 */ 3254 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3255 .phy_read = mv88e6xxx_phy_ppu_read, 3256 .phy_write = mv88e6xxx_phy_ppu_write, 3257 .port_set_link = mv88e6xxx_port_set_link, 3258 .port_set_duplex = mv88e6xxx_port_set_duplex, 3259 .port_set_speed = mv88e6185_port_set_speed, 3260 .port_tag_remap = mv88e6095_port_tag_remap, 3261 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3262 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3263 .port_set_ether_type = mv88e6351_port_set_ether_type, 3264 .port_jumbo_config = mv88e6165_port_jumbo_config, 3265 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3266 .port_pause_config = mv88e6097_port_pause_config, 3267 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3268 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3269 .stats_get_strings = mv88e6095_stats_get_strings, 3270 .stats_get_stats = mv88e6095_stats_get_stats, 3271 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3272 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3273 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3274 .ppu_enable = mv88e6185_g1_ppu_enable, 3275 .ppu_disable = mv88e6185_g1_ppu_disable, 3276 .reset = mv88e6185_g1_reset, 3277 }; 3278 3279 static const struct mv88e6xxx_ops mv88e6161_ops = { 3280 /* MV88E6XXX_FAMILY_6165 */ 3281 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3282 .phy_read = mv88e6xxx_read, 3283 .phy_write = mv88e6xxx_write, 3284 .port_set_link = mv88e6xxx_port_set_link, 3285 .port_set_duplex = mv88e6xxx_port_set_duplex, 3286 .port_set_speed = mv88e6185_port_set_speed, 3287 .port_tag_remap = mv88e6095_port_tag_remap, 3288 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3289 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3290 .port_set_ether_type = mv88e6351_port_set_ether_type, 3291 .port_jumbo_config = mv88e6165_port_jumbo_config, 3292 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3293 .port_pause_config = mv88e6097_port_pause_config, 3294 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3295 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3296 .stats_get_strings = mv88e6095_stats_get_strings, 3297 .stats_get_stats = mv88e6095_stats_get_stats, 3298 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3299 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3300 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3301 .reset = mv88e6352_g1_reset, 3302 }; 3303 3304 static const struct mv88e6xxx_ops mv88e6165_ops = { 3305 /* MV88E6XXX_FAMILY_6165 */ 3306 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3307 .phy_read = mv88e6xxx_read, 3308 .phy_write = mv88e6xxx_write, 3309 .port_set_link = mv88e6xxx_port_set_link, 3310 .port_set_duplex = mv88e6xxx_port_set_duplex, 3311 .port_set_speed = mv88e6185_port_set_speed, 3312 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3313 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3314 .stats_get_strings = mv88e6095_stats_get_strings, 3315 .stats_get_stats = mv88e6095_stats_get_stats, 3316 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3317 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3318 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3319 .reset = mv88e6352_g1_reset, 3320 }; 3321 3322 static const struct mv88e6xxx_ops mv88e6171_ops = { 3323 /* MV88E6XXX_FAMILY_6351 */ 3324 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3325 .phy_read = mv88e6xxx_g2_smi_phy_read, 3326 .phy_write = mv88e6xxx_g2_smi_phy_write, 3327 .port_set_link = mv88e6xxx_port_set_link, 3328 .port_set_duplex = mv88e6xxx_port_set_duplex, 3329 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3330 .port_set_speed = mv88e6185_port_set_speed, 3331 .port_tag_remap = mv88e6095_port_tag_remap, 3332 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3333 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3334 .port_set_ether_type = mv88e6351_port_set_ether_type, 3335 .port_jumbo_config = mv88e6165_port_jumbo_config, 3336 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3337 .port_pause_config = mv88e6097_port_pause_config, 3338 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3339 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3340 .stats_get_strings = mv88e6095_stats_get_strings, 3341 .stats_get_stats = mv88e6095_stats_get_stats, 3342 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3343 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3344 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3345 .reset = mv88e6352_g1_reset, 3346 }; 3347 3348 static const struct mv88e6xxx_ops mv88e6172_ops = { 3349 /* MV88E6XXX_FAMILY_6352 */ 3350 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3351 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3352 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3353 .phy_read = mv88e6xxx_g2_smi_phy_read, 3354 .phy_write = mv88e6xxx_g2_smi_phy_write, 3355 .port_set_link = mv88e6xxx_port_set_link, 3356 .port_set_duplex = mv88e6xxx_port_set_duplex, 3357 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3358 .port_set_speed = mv88e6352_port_set_speed, 3359 .port_tag_remap = mv88e6095_port_tag_remap, 3360 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3361 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3362 .port_set_ether_type = mv88e6351_port_set_ether_type, 3363 .port_jumbo_config = mv88e6165_port_jumbo_config, 3364 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3365 .port_pause_config = mv88e6097_port_pause_config, 3366 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3367 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3368 .stats_get_strings = mv88e6095_stats_get_strings, 3369 .stats_get_stats = mv88e6095_stats_get_stats, 3370 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3371 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3372 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3373 .reset = mv88e6352_g1_reset, 3374 }; 3375 3376 static const struct mv88e6xxx_ops mv88e6175_ops = { 3377 /* MV88E6XXX_FAMILY_6351 */ 3378 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3379 .phy_read = mv88e6xxx_g2_smi_phy_read, 3380 .phy_write = mv88e6xxx_g2_smi_phy_write, 3381 .port_set_link = mv88e6xxx_port_set_link, 3382 .port_set_duplex = mv88e6xxx_port_set_duplex, 3383 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3384 .port_set_speed = mv88e6185_port_set_speed, 3385 .port_tag_remap = mv88e6095_port_tag_remap, 3386 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3387 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3388 .port_set_ether_type = mv88e6351_port_set_ether_type, 3389 .port_jumbo_config = mv88e6165_port_jumbo_config, 3390 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3391 .port_pause_config = mv88e6097_port_pause_config, 3392 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3393 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3394 .stats_get_strings = mv88e6095_stats_get_strings, 3395 .stats_get_stats = mv88e6095_stats_get_stats, 3396 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3397 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3398 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3399 .reset = mv88e6352_g1_reset, 3400 }; 3401 3402 static const struct mv88e6xxx_ops mv88e6176_ops = { 3403 /* MV88E6XXX_FAMILY_6352 */ 3404 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3405 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3406 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3407 .phy_read = mv88e6xxx_g2_smi_phy_read, 3408 .phy_write = mv88e6xxx_g2_smi_phy_write, 3409 .port_set_link = mv88e6xxx_port_set_link, 3410 .port_set_duplex = mv88e6xxx_port_set_duplex, 3411 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3412 .port_set_speed = mv88e6352_port_set_speed, 3413 .port_tag_remap = mv88e6095_port_tag_remap, 3414 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3415 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3416 .port_set_ether_type = mv88e6351_port_set_ether_type, 3417 .port_jumbo_config = mv88e6165_port_jumbo_config, 3418 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3419 .port_pause_config = mv88e6097_port_pause_config, 3420 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3421 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3422 .stats_get_strings = mv88e6095_stats_get_strings, 3423 .stats_get_stats = mv88e6095_stats_get_stats, 3424 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3425 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3426 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3427 .reset = mv88e6352_g1_reset, 3428 }; 3429 3430 static const struct mv88e6xxx_ops mv88e6185_ops = { 3431 /* MV88E6XXX_FAMILY_6185 */ 3432 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3433 .phy_read = mv88e6xxx_phy_ppu_read, 3434 .phy_write = mv88e6xxx_phy_ppu_write, 3435 .port_set_link = mv88e6xxx_port_set_link, 3436 .port_set_duplex = mv88e6xxx_port_set_duplex, 3437 .port_set_speed = mv88e6185_port_set_speed, 3438 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3439 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3440 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3441 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3442 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3443 .stats_get_strings = mv88e6095_stats_get_strings, 3444 .stats_get_stats = mv88e6095_stats_get_stats, 3445 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3446 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3447 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3448 .ppu_enable = mv88e6185_g1_ppu_enable, 3449 .ppu_disable = mv88e6185_g1_ppu_disable, 3450 .reset = mv88e6185_g1_reset, 3451 }; 3452 3453 static const struct mv88e6xxx_ops mv88e6190_ops = { 3454 /* MV88E6XXX_FAMILY_6390 */ 3455 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3456 .phy_read = mv88e6xxx_g2_smi_phy_read, 3457 .phy_write = mv88e6xxx_g2_smi_phy_write, 3458 .port_set_link = mv88e6xxx_port_set_link, 3459 .port_set_duplex = mv88e6xxx_port_set_duplex, 3460 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3461 .port_set_speed = mv88e6390_port_set_speed, 3462 .port_tag_remap = mv88e6390_port_tag_remap, 3463 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3464 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3465 .port_set_ether_type = mv88e6351_port_set_ether_type, 3466 .port_pause_config = mv88e6390_port_pause_config, 3467 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3468 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3469 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3470 .stats_get_strings = mv88e6320_stats_get_strings, 3471 .stats_get_stats = mv88e6390_stats_get_stats, 3472 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3473 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3474 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3475 .reset = mv88e6352_g1_reset, 3476 }; 3477 3478 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3479 /* MV88E6XXX_FAMILY_6390 */ 3480 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3481 .phy_read = mv88e6xxx_g2_smi_phy_read, 3482 .phy_write = mv88e6xxx_g2_smi_phy_write, 3483 .port_set_link = mv88e6xxx_port_set_link, 3484 .port_set_duplex = mv88e6xxx_port_set_duplex, 3485 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3486 .port_set_speed = mv88e6390x_port_set_speed, 3487 .port_tag_remap = mv88e6390_port_tag_remap, 3488 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3489 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3490 .port_set_ether_type = mv88e6351_port_set_ether_type, 3491 .port_pause_config = mv88e6390_port_pause_config, 3492 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3493 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3494 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3495 .stats_get_strings = mv88e6320_stats_get_strings, 3496 .stats_get_stats = mv88e6390_stats_get_stats, 3497 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3498 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3499 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3500 .reset = mv88e6352_g1_reset, 3501 }; 3502 3503 static const struct mv88e6xxx_ops mv88e6191_ops = { 3504 /* MV88E6XXX_FAMILY_6390 */ 3505 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3506 .phy_read = mv88e6xxx_g2_smi_phy_read, 3507 .phy_write = mv88e6xxx_g2_smi_phy_write, 3508 .port_set_link = mv88e6xxx_port_set_link, 3509 .port_set_duplex = mv88e6xxx_port_set_duplex, 3510 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3511 .port_set_speed = mv88e6390_port_set_speed, 3512 .port_tag_remap = mv88e6390_port_tag_remap, 3513 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3514 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3515 .port_set_ether_type = mv88e6351_port_set_ether_type, 3516 .port_pause_config = mv88e6390_port_pause_config, 3517 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3518 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3519 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3520 .stats_get_strings = mv88e6320_stats_get_strings, 3521 .stats_get_stats = mv88e6390_stats_get_stats, 3522 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3523 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3524 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3525 .reset = mv88e6352_g1_reset, 3526 }; 3527 3528 static const struct mv88e6xxx_ops mv88e6240_ops = { 3529 /* MV88E6XXX_FAMILY_6352 */ 3530 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3531 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3532 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3533 .phy_read = mv88e6xxx_g2_smi_phy_read, 3534 .phy_write = mv88e6xxx_g2_smi_phy_write, 3535 .port_set_link = mv88e6xxx_port_set_link, 3536 .port_set_duplex = mv88e6xxx_port_set_duplex, 3537 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3538 .port_set_speed = mv88e6352_port_set_speed, 3539 .port_tag_remap = mv88e6095_port_tag_remap, 3540 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3541 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3542 .port_set_ether_type = mv88e6351_port_set_ether_type, 3543 .port_jumbo_config = mv88e6165_port_jumbo_config, 3544 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3545 .port_pause_config = mv88e6097_port_pause_config, 3546 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3547 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3548 .stats_get_strings = mv88e6095_stats_get_strings, 3549 .stats_get_stats = mv88e6095_stats_get_stats, 3550 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3551 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3552 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3553 .reset = mv88e6352_g1_reset, 3554 }; 3555 3556 static const struct mv88e6xxx_ops mv88e6290_ops = { 3557 /* MV88E6XXX_FAMILY_6390 */ 3558 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3559 .phy_read = mv88e6xxx_g2_smi_phy_read, 3560 .phy_write = mv88e6xxx_g2_smi_phy_write, 3561 .port_set_link = mv88e6xxx_port_set_link, 3562 .port_set_duplex = mv88e6xxx_port_set_duplex, 3563 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3564 .port_set_speed = mv88e6390_port_set_speed, 3565 .port_tag_remap = mv88e6390_port_tag_remap, 3566 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3567 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3568 .port_set_ether_type = mv88e6351_port_set_ether_type, 3569 .port_pause_config = mv88e6390_port_pause_config, 3570 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3571 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3572 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3573 .stats_get_strings = mv88e6320_stats_get_strings, 3574 .stats_get_stats = mv88e6390_stats_get_stats, 3575 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3576 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3577 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3578 .reset = mv88e6352_g1_reset, 3579 }; 3580 3581 static const struct mv88e6xxx_ops mv88e6320_ops = { 3582 /* MV88E6XXX_FAMILY_6320 */ 3583 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3584 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3585 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3586 .phy_read = mv88e6xxx_g2_smi_phy_read, 3587 .phy_write = mv88e6xxx_g2_smi_phy_write, 3588 .port_set_link = mv88e6xxx_port_set_link, 3589 .port_set_duplex = mv88e6xxx_port_set_duplex, 3590 .port_set_speed = mv88e6185_port_set_speed, 3591 .port_tag_remap = mv88e6095_port_tag_remap, 3592 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3593 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3594 .port_set_ether_type = mv88e6351_port_set_ether_type, 3595 .port_jumbo_config = mv88e6165_port_jumbo_config, 3596 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3597 .port_pause_config = mv88e6097_port_pause_config, 3598 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3599 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3600 .stats_get_strings = mv88e6320_stats_get_strings, 3601 .stats_get_stats = mv88e6320_stats_get_stats, 3602 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3603 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3604 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3605 .reset = mv88e6352_g1_reset, 3606 }; 3607 3608 static const struct mv88e6xxx_ops mv88e6321_ops = { 3609 /* MV88E6XXX_FAMILY_6321 */ 3610 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3611 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3612 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3613 .phy_read = mv88e6xxx_g2_smi_phy_read, 3614 .phy_write = mv88e6xxx_g2_smi_phy_write, 3615 .port_set_link = mv88e6xxx_port_set_link, 3616 .port_set_duplex = mv88e6xxx_port_set_duplex, 3617 .port_set_speed = mv88e6185_port_set_speed, 3618 .port_tag_remap = mv88e6095_port_tag_remap, 3619 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3620 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3621 .port_set_ether_type = mv88e6351_port_set_ether_type, 3622 .port_jumbo_config = mv88e6165_port_jumbo_config, 3623 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3624 .port_pause_config = mv88e6097_port_pause_config, 3625 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3626 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3627 .stats_get_strings = mv88e6320_stats_get_strings, 3628 .stats_get_stats = mv88e6320_stats_get_stats, 3629 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3630 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3631 .reset = mv88e6352_g1_reset, 3632 }; 3633 3634 static const struct mv88e6xxx_ops mv88e6350_ops = { 3635 /* MV88E6XXX_FAMILY_6351 */ 3636 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3637 .phy_read = mv88e6xxx_g2_smi_phy_read, 3638 .phy_write = mv88e6xxx_g2_smi_phy_write, 3639 .port_set_link = mv88e6xxx_port_set_link, 3640 .port_set_duplex = mv88e6xxx_port_set_duplex, 3641 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3642 .port_set_speed = mv88e6185_port_set_speed, 3643 .port_tag_remap = mv88e6095_port_tag_remap, 3644 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3645 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3646 .port_set_ether_type = mv88e6351_port_set_ether_type, 3647 .port_jumbo_config = mv88e6165_port_jumbo_config, 3648 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3649 .port_pause_config = mv88e6097_port_pause_config, 3650 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3651 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3652 .stats_get_strings = mv88e6095_stats_get_strings, 3653 .stats_get_stats = mv88e6095_stats_get_stats, 3654 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3655 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3656 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3657 .reset = mv88e6352_g1_reset, 3658 }; 3659 3660 static const struct mv88e6xxx_ops mv88e6351_ops = { 3661 /* MV88E6XXX_FAMILY_6351 */ 3662 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3663 .phy_read = mv88e6xxx_g2_smi_phy_read, 3664 .phy_write = mv88e6xxx_g2_smi_phy_write, 3665 .port_set_link = mv88e6xxx_port_set_link, 3666 .port_set_duplex = mv88e6xxx_port_set_duplex, 3667 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3668 .port_set_speed = mv88e6185_port_set_speed, 3669 .port_tag_remap = mv88e6095_port_tag_remap, 3670 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3671 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3672 .port_set_ether_type = mv88e6351_port_set_ether_type, 3673 .port_jumbo_config = mv88e6165_port_jumbo_config, 3674 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3675 .port_pause_config = mv88e6097_port_pause_config, 3676 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3677 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3678 .stats_get_strings = mv88e6095_stats_get_strings, 3679 .stats_get_stats = mv88e6095_stats_get_stats, 3680 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3681 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3682 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3683 .reset = mv88e6352_g1_reset, 3684 }; 3685 3686 static const struct mv88e6xxx_ops mv88e6352_ops = { 3687 /* MV88E6XXX_FAMILY_6352 */ 3688 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3689 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3690 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3691 .phy_read = mv88e6xxx_g2_smi_phy_read, 3692 .phy_write = mv88e6xxx_g2_smi_phy_write, 3693 .port_set_link = mv88e6xxx_port_set_link, 3694 .port_set_duplex = mv88e6xxx_port_set_duplex, 3695 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3696 .port_set_speed = mv88e6352_port_set_speed, 3697 .port_tag_remap = mv88e6095_port_tag_remap, 3698 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3699 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3700 .port_set_ether_type = mv88e6351_port_set_ether_type, 3701 .port_jumbo_config = mv88e6165_port_jumbo_config, 3702 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3703 .port_pause_config = mv88e6097_port_pause_config, 3704 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3705 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3706 .stats_get_strings = mv88e6095_stats_get_strings, 3707 .stats_get_stats = mv88e6095_stats_get_stats, 3708 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3709 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3710 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3711 .reset = mv88e6352_g1_reset, 3712 }; 3713 3714 static const struct mv88e6xxx_ops mv88e6390_ops = { 3715 /* MV88E6XXX_FAMILY_6390 */ 3716 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3717 .phy_read = mv88e6xxx_g2_smi_phy_read, 3718 .phy_write = mv88e6xxx_g2_smi_phy_write, 3719 .port_set_link = mv88e6xxx_port_set_link, 3720 .port_set_duplex = mv88e6xxx_port_set_duplex, 3721 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3722 .port_set_speed = mv88e6390_port_set_speed, 3723 .port_tag_remap = mv88e6390_port_tag_remap, 3724 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3725 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3726 .port_set_ether_type = mv88e6351_port_set_ether_type, 3727 .port_jumbo_config = mv88e6165_port_jumbo_config, 3728 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3729 .port_pause_config = mv88e6390_port_pause_config, 3730 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3731 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3732 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3733 .stats_get_strings = mv88e6320_stats_get_strings, 3734 .stats_get_stats = mv88e6390_stats_get_stats, 3735 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3736 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3737 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3738 .reset = mv88e6352_g1_reset, 3739 }; 3740 3741 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3742 /* MV88E6XXX_FAMILY_6390 */ 3743 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3744 .phy_read = mv88e6xxx_g2_smi_phy_read, 3745 .phy_write = mv88e6xxx_g2_smi_phy_write, 3746 .port_set_link = mv88e6xxx_port_set_link, 3747 .port_set_duplex = mv88e6xxx_port_set_duplex, 3748 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3749 .port_set_speed = mv88e6390x_port_set_speed, 3750 .port_tag_remap = mv88e6390_port_tag_remap, 3751 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3752 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3753 .port_set_ether_type = mv88e6351_port_set_ether_type, 3754 .port_jumbo_config = mv88e6165_port_jumbo_config, 3755 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3756 .port_pause_config = mv88e6390_port_pause_config, 3757 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3758 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3759 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3760 .stats_get_strings = mv88e6320_stats_get_strings, 3761 .stats_get_stats = mv88e6390_stats_get_stats, 3762 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3763 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3764 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3765 .reset = mv88e6352_g1_reset, 3766 }; 3767 3768 static const struct mv88e6xxx_ops mv88e6391_ops = { 3769 /* MV88E6XXX_FAMILY_6390 */ 3770 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3771 .phy_read = mv88e6xxx_g2_smi_phy_read, 3772 .phy_write = mv88e6xxx_g2_smi_phy_write, 3773 .port_set_link = mv88e6xxx_port_set_link, 3774 .port_set_duplex = mv88e6xxx_port_set_duplex, 3775 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3776 .port_set_speed = mv88e6390_port_set_speed, 3777 .port_tag_remap = mv88e6390_port_tag_remap, 3778 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3779 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3780 .port_set_ether_type = mv88e6351_port_set_ether_type, 3781 .port_pause_config = mv88e6390_port_pause_config, 3782 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3783 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3784 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3785 .stats_get_strings = mv88e6320_stats_get_strings, 3786 .stats_get_stats = mv88e6390_stats_get_stats, 3787 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3788 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3789 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3790 .reset = mv88e6352_g1_reset, 3791 }; 3792 3793 static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip, 3794 const struct mv88e6xxx_ops *ops) 3795 { 3796 if (!ops->port_set_frame_mode) { 3797 dev_err(chip->dev, "Missing port_set_frame_mode"); 3798 return -EINVAL; 3799 } 3800 3801 if (!ops->port_set_egress_unknowns) { 3802 dev_err(chip->dev, "Missing port_set_egress_mode"); 3803 return -EINVAL; 3804 } 3805 3806 return 0; 3807 } 3808 3809 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3810 [MV88E6085] = { 3811 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, 3812 .family = MV88E6XXX_FAMILY_6097, 3813 .name = "Marvell 88E6085", 3814 .num_databases = 4096, 3815 .num_ports = 10, 3816 .port_base_addr = 0x10, 3817 .global1_addr = 0x1b, 3818 .age_time_coeff = 15000, 3819 .g1_irqs = 8, 3820 .tag_protocol = DSA_TAG_PROTO_DSA, 3821 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3822 .ops = &mv88e6085_ops, 3823 }, 3824 3825 [MV88E6095] = { 3826 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, 3827 .family = MV88E6XXX_FAMILY_6095, 3828 .name = "Marvell 88E6095/88E6095F", 3829 .num_databases = 256, 3830 .num_ports = 11, 3831 .port_base_addr = 0x10, 3832 .global1_addr = 0x1b, 3833 .age_time_coeff = 15000, 3834 .g1_irqs = 8, 3835 .tag_protocol = DSA_TAG_PROTO_DSA, 3836 .flags = MV88E6XXX_FLAGS_FAMILY_6095, 3837 .ops = &mv88e6095_ops, 3838 }, 3839 3840 [MV88E6097] = { 3841 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097, 3842 .family = MV88E6XXX_FAMILY_6097, 3843 .name = "Marvell 88E6097/88E6097F", 3844 .num_databases = 4096, 3845 .num_ports = 11, 3846 .port_base_addr = 0x10, 3847 .global1_addr = 0x1b, 3848 .age_time_coeff = 15000, 3849 .g1_irqs = 8, 3850 .tag_protocol = DSA_TAG_PROTO_EDSA, 3851 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3852 .ops = &mv88e6097_ops, 3853 }, 3854 3855 [MV88E6123] = { 3856 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, 3857 .family = MV88E6XXX_FAMILY_6165, 3858 .name = "Marvell 88E6123", 3859 .num_databases = 4096, 3860 .num_ports = 3, 3861 .port_base_addr = 0x10, 3862 .global1_addr = 0x1b, 3863 .age_time_coeff = 15000, 3864 .g1_irqs = 9, 3865 .tag_protocol = DSA_TAG_PROTO_DSA, 3866 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3867 .ops = &mv88e6123_ops, 3868 }, 3869 3870 [MV88E6131] = { 3871 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, 3872 .family = MV88E6XXX_FAMILY_6185, 3873 .name = "Marvell 88E6131", 3874 .num_databases = 256, 3875 .num_ports = 8, 3876 .port_base_addr = 0x10, 3877 .global1_addr = 0x1b, 3878 .age_time_coeff = 15000, 3879 .g1_irqs = 9, 3880 .tag_protocol = DSA_TAG_PROTO_DSA, 3881 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3882 .ops = &mv88e6131_ops, 3883 }, 3884 3885 [MV88E6161] = { 3886 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, 3887 .family = MV88E6XXX_FAMILY_6165, 3888 .name = "Marvell 88E6161", 3889 .num_databases = 4096, 3890 .num_ports = 6, 3891 .port_base_addr = 0x10, 3892 .global1_addr = 0x1b, 3893 .age_time_coeff = 15000, 3894 .g1_irqs = 9, 3895 .tag_protocol = DSA_TAG_PROTO_DSA, 3896 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3897 .ops = &mv88e6161_ops, 3898 }, 3899 3900 [MV88E6165] = { 3901 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, 3902 .family = MV88E6XXX_FAMILY_6165, 3903 .name = "Marvell 88E6165", 3904 .num_databases = 4096, 3905 .num_ports = 6, 3906 .port_base_addr = 0x10, 3907 .global1_addr = 0x1b, 3908 .age_time_coeff = 15000, 3909 .g1_irqs = 9, 3910 .tag_protocol = DSA_TAG_PROTO_DSA, 3911 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3912 .ops = &mv88e6165_ops, 3913 }, 3914 3915 [MV88E6171] = { 3916 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, 3917 .family = MV88E6XXX_FAMILY_6351, 3918 .name = "Marvell 88E6171", 3919 .num_databases = 4096, 3920 .num_ports = 7, 3921 .port_base_addr = 0x10, 3922 .global1_addr = 0x1b, 3923 .age_time_coeff = 15000, 3924 .g1_irqs = 9, 3925 .tag_protocol = DSA_TAG_PROTO_EDSA, 3926 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3927 .ops = &mv88e6171_ops, 3928 }, 3929 3930 [MV88E6172] = { 3931 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, 3932 .family = MV88E6XXX_FAMILY_6352, 3933 .name = "Marvell 88E6172", 3934 .num_databases = 4096, 3935 .num_ports = 7, 3936 .port_base_addr = 0x10, 3937 .global1_addr = 0x1b, 3938 .age_time_coeff = 15000, 3939 .g1_irqs = 9, 3940 .tag_protocol = DSA_TAG_PROTO_EDSA, 3941 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3942 .ops = &mv88e6172_ops, 3943 }, 3944 3945 [MV88E6175] = { 3946 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, 3947 .family = MV88E6XXX_FAMILY_6351, 3948 .name = "Marvell 88E6175", 3949 .num_databases = 4096, 3950 .num_ports = 7, 3951 .port_base_addr = 0x10, 3952 .global1_addr = 0x1b, 3953 .age_time_coeff = 15000, 3954 .g1_irqs = 9, 3955 .tag_protocol = DSA_TAG_PROTO_EDSA, 3956 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3957 .ops = &mv88e6175_ops, 3958 }, 3959 3960 [MV88E6176] = { 3961 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, 3962 .family = MV88E6XXX_FAMILY_6352, 3963 .name = "Marvell 88E6176", 3964 .num_databases = 4096, 3965 .num_ports = 7, 3966 .port_base_addr = 0x10, 3967 .global1_addr = 0x1b, 3968 .age_time_coeff = 15000, 3969 .g1_irqs = 9, 3970 .tag_protocol = DSA_TAG_PROTO_EDSA, 3971 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3972 .ops = &mv88e6176_ops, 3973 }, 3974 3975 [MV88E6185] = { 3976 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, 3977 .family = MV88E6XXX_FAMILY_6185, 3978 .name = "Marvell 88E6185", 3979 .num_databases = 256, 3980 .num_ports = 10, 3981 .port_base_addr = 0x10, 3982 .global1_addr = 0x1b, 3983 .age_time_coeff = 15000, 3984 .g1_irqs = 8, 3985 .tag_protocol = DSA_TAG_PROTO_EDSA, 3986 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3987 .ops = &mv88e6185_ops, 3988 }, 3989 3990 [MV88E6190] = { 3991 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190, 3992 .family = MV88E6XXX_FAMILY_6390, 3993 .name = "Marvell 88E6190", 3994 .num_databases = 4096, 3995 .num_ports = 11, /* 10 + Z80 */ 3996 .port_base_addr = 0x0, 3997 .global1_addr = 0x1b, 3998 .tag_protocol = DSA_TAG_PROTO_DSA, 3999 .age_time_coeff = 15000, 4000 .g1_irqs = 9, 4001 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4002 .ops = &mv88e6190_ops, 4003 }, 4004 4005 [MV88E6190X] = { 4006 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X, 4007 .family = MV88E6XXX_FAMILY_6390, 4008 .name = "Marvell 88E6190X", 4009 .num_databases = 4096, 4010 .num_ports = 11, /* 10 + Z80 */ 4011 .port_base_addr = 0x0, 4012 .global1_addr = 0x1b, 4013 .age_time_coeff = 15000, 4014 .g1_irqs = 9, 4015 .tag_protocol = DSA_TAG_PROTO_DSA, 4016 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4017 .ops = &mv88e6190x_ops, 4018 }, 4019 4020 [MV88E6191] = { 4021 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191, 4022 .family = MV88E6XXX_FAMILY_6390, 4023 .name = "Marvell 88E6191", 4024 .num_databases = 4096, 4025 .num_ports = 11, /* 10 + Z80 */ 4026 .port_base_addr = 0x0, 4027 .global1_addr = 0x1b, 4028 .age_time_coeff = 15000, 4029 .g1_irqs = 9, 4030 .tag_protocol = DSA_TAG_PROTO_DSA, 4031 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4032 .ops = &mv88e6391_ops, 4033 }, 4034 4035 [MV88E6240] = { 4036 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, 4037 .family = MV88E6XXX_FAMILY_6352, 4038 .name = "Marvell 88E6240", 4039 .num_databases = 4096, 4040 .num_ports = 7, 4041 .port_base_addr = 0x10, 4042 .global1_addr = 0x1b, 4043 .age_time_coeff = 15000, 4044 .g1_irqs = 9, 4045 .tag_protocol = DSA_TAG_PROTO_EDSA, 4046 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4047 .ops = &mv88e6240_ops, 4048 }, 4049 4050 [MV88E6290] = { 4051 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290, 4052 .family = MV88E6XXX_FAMILY_6390, 4053 .name = "Marvell 88E6290", 4054 .num_databases = 4096, 4055 .num_ports = 11, /* 10 + Z80 */ 4056 .port_base_addr = 0x0, 4057 .global1_addr = 0x1b, 4058 .age_time_coeff = 15000, 4059 .g1_irqs = 9, 4060 .tag_protocol = DSA_TAG_PROTO_DSA, 4061 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4062 .ops = &mv88e6290_ops, 4063 }, 4064 4065 [MV88E6320] = { 4066 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, 4067 .family = MV88E6XXX_FAMILY_6320, 4068 .name = "Marvell 88E6320", 4069 .num_databases = 4096, 4070 .num_ports = 7, 4071 .port_base_addr = 0x10, 4072 .global1_addr = 0x1b, 4073 .age_time_coeff = 15000, 4074 .g1_irqs = 8, 4075 .tag_protocol = DSA_TAG_PROTO_EDSA, 4076 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4077 .ops = &mv88e6320_ops, 4078 }, 4079 4080 [MV88E6321] = { 4081 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, 4082 .family = MV88E6XXX_FAMILY_6320, 4083 .name = "Marvell 88E6321", 4084 .num_databases = 4096, 4085 .num_ports = 7, 4086 .port_base_addr = 0x10, 4087 .global1_addr = 0x1b, 4088 .age_time_coeff = 15000, 4089 .g1_irqs = 8, 4090 .tag_protocol = DSA_TAG_PROTO_EDSA, 4091 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4092 .ops = &mv88e6321_ops, 4093 }, 4094 4095 [MV88E6350] = { 4096 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, 4097 .family = MV88E6XXX_FAMILY_6351, 4098 .name = "Marvell 88E6350", 4099 .num_databases = 4096, 4100 .num_ports = 7, 4101 .port_base_addr = 0x10, 4102 .global1_addr = 0x1b, 4103 .age_time_coeff = 15000, 4104 .g1_irqs = 9, 4105 .tag_protocol = DSA_TAG_PROTO_EDSA, 4106 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4107 .ops = &mv88e6350_ops, 4108 }, 4109 4110 [MV88E6351] = { 4111 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, 4112 .family = MV88E6XXX_FAMILY_6351, 4113 .name = "Marvell 88E6351", 4114 .num_databases = 4096, 4115 .num_ports = 7, 4116 .port_base_addr = 0x10, 4117 .global1_addr = 0x1b, 4118 .age_time_coeff = 15000, 4119 .g1_irqs = 9, 4120 .tag_protocol = DSA_TAG_PROTO_EDSA, 4121 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4122 .ops = &mv88e6351_ops, 4123 }, 4124 4125 [MV88E6352] = { 4126 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, 4127 .family = MV88E6XXX_FAMILY_6352, 4128 .name = "Marvell 88E6352", 4129 .num_databases = 4096, 4130 .num_ports = 7, 4131 .port_base_addr = 0x10, 4132 .global1_addr = 0x1b, 4133 .age_time_coeff = 15000, 4134 .g1_irqs = 9, 4135 .tag_protocol = DSA_TAG_PROTO_EDSA, 4136 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4137 .ops = &mv88e6352_ops, 4138 }, 4139 [MV88E6390] = { 4140 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390, 4141 .family = MV88E6XXX_FAMILY_6390, 4142 .name = "Marvell 88E6390", 4143 .num_databases = 4096, 4144 .num_ports = 11, /* 10 + Z80 */ 4145 .port_base_addr = 0x0, 4146 .global1_addr = 0x1b, 4147 .age_time_coeff = 15000, 4148 .g1_irqs = 9, 4149 .tag_protocol = DSA_TAG_PROTO_DSA, 4150 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4151 .ops = &mv88e6390_ops, 4152 }, 4153 [MV88E6390X] = { 4154 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X, 4155 .family = MV88E6XXX_FAMILY_6390, 4156 .name = "Marvell 88E6390X", 4157 .num_databases = 4096, 4158 .num_ports = 11, /* 10 + Z80 */ 4159 .port_base_addr = 0x0, 4160 .global1_addr = 0x1b, 4161 .age_time_coeff = 15000, 4162 .g1_irqs = 9, 4163 .tag_protocol = DSA_TAG_PROTO_DSA, 4164 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4165 .ops = &mv88e6390x_ops, 4166 }, 4167 }; 4168 4169 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4170 { 4171 int i; 4172 4173 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4174 if (mv88e6xxx_table[i].prod_num == prod_num) 4175 return &mv88e6xxx_table[i]; 4176 4177 return NULL; 4178 } 4179 4180 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4181 { 4182 const struct mv88e6xxx_info *info; 4183 unsigned int prod_num, rev; 4184 u16 id; 4185 int err; 4186 4187 mutex_lock(&chip->reg_lock); 4188 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); 4189 mutex_unlock(&chip->reg_lock); 4190 if (err) 4191 return err; 4192 4193 prod_num = (id & 0xfff0) >> 4; 4194 rev = id & 0x000f; 4195 4196 info = mv88e6xxx_lookup_info(prod_num); 4197 if (!info) 4198 return -ENODEV; 4199 4200 /* Update the compatible info with the probed one */ 4201 chip->info = info; 4202 4203 err = mv88e6xxx_g2_require(chip); 4204 if (err) 4205 return err; 4206 4207 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4208 chip->info->prod_num, chip->info->name, rev); 4209 4210 return 0; 4211 } 4212 4213 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4214 { 4215 struct mv88e6xxx_chip *chip; 4216 4217 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4218 if (!chip) 4219 return NULL; 4220 4221 chip->dev = dev; 4222 4223 mutex_init(&chip->reg_lock); 4224 4225 return chip; 4226 } 4227 4228 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) 4229 { 4230 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) 4231 mv88e6xxx_ppu_state_init(chip); 4232 } 4233 4234 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) 4235 { 4236 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) 4237 mv88e6xxx_ppu_state_destroy(chip); 4238 } 4239 4240 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4241 struct mii_bus *bus, int sw_addr) 4242 { 4243 /* ADDR[0] pin is unavailable externally and considered zero */ 4244 if (sw_addr & 0x1) 4245 return -EINVAL; 4246 4247 if (sw_addr == 0) 4248 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4249 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) 4250 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4251 else 4252 return -EINVAL; 4253 4254 chip->bus = bus; 4255 chip->sw_addr = sw_addr; 4256 4257 return 0; 4258 } 4259 4260 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 4261 { 4262 struct mv88e6xxx_chip *chip = ds->priv; 4263 4264 return chip->info->tag_protocol; 4265 } 4266 4267 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4268 struct device *host_dev, int sw_addr, 4269 void **priv) 4270 { 4271 struct mv88e6xxx_chip *chip; 4272 struct mii_bus *bus; 4273 int err; 4274 4275 bus = dsa_host_dev_to_mii_bus(host_dev); 4276 if (!bus) 4277 return NULL; 4278 4279 chip = mv88e6xxx_alloc_chip(dsa_dev); 4280 if (!chip) 4281 return NULL; 4282 4283 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4284 chip->info = &mv88e6xxx_table[MV88E6085]; 4285 4286 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4287 if (err) 4288 goto free; 4289 4290 err = mv88e6xxx_detect(chip); 4291 if (err) 4292 goto free; 4293 4294 mutex_lock(&chip->reg_lock); 4295 err = mv88e6xxx_switch_reset(chip); 4296 mutex_unlock(&chip->reg_lock); 4297 if (err) 4298 goto free; 4299 4300 mv88e6xxx_phy_init(chip); 4301 4302 err = mv88e6xxx_mdio_register(chip, NULL); 4303 if (err) 4304 goto free; 4305 4306 *priv = chip; 4307 4308 return chip->info->name; 4309 free: 4310 devm_kfree(dsa_dev, chip); 4311 4312 return NULL; 4313 } 4314 4315 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4316 const struct switchdev_obj_port_mdb *mdb, 4317 struct switchdev_trans *trans) 4318 { 4319 /* We don't need any dynamic resource from the kernel (yet), 4320 * so skip the prepare phase. 4321 */ 4322 4323 return 0; 4324 } 4325 4326 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4327 const struct switchdev_obj_port_mdb *mdb, 4328 struct switchdev_trans *trans) 4329 { 4330 struct mv88e6xxx_chip *chip = ds->priv; 4331 4332 mutex_lock(&chip->reg_lock); 4333 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4334 GLOBAL_ATU_DATA_STATE_MC_STATIC)) 4335 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); 4336 mutex_unlock(&chip->reg_lock); 4337 } 4338 4339 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4340 const struct switchdev_obj_port_mdb *mdb) 4341 { 4342 struct mv88e6xxx_chip *chip = ds->priv; 4343 int err; 4344 4345 mutex_lock(&chip->reg_lock); 4346 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4347 GLOBAL_ATU_DATA_STATE_UNUSED); 4348 mutex_unlock(&chip->reg_lock); 4349 4350 return err; 4351 } 4352 4353 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, 4354 struct switchdev_obj_port_mdb *mdb, 4355 int (*cb)(struct switchdev_obj *obj)) 4356 { 4357 struct mv88e6xxx_chip *chip = ds->priv; 4358 int err; 4359 4360 mutex_lock(&chip->reg_lock); 4361 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); 4362 mutex_unlock(&chip->reg_lock); 4363 4364 return err; 4365 } 4366 4367 static struct dsa_switch_ops mv88e6xxx_switch_ops = { 4368 .probe = mv88e6xxx_drv_probe, 4369 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4370 .setup = mv88e6xxx_setup, 4371 .set_addr = mv88e6xxx_set_addr, 4372 .adjust_link = mv88e6xxx_adjust_link, 4373 .get_strings = mv88e6xxx_get_strings, 4374 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4375 .get_sset_count = mv88e6xxx_get_sset_count, 4376 .set_eee = mv88e6xxx_set_eee, 4377 .get_eee = mv88e6xxx_get_eee, 4378 #ifdef CONFIG_NET_DSA_HWMON 4379 .get_temp = mv88e6xxx_get_temp, 4380 .get_temp_limit = mv88e6xxx_get_temp_limit, 4381 .set_temp_limit = mv88e6xxx_set_temp_limit, 4382 .get_temp_alarm = mv88e6xxx_get_temp_alarm, 4383 #endif 4384 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4385 .get_eeprom = mv88e6xxx_get_eeprom, 4386 .set_eeprom = mv88e6xxx_set_eeprom, 4387 .get_regs_len = mv88e6xxx_get_regs_len, 4388 .get_regs = mv88e6xxx_get_regs, 4389 .set_ageing_time = mv88e6xxx_set_ageing_time, 4390 .port_bridge_join = mv88e6xxx_port_bridge_join, 4391 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4392 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4393 .port_fast_age = mv88e6xxx_port_fast_age, 4394 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4395 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4396 .port_vlan_add = mv88e6xxx_port_vlan_add, 4397 .port_vlan_del = mv88e6xxx_port_vlan_del, 4398 .port_vlan_dump = mv88e6xxx_port_vlan_dump, 4399 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, 4400 .port_fdb_add = mv88e6xxx_port_fdb_add, 4401 .port_fdb_del = mv88e6xxx_port_fdb_del, 4402 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4403 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4404 .port_mdb_add = mv88e6xxx_port_mdb_add, 4405 .port_mdb_del = mv88e6xxx_port_mdb_del, 4406 .port_mdb_dump = mv88e6xxx_port_mdb_dump, 4407 }; 4408 4409 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, 4410 struct device_node *np) 4411 { 4412 struct device *dev = chip->dev; 4413 struct dsa_switch *ds; 4414 4415 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 4416 if (!ds) 4417 return -ENOMEM; 4418 4419 ds->dev = dev; 4420 ds->priv = chip; 4421 ds->ops = &mv88e6xxx_switch_ops; 4422 4423 dev_set_drvdata(dev, ds); 4424 4425 return dsa_register_switch(ds, np); 4426 } 4427 4428 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4429 { 4430 dsa_unregister_switch(chip->ds); 4431 } 4432 4433 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4434 { 4435 struct device *dev = &mdiodev->dev; 4436 struct device_node *np = dev->of_node; 4437 const struct mv88e6xxx_info *compat_info; 4438 struct mv88e6xxx_chip *chip; 4439 u32 eeprom_len; 4440 int err; 4441 4442 compat_info = of_device_get_match_data(dev); 4443 if (!compat_info) 4444 return -EINVAL; 4445 4446 chip = mv88e6xxx_alloc_chip(dev); 4447 if (!chip) 4448 return -ENOMEM; 4449 4450 chip->info = compat_info; 4451 4452 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops); 4453 if (err) 4454 return err; 4455 4456 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4457 if (err) 4458 return err; 4459 4460 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4461 if (IS_ERR(chip->reset)) 4462 return PTR_ERR(chip->reset); 4463 4464 err = mv88e6xxx_detect(chip); 4465 if (err) 4466 return err; 4467 4468 mv88e6xxx_phy_init(chip); 4469 4470 if (chip->info->ops->get_eeprom && 4471 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 4472 chip->eeprom_len = eeprom_len; 4473 4474 mutex_lock(&chip->reg_lock); 4475 err = mv88e6xxx_switch_reset(chip); 4476 mutex_unlock(&chip->reg_lock); 4477 if (err) 4478 goto out; 4479 4480 chip->irq = of_irq_get(np, 0); 4481 if (chip->irq == -EPROBE_DEFER) { 4482 err = chip->irq; 4483 goto out; 4484 } 4485 4486 if (chip->irq > 0) { 4487 /* Has to be performed before the MDIO bus is created, 4488 * because the PHYs will link there interrupts to these 4489 * interrupt controllers 4490 */ 4491 mutex_lock(&chip->reg_lock); 4492 err = mv88e6xxx_g1_irq_setup(chip); 4493 mutex_unlock(&chip->reg_lock); 4494 4495 if (err) 4496 goto out; 4497 4498 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { 4499 err = mv88e6xxx_g2_irq_setup(chip); 4500 if (err) 4501 goto out_g1_irq; 4502 } 4503 } 4504 4505 err = mv88e6xxx_mdio_register(chip, np); 4506 if (err) 4507 goto out_g2_irq; 4508 4509 err = mv88e6xxx_register_switch(chip, np); 4510 if (err) 4511 goto out_mdio; 4512 4513 return 0; 4514 4515 out_mdio: 4516 mv88e6xxx_mdio_unregister(chip); 4517 out_g2_irq: 4518 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) 4519 mv88e6xxx_g2_irq_free(chip); 4520 out_g1_irq: 4521 if (chip->irq > 0) { 4522 mutex_lock(&chip->reg_lock); 4523 mv88e6xxx_g1_irq_free(chip); 4524 mutex_unlock(&chip->reg_lock); 4525 } 4526 out: 4527 return err; 4528 } 4529 4530 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4531 { 4532 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4533 struct mv88e6xxx_chip *chip = ds->priv; 4534 4535 mv88e6xxx_phy_destroy(chip); 4536 mv88e6xxx_unregister_switch(chip); 4537 mv88e6xxx_mdio_unregister(chip); 4538 4539 if (chip->irq > 0) { 4540 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) 4541 mv88e6xxx_g2_irq_free(chip); 4542 mv88e6xxx_g1_irq_free(chip); 4543 } 4544 } 4545 4546 static const struct of_device_id mv88e6xxx_of_match[] = { 4547 { 4548 .compatible = "marvell,mv88e6085", 4549 .data = &mv88e6xxx_table[MV88E6085], 4550 }, 4551 { 4552 .compatible = "marvell,mv88e6190", 4553 .data = &mv88e6xxx_table[MV88E6190], 4554 }, 4555 { /* sentinel */ }, 4556 }; 4557 4558 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4559 4560 static struct mdio_driver mv88e6xxx_driver = { 4561 .probe = mv88e6xxx_probe, 4562 .remove = mv88e6xxx_remove, 4563 .mdiodrv.driver = { 4564 .name = "mv88e6085", 4565 .of_match_table = mv88e6xxx_of_match, 4566 }, 4567 }; 4568 4569 static int __init mv88e6xxx_init(void) 4570 { 4571 register_switch_driver(&mv88e6xxx_switch_ops); 4572 return mdio_driver_register(&mv88e6xxx_driver); 4573 } 4574 module_init(mv88e6xxx_init); 4575 4576 static void __exit mv88e6xxx_cleanup(void) 4577 { 4578 mdio_driver_unregister(&mv88e6xxx_driver); 4579 unregister_switch_driver(&mv88e6xxx_switch_ops); 4580 } 4581 module_exit(mv88e6xxx_cleanup); 4582 4583 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4584 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4585 MODULE_LICENSE("GPL"); 4586