1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "devlink.h" 36 #include "global1.h" 37 #include "global2.h" 38 #include "hwtstamp.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "ptp.h" 42 #include "serdes.h" 43 #include "smi.h" 44 45 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 46 { 47 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 48 dev_err(chip->dev, "Switch registers lock not held!\n"); 49 dump_stack(); 50 } 51 } 52 53 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 54 { 55 int err; 56 57 assert_reg_lock(chip); 58 59 err = mv88e6xxx_smi_read(chip, addr, reg, val); 60 if (err) 61 return err; 62 63 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 64 addr, reg, *val); 65 66 return 0; 67 } 68 69 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 70 { 71 int err; 72 73 assert_reg_lock(chip); 74 75 err = mv88e6xxx_smi_write(chip, addr, reg, val); 76 if (err) 77 return err; 78 79 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 80 addr, reg, val); 81 82 return 0; 83 } 84 85 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 86 u16 mask, u16 val) 87 { 88 u16 data; 89 int err; 90 int i; 91 92 /* There's no bus specific operation to wait for a mask */ 93 for (i = 0; i < 16; i++) { 94 err = mv88e6xxx_read(chip, addr, reg, &data); 95 if (err) 96 return err; 97 98 if ((data & mask) == val) 99 return 0; 100 101 usleep_range(1000, 2000); 102 } 103 104 dev_err(chip->dev, "Timeout while waiting for switch\n"); 105 return -ETIMEDOUT; 106 } 107 108 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 109 int bit, int val) 110 { 111 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 112 val ? BIT(bit) : 0x0000); 113 } 114 115 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 116 { 117 struct mv88e6xxx_mdio_bus *mdio_bus; 118 119 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 120 list); 121 if (!mdio_bus) 122 return NULL; 123 124 return mdio_bus->bus; 125 } 126 127 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 128 { 129 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 130 unsigned int n = d->hwirq; 131 132 chip->g1_irq.masked |= (1 << n); 133 } 134 135 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked &= ~(1 << n); 141 } 142 143 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 144 { 145 unsigned int nhandled = 0; 146 unsigned int sub_irq; 147 unsigned int n; 148 u16 reg; 149 u16 ctl1; 150 int err; 151 152 mv88e6xxx_reg_lock(chip); 153 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 154 mv88e6xxx_reg_unlock(chip); 155 156 if (err) 157 goto out; 158 159 do { 160 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 161 if (reg & (1 << n)) { 162 sub_irq = irq_find_mapping(chip->g1_irq.domain, 163 n); 164 handle_nested_irq(sub_irq); 165 ++nhandled; 166 } 167 } 168 169 mv88e6xxx_reg_lock(chip); 170 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 171 if (err) 172 goto unlock; 173 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 174 unlock: 175 mv88e6xxx_reg_unlock(chip); 176 if (err) 177 goto out; 178 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 179 } while (reg & ctl1); 180 181 out: 182 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 183 } 184 185 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 186 { 187 struct mv88e6xxx_chip *chip = dev_id; 188 189 return mv88e6xxx_g1_irq_thread_work(chip); 190 } 191 192 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 193 { 194 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 195 196 mv88e6xxx_reg_lock(chip); 197 } 198 199 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 200 { 201 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 202 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 203 u16 reg; 204 int err; 205 206 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 207 if (err) 208 goto out; 209 210 reg &= ~mask; 211 reg |= (~chip->g1_irq.masked & mask); 212 213 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 214 if (err) 215 goto out; 216 217 out: 218 mv88e6xxx_reg_unlock(chip); 219 } 220 221 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 222 .name = "mv88e6xxx-g1", 223 .irq_mask = mv88e6xxx_g1_irq_mask, 224 .irq_unmask = mv88e6xxx_g1_irq_unmask, 225 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 226 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 227 }; 228 229 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 230 unsigned int irq, 231 irq_hw_number_t hwirq) 232 { 233 struct mv88e6xxx_chip *chip = d->host_data; 234 235 irq_set_chip_data(irq, d->host_data); 236 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 237 irq_set_noprobe(irq); 238 239 return 0; 240 } 241 242 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 243 .map = mv88e6xxx_g1_irq_domain_map, 244 .xlate = irq_domain_xlate_twocell, 245 }; 246 247 /* To be called with reg_lock held */ 248 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 249 { 250 int irq, virq; 251 u16 mask; 252 253 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 254 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 255 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 256 257 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 258 virq = irq_find_mapping(chip->g1_irq.domain, irq); 259 irq_dispose_mapping(virq); 260 } 261 262 irq_domain_remove(chip->g1_irq.domain); 263 } 264 265 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 266 { 267 /* 268 * free_irq must be called without reg_lock taken because the irq 269 * handler takes this lock, too. 270 */ 271 free_irq(chip->irq, chip); 272 273 mv88e6xxx_reg_lock(chip); 274 mv88e6xxx_g1_irq_free_common(chip); 275 mv88e6xxx_reg_unlock(chip); 276 } 277 278 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 279 { 280 int err, irq, virq; 281 u16 reg, mask; 282 283 chip->g1_irq.nirqs = chip->info->g1_irqs; 284 chip->g1_irq.domain = irq_domain_add_simple( 285 NULL, chip->g1_irq.nirqs, 0, 286 &mv88e6xxx_g1_irq_domain_ops, chip); 287 if (!chip->g1_irq.domain) 288 return -ENOMEM; 289 290 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 291 irq_create_mapping(chip->g1_irq.domain, irq); 292 293 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 294 chip->g1_irq.masked = ~0; 295 296 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 297 if (err) 298 goto out_mapping; 299 300 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 303 if (err) 304 goto out_disable; 305 306 /* Reading the interrupt status clears (most of) them */ 307 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 308 if (err) 309 goto out_disable; 310 311 return 0; 312 313 out_disable: 314 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 315 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 316 317 out_mapping: 318 for (irq = 0; irq < 16; irq++) { 319 virq = irq_find_mapping(chip->g1_irq.domain, irq); 320 irq_dispose_mapping(virq); 321 } 322 323 irq_domain_remove(chip->g1_irq.domain); 324 325 return err; 326 } 327 328 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 329 { 330 static struct lock_class_key lock_key; 331 static struct lock_class_key request_key; 332 int err; 333 334 err = mv88e6xxx_g1_irq_setup_common(chip); 335 if (err) 336 return err; 337 338 /* These lock classes tells lockdep that global 1 irqs are in 339 * a different category than their parent GPIO, so it won't 340 * report false recursion. 341 */ 342 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 343 344 snprintf(chip->irq_name, sizeof(chip->irq_name), 345 "mv88e6xxx-%s", dev_name(chip->dev)); 346 347 mv88e6xxx_reg_unlock(chip); 348 err = request_threaded_irq(chip->irq, NULL, 349 mv88e6xxx_g1_irq_thread_fn, 350 IRQF_ONESHOT | IRQF_SHARED, 351 chip->irq_name, chip); 352 mv88e6xxx_reg_lock(chip); 353 if (err) 354 mv88e6xxx_g1_irq_free_common(chip); 355 356 return err; 357 } 358 359 static void mv88e6xxx_irq_poll(struct kthread_work *work) 360 { 361 struct mv88e6xxx_chip *chip = container_of(work, 362 struct mv88e6xxx_chip, 363 irq_poll_work.work); 364 mv88e6xxx_g1_irq_thread_work(chip); 365 366 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 367 msecs_to_jiffies(100)); 368 } 369 370 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 371 { 372 int err; 373 374 err = mv88e6xxx_g1_irq_setup_common(chip); 375 if (err) 376 return err; 377 378 kthread_init_delayed_work(&chip->irq_poll_work, 379 mv88e6xxx_irq_poll); 380 381 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 382 if (IS_ERR(chip->kworker)) 383 return PTR_ERR(chip->kworker); 384 385 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 386 msecs_to_jiffies(100)); 387 388 return 0; 389 } 390 391 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 392 { 393 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 394 kthread_destroy_worker(chip->kworker); 395 396 mv88e6xxx_reg_lock(chip); 397 mv88e6xxx_g1_irq_free_common(chip); 398 mv88e6xxx_reg_unlock(chip); 399 } 400 401 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 402 int port, phy_interface_t interface) 403 { 404 int err; 405 406 if (chip->info->ops->port_set_rgmii_delay) { 407 err = chip->info->ops->port_set_rgmii_delay(chip, port, 408 interface); 409 if (err && err != -EOPNOTSUPP) 410 return err; 411 } 412 413 if (chip->info->ops->port_set_cmode) { 414 err = chip->info->ops->port_set_cmode(chip, port, 415 interface); 416 if (err && err != -EOPNOTSUPP) 417 return err; 418 } 419 420 return 0; 421 } 422 423 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 424 int link, int speed, int duplex, int pause, 425 phy_interface_t mode) 426 { 427 int err; 428 429 if (!chip->info->ops->port_set_link) 430 return 0; 431 432 /* Port's MAC control must not be changed unless the link is down */ 433 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 434 if (err) 435 return err; 436 437 if (chip->info->ops->port_set_speed_duplex) { 438 err = chip->info->ops->port_set_speed_duplex(chip, port, 439 speed, duplex); 440 if (err && err != -EOPNOTSUPP) 441 goto restore_link; 442 } 443 444 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 445 mode = chip->info->ops->port_max_speed_mode(port); 446 447 if (chip->info->ops->port_set_pause) { 448 err = chip->info->ops->port_set_pause(chip, port, pause); 449 if (err) 450 goto restore_link; 451 } 452 453 err = mv88e6xxx_port_config_interface(chip, port, mode); 454 restore_link: 455 if (chip->info->ops->port_set_link(chip, port, link)) 456 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 457 458 return err; 459 } 460 461 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 462 { 463 struct mv88e6xxx_chip *chip = ds->priv; 464 465 return port < chip->info->num_internal_phys; 466 } 467 468 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 469 { 470 u16 reg; 471 int err; 472 473 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 474 if (err) { 475 dev_err(chip->dev, 476 "p%d: %s: failed to read port status\n", 477 port, __func__); 478 return err; 479 } 480 481 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 482 } 483 484 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 485 struct phylink_link_state *state) 486 { 487 struct mv88e6xxx_chip *chip = ds->priv; 488 u8 lane; 489 int err; 490 491 mv88e6xxx_reg_lock(chip); 492 lane = mv88e6xxx_serdes_get_lane(chip, port); 493 if (lane && chip->info->ops->serdes_pcs_get_state) 494 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 495 state); 496 else 497 err = -EOPNOTSUPP; 498 mv88e6xxx_reg_unlock(chip); 499 500 return err; 501 } 502 503 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 504 unsigned int mode, 505 phy_interface_t interface, 506 const unsigned long *advertise) 507 { 508 const struct mv88e6xxx_ops *ops = chip->info->ops; 509 u8 lane; 510 511 if (ops->serdes_pcs_config) { 512 lane = mv88e6xxx_serdes_get_lane(chip, port); 513 if (lane) 514 return ops->serdes_pcs_config(chip, port, lane, mode, 515 interface, advertise); 516 } 517 518 return 0; 519 } 520 521 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 522 { 523 struct mv88e6xxx_chip *chip = ds->priv; 524 const struct mv88e6xxx_ops *ops; 525 int err = 0; 526 u8 lane; 527 528 ops = chip->info->ops; 529 530 if (ops->serdes_pcs_an_restart) { 531 mv88e6xxx_reg_lock(chip); 532 lane = mv88e6xxx_serdes_get_lane(chip, port); 533 if (lane) 534 err = ops->serdes_pcs_an_restart(chip, port, lane); 535 mv88e6xxx_reg_unlock(chip); 536 537 if (err) 538 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 539 } 540 } 541 542 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 543 unsigned int mode, 544 int speed, int duplex) 545 { 546 const struct mv88e6xxx_ops *ops = chip->info->ops; 547 u8 lane; 548 549 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 550 lane = mv88e6xxx_serdes_get_lane(chip, port); 551 if (lane) 552 return ops->serdes_pcs_link_up(chip, port, lane, 553 speed, duplex); 554 } 555 556 return 0; 557 } 558 559 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 560 unsigned long *mask, 561 struct phylink_link_state *state) 562 { 563 if (!phy_interface_mode_is_8023z(state->interface)) { 564 /* 10M and 100M are only supported in non-802.3z mode */ 565 phylink_set(mask, 10baseT_Half); 566 phylink_set(mask, 10baseT_Full); 567 phylink_set(mask, 100baseT_Half); 568 phylink_set(mask, 100baseT_Full); 569 } 570 } 571 572 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 573 unsigned long *mask, 574 struct phylink_link_state *state) 575 { 576 /* FIXME: if the port is in 1000Base-X mode, then it only supports 577 * 1000M FD speeds. In this case, CMODE will indicate 5. 578 */ 579 phylink_set(mask, 1000baseT_Full); 580 phylink_set(mask, 1000baseX_Full); 581 582 mv88e6065_phylink_validate(chip, port, mask, state); 583 } 584 585 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 586 unsigned long *mask, 587 struct phylink_link_state *state) 588 { 589 if (port >= 5) 590 phylink_set(mask, 2500baseX_Full); 591 592 /* No ethtool bits for 200Mbps */ 593 phylink_set(mask, 1000baseT_Full); 594 phylink_set(mask, 1000baseX_Full); 595 596 mv88e6065_phylink_validate(chip, port, mask, state); 597 } 598 599 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 600 unsigned long *mask, 601 struct phylink_link_state *state) 602 { 603 /* No ethtool bits for 200Mbps */ 604 phylink_set(mask, 1000baseT_Full); 605 phylink_set(mask, 1000baseX_Full); 606 607 mv88e6065_phylink_validate(chip, port, mask, state); 608 } 609 610 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 611 unsigned long *mask, 612 struct phylink_link_state *state) 613 { 614 if (port >= 9) { 615 phylink_set(mask, 2500baseX_Full); 616 phylink_set(mask, 2500baseT_Full); 617 } 618 619 /* No ethtool bits for 200Mbps */ 620 phylink_set(mask, 1000baseT_Full); 621 phylink_set(mask, 1000baseX_Full); 622 623 mv88e6065_phylink_validate(chip, port, mask, state); 624 } 625 626 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 627 unsigned long *mask, 628 struct phylink_link_state *state) 629 { 630 if (port >= 9) { 631 phylink_set(mask, 10000baseT_Full); 632 phylink_set(mask, 10000baseKR_Full); 633 } 634 635 mv88e6390_phylink_validate(chip, port, mask, state); 636 } 637 638 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 639 unsigned long *supported, 640 struct phylink_link_state *state) 641 { 642 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 643 struct mv88e6xxx_chip *chip = ds->priv; 644 645 /* Allow all the expected bits */ 646 phylink_set(mask, Autoneg); 647 phylink_set(mask, Pause); 648 phylink_set_port_modes(mask); 649 650 if (chip->info->ops->phylink_validate) 651 chip->info->ops->phylink_validate(chip, port, mask, state); 652 653 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 654 bitmap_and(state->advertising, state->advertising, mask, 655 __ETHTOOL_LINK_MODE_MASK_NBITS); 656 657 /* We can only operate at 2500BaseX or 1000BaseX. If requested 658 * to advertise both, only report advertising at 2500BaseX. 659 */ 660 phylink_helper_basex_speed(state); 661 } 662 663 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 664 unsigned int mode, 665 const struct phylink_link_state *state) 666 { 667 struct mv88e6xxx_chip *chip = ds->priv; 668 struct mv88e6xxx_port *p; 669 int err; 670 671 p = &chip->ports[port]; 672 673 /* FIXME: is this the correct test? If we're in fixed mode on an 674 * internal port, why should we process this any different from 675 * PHY mode? On the other hand, the port may be automedia between 676 * an internal PHY and the serdes... 677 */ 678 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 679 return; 680 681 mv88e6xxx_reg_lock(chip); 682 /* In inband mode, the link may come up at any time while the link 683 * is not forced down. Force the link down while we reconfigure the 684 * interface mode. 685 */ 686 if (mode == MLO_AN_INBAND && p->interface != state->interface && 687 chip->info->ops->port_set_link) 688 chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 689 690 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 691 if (err && err != -EOPNOTSUPP) 692 goto err_unlock; 693 694 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 695 state->advertising); 696 /* FIXME: we should restart negotiation if something changed - which 697 * is something we get if we convert to using phylinks PCS operations. 698 */ 699 if (err > 0) 700 err = 0; 701 702 /* Undo the forced down state above after completing configuration 703 * irrespective of its state on entry, which allows the link to come up. 704 */ 705 if (mode == MLO_AN_INBAND && p->interface != state->interface && 706 chip->info->ops->port_set_link) 707 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 708 709 p->interface = state->interface; 710 711 err_unlock: 712 mv88e6xxx_reg_unlock(chip); 713 714 if (err && err != -EOPNOTSUPP) 715 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 716 } 717 718 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 719 unsigned int mode, 720 phy_interface_t interface) 721 { 722 struct mv88e6xxx_chip *chip = ds->priv; 723 const struct mv88e6xxx_ops *ops; 724 int err = 0; 725 726 ops = chip->info->ops; 727 728 mv88e6xxx_reg_lock(chip); 729 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 730 mode == MLO_AN_FIXED) && ops->port_sync_link) 731 err = ops->port_sync_link(chip, port, mode, false); 732 mv88e6xxx_reg_unlock(chip); 733 734 if (err) 735 dev_err(chip->dev, 736 "p%d: failed to force MAC link down\n", port); 737 } 738 739 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 740 unsigned int mode, phy_interface_t interface, 741 struct phy_device *phydev, 742 int speed, int duplex, 743 bool tx_pause, bool rx_pause) 744 { 745 struct mv88e6xxx_chip *chip = ds->priv; 746 const struct mv88e6xxx_ops *ops; 747 int err = 0; 748 749 ops = chip->info->ops; 750 751 mv88e6xxx_reg_lock(chip); 752 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 753 /* FIXME: for an automedia port, should we force the link 754 * down here - what if the link comes up due to "other" media 755 * while we're bringing the port up, how is the exclusivity 756 * handled in the Marvell hardware? E.g. port 2 on 88E6390 757 * shared between internal PHY and Serdes. 758 */ 759 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 760 duplex); 761 if (err) 762 goto error; 763 764 if (ops->port_set_speed_duplex) { 765 err = ops->port_set_speed_duplex(chip, port, 766 speed, duplex); 767 if (err && err != -EOPNOTSUPP) 768 goto error; 769 } 770 771 if (ops->port_sync_link) 772 err = ops->port_sync_link(chip, port, mode, true); 773 } 774 error: 775 mv88e6xxx_reg_unlock(chip); 776 777 if (err && err != -EOPNOTSUPP) 778 dev_err(ds->dev, 779 "p%d: failed to configure MAC link up\n", port); 780 } 781 782 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 783 { 784 if (!chip->info->ops->stats_snapshot) 785 return -EOPNOTSUPP; 786 787 return chip->info->ops->stats_snapshot(chip, port); 788 } 789 790 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 791 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 792 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 793 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 794 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 795 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 796 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 797 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 798 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 799 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 800 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 801 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 802 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 803 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 804 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 805 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 806 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 807 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 808 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 809 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 810 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 811 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 812 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 813 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 814 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 815 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 816 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 817 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 818 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 819 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 820 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 821 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 822 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 823 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 824 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 825 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 826 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 827 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 828 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 829 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 830 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 831 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 832 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 833 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 834 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 835 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 836 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 837 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 838 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 839 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 840 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 841 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 842 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 843 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 844 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 845 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 846 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 847 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 848 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 849 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 850 }; 851 852 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 853 struct mv88e6xxx_hw_stat *s, 854 int port, u16 bank1_select, 855 u16 histogram) 856 { 857 u32 low; 858 u32 high = 0; 859 u16 reg = 0; 860 int err; 861 u64 value; 862 863 switch (s->type) { 864 case STATS_TYPE_PORT: 865 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 866 if (err) 867 return U64_MAX; 868 869 low = reg; 870 if (s->size == 4) { 871 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 872 if (err) 873 return U64_MAX; 874 low |= ((u32)reg) << 16; 875 } 876 break; 877 case STATS_TYPE_BANK1: 878 reg = bank1_select; 879 fallthrough; 880 case STATS_TYPE_BANK0: 881 reg |= s->reg | histogram; 882 mv88e6xxx_g1_stats_read(chip, reg, &low); 883 if (s->size == 8) 884 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 885 break; 886 default: 887 return U64_MAX; 888 } 889 value = (((u64)high) << 32) | low; 890 return value; 891 } 892 893 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 894 uint8_t *data, int types) 895 { 896 struct mv88e6xxx_hw_stat *stat; 897 int i, j; 898 899 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 900 stat = &mv88e6xxx_hw_stats[i]; 901 if (stat->type & types) { 902 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 903 ETH_GSTRING_LEN); 904 j++; 905 } 906 } 907 908 return j; 909 } 910 911 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 912 uint8_t *data) 913 { 914 return mv88e6xxx_stats_get_strings(chip, data, 915 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 916 } 917 918 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 919 uint8_t *data) 920 { 921 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 922 } 923 924 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 925 uint8_t *data) 926 { 927 return mv88e6xxx_stats_get_strings(chip, data, 928 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 929 } 930 931 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 932 "atu_member_violation", 933 "atu_miss_violation", 934 "atu_full_violation", 935 "vtu_member_violation", 936 "vtu_miss_violation", 937 }; 938 939 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 940 { 941 unsigned int i; 942 943 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 944 strlcpy(data + i * ETH_GSTRING_LEN, 945 mv88e6xxx_atu_vtu_stats_strings[i], 946 ETH_GSTRING_LEN); 947 } 948 949 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 950 u32 stringset, uint8_t *data) 951 { 952 struct mv88e6xxx_chip *chip = ds->priv; 953 int count = 0; 954 955 if (stringset != ETH_SS_STATS) 956 return; 957 958 mv88e6xxx_reg_lock(chip); 959 960 if (chip->info->ops->stats_get_strings) 961 count = chip->info->ops->stats_get_strings(chip, data); 962 963 if (chip->info->ops->serdes_get_strings) { 964 data += count * ETH_GSTRING_LEN; 965 count = chip->info->ops->serdes_get_strings(chip, port, data); 966 } 967 968 data += count * ETH_GSTRING_LEN; 969 mv88e6xxx_atu_vtu_get_strings(data); 970 971 mv88e6xxx_reg_unlock(chip); 972 } 973 974 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 975 int types) 976 { 977 struct mv88e6xxx_hw_stat *stat; 978 int i, j; 979 980 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 981 stat = &mv88e6xxx_hw_stats[i]; 982 if (stat->type & types) 983 j++; 984 } 985 return j; 986 } 987 988 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 989 { 990 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 991 STATS_TYPE_PORT); 992 } 993 994 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 995 { 996 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 997 } 998 999 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1000 { 1001 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1002 STATS_TYPE_BANK1); 1003 } 1004 1005 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1006 { 1007 struct mv88e6xxx_chip *chip = ds->priv; 1008 int serdes_count = 0; 1009 int count = 0; 1010 1011 if (sset != ETH_SS_STATS) 1012 return 0; 1013 1014 mv88e6xxx_reg_lock(chip); 1015 if (chip->info->ops->stats_get_sset_count) 1016 count = chip->info->ops->stats_get_sset_count(chip); 1017 if (count < 0) 1018 goto out; 1019 1020 if (chip->info->ops->serdes_get_sset_count) 1021 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1022 port); 1023 if (serdes_count < 0) { 1024 count = serdes_count; 1025 goto out; 1026 } 1027 count += serdes_count; 1028 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1029 1030 out: 1031 mv88e6xxx_reg_unlock(chip); 1032 1033 return count; 1034 } 1035 1036 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1037 uint64_t *data, int types, 1038 u16 bank1_select, u16 histogram) 1039 { 1040 struct mv88e6xxx_hw_stat *stat; 1041 int i, j; 1042 1043 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1044 stat = &mv88e6xxx_hw_stats[i]; 1045 if (stat->type & types) { 1046 mv88e6xxx_reg_lock(chip); 1047 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1048 bank1_select, 1049 histogram); 1050 mv88e6xxx_reg_unlock(chip); 1051 1052 j++; 1053 } 1054 } 1055 return j; 1056 } 1057 1058 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1059 uint64_t *data) 1060 { 1061 return mv88e6xxx_stats_get_stats(chip, port, data, 1062 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1063 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1064 } 1065 1066 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1067 uint64_t *data) 1068 { 1069 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1070 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1071 } 1072 1073 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1074 uint64_t *data) 1075 { 1076 return mv88e6xxx_stats_get_stats(chip, port, data, 1077 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1078 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1079 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1080 } 1081 1082 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1083 uint64_t *data) 1084 { 1085 return mv88e6xxx_stats_get_stats(chip, port, data, 1086 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1087 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1088 0); 1089 } 1090 1091 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1092 uint64_t *data) 1093 { 1094 *data++ = chip->ports[port].atu_member_violation; 1095 *data++ = chip->ports[port].atu_miss_violation; 1096 *data++ = chip->ports[port].atu_full_violation; 1097 *data++ = chip->ports[port].vtu_member_violation; 1098 *data++ = chip->ports[port].vtu_miss_violation; 1099 } 1100 1101 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1102 uint64_t *data) 1103 { 1104 int count = 0; 1105 1106 if (chip->info->ops->stats_get_stats) 1107 count = chip->info->ops->stats_get_stats(chip, port, data); 1108 1109 mv88e6xxx_reg_lock(chip); 1110 if (chip->info->ops->serdes_get_stats) { 1111 data += count; 1112 count = chip->info->ops->serdes_get_stats(chip, port, data); 1113 } 1114 data += count; 1115 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1116 mv88e6xxx_reg_unlock(chip); 1117 } 1118 1119 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1120 uint64_t *data) 1121 { 1122 struct mv88e6xxx_chip *chip = ds->priv; 1123 int ret; 1124 1125 mv88e6xxx_reg_lock(chip); 1126 1127 ret = mv88e6xxx_stats_snapshot(chip, port); 1128 mv88e6xxx_reg_unlock(chip); 1129 1130 if (ret < 0) 1131 return; 1132 1133 mv88e6xxx_get_stats(chip, port, data); 1134 1135 } 1136 1137 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1138 { 1139 struct mv88e6xxx_chip *chip = ds->priv; 1140 int len; 1141 1142 len = 32 * sizeof(u16); 1143 if (chip->info->ops->serdes_get_regs_len) 1144 len += chip->info->ops->serdes_get_regs_len(chip, port); 1145 1146 return len; 1147 } 1148 1149 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1150 struct ethtool_regs *regs, void *_p) 1151 { 1152 struct mv88e6xxx_chip *chip = ds->priv; 1153 int err; 1154 u16 reg; 1155 u16 *p = _p; 1156 int i; 1157 1158 regs->version = chip->info->prod_num; 1159 1160 memset(p, 0xff, 32 * sizeof(u16)); 1161 1162 mv88e6xxx_reg_lock(chip); 1163 1164 for (i = 0; i < 32; i++) { 1165 1166 err = mv88e6xxx_port_read(chip, port, i, ®); 1167 if (!err) 1168 p[i] = reg; 1169 } 1170 1171 if (chip->info->ops->serdes_get_regs) 1172 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1173 1174 mv88e6xxx_reg_unlock(chip); 1175 } 1176 1177 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1178 struct ethtool_eee *e) 1179 { 1180 /* Nothing to do on the port's MAC */ 1181 return 0; 1182 } 1183 1184 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1185 struct ethtool_eee *e) 1186 { 1187 /* Nothing to do on the port's MAC */ 1188 return 0; 1189 } 1190 1191 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1192 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1193 { 1194 struct dsa_switch *ds = chip->ds; 1195 struct dsa_switch_tree *dst = ds->dst; 1196 struct net_device *br; 1197 struct dsa_port *dp; 1198 bool found = false; 1199 u16 pvlan; 1200 1201 list_for_each_entry(dp, &dst->ports, list) { 1202 if (dp->ds->index == dev && dp->index == port) { 1203 found = true; 1204 break; 1205 } 1206 } 1207 1208 /* Prevent frames from unknown switch or port */ 1209 if (!found) 1210 return 0; 1211 1212 /* Frames from DSA links and CPU ports can egress any local port */ 1213 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1214 return mv88e6xxx_port_mask(chip); 1215 1216 br = dp->bridge_dev; 1217 pvlan = 0; 1218 1219 /* Frames from user ports can egress any local DSA links and CPU ports, 1220 * as well as any local member of their bridge group. 1221 */ 1222 list_for_each_entry(dp, &dst->ports, list) 1223 if (dp->ds == ds && 1224 (dp->type == DSA_PORT_TYPE_CPU || 1225 dp->type == DSA_PORT_TYPE_DSA || 1226 (br && dp->bridge_dev == br))) 1227 pvlan |= BIT(dp->index); 1228 1229 return pvlan; 1230 } 1231 1232 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1233 { 1234 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1235 1236 /* prevent frames from going back out of the port they came in on */ 1237 output_ports &= ~BIT(port); 1238 1239 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1240 } 1241 1242 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1243 u8 state) 1244 { 1245 struct mv88e6xxx_chip *chip = ds->priv; 1246 int err; 1247 1248 mv88e6xxx_reg_lock(chip); 1249 err = mv88e6xxx_port_set_state(chip, port, state); 1250 mv88e6xxx_reg_unlock(chip); 1251 1252 if (err) 1253 dev_err(ds->dev, "p%d: failed to update state\n", port); 1254 } 1255 1256 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1257 { 1258 int err; 1259 1260 if (chip->info->ops->ieee_pri_map) { 1261 err = chip->info->ops->ieee_pri_map(chip); 1262 if (err) 1263 return err; 1264 } 1265 1266 if (chip->info->ops->ip_pri_map) { 1267 err = chip->info->ops->ip_pri_map(chip); 1268 if (err) 1269 return err; 1270 } 1271 1272 return 0; 1273 } 1274 1275 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1276 { 1277 struct dsa_switch *ds = chip->ds; 1278 int target, port; 1279 int err; 1280 1281 if (!chip->info->global2_addr) 1282 return 0; 1283 1284 /* Initialize the routing port to the 32 possible target devices */ 1285 for (target = 0; target < 32; target++) { 1286 port = dsa_routing_port(ds, target); 1287 if (port == ds->num_ports) 1288 port = 0x1f; 1289 1290 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1291 if (err) 1292 return err; 1293 } 1294 1295 if (chip->info->ops->set_cascade_port) { 1296 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1297 err = chip->info->ops->set_cascade_port(chip, port); 1298 if (err) 1299 return err; 1300 } 1301 1302 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1303 if (err) 1304 return err; 1305 1306 return 0; 1307 } 1308 1309 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 /* Clear all trunk masks and mapping */ 1312 if (chip->info->global2_addr) 1313 return mv88e6xxx_g2_trunk_clear(chip); 1314 1315 return 0; 1316 } 1317 1318 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1319 { 1320 if (chip->info->ops->rmu_disable) 1321 return chip->info->ops->rmu_disable(chip); 1322 1323 return 0; 1324 } 1325 1326 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1327 { 1328 if (chip->info->ops->pot_clear) 1329 return chip->info->ops->pot_clear(chip); 1330 1331 return 0; 1332 } 1333 1334 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1335 { 1336 if (chip->info->ops->mgmt_rsvd2cpu) 1337 return chip->info->ops->mgmt_rsvd2cpu(chip); 1338 1339 return 0; 1340 } 1341 1342 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1343 { 1344 int err; 1345 1346 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1347 if (err) 1348 return err; 1349 1350 /* The chips that have a "learn2all" bit in Global1, ATU 1351 * Control are precisely those whose port registers have a 1352 * Message Port bit in Port Control 1 and hence implement 1353 * ->port_setup_message_port. 1354 */ 1355 if (chip->info->ops->port_setup_message_port) { 1356 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1357 if (err) 1358 return err; 1359 } 1360 1361 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1362 } 1363 1364 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1365 { 1366 int port; 1367 int err; 1368 1369 if (!chip->info->ops->irl_init_all) 1370 return 0; 1371 1372 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1373 /* Disable ingress rate limiting by resetting all per port 1374 * ingress rate limit resources to their initial state. 1375 */ 1376 err = chip->info->ops->irl_init_all(chip, port); 1377 if (err) 1378 return err; 1379 } 1380 1381 return 0; 1382 } 1383 1384 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1385 { 1386 if (chip->info->ops->set_switch_mac) { 1387 u8 addr[ETH_ALEN]; 1388 1389 eth_random_addr(addr); 1390 1391 return chip->info->ops->set_switch_mac(chip, addr); 1392 } 1393 1394 return 0; 1395 } 1396 1397 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1398 { 1399 u16 pvlan = 0; 1400 1401 if (!mv88e6xxx_has_pvt(chip)) 1402 return 0; 1403 1404 /* Skip the local source device, which uses in-chip port VLAN */ 1405 if (dev != chip->ds->index) 1406 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1407 1408 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1409 } 1410 1411 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1412 { 1413 int dev, port; 1414 int err; 1415 1416 if (!mv88e6xxx_has_pvt(chip)) 1417 return 0; 1418 1419 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1420 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1421 */ 1422 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1423 if (err) 1424 return err; 1425 1426 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1427 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1428 err = mv88e6xxx_pvt_map(chip, dev, port); 1429 if (err) 1430 return err; 1431 } 1432 } 1433 1434 return 0; 1435 } 1436 1437 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1438 { 1439 struct mv88e6xxx_chip *chip = ds->priv; 1440 int err; 1441 1442 mv88e6xxx_reg_lock(chip); 1443 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1444 mv88e6xxx_reg_unlock(chip); 1445 1446 if (err) 1447 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1448 } 1449 1450 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1451 { 1452 if (!mv88e6xxx_max_vid(chip)) 1453 return 0; 1454 1455 return mv88e6xxx_g1_vtu_flush(chip); 1456 } 1457 1458 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1459 struct mv88e6xxx_vtu_entry *entry) 1460 { 1461 if (!chip->info->ops->vtu_getnext) 1462 return -EOPNOTSUPP; 1463 1464 return chip->info->ops->vtu_getnext(chip, entry); 1465 } 1466 1467 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1468 struct mv88e6xxx_vtu_entry *entry) 1469 { 1470 if (!chip->info->ops->vtu_loadpurge) 1471 return -EOPNOTSUPP; 1472 1473 return chip->info->ops->vtu_loadpurge(chip, entry); 1474 } 1475 1476 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1477 { 1478 struct mv88e6xxx_vtu_entry vlan; 1479 int i, err; 1480 u16 fid; 1481 1482 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1483 1484 /* Set every FID bit used by the (un)bridged ports */ 1485 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1486 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1487 if (err) 1488 return err; 1489 1490 set_bit(fid, fid_bitmap); 1491 } 1492 1493 /* Set every FID bit used by the VLAN entries */ 1494 vlan.vid = mv88e6xxx_max_vid(chip); 1495 vlan.valid = false; 1496 1497 do { 1498 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1499 if (err) 1500 return err; 1501 1502 if (!vlan.valid) 1503 break; 1504 1505 set_bit(vlan.fid, fid_bitmap); 1506 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 1507 1508 return 0; 1509 } 1510 1511 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1512 { 1513 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1514 int err; 1515 1516 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1517 if (err) 1518 return err; 1519 1520 /* The reset value 0x000 is used to indicate that multiple address 1521 * databases are not needed. Return the next positive available. 1522 */ 1523 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1524 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1525 return -ENOSPC; 1526 1527 /* Clear the database */ 1528 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1529 } 1530 1531 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1532 u16 vid_begin, u16 vid_end) 1533 { 1534 struct mv88e6xxx_chip *chip = ds->priv; 1535 struct mv88e6xxx_vtu_entry vlan; 1536 int i, err; 1537 1538 /* DSA and CPU ports have to be members of multiple vlans */ 1539 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1540 return 0; 1541 1542 if (!vid_begin) 1543 return -EOPNOTSUPP; 1544 1545 vlan.vid = vid_begin - 1; 1546 vlan.valid = false; 1547 1548 do { 1549 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1550 if (err) 1551 return err; 1552 1553 if (!vlan.valid) 1554 break; 1555 1556 if (vlan.vid > vid_end) 1557 break; 1558 1559 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1560 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1561 continue; 1562 1563 if (!dsa_to_port(ds, i)->slave) 1564 continue; 1565 1566 if (vlan.member[i] == 1567 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1568 continue; 1569 1570 if (dsa_to_port(ds, i)->bridge_dev == 1571 dsa_to_port(ds, port)->bridge_dev) 1572 break; /* same bridge, check next VLAN */ 1573 1574 if (!dsa_to_port(ds, i)->bridge_dev) 1575 continue; 1576 1577 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1578 port, vlan.vid, i, 1579 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1580 return -EOPNOTSUPP; 1581 } 1582 } while (vlan.vid < vid_end); 1583 1584 return 0; 1585 } 1586 1587 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1588 bool vlan_filtering, 1589 struct switchdev_trans *trans) 1590 { 1591 struct mv88e6xxx_chip *chip = ds->priv; 1592 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1593 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1594 int err; 1595 1596 if (switchdev_trans_ph_prepare(trans)) 1597 return mv88e6xxx_max_vid(chip) ? 0 : -EOPNOTSUPP; 1598 1599 mv88e6xxx_reg_lock(chip); 1600 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1601 mv88e6xxx_reg_unlock(chip); 1602 1603 return err; 1604 } 1605 1606 static int 1607 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1608 const struct switchdev_obj_port_vlan *vlan) 1609 { 1610 struct mv88e6xxx_chip *chip = ds->priv; 1611 int err; 1612 1613 if (!mv88e6xxx_max_vid(chip)) 1614 return -EOPNOTSUPP; 1615 1616 /* If the requested port doesn't belong to the same bridge as the VLAN 1617 * members, do not support it (yet) and fallback to software VLAN. 1618 */ 1619 mv88e6xxx_reg_lock(chip); 1620 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1621 vlan->vid_end); 1622 mv88e6xxx_reg_unlock(chip); 1623 1624 /* We don't need any dynamic resource from the kernel (yet), 1625 * so skip the prepare phase. 1626 */ 1627 return err; 1628 } 1629 1630 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1631 const unsigned char *addr, u16 vid, 1632 u8 state) 1633 { 1634 struct mv88e6xxx_atu_entry entry; 1635 struct mv88e6xxx_vtu_entry vlan; 1636 u16 fid; 1637 int err; 1638 1639 /* Null VLAN ID corresponds to the port private database */ 1640 if (vid == 0) { 1641 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1642 if (err) 1643 return err; 1644 } else { 1645 vlan.vid = vid - 1; 1646 vlan.valid = false; 1647 1648 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1649 if (err) 1650 return err; 1651 1652 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1653 if (vlan.vid != vid || !vlan.valid) 1654 return -EOPNOTSUPP; 1655 1656 fid = vlan.fid; 1657 } 1658 1659 entry.state = 0; 1660 ether_addr_copy(entry.mac, addr); 1661 eth_addr_dec(entry.mac); 1662 1663 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1664 if (err) 1665 return err; 1666 1667 /* Initialize a fresh ATU entry if it isn't found */ 1668 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1669 memset(&entry, 0, sizeof(entry)); 1670 ether_addr_copy(entry.mac, addr); 1671 } 1672 1673 /* Purge the ATU entry only if no port is using it anymore */ 1674 if (!state) { 1675 entry.portvec &= ~BIT(port); 1676 if (!entry.portvec) 1677 entry.state = 0; 1678 } else { 1679 entry.portvec |= BIT(port); 1680 entry.state = state; 1681 } 1682 1683 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1684 } 1685 1686 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1687 const struct mv88e6xxx_policy *policy) 1688 { 1689 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1690 enum mv88e6xxx_policy_action action = policy->action; 1691 const u8 *addr = policy->addr; 1692 u16 vid = policy->vid; 1693 u8 state; 1694 int err; 1695 int id; 1696 1697 if (!chip->info->ops->port_set_policy) 1698 return -EOPNOTSUPP; 1699 1700 switch (mapping) { 1701 case MV88E6XXX_POLICY_MAPPING_DA: 1702 case MV88E6XXX_POLICY_MAPPING_SA: 1703 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1704 state = 0; /* Dissociate the port and address */ 1705 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1706 is_multicast_ether_addr(addr)) 1707 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1708 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1709 is_unicast_ether_addr(addr)) 1710 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1711 else 1712 return -EOPNOTSUPP; 1713 1714 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1715 state); 1716 if (err) 1717 return err; 1718 break; 1719 default: 1720 return -EOPNOTSUPP; 1721 } 1722 1723 /* Skip the port's policy clearing if the mapping is still in use */ 1724 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1725 idr_for_each_entry(&chip->policies, policy, id) 1726 if (policy->port == port && 1727 policy->mapping == mapping && 1728 policy->action != action) 1729 return 0; 1730 1731 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1732 } 1733 1734 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1735 struct ethtool_rx_flow_spec *fs) 1736 { 1737 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1738 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1739 enum mv88e6xxx_policy_mapping mapping; 1740 enum mv88e6xxx_policy_action action; 1741 struct mv88e6xxx_policy *policy; 1742 u16 vid = 0; 1743 u8 *addr; 1744 int err; 1745 int id; 1746 1747 if (fs->location != RX_CLS_LOC_ANY) 1748 return -EINVAL; 1749 1750 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1751 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1752 else 1753 return -EOPNOTSUPP; 1754 1755 switch (fs->flow_type & ~FLOW_EXT) { 1756 case ETHER_FLOW: 1757 if (!is_zero_ether_addr(mac_mask->h_dest) && 1758 is_zero_ether_addr(mac_mask->h_source)) { 1759 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1760 addr = mac_entry->h_dest; 1761 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1762 !is_zero_ether_addr(mac_mask->h_source)) { 1763 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1764 addr = mac_entry->h_source; 1765 } else { 1766 /* Cannot support DA and SA mapping in the same rule */ 1767 return -EOPNOTSUPP; 1768 } 1769 break; 1770 default: 1771 return -EOPNOTSUPP; 1772 } 1773 1774 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1775 if (fs->m_ext.vlan_tci != htons(0xffff)) 1776 return -EOPNOTSUPP; 1777 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1778 } 1779 1780 idr_for_each_entry(&chip->policies, policy, id) { 1781 if (policy->port == port && policy->mapping == mapping && 1782 policy->action == action && policy->vid == vid && 1783 ether_addr_equal(policy->addr, addr)) 1784 return -EEXIST; 1785 } 1786 1787 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1788 if (!policy) 1789 return -ENOMEM; 1790 1791 fs->location = 0; 1792 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1793 GFP_KERNEL); 1794 if (err) { 1795 devm_kfree(chip->dev, policy); 1796 return err; 1797 } 1798 1799 memcpy(&policy->fs, fs, sizeof(*fs)); 1800 ether_addr_copy(policy->addr, addr); 1801 policy->mapping = mapping; 1802 policy->action = action; 1803 policy->port = port; 1804 policy->vid = vid; 1805 1806 err = mv88e6xxx_policy_apply(chip, port, policy); 1807 if (err) { 1808 idr_remove(&chip->policies, fs->location); 1809 devm_kfree(chip->dev, policy); 1810 return err; 1811 } 1812 1813 return 0; 1814 } 1815 1816 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1817 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1818 { 1819 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1820 struct mv88e6xxx_chip *chip = ds->priv; 1821 struct mv88e6xxx_policy *policy; 1822 int err; 1823 int id; 1824 1825 mv88e6xxx_reg_lock(chip); 1826 1827 switch (rxnfc->cmd) { 1828 case ETHTOOL_GRXCLSRLCNT: 1829 rxnfc->data = 0; 1830 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1831 rxnfc->rule_cnt = 0; 1832 idr_for_each_entry(&chip->policies, policy, id) 1833 if (policy->port == port) 1834 rxnfc->rule_cnt++; 1835 err = 0; 1836 break; 1837 case ETHTOOL_GRXCLSRULE: 1838 err = -ENOENT; 1839 policy = idr_find(&chip->policies, fs->location); 1840 if (policy) { 1841 memcpy(fs, &policy->fs, sizeof(*fs)); 1842 err = 0; 1843 } 1844 break; 1845 case ETHTOOL_GRXCLSRLALL: 1846 rxnfc->data = 0; 1847 rxnfc->rule_cnt = 0; 1848 idr_for_each_entry(&chip->policies, policy, id) 1849 if (policy->port == port) 1850 rule_locs[rxnfc->rule_cnt++] = id; 1851 err = 0; 1852 break; 1853 default: 1854 err = -EOPNOTSUPP; 1855 break; 1856 } 1857 1858 mv88e6xxx_reg_unlock(chip); 1859 1860 return err; 1861 } 1862 1863 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1864 struct ethtool_rxnfc *rxnfc) 1865 { 1866 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1867 struct mv88e6xxx_chip *chip = ds->priv; 1868 struct mv88e6xxx_policy *policy; 1869 int err; 1870 1871 mv88e6xxx_reg_lock(chip); 1872 1873 switch (rxnfc->cmd) { 1874 case ETHTOOL_SRXCLSRLINS: 1875 err = mv88e6xxx_policy_insert(chip, port, fs); 1876 break; 1877 case ETHTOOL_SRXCLSRLDEL: 1878 err = -ENOENT; 1879 policy = idr_remove(&chip->policies, fs->location); 1880 if (policy) { 1881 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1882 err = mv88e6xxx_policy_apply(chip, port, policy); 1883 devm_kfree(chip->dev, policy); 1884 } 1885 break; 1886 default: 1887 err = -EOPNOTSUPP; 1888 break; 1889 } 1890 1891 mv88e6xxx_reg_unlock(chip); 1892 1893 return err; 1894 } 1895 1896 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1897 u16 vid) 1898 { 1899 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1900 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1901 1902 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1903 } 1904 1905 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1906 { 1907 int port; 1908 int err; 1909 1910 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1911 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1912 if (err) 1913 return err; 1914 } 1915 1916 return 0; 1917 } 1918 1919 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1920 u16 vid, u8 member, bool warn) 1921 { 1922 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1923 struct mv88e6xxx_vtu_entry vlan; 1924 int i, err; 1925 1926 if (!vid) 1927 return -EOPNOTSUPP; 1928 1929 vlan.vid = vid - 1; 1930 vlan.valid = false; 1931 1932 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1933 if (err) 1934 return err; 1935 1936 if (vlan.vid != vid || !vlan.valid) { 1937 memset(&vlan, 0, sizeof(vlan)); 1938 1939 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1940 if (err) 1941 return err; 1942 1943 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1944 if (i == port) 1945 vlan.member[i] = member; 1946 else 1947 vlan.member[i] = non_member; 1948 1949 vlan.vid = vid; 1950 vlan.valid = true; 1951 1952 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1953 if (err) 1954 return err; 1955 1956 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1957 if (err) 1958 return err; 1959 } else if (vlan.member[port] != member) { 1960 vlan.member[port] = member; 1961 1962 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1963 if (err) 1964 return err; 1965 } else if (warn) { 1966 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1967 port, vid); 1968 } 1969 1970 return 0; 1971 } 1972 1973 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1974 const struct switchdev_obj_port_vlan *vlan) 1975 { 1976 struct mv88e6xxx_chip *chip = ds->priv; 1977 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1978 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1979 bool warn; 1980 u8 member; 1981 u16 vid; 1982 1983 if (!mv88e6xxx_max_vid(chip)) 1984 return; 1985 1986 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1987 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1988 else if (untagged) 1989 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1990 else 1991 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1992 1993 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 1994 * and then the CPU port. Do not warn for duplicates for the CPU port. 1995 */ 1996 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 1997 1998 mv88e6xxx_reg_lock(chip); 1999 2000 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 2001 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn)) 2002 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2003 vid, untagged ? 'u' : 't'); 2004 2005 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 2006 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 2007 vlan->vid_end); 2008 2009 mv88e6xxx_reg_unlock(chip); 2010 } 2011 2012 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2013 int port, u16 vid) 2014 { 2015 struct mv88e6xxx_vtu_entry vlan; 2016 int i, err; 2017 2018 if (!vid) 2019 return -EOPNOTSUPP; 2020 2021 vlan.vid = vid - 1; 2022 vlan.valid = false; 2023 2024 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2025 if (err) 2026 return err; 2027 2028 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2029 * tell switchdev that this VLAN is likely handled in software. 2030 */ 2031 if (vlan.vid != vid || !vlan.valid || 2032 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2033 return -EOPNOTSUPP; 2034 2035 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2036 2037 /* keep the VLAN unless all ports are excluded */ 2038 vlan.valid = false; 2039 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2040 if (vlan.member[i] != 2041 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2042 vlan.valid = true; 2043 break; 2044 } 2045 } 2046 2047 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2048 if (err) 2049 return err; 2050 2051 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2052 } 2053 2054 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2055 const struct switchdev_obj_port_vlan *vlan) 2056 { 2057 struct mv88e6xxx_chip *chip = ds->priv; 2058 u16 pvid, vid; 2059 int err = 0; 2060 2061 if (!mv88e6xxx_max_vid(chip)) 2062 return -EOPNOTSUPP; 2063 2064 mv88e6xxx_reg_lock(chip); 2065 2066 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2067 if (err) 2068 goto unlock; 2069 2070 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2071 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 2072 if (err) 2073 goto unlock; 2074 2075 if (vid == pvid) { 2076 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2077 if (err) 2078 goto unlock; 2079 } 2080 } 2081 2082 unlock: 2083 mv88e6xxx_reg_unlock(chip); 2084 2085 return err; 2086 } 2087 2088 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2089 const unsigned char *addr, u16 vid) 2090 { 2091 struct mv88e6xxx_chip *chip = ds->priv; 2092 int err; 2093 2094 mv88e6xxx_reg_lock(chip); 2095 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2096 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2097 mv88e6xxx_reg_unlock(chip); 2098 2099 return err; 2100 } 2101 2102 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2103 const unsigned char *addr, u16 vid) 2104 { 2105 struct mv88e6xxx_chip *chip = ds->priv; 2106 int err; 2107 2108 mv88e6xxx_reg_lock(chip); 2109 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2110 mv88e6xxx_reg_unlock(chip); 2111 2112 return err; 2113 } 2114 2115 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2116 u16 fid, u16 vid, int port, 2117 dsa_fdb_dump_cb_t *cb, void *data) 2118 { 2119 struct mv88e6xxx_atu_entry addr; 2120 bool is_static; 2121 int err; 2122 2123 addr.state = 0; 2124 eth_broadcast_addr(addr.mac); 2125 2126 do { 2127 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2128 if (err) 2129 return err; 2130 2131 if (!addr.state) 2132 break; 2133 2134 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2135 continue; 2136 2137 if (!is_unicast_ether_addr(addr.mac)) 2138 continue; 2139 2140 is_static = (addr.state == 2141 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2142 err = cb(addr.mac, vid, is_static, data); 2143 if (err) 2144 return err; 2145 } while (!is_broadcast_ether_addr(addr.mac)); 2146 2147 return err; 2148 } 2149 2150 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2151 dsa_fdb_dump_cb_t *cb, void *data) 2152 { 2153 struct mv88e6xxx_vtu_entry vlan; 2154 u16 fid; 2155 int err; 2156 2157 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2158 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2159 if (err) 2160 return err; 2161 2162 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2163 if (err) 2164 return err; 2165 2166 /* Dump VLANs' Filtering Information Databases */ 2167 vlan.vid = mv88e6xxx_max_vid(chip); 2168 vlan.valid = false; 2169 2170 do { 2171 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2172 if (err) 2173 return err; 2174 2175 if (!vlan.valid) 2176 break; 2177 2178 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2179 cb, data); 2180 if (err) 2181 return err; 2182 } while (vlan.vid < mv88e6xxx_max_vid(chip)); 2183 2184 return err; 2185 } 2186 2187 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2188 dsa_fdb_dump_cb_t *cb, void *data) 2189 { 2190 struct mv88e6xxx_chip *chip = ds->priv; 2191 int err; 2192 2193 mv88e6xxx_reg_lock(chip); 2194 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2195 mv88e6xxx_reg_unlock(chip); 2196 2197 return err; 2198 } 2199 2200 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2201 struct net_device *br) 2202 { 2203 struct dsa_switch *ds = chip->ds; 2204 struct dsa_switch_tree *dst = ds->dst; 2205 struct dsa_port *dp; 2206 int err; 2207 2208 list_for_each_entry(dp, &dst->ports, list) { 2209 if (dp->bridge_dev == br) { 2210 if (dp->ds == ds) { 2211 /* This is a local bridge group member, 2212 * remap its Port VLAN Map. 2213 */ 2214 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2215 if (err) 2216 return err; 2217 } else { 2218 /* This is an external bridge group member, 2219 * remap its cross-chip Port VLAN Table entry. 2220 */ 2221 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2222 dp->index); 2223 if (err) 2224 return err; 2225 } 2226 } 2227 } 2228 2229 return 0; 2230 } 2231 2232 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2233 struct net_device *br) 2234 { 2235 struct mv88e6xxx_chip *chip = ds->priv; 2236 int err; 2237 2238 mv88e6xxx_reg_lock(chip); 2239 err = mv88e6xxx_bridge_map(chip, br); 2240 mv88e6xxx_reg_unlock(chip); 2241 2242 return err; 2243 } 2244 2245 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2246 struct net_device *br) 2247 { 2248 struct mv88e6xxx_chip *chip = ds->priv; 2249 2250 mv88e6xxx_reg_lock(chip); 2251 if (mv88e6xxx_bridge_map(chip, br) || 2252 mv88e6xxx_port_vlan_map(chip, port)) 2253 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2254 mv88e6xxx_reg_unlock(chip); 2255 } 2256 2257 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2258 int tree_index, int sw_index, 2259 int port, struct net_device *br) 2260 { 2261 struct mv88e6xxx_chip *chip = ds->priv; 2262 int err; 2263 2264 if (tree_index != ds->dst->index) 2265 return 0; 2266 2267 mv88e6xxx_reg_lock(chip); 2268 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2269 mv88e6xxx_reg_unlock(chip); 2270 2271 return err; 2272 } 2273 2274 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2275 int tree_index, int sw_index, 2276 int port, struct net_device *br) 2277 { 2278 struct mv88e6xxx_chip *chip = ds->priv; 2279 2280 if (tree_index != ds->dst->index) 2281 return; 2282 2283 mv88e6xxx_reg_lock(chip); 2284 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2285 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2286 mv88e6xxx_reg_unlock(chip); 2287 } 2288 2289 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2290 { 2291 if (chip->info->ops->reset) 2292 return chip->info->ops->reset(chip); 2293 2294 return 0; 2295 } 2296 2297 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2298 { 2299 struct gpio_desc *gpiod = chip->reset; 2300 2301 /* If there is a GPIO connected to the reset pin, toggle it */ 2302 if (gpiod) { 2303 gpiod_set_value_cansleep(gpiod, 1); 2304 usleep_range(10000, 20000); 2305 gpiod_set_value_cansleep(gpiod, 0); 2306 usleep_range(10000, 20000); 2307 2308 mv88e6xxx_g1_wait_eeprom_done(chip); 2309 } 2310 } 2311 2312 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2313 { 2314 int i, err; 2315 2316 /* Set all ports to the Disabled state */ 2317 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2318 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2319 if (err) 2320 return err; 2321 } 2322 2323 /* Wait for transmit queues to drain, 2324 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2325 */ 2326 usleep_range(2000, 4000); 2327 2328 return 0; 2329 } 2330 2331 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2332 { 2333 int err; 2334 2335 err = mv88e6xxx_disable_ports(chip); 2336 if (err) 2337 return err; 2338 2339 mv88e6xxx_hardware_reset(chip); 2340 2341 return mv88e6xxx_software_reset(chip); 2342 } 2343 2344 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2345 enum mv88e6xxx_frame_mode frame, 2346 enum mv88e6xxx_egress_mode egress, u16 etype) 2347 { 2348 int err; 2349 2350 if (!chip->info->ops->port_set_frame_mode) 2351 return -EOPNOTSUPP; 2352 2353 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2354 if (err) 2355 return err; 2356 2357 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2358 if (err) 2359 return err; 2360 2361 if (chip->info->ops->port_set_ether_type) 2362 return chip->info->ops->port_set_ether_type(chip, port, etype); 2363 2364 return 0; 2365 } 2366 2367 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2368 { 2369 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2370 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2371 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2372 } 2373 2374 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2375 { 2376 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2377 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2378 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2379 } 2380 2381 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2382 { 2383 return mv88e6xxx_set_port_mode(chip, port, 2384 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2385 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2386 ETH_P_EDSA); 2387 } 2388 2389 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2390 { 2391 if (dsa_is_dsa_port(chip->ds, port)) 2392 return mv88e6xxx_set_port_mode_dsa(chip, port); 2393 2394 if (dsa_is_user_port(chip->ds, port)) 2395 return mv88e6xxx_set_port_mode_normal(chip, port); 2396 2397 /* Setup CPU port mode depending on its supported tag format */ 2398 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2399 return mv88e6xxx_set_port_mode_dsa(chip, port); 2400 2401 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2402 return mv88e6xxx_set_port_mode_edsa(chip, port); 2403 2404 return -EINVAL; 2405 } 2406 2407 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2408 { 2409 bool message = dsa_is_dsa_port(chip->ds, port); 2410 2411 return mv88e6xxx_port_set_message_port(chip, port, message); 2412 } 2413 2414 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2415 { 2416 struct dsa_switch *ds = chip->ds; 2417 bool flood; 2418 2419 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2420 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2421 if (chip->info->ops->port_set_egress_floods) 2422 return chip->info->ops->port_set_egress_floods(chip, port, 2423 flood, flood); 2424 2425 return 0; 2426 } 2427 2428 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2429 { 2430 struct mv88e6xxx_port *mvp = dev_id; 2431 struct mv88e6xxx_chip *chip = mvp->chip; 2432 irqreturn_t ret = IRQ_NONE; 2433 int port = mvp->port; 2434 u8 lane; 2435 2436 mv88e6xxx_reg_lock(chip); 2437 lane = mv88e6xxx_serdes_get_lane(chip, port); 2438 if (lane) 2439 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2440 mv88e6xxx_reg_unlock(chip); 2441 2442 return ret; 2443 } 2444 2445 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2446 u8 lane) 2447 { 2448 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2449 unsigned int irq; 2450 int err; 2451 2452 /* Nothing to request if this SERDES port has no IRQ */ 2453 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2454 if (!irq) 2455 return 0; 2456 2457 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2458 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2459 2460 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2461 mv88e6xxx_reg_unlock(chip); 2462 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2463 IRQF_ONESHOT, dev_id->serdes_irq_name, 2464 dev_id); 2465 mv88e6xxx_reg_lock(chip); 2466 if (err) 2467 return err; 2468 2469 dev_id->serdes_irq = irq; 2470 2471 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2472 } 2473 2474 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2475 u8 lane) 2476 { 2477 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2478 unsigned int irq = dev_id->serdes_irq; 2479 int err; 2480 2481 /* Nothing to free if no IRQ has been requested */ 2482 if (!irq) 2483 return 0; 2484 2485 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2486 2487 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2488 mv88e6xxx_reg_unlock(chip); 2489 free_irq(irq, dev_id); 2490 mv88e6xxx_reg_lock(chip); 2491 2492 dev_id->serdes_irq = 0; 2493 2494 return err; 2495 } 2496 2497 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2498 bool on) 2499 { 2500 u8 lane; 2501 int err; 2502 2503 lane = mv88e6xxx_serdes_get_lane(chip, port); 2504 if (!lane) 2505 return 0; 2506 2507 if (on) { 2508 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2509 if (err) 2510 return err; 2511 2512 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2513 } else { 2514 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2515 if (err) 2516 return err; 2517 2518 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2519 } 2520 2521 return err; 2522 } 2523 2524 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2525 { 2526 struct dsa_switch *ds = chip->ds; 2527 int upstream_port; 2528 int err; 2529 2530 upstream_port = dsa_upstream_port(ds, port); 2531 if (chip->info->ops->port_set_upstream_port) { 2532 err = chip->info->ops->port_set_upstream_port(chip, port, 2533 upstream_port); 2534 if (err) 2535 return err; 2536 } 2537 2538 if (port == upstream_port) { 2539 if (chip->info->ops->set_cpu_port) { 2540 err = chip->info->ops->set_cpu_port(chip, 2541 upstream_port); 2542 if (err) 2543 return err; 2544 } 2545 2546 if (chip->info->ops->set_egress_port) { 2547 err = chip->info->ops->set_egress_port(chip, 2548 MV88E6XXX_EGRESS_DIR_INGRESS, 2549 upstream_port); 2550 if (err) 2551 return err; 2552 2553 err = chip->info->ops->set_egress_port(chip, 2554 MV88E6XXX_EGRESS_DIR_EGRESS, 2555 upstream_port); 2556 if (err) 2557 return err; 2558 } 2559 } 2560 2561 return 0; 2562 } 2563 2564 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2565 { 2566 struct dsa_switch *ds = chip->ds; 2567 int err; 2568 u16 reg; 2569 2570 chip->ports[port].chip = chip; 2571 chip->ports[port].port = port; 2572 2573 /* MAC Forcing register: don't force link, speed, duplex or flow control 2574 * state to any particular values on physical ports, but force the CPU 2575 * port and all DSA ports to their maximum bandwidth and full duplex. 2576 */ 2577 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2578 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2579 SPEED_MAX, DUPLEX_FULL, 2580 PAUSE_OFF, 2581 PHY_INTERFACE_MODE_NA); 2582 else 2583 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2584 SPEED_UNFORCED, DUPLEX_UNFORCED, 2585 PAUSE_ON, 2586 PHY_INTERFACE_MODE_NA); 2587 if (err) 2588 return err; 2589 2590 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2591 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2592 * tunneling, determine priority by looking at 802.1p and IP 2593 * priority fields (IP prio has precedence), and set STP state 2594 * to Forwarding. 2595 * 2596 * If this is the CPU link, use DSA or EDSA tagging depending 2597 * on which tagging mode was configured. 2598 * 2599 * If this is a link to another switch, use DSA tagging mode. 2600 * 2601 * If this is the upstream port for this switch, enable 2602 * forwarding of unknown unicasts and multicasts. 2603 */ 2604 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2605 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2606 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2607 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2608 if (err) 2609 return err; 2610 2611 err = mv88e6xxx_setup_port_mode(chip, port); 2612 if (err) 2613 return err; 2614 2615 err = mv88e6xxx_setup_egress_floods(chip, port); 2616 if (err) 2617 return err; 2618 2619 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2620 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2621 * untagged frames on this port, do a destination address lookup on all 2622 * received packets as usual, disable ARP mirroring and don't send a 2623 * copy of all transmitted/received frames on this port to the CPU. 2624 */ 2625 err = mv88e6xxx_port_set_map_da(chip, port); 2626 if (err) 2627 return err; 2628 2629 err = mv88e6xxx_setup_upstream_port(chip, port); 2630 if (err) 2631 return err; 2632 2633 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2634 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2635 if (err) 2636 return err; 2637 2638 if (chip->info->ops->port_set_jumbo_size) { 2639 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2640 if (err) 2641 return err; 2642 } 2643 2644 /* Port Association Vector: when learning source addresses 2645 * of packets, add the address to the address database using 2646 * a port bitmap that has only the bit for this port set and 2647 * the other bits clear. 2648 */ 2649 reg = 1 << port; 2650 /* Disable learning for CPU port */ 2651 if (dsa_is_cpu_port(ds, port)) 2652 reg = 0; 2653 2654 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2655 reg); 2656 if (err) 2657 return err; 2658 2659 /* Egress rate control 2: disable egress rate control. */ 2660 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2661 0x0000); 2662 if (err) 2663 return err; 2664 2665 if (chip->info->ops->port_pause_limit) { 2666 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2667 if (err) 2668 return err; 2669 } 2670 2671 if (chip->info->ops->port_disable_learn_limit) { 2672 err = chip->info->ops->port_disable_learn_limit(chip, port); 2673 if (err) 2674 return err; 2675 } 2676 2677 if (chip->info->ops->port_disable_pri_override) { 2678 err = chip->info->ops->port_disable_pri_override(chip, port); 2679 if (err) 2680 return err; 2681 } 2682 2683 if (chip->info->ops->port_tag_remap) { 2684 err = chip->info->ops->port_tag_remap(chip, port); 2685 if (err) 2686 return err; 2687 } 2688 2689 if (chip->info->ops->port_egress_rate_limiting) { 2690 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2691 if (err) 2692 return err; 2693 } 2694 2695 if (chip->info->ops->port_setup_message_port) { 2696 err = chip->info->ops->port_setup_message_port(chip, port); 2697 if (err) 2698 return err; 2699 } 2700 2701 /* Port based VLAN map: give each port the same default address 2702 * database, and allow bidirectional communication between the 2703 * CPU and DSA port(s), and the other ports. 2704 */ 2705 err = mv88e6xxx_port_set_fid(chip, port, 0); 2706 if (err) 2707 return err; 2708 2709 err = mv88e6xxx_port_vlan_map(chip, port); 2710 if (err) 2711 return err; 2712 2713 /* Default VLAN ID and priority: don't set a default VLAN 2714 * ID, and set the default packet priority to zero. 2715 */ 2716 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2717 } 2718 2719 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 2720 { 2721 struct mv88e6xxx_chip *chip = ds->priv; 2722 2723 if (chip->info->ops->port_set_jumbo_size) 2724 return 10240; 2725 else if (chip->info->ops->set_max_frame_size) 2726 return 1632; 2727 return 1522; 2728 } 2729 2730 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 2731 { 2732 struct mv88e6xxx_chip *chip = ds->priv; 2733 int ret = 0; 2734 2735 mv88e6xxx_reg_lock(chip); 2736 if (chip->info->ops->port_set_jumbo_size) 2737 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 2738 else if (chip->info->ops->set_max_frame_size) 2739 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 2740 else 2741 if (new_mtu > 1522) 2742 ret = -EINVAL; 2743 mv88e6xxx_reg_unlock(chip); 2744 2745 return ret; 2746 } 2747 2748 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2749 struct phy_device *phydev) 2750 { 2751 struct mv88e6xxx_chip *chip = ds->priv; 2752 int err; 2753 2754 mv88e6xxx_reg_lock(chip); 2755 err = mv88e6xxx_serdes_power(chip, port, true); 2756 mv88e6xxx_reg_unlock(chip); 2757 2758 return err; 2759 } 2760 2761 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2762 { 2763 struct mv88e6xxx_chip *chip = ds->priv; 2764 2765 mv88e6xxx_reg_lock(chip); 2766 if (mv88e6xxx_serdes_power(chip, port, false)) 2767 dev_err(chip->dev, "failed to power off SERDES\n"); 2768 mv88e6xxx_reg_unlock(chip); 2769 } 2770 2771 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2772 unsigned int ageing_time) 2773 { 2774 struct mv88e6xxx_chip *chip = ds->priv; 2775 int err; 2776 2777 mv88e6xxx_reg_lock(chip); 2778 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2779 mv88e6xxx_reg_unlock(chip); 2780 2781 return err; 2782 } 2783 2784 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2785 { 2786 int err; 2787 2788 /* Initialize the statistics unit */ 2789 if (chip->info->ops->stats_set_histogram) { 2790 err = chip->info->ops->stats_set_histogram(chip); 2791 if (err) 2792 return err; 2793 } 2794 2795 return mv88e6xxx_g1_stats_clear(chip); 2796 } 2797 2798 /* Check if the errata has already been applied. */ 2799 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2800 { 2801 int port; 2802 int err; 2803 u16 val; 2804 2805 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2806 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2807 if (err) { 2808 dev_err(chip->dev, 2809 "Error reading hidden register: %d\n", err); 2810 return false; 2811 } 2812 if (val != 0x01c0) 2813 return false; 2814 } 2815 2816 return true; 2817 } 2818 2819 /* The 6390 copper ports have an errata which require poking magic 2820 * values into undocumented hidden registers and then performing a 2821 * software reset. 2822 */ 2823 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2824 { 2825 int port; 2826 int err; 2827 2828 if (mv88e6390_setup_errata_applied(chip)) 2829 return 0; 2830 2831 /* Set the ports into blocking mode */ 2832 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2833 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2834 if (err) 2835 return err; 2836 } 2837 2838 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2839 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2840 if (err) 2841 return err; 2842 } 2843 2844 return mv88e6xxx_software_reset(chip); 2845 } 2846 2847 static void mv88e6xxx_teardown(struct dsa_switch *ds) 2848 { 2849 mv88e6xxx_teardown_devlink_params(ds); 2850 dsa_devlink_resources_unregister(ds); 2851 mv88e6xxx_teardown_devlink_regions(ds); 2852 } 2853 2854 static int mv88e6xxx_setup(struct dsa_switch *ds) 2855 { 2856 struct mv88e6xxx_chip *chip = ds->priv; 2857 u8 cmode; 2858 int err; 2859 int i; 2860 2861 chip->ds = ds; 2862 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2863 ds->configure_vlan_while_not_filtering = true; 2864 2865 mv88e6xxx_reg_lock(chip); 2866 2867 if (chip->info->ops->setup_errata) { 2868 err = chip->info->ops->setup_errata(chip); 2869 if (err) 2870 goto unlock; 2871 } 2872 2873 /* Cache the cmode of each port. */ 2874 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2875 if (chip->info->ops->port_get_cmode) { 2876 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2877 if (err) 2878 goto unlock; 2879 2880 chip->ports[i].cmode = cmode; 2881 } 2882 } 2883 2884 /* Setup Switch Port Registers */ 2885 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2886 if (dsa_is_unused_port(ds, i)) 2887 continue; 2888 2889 /* Prevent the use of an invalid port. */ 2890 if (mv88e6xxx_is_invalid_port(chip, i)) { 2891 dev_err(chip->dev, "port %d is invalid\n", i); 2892 err = -EINVAL; 2893 goto unlock; 2894 } 2895 2896 err = mv88e6xxx_setup_port(chip, i); 2897 if (err) 2898 goto unlock; 2899 } 2900 2901 err = mv88e6xxx_irl_setup(chip); 2902 if (err) 2903 goto unlock; 2904 2905 err = mv88e6xxx_mac_setup(chip); 2906 if (err) 2907 goto unlock; 2908 2909 err = mv88e6xxx_phy_setup(chip); 2910 if (err) 2911 goto unlock; 2912 2913 err = mv88e6xxx_vtu_setup(chip); 2914 if (err) 2915 goto unlock; 2916 2917 err = mv88e6xxx_pvt_setup(chip); 2918 if (err) 2919 goto unlock; 2920 2921 err = mv88e6xxx_atu_setup(chip); 2922 if (err) 2923 goto unlock; 2924 2925 err = mv88e6xxx_broadcast_setup(chip, 0); 2926 if (err) 2927 goto unlock; 2928 2929 err = mv88e6xxx_pot_setup(chip); 2930 if (err) 2931 goto unlock; 2932 2933 err = mv88e6xxx_rmu_setup(chip); 2934 if (err) 2935 goto unlock; 2936 2937 err = mv88e6xxx_rsvd2cpu_setup(chip); 2938 if (err) 2939 goto unlock; 2940 2941 err = mv88e6xxx_trunk_setup(chip); 2942 if (err) 2943 goto unlock; 2944 2945 err = mv88e6xxx_devmap_setup(chip); 2946 if (err) 2947 goto unlock; 2948 2949 err = mv88e6xxx_pri_setup(chip); 2950 if (err) 2951 goto unlock; 2952 2953 /* Setup PTP Hardware Clock and timestamping */ 2954 if (chip->info->ptp_support) { 2955 err = mv88e6xxx_ptp_setup(chip); 2956 if (err) 2957 goto unlock; 2958 2959 err = mv88e6xxx_hwtstamp_setup(chip); 2960 if (err) 2961 goto unlock; 2962 } 2963 2964 err = mv88e6xxx_stats_setup(chip); 2965 if (err) 2966 goto unlock; 2967 2968 unlock: 2969 mv88e6xxx_reg_unlock(chip); 2970 2971 if (err) 2972 return err; 2973 2974 /* Have to be called without holding the register lock, since 2975 * they take the devlink lock, and we later take the locks in 2976 * the reverse order when getting/setting parameters or 2977 * resource occupancy. 2978 */ 2979 err = mv88e6xxx_setup_devlink_resources(ds); 2980 if (err) 2981 return err; 2982 2983 err = mv88e6xxx_setup_devlink_params(ds); 2984 if (err) 2985 goto out_resources; 2986 2987 err = mv88e6xxx_setup_devlink_regions(ds); 2988 if (err) 2989 goto out_params; 2990 2991 return 0; 2992 2993 out_params: 2994 mv88e6xxx_teardown_devlink_params(ds); 2995 out_resources: 2996 dsa_devlink_resources_unregister(ds); 2997 2998 return err; 2999 } 3000 3001 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3002 { 3003 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3004 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3005 u16 val; 3006 int err; 3007 3008 if (!chip->info->ops->phy_read) 3009 return -EOPNOTSUPP; 3010 3011 mv88e6xxx_reg_lock(chip); 3012 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3013 mv88e6xxx_reg_unlock(chip); 3014 3015 if (reg == MII_PHYSID2) { 3016 /* Some internal PHYs don't have a model number. */ 3017 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3018 /* Then there is the 6165 family. It gets is 3019 * PHYs correct. But it can also have two 3020 * SERDES interfaces in the PHY address 3021 * space. And these don't have a model 3022 * number. But they are not PHYs, so we don't 3023 * want to give them something a PHY driver 3024 * will recognise. 3025 * 3026 * Use the mv88e6390 family model number 3027 * instead, for anything which really could be 3028 * a PHY, 3029 */ 3030 if (!(val & 0x3f0)) 3031 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3032 } 3033 3034 return err ? err : val; 3035 } 3036 3037 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3038 { 3039 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3040 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3041 int err; 3042 3043 if (!chip->info->ops->phy_write) 3044 return -EOPNOTSUPP; 3045 3046 mv88e6xxx_reg_lock(chip); 3047 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3048 mv88e6xxx_reg_unlock(chip); 3049 3050 return err; 3051 } 3052 3053 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3054 struct device_node *np, 3055 bool external) 3056 { 3057 static int index; 3058 struct mv88e6xxx_mdio_bus *mdio_bus; 3059 struct mii_bus *bus; 3060 int err; 3061 3062 if (external) { 3063 mv88e6xxx_reg_lock(chip); 3064 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3065 mv88e6xxx_reg_unlock(chip); 3066 3067 if (err) 3068 return err; 3069 } 3070 3071 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3072 if (!bus) 3073 return -ENOMEM; 3074 3075 mdio_bus = bus->priv; 3076 mdio_bus->bus = bus; 3077 mdio_bus->chip = chip; 3078 INIT_LIST_HEAD(&mdio_bus->list); 3079 mdio_bus->external = external; 3080 3081 if (np) { 3082 bus->name = np->full_name; 3083 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3084 } else { 3085 bus->name = "mv88e6xxx SMI"; 3086 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3087 } 3088 3089 bus->read = mv88e6xxx_mdio_read; 3090 bus->write = mv88e6xxx_mdio_write; 3091 bus->parent = chip->dev; 3092 3093 if (!external) { 3094 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3095 if (err) 3096 return err; 3097 } 3098 3099 err = of_mdiobus_register(bus, np); 3100 if (err) { 3101 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3102 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3103 return err; 3104 } 3105 3106 if (external) 3107 list_add_tail(&mdio_bus->list, &chip->mdios); 3108 else 3109 list_add(&mdio_bus->list, &chip->mdios); 3110 3111 return 0; 3112 } 3113 3114 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3115 3116 { 3117 struct mv88e6xxx_mdio_bus *mdio_bus; 3118 struct mii_bus *bus; 3119 3120 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3121 bus = mdio_bus->bus; 3122 3123 if (!mdio_bus->external) 3124 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3125 3126 mdiobus_unregister(bus); 3127 } 3128 } 3129 3130 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3131 struct device_node *np) 3132 { 3133 struct device_node *child; 3134 int err; 3135 3136 /* Always register one mdio bus for the internal/default mdio 3137 * bus. This maybe represented in the device tree, but is 3138 * optional. 3139 */ 3140 child = of_get_child_by_name(np, "mdio"); 3141 err = mv88e6xxx_mdio_register(chip, child, false); 3142 if (err) 3143 return err; 3144 3145 /* Walk the device tree, and see if there are any other nodes 3146 * which say they are compatible with the external mdio 3147 * bus. 3148 */ 3149 for_each_available_child_of_node(np, child) { 3150 if (of_device_is_compatible( 3151 child, "marvell,mv88e6xxx-mdio-external")) { 3152 err = mv88e6xxx_mdio_register(chip, child, true); 3153 if (err) { 3154 mv88e6xxx_mdios_unregister(chip); 3155 of_node_put(child); 3156 return err; 3157 } 3158 } 3159 } 3160 3161 return 0; 3162 } 3163 3164 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3165 { 3166 struct mv88e6xxx_chip *chip = ds->priv; 3167 3168 return chip->eeprom_len; 3169 } 3170 3171 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3172 struct ethtool_eeprom *eeprom, u8 *data) 3173 { 3174 struct mv88e6xxx_chip *chip = ds->priv; 3175 int err; 3176 3177 if (!chip->info->ops->get_eeprom) 3178 return -EOPNOTSUPP; 3179 3180 mv88e6xxx_reg_lock(chip); 3181 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3182 mv88e6xxx_reg_unlock(chip); 3183 3184 if (err) 3185 return err; 3186 3187 eeprom->magic = 0xc3ec4951; 3188 3189 return 0; 3190 } 3191 3192 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3193 struct ethtool_eeprom *eeprom, u8 *data) 3194 { 3195 struct mv88e6xxx_chip *chip = ds->priv; 3196 int err; 3197 3198 if (!chip->info->ops->set_eeprom) 3199 return -EOPNOTSUPP; 3200 3201 if (eeprom->magic != 0xc3ec4951) 3202 return -EINVAL; 3203 3204 mv88e6xxx_reg_lock(chip); 3205 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3206 mv88e6xxx_reg_unlock(chip); 3207 3208 return err; 3209 } 3210 3211 static const struct mv88e6xxx_ops mv88e6085_ops = { 3212 /* MV88E6XXX_FAMILY_6097 */ 3213 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3214 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3215 .irl_init_all = mv88e6352_g2_irl_init_all, 3216 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3217 .phy_read = mv88e6185_phy_ppu_read, 3218 .phy_write = mv88e6185_phy_ppu_write, 3219 .port_set_link = mv88e6xxx_port_set_link, 3220 .port_sync_link = mv88e6xxx_port_sync_link, 3221 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3222 .port_tag_remap = mv88e6095_port_tag_remap, 3223 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3224 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3225 .port_set_ether_type = mv88e6351_port_set_ether_type, 3226 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3227 .port_pause_limit = mv88e6097_port_pause_limit, 3228 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3229 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3230 .port_get_cmode = mv88e6185_port_get_cmode, 3231 .port_setup_message_port = mv88e6xxx_setup_message_port, 3232 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3233 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3234 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3235 .stats_get_strings = mv88e6095_stats_get_strings, 3236 .stats_get_stats = mv88e6095_stats_get_stats, 3237 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3238 .set_egress_port = mv88e6095_g1_set_egress_port, 3239 .watchdog_ops = &mv88e6097_watchdog_ops, 3240 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3241 .pot_clear = mv88e6xxx_g2_pot_clear, 3242 .ppu_enable = mv88e6185_g1_ppu_enable, 3243 .ppu_disable = mv88e6185_g1_ppu_disable, 3244 .reset = mv88e6185_g1_reset, 3245 .rmu_disable = mv88e6085_g1_rmu_disable, 3246 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3247 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3248 .phylink_validate = mv88e6185_phylink_validate, 3249 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3250 }; 3251 3252 static const struct mv88e6xxx_ops mv88e6095_ops = { 3253 /* MV88E6XXX_FAMILY_6095 */ 3254 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3255 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3256 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3257 .phy_read = mv88e6185_phy_ppu_read, 3258 .phy_write = mv88e6185_phy_ppu_write, 3259 .port_set_link = mv88e6xxx_port_set_link, 3260 .port_sync_link = mv88e6185_port_sync_link, 3261 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3262 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3263 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3264 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3265 .port_get_cmode = mv88e6185_port_get_cmode, 3266 .port_setup_message_port = mv88e6xxx_setup_message_port, 3267 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3268 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3269 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3270 .stats_get_strings = mv88e6095_stats_get_strings, 3271 .stats_get_stats = mv88e6095_stats_get_stats, 3272 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3273 .serdes_power = mv88e6185_serdes_power, 3274 .serdes_get_lane = mv88e6185_serdes_get_lane, 3275 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3276 .ppu_enable = mv88e6185_g1_ppu_enable, 3277 .ppu_disable = mv88e6185_g1_ppu_disable, 3278 .reset = mv88e6185_g1_reset, 3279 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3280 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3281 .phylink_validate = mv88e6185_phylink_validate, 3282 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3283 }; 3284 3285 static const struct mv88e6xxx_ops mv88e6097_ops = { 3286 /* MV88E6XXX_FAMILY_6097 */ 3287 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3288 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3289 .irl_init_all = mv88e6352_g2_irl_init_all, 3290 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3291 .phy_read = mv88e6xxx_g2_smi_phy_read, 3292 .phy_write = mv88e6xxx_g2_smi_phy_write, 3293 .port_set_link = mv88e6xxx_port_set_link, 3294 .port_sync_link = mv88e6185_port_sync_link, 3295 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3296 .port_tag_remap = mv88e6095_port_tag_remap, 3297 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3298 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3299 .port_set_ether_type = mv88e6351_port_set_ether_type, 3300 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3301 .port_pause_limit = mv88e6097_port_pause_limit, 3302 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3303 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3304 .port_get_cmode = mv88e6185_port_get_cmode, 3305 .port_setup_message_port = mv88e6xxx_setup_message_port, 3306 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3307 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3308 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3309 .stats_get_strings = mv88e6095_stats_get_strings, 3310 .stats_get_stats = mv88e6095_stats_get_stats, 3311 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3312 .set_egress_port = mv88e6095_g1_set_egress_port, 3313 .watchdog_ops = &mv88e6097_watchdog_ops, 3314 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3315 .serdes_power = mv88e6185_serdes_power, 3316 .serdes_get_lane = mv88e6185_serdes_get_lane, 3317 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3318 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3319 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3320 .serdes_irq_status = mv88e6097_serdes_irq_status, 3321 .pot_clear = mv88e6xxx_g2_pot_clear, 3322 .reset = mv88e6352_g1_reset, 3323 .rmu_disable = mv88e6085_g1_rmu_disable, 3324 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3325 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3326 .phylink_validate = mv88e6185_phylink_validate, 3327 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3328 }; 3329 3330 static const struct mv88e6xxx_ops mv88e6123_ops = { 3331 /* MV88E6XXX_FAMILY_6165 */ 3332 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3333 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3334 .irl_init_all = mv88e6352_g2_irl_init_all, 3335 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3336 .phy_read = mv88e6xxx_g2_smi_phy_read, 3337 .phy_write = mv88e6xxx_g2_smi_phy_write, 3338 .port_set_link = mv88e6xxx_port_set_link, 3339 .port_sync_link = mv88e6xxx_port_sync_link, 3340 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3341 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3342 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3343 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3344 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3345 .port_get_cmode = mv88e6185_port_get_cmode, 3346 .port_setup_message_port = mv88e6xxx_setup_message_port, 3347 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3348 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3349 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3350 .stats_get_strings = mv88e6095_stats_get_strings, 3351 .stats_get_stats = mv88e6095_stats_get_stats, 3352 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3353 .set_egress_port = mv88e6095_g1_set_egress_port, 3354 .watchdog_ops = &mv88e6097_watchdog_ops, 3355 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3356 .pot_clear = mv88e6xxx_g2_pot_clear, 3357 .reset = mv88e6352_g1_reset, 3358 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3359 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3360 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3361 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3362 .phylink_validate = mv88e6185_phylink_validate, 3363 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3364 }; 3365 3366 static const struct mv88e6xxx_ops mv88e6131_ops = { 3367 /* MV88E6XXX_FAMILY_6185 */ 3368 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3369 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3370 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3371 .phy_read = mv88e6185_phy_ppu_read, 3372 .phy_write = mv88e6185_phy_ppu_write, 3373 .port_set_link = mv88e6xxx_port_set_link, 3374 .port_sync_link = mv88e6xxx_port_sync_link, 3375 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3376 .port_tag_remap = mv88e6095_port_tag_remap, 3377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3378 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3379 .port_set_ether_type = mv88e6351_port_set_ether_type, 3380 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3381 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3383 .port_pause_limit = mv88e6097_port_pause_limit, 3384 .port_set_pause = mv88e6185_port_set_pause, 3385 .port_get_cmode = mv88e6185_port_get_cmode, 3386 .port_setup_message_port = mv88e6xxx_setup_message_port, 3387 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3388 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3389 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3390 .stats_get_strings = mv88e6095_stats_get_strings, 3391 .stats_get_stats = mv88e6095_stats_get_stats, 3392 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3393 .set_egress_port = mv88e6095_g1_set_egress_port, 3394 .watchdog_ops = &mv88e6097_watchdog_ops, 3395 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3396 .ppu_enable = mv88e6185_g1_ppu_enable, 3397 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3398 .ppu_disable = mv88e6185_g1_ppu_disable, 3399 .reset = mv88e6185_g1_reset, 3400 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3401 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3402 .phylink_validate = mv88e6185_phylink_validate, 3403 }; 3404 3405 static const struct mv88e6xxx_ops mv88e6141_ops = { 3406 /* MV88E6XXX_FAMILY_6341 */ 3407 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3408 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3409 .irl_init_all = mv88e6352_g2_irl_init_all, 3410 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3411 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3412 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3413 .phy_read = mv88e6xxx_g2_smi_phy_read, 3414 .phy_write = mv88e6xxx_g2_smi_phy_write, 3415 .port_set_link = mv88e6xxx_port_set_link, 3416 .port_sync_link = mv88e6xxx_port_sync_link, 3417 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3418 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3419 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3420 .port_tag_remap = mv88e6095_port_tag_remap, 3421 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3422 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3423 .port_set_ether_type = mv88e6351_port_set_ether_type, 3424 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3425 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3426 .port_pause_limit = mv88e6097_port_pause_limit, 3427 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3428 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3429 .port_get_cmode = mv88e6352_port_get_cmode, 3430 .port_set_cmode = mv88e6341_port_set_cmode, 3431 .port_setup_message_port = mv88e6xxx_setup_message_port, 3432 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3433 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3434 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3435 .stats_get_strings = mv88e6320_stats_get_strings, 3436 .stats_get_stats = mv88e6390_stats_get_stats, 3437 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3438 .set_egress_port = mv88e6390_g1_set_egress_port, 3439 .watchdog_ops = &mv88e6390_watchdog_ops, 3440 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3441 .pot_clear = mv88e6xxx_g2_pot_clear, 3442 .reset = mv88e6352_g1_reset, 3443 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3444 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3445 .serdes_power = mv88e6390_serdes_power, 3446 .serdes_get_lane = mv88e6341_serdes_get_lane, 3447 /* Check status register pause & lpa register */ 3448 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3449 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3450 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3451 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3452 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3453 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3454 .serdes_irq_status = mv88e6390_serdes_irq_status, 3455 .gpio_ops = &mv88e6352_gpio_ops, 3456 .phylink_validate = mv88e6341_phylink_validate, 3457 }; 3458 3459 static const struct mv88e6xxx_ops mv88e6161_ops = { 3460 /* MV88E6XXX_FAMILY_6165 */ 3461 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3462 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3463 .irl_init_all = mv88e6352_g2_irl_init_all, 3464 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3465 .phy_read = mv88e6xxx_g2_smi_phy_read, 3466 .phy_write = mv88e6xxx_g2_smi_phy_write, 3467 .port_set_link = mv88e6xxx_port_set_link, 3468 .port_sync_link = mv88e6xxx_port_sync_link, 3469 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3470 .port_tag_remap = mv88e6095_port_tag_remap, 3471 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3472 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3473 .port_set_ether_type = mv88e6351_port_set_ether_type, 3474 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3475 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3476 .port_pause_limit = mv88e6097_port_pause_limit, 3477 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3478 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3479 .port_get_cmode = mv88e6185_port_get_cmode, 3480 .port_setup_message_port = mv88e6xxx_setup_message_port, 3481 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3482 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3483 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3484 .stats_get_strings = mv88e6095_stats_get_strings, 3485 .stats_get_stats = mv88e6095_stats_get_stats, 3486 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3487 .set_egress_port = mv88e6095_g1_set_egress_port, 3488 .watchdog_ops = &mv88e6097_watchdog_ops, 3489 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3490 .pot_clear = mv88e6xxx_g2_pot_clear, 3491 .reset = mv88e6352_g1_reset, 3492 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3493 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3494 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3495 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3496 .avb_ops = &mv88e6165_avb_ops, 3497 .ptp_ops = &mv88e6165_ptp_ops, 3498 .phylink_validate = mv88e6185_phylink_validate, 3499 }; 3500 3501 static const struct mv88e6xxx_ops mv88e6165_ops = { 3502 /* MV88E6XXX_FAMILY_6165 */ 3503 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3504 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3505 .irl_init_all = mv88e6352_g2_irl_init_all, 3506 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3507 .phy_read = mv88e6165_phy_read, 3508 .phy_write = mv88e6165_phy_write, 3509 .port_set_link = mv88e6xxx_port_set_link, 3510 .port_sync_link = mv88e6xxx_port_sync_link, 3511 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3512 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3513 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3514 .port_get_cmode = mv88e6185_port_get_cmode, 3515 .port_setup_message_port = mv88e6xxx_setup_message_port, 3516 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3517 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3518 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3519 .stats_get_strings = mv88e6095_stats_get_strings, 3520 .stats_get_stats = mv88e6095_stats_get_stats, 3521 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3522 .set_egress_port = mv88e6095_g1_set_egress_port, 3523 .watchdog_ops = &mv88e6097_watchdog_ops, 3524 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3525 .pot_clear = mv88e6xxx_g2_pot_clear, 3526 .reset = mv88e6352_g1_reset, 3527 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3528 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3529 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3530 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3531 .avb_ops = &mv88e6165_avb_ops, 3532 .ptp_ops = &mv88e6165_ptp_ops, 3533 .phylink_validate = mv88e6185_phylink_validate, 3534 }; 3535 3536 static const struct mv88e6xxx_ops mv88e6171_ops = { 3537 /* MV88E6XXX_FAMILY_6351 */ 3538 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3539 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3540 .irl_init_all = mv88e6352_g2_irl_init_all, 3541 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3542 .phy_read = mv88e6xxx_g2_smi_phy_read, 3543 .phy_write = mv88e6xxx_g2_smi_phy_write, 3544 .port_set_link = mv88e6xxx_port_set_link, 3545 .port_sync_link = mv88e6xxx_port_sync_link, 3546 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3547 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3548 .port_tag_remap = mv88e6095_port_tag_remap, 3549 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3550 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3551 .port_set_ether_type = mv88e6351_port_set_ether_type, 3552 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3553 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3554 .port_pause_limit = mv88e6097_port_pause_limit, 3555 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3556 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3557 .port_get_cmode = mv88e6352_port_get_cmode, 3558 .port_setup_message_port = mv88e6xxx_setup_message_port, 3559 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3560 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3561 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3562 .stats_get_strings = mv88e6095_stats_get_strings, 3563 .stats_get_stats = mv88e6095_stats_get_stats, 3564 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3565 .set_egress_port = mv88e6095_g1_set_egress_port, 3566 .watchdog_ops = &mv88e6097_watchdog_ops, 3567 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3568 .pot_clear = mv88e6xxx_g2_pot_clear, 3569 .reset = mv88e6352_g1_reset, 3570 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3571 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3572 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3573 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3574 .phylink_validate = mv88e6185_phylink_validate, 3575 }; 3576 3577 static const struct mv88e6xxx_ops mv88e6172_ops = { 3578 /* MV88E6XXX_FAMILY_6352 */ 3579 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3580 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3581 .irl_init_all = mv88e6352_g2_irl_init_all, 3582 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3583 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3584 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3585 .phy_read = mv88e6xxx_g2_smi_phy_read, 3586 .phy_write = mv88e6xxx_g2_smi_phy_write, 3587 .port_set_link = mv88e6xxx_port_set_link, 3588 .port_sync_link = mv88e6xxx_port_sync_link, 3589 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3590 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3591 .port_tag_remap = mv88e6095_port_tag_remap, 3592 .port_set_policy = mv88e6352_port_set_policy, 3593 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3594 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3595 .port_set_ether_type = mv88e6351_port_set_ether_type, 3596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3598 .port_pause_limit = mv88e6097_port_pause_limit, 3599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3601 .port_get_cmode = mv88e6352_port_get_cmode, 3602 .port_setup_message_port = mv88e6xxx_setup_message_port, 3603 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3604 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3605 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3606 .stats_get_strings = mv88e6095_stats_get_strings, 3607 .stats_get_stats = mv88e6095_stats_get_stats, 3608 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3609 .set_egress_port = mv88e6095_g1_set_egress_port, 3610 .watchdog_ops = &mv88e6097_watchdog_ops, 3611 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3612 .pot_clear = mv88e6xxx_g2_pot_clear, 3613 .reset = mv88e6352_g1_reset, 3614 .rmu_disable = mv88e6352_g1_rmu_disable, 3615 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3616 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3617 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3618 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3619 .serdes_get_lane = mv88e6352_serdes_get_lane, 3620 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3621 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3622 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3623 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3624 .serdes_power = mv88e6352_serdes_power, 3625 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3626 .serdes_get_regs = mv88e6352_serdes_get_regs, 3627 .gpio_ops = &mv88e6352_gpio_ops, 3628 .phylink_validate = mv88e6352_phylink_validate, 3629 }; 3630 3631 static const struct mv88e6xxx_ops mv88e6175_ops = { 3632 /* MV88E6XXX_FAMILY_6351 */ 3633 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3634 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3635 .irl_init_all = mv88e6352_g2_irl_init_all, 3636 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3637 .phy_read = mv88e6xxx_g2_smi_phy_read, 3638 .phy_write = mv88e6xxx_g2_smi_phy_write, 3639 .port_set_link = mv88e6xxx_port_set_link, 3640 .port_sync_link = mv88e6xxx_port_sync_link, 3641 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3642 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3643 .port_tag_remap = mv88e6095_port_tag_remap, 3644 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3645 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3646 .port_set_ether_type = mv88e6351_port_set_ether_type, 3647 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3648 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3649 .port_pause_limit = mv88e6097_port_pause_limit, 3650 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3651 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3652 .port_get_cmode = mv88e6352_port_get_cmode, 3653 .port_setup_message_port = mv88e6xxx_setup_message_port, 3654 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3655 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3656 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3657 .stats_get_strings = mv88e6095_stats_get_strings, 3658 .stats_get_stats = mv88e6095_stats_get_stats, 3659 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3660 .set_egress_port = mv88e6095_g1_set_egress_port, 3661 .watchdog_ops = &mv88e6097_watchdog_ops, 3662 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3663 .pot_clear = mv88e6xxx_g2_pot_clear, 3664 .reset = mv88e6352_g1_reset, 3665 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3666 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3667 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3668 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3669 .phylink_validate = mv88e6185_phylink_validate, 3670 }; 3671 3672 static const struct mv88e6xxx_ops mv88e6176_ops = { 3673 /* MV88E6XXX_FAMILY_6352 */ 3674 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3675 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3676 .irl_init_all = mv88e6352_g2_irl_init_all, 3677 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3678 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3679 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3680 .phy_read = mv88e6xxx_g2_smi_phy_read, 3681 .phy_write = mv88e6xxx_g2_smi_phy_write, 3682 .port_set_link = mv88e6xxx_port_set_link, 3683 .port_sync_link = mv88e6xxx_port_sync_link, 3684 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3685 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3686 .port_tag_remap = mv88e6095_port_tag_remap, 3687 .port_set_policy = mv88e6352_port_set_policy, 3688 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3689 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3690 .port_set_ether_type = mv88e6351_port_set_ether_type, 3691 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3692 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3693 .port_pause_limit = mv88e6097_port_pause_limit, 3694 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3695 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3696 .port_get_cmode = mv88e6352_port_get_cmode, 3697 .port_setup_message_port = mv88e6xxx_setup_message_port, 3698 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3699 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3700 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3701 .stats_get_strings = mv88e6095_stats_get_strings, 3702 .stats_get_stats = mv88e6095_stats_get_stats, 3703 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3704 .set_egress_port = mv88e6095_g1_set_egress_port, 3705 .watchdog_ops = &mv88e6097_watchdog_ops, 3706 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3707 .pot_clear = mv88e6xxx_g2_pot_clear, 3708 .reset = mv88e6352_g1_reset, 3709 .rmu_disable = mv88e6352_g1_rmu_disable, 3710 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3711 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3712 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3713 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3714 .serdes_get_lane = mv88e6352_serdes_get_lane, 3715 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3716 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3717 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3718 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3719 .serdes_power = mv88e6352_serdes_power, 3720 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3721 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3722 .serdes_irq_status = mv88e6352_serdes_irq_status, 3723 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3724 .serdes_get_regs = mv88e6352_serdes_get_regs, 3725 .gpio_ops = &mv88e6352_gpio_ops, 3726 .phylink_validate = mv88e6352_phylink_validate, 3727 }; 3728 3729 static const struct mv88e6xxx_ops mv88e6185_ops = { 3730 /* MV88E6XXX_FAMILY_6185 */ 3731 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3732 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3733 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3734 .phy_read = mv88e6185_phy_ppu_read, 3735 .phy_write = mv88e6185_phy_ppu_write, 3736 .port_set_link = mv88e6xxx_port_set_link, 3737 .port_sync_link = mv88e6185_port_sync_link, 3738 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3739 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3740 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3741 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3742 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3743 .port_set_pause = mv88e6185_port_set_pause, 3744 .port_get_cmode = mv88e6185_port_get_cmode, 3745 .port_setup_message_port = mv88e6xxx_setup_message_port, 3746 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3747 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3748 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3749 .stats_get_strings = mv88e6095_stats_get_strings, 3750 .stats_get_stats = mv88e6095_stats_get_stats, 3751 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3752 .set_egress_port = mv88e6095_g1_set_egress_port, 3753 .watchdog_ops = &mv88e6097_watchdog_ops, 3754 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3755 .serdes_power = mv88e6185_serdes_power, 3756 .serdes_get_lane = mv88e6185_serdes_get_lane, 3757 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3758 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3759 .ppu_enable = mv88e6185_g1_ppu_enable, 3760 .ppu_disable = mv88e6185_g1_ppu_disable, 3761 .reset = mv88e6185_g1_reset, 3762 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3763 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3764 .phylink_validate = mv88e6185_phylink_validate, 3765 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3766 }; 3767 3768 static const struct mv88e6xxx_ops mv88e6190_ops = { 3769 /* MV88E6XXX_FAMILY_6390 */ 3770 .setup_errata = mv88e6390_setup_errata, 3771 .irl_init_all = mv88e6390_g2_irl_init_all, 3772 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3773 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3774 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3775 .phy_read = mv88e6xxx_g2_smi_phy_read, 3776 .phy_write = mv88e6xxx_g2_smi_phy_write, 3777 .port_set_link = mv88e6xxx_port_set_link, 3778 .port_sync_link = mv88e6xxx_port_sync_link, 3779 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3780 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3781 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3782 .port_tag_remap = mv88e6390_port_tag_remap, 3783 .port_set_policy = mv88e6352_port_set_policy, 3784 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3785 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3786 .port_set_ether_type = mv88e6351_port_set_ether_type, 3787 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3788 .port_pause_limit = mv88e6390_port_pause_limit, 3789 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3790 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3791 .port_get_cmode = mv88e6352_port_get_cmode, 3792 .port_set_cmode = mv88e6390_port_set_cmode, 3793 .port_setup_message_port = mv88e6xxx_setup_message_port, 3794 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3795 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3796 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3797 .stats_get_strings = mv88e6320_stats_get_strings, 3798 .stats_get_stats = mv88e6390_stats_get_stats, 3799 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3800 .set_egress_port = mv88e6390_g1_set_egress_port, 3801 .watchdog_ops = &mv88e6390_watchdog_ops, 3802 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3803 .pot_clear = mv88e6xxx_g2_pot_clear, 3804 .reset = mv88e6352_g1_reset, 3805 .rmu_disable = mv88e6390_g1_rmu_disable, 3806 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3807 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3808 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3809 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3810 .serdes_power = mv88e6390_serdes_power, 3811 .serdes_get_lane = mv88e6390_serdes_get_lane, 3812 /* Check status register pause & lpa register */ 3813 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3814 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3815 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3816 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3817 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3818 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3819 .serdes_irq_status = mv88e6390_serdes_irq_status, 3820 .serdes_get_strings = mv88e6390_serdes_get_strings, 3821 .serdes_get_stats = mv88e6390_serdes_get_stats, 3822 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3823 .serdes_get_regs = mv88e6390_serdes_get_regs, 3824 .gpio_ops = &mv88e6352_gpio_ops, 3825 .phylink_validate = mv88e6390_phylink_validate, 3826 }; 3827 3828 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3829 /* MV88E6XXX_FAMILY_6390 */ 3830 .setup_errata = mv88e6390_setup_errata, 3831 .irl_init_all = mv88e6390_g2_irl_init_all, 3832 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3833 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3834 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3835 .phy_read = mv88e6xxx_g2_smi_phy_read, 3836 .phy_write = mv88e6xxx_g2_smi_phy_write, 3837 .port_set_link = mv88e6xxx_port_set_link, 3838 .port_sync_link = mv88e6xxx_port_sync_link, 3839 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3840 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 3841 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3842 .port_tag_remap = mv88e6390_port_tag_remap, 3843 .port_set_policy = mv88e6352_port_set_policy, 3844 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3845 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3846 .port_set_ether_type = mv88e6351_port_set_ether_type, 3847 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3848 .port_pause_limit = mv88e6390_port_pause_limit, 3849 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3850 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3851 .port_get_cmode = mv88e6352_port_get_cmode, 3852 .port_set_cmode = mv88e6390x_port_set_cmode, 3853 .port_setup_message_port = mv88e6xxx_setup_message_port, 3854 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3855 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3856 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3857 .stats_get_strings = mv88e6320_stats_get_strings, 3858 .stats_get_stats = mv88e6390_stats_get_stats, 3859 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3860 .set_egress_port = mv88e6390_g1_set_egress_port, 3861 .watchdog_ops = &mv88e6390_watchdog_ops, 3862 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3863 .pot_clear = mv88e6xxx_g2_pot_clear, 3864 .reset = mv88e6352_g1_reset, 3865 .rmu_disable = mv88e6390_g1_rmu_disable, 3866 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3867 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3868 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3869 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3870 .serdes_power = mv88e6390_serdes_power, 3871 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3872 /* Check status register pause & lpa register */ 3873 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3874 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3875 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3876 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3877 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3878 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3879 .serdes_irq_status = mv88e6390_serdes_irq_status, 3880 .serdes_get_strings = mv88e6390_serdes_get_strings, 3881 .serdes_get_stats = mv88e6390_serdes_get_stats, 3882 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3883 .serdes_get_regs = mv88e6390_serdes_get_regs, 3884 .gpio_ops = &mv88e6352_gpio_ops, 3885 .phylink_validate = mv88e6390x_phylink_validate, 3886 }; 3887 3888 static const struct mv88e6xxx_ops mv88e6191_ops = { 3889 /* MV88E6XXX_FAMILY_6390 */ 3890 .setup_errata = mv88e6390_setup_errata, 3891 .irl_init_all = mv88e6390_g2_irl_init_all, 3892 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3893 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3894 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3895 .phy_read = mv88e6xxx_g2_smi_phy_read, 3896 .phy_write = mv88e6xxx_g2_smi_phy_write, 3897 .port_set_link = mv88e6xxx_port_set_link, 3898 .port_sync_link = mv88e6xxx_port_sync_link, 3899 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3900 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3901 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3902 .port_tag_remap = mv88e6390_port_tag_remap, 3903 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3904 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3905 .port_set_ether_type = mv88e6351_port_set_ether_type, 3906 .port_pause_limit = mv88e6390_port_pause_limit, 3907 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3908 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3909 .port_get_cmode = mv88e6352_port_get_cmode, 3910 .port_set_cmode = mv88e6390_port_set_cmode, 3911 .port_setup_message_port = mv88e6xxx_setup_message_port, 3912 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3913 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3914 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3915 .stats_get_strings = mv88e6320_stats_get_strings, 3916 .stats_get_stats = mv88e6390_stats_get_stats, 3917 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3918 .set_egress_port = mv88e6390_g1_set_egress_port, 3919 .watchdog_ops = &mv88e6390_watchdog_ops, 3920 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3921 .pot_clear = mv88e6xxx_g2_pot_clear, 3922 .reset = mv88e6352_g1_reset, 3923 .rmu_disable = mv88e6390_g1_rmu_disable, 3924 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3925 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3926 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3927 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3928 .serdes_power = mv88e6390_serdes_power, 3929 .serdes_get_lane = mv88e6390_serdes_get_lane, 3930 /* Check status register pause & lpa register */ 3931 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3932 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3933 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3934 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3935 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3936 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3937 .serdes_irq_status = mv88e6390_serdes_irq_status, 3938 .serdes_get_strings = mv88e6390_serdes_get_strings, 3939 .serdes_get_stats = mv88e6390_serdes_get_stats, 3940 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3941 .serdes_get_regs = mv88e6390_serdes_get_regs, 3942 .avb_ops = &mv88e6390_avb_ops, 3943 .ptp_ops = &mv88e6352_ptp_ops, 3944 .phylink_validate = mv88e6390_phylink_validate, 3945 }; 3946 3947 static const struct mv88e6xxx_ops mv88e6240_ops = { 3948 /* MV88E6XXX_FAMILY_6352 */ 3949 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3950 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3951 .irl_init_all = mv88e6352_g2_irl_init_all, 3952 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3953 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3954 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3955 .phy_read = mv88e6xxx_g2_smi_phy_read, 3956 .phy_write = mv88e6xxx_g2_smi_phy_write, 3957 .port_set_link = mv88e6xxx_port_set_link, 3958 .port_sync_link = mv88e6xxx_port_sync_link, 3959 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3960 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3961 .port_tag_remap = mv88e6095_port_tag_remap, 3962 .port_set_policy = mv88e6352_port_set_policy, 3963 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3964 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3965 .port_set_ether_type = mv88e6351_port_set_ether_type, 3966 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3967 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3968 .port_pause_limit = mv88e6097_port_pause_limit, 3969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3971 .port_get_cmode = mv88e6352_port_get_cmode, 3972 .port_setup_message_port = mv88e6xxx_setup_message_port, 3973 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3974 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3975 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3976 .stats_get_strings = mv88e6095_stats_get_strings, 3977 .stats_get_stats = mv88e6095_stats_get_stats, 3978 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3979 .set_egress_port = mv88e6095_g1_set_egress_port, 3980 .watchdog_ops = &mv88e6097_watchdog_ops, 3981 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3982 .pot_clear = mv88e6xxx_g2_pot_clear, 3983 .reset = mv88e6352_g1_reset, 3984 .rmu_disable = mv88e6352_g1_rmu_disable, 3985 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3986 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3987 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3988 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3989 .serdes_get_lane = mv88e6352_serdes_get_lane, 3990 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3991 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3992 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3993 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3994 .serdes_power = mv88e6352_serdes_power, 3995 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3996 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3997 .serdes_irq_status = mv88e6352_serdes_irq_status, 3998 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3999 .serdes_get_regs = mv88e6352_serdes_get_regs, 4000 .gpio_ops = &mv88e6352_gpio_ops, 4001 .avb_ops = &mv88e6352_avb_ops, 4002 .ptp_ops = &mv88e6352_ptp_ops, 4003 .phylink_validate = mv88e6352_phylink_validate, 4004 }; 4005 4006 static const struct mv88e6xxx_ops mv88e6250_ops = { 4007 /* MV88E6XXX_FAMILY_6250 */ 4008 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4009 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4010 .irl_init_all = mv88e6352_g2_irl_init_all, 4011 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4012 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4013 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4014 .phy_read = mv88e6xxx_g2_smi_phy_read, 4015 .phy_write = mv88e6xxx_g2_smi_phy_write, 4016 .port_set_link = mv88e6xxx_port_set_link, 4017 .port_sync_link = mv88e6xxx_port_sync_link, 4018 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4019 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4020 .port_tag_remap = mv88e6095_port_tag_remap, 4021 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4022 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4023 .port_set_ether_type = mv88e6351_port_set_ether_type, 4024 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4025 .port_pause_limit = mv88e6097_port_pause_limit, 4026 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4027 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4028 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4029 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4030 .stats_get_strings = mv88e6250_stats_get_strings, 4031 .stats_get_stats = mv88e6250_stats_get_stats, 4032 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4033 .set_egress_port = mv88e6095_g1_set_egress_port, 4034 .watchdog_ops = &mv88e6250_watchdog_ops, 4035 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4036 .pot_clear = mv88e6xxx_g2_pot_clear, 4037 .reset = mv88e6250_g1_reset, 4038 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4039 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4040 .avb_ops = &mv88e6352_avb_ops, 4041 .ptp_ops = &mv88e6250_ptp_ops, 4042 .phylink_validate = mv88e6065_phylink_validate, 4043 }; 4044 4045 static const struct mv88e6xxx_ops mv88e6290_ops = { 4046 /* MV88E6XXX_FAMILY_6390 */ 4047 .setup_errata = mv88e6390_setup_errata, 4048 .irl_init_all = mv88e6390_g2_irl_init_all, 4049 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4050 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4051 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4052 .phy_read = mv88e6xxx_g2_smi_phy_read, 4053 .phy_write = mv88e6xxx_g2_smi_phy_write, 4054 .port_set_link = mv88e6xxx_port_set_link, 4055 .port_sync_link = mv88e6xxx_port_sync_link, 4056 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4057 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4058 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4059 .port_tag_remap = mv88e6390_port_tag_remap, 4060 .port_set_policy = mv88e6352_port_set_policy, 4061 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4062 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4063 .port_set_ether_type = mv88e6351_port_set_ether_type, 4064 .port_pause_limit = mv88e6390_port_pause_limit, 4065 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4066 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4067 .port_get_cmode = mv88e6352_port_get_cmode, 4068 .port_set_cmode = mv88e6390_port_set_cmode, 4069 .port_setup_message_port = mv88e6xxx_setup_message_port, 4070 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4071 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4072 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4073 .stats_get_strings = mv88e6320_stats_get_strings, 4074 .stats_get_stats = mv88e6390_stats_get_stats, 4075 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4076 .set_egress_port = mv88e6390_g1_set_egress_port, 4077 .watchdog_ops = &mv88e6390_watchdog_ops, 4078 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4079 .pot_clear = mv88e6xxx_g2_pot_clear, 4080 .reset = mv88e6352_g1_reset, 4081 .rmu_disable = mv88e6390_g1_rmu_disable, 4082 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4083 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4084 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4085 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4086 .serdes_power = mv88e6390_serdes_power, 4087 .serdes_get_lane = mv88e6390_serdes_get_lane, 4088 /* Check status register pause & lpa register */ 4089 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4090 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4091 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4092 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4093 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4094 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4095 .serdes_irq_status = mv88e6390_serdes_irq_status, 4096 .serdes_get_strings = mv88e6390_serdes_get_strings, 4097 .serdes_get_stats = mv88e6390_serdes_get_stats, 4098 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4099 .serdes_get_regs = mv88e6390_serdes_get_regs, 4100 .gpio_ops = &mv88e6352_gpio_ops, 4101 .avb_ops = &mv88e6390_avb_ops, 4102 .ptp_ops = &mv88e6352_ptp_ops, 4103 .phylink_validate = mv88e6390_phylink_validate, 4104 }; 4105 4106 static const struct mv88e6xxx_ops mv88e6320_ops = { 4107 /* MV88E6XXX_FAMILY_6320 */ 4108 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4109 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4110 .irl_init_all = mv88e6352_g2_irl_init_all, 4111 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4112 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4113 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4114 .phy_read = mv88e6xxx_g2_smi_phy_read, 4115 .phy_write = mv88e6xxx_g2_smi_phy_write, 4116 .port_set_link = mv88e6xxx_port_set_link, 4117 .port_sync_link = mv88e6xxx_port_sync_link, 4118 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4119 .port_tag_remap = mv88e6095_port_tag_remap, 4120 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4121 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4122 .port_set_ether_type = mv88e6351_port_set_ether_type, 4123 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4124 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4125 .port_pause_limit = mv88e6097_port_pause_limit, 4126 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4127 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4128 .port_get_cmode = mv88e6352_port_get_cmode, 4129 .port_setup_message_port = mv88e6xxx_setup_message_port, 4130 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4131 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4132 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4133 .stats_get_strings = mv88e6320_stats_get_strings, 4134 .stats_get_stats = mv88e6320_stats_get_stats, 4135 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4136 .set_egress_port = mv88e6095_g1_set_egress_port, 4137 .watchdog_ops = &mv88e6390_watchdog_ops, 4138 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4139 .pot_clear = mv88e6xxx_g2_pot_clear, 4140 .reset = mv88e6352_g1_reset, 4141 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4142 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4143 .gpio_ops = &mv88e6352_gpio_ops, 4144 .avb_ops = &mv88e6352_avb_ops, 4145 .ptp_ops = &mv88e6352_ptp_ops, 4146 .phylink_validate = mv88e6185_phylink_validate, 4147 }; 4148 4149 static const struct mv88e6xxx_ops mv88e6321_ops = { 4150 /* MV88E6XXX_FAMILY_6320 */ 4151 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4152 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4153 .irl_init_all = mv88e6352_g2_irl_init_all, 4154 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4155 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4156 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4157 .phy_read = mv88e6xxx_g2_smi_phy_read, 4158 .phy_write = mv88e6xxx_g2_smi_phy_write, 4159 .port_set_link = mv88e6xxx_port_set_link, 4160 .port_sync_link = mv88e6xxx_port_sync_link, 4161 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4162 .port_tag_remap = mv88e6095_port_tag_remap, 4163 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4164 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4165 .port_set_ether_type = mv88e6351_port_set_ether_type, 4166 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4167 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4168 .port_pause_limit = mv88e6097_port_pause_limit, 4169 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4170 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4171 .port_get_cmode = mv88e6352_port_get_cmode, 4172 .port_setup_message_port = mv88e6xxx_setup_message_port, 4173 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4174 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4175 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4176 .stats_get_strings = mv88e6320_stats_get_strings, 4177 .stats_get_stats = mv88e6320_stats_get_stats, 4178 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4179 .set_egress_port = mv88e6095_g1_set_egress_port, 4180 .watchdog_ops = &mv88e6390_watchdog_ops, 4181 .reset = mv88e6352_g1_reset, 4182 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4183 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4184 .gpio_ops = &mv88e6352_gpio_ops, 4185 .avb_ops = &mv88e6352_avb_ops, 4186 .ptp_ops = &mv88e6352_ptp_ops, 4187 .phylink_validate = mv88e6185_phylink_validate, 4188 }; 4189 4190 static const struct mv88e6xxx_ops mv88e6341_ops = { 4191 /* MV88E6XXX_FAMILY_6341 */ 4192 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4193 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4194 .irl_init_all = mv88e6352_g2_irl_init_all, 4195 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4196 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4197 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4198 .phy_read = mv88e6xxx_g2_smi_phy_read, 4199 .phy_write = mv88e6xxx_g2_smi_phy_write, 4200 .port_set_link = mv88e6xxx_port_set_link, 4201 .port_sync_link = mv88e6xxx_port_sync_link, 4202 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4203 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4204 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4205 .port_tag_remap = mv88e6095_port_tag_remap, 4206 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4207 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4208 .port_set_ether_type = mv88e6351_port_set_ether_type, 4209 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4210 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4211 .port_pause_limit = mv88e6097_port_pause_limit, 4212 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4213 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4214 .port_get_cmode = mv88e6352_port_get_cmode, 4215 .port_set_cmode = mv88e6341_port_set_cmode, 4216 .port_setup_message_port = mv88e6xxx_setup_message_port, 4217 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4218 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4219 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4220 .stats_get_strings = mv88e6320_stats_get_strings, 4221 .stats_get_stats = mv88e6390_stats_get_stats, 4222 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4223 .set_egress_port = mv88e6390_g1_set_egress_port, 4224 .watchdog_ops = &mv88e6390_watchdog_ops, 4225 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4226 .pot_clear = mv88e6xxx_g2_pot_clear, 4227 .reset = mv88e6352_g1_reset, 4228 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4229 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4230 .serdes_power = mv88e6390_serdes_power, 4231 .serdes_get_lane = mv88e6341_serdes_get_lane, 4232 /* Check status register pause & lpa register */ 4233 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4234 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4235 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4236 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4237 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4238 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4239 .serdes_irq_status = mv88e6390_serdes_irq_status, 4240 .gpio_ops = &mv88e6352_gpio_ops, 4241 .avb_ops = &mv88e6390_avb_ops, 4242 .ptp_ops = &mv88e6352_ptp_ops, 4243 .phylink_validate = mv88e6341_phylink_validate, 4244 }; 4245 4246 static const struct mv88e6xxx_ops mv88e6350_ops = { 4247 /* MV88E6XXX_FAMILY_6351 */ 4248 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4249 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4250 .irl_init_all = mv88e6352_g2_irl_init_all, 4251 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4252 .phy_read = mv88e6xxx_g2_smi_phy_read, 4253 .phy_write = mv88e6xxx_g2_smi_phy_write, 4254 .port_set_link = mv88e6xxx_port_set_link, 4255 .port_sync_link = mv88e6xxx_port_sync_link, 4256 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4257 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4258 .port_tag_remap = mv88e6095_port_tag_remap, 4259 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4260 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4261 .port_set_ether_type = mv88e6351_port_set_ether_type, 4262 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4263 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4264 .port_pause_limit = mv88e6097_port_pause_limit, 4265 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4266 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4267 .port_get_cmode = mv88e6352_port_get_cmode, 4268 .port_setup_message_port = mv88e6xxx_setup_message_port, 4269 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4270 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4271 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4272 .stats_get_strings = mv88e6095_stats_get_strings, 4273 .stats_get_stats = mv88e6095_stats_get_stats, 4274 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4275 .set_egress_port = mv88e6095_g1_set_egress_port, 4276 .watchdog_ops = &mv88e6097_watchdog_ops, 4277 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4278 .pot_clear = mv88e6xxx_g2_pot_clear, 4279 .reset = mv88e6352_g1_reset, 4280 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4281 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4282 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4283 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4284 .phylink_validate = mv88e6185_phylink_validate, 4285 }; 4286 4287 static const struct mv88e6xxx_ops mv88e6351_ops = { 4288 /* MV88E6XXX_FAMILY_6351 */ 4289 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4290 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4291 .irl_init_all = mv88e6352_g2_irl_init_all, 4292 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4293 .phy_read = mv88e6xxx_g2_smi_phy_read, 4294 .phy_write = mv88e6xxx_g2_smi_phy_write, 4295 .port_set_link = mv88e6xxx_port_set_link, 4296 .port_sync_link = mv88e6xxx_port_sync_link, 4297 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4298 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4299 .port_tag_remap = mv88e6095_port_tag_remap, 4300 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4301 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4302 .port_set_ether_type = mv88e6351_port_set_ether_type, 4303 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4304 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4305 .port_pause_limit = mv88e6097_port_pause_limit, 4306 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4307 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4308 .port_get_cmode = mv88e6352_port_get_cmode, 4309 .port_setup_message_port = mv88e6xxx_setup_message_port, 4310 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4311 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4312 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4313 .stats_get_strings = mv88e6095_stats_get_strings, 4314 .stats_get_stats = mv88e6095_stats_get_stats, 4315 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4316 .set_egress_port = mv88e6095_g1_set_egress_port, 4317 .watchdog_ops = &mv88e6097_watchdog_ops, 4318 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4319 .pot_clear = mv88e6xxx_g2_pot_clear, 4320 .reset = mv88e6352_g1_reset, 4321 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4322 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4323 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4324 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4325 .avb_ops = &mv88e6352_avb_ops, 4326 .ptp_ops = &mv88e6352_ptp_ops, 4327 .phylink_validate = mv88e6185_phylink_validate, 4328 }; 4329 4330 static const struct mv88e6xxx_ops mv88e6352_ops = { 4331 /* MV88E6XXX_FAMILY_6352 */ 4332 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4333 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4334 .irl_init_all = mv88e6352_g2_irl_init_all, 4335 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4336 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4337 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4338 .phy_read = mv88e6xxx_g2_smi_phy_read, 4339 .phy_write = mv88e6xxx_g2_smi_phy_write, 4340 .port_set_link = mv88e6xxx_port_set_link, 4341 .port_sync_link = mv88e6xxx_port_sync_link, 4342 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4343 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4344 .port_tag_remap = mv88e6095_port_tag_remap, 4345 .port_set_policy = mv88e6352_port_set_policy, 4346 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4347 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4348 .port_set_ether_type = mv88e6351_port_set_ether_type, 4349 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4350 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4351 .port_pause_limit = mv88e6097_port_pause_limit, 4352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4354 .port_get_cmode = mv88e6352_port_get_cmode, 4355 .port_setup_message_port = mv88e6xxx_setup_message_port, 4356 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4357 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4358 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4359 .stats_get_strings = mv88e6095_stats_get_strings, 4360 .stats_get_stats = mv88e6095_stats_get_stats, 4361 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4362 .set_egress_port = mv88e6095_g1_set_egress_port, 4363 .watchdog_ops = &mv88e6097_watchdog_ops, 4364 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4365 .pot_clear = mv88e6xxx_g2_pot_clear, 4366 .reset = mv88e6352_g1_reset, 4367 .rmu_disable = mv88e6352_g1_rmu_disable, 4368 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4369 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4370 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4371 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4372 .serdes_get_lane = mv88e6352_serdes_get_lane, 4373 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4374 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4375 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4376 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4377 .serdes_power = mv88e6352_serdes_power, 4378 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4379 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4380 .serdes_irq_status = mv88e6352_serdes_irq_status, 4381 .gpio_ops = &mv88e6352_gpio_ops, 4382 .avb_ops = &mv88e6352_avb_ops, 4383 .ptp_ops = &mv88e6352_ptp_ops, 4384 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4385 .serdes_get_strings = mv88e6352_serdes_get_strings, 4386 .serdes_get_stats = mv88e6352_serdes_get_stats, 4387 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4388 .serdes_get_regs = mv88e6352_serdes_get_regs, 4389 .phylink_validate = mv88e6352_phylink_validate, 4390 }; 4391 4392 static const struct mv88e6xxx_ops mv88e6390_ops = { 4393 /* MV88E6XXX_FAMILY_6390 */ 4394 .setup_errata = mv88e6390_setup_errata, 4395 .irl_init_all = mv88e6390_g2_irl_init_all, 4396 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4397 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4398 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4399 .phy_read = mv88e6xxx_g2_smi_phy_read, 4400 .phy_write = mv88e6xxx_g2_smi_phy_write, 4401 .port_set_link = mv88e6xxx_port_set_link, 4402 .port_sync_link = mv88e6xxx_port_sync_link, 4403 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4404 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4405 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4406 .port_tag_remap = mv88e6390_port_tag_remap, 4407 .port_set_policy = mv88e6352_port_set_policy, 4408 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4409 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4410 .port_set_ether_type = mv88e6351_port_set_ether_type, 4411 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4412 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4413 .port_pause_limit = mv88e6390_port_pause_limit, 4414 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4415 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4416 .port_get_cmode = mv88e6352_port_get_cmode, 4417 .port_set_cmode = mv88e6390_port_set_cmode, 4418 .port_setup_message_port = mv88e6xxx_setup_message_port, 4419 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4420 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4421 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4422 .stats_get_strings = mv88e6320_stats_get_strings, 4423 .stats_get_stats = mv88e6390_stats_get_stats, 4424 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4425 .set_egress_port = mv88e6390_g1_set_egress_port, 4426 .watchdog_ops = &mv88e6390_watchdog_ops, 4427 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4428 .pot_clear = mv88e6xxx_g2_pot_clear, 4429 .reset = mv88e6352_g1_reset, 4430 .rmu_disable = mv88e6390_g1_rmu_disable, 4431 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4432 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4433 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4434 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4435 .serdes_power = mv88e6390_serdes_power, 4436 .serdes_get_lane = mv88e6390_serdes_get_lane, 4437 /* Check status register pause & lpa register */ 4438 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4439 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4440 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4441 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4442 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4443 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4444 .serdes_irq_status = mv88e6390_serdes_irq_status, 4445 .gpio_ops = &mv88e6352_gpio_ops, 4446 .avb_ops = &mv88e6390_avb_ops, 4447 .ptp_ops = &mv88e6352_ptp_ops, 4448 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4449 .serdes_get_strings = mv88e6390_serdes_get_strings, 4450 .serdes_get_stats = mv88e6390_serdes_get_stats, 4451 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4452 .serdes_get_regs = mv88e6390_serdes_get_regs, 4453 .phylink_validate = mv88e6390_phylink_validate, 4454 }; 4455 4456 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4457 /* MV88E6XXX_FAMILY_6390 */ 4458 .setup_errata = mv88e6390_setup_errata, 4459 .irl_init_all = mv88e6390_g2_irl_init_all, 4460 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4461 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4462 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4463 .phy_read = mv88e6xxx_g2_smi_phy_read, 4464 .phy_write = mv88e6xxx_g2_smi_phy_write, 4465 .port_set_link = mv88e6xxx_port_set_link, 4466 .port_sync_link = mv88e6xxx_port_sync_link, 4467 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4468 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4469 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4470 .port_tag_remap = mv88e6390_port_tag_remap, 4471 .port_set_policy = mv88e6352_port_set_policy, 4472 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4473 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4474 .port_set_ether_type = mv88e6351_port_set_ether_type, 4475 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4476 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4477 .port_pause_limit = mv88e6390_port_pause_limit, 4478 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4479 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4480 .port_get_cmode = mv88e6352_port_get_cmode, 4481 .port_set_cmode = mv88e6390x_port_set_cmode, 4482 .port_setup_message_port = mv88e6xxx_setup_message_port, 4483 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4484 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4485 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4486 .stats_get_strings = mv88e6320_stats_get_strings, 4487 .stats_get_stats = mv88e6390_stats_get_stats, 4488 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4489 .set_egress_port = mv88e6390_g1_set_egress_port, 4490 .watchdog_ops = &mv88e6390_watchdog_ops, 4491 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4492 .pot_clear = mv88e6xxx_g2_pot_clear, 4493 .reset = mv88e6352_g1_reset, 4494 .rmu_disable = mv88e6390_g1_rmu_disable, 4495 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4496 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4497 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4498 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4499 .serdes_power = mv88e6390_serdes_power, 4500 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4501 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4502 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4503 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4504 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4505 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4506 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4507 .serdes_irq_status = mv88e6390_serdes_irq_status, 4508 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4509 .serdes_get_strings = mv88e6390_serdes_get_strings, 4510 .serdes_get_stats = mv88e6390_serdes_get_stats, 4511 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4512 .serdes_get_regs = mv88e6390_serdes_get_regs, 4513 .gpio_ops = &mv88e6352_gpio_ops, 4514 .avb_ops = &mv88e6390_avb_ops, 4515 .ptp_ops = &mv88e6352_ptp_ops, 4516 .phylink_validate = mv88e6390x_phylink_validate, 4517 }; 4518 4519 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4520 [MV88E6085] = { 4521 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4522 .family = MV88E6XXX_FAMILY_6097, 4523 .name = "Marvell 88E6085", 4524 .num_databases = 4096, 4525 .num_macs = 8192, 4526 .num_ports = 10, 4527 .num_internal_phys = 5, 4528 .max_vid = 4095, 4529 .port_base_addr = 0x10, 4530 .phy_base_addr = 0x0, 4531 .global1_addr = 0x1b, 4532 .global2_addr = 0x1c, 4533 .age_time_coeff = 15000, 4534 .g1_irqs = 8, 4535 .g2_irqs = 10, 4536 .atu_move_port_mask = 0xf, 4537 .pvt = true, 4538 .multi_chip = true, 4539 .tag_protocol = DSA_TAG_PROTO_DSA, 4540 .ops = &mv88e6085_ops, 4541 }, 4542 4543 [MV88E6095] = { 4544 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4545 .family = MV88E6XXX_FAMILY_6095, 4546 .name = "Marvell 88E6095/88E6095F", 4547 .num_databases = 256, 4548 .num_macs = 8192, 4549 .num_ports = 11, 4550 .num_internal_phys = 0, 4551 .max_vid = 4095, 4552 .port_base_addr = 0x10, 4553 .phy_base_addr = 0x0, 4554 .global1_addr = 0x1b, 4555 .global2_addr = 0x1c, 4556 .age_time_coeff = 15000, 4557 .g1_irqs = 8, 4558 .atu_move_port_mask = 0xf, 4559 .multi_chip = true, 4560 .tag_protocol = DSA_TAG_PROTO_DSA, 4561 .ops = &mv88e6095_ops, 4562 }, 4563 4564 [MV88E6097] = { 4565 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4566 .family = MV88E6XXX_FAMILY_6097, 4567 .name = "Marvell 88E6097/88E6097F", 4568 .num_databases = 4096, 4569 .num_macs = 8192, 4570 .num_ports = 11, 4571 .num_internal_phys = 8, 4572 .max_vid = 4095, 4573 .port_base_addr = 0x10, 4574 .phy_base_addr = 0x0, 4575 .global1_addr = 0x1b, 4576 .global2_addr = 0x1c, 4577 .age_time_coeff = 15000, 4578 .g1_irqs = 8, 4579 .g2_irqs = 10, 4580 .atu_move_port_mask = 0xf, 4581 .pvt = true, 4582 .multi_chip = true, 4583 .tag_protocol = DSA_TAG_PROTO_EDSA, 4584 .ops = &mv88e6097_ops, 4585 }, 4586 4587 [MV88E6123] = { 4588 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4589 .family = MV88E6XXX_FAMILY_6165, 4590 .name = "Marvell 88E6123", 4591 .num_databases = 4096, 4592 .num_macs = 1024, 4593 .num_ports = 3, 4594 .num_internal_phys = 5, 4595 .max_vid = 4095, 4596 .port_base_addr = 0x10, 4597 .phy_base_addr = 0x0, 4598 .global1_addr = 0x1b, 4599 .global2_addr = 0x1c, 4600 .age_time_coeff = 15000, 4601 .g1_irqs = 9, 4602 .g2_irqs = 10, 4603 .atu_move_port_mask = 0xf, 4604 .pvt = true, 4605 .multi_chip = true, 4606 .tag_protocol = DSA_TAG_PROTO_EDSA, 4607 .ops = &mv88e6123_ops, 4608 }, 4609 4610 [MV88E6131] = { 4611 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4612 .family = MV88E6XXX_FAMILY_6185, 4613 .name = "Marvell 88E6131", 4614 .num_databases = 256, 4615 .num_macs = 8192, 4616 .num_ports = 8, 4617 .num_internal_phys = 0, 4618 .max_vid = 4095, 4619 .port_base_addr = 0x10, 4620 .phy_base_addr = 0x0, 4621 .global1_addr = 0x1b, 4622 .global2_addr = 0x1c, 4623 .age_time_coeff = 15000, 4624 .g1_irqs = 9, 4625 .atu_move_port_mask = 0xf, 4626 .multi_chip = true, 4627 .tag_protocol = DSA_TAG_PROTO_DSA, 4628 .ops = &mv88e6131_ops, 4629 }, 4630 4631 [MV88E6141] = { 4632 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4633 .family = MV88E6XXX_FAMILY_6341, 4634 .name = "Marvell 88E6141", 4635 .num_databases = 4096, 4636 .num_macs = 2048, 4637 .num_ports = 6, 4638 .num_internal_phys = 5, 4639 .num_gpio = 11, 4640 .max_vid = 4095, 4641 .port_base_addr = 0x10, 4642 .phy_base_addr = 0x10, 4643 .global1_addr = 0x1b, 4644 .global2_addr = 0x1c, 4645 .age_time_coeff = 3750, 4646 .atu_move_port_mask = 0x1f, 4647 .g1_irqs = 9, 4648 .g2_irqs = 10, 4649 .pvt = true, 4650 .multi_chip = true, 4651 .tag_protocol = DSA_TAG_PROTO_EDSA, 4652 .ops = &mv88e6141_ops, 4653 }, 4654 4655 [MV88E6161] = { 4656 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4657 .family = MV88E6XXX_FAMILY_6165, 4658 .name = "Marvell 88E6161", 4659 .num_databases = 4096, 4660 .num_macs = 1024, 4661 .num_ports = 6, 4662 .num_internal_phys = 5, 4663 .max_vid = 4095, 4664 .port_base_addr = 0x10, 4665 .phy_base_addr = 0x0, 4666 .global1_addr = 0x1b, 4667 .global2_addr = 0x1c, 4668 .age_time_coeff = 15000, 4669 .g1_irqs = 9, 4670 .g2_irqs = 10, 4671 .atu_move_port_mask = 0xf, 4672 .pvt = true, 4673 .multi_chip = true, 4674 .tag_protocol = DSA_TAG_PROTO_EDSA, 4675 .ptp_support = true, 4676 .ops = &mv88e6161_ops, 4677 }, 4678 4679 [MV88E6165] = { 4680 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4681 .family = MV88E6XXX_FAMILY_6165, 4682 .name = "Marvell 88E6165", 4683 .num_databases = 4096, 4684 .num_macs = 8192, 4685 .num_ports = 6, 4686 .num_internal_phys = 0, 4687 .max_vid = 4095, 4688 .port_base_addr = 0x10, 4689 .phy_base_addr = 0x0, 4690 .global1_addr = 0x1b, 4691 .global2_addr = 0x1c, 4692 .age_time_coeff = 15000, 4693 .g1_irqs = 9, 4694 .g2_irqs = 10, 4695 .atu_move_port_mask = 0xf, 4696 .pvt = true, 4697 .multi_chip = true, 4698 .tag_protocol = DSA_TAG_PROTO_DSA, 4699 .ptp_support = true, 4700 .ops = &mv88e6165_ops, 4701 }, 4702 4703 [MV88E6171] = { 4704 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4705 .family = MV88E6XXX_FAMILY_6351, 4706 .name = "Marvell 88E6171", 4707 .num_databases = 4096, 4708 .num_macs = 8192, 4709 .num_ports = 7, 4710 .num_internal_phys = 5, 4711 .max_vid = 4095, 4712 .port_base_addr = 0x10, 4713 .phy_base_addr = 0x0, 4714 .global1_addr = 0x1b, 4715 .global2_addr = 0x1c, 4716 .age_time_coeff = 15000, 4717 .g1_irqs = 9, 4718 .g2_irqs = 10, 4719 .atu_move_port_mask = 0xf, 4720 .pvt = true, 4721 .multi_chip = true, 4722 .tag_protocol = DSA_TAG_PROTO_EDSA, 4723 .ops = &mv88e6171_ops, 4724 }, 4725 4726 [MV88E6172] = { 4727 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4728 .family = MV88E6XXX_FAMILY_6352, 4729 .name = "Marvell 88E6172", 4730 .num_databases = 4096, 4731 .num_macs = 8192, 4732 .num_ports = 7, 4733 .num_internal_phys = 5, 4734 .num_gpio = 15, 4735 .max_vid = 4095, 4736 .port_base_addr = 0x10, 4737 .phy_base_addr = 0x0, 4738 .global1_addr = 0x1b, 4739 .global2_addr = 0x1c, 4740 .age_time_coeff = 15000, 4741 .g1_irqs = 9, 4742 .g2_irqs = 10, 4743 .atu_move_port_mask = 0xf, 4744 .pvt = true, 4745 .multi_chip = true, 4746 .tag_protocol = DSA_TAG_PROTO_EDSA, 4747 .ops = &mv88e6172_ops, 4748 }, 4749 4750 [MV88E6175] = { 4751 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4752 .family = MV88E6XXX_FAMILY_6351, 4753 .name = "Marvell 88E6175", 4754 .num_databases = 4096, 4755 .num_macs = 8192, 4756 .num_ports = 7, 4757 .num_internal_phys = 5, 4758 .max_vid = 4095, 4759 .port_base_addr = 0x10, 4760 .phy_base_addr = 0x0, 4761 .global1_addr = 0x1b, 4762 .global2_addr = 0x1c, 4763 .age_time_coeff = 15000, 4764 .g1_irqs = 9, 4765 .g2_irqs = 10, 4766 .atu_move_port_mask = 0xf, 4767 .pvt = true, 4768 .multi_chip = true, 4769 .tag_protocol = DSA_TAG_PROTO_EDSA, 4770 .ops = &mv88e6175_ops, 4771 }, 4772 4773 [MV88E6176] = { 4774 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4775 .family = MV88E6XXX_FAMILY_6352, 4776 .name = "Marvell 88E6176", 4777 .num_databases = 4096, 4778 .num_macs = 8192, 4779 .num_ports = 7, 4780 .num_internal_phys = 5, 4781 .num_gpio = 15, 4782 .max_vid = 4095, 4783 .port_base_addr = 0x10, 4784 .phy_base_addr = 0x0, 4785 .global1_addr = 0x1b, 4786 .global2_addr = 0x1c, 4787 .age_time_coeff = 15000, 4788 .g1_irqs = 9, 4789 .g2_irqs = 10, 4790 .atu_move_port_mask = 0xf, 4791 .pvt = true, 4792 .multi_chip = true, 4793 .tag_protocol = DSA_TAG_PROTO_EDSA, 4794 .ops = &mv88e6176_ops, 4795 }, 4796 4797 [MV88E6185] = { 4798 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4799 .family = MV88E6XXX_FAMILY_6185, 4800 .name = "Marvell 88E6185", 4801 .num_databases = 256, 4802 .num_macs = 8192, 4803 .num_ports = 10, 4804 .num_internal_phys = 0, 4805 .max_vid = 4095, 4806 .port_base_addr = 0x10, 4807 .phy_base_addr = 0x0, 4808 .global1_addr = 0x1b, 4809 .global2_addr = 0x1c, 4810 .age_time_coeff = 15000, 4811 .g1_irqs = 8, 4812 .atu_move_port_mask = 0xf, 4813 .multi_chip = true, 4814 .tag_protocol = DSA_TAG_PROTO_EDSA, 4815 .ops = &mv88e6185_ops, 4816 }, 4817 4818 [MV88E6190] = { 4819 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4820 .family = MV88E6XXX_FAMILY_6390, 4821 .name = "Marvell 88E6190", 4822 .num_databases = 4096, 4823 .num_macs = 16384, 4824 .num_ports = 11, /* 10 + Z80 */ 4825 .num_internal_phys = 9, 4826 .num_gpio = 16, 4827 .max_vid = 8191, 4828 .port_base_addr = 0x0, 4829 .phy_base_addr = 0x0, 4830 .global1_addr = 0x1b, 4831 .global2_addr = 0x1c, 4832 .tag_protocol = DSA_TAG_PROTO_DSA, 4833 .age_time_coeff = 3750, 4834 .g1_irqs = 9, 4835 .g2_irqs = 14, 4836 .pvt = true, 4837 .multi_chip = true, 4838 .atu_move_port_mask = 0x1f, 4839 .ops = &mv88e6190_ops, 4840 }, 4841 4842 [MV88E6190X] = { 4843 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4844 .family = MV88E6XXX_FAMILY_6390, 4845 .name = "Marvell 88E6190X", 4846 .num_databases = 4096, 4847 .num_macs = 16384, 4848 .num_ports = 11, /* 10 + Z80 */ 4849 .num_internal_phys = 9, 4850 .num_gpio = 16, 4851 .max_vid = 8191, 4852 .port_base_addr = 0x0, 4853 .phy_base_addr = 0x0, 4854 .global1_addr = 0x1b, 4855 .global2_addr = 0x1c, 4856 .age_time_coeff = 3750, 4857 .g1_irqs = 9, 4858 .g2_irqs = 14, 4859 .atu_move_port_mask = 0x1f, 4860 .pvt = true, 4861 .multi_chip = true, 4862 .tag_protocol = DSA_TAG_PROTO_DSA, 4863 .ops = &mv88e6190x_ops, 4864 }, 4865 4866 [MV88E6191] = { 4867 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4868 .family = MV88E6XXX_FAMILY_6390, 4869 .name = "Marvell 88E6191", 4870 .num_databases = 4096, 4871 .num_macs = 16384, 4872 .num_ports = 11, /* 10 + Z80 */ 4873 .num_internal_phys = 9, 4874 .max_vid = 8191, 4875 .port_base_addr = 0x0, 4876 .phy_base_addr = 0x0, 4877 .global1_addr = 0x1b, 4878 .global2_addr = 0x1c, 4879 .age_time_coeff = 3750, 4880 .g1_irqs = 9, 4881 .g2_irqs = 14, 4882 .atu_move_port_mask = 0x1f, 4883 .pvt = true, 4884 .multi_chip = true, 4885 .tag_protocol = DSA_TAG_PROTO_DSA, 4886 .ptp_support = true, 4887 .ops = &mv88e6191_ops, 4888 }, 4889 4890 [MV88E6220] = { 4891 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4892 .family = MV88E6XXX_FAMILY_6250, 4893 .name = "Marvell 88E6220", 4894 .num_databases = 64, 4895 4896 /* Ports 2-4 are not routed to pins 4897 * => usable ports 0, 1, 5, 6 4898 */ 4899 .num_ports = 7, 4900 .num_internal_phys = 2, 4901 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4902 .max_vid = 4095, 4903 .port_base_addr = 0x08, 4904 .phy_base_addr = 0x00, 4905 .global1_addr = 0x0f, 4906 .global2_addr = 0x07, 4907 .age_time_coeff = 15000, 4908 .g1_irqs = 9, 4909 .g2_irqs = 10, 4910 .atu_move_port_mask = 0xf, 4911 .dual_chip = true, 4912 .tag_protocol = DSA_TAG_PROTO_DSA, 4913 .ptp_support = true, 4914 .ops = &mv88e6250_ops, 4915 }, 4916 4917 [MV88E6240] = { 4918 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4919 .family = MV88E6XXX_FAMILY_6352, 4920 .name = "Marvell 88E6240", 4921 .num_databases = 4096, 4922 .num_macs = 8192, 4923 .num_ports = 7, 4924 .num_internal_phys = 5, 4925 .num_gpio = 15, 4926 .max_vid = 4095, 4927 .port_base_addr = 0x10, 4928 .phy_base_addr = 0x0, 4929 .global1_addr = 0x1b, 4930 .global2_addr = 0x1c, 4931 .age_time_coeff = 15000, 4932 .g1_irqs = 9, 4933 .g2_irqs = 10, 4934 .atu_move_port_mask = 0xf, 4935 .pvt = true, 4936 .multi_chip = true, 4937 .tag_protocol = DSA_TAG_PROTO_EDSA, 4938 .ptp_support = true, 4939 .ops = &mv88e6240_ops, 4940 }, 4941 4942 [MV88E6250] = { 4943 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4944 .family = MV88E6XXX_FAMILY_6250, 4945 .name = "Marvell 88E6250", 4946 .num_databases = 64, 4947 .num_ports = 7, 4948 .num_internal_phys = 5, 4949 .max_vid = 4095, 4950 .port_base_addr = 0x08, 4951 .phy_base_addr = 0x00, 4952 .global1_addr = 0x0f, 4953 .global2_addr = 0x07, 4954 .age_time_coeff = 15000, 4955 .g1_irqs = 9, 4956 .g2_irqs = 10, 4957 .atu_move_port_mask = 0xf, 4958 .dual_chip = true, 4959 .tag_protocol = DSA_TAG_PROTO_DSA, 4960 .ptp_support = true, 4961 .ops = &mv88e6250_ops, 4962 }, 4963 4964 [MV88E6290] = { 4965 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4966 .family = MV88E6XXX_FAMILY_6390, 4967 .name = "Marvell 88E6290", 4968 .num_databases = 4096, 4969 .num_ports = 11, /* 10 + Z80 */ 4970 .num_internal_phys = 9, 4971 .num_gpio = 16, 4972 .max_vid = 8191, 4973 .port_base_addr = 0x0, 4974 .phy_base_addr = 0x0, 4975 .global1_addr = 0x1b, 4976 .global2_addr = 0x1c, 4977 .age_time_coeff = 3750, 4978 .g1_irqs = 9, 4979 .g2_irqs = 14, 4980 .atu_move_port_mask = 0x1f, 4981 .pvt = true, 4982 .multi_chip = true, 4983 .tag_protocol = DSA_TAG_PROTO_DSA, 4984 .ptp_support = true, 4985 .ops = &mv88e6290_ops, 4986 }, 4987 4988 [MV88E6320] = { 4989 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4990 .family = MV88E6XXX_FAMILY_6320, 4991 .name = "Marvell 88E6320", 4992 .num_databases = 4096, 4993 .num_macs = 8192, 4994 .num_ports = 7, 4995 .num_internal_phys = 5, 4996 .num_gpio = 15, 4997 .max_vid = 4095, 4998 .port_base_addr = 0x10, 4999 .phy_base_addr = 0x0, 5000 .global1_addr = 0x1b, 5001 .global2_addr = 0x1c, 5002 .age_time_coeff = 15000, 5003 .g1_irqs = 8, 5004 .g2_irqs = 10, 5005 .atu_move_port_mask = 0xf, 5006 .pvt = true, 5007 .multi_chip = true, 5008 .tag_protocol = DSA_TAG_PROTO_EDSA, 5009 .ptp_support = true, 5010 .ops = &mv88e6320_ops, 5011 }, 5012 5013 [MV88E6321] = { 5014 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5015 .family = MV88E6XXX_FAMILY_6320, 5016 .name = "Marvell 88E6321", 5017 .num_databases = 4096, 5018 .num_macs = 8192, 5019 .num_ports = 7, 5020 .num_internal_phys = 5, 5021 .num_gpio = 15, 5022 .max_vid = 4095, 5023 .port_base_addr = 0x10, 5024 .phy_base_addr = 0x0, 5025 .global1_addr = 0x1b, 5026 .global2_addr = 0x1c, 5027 .age_time_coeff = 15000, 5028 .g1_irqs = 8, 5029 .g2_irqs = 10, 5030 .atu_move_port_mask = 0xf, 5031 .multi_chip = true, 5032 .tag_protocol = DSA_TAG_PROTO_EDSA, 5033 .ptp_support = true, 5034 .ops = &mv88e6321_ops, 5035 }, 5036 5037 [MV88E6341] = { 5038 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5039 .family = MV88E6XXX_FAMILY_6341, 5040 .name = "Marvell 88E6341", 5041 .num_databases = 4096, 5042 .num_macs = 2048, 5043 .num_internal_phys = 5, 5044 .num_ports = 6, 5045 .num_gpio = 11, 5046 .max_vid = 4095, 5047 .port_base_addr = 0x10, 5048 .phy_base_addr = 0x10, 5049 .global1_addr = 0x1b, 5050 .global2_addr = 0x1c, 5051 .age_time_coeff = 3750, 5052 .atu_move_port_mask = 0x1f, 5053 .g1_irqs = 9, 5054 .g2_irqs = 10, 5055 .pvt = true, 5056 .multi_chip = true, 5057 .tag_protocol = DSA_TAG_PROTO_EDSA, 5058 .ptp_support = true, 5059 .ops = &mv88e6341_ops, 5060 }, 5061 5062 [MV88E6350] = { 5063 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5064 .family = MV88E6XXX_FAMILY_6351, 5065 .name = "Marvell 88E6350", 5066 .num_databases = 4096, 5067 .num_macs = 8192, 5068 .num_ports = 7, 5069 .num_internal_phys = 5, 5070 .max_vid = 4095, 5071 .port_base_addr = 0x10, 5072 .phy_base_addr = 0x0, 5073 .global1_addr = 0x1b, 5074 .global2_addr = 0x1c, 5075 .age_time_coeff = 15000, 5076 .g1_irqs = 9, 5077 .g2_irqs = 10, 5078 .atu_move_port_mask = 0xf, 5079 .pvt = true, 5080 .multi_chip = true, 5081 .tag_protocol = DSA_TAG_PROTO_EDSA, 5082 .ops = &mv88e6350_ops, 5083 }, 5084 5085 [MV88E6351] = { 5086 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5087 .family = MV88E6XXX_FAMILY_6351, 5088 .name = "Marvell 88E6351", 5089 .num_databases = 4096, 5090 .num_macs = 8192, 5091 .num_ports = 7, 5092 .num_internal_phys = 5, 5093 .max_vid = 4095, 5094 .port_base_addr = 0x10, 5095 .phy_base_addr = 0x0, 5096 .global1_addr = 0x1b, 5097 .global2_addr = 0x1c, 5098 .age_time_coeff = 15000, 5099 .g1_irqs = 9, 5100 .g2_irqs = 10, 5101 .atu_move_port_mask = 0xf, 5102 .pvt = true, 5103 .multi_chip = true, 5104 .tag_protocol = DSA_TAG_PROTO_EDSA, 5105 .ops = &mv88e6351_ops, 5106 }, 5107 5108 [MV88E6352] = { 5109 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5110 .family = MV88E6XXX_FAMILY_6352, 5111 .name = "Marvell 88E6352", 5112 .num_databases = 4096, 5113 .num_macs = 8192, 5114 .num_ports = 7, 5115 .num_internal_phys = 5, 5116 .num_gpio = 15, 5117 .max_vid = 4095, 5118 .port_base_addr = 0x10, 5119 .phy_base_addr = 0x0, 5120 .global1_addr = 0x1b, 5121 .global2_addr = 0x1c, 5122 .age_time_coeff = 15000, 5123 .g1_irqs = 9, 5124 .g2_irqs = 10, 5125 .atu_move_port_mask = 0xf, 5126 .pvt = true, 5127 .multi_chip = true, 5128 .tag_protocol = DSA_TAG_PROTO_EDSA, 5129 .ptp_support = true, 5130 .ops = &mv88e6352_ops, 5131 }, 5132 [MV88E6390] = { 5133 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5134 .family = MV88E6XXX_FAMILY_6390, 5135 .name = "Marvell 88E6390", 5136 .num_databases = 4096, 5137 .num_macs = 16384, 5138 .num_ports = 11, /* 10 + Z80 */ 5139 .num_internal_phys = 9, 5140 .num_gpio = 16, 5141 .max_vid = 8191, 5142 .port_base_addr = 0x0, 5143 .phy_base_addr = 0x0, 5144 .global1_addr = 0x1b, 5145 .global2_addr = 0x1c, 5146 .age_time_coeff = 3750, 5147 .g1_irqs = 9, 5148 .g2_irqs = 14, 5149 .atu_move_port_mask = 0x1f, 5150 .pvt = true, 5151 .multi_chip = true, 5152 .tag_protocol = DSA_TAG_PROTO_DSA, 5153 .ptp_support = true, 5154 .ops = &mv88e6390_ops, 5155 }, 5156 [MV88E6390X] = { 5157 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5158 .family = MV88E6XXX_FAMILY_6390, 5159 .name = "Marvell 88E6390X", 5160 .num_databases = 4096, 5161 .num_macs = 16384, 5162 .num_ports = 11, /* 10 + Z80 */ 5163 .num_internal_phys = 9, 5164 .num_gpio = 16, 5165 .max_vid = 8191, 5166 .port_base_addr = 0x0, 5167 .phy_base_addr = 0x0, 5168 .global1_addr = 0x1b, 5169 .global2_addr = 0x1c, 5170 .age_time_coeff = 3750, 5171 .g1_irqs = 9, 5172 .g2_irqs = 14, 5173 .atu_move_port_mask = 0x1f, 5174 .pvt = true, 5175 .multi_chip = true, 5176 .tag_protocol = DSA_TAG_PROTO_DSA, 5177 .ptp_support = true, 5178 .ops = &mv88e6390x_ops, 5179 }, 5180 }; 5181 5182 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5183 { 5184 int i; 5185 5186 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5187 if (mv88e6xxx_table[i].prod_num == prod_num) 5188 return &mv88e6xxx_table[i]; 5189 5190 return NULL; 5191 } 5192 5193 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5194 { 5195 const struct mv88e6xxx_info *info; 5196 unsigned int prod_num, rev; 5197 u16 id; 5198 int err; 5199 5200 mv88e6xxx_reg_lock(chip); 5201 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5202 mv88e6xxx_reg_unlock(chip); 5203 if (err) 5204 return err; 5205 5206 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5207 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5208 5209 info = mv88e6xxx_lookup_info(prod_num); 5210 if (!info) 5211 return -ENODEV; 5212 5213 /* Update the compatible info with the probed one */ 5214 chip->info = info; 5215 5216 err = mv88e6xxx_g2_require(chip); 5217 if (err) 5218 return err; 5219 5220 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5221 chip->info->prod_num, chip->info->name, rev); 5222 5223 return 0; 5224 } 5225 5226 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5227 { 5228 struct mv88e6xxx_chip *chip; 5229 5230 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5231 if (!chip) 5232 return NULL; 5233 5234 chip->dev = dev; 5235 5236 mutex_init(&chip->reg_lock); 5237 INIT_LIST_HEAD(&chip->mdios); 5238 idr_init(&chip->policies); 5239 5240 return chip; 5241 } 5242 5243 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5244 int port, 5245 enum dsa_tag_protocol m) 5246 { 5247 struct mv88e6xxx_chip *chip = ds->priv; 5248 5249 return chip->info->tag_protocol; 5250 } 5251 5252 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5253 const struct switchdev_obj_port_mdb *mdb) 5254 { 5255 /* We don't need any dynamic resource from the kernel (yet), 5256 * so skip the prepare phase. 5257 */ 5258 5259 return 0; 5260 } 5261 5262 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5263 const struct switchdev_obj_port_mdb *mdb) 5264 { 5265 struct mv88e6xxx_chip *chip = ds->priv; 5266 5267 mv88e6xxx_reg_lock(chip); 5268 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5269 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5270 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5271 port); 5272 mv88e6xxx_reg_unlock(chip); 5273 } 5274 5275 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5276 const struct switchdev_obj_port_mdb *mdb) 5277 { 5278 struct mv88e6xxx_chip *chip = ds->priv; 5279 int err; 5280 5281 mv88e6xxx_reg_lock(chip); 5282 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5283 mv88e6xxx_reg_unlock(chip); 5284 5285 return err; 5286 } 5287 5288 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5289 struct dsa_mall_mirror_tc_entry *mirror, 5290 bool ingress) 5291 { 5292 enum mv88e6xxx_egress_direction direction = ingress ? 5293 MV88E6XXX_EGRESS_DIR_INGRESS : 5294 MV88E6XXX_EGRESS_DIR_EGRESS; 5295 struct mv88e6xxx_chip *chip = ds->priv; 5296 bool other_mirrors = false; 5297 int i; 5298 int err; 5299 5300 if (!chip->info->ops->set_egress_port) 5301 return -EOPNOTSUPP; 5302 5303 mutex_lock(&chip->reg_lock); 5304 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5305 mirror->to_local_port) { 5306 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5307 other_mirrors |= ingress ? 5308 chip->ports[i].mirror_ingress : 5309 chip->ports[i].mirror_egress; 5310 5311 /* Can't change egress port when other mirror is active */ 5312 if (other_mirrors) { 5313 err = -EBUSY; 5314 goto out; 5315 } 5316 5317 err = chip->info->ops->set_egress_port(chip, 5318 direction, 5319 mirror->to_local_port); 5320 if (err) 5321 goto out; 5322 } 5323 5324 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5325 out: 5326 mutex_unlock(&chip->reg_lock); 5327 5328 return err; 5329 } 5330 5331 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5332 struct dsa_mall_mirror_tc_entry *mirror) 5333 { 5334 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5335 MV88E6XXX_EGRESS_DIR_INGRESS : 5336 MV88E6XXX_EGRESS_DIR_EGRESS; 5337 struct mv88e6xxx_chip *chip = ds->priv; 5338 bool other_mirrors = false; 5339 int i; 5340 5341 mutex_lock(&chip->reg_lock); 5342 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5343 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5344 5345 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5346 other_mirrors |= mirror->ingress ? 5347 chip->ports[i].mirror_ingress : 5348 chip->ports[i].mirror_egress; 5349 5350 /* Reset egress port when no other mirror is active */ 5351 if (!other_mirrors) { 5352 if (chip->info->ops->set_egress_port(chip, 5353 direction, 5354 dsa_upstream_port(ds, 5355 port))) 5356 dev_err(ds->dev, "failed to set egress port\n"); 5357 } 5358 5359 mutex_unlock(&chip->reg_lock); 5360 } 5361 5362 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5363 bool unicast, bool multicast) 5364 { 5365 struct mv88e6xxx_chip *chip = ds->priv; 5366 int err = -EOPNOTSUPP; 5367 5368 mv88e6xxx_reg_lock(chip); 5369 if (chip->info->ops->port_set_egress_floods) 5370 err = chip->info->ops->port_set_egress_floods(chip, port, 5371 unicast, 5372 multicast); 5373 mv88e6xxx_reg_unlock(chip); 5374 5375 return err; 5376 } 5377 5378 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5379 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5380 .setup = mv88e6xxx_setup, 5381 .teardown = mv88e6xxx_teardown, 5382 .phylink_validate = mv88e6xxx_validate, 5383 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5384 .phylink_mac_config = mv88e6xxx_mac_config, 5385 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5386 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5387 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5388 .get_strings = mv88e6xxx_get_strings, 5389 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5390 .get_sset_count = mv88e6xxx_get_sset_count, 5391 .port_enable = mv88e6xxx_port_enable, 5392 .port_disable = mv88e6xxx_port_disable, 5393 .port_max_mtu = mv88e6xxx_get_max_mtu, 5394 .port_change_mtu = mv88e6xxx_change_mtu, 5395 .get_mac_eee = mv88e6xxx_get_mac_eee, 5396 .set_mac_eee = mv88e6xxx_set_mac_eee, 5397 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5398 .get_eeprom = mv88e6xxx_get_eeprom, 5399 .set_eeprom = mv88e6xxx_set_eeprom, 5400 .get_regs_len = mv88e6xxx_get_regs_len, 5401 .get_regs = mv88e6xxx_get_regs, 5402 .get_rxnfc = mv88e6xxx_get_rxnfc, 5403 .set_rxnfc = mv88e6xxx_set_rxnfc, 5404 .set_ageing_time = mv88e6xxx_set_ageing_time, 5405 .port_bridge_join = mv88e6xxx_port_bridge_join, 5406 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5407 .port_egress_floods = mv88e6xxx_port_egress_floods, 5408 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5409 .port_fast_age = mv88e6xxx_port_fast_age, 5410 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5411 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5412 .port_vlan_add = mv88e6xxx_port_vlan_add, 5413 .port_vlan_del = mv88e6xxx_port_vlan_del, 5414 .port_fdb_add = mv88e6xxx_port_fdb_add, 5415 .port_fdb_del = mv88e6xxx_port_fdb_del, 5416 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5417 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5418 .port_mdb_add = mv88e6xxx_port_mdb_add, 5419 .port_mdb_del = mv88e6xxx_port_mdb_del, 5420 .port_mirror_add = mv88e6xxx_port_mirror_add, 5421 .port_mirror_del = mv88e6xxx_port_mirror_del, 5422 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5423 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5424 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5425 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5426 .port_txtstamp = mv88e6xxx_port_txtstamp, 5427 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5428 .get_ts_info = mv88e6xxx_get_ts_info, 5429 .devlink_param_get = mv88e6xxx_devlink_param_get, 5430 .devlink_param_set = mv88e6xxx_devlink_param_set, 5431 .devlink_info_get = mv88e6xxx_devlink_info_get, 5432 }; 5433 5434 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5435 { 5436 struct device *dev = chip->dev; 5437 struct dsa_switch *ds; 5438 5439 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5440 if (!ds) 5441 return -ENOMEM; 5442 5443 ds->dev = dev; 5444 ds->num_ports = mv88e6xxx_num_ports(chip); 5445 ds->priv = chip; 5446 ds->dev = dev; 5447 ds->ops = &mv88e6xxx_switch_ops; 5448 ds->ageing_time_min = chip->info->age_time_coeff; 5449 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5450 5451 dev_set_drvdata(dev, ds); 5452 5453 return dsa_register_switch(ds); 5454 } 5455 5456 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5457 { 5458 dsa_unregister_switch(chip->ds); 5459 } 5460 5461 static const void *pdata_device_get_match_data(struct device *dev) 5462 { 5463 const struct of_device_id *matches = dev->driver->of_match_table; 5464 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5465 5466 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5467 matches++) { 5468 if (!strcmp(pdata->compatible, matches->compatible)) 5469 return matches->data; 5470 } 5471 return NULL; 5472 } 5473 5474 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5475 * would be lost after a power cycle so prevent it to be suspended. 5476 */ 5477 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5478 { 5479 return -EOPNOTSUPP; 5480 } 5481 5482 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5483 { 5484 return 0; 5485 } 5486 5487 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5488 5489 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5490 { 5491 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5492 const struct mv88e6xxx_info *compat_info = NULL; 5493 struct device *dev = &mdiodev->dev; 5494 struct device_node *np = dev->of_node; 5495 struct mv88e6xxx_chip *chip; 5496 int port; 5497 int err; 5498 5499 if (!np && !pdata) 5500 return -EINVAL; 5501 5502 if (np) 5503 compat_info = of_device_get_match_data(dev); 5504 5505 if (pdata) { 5506 compat_info = pdata_device_get_match_data(dev); 5507 5508 if (!pdata->netdev) 5509 return -EINVAL; 5510 5511 for (port = 0; port < DSA_MAX_PORTS; port++) { 5512 if (!(pdata->enabled_ports & (1 << port))) 5513 continue; 5514 if (strcmp(pdata->cd.port_names[port], "cpu")) 5515 continue; 5516 pdata->cd.netdev[port] = &pdata->netdev->dev; 5517 break; 5518 } 5519 } 5520 5521 if (!compat_info) 5522 return -EINVAL; 5523 5524 chip = mv88e6xxx_alloc_chip(dev); 5525 if (!chip) { 5526 err = -ENOMEM; 5527 goto out; 5528 } 5529 5530 chip->info = compat_info; 5531 5532 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5533 if (err) 5534 goto out; 5535 5536 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5537 if (IS_ERR(chip->reset)) { 5538 err = PTR_ERR(chip->reset); 5539 goto out; 5540 } 5541 if (chip->reset) 5542 usleep_range(1000, 2000); 5543 5544 err = mv88e6xxx_detect(chip); 5545 if (err) 5546 goto out; 5547 5548 mv88e6xxx_phy_init(chip); 5549 5550 if (chip->info->ops->get_eeprom) { 5551 if (np) 5552 of_property_read_u32(np, "eeprom-length", 5553 &chip->eeprom_len); 5554 else 5555 chip->eeprom_len = pdata->eeprom_len; 5556 } 5557 5558 mv88e6xxx_reg_lock(chip); 5559 err = mv88e6xxx_switch_reset(chip); 5560 mv88e6xxx_reg_unlock(chip); 5561 if (err) 5562 goto out; 5563 5564 if (np) { 5565 chip->irq = of_irq_get(np, 0); 5566 if (chip->irq == -EPROBE_DEFER) { 5567 err = chip->irq; 5568 goto out; 5569 } 5570 } 5571 5572 if (pdata) 5573 chip->irq = pdata->irq; 5574 5575 /* Has to be performed before the MDIO bus is created, because 5576 * the PHYs will link their interrupts to these interrupt 5577 * controllers 5578 */ 5579 mv88e6xxx_reg_lock(chip); 5580 if (chip->irq > 0) 5581 err = mv88e6xxx_g1_irq_setup(chip); 5582 else 5583 err = mv88e6xxx_irq_poll_setup(chip); 5584 mv88e6xxx_reg_unlock(chip); 5585 5586 if (err) 5587 goto out; 5588 5589 if (chip->info->g2_irqs > 0) { 5590 err = mv88e6xxx_g2_irq_setup(chip); 5591 if (err) 5592 goto out_g1_irq; 5593 } 5594 5595 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5596 if (err) 5597 goto out_g2_irq; 5598 5599 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5600 if (err) 5601 goto out_g1_atu_prob_irq; 5602 5603 err = mv88e6xxx_mdios_register(chip, np); 5604 if (err) 5605 goto out_g1_vtu_prob_irq; 5606 5607 err = mv88e6xxx_register_switch(chip); 5608 if (err) 5609 goto out_mdio; 5610 5611 return 0; 5612 5613 out_mdio: 5614 mv88e6xxx_mdios_unregister(chip); 5615 out_g1_vtu_prob_irq: 5616 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5617 out_g1_atu_prob_irq: 5618 mv88e6xxx_g1_atu_prob_irq_free(chip); 5619 out_g2_irq: 5620 if (chip->info->g2_irqs > 0) 5621 mv88e6xxx_g2_irq_free(chip); 5622 out_g1_irq: 5623 if (chip->irq > 0) 5624 mv88e6xxx_g1_irq_free(chip); 5625 else 5626 mv88e6xxx_irq_poll_free(chip); 5627 out: 5628 if (pdata) 5629 dev_put(pdata->netdev); 5630 5631 return err; 5632 } 5633 5634 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5635 { 5636 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5637 struct mv88e6xxx_chip *chip = ds->priv; 5638 5639 if (chip->info->ptp_support) { 5640 mv88e6xxx_hwtstamp_free(chip); 5641 mv88e6xxx_ptp_free(chip); 5642 } 5643 5644 mv88e6xxx_phy_destroy(chip); 5645 mv88e6xxx_unregister_switch(chip); 5646 mv88e6xxx_mdios_unregister(chip); 5647 5648 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5649 mv88e6xxx_g1_atu_prob_irq_free(chip); 5650 5651 if (chip->info->g2_irqs > 0) 5652 mv88e6xxx_g2_irq_free(chip); 5653 5654 if (chip->irq > 0) 5655 mv88e6xxx_g1_irq_free(chip); 5656 else 5657 mv88e6xxx_irq_poll_free(chip); 5658 } 5659 5660 static const struct of_device_id mv88e6xxx_of_match[] = { 5661 { 5662 .compatible = "marvell,mv88e6085", 5663 .data = &mv88e6xxx_table[MV88E6085], 5664 }, 5665 { 5666 .compatible = "marvell,mv88e6190", 5667 .data = &mv88e6xxx_table[MV88E6190], 5668 }, 5669 { 5670 .compatible = "marvell,mv88e6250", 5671 .data = &mv88e6xxx_table[MV88E6250], 5672 }, 5673 { /* sentinel */ }, 5674 }; 5675 5676 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5677 5678 static struct mdio_driver mv88e6xxx_driver = { 5679 .probe = mv88e6xxx_probe, 5680 .remove = mv88e6xxx_remove, 5681 .mdiodrv.driver = { 5682 .name = "mv88e6085", 5683 .of_match_table = mv88e6xxx_of_match, 5684 .pm = &mv88e6xxx_pm_ops, 5685 }, 5686 }; 5687 5688 mdio_module_driver(mv88e6xxx_driver); 5689 5690 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5691 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5692 MODULE_LICENSE("GPL"); 5693