1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "serdes.h" 42 43 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 44 { 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 46 dev_err(chip->dev, "Switch registers lock not held!\n"); 47 dump_stack(); 48 } 49 } 50 51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 53 * 54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 55 * is the only device connected to the SMI master. In this mode it responds to 56 * all 32 possible SMI addresses, and thus maps directly the internal devices. 57 * 58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 59 * multiple devices to share the SMI interface. In this mode it responds to only 60 * 2 registers, used to indirectly access the internal SMI devices. 61 */ 62 63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 *val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->read(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 val) 74 { 75 if (!chip->smi_ops) 76 return -EOPNOTSUPP; 77 78 return chip->smi_ops->write(chip, addr, reg, val); 79 } 80 81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 82 int addr, int reg, u16 *val) 83 { 84 int ret; 85 86 ret = mdiobus_read_nested(chip->bus, addr, reg); 87 if (ret < 0) 88 return ret; 89 90 *val = ret & 0xffff; 91 92 return 0; 93 } 94 95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 96 int addr, int reg, u16 val) 97 { 98 int ret; 99 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 101 if (ret < 0) 102 return ret; 103 104 return 0; 105 } 106 107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 108 .read = mv88e6xxx_smi_single_chip_read, 109 .write = mv88e6xxx_smi_single_chip_write, 110 }; 111 112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 113 { 114 int ret; 115 int i; 116 117 for (i = 0; i < 16; i++) { 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 119 if (ret < 0) 120 return ret; 121 122 if ((ret & SMI_CMD_BUSY) == 0) 123 return 0; 124 } 125 126 return -ETIMEDOUT; 127 } 128 129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 130 int addr, int reg, u16 *val) 131 { 132 int ret; 133 134 /* Wait for the bus to become free. */ 135 ret = mv88e6xxx_smi_multi_chip_wait(chip); 136 if (ret < 0) 137 return ret; 138 139 /* Transmit the read command. */ 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 141 SMI_CMD_OP_22_READ | (addr << 5) | reg); 142 if (ret < 0) 143 return ret; 144 145 /* Wait for the read command to complete. */ 146 ret = mv88e6xxx_smi_multi_chip_wait(chip); 147 if (ret < 0) 148 return ret; 149 150 /* Read the data. */ 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 152 if (ret < 0) 153 return ret; 154 155 *val = ret & 0xffff; 156 157 return 0; 158 } 159 160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 161 int addr, int reg, u16 val) 162 { 163 int ret; 164 165 /* Wait for the bus to become free. */ 166 ret = mv88e6xxx_smi_multi_chip_wait(chip); 167 if (ret < 0) 168 return ret; 169 170 /* Transmit the data to write. */ 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 172 if (ret < 0) 173 return ret; 174 175 /* Transmit the write command. */ 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 178 if (ret < 0) 179 return ret; 180 181 /* Wait for the write command to complete. */ 182 ret = mv88e6xxx_smi_multi_chip_wait(chip); 183 if (ret < 0) 184 return ret; 185 186 return 0; 187 } 188 189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 190 .read = mv88e6xxx_smi_multi_chip_read, 191 .write = mv88e6xxx_smi_multi_chip_write, 192 }; 193 194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 195 { 196 int err; 197 198 assert_reg_lock(chip); 199 200 err = mv88e6xxx_smi_read(chip, addr, reg, val); 201 if (err) 202 return err; 203 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 205 addr, reg, *val); 206 207 return 0; 208 } 209 210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 211 { 212 int err; 213 214 assert_reg_lock(chip); 215 216 err = mv88e6xxx_smi_write(chip, addr, reg, val); 217 if (err) 218 return err; 219 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 221 addr, reg, val); 222 223 return 0; 224 } 225 226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 227 { 228 struct mv88e6xxx_mdio_bus *mdio_bus; 229 230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 231 list); 232 if (!mdio_bus) 233 return NULL; 234 235 return mdio_bus->bus; 236 } 237 238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 239 { 240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 241 unsigned int n = d->hwirq; 242 243 chip->g1_irq.masked |= (1 << n); 244 } 245 246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 247 { 248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 249 unsigned int n = d->hwirq; 250 251 chip->g1_irq.masked &= ~(1 << n); 252 } 253 254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 255 { 256 struct mv88e6xxx_chip *chip = dev_id; 257 unsigned int nhandled = 0; 258 unsigned int sub_irq; 259 unsigned int n; 260 u16 reg; 261 int err; 262 263 mutex_lock(&chip->reg_lock); 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 265 mutex_unlock(&chip->reg_lock); 266 267 if (err) 268 goto out; 269 270 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 271 if (reg & (1 << n)) { 272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 273 handle_nested_irq(sub_irq); 274 ++nhandled; 275 } 276 } 277 out: 278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 279 } 280 281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 282 { 283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 284 285 mutex_lock(&chip->reg_lock); 286 } 287 288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 289 { 290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 292 u16 reg; 293 int err; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 296 if (err) 297 goto out; 298 299 reg &= ~mask; 300 reg |= (~chip->g1_irq.masked & mask); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 303 if (err) 304 goto out; 305 306 out: 307 mutex_unlock(&chip->reg_lock); 308 } 309 310 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 311 .name = "mv88e6xxx-g1", 312 .irq_mask = mv88e6xxx_g1_irq_mask, 313 .irq_unmask = mv88e6xxx_g1_irq_unmask, 314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 316 }; 317 318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 319 unsigned int irq, 320 irq_hw_number_t hwirq) 321 { 322 struct mv88e6xxx_chip *chip = d->host_data; 323 324 irq_set_chip_data(irq, d->host_data); 325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 326 irq_set_noprobe(irq); 327 328 return 0; 329 } 330 331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 332 .map = mv88e6xxx_g1_irq_domain_map, 333 .xlate = irq_domain_xlate_twocell, 334 }; 335 336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 337 { 338 int irq, virq; 339 u16 mask; 340 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 342 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 344 345 free_irq(chip->irq, chip); 346 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 348 virq = irq_find_mapping(chip->g1_irq.domain, irq); 349 irq_dispose_mapping(virq); 350 } 351 352 irq_domain_remove(chip->g1_irq.domain); 353 } 354 355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 356 { 357 int err, irq, virq; 358 u16 reg, mask; 359 360 chip->g1_irq.nirqs = chip->info->g1_irqs; 361 chip->g1_irq.domain = irq_domain_add_simple( 362 NULL, chip->g1_irq.nirqs, 0, 363 &mv88e6xxx_g1_irq_domain_ops, chip); 364 if (!chip->g1_irq.domain) 365 return -ENOMEM; 366 367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 368 irq_create_mapping(chip->g1_irq.domain, irq); 369 370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 371 chip->g1_irq.masked = ~0; 372 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 374 if (err) 375 goto out_mapping; 376 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 378 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 380 if (err) 381 goto out_disable; 382 383 /* Reading the interrupt status clears (most of) them */ 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 385 if (err) 386 goto out_disable; 387 388 err = request_threaded_irq(chip->irq, NULL, 389 mv88e6xxx_g1_irq_thread_fn, 390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 391 dev_name(chip->dev), chip); 392 if (err) 393 goto out_disable; 394 395 return 0; 396 397 out_disable: 398 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 400 401 out_mapping: 402 for (irq = 0; irq < 16; irq++) { 403 virq = irq_find_mapping(chip->g1_irq.domain, irq); 404 irq_dispose_mapping(virq); 405 } 406 407 irq_domain_remove(chip->g1_irq.domain); 408 409 return err; 410 } 411 412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 413 { 414 int i; 415 416 for (i = 0; i < 16; i++) { 417 u16 val; 418 int err; 419 420 err = mv88e6xxx_read(chip, addr, reg, &val); 421 if (err) 422 return err; 423 424 if (!(val & mask)) 425 return 0; 426 427 usleep_range(1000, 2000); 428 } 429 430 dev_err(chip->dev, "Timeout while waiting for switch\n"); 431 return -ETIMEDOUT; 432 } 433 434 /* Indirect write to single pointer-data register with an Update bit */ 435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 436 { 437 u16 val; 438 int err; 439 440 /* Wait until the previous operation is completed */ 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 442 if (err) 443 return err; 444 445 /* Set the Update bit to trigger a write operation */ 446 val = BIT(15) | update; 447 448 return mv88e6xxx_write(chip, addr, reg, val); 449 } 450 451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 452 int link, int speed, int duplex, 453 phy_interface_t mode) 454 { 455 int err; 456 457 if (!chip->info->ops->port_set_link) 458 return 0; 459 460 /* Port's MAC control must not be changed unless the link is down */ 461 err = chip->info->ops->port_set_link(chip, port, 0); 462 if (err) 463 return err; 464 465 if (chip->info->ops->port_set_speed) { 466 err = chip->info->ops->port_set_speed(chip, port, speed); 467 if (err && err != -EOPNOTSUPP) 468 goto restore_link; 469 } 470 471 if (chip->info->ops->port_set_duplex) { 472 err = chip->info->ops->port_set_duplex(chip, port, duplex); 473 if (err && err != -EOPNOTSUPP) 474 goto restore_link; 475 } 476 477 if (chip->info->ops->port_set_rgmii_delay) { 478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 479 if (err && err != -EOPNOTSUPP) 480 goto restore_link; 481 } 482 483 if (chip->info->ops->port_set_cmode) { 484 err = chip->info->ops->port_set_cmode(chip, port, mode); 485 if (err && err != -EOPNOTSUPP) 486 goto restore_link; 487 } 488 489 err = 0; 490 restore_link: 491 if (chip->info->ops->port_set_link(chip, port, link)) 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 493 494 return err; 495 } 496 497 /* We expect the switch to perform auto negotiation if there is a real 498 * phy. However, in the case of a fixed link phy, we force the port 499 * settings from the fixed link settings. 500 */ 501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 502 struct phy_device *phydev) 503 { 504 struct mv88e6xxx_chip *chip = ds->priv; 505 int err; 506 507 if (!phy_is_pseudo_fixed_link(phydev)) 508 return; 509 510 mutex_lock(&chip->reg_lock); 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 512 phydev->duplex, phydev->interface); 513 mutex_unlock(&chip->reg_lock); 514 515 if (err && err != -EOPNOTSUPP) 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 517 } 518 519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 if (!chip->info->ops->stats_snapshot) 522 return -EOPNOTSUPP; 523 524 return chip->info->ops->stats_snapshot(chip, port); 525 } 526 527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 548 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 551 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 587 }; 588 589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 590 struct mv88e6xxx_hw_stat *s, 591 int port, u16 bank1_select, 592 u16 histogram) 593 { 594 u32 low; 595 u32 high = 0; 596 u16 reg = 0; 597 int err; 598 u64 value; 599 600 switch (s->type) { 601 case STATS_TYPE_PORT: 602 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 603 if (err) 604 return UINT64_MAX; 605 606 low = reg; 607 if (s->sizeof_stat == 4) { 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 609 if (err) 610 return UINT64_MAX; 611 high = reg; 612 } 613 break; 614 case STATS_TYPE_BANK1: 615 reg = bank1_select; 616 /* fall through */ 617 case STATS_TYPE_BANK0: 618 reg |= s->reg | histogram; 619 mv88e6xxx_g1_stats_read(chip, reg, &low); 620 if (s->sizeof_stat == 8) 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 622 break; 623 default: 624 return UINT64_MAX; 625 } 626 value = (((u64)high) << 16) | low; 627 return value; 628 } 629 630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 631 uint8_t *data, int types) 632 { 633 struct mv88e6xxx_hw_stat *stat; 634 int i, j; 635 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 637 stat = &mv88e6xxx_hw_stats[i]; 638 if (stat->type & types) { 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 640 ETH_GSTRING_LEN); 641 j++; 642 } 643 } 644 } 645 646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 647 uint8_t *data) 648 { 649 mv88e6xxx_stats_get_strings(chip, data, 650 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 651 } 652 653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 654 uint8_t *data) 655 { 656 mv88e6xxx_stats_get_strings(chip, data, 657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 658 } 659 660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 661 uint8_t *data) 662 { 663 struct mv88e6xxx_chip *chip = ds->priv; 664 665 if (chip->info->ops->stats_get_strings) 666 chip->info->ops->stats_get_strings(chip, data); 667 } 668 669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 670 int types) 671 { 672 struct mv88e6xxx_hw_stat *stat; 673 int i, j; 674 675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 676 stat = &mv88e6xxx_hw_stats[i]; 677 if (stat->type & types) 678 j++; 679 } 680 return j; 681 } 682 683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 684 { 685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 686 STATS_TYPE_PORT); 687 } 688 689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 692 STATS_TYPE_BANK1); 693 } 694 695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 696 { 697 struct mv88e6xxx_chip *chip = ds->priv; 698 699 if (chip->info->ops->stats_get_sset_count) 700 return chip->info->ops->stats_get_sset_count(chip); 701 702 return 0; 703 } 704 705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 706 uint64_t *data, int types, 707 u16 bank1_select, u16 histogram) 708 { 709 struct mv88e6xxx_hw_stat *stat; 710 int i, j; 711 712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 713 stat = &mv88e6xxx_hw_stats[i]; 714 if (stat->type & types) { 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 716 bank1_select, 717 histogram); 718 j++; 719 } 720 } 721 } 722 723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 724 uint64_t *data) 725 { 726 return mv88e6xxx_stats_get_stats(chip, port, data, 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 729 } 730 731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 732 uint64_t *data) 733 { 734 return mv88e6xxx_stats_get_stats(chip, port, data, 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 738 } 739 740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 741 uint64_t *data) 742 { 743 return mv88e6xxx_stats_get_stats(chip, port, data, 744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 746 0); 747 } 748 749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 750 uint64_t *data) 751 { 752 if (chip->info->ops->stats_get_stats) 753 chip->info->ops->stats_get_stats(chip, port, data); 754 } 755 756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 757 uint64_t *data) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 int ret; 761 762 mutex_lock(&chip->reg_lock); 763 764 ret = mv88e6xxx_stats_snapshot(chip, port); 765 if (ret < 0) { 766 mutex_unlock(&chip->reg_lock); 767 return; 768 } 769 770 mv88e6xxx_get_stats(chip, port, data); 771 772 mutex_unlock(&chip->reg_lock); 773 } 774 775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 776 { 777 if (chip->info->ops->stats_set_histogram) 778 return chip->info->ops->stats_set_histogram(chip); 779 780 return 0; 781 } 782 783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 784 { 785 return 32 * sizeof(u16); 786 } 787 788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 789 struct ethtool_regs *regs, void *_p) 790 { 791 struct mv88e6xxx_chip *chip = ds->priv; 792 int err; 793 u16 reg; 794 u16 *p = _p; 795 int i; 796 797 regs->version = 0; 798 799 memset(p, 0xff, 32 * sizeof(u16)); 800 801 mutex_lock(&chip->reg_lock); 802 803 for (i = 0; i < 32; i++) { 804 805 err = mv88e6xxx_port_read(chip, port, i, ®); 806 if (!err) 807 p[i] = reg; 808 } 809 810 mutex_unlock(&chip->reg_lock); 811 } 812 813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 814 struct ethtool_eee *e) 815 { 816 /* Nothing to do on the port's MAC */ 817 return 0; 818 } 819 820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 821 struct ethtool_eee *e) 822 { 823 /* Nothing to do on the port's MAC */ 824 return 0; 825 } 826 827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 828 { 829 struct dsa_switch *ds = NULL; 830 struct net_device *br; 831 u16 pvlan; 832 int i; 833 834 if (dev < DSA_MAX_SWITCHES) 835 ds = chip->ds->dst->ds[dev]; 836 837 /* Prevent frames from unknown switch or port */ 838 if (!ds || port >= ds->num_ports) 839 return 0; 840 841 /* Frames from DSA links and CPU ports can egress any local port */ 842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 843 return mv88e6xxx_port_mask(chip); 844 845 br = ds->ports[port].bridge_dev; 846 pvlan = 0; 847 848 /* Frames from user ports can egress any local DSA links and CPU ports, 849 * as well as any local member of their bridge group. 850 */ 851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 852 if (dsa_is_cpu_port(chip->ds, i) || 853 dsa_is_dsa_port(chip->ds, i) || 854 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 855 pvlan |= BIT(i); 856 857 return pvlan; 858 } 859 860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 861 { 862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 863 864 /* prevent frames from going back out of the port they came in on */ 865 output_ports &= ~BIT(port); 866 867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 868 } 869 870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 871 u8 state) 872 { 873 struct mv88e6xxx_chip *chip = ds->priv; 874 int err; 875 876 mutex_lock(&chip->reg_lock); 877 err = mv88e6xxx_port_set_state(chip, port, state); 878 mutex_unlock(&chip->reg_lock); 879 880 if (err) 881 dev_err(ds->dev, "p%d: failed to update state\n", port); 882 } 883 884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 885 { 886 if (chip->info->ops->pot_clear) 887 return chip->info->ops->pot_clear(chip); 888 889 return 0; 890 } 891 892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 893 { 894 if (chip->info->ops->mgmt_rsvd2cpu) 895 return chip->info->ops->mgmt_rsvd2cpu(chip); 896 897 return 0; 898 } 899 900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 901 { 902 int err; 903 904 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 905 if (err) 906 return err; 907 908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 909 if (err) 910 return err; 911 912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 913 } 914 915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 916 { 917 int port; 918 int err; 919 920 if (!chip->info->ops->irl_init_all) 921 return 0; 922 923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 924 /* Disable ingress rate limiting by resetting all per port 925 * ingress rate limit resources to their initial state. 926 */ 927 err = chip->info->ops->irl_init_all(chip, port); 928 if (err) 929 return err; 930 } 931 932 return 0; 933 } 934 935 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 936 { 937 if (chip->info->ops->set_switch_mac) { 938 u8 addr[ETH_ALEN]; 939 940 eth_random_addr(addr); 941 942 return chip->info->ops->set_switch_mac(chip, addr); 943 } 944 945 return 0; 946 } 947 948 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 949 { 950 u16 pvlan = 0; 951 952 if (!mv88e6xxx_has_pvt(chip)) 953 return -EOPNOTSUPP; 954 955 /* Skip the local source device, which uses in-chip port VLAN */ 956 if (dev != chip->ds->index) 957 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 958 959 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 960 } 961 962 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 963 { 964 int dev, port; 965 int err; 966 967 if (!mv88e6xxx_has_pvt(chip)) 968 return 0; 969 970 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 971 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 972 */ 973 err = mv88e6xxx_g2_misc_4_bit_port(chip); 974 if (err) 975 return err; 976 977 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 978 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 979 err = mv88e6xxx_pvt_map(chip, dev, port); 980 if (err) 981 return err; 982 } 983 } 984 985 return 0; 986 } 987 988 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 989 { 990 struct mv88e6xxx_chip *chip = ds->priv; 991 int err; 992 993 mutex_lock(&chip->reg_lock); 994 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 995 mutex_unlock(&chip->reg_lock); 996 997 if (err) 998 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 999 } 1000 1001 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1002 { 1003 if (!chip->info->max_vid) 1004 return 0; 1005 1006 return mv88e6xxx_g1_vtu_flush(chip); 1007 } 1008 1009 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1010 struct mv88e6xxx_vtu_entry *entry) 1011 { 1012 if (!chip->info->ops->vtu_getnext) 1013 return -EOPNOTSUPP; 1014 1015 return chip->info->ops->vtu_getnext(chip, entry); 1016 } 1017 1018 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1019 struct mv88e6xxx_vtu_entry *entry) 1020 { 1021 if (!chip->info->ops->vtu_loadpurge) 1022 return -EOPNOTSUPP; 1023 1024 return chip->info->ops->vtu_loadpurge(chip, entry); 1025 } 1026 1027 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1028 { 1029 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1030 struct mv88e6xxx_vtu_entry vlan = { 1031 .vid = chip->info->max_vid, 1032 }; 1033 int i, err; 1034 1035 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1036 1037 /* Set every FID bit used by the (un)bridged ports */ 1038 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1039 err = mv88e6xxx_port_get_fid(chip, i, fid); 1040 if (err) 1041 return err; 1042 1043 set_bit(*fid, fid_bitmap); 1044 } 1045 1046 /* Set every FID bit used by the VLAN entries */ 1047 do { 1048 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1049 if (err) 1050 return err; 1051 1052 if (!vlan.valid) 1053 break; 1054 1055 set_bit(vlan.fid, fid_bitmap); 1056 } while (vlan.vid < chip->info->max_vid); 1057 1058 /* The reset value 0x000 is used to indicate that multiple address 1059 * databases are not needed. Return the next positive available. 1060 */ 1061 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1062 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1063 return -ENOSPC; 1064 1065 /* Clear the database */ 1066 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1067 } 1068 1069 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1070 struct mv88e6xxx_vtu_entry *entry, bool new) 1071 { 1072 int err; 1073 1074 if (!vid) 1075 return -EINVAL; 1076 1077 entry->vid = vid - 1; 1078 entry->valid = false; 1079 1080 err = mv88e6xxx_vtu_getnext(chip, entry); 1081 if (err) 1082 return err; 1083 1084 if (entry->vid == vid && entry->valid) 1085 return 0; 1086 1087 if (new) { 1088 int i; 1089 1090 /* Initialize a fresh VLAN entry */ 1091 memset(entry, 0, sizeof(*entry)); 1092 entry->valid = true; 1093 entry->vid = vid; 1094 1095 /* Exclude all ports */ 1096 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1097 entry->member[i] = 1098 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1099 1100 return mv88e6xxx_atu_new(chip, &entry->fid); 1101 } 1102 1103 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1104 return -EOPNOTSUPP; 1105 } 1106 1107 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1108 u16 vid_begin, u16 vid_end) 1109 { 1110 struct mv88e6xxx_chip *chip = ds->priv; 1111 struct mv88e6xxx_vtu_entry vlan = { 1112 .vid = vid_begin - 1, 1113 }; 1114 int i, err; 1115 1116 /* DSA and CPU ports have to be members of multiple vlans */ 1117 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1118 return 0; 1119 1120 if (!vid_begin) 1121 return -EOPNOTSUPP; 1122 1123 mutex_lock(&chip->reg_lock); 1124 1125 do { 1126 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1127 if (err) 1128 goto unlock; 1129 1130 if (!vlan.valid) 1131 break; 1132 1133 if (vlan.vid > vid_end) 1134 break; 1135 1136 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1137 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1138 continue; 1139 1140 if (!ds->ports[i].slave) 1141 continue; 1142 1143 if (vlan.member[i] == 1144 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1145 continue; 1146 1147 if (dsa_to_port(ds, i)->bridge_dev == 1148 ds->ports[port].bridge_dev) 1149 break; /* same bridge, check next VLAN */ 1150 1151 if (!dsa_to_port(ds, i)->bridge_dev) 1152 continue; 1153 1154 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1155 port, vlan.vid, i, 1156 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1157 err = -EOPNOTSUPP; 1158 goto unlock; 1159 } 1160 } while (vlan.vid < vid_end); 1161 1162 unlock: 1163 mutex_unlock(&chip->reg_lock); 1164 1165 return err; 1166 } 1167 1168 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1169 bool vlan_filtering) 1170 { 1171 struct mv88e6xxx_chip *chip = ds->priv; 1172 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1173 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1174 int err; 1175 1176 if (!chip->info->max_vid) 1177 return -EOPNOTSUPP; 1178 1179 mutex_lock(&chip->reg_lock); 1180 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1181 mutex_unlock(&chip->reg_lock); 1182 1183 return err; 1184 } 1185 1186 static int 1187 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1188 const struct switchdev_obj_port_vlan *vlan) 1189 { 1190 struct mv88e6xxx_chip *chip = ds->priv; 1191 int err; 1192 1193 if (!chip->info->max_vid) 1194 return -EOPNOTSUPP; 1195 1196 /* If the requested port doesn't belong to the same bridge as the VLAN 1197 * members, do not support it (yet) and fallback to software VLAN. 1198 */ 1199 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1200 vlan->vid_end); 1201 if (err) 1202 return err; 1203 1204 /* We don't need any dynamic resource from the kernel (yet), 1205 * so skip the prepare phase. 1206 */ 1207 return 0; 1208 } 1209 1210 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1211 const unsigned char *addr, u16 vid, 1212 u8 state) 1213 { 1214 struct mv88e6xxx_vtu_entry vlan; 1215 struct mv88e6xxx_atu_entry entry; 1216 int err; 1217 1218 /* Null VLAN ID corresponds to the port private database */ 1219 if (vid == 0) 1220 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1221 else 1222 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1223 if (err) 1224 return err; 1225 1226 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1227 ether_addr_copy(entry.mac, addr); 1228 eth_addr_dec(entry.mac); 1229 1230 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1231 if (err) 1232 return err; 1233 1234 /* Initialize a fresh ATU entry if it isn't found */ 1235 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1236 !ether_addr_equal(entry.mac, addr)) { 1237 memset(&entry, 0, sizeof(entry)); 1238 ether_addr_copy(entry.mac, addr); 1239 } 1240 1241 /* Purge the ATU entry only if no port is using it anymore */ 1242 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1243 entry.portvec &= ~BIT(port); 1244 if (!entry.portvec) 1245 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1246 } else { 1247 entry.portvec |= BIT(port); 1248 entry.state = state; 1249 } 1250 1251 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1252 } 1253 1254 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1255 u16 vid) 1256 { 1257 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1258 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1259 1260 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1261 } 1262 1263 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1264 { 1265 int port; 1266 int err; 1267 1268 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1269 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1270 if (err) 1271 return err; 1272 } 1273 1274 return 0; 1275 } 1276 1277 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1278 u16 vid, u8 member) 1279 { 1280 struct mv88e6xxx_vtu_entry vlan; 1281 int err; 1282 1283 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1284 if (err) 1285 return err; 1286 1287 vlan.member[port] = member; 1288 1289 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1290 if (err) 1291 return err; 1292 1293 return mv88e6xxx_broadcast_setup(chip, vid); 1294 } 1295 1296 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1297 const struct switchdev_obj_port_vlan *vlan) 1298 { 1299 struct mv88e6xxx_chip *chip = ds->priv; 1300 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1301 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1302 u8 member; 1303 u16 vid; 1304 1305 if (!chip->info->max_vid) 1306 return; 1307 1308 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1309 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1310 else if (untagged) 1311 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1312 else 1313 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1314 1315 mutex_lock(&chip->reg_lock); 1316 1317 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1318 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1319 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1320 vid, untagged ? 'u' : 't'); 1321 1322 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1323 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1324 vlan->vid_end); 1325 1326 mutex_unlock(&chip->reg_lock); 1327 } 1328 1329 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1330 int port, u16 vid) 1331 { 1332 struct mv88e6xxx_vtu_entry vlan; 1333 int i, err; 1334 1335 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1336 if (err) 1337 return err; 1338 1339 /* Tell switchdev if this VLAN is handled in software */ 1340 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1341 return -EOPNOTSUPP; 1342 1343 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1344 1345 /* keep the VLAN unless all ports are excluded */ 1346 vlan.valid = false; 1347 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1348 if (vlan.member[i] != 1349 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1350 vlan.valid = true; 1351 break; 1352 } 1353 } 1354 1355 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1356 if (err) 1357 return err; 1358 1359 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1360 } 1361 1362 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1363 const struct switchdev_obj_port_vlan *vlan) 1364 { 1365 struct mv88e6xxx_chip *chip = ds->priv; 1366 u16 pvid, vid; 1367 int err = 0; 1368 1369 if (!chip->info->max_vid) 1370 return -EOPNOTSUPP; 1371 1372 mutex_lock(&chip->reg_lock); 1373 1374 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1375 if (err) 1376 goto unlock; 1377 1378 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1379 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1380 if (err) 1381 goto unlock; 1382 1383 if (vid == pvid) { 1384 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1385 if (err) 1386 goto unlock; 1387 } 1388 } 1389 1390 unlock: 1391 mutex_unlock(&chip->reg_lock); 1392 1393 return err; 1394 } 1395 1396 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1397 const unsigned char *addr, u16 vid) 1398 { 1399 struct mv88e6xxx_chip *chip = ds->priv; 1400 int err; 1401 1402 mutex_lock(&chip->reg_lock); 1403 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1404 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1405 mutex_unlock(&chip->reg_lock); 1406 1407 return err; 1408 } 1409 1410 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1411 const unsigned char *addr, u16 vid) 1412 { 1413 struct mv88e6xxx_chip *chip = ds->priv; 1414 int err; 1415 1416 mutex_lock(&chip->reg_lock); 1417 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1418 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1419 mutex_unlock(&chip->reg_lock); 1420 1421 return err; 1422 } 1423 1424 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1425 u16 fid, u16 vid, int port, 1426 dsa_fdb_dump_cb_t *cb, void *data) 1427 { 1428 struct mv88e6xxx_atu_entry addr; 1429 bool is_static; 1430 int err; 1431 1432 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1433 eth_broadcast_addr(addr.mac); 1434 1435 do { 1436 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1437 if (err) 1438 return err; 1439 1440 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1441 break; 1442 1443 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1444 continue; 1445 1446 if (!is_unicast_ether_addr(addr.mac)) 1447 continue; 1448 1449 is_static = (addr.state == 1450 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1451 err = cb(addr.mac, vid, is_static, data); 1452 if (err) 1453 return err; 1454 } while (!is_broadcast_ether_addr(addr.mac)); 1455 1456 return err; 1457 } 1458 1459 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1460 dsa_fdb_dump_cb_t *cb, void *data) 1461 { 1462 struct mv88e6xxx_vtu_entry vlan = { 1463 .vid = chip->info->max_vid, 1464 }; 1465 u16 fid; 1466 int err; 1467 1468 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1469 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1470 if (err) 1471 return err; 1472 1473 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1474 if (err) 1475 return err; 1476 1477 /* Dump VLANs' Filtering Information Databases */ 1478 do { 1479 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1480 if (err) 1481 return err; 1482 1483 if (!vlan.valid) 1484 break; 1485 1486 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1487 cb, data); 1488 if (err) 1489 return err; 1490 } while (vlan.vid < chip->info->max_vid); 1491 1492 return err; 1493 } 1494 1495 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1496 dsa_fdb_dump_cb_t *cb, void *data) 1497 { 1498 struct mv88e6xxx_chip *chip = ds->priv; 1499 int err; 1500 1501 mutex_lock(&chip->reg_lock); 1502 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1503 mutex_unlock(&chip->reg_lock); 1504 1505 return err; 1506 } 1507 1508 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1509 struct net_device *br) 1510 { 1511 struct dsa_switch *ds; 1512 int port; 1513 int dev; 1514 int err; 1515 1516 /* Remap the Port VLAN of each local bridge group member */ 1517 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1518 if (chip->ds->ports[port].bridge_dev == br) { 1519 err = mv88e6xxx_port_vlan_map(chip, port); 1520 if (err) 1521 return err; 1522 } 1523 } 1524 1525 if (!mv88e6xxx_has_pvt(chip)) 1526 return 0; 1527 1528 /* Remap the Port VLAN of each cross-chip bridge group member */ 1529 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1530 ds = chip->ds->dst->ds[dev]; 1531 if (!ds) 1532 break; 1533 1534 for (port = 0; port < ds->num_ports; ++port) { 1535 if (ds->ports[port].bridge_dev == br) { 1536 err = mv88e6xxx_pvt_map(chip, dev, port); 1537 if (err) 1538 return err; 1539 } 1540 } 1541 } 1542 1543 return 0; 1544 } 1545 1546 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1547 struct net_device *br) 1548 { 1549 struct mv88e6xxx_chip *chip = ds->priv; 1550 int err; 1551 1552 mutex_lock(&chip->reg_lock); 1553 err = mv88e6xxx_bridge_map(chip, br); 1554 mutex_unlock(&chip->reg_lock); 1555 1556 return err; 1557 } 1558 1559 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1560 struct net_device *br) 1561 { 1562 struct mv88e6xxx_chip *chip = ds->priv; 1563 1564 mutex_lock(&chip->reg_lock); 1565 if (mv88e6xxx_bridge_map(chip, br) || 1566 mv88e6xxx_port_vlan_map(chip, port)) 1567 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1568 mutex_unlock(&chip->reg_lock); 1569 } 1570 1571 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1572 int port, struct net_device *br) 1573 { 1574 struct mv88e6xxx_chip *chip = ds->priv; 1575 int err; 1576 1577 if (!mv88e6xxx_has_pvt(chip)) 1578 return 0; 1579 1580 mutex_lock(&chip->reg_lock); 1581 err = mv88e6xxx_pvt_map(chip, dev, port); 1582 mutex_unlock(&chip->reg_lock); 1583 1584 return err; 1585 } 1586 1587 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1588 int port, struct net_device *br) 1589 { 1590 struct mv88e6xxx_chip *chip = ds->priv; 1591 1592 if (!mv88e6xxx_has_pvt(chip)) 1593 return; 1594 1595 mutex_lock(&chip->reg_lock); 1596 if (mv88e6xxx_pvt_map(chip, dev, port)) 1597 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1598 mutex_unlock(&chip->reg_lock); 1599 } 1600 1601 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1602 { 1603 if (chip->info->ops->reset) 1604 return chip->info->ops->reset(chip); 1605 1606 return 0; 1607 } 1608 1609 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1610 { 1611 struct gpio_desc *gpiod = chip->reset; 1612 1613 /* If there is a GPIO connected to the reset pin, toggle it */ 1614 if (gpiod) { 1615 gpiod_set_value_cansleep(gpiod, 1); 1616 usleep_range(10000, 20000); 1617 gpiod_set_value_cansleep(gpiod, 0); 1618 usleep_range(10000, 20000); 1619 } 1620 } 1621 1622 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1623 { 1624 int i, err; 1625 1626 /* Set all ports to the Disabled state */ 1627 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1628 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1629 if (err) 1630 return err; 1631 } 1632 1633 /* Wait for transmit queues to drain, 1634 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1635 */ 1636 usleep_range(2000, 4000); 1637 1638 return 0; 1639 } 1640 1641 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1642 { 1643 int err; 1644 1645 err = mv88e6xxx_disable_ports(chip); 1646 if (err) 1647 return err; 1648 1649 mv88e6xxx_hardware_reset(chip); 1650 1651 return mv88e6xxx_software_reset(chip); 1652 } 1653 1654 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1655 enum mv88e6xxx_frame_mode frame, 1656 enum mv88e6xxx_egress_mode egress, u16 etype) 1657 { 1658 int err; 1659 1660 if (!chip->info->ops->port_set_frame_mode) 1661 return -EOPNOTSUPP; 1662 1663 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1664 if (err) 1665 return err; 1666 1667 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1668 if (err) 1669 return err; 1670 1671 if (chip->info->ops->port_set_ether_type) 1672 return chip->info->ops->port_set_ether_type(chip, port, etype); 1673 1674 return 0; 1675 } 1676 1677 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1678 { 1679 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1680 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1681 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1682 } 1683 1684 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1685 { 1686 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1687 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1688 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1689 } 1690 1691 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1692 { 1693 return mv88e6xxx_set_port_mode(chip, port, 1694 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1695 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1696 ETH_P_EDSA); 1697 } 1698 1699 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1700 { 1701 if (dsa_is_dsa_port(chip->ds, port)) 1702 return mv88e6xxx_set_port_mode_dsa(chip, port); 1703 1704 if (dsa_is_user_port(chip->ds, port)) 1705 return mv88e6xxx_set_port_mode_normal(chip, port); 1706 1707 /* Setup CPU port mode depending on its supported tag format */ 1708 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1709 return mv88e6xxx_set_port_mode_dsa(chip, port); 1710 1711 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1712 return mv88e6xxx_set_port_mode_edsa(chip, port); 1713 1714 return -EINVAL; 1715 } 1716 1717 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1718 { 1719 bool message = dsa_is_dsa_port(chip->ds, port); 1720 1721 return mv88e6xxx_port_set_message_port(chip, port, message); 1722 } 1723 1724 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1725 { 1726 struct dsa_switch *ds = chip->ds; 1727 bool flood; 1728 1729 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1730 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 1731 if (chip->info->ops->port_set_egress_floods) 1732 return chip->info->ops->port_set_egress_floods(chip, port, 1733 flood, flood); 1734 1735 return 0; 1736 } 1737 1738 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1739 bool on) 1740 { 1741 if (chip->info->ops->serdes_power) 1742 return chip->info->ops->serdes_power(chip, port, on); 1743 1744 return 0; 1745 } 1746 1747 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 1748 { 1749 struct dsa_switch *ds = chip->ds; 1750 int upstream_port; 1751 int err; 1752 1753 upstream_port = dsa_upstream_port(ds, port); 1754 if (chip->info->ops->port_set_upstream_port) { 1755 err = chip->info->ops->port_set_upstream_port(chip, port, 1756 upstream_port); 1757 if (err) 1758 return err; 1759 } 1760 1761 if (port == upstream_port) { 1762 if (chip->info->ops->set_cpu_port) { 1763 err = chip->info->ops->set_cpu_port(chip, 1764 upstream_port); 1765 if (err) 1766 return err; 1767 } 1768 1769 if (chip->info->ops->set_egress_port) { 1770 err = chip->info->ops->set_egress_port(chip, 1771 upstream_port); 1772 if (err) 1773 return err; 1774 } 1775 } 1776 1777 return 0; 1778 } 1779 1780 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1781 { 1782 struct dsa_switch *ds = chip->ds; 1783 int err; 1784 u16 reg; 1785 1786 /* MAC Forcing register: don't force link, speed, duplex or flow control 1787 * state to any particular values on physical ports, but force the CPU 1788 * port and all DSA ports to their maximum bandwidth and full duplex. 1789 */ 1790 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1791 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1792 SPEED_MAX, DUPLEX_FULL, 1793 PHY_INTERFACE_MODE_NA); 1794 else 1795 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1796 SPEED_UNFORCED, DUPLEX_UNFORCED, 1797 PHY_INTERFACE_MODE_NA); 1798 if (err) 1799 return err; 1800 1801 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1802 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1803 * tunneling, determine priority by looking at 802.1p and IP 1804 * priority fields (IP prio has precedence), and set STP state 1805 * to Forwarding. 1806 * 1807 * If this is the CPU link, use DSA or EDSA tagging depending 1808 * on which tagging mode was configured. 1809 * 1810 * If this is a link to another switch, use DSA tagging mode. 1811 * 1812 * If this is the upstream port for this switch, enable 1813 * forwarding of unknown unicasts and multicasts. 1814 */ 1815 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1816 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1817 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1818 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1819 if (err) 1820 return err; 1821 1822 err = mv88e6xxx_setup_port_mode(chip, port); 1823 if (err) 1824 return err; 1825 1826 err = mv88e6xxx_setup_egress_floods(chip, port); 1827 if (err) 1828 return err; 1829 1830 /* Enable the SERDES interface for DSA and CPU ports. Normal 1831 * ports SERDES are enabled when the port is enabled, thus 1832 * saving a bit of power. 1833 */ 1834 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1835 err = mv88e6xxx_serdes_power(chip, port, true); 1836 if (err) 1837 return err; 1838 } 1839 1840 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1841 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1842 * untagged frames on this port, do a destination address lookup on all 1843 * received packets as usual, disable ARP mirroring and don't send a 1844 * copy of all transmitted/received frames on this port to the CPU. 1845 */ 1846 err = mv88e6xxx_port_set_map_da(chip, port); 1847 if (err) 1848 return err; 1849 1850 err = mv88e6xxx_setup_upstream_port(chip, port); 1851 if (err) 1852 return err; 1853 1854 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1855 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1856 if (err) 1857 return err; 1858 1859 if (chip->info->ops->port_set_jumbo_size) { 1860 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1861 if (err) 1862 return err; 1863 } 1864 1865 /* Port Association Vector: when learning source addresses 1866 * of packets, add the address to the address database using 1867 * a port bitmap that has only the bit for this port set and 1868 * the other bits clear. 1869 */ 1870 reg = 1 << port; 1871 /* Disable learning for CPU port */ 1872 if (dsa_is_cpu_port(ds, port)) 1873 reg = 0; 1874 1875 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1876 reg); 1877 if (err) 1878 return err; 1879 1880 /* Egress rate control 2: disable egress rate control. */ 1881 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1882 0x0000); 1883 if (err) 1884 return err; 1885 1886 if (chip->info->ops->port_pause_limit) { 1887 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1888 if (err) 1889 return err; 1890 } 1891 1892 if (chip->info->ops->port_disable_learn_limit) { 1893 err = chip->info->ops->port_disable_learn_limit(chip, port); 1894 if (err) 1895 return err; 1896 } 1897 1898 if (chip->info->ops->port_disable_pri_override) { 1899 err = chip->info->ops->port_disable_pri_override(chip, port); 1900 if (err) 1901 return err; 1902 } 1903 1904 if (chip->info->ops->port_tag_remap) { 1905 err = chip->info->ops->port_tag_remap(chip, port); 1906 if (err) 1907 return err; 1908 } 1909 1910 if (chip->info->ops->port_egress_rate_limiting) { 1911 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1912 if (err) 1913 return err; 1914 } 1915 1916 err = mv88e6xxx_setup_message_port(chip, port); 1917 if (err) 1918 return err; 1919 1920 /* Port based VLAN map: give each port the same default address 1921 * database, and allow bidirectional communication between the 1922 * CPU and DSA port(s), and the other ports. 1923 */ 1924 err = mv88e6xxx_port_set_fid(chip, port, 0); 1925 if (err) 1926 return err; 1927 1928 err = mv88e6xxx_port_vlan_map(chip, port); 1929 if (err) 1930 return err; 1931 1932 /* Default VLAN ID and priority: don't set a default VLAN 1933 * ID, and set the default packet priority to zero. 1934 */ 1935 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 1936 } 1937 1938 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 1939 struct phy_device *phydev) 1940 { 1941 struct mv88e6xxx_chip *chip = ds->priv; 1942 int err; 1943 1944 mutex_lock(&chip->reg_lock); 1945 err = mv88e6xxx_serdes_power(chip, port, true); 1946 mutex_unlock(&chip->reg_lock); 1947 1948 return err; 1949 } 1950 1951 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 1952 struct phy_device *phydev) 1953 { 1954 struct mv88e6xxx_chip *chip = ds->priv; 1955 1956 mutex_lock(&chip->reg_lock); 1957 if (mv88e6xxx_serdes_power(chip, port, false)) 1958 dev_err(chip->dev, "failed to power off SERDES\n"); 1959 mutex_unlock(&chip->reg_lock); 1960 } 1961 1962 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 1963 unsigned int ageing_time) 1964 { 1965 struct mv88e6xxx_chip *chip = ds->priv; 1966 int err; 1967 1968 mutex_lock(&chip->reg_lock); 1969 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 1970 mutex_unlock(&chip->reg_lock); 1971 1972 return err; 1973 } 1974 1975 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 1976 { 1977 struct dsa_switch *ds = chip->ds; 1978 int err; 1979 1980 /* Disable remote management, and set the switch's DSA device number. */ 1981 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 1982 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 1983 (ds->index & 0x1f)); 1984 if (err) 1985 return err; 1986 1987 /* Configure the IP ToS mapping registers. */ 1988 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 1989 if (err) 1990 return err; 1991 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 1992 if (err) 1993 return err; 1994 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 1995 if (err) 1996 return err; 1997 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 1998 if (err) 1999 return err; 2000 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 2001 if (err) 2002 return err; 2003 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 2004 if (err) 2005 return err; 2006 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 2007 if (err) 2008 return err; 2009 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 2010 if (err) 2011 return err; 2012 2013 /* Configure the IEEE 802.1p priority mapping register. */ 2014 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 2015 if (err) 2016 return err; 2017 2018 /* Initialize the statistics unit */ 2019 err = mv88e6xxx_stats_set_histogram(chip); 2020 if (err) 2021 return err; 2022 2023 return mv88e6xxx_g1_stats_clear(chip); 2024 } 2025 2026 static int mv88e6xxx_setup(struct dsa_switch *ds) 2027 { 2028 struct mv88e6xxx_chip *chip = ds->priv; 2029 int err; 2030 int i; 2031 2032 chip->ds = ds; 2033 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2034 2035 mutex_lock(&chip->reg_lock); 2036 2037 /* Setup Switch Port Registers */ 2038 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2039 if (dsa_is_unused_port(ds, i)) 2040 continue; 2041 2042 err = mv88e6xxx_setup_port(chip, i); 2043 if (err) 2044 goto unlock; 2045 } 2046 2047 /* Setup Switch Global 1 Registers */ 2048 err = mv88e6xxx_g1_setup(chip); 2049 if (err) 2050 goto unlock; 2051 2052 /* Setup Switch Global 2 Registers */ 2053 if (chip->info->global2_addr) { 2054 err = mv88e6xxx_g2_setup(chip); 2055 if (err) 2056 goto unlock; 2057 } 2058 2059 err = mv88e6xxx_irl_setup(chip); 2060 if (err) 2061 goto unlock; 2062 2063 err = mv88e6xxx_mac_setup(chip); 2064 if (err) 2065 goto unlock; 2066 2067 err = mv88e6xxx_phy_setup(chip); 2068 if (err) 2069 goto unlock; 2070 2071 err = mv88e6xxx_vtu_setup(chip); 2072 if (err) 2073 goto unlock; 2074 2075 err = mv88e6xxx_pvt_setup(chip); 2076 if (err) 2077 goto unlock; 2078 2079 err = mv88e6xxx_atu_setup(chip); 2080 if (err) 2081 goto unlock; 2082 2083 err = mv88e6xxx_broadcast_setup(chip, 0); 2084 if (err) 2085 goto unlock; 2086 2087 err = mv88e6xxx_pot_setup(chip); 2088 if (err) 2089 goto unlock; 2090 2091 err = mv88e6xxx_rsvd2cpu_setup(chip); 2092 if (err) 2093 goto unlock; 2094 2095 unlock: 2096 mutex_unlock(&chip->reg_lock); 2097 2098 return err; 2099 } 2100 2101 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2102 { 2103 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2104 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2105 u16 val; 2106 int err; 2107 2108 if (!chip->info->ops->phy_read) 2109 return -EOPNOTSUPP; 2110 2111 mutex_lock(&chip->reg_lock); 2112 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2113 mutex_unlock(&chip->reg_lock); 2114 2115 if (reg == MII_PHYSID2) { 2116 /* Some internal PHYS don't have a model number. Use 2117 * the mv88e6390 family model number instead. 2118 */ 2119 if (!(val & 0x3f0)) 2120 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2121 } 2122 2123 return err ? err : val; 2124 } 2125 2126 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2127 { 2128 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2129 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2130 int err; 2131 2132 if (!chip->info->ops->phy_write) 2133 return -EOPNOTSUPP; 2134 2135 mutex_lock(&chip->reg_lock); 2136 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2137 mutex_unlock(&chip->reg_lock); 2138 2139 return err; 2140 } 2141 2142 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2143 struct device_node *np, 2144 bool external) 2145 { 2146 static int index; 2147 struct mv88e6xxx_mdio_bus *mdio_bus; 2148 struct mii_bus *bus; 2149 int err; 2150 2151 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2152 if (!bus) 2153 return -ENOMEM; 2154 2155 mdio_bus = bus->priv; 2156 mdio_bus->bus = bus; 2157 mdio_bus->chip = chip; 2158 INIT_LIST_HEAD(&mdio_bus->list); 2159 mdio_bus->external = external; 2160 2161 if (np) { 2162 bus->name = np->full_name; 2163 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2164 } else { 2165 bus->name = "mv88e6xxx SMI"; 2166 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2167 } 2168 2169 bus->read = mv88e6xxx_mdio_read; 2170 bus->write = mv88e6xxx_mdio_write; 2171 bus->parent = chip->dev; 2172 2173 if (np) 2174 err = of_mdiobus_register(bus, np); 2175 else 2176 err = mdiobus_register(bus); 2177 if (err) { 2178 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2179 return err; 2180 } 2181 2182 if (external) 2183 list_add_tail(&mdio_bus->list, &chip->mdios); 2184 else 2185 list_add(&mdio_bus->list, &chip->mdios); 2186 2187 return 0; 2188 } 2189 2190 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2191 { .compatible = "marvell,mv88e6xxx-mdio-external", 2192 .data = (void *)true }, 2193 { }, 2194 }; 2195 2196 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2197 2198 { 2199 struct mv88e6xxx_mdio_bus *mdio_bus; 2200 struct mii_bus *bus; 2201 2202 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2203 bus = mdio_bus->bus; 2204 2205 mdiobus_unregister(bus); 2206 } 2207 } 2208 2209 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2210 struct device_node *np) 2211 { 2212 const struct of_device_id *match; 2213 struct device_node *child; 2214 int err; 2215 2216 /* Always register one mdio bus for the internal/default mdio 2217 * bus. This maybe represented in the device tree, but is 2218 * optional. 2219 */ 2220 child = of_get_child_by_name(np, "mdio"); 2221 err = mv88e6xxx_mdio_register(chip, child, false); 2222 if (err) 2223 return err; 2224 2225 /* Walk the device tree, and see if there are any other nodes 2226 * which say they are compatible with the external mdio 2227 * bus. 2228 */ 2229 for_each_available_child_of_node(np, child) { 2230 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2231 if (match) { 2232 err = mv88e6xxx_mdio_register(chip, child, true); 2233 if (err) { 2234 mv88e6xxx_mdios_unregister(chip); 2235 return err; 2236 } 2237 } 2238 } 2239 2240 return 0; 2241 } 2242 2243 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2244 { 2245 struct mv88e6xxx_chip *chip = ds->priv; 2246 2247 return chip->eeprom_len; 2248 } 2249 2250 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2251 struct ethtool_eeprom *eeprom, u8 *data) 2252 { 2253 struct mv88e6xxx_chip *chip = ds->priv; 2254 int err; 2255 2256 if (!chip->info->ops->get_eeprom) 2257 return -EOPNOTSUPP; 2258 2259 mutex_lock(&chip->reg_lock); 2260 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2261 mutex_unlock(&chip->reg_lock); 2262 2263 if (err) 2264 return err; 2265 2266 eeprom->magic = 0xc3ec4951; 2267 2268 return 0; 2269 } 2270 2271 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2272 struct ethtool_eeprom *eeprom, u8 *data) 2273 { 2274 struct mv88e6xxx_chip *chip = ds->priv; 2275 int err; 2276 2277 if (!chip->info->ops->set_eeprom) 2278 return -EOPNOTSUPP; 2279 2280 if (eeprom->magic != 0xc3ec4951) 2281 return -EINVAL; 2282 2283 mutex_lock(&chip->reg_lock); 2284 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2285 mutex_unlock(&chip->reg_lock); 2286 2287 return err; 2288 } 2289 2290 static const struct mv88e6xxx_ops mv88e6085_ops = { 2291 /* MV88E6XXX_FAMILY_6097 */ 2292 .irl_init_all = mv88e6352_g2_irl_init_all, 2293 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2294 .phy_read = mv88e6185_phy_ppu_read, 2295 .phy_write = mv88e6185_phy_ppu_write, 2296 .port_set_link = mv88e6xxx_port_set_link, 2297 .port_set_duplex = mv88e6xxx_port_set_duplex, 2298 .port_set_speed = mv88e6185_port_set_speed, 2299 .port_tag_remap = mv88e6095_port_tag_remap, 2300 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2301 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2302 .port_set_ether_type = mv88e6351_port_set_ether_type, 2303 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2304 .port_pause_limit = mv88e6097_port_pause_limit, 2305 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2306 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2307 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2308 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2309 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2310 .stats_get_strings = mv88e6095_stats_get_strings, 2311 .stats_get_stats = mv88e6095_stats_get_stats, 2312 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2313 .set_egress_port = mv88e6095_g1_set_egress_port, 2314 .watchdog_ops = &mv88e6097_watchdog_ops, 2315 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2316 .pot_clear = mv88e6xxx_g2_pot_clear, 2317 .ppu_enable = mv88e6185_g1_ppu_enable, 2318 .ppu_disable = mv88e6185_g1_ppu_disable, 2319 .reset = mv88e6185_g1_reset, 2320 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2321 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2322 }; 2323 2324 static const struct mv88e6xxx_ops mv88e6095_ops = { 2325 /* MV88E6XXX_FAMILY_6095 */ 2326 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2327 .phy_read = mv88e6185_phy_ppu_read, 2328 .phy_write = mv88e6185_phy_ppu_write, 2329 .port_set_link = mv88e6xxx_port_set_link, 2330 .port_set_duplex = mv88e6xxx_port_set_duplex, 2331 .port_set_speed = mv88e6185_port_set_speed, 2332 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2333 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2334 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2335 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2336 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2337 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2338 .stats_get_strings = mv88e6095_stats_get_strings, 2339 .stats_get_stats = mv88e6095_stats_get_stats, 2340 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2341 .ppu_enable = mv88e6185_g1_ppu_enable, 2342 .ppu_disable = mv88e6185_g1_ppu_disable, 2343 .reset = mv88e6185_g1_reset, 2344 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2345 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2346 }; 2347 2348 static const struct mv88e6xxx_ops mv88e6097_ops = { 2349 /* MV88E6XXX_FAMILY_6097 */ 2350 .irl_init_all = mv88e6352_g2_irl_init_all, 2351 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2352 .phy_read = mv88e6xxx_g2_smi_phy_read, 2353 .phy_write = mv88e6xxx_g2_smi_phy_write, 2354 .port_set_link = mv88e6xxx_port_set_link, 2355 .port_set_duplex = mv88e6xxx_port_set_duplex, 2356 .port_set_speed = mv88e6185_port_set_speed, 2357 .port_tag_remap = mv88e6095_port_tag_remap, 2358 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2359 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2360 .port_set_ether_type = mv88e6351_port_set_ether_type, 2361 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2362 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2363 .port_pause_limit = mv88e6097_port_pause_limit, 2364 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2365 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2366 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2367 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2368 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2369 .stats_get_strings = mv88e6095_stats_get_strings, 2370 .stats_get_stats = mv88e6095_stats_get_stats, 2371 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2372 .set_egress_port = mv88e6095_g1_set_egress_port, 2373 .watchdog_ops = &mv88e6097_watchdog_ops, 2374 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2375 .pot_clear = mv88e6xxx_g2_pot_clear, 2376 .reset = mv88e6352_g1_reset, 2377 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2378 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2379 }; 2380 2381 static const struct mv88e6xxx_ops mv88e6123_ops = { 2382 /* MV88E6XXX_FAMILY_6165 */ 2383 .irl_init_all = mv88e6352_g2_irl_init_all, 2384 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2385 .phy_read = mv88e6xxx_g2_smi_phy_read, 2386 .phy_write = mv88e6xxx_g2_smi_phy_write, 2387 .port_set_link = mv88e6xxx_port_set_link, 2388 .port_set_duplex = mv88e6xxx_port_set_duplex, 2389 .port_set_speed = mv88e6185_port_set_speed, 2390 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2391 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2392 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2393 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2394 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2395 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2396 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2397 .stats_get_strings = mv88e6095_stats_get_strings, 2398 .stats_get_stats = mv88e6095_stats_get_stats, 2399 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2400 .set_egress_port = mv88e6095_g1_set_egress_port, 2401 .watchdog_ops = &mv88e6097_watchdog_ops, 2402 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2403 .pot_clear = mv88e6xxx_g2_pot_clear, 2404 .reset = mv88e6352_g1_reset, 2405 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2406 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2407 }; 2408 2409 static const struct mv88e6xxx_ops mv88e6131_ops = { 2410 /* MV88E6XXX_FAMILY_6185 */ 2411 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2412 .phy_read = mv88e6185_phy_ppu_read, 2413 .phy_write = mv88e6185_phy_ppu_write, 2414 .port_set_link = mv88e6xxx_port_set_link, 2415 .port_set_duplex = mv88e6xxx_port_set_duplex, 2416 .port_set_speed = mv88e6185_port_set_speed, 2417 .port_tag_remap = mv88e6095_port_tag_remap, 2418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2419 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2420 .port_set_ether_type = mv88e6351_port_set_ether_type, 2421 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2422 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2423 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2424 .port_pause_limit = mv88e6097_port_pause_limit, 2425 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2426 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2427 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2428 .stats_get_strings = mv88e6095_stats_get_strings, 2429 .stats_get_stats = mv88e6095_stats_get_stats, 2430 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2431 .set_egress_port = mv88e6095_g1_set_egress_port, 2432 .watchdog_ops = &mv88e6097_watchdog_ops, 2433 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2434 .ppu_enable = mv88e6185_g1_ppu_enable, 2435 .ppu_disable = mv88e6185_g1_ppu_disable, 2436 .reset = mv88e6185_g1_reset, 2437 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2438 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2439 }; 2440 2441 static const struct mv88e6xxx_ops mv88e6141_ops = { 2442 /* MV88E6XXX_FAMILY_6341 */ 2443 .irl_init_all = mv88e6352_g2_irl_init_all, 2444 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2445 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2446 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2447 .phy_read = mv88e6xxx_g2_smi_phy_read, 2448 .phy_write = mv88e6xxx_g2_smi_phy_write, 2449 .port_set_link = mv88e6xxx_port_set_link, 2450 .port_set_duplex = mv88e6xxx_port_set_duplex, 2451 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2452 .port_set_speed = mv88e6390_port_set_speed, 2453 .port_tag_remap = mv88e6095_port_tag_remap, 2454 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2455 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2456 .port_set_ether_type = mv88e6351_port_set_ether_type, 2457 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2458 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2459 .port_pause_limit = mv88e6097_port_pause_limit, 2460 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2461 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2462 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2463 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2464 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2465 .stats_get_strings = mv88e6320_stats_get_strings, 2466 .stats_get_stats = mv88e6390_stats_get_stats, 2467 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2468 .set_egress_port = mv88e6390_g1_set_egress_port, 2469 .watchdog_ops = &mv88e6390_watchdog_ops, 2470 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2471 .pot_clear = mv88e6xxx_g2_pot_clear, 2472 .reset = mv88e6352_g1_reset, 2473 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2474 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2475 }; 2476 2477 static const struct mv88e6xxx_ops mv88e6161_ops = { 2478 /* MV88E6XXX_FAMILY_6165 */ 2479 .irl_init_all = mv88e6352_g2_irl_init_all, 2480 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2481 .phy_read = mv88e6xxx_g2_smi_phy_read, 2482 .phy_write = mv88e6xxx_g2_smi_phy_write, 2483 .port_set_link = mv88e6xxx_port_set_link, 2484 .port_set_duplex = mv88e6xxx_port_set_duplex, 2485 .port_set_speed = mv88e6185_port_set_speed, 2486 .port_tag_remap = mv88e6095_port_tag_remap, 2487 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2488 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2489 .port_set_ether_type = mv88e6351_port_set_ether_type, 2490 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2492 .port_pause_limit = mv88e6097_port_pause_limit, 2493 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2494 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2495 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2496 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2497 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2498 .stats_get_strings = mv88e6095_stats_get_strings, 2499 .stats_get_stats = mv88e6095_stats_get_stats, 2500 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2501 .set_egress_port = mv88e6095_g1_set_egress_port, 2502 .watchdog_ops = &mv88e6097_watchdog_ops, 2503 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2504 .pot_clear = mv88e6xxx_g2_pot_clear, 2505 .reset = mv88e6352_g1_reset, 2506 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2507 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2508 }; 2509 2510 static const struct mv88e6xxx_ops mv88e6165_ops = { 2511 /* MV88E6XXX_FAMILY_6165 */ 2512 .irl_init_all = mv88e6352_g2_irl_init_all, 2513 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2514 .phy_read = mv88e6165_phy_read, 2515 .phy_write = mv88e6165_phy_write, 2516 .port_set_link = mv88e6xxx_port_set_link, 2517 .port_set_duplex = mv88e6xxx_port_set_duplex, 2518 .port_set_speed = mv88e6185_port_set_speed, 2519 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2520 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2521 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2522 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2523 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2524 .stats_get_strings = mv88e6095_stats_get_strings, 2525 .stats_get_stats = mv88e6095_stats_get_stats, 2526 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2527 .set_egress_port = mv88e6095_g1_set_egress_port, 2528 .watchdog_ops = &mv88e6097_watchdog_ops, 2529 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2530 .pot_clear = mv88e6xxx_g2_pot_clear, 2531 .reset = mv88e6352_g1_reset, 2532 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2533 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2534 }; 2535 2536 static const struct mv88e6xxx_ops mv88e6171_ops = { 2537 /* MV88E6XXX_FAMILY_6351 */ 2538 .irl_init_all = mv88e6352_g2_irl_init_all, 2539 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2540 .phy_read = mv88e6xxx_g2_smi_phy_read, 2541 .phy_write = mv88e6xxx_g2_smi_phy_write, 2542 .port_set_link = mv88e6xxx_port_set_link, 2543 .port_set_duplex = mv88e6xxx_port_set_duplex, 2544 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2545 .port_set_speed = mv88e6185_port_set_speed, 2546 .port_tag_remap = mv88e6095_port_tag_remap, 2547 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2548 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2549 .port_set_ether_type = mv88e6351_port_set_ether_type, 2550 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2551 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2552 .port_pause_limit = mv88e6097_port_pause_limit, 2553 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2554 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2555 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2556 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2557 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2558 .stats_get_strings = mv88e6095_stats_get_strings, 2559 .stats_get_stats = mv88e6095_stats_get_stats, 2560 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2561 .set_egress_port = mv88e6095_g1_set_egress_port, 2562 .watchdog_ops = &mv88e6097_watchdog_ops, 2563 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2564 .pot_clear = mv88e6xxx_g2_pot_clear, 2565 .reset = mv88e6352_g1_reset, 2566 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2567 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2568 }; 2569 2570 static const struct mv88e6xxx_ops mv88e6172_ops = { 2571 /* MV88E6XXX_FAMILY_6352 */ 2572 .irl_init_all = mv88e6352_g2_irl_init_all, 2573 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2574 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2576 .phy_read = mv88e6xxx_g2_smi_phy_read, 2577 .phy_write = mv88e6xxx_g2_smi_phy_write, 2578 .port_set_link = mv88e6xxx_port_set_link, 2579 .port_set_duplex = mv88e6xxx_port_set_duplex, 2580 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2581 .port_set_speed = mv88e6352_port_set_speed, 2582 .port_tag_remap = mv88e6095_port_tag_remap, 2583 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2584 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2585 .port_set_ether_type = mv88e6351_port_set_ether_type, 2586 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2587 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2588 .port_pause_limit = mv88e6097_port_pause_limit, 2589 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2590 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2591 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2592 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2593 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2594 .stats_get_strings = mv88e6095_stats_get_strings, 2595 .stats_get_stats = mv88e6095_stats_get_stats, 2596 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2597 .set_egress_port = mv88e6095_g1_set_egress_port, 2598 .watchdog_ops = &mv88e6097_watchdog_ops, 2599 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2600 .pot_clear = mv88e6xxx_g2_pot_clear, 2601 .reset = mv88e6352_g1_reset, 2602 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2603 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2604 .serdes_power = mv88e6352_serdes_power, 2605 }; 2606 2607 static const struct mv88e6xxx_ops mv88e6175_ops = { 2608 /* MV88E6XXX_FAMILY_6351 */ 2609 .irl_init_all = mv88e6352_g2_irl_init_all, 2610 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2611 .phy_read = mv88e6xxx_g2_smi_phy_read, 2612 .phy_write = mv88e6xxx_g2_smi_phy_write, 2613 .port_set_link = mv88e6xxx_port_set_link, 2614 .port_set_duplex = mv88e6xxx_port_set_duplex, 2615 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2616 .port_set_speed = mv88e6185_port_set_speed, 2617 .port_tag_remap = mv88e6095_port_tag_remap, 2618 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2619 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2620 .port_set_ether_type = mv88e6351_port_set_ether_type, 2621 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2622 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2623 .port_pause_limit = mv88e6097_port_pause_limit, 2624 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2625 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2626 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2627 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2628 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2629 .stats_get_strings = mv88e6095_stats_get_strings, 2630 .stats_get_stats = mv88e6095_stats_get_stats, 2631 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2632 .set_egress_port = mv88e6095_g1_set_egress_port, 2633 .watchdog_ops = &mv88e6097_watchdog_ops, 2634 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2635 .pot_clear = mv88e6xxx_g2_pot_clear, 2636 .reset = mv88e6352_g1_reset, 2637 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2638 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2639 }; 2640 2641 static const struct mv88e6xxx_ops mv88e6176_ops = { 2642 /* MV88E6XXX_FAMILY_6352 */ 2643 .irl_init_all = mv88e6352_g2_irl_init_all, 2644 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2645 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2646 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2647 .phy_read = mv88e6xxx_g2_smi_phy_read, 2648 .phy_write = mv88e6xxx_g2_smi_phy_write, 2649 .port_set_link = mv88e6xxx_port_set_link, 2650 .port_set_duplex = mv88e6xxx_port_set_duplex, 2651 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2652 .port_set_speed = mv88e6352_port_set_speed, 2653 .port_tag_remap = mv88e6095_port_tag_remap, 2654 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2655 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2656 .port_set_ether_type = mv88e6351_port_set_ether_type, 2657 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2658 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2659 .port_pause_limit = mv88e6097_port_pause_limit, 2660 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2661 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2662 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2663 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2664 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2665 .stats_get_strings = mv88e6095_stats_get_strings, 2666 .stats_get_stats = mv88e6095_stats_get_stats, 2667 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2668 .set_egress_port = mv88e6095_g1_set_egress_port, 2669 .watchdog_ops = &mv88e6097_watchdog_ops, 2670 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2671 .pot_clear = mv88e6xxx_g2_pot_clear, 2672 .reset = mv88e6352_g1_reset, 2673 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2674 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2675 .serdes_power = mv88e6352_serdes_power, 2676 }; 2677 2678 static const struct mv88e6xxx_ops mv88e6185_ops = { 2679 /* MV88E6XXX_FAMILY_6185 */ 2680 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2681 .phy_read = mv88e6185_phy_ppu_read, 2682 .phy_write = mv88e6185_phy_ppu_write, 2683 .port_set_link = mv88e6xxx_port_set_link, 2684 .port_set_duplex = mv88e6xxx_port_set_duplex, 2685 .port_set_speed = mv88e6185_port_set_speed, 2686 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2687 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2688 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2689 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2690 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2691 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2692 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2693 .stats_get_strings = mv88e6095_stats_get_strings, 2694 .stats_get_stats = mv88e6095_stats_get_stats, 2695 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2696 .set_egress_port = mv88e6095_g1_set_egress_port, 2697 .watchdog_ops = &mv88e6097_watchdog_ops, 2698 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2699 .ppu_enable = mv88e6185_g1_ppu_enable, 2700 .ppu_disable = mv88e6185_g1_ppu_disable, 2701 .reset = mv88e6185_g1_reset, 2702 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2703 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2704 }; 2705 2706 static const struct mv88e6xxx_ops mv88e6190_ops = { 2707 /* MV88E6XXX_FAMILY_6390 */ 2708 .irl_init_all = mv88e6390_g2_irl_init_all, 2709 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2710 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2712 .phy_read = mv88e6xxx_g2_smi_phy_read, 2713 .phy_write = mv88e6xxx_g2_smi_phy_write, 2714 .port_set_link = mv88e6xxx_port_set_link, 2715 .port_set_duplex = mv88e6xxx_port_set_duplex, 2716 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2717 .port_set_speed = mv88e6390_port_set_speed, 2718 .port_tag_remap = mv88e6390_port_tag_remap, 2719 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2720 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2721 .port_set_ether_type = mv88e6351_port_set_ether_type, 2722 .port_pause_limit = mv88e6390_port_pause_limit, 2723 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2724 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2725 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2726 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2727 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2728 .stats_get_strings = mv88e6320_stats_get_strings, 2729 .stats_get_stats = mv88e6390_stats_get_stats, 2730 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2731 .set_egress_port = mv88e6390_g1_set_egress_port, 2732 .watchdog_ops = &mv88e6390_watchdog_ops, 2733 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2734 .pot_clear = mv88e6xxx_g2_pot_clear, 2735 .reset = mv88e6352_g1_reset, 2736 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2737 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2738 .serdes_power = mv88e6390_serdes_power, 2739 }; 2740 2741 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2742 /* MV88E6XXX_FAMILY_6390 */ 2743 .irl_init_all = mv88e6390_g2_irl_init_all, 2744 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2745 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2746 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2747 .phy_read = mv88e6xxx_g2_smi_phy_read, 2748 .phy_write = mv88e6xxx_g2_smi_phy_write, 2749 .port_set_link = mv88e6xxx_port_set_link, 2750 .port_set_duplex = mv88e6xxx_port_set_duplex, 2751 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2752 .port_set_speed = mv88e6390x_port_set_speed, 2753 .port_tag_remap = mv88e6390_port_tag_remap, 2754 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2755 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2756 .port_set_ether_type = mv88e6351_port_set_ether_type, 2757 .port_pause_limit = mv88e6390_port_pause_limit, 2758 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2759 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2760 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2761 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2762 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2763 .stats_get_strings = mv88e6320_stats_get_strings, 2764 .stats_get_stats = mv88e6390_stats_get_stats, 2765 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2766 .set_egress_port = mv88e6390_g1_set_egress_port, 2767 .watchdog_ops = &mv88e6390_watchdog_ops, 2768 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2769 .pot_clear = mv88e6xxx_g2_pot_clear, 2770 .reset = mv88e6352_g1_reset, 2771 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2772 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2773 .serdes_power = mv88e6390_serdes_power, 2774 }; 2775 2776 static const struct mv88e6xxx_ops mv88e6191_ops = { 2777 /* MV88E6XXX_FAMILY_6390 */ 2778 .irl_init_all = mv88e6390_g2_irl_init_all, 2779 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2780 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2781 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2782 .phy_read = mv88e6xxx_g2_smi_phy_read, 2783 .phy_write = mv88e6xxx_g2_smi_phy_write, 2784 .port_set_link = mv88e6xxx_port_set_link, 2785 .port_set_duplex = mv88e6xxx_port_set_duplex, 2786 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2787 .port_set_speed = mv88e6390_port_set_speed, 2788 .port_tag_remap = mv88e6390_port_tag_remap, 2789 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2790 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2791 .port_set_ether_type = mv88e6351_port_set_ether_type, 2792 .port_pause_limit = mv88e6390_port_pause_limit, 2793 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2794 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2795 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2796 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2797 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2798 .stats_get_strings = mv88e6320_stats_get_strings, 2799 .stats_get_stats = mv88e6390_stats_get_stats, 2800 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2801 .set_egress_port = mv88e6390_g1_set_egress_port, 2802 .watchdog_ops = &mv88e6390_watchdog_ops, 2803 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2804 .pot_clear = mv88e6xxx_g2_pot_clear, 2805 .reset = mv88e6352_g1_reset, 2806 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2807 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2808 .serdes_power = mv88e6390_serdes_power, 2809 }; 2810 2811 static const struct mv88e6xxx_ops mv88e6240_ops = { 2812 /* MV88E6XXX_FAMILY_6352 */ 2813 .irl_init_all = mv88e6352_g2_irl_init_all, 2814 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2815 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2816 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2817 .phy_read = mv88e6xxx_g2_smi_phy_read, 2818 .phy_write = mv88e6xxx_g2_smi_phy_write, 2819 .port_set_link = mv88e6xxx_port_set_link, 2820 .port_set_duplex = mv88e6xxx_port_set_duplex, 2821 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2822 .port_set_speed = mv88e6352_port_set_speed, 2823 .port_tag_remap = mv88e6095_port_tag_remap, 2824 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2825 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2826 .port_set_ether_type = mv88e6351_port_set_ether_type, 2827 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2828 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2829 .port_pause_limit = mv88e6097_port_pause_limit, 2830 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2831 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2832 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2833 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2834 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2835 .stats_get_strings = mv88e6095_stats_get_strings, 2836 .stats_get_stats = mv88e6095_stats_get_stats, 2837 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2838 .set_egress_port = mv88e6095_g1_set_egress_port, 2839 .watchdog_ops = &mv88e6097_watchdog_ops, 2840 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2841 .pot_clear = mv88e6xxx_g2_pot_clear, 2842 .reset = mv88e6352_g1_reset, 2843 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2844 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2845 .serdes_power = mv88e6352_serdes_power, 2846 }; 2847 2848 static const struct mv88e6xxx_ops mv88e6290_ops = { 2849 /* MV88E6XXX_FAMILY_6390 */ 2850 .irl_init_all = mv88e6390_g2_irl_init_all, 2851 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2852 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2853 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2854 .phy_read = mv88e6xxx_g2_smi_phy_read, 2855 .phy_write = mv88e6xxx_g2_smi_phy_write, 2856 .port_set_link = mv88e6xxx_port_set_link, 2857 .port_set_duplex = mv88e6xxx_port_set_duplex, 2858 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2859 .port_set_speed = mv88e6390_port_set_speed, 2860 .port_tag_remap = mv88e6390_port_tag_remap, 2861 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2862 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2863 .port_set_ether_type = mv88e6351_port_set_ether_type, 2864 .port_pause_limit = mv88e6390_port_pause_limit, 2865 .port_set_cmode = mv88e6390x_port_set_cmode, 2866 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2867 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2868 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2869 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2870 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2871 .stats_get_strings = mv88e6320_stats_get_strings, 2872 .stats_get_stats = mv88e6390_stats_get_stats, 2873 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2874 .set_egress_port = mv88e6390_g1_set_egress_port, 2875 .watchdog_ops = &mv88e6390_watchdog_ops, 2876 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2877 .pot_clear = mv88e6xxx_g2_pot_clear, 2878 .reset = mv88e6352_g1_reset, 2879 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2880 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2881 .serdes_power = mv88e6390_serdes_power, 2882 }; 2883 2884 static const struct mv88e6xxx_ops mv88e6320_ops = { 2885 /* MV88E6XXX_FAMILY_6320 */ 2886 .irl_init_all = mv88e6352_g2_irl_init_all, 2887 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2888 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2889 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2890 .phy_read = mv88e6xxx_g2_smi_phy_read, 2891 .phy_write = mv88e6xxx_g2_smi_phy_write, 2892 .port_set_link = mv88e6xxx_port_set_link, 2893 .port_set_duplex = mv88e6xxx_port_set_duplex, 2894 .port_set_speed = mv88e6185_port_set_speed, 2895 .port_tag_remap = mv88e6095_port_tag_remap, 2896 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2897 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2898 .port_set_ether_type = mv88e6351_port_set_ether_type, 2899 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2900 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2901 .port_pause_limit = mv88e6097_port_pause_limit, 2902 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2903 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2904 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2905 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2906 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2907 .stats_get_strings = mv88e6320_stats_get_strings, 2908 .stats_get_stats = mv88e6320_stats_get_stats, 2909 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2910 .set_egress_port = mv88e6095_g1_set_egress_port, 2911 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2912 .pot_clear = mv88e6xxx_g2_pot_clear, 2913 .reset = mv88e6352_g1_reset, 2914 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2915 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2916 }; 2917 2918 static const struct mv88e6xxx_ops mv88e6321_ops = { 2919 /* MV88E6XXX_FAMILY_6320 */ 2920 .irl_init_all = mv88e6352_g2_irl_init_all, 2921 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2922 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2923 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2924 .phy_read = mv88e6xxx_g2_smi_phy_read, 2925 .phy_write = mv88e6xxx_g2_smi_phy_write, 2926 .port_set_link = mv88e6xxx_port_set_link, 2927 .port_set_duplex = mv88e6xxx_port_set_duplex, 2928 .port_set_speed = mv88e6185_port_set_speed, 2929 .port_tag_remap = mv88e6095_port_tag_remap, 2930 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2931 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2932 .port_set_ether_type = mv88e6351_port_set_ether_type, 2933 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2934 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2935 .port_pause_limit = mv88e6097_port_pause_limit, 2936 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2937 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2938 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2939 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2940 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2941 .stats_get_strings = mv88e6320_stats_get_strings, 2942 .stats_get_stats = mv88e6320_stats_get_stats, 2943 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2944 .set_egress_port = mv88e6095_g1_set_egress_port, 2945 .reset = mv88e6352_g1_reset, 2946 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2947 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2948 }; 2949 2950 static const struct mv88e6xxx_ops mv88e6341_ops = { 2951 /* MV88E6XXX_FAMILY_6341 */ 2952 .irl_init_all = mv88e6352_g2_irl_init_all, 2953 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2954 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2955 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2956 .phy_read = mv88e6xxx_g2_smi_phy_read, 2957 .phy_write = mv88e6xxx_g2_smi_phy_write, 2958 .port_set_link = mv88e6xxx_port_set_link, 2959 .port_set_duplex = mv88e6xxx_port_set_duplex, 2960 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2961 .port_set_speed = mv88e6390_port_set_speed, 2962 .port_tag_remap = mv88e6095_port_tag_remap, 2963 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2964 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2965 .port_set_ether_type = mv88e6351_port_set_ether_type, 2966 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2967 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2968 .port_pause_limit = mv88e6097_port_pause_limit, 2969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2971 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2972 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2973 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2974 .stats_get_strings = mv88e6320_stats_get_strings, 2975 .stats_get_stats = mv88e6390_stats_get_stats, 2976 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2977 .set_egress_port = mv88e6390_g1_set_egress_port, 2978 .watchdog_ops = &mv88e6390_watchdog_ops, 2979 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2980 .pot_clear = mv88e6xxx_g2_pot_clear, 2981 .reset = mv88e6352_g1_reset, 2982 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2983 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2984 }; 2985 2986 static const struct mv88e6xxx_ops mv88e6350_ops = { 2987 /* MV88E6XXX_FAMILY_6351 */ 2988 .irl_init_all = mv88e6352_g2_irl_init_all, 2989 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2990 .phy_read = mv88e6xxx_g2_smi_phy_read, 2991 .phy_write = mv88e6xxx_g2_smi_phy_write, 2992 .port_set_link = mv88e6xxx_port_set_link, 2993 .port_set_duplex = mv88e6xxx_port_set_duplex, 2994 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2995 .port_set_speed = mv88e6185_port_set_speed, 2996 .port_tag_remap = mv88e6095_port_tag_remap, 2997 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2998 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2999 .port_set_ether_type = mv88e6351_port_set_ether_type, 3000 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3001 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3002 .port_pause_limit = mv88e6097_port_pause_limit, 3003 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3004 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3005 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3006 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3007 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3008 .stats_get_strings = mv88e6095_stats_get_strings, 3009 .stats_get_stats = mv88e6095_stats_get_stats, 3010 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3011 .set_egress_port = mv88e6095_g1_set_egress_port, 3012 .watchdog_ops = &mv88e6097_watchdog_ops, 3013 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3014 .pot_clear = mv88e6xxx_g2_pot_clear, 3015 .reset = mv88e6352_g1_reset, 3016 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3017 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3018 }; 3019 3020 static const struct mv88e6xxx_ops mv88e6351_ops = { 3021 /* MV88E6XXX_FAMILY_6351 */ 3022 .irl_init_all = mv88e6352_g2_irl_init_all, 3023 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3024 .phy_read = mv88e6xxx_g2_smi_phy_read, 3025 .phy_write = mv88e6xxx_g2_smi_phy_write, 3026 .port_set_link = mv88e6xxx_port_set_link, 3027 .port_set_duplex = mv88e6xxx_port_set_duplex, 3028 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3029 .port_set_speed = mv88e6185_port_set_speed, 3030 .port_tag_remap = mv88e6095_port_tag_remap, 3031 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3032 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3033 .port_set_ether_type = mv88e6351_port_set_ether_type, 3034 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3035 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3036 .port_pause_limit = mv88e6097_port_pause_limit, 3037 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3038 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3039 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3040 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3041 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3042 .stats_get_strings = mv88e6095_stats_get_strings, 3043 .stats_get_stats = mv88e6095_stats_get_stats, 3044 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3045 .set_egress_port = mv88e6095_g1_set_egress_port, 3046 .watchdog_ops = &mv88e6097_watchdog_ops, 3047 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3048 .pot_clear = mv88e6xxx_g2_pot_clear, 3049 .reset = mv88e6352_g1_reset, 3050 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3051 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3052 }; 3053 3054 static const struct mv88e6xxx_ops mv88e6352_ops = { 3055 /* MV88E6XXX_FAMILY_6352 */ 3056 .irl_init_all = mv88e6352_g2_irl_init_all, 3057 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3058 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3059 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3060 .phy_read = mv88e6xxx_g2_smi_phy_read, 3061 .phy_write = mv88e6xxx_g2_smi_phy_write, 3062 .port_set_link = mv88e6xxx_port_set_link, 3063 .port_set_duplex = mv88e6xxx_port_set_duplex, 3064 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3065 .port_set_speed = mv88e6352_port_set_speed, 3066 .port_tag_remap = mv88e6095_port_tag_remap, 3067 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3068 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3069 .port_set_ether_type = mv88e6351_port_set_ether_type, 3070 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3071 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3072 .port_pause_limit = mv88e6097_port_pause_limit, 3073 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3074 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3075 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3076 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3077 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3078 .stats_get_strings = mv88e6095_stats_get_strings, 3079 .stats_get_stats = mv88e6095_stats_get_stats, 3080 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3081 .set_egress_port = mv88e6095_g1_set_egress_port, 3082 .watchdog_ops = &mv88e6097_watchdog_ops, 3083 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3084 .pot_clear = mv88e6xxx_g2_pot_clear, 3085 .reset = mv88e6352_g1_reset, 3086 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3087 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3088 .serdes_power = mv88e6352_serdes_power, 3089 }; 3090 3091 static const struct mv88e6xxx_ops mv88e6390_ops = { 3092 /* MV88E6XXX_FAMILY_6390 */ 3093 .irl_init_all = mv88e6390_g2_irl_init_all, 3094 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3095 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3096 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3097 .phy_read = mv88e6xxx_g2_smi_phy_read, 3098 .phy_write = mv88e6xxx_g2_smi_phy_write, 3099 .port_set_link = mv88e6xxx_port_set_link, 3100 .port_set_duplex = mv88e6xxx_port_set_duplex, 3101 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3102 .port_set_speed = mv88e6390_port_set_speed, 3103 .port_tag_remap = mv88e6390_port_tag_remap, 3104 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3105 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3106 .port_set_ether_type = mv88e6351_port_set_ether_type, 3107 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3108 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3109 .port_pause_limit = mv88e6390_port_pause_limit, 3110 .port_set_cmode = mv88e6390x_port_set_cmode, 3111 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3112 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3113 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3114 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3115 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3116 .stats_get_strings = mv88e6320_stats_get_strings, 3117 .stats_get_stats = mv88e6390_stats_get_stats, 3118 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3119 .set_egress_port = mv88e6390_g1_set_egress_port, 3120 .watchdog_ops = &mv88e6390_watchdog_ops, 3121 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3122 .pot_clear = mv88e6xxx_g2_pot_clear, 3123 .reset = mv88e6352_g1_reset, 3124 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3125 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3126 .serdes_power = mv88e6390_serdes_power, 3127 }; 3128 3129 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3130 /* MV88E6XXX_FAMILY_6390 */ 3131 .irl_init_all = mv88e6390_g2_irl_init_all, 3132 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3133 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3134 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3135 .phy_read = mv88e6xxx_g2_smi_phy_read, 3136 .phy_write = mv88e6xxx_g2_smi_phy_write, 3137 .port_set_link = mv88e6xxx_port_set_link, 3138 .port_set_duplex = mv88e6xxx_port_set_duplex, 3139 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3140 .port_set_speed = mv88e6390x_port_set_speed, 3141 .port_tag_remap = mv88e6390_port_tag_remap, 3142 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3143 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3144 .port_set_ether_type = mv88e6351_port_set_ether_type, 3145 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3146 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3147 .port_pause_limit = mv88e6390_port_pause_limit, 3148 .port_set_cmode = mv88e6390x_port_set_cmode, 3149 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3150 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3151 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3152 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3153 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3154 .stats_get_strings = mv88e6320_stats_get_strings, 3155 .stats_get_stats = mv88e6390_stats_get_stats, 3156 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3157 .set_egress_port = mv88e6390_g1_set_egress_port, 3158 .watchdog_ops = &mv88e6390_watchdog_ops, 3159 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3160 .pot_clear = mv88e6xxx_g2_pot_clear, 3161 .reset = mv88e6352_g1_reset, 3162 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3163 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3164 .serdes_power = mv88e6390_serdes_power, 3165 }; 3166 3167 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3168 [MV88E6085] = { 3169 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3170 .family = MV88E6XXX_FAMILY_6097, 3171 .name = "Marvell 88E6085", 3172 .num_databases = 4096, 3173 .num_ports = 10, 3174 .max_vid = 4095, 3175 .port_base_addr = 0x10, 3176 .global1_addr = 0x1b, 3177 .global2_addr = 0x1c, 3178 .age_time_coeff = 15000, 3179 .g1_irqs = 8, 3180 .g2_irqs = 10, 3181 .atu_move_port_mask = 0xf, 3182 .pvt = true, 3183 .multi_chip = true, 3184 .tag_protocol = DSA_TAG_PROTO_DSA, 3185 .ops = &mv88e6085_ops, 3186 }, 3187 3188 [MV88E6095] = { 3189 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3190 .family = MV88E6XXX_FAMILY_6095, 3191 .name = "Marvell 88E6095/88E6095F", 3192 .num_databases = 256, 3193 .num_ports = 11, 3194 .max_vid = 4095, 3195 .port_base_addr = 0x10, 3196 .global1_addr = 0x1b, 3197 .global2_addr = 0x1c, 3198 .age_time_coeff = 15000, 3199 .g1_irqs = 8, 3200 .atu_move_port_mask = 0xf, 3201 .multi_chip = true, 3202 .tag_protocol = DSA_TAG_PROTO_DSA, 3203 .ops = &mv88e6095_ops, 3204 }, 3205 3206 [MV88E6097] = { 3207 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3208 .family = MV88E6XXX_FAMILY_6097, 3209 .name = "Marvell 88E6097/88E6097F", 3210 .num_databases = 4096, 3211 .num_ports = 11, 3212 .max_vid = 4095, 3213 .port_base_addr = 0x10, 3214 .global1_addr = 0x1b, 3215 .global2_addr = 0x1c, 3216 .age_time_coeff = 15000, 3217 .g1_irqs = 8, 3218 .g2_irqs = 10, 3219 .atu_move_port_mask = 0xf, 3220 .pvt = true, 3221 .multi_chip = true, 3222 .tag_protocol = DSA_TAG_PROTO_EDSA, 3223 .ops = &mv88e6097_ops, 3224 }, 3225 3226 [MV88E6123] = { 3227 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3228 .family = MV88E6XXX_FAMILY_6165, 3229 .name = "Marvell 88E6123", 3230 .num_databases = 4096, 3231 .num_ports = 3, 3232 .max_vid = 4095, 3233 .port_base_addr = 0x10, 3234 .global1_addr = 0x1b, 3235 .global2_addr = 0x1c, 3236 .age_time_coeff = 15000, 3237 .g1_irqs = 9, 3238 .g2_irqs = 10, 3239 .atu_move_port_mask = 0xf, 3240 .pvt = true, 3241 .multi_chip = true, 3242 .tag_protocol = DSA_TAG_PROTO_EDSA, 3243 .ops = &mv88e6123_ops, 3244 }, 3245 3246 [MV88E6131] = { 3247 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3248 .family = MV88E6XXX_FAMILY_6185, 3249 .name = "Marvell 88E6131", 3250 .num_databases = 256, 3251 .num_ports = 8, 3252 .max_vid = 4095, 3253 .port_base_addr = 0x10, 3254 .global1_addr = 0x1b, 3255 .global2_addr = 0x1c, 3256 .age_time_coeff = 15000, 3257 .g1_irqs = 9, 3258 .atu_move_port_mask = 0xf, 3259 .multi_chip = true, 3260 .tag_protocol = DSA_TAG_PROTO_DSA, 3261 .ops = &mv88e6131_ops, 3262 }, 3263 3264 [MV88E6141] = { 3265 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3266 .family = MV88E6XXX_FAMILY_6341, 3267 .name = "Marvell 88E6341", 3268 .num_databases = 4096, 3269 .num_ports = 6, 3270 .max_vid = 4095, 3271 .port_base_addr = 0x10, 3272 .global1_addr = 0x1b, 3273 .global2_addr = 0x1c, 3274 .age_time_coeff = 3750, 3275 .atu_move_port_mask = 0x1f, 3276 .g2_irqs = 10, 3277 .pvt = true, 3278 .multi_chip = true, 3279 .tag_protocol = DSA_TAG_PROTO_EDSA, 3280 .ops = &mv88e6141_ops, 3281 }, 3282 3283 [MV88E6161] = { 3284 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3285 .family = MV88E6XXX_FAMILY_6165, 3286 .name = "Marvell 88E6161", 3287 .num_databases = 4096, 3288 .num_ports = 6, 3289 .max_vid = 4095, 3290 .port_base_addr = 0x10, 3291 .global1_addr = 0x1b, 3292 .global2_addr = 0x1c, 3293 .age_time_coeff = 15000, 3294 .g1_irqs = 9, 3295 .g2_irqs = 10, 3296 .atu_move_port_mask = 0xf, 3297 .pvt = true, 3298 .multi_chip = true, 3299 .tag_protocol = DSA_TAG_PROTO_EDSA, 3300 .ops = &mv88e6161_ops, 3301 }, 3302 3303 [MV88E6165] = { 3304 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3305 .family = MV88E6XXX_FAMILY_6165, 3306 .name = "Marvell 88E6165", 3307 .num_databases = 4096, 3308 .num_ports = 6, 3309 .max_vid = 4095, 3310 .port_base_addr = 0x10, 3311 .global1_addr = 0x1b, 3312 .global2_addr = 0x1c, 3313 .age_time_coeff = 15000, 3314 .g1_irqs = 9, 3315 .g2_irqs = 10, 3316 .atu_move_port_mask = 0xf, 3317 .pvt = true, 3318 .multi_chip = true, 3319 .tag_protocol = DSA_TAG_PROTO_DSA, 3320 .ops = &mv88e6165_ops, 3321 }, 3322 3323 [MV88E6171] = { 3324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3325 .family = MV88E6XXX_FAMILY_6351, 3326 .name = "Marvell 88E6171", 3327 .num_databases = 4096, 3328 .num_ports = 7, 3329 .max_vid = 4095, 3330 .port_base_addr = 0x10, 3331 .global1_addr = 0x1b, 3332 .global2_addr = 0x1c, 3333 .age_time_coeff = 15000, 3334 .g1_irqs = 9, 3335 .g2_irqs = 10, 3336 .atu_move_port_mask = 0xf, 3337 .pvt = true, 3338 .multi_chip = true, 3339 .tag_protocol = DSA_TAG_PROTO_EDSA, 3340 .ops = &mv88e6171_ops, 3341 }, 3342 3343 [MV88E6172] = { 3344 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3345 .family = MV88E6XXX_FAMILY_6352, 3346 .name = "Marvell 88E6172", 3347 .num_databases = 4096, 3348 .num_ports = 7, 3349 .max_vid = 4095, 3350 .port_base_addr = 0x10, 3351 .global1_addr = 0x1b, 3352 .global2_addr = 0x1c, 3353 .age_time_coeff = 15000, 3354 .g1_irqs = 9, 3355 .g2_irqs = 10, 3356 .atu_move_port_mask = 0xf, 3357 .pvt = true, 3358 .multi_chip = true, 3359 .tag_protocol = DSA_TAG_PROTO_EDSA, 3360 .ops = &mv88e6172_ops, 3361 }, 3362 3363 [MV88E6175] = { 3364 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3365 .family = MV88E6XXX_FAMILY_6351, 3366 .name = "Marvell 88E6175", 3367 .num_databases = 4096, 3368 .num_ports = 7, 3369 .max_vid = 4095, 3370 .port_base_addr = 0x10, 3371 .global1_addr = 0x1b, 3372 .global2_addr = 0x1c, 3373 .age_time_coeff = 15000, 3374 .g1_irqs = 9, 3375 .g2_irqs = 10, 3376 .atu_move_port_mask = 0xf, 3377 .pvt = true, 3378 .multi_chip = true, 3379 .tag_protocol = DSA_TAG_PROTO_EDSA, 3380 .ops = &mv88e6175_ops, 3381 }, 3382 3383 [MV88E6176] = { 3384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3385 .family = MV88E6XXX_FAMILY_6352, 3386 .name = "Marvell 88E6176", 3387 .num_databases = 4096, 3388 .num_ports = 7, 3389 .max_vid = 4095, 3390 .port_base_addr = 0x10, 3391 .global1_addr = 0x1b, 3392 .global2_addr = 0x1c, 3393 .age_time_coeff = 15000, 3394 .g1_irqs = 9, 3395 .g2_irqs = 10, 3396 .atu_move_port_mask = 0xf, 3397 .pvt = true, 3398 .multi_chip = true, 3399 .tag_protocol = DSA_TAG_PROTO_EDSA, 3400 .ops = &mv88e6176_ops, 3401 }, 3402 3403 [MV88E6185] = { 3404 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3405 .family = MV88E6XXX_FAMILY_6185, 3406 .name = "Marvell 88E6185", 3407 .num_databases = 256, 3408 .num_ports = 10, 3409 .max_vid = 4095, 3410 .port_base_addr = 0x10, 3411 .global1_addr = 0x1b, 3412 .global2_addr = 0x1c, 3413 .age_time_coeff = 15000, 3414 .g1_irqs = 8, 3415 .atu_move_port_mask = 0xf, 3416 .multi_chip = true, 3417 .tag_protocol = DSA_TAG_PROTO_EDSA, 3418 .ops = &mv88e6185_ops, 3419 }, 3420 3421 [MV88E6190] = { 3422 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3423 .family = MV88E6XXX_FAMILY_6390, 3424 .name = "Marvell 88E6190", 3425 .num_databases = 4096, 3426 .num_ports = 11, /* 10 + Z80 */ 3427 .max_vid = 8191, 3428 .port_base_addr = 0x0, 3429 .global1_addr = 0x1b, 3430 .global2_addr = 0x1c, 3431 .tag_protocol = DSA_TAG_PROTO_DSA, 3432 .age_time_coeff = 3750, 3433 .g1_irqs = 9, 3434 .g2_irqs = 14, 3435 .pvt = true, 3436 .multi_chip = true, 3437 .atu_move_port_mask = 0x1f, 3438 .ops = &mv88e6190_ops, 3439 }, 3440 3441 [MV88E6190X] = { 3442 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3443 .family = MV88E6XXX_FAMILY_6390, 3444 .name = "Marvell 88E6190X", 3445 .num_databases = 4096, 3446 .num_ports = 11, /* 10 + Z80 */ 3447 .max_vid = 8191, 3448 .port_base_addr = 0x0, 3449 .global1_addr = 0x1b, 3450 .global2_addr = 0x1c, 3451 .age_time_coeff = 3750, 3452 .g1_irqs = 9, 3453 .g2_irqs = 14, 3454 .atu_move_port_mask = 0x1f, 3455 .pvt = true, 3456 .multi_chip = true, 3457 .tag_protocol = DSA_TAG_PROTO_DSA, 3458 .ops = &mv88e6190x_ops, 3459 }, 3460 3461 [MV88E6191] = { 3462 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3463 .family = MV88E6XXX_FAMILY_6390, 3464 .name = "Marvell 88E6191", 3465 .num_databases = 4096, 3466 .num_ports = 11, /* 10 + Z80 */ 3467 .max_vid = 8191, 3468 .port_base_addr = 0x0, 3469 .global1_addr = 0x1b, 3470 .global2_addr = 0x1c, 3471 .age_time_coeff = 3750, 3472 .g1_irqs = 9, 3473 .g2_irqs = 14, 3474 .atu_move_port_mask = 0x1f, 3475 .pvt = true, 3476 .multi_chip = true, 3477 .tag_protocol = DSA_TAG_PROTO_DSA, 3478 .ops = &mv88e6191_ops, 3479 }, 3480 3481 [MV88E6240] = { 3482 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3483 .family = MV88E6XXX_FAMILY_6352, 3484 .name = "Marvell 88E6240", 3485 .num_databases = 4096, 3486 .num_ports = 7, 3487 .max_vid = 4095, 3488 .port_base_addr = 0x10, 3489 .global1_addr = 0x1b, 3490 .global2_addr = 0x1c, 3491 .age_time_coeff = 15000, 3492 .g1_irqs = 9, 3493 .g2_irqs = 10, 3494 .atu_move_port_mask = 0xf, 3495 .pvt = true, 3496 .multi_chip = true, 3497 .tag_protocol = DSA_TAG_PROTO_EDSA, 3498 .ops = &mv88e6240_ops, 3499 }, 3500 3501 [MV88E6290] = { 3502 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3503 .family = MV88E6XXX_FAMILY_6390, 3504 .name = "Marvell 88E6290", 3505 .num_databases = 4096, 3506 .num_ports = 11, /* 10 + Z80 */ 3507 .max_vid = 8191, 3508 .port_base_addr = 0x0, 3509 .global1_addr = 0x1b, 3510 .global2_addr = 0x1c, 3511 .age_time_coeff = 3750, 3512 .g1_irqs = 9, 3513 .g2_irqs = 14, 3514 .atu_move_port_mask = 0x1f, 3515 .pvt = true, 3516 .multi_chip = true, 3517 .tag_protocol = DSA_TAG_PROTO_DSA, 3518 .ops = &mv88e6290_ops, 3519 }, 3520 3521 [MV88E6320] = { 3522 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3523 .family = MV88E6XXX_FAMILY_6320, 3524 .name = "Marvell 88E6320", 3525 .num_databases = 4096, 3526 .num_ports = 7, 3527 .max_vid = 4095, 3528 .port_base_addr = 0x10, 3529 .global1_addr = 0x1b, 3530 .global2_addr = 0x1c, 3531 .age_time_coeff = 15000, 3532 .g1_irqs = 8, 3533 .atu_move_port_mask = 0xf, 3534 .pvt = true, 3535 .multi_chip = true, 3536 .tag_protocol = DSA_TAG_PROTO_EDSA, 3537 .ops = &mv88e6320_ops, 3538 }, 3539 3540 [MV88E6321] = { 3541 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3542 .family = MV88E6XXX_FAMILY_6320, 3543 .name = "Marvell 88E6321", 3544 .num_databases = 4096, 3545 .num_ports = 7, 3546 .max_vid = 4095, 3547 .port_base_addr = 0x10, 3548 .global1_addr = 0x1b, 3549 .global2_addr = 0x1c, 3550 .age_time_coeff = 15000, 3551 .g1_irqs = 8, 3552 .atu_move_port_mask = 0xf, 3553 .multi_chip = true, 3554 .tag_protocol = DSA_TAG_PROTO_EDSA, 3555 .ops = &mv88e6321_ops, 3556 }, 3557 3558 [MV88E6341] = { 3559 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3560 .family = MV88E6XXX_FAMILY_6341, 3561 .name = "Marvell 88E6341", 3562 .num_databases = 4096, 3563 .num_ports = 6, 3564 .max_vid = 4095, 3565 .port_base_addr = 0x10, 3566 .global1_addr = 0x1b, 3567 .global2_addr = 0x1c, 3568 .age_time_coeff = 3750, 3569 .atu_move_port_mask = 0x1f, 3570 .g2_irqs = 10, 3571 .pvt = true, 3572 .multi_chip = true, 3573 .tag_protocol = DSA_TAG_PROTO_EDSA, 3574 .ops = &mv88e6341_ops, 3575 }, 3576 3577 [MV88E6350] = { 3578 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3579 .family = MV88E6XXX_FAMILY_6351, 3580 .name = "Marvell 88E6350", 3581 .num_databases = 4096, 3582 .num_ports = 7, 3583 .max_vid = 4095, 3584 .port_base_addr = 0x10, 3585 .global1_addr = 0x1b, 3586 .global2_addr = 0x1c, 3587 .age_time_coeff = 15000, 3588 .g1_irqs = 9, 3589 .g2_irqs = 10, 3590 .atu_move_port_mask = 0xf, 3591 .pvt = true, 3592 .multi_chip = true, 3593 .tag_protocol = DSA_TAG_PROTO_EDSA, 3594 .ops = &mv88e6350_ops, 3595 }, 3596 3597 [MV88E6351] = { 3598 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3599 .family = MV88E6XXX_FAMILY_6351, 3600 .name = "Marvell 88E6351", 3601 .num_databases = 4096, 3602 .num_ports = 7, 3603 .max_vid = 4095, 3604 .port_base_addr = 0x10, 3605 .global1_addr = 0x1b, 3606 .global2_addr = 0x1c, 3607 .age_time_coeff = 15000, 3608 .g1_irqs = 9, 3609 .g2_irqs = 10, 3610 .atu_move_port_mask = 0xf, 3611 .pvt = true, 3612 .multi_chip = true, 3613 .tag_protocol = DSA_TAG_PROTO_EDSA, 3614 .ops = &mv88e6351_ops, 3615 }, 3616 3617 [MV88E6352] = { 3618 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3619 .family = MV88E6XXX_FAMILY_6352, 3620 .name = "Marvell 88E6352", 3621 .num_databases = 4096, 3622 .num_ports = 7, 3623 .max_vid = 4095, 3624 .port_base_addr = 0x10, 3625 .global1_addr = 0x1b, 3626 .global2_addr = 0x1c, 3627 .age_time_coeff = 15000, 3628 .g1_irqs = 9, 3629 .g2_irqs = 10, 3630 .atu_move_port_mask = 0xf, 3631 .pvt = true, 3632 .multi_chip = true, 3633 .tag_protocol = DSA_TAG_PROTO_EDSA, 3634 .ops = &mv88e6352_ops, 3635 }, 3636 [MV88E6390] = { 3637 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3638 .family = MV88E6XXX_FAMILY_6390, 3639 .name = "Marvell 88E6390", 3640 .num_databases = 4096, 3641 .num_ports = 11, /* 10 + Z80 */ 3642 .max_vid = 8191, 3643 .port_base_addr = 0x0, 3644 .global1_addr = 0x1b, 3645 .global2_addr = 0x1c, 3646 .age_time_coeff = 3750, 3647 .g1_irqs = 9, 3648 .g2_irqs = 14, 3649 .atu_move_port_mask = 0x1f, 3650 .pvt = true, 3651 .multi_chip = true, 3652 .tag_protocol = DSA_TAG_PROTO_DSA, 3653 .ops = &mv88e6390_ops, 3654 }, 3655 [MV88E6390X] = { 3656 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3657 .family = MV88E6XXX_FAMILY_6390, 3658 .name = "Marvell 88E6390X", 3659 .num_databases = 4096, 3660 .num_ports = 11, /* 10 + Z80 */ 3661 .max_vid = 8191, 3662 .port_base_addr = 0x0, 3663 .global1_addr = 0x1b, 3664 .global2_addr = 0x1c, 3665 .age_time_coeff = 3750, 3666 .g1_irqs = 9, 3667 .g2_irqs = 14, 3668 .atu_move_port_mask = 0x1f, 3669 .pvt = true, 3670 .multi_chip = true, 3671 .tag_protocol = DSA_TAG_PROTO_DSA, 3672 .ops = &mv88e6390x_ops, 3673 }, 3674 }; 3675 3676 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3677 { 3678 int i; 3679 3680 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3681 if (mv88e6xxx_table[i].prod_num == prod_num) 3682 return &mv88e6xxx_table[i]; 3683 3684 return NULL; 3685 } 3686 3687 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3688 { 3689 const struct mv88e6xxx_info *info; 3690 unsigned int prod_num, rev; 3691 u16 id; 3692 int err; 3693 3694 mutex_lock(&chip->reg_lock); 3695 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3696 mutex_unlock(&chip->reg_lock); 3697 if (err) 3698 return err; 3699 3700 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3701 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3702 3703 info = mv88e6xxx_lookup_info(prod_num); 3704 if (!info) 3705 return -ENODEV; 3706 3707 /* Update the compatible info with the probed one */ 3708 chip->info = info; 3709 3710 err = mv88e6xxx_g2_require(chip); 3711 if (err) 3712 return err; 3713 3714 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3715 chip->info->prod_num, chip->info->name, rev); 3716 3717 return 0; 3718 } 3719 3720 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3721 { 3722 struct mv88e6xxx_chip *chip; 3723 3724 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3725 if (!chip) 3726 return NULL; 3727 3728 chip->dev = dev; 3729 3730 mutex_init(&chip->reg_lock); 3731 INIT_LIST_HEAD(&chip->mdios); 3732 3733 return chip; 3734 } 3735 3736 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3737 struct mii_bus *bus, int sw_addr) 3738 { 3739 if (sw_addr == 0) 3740 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3741 else if (chip->info->multi_chip) 3742 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3743 else 3744 return -EINVAL; 3745 3746 chip->bus = bus; 3747 chip->sw_addr = sw_addr; 3748 3749 return 0; 3750 } 3751 3752 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 3753 int port) 3754 { 3755 struct mv88e6xxx_chip *chip = ds->priv; 3756 3757 return chip->info->tag_protocol; 3758 } 3759 3760 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 3761 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3762 struct device *host_dev, int sw_addr, 3763 void **priv) 3764 { 3765 struct mv88e6xxx_chip *chip; 3766 struct mii_bus *bus; 3767 int err; 3768 3769 bus = dsa_host_dev_to_mii_bus(host_dev); 3770 if (!bus) 3771 return NULL; 3772 3773 chip = mv88e6xxx_alloc_chip(dsa_dev); 3774 if (!chip) 3775 return NULL; 3776 3777 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3778 chip->info = &mv88e6xxx_table[MV88E6085]; 3779 3780 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3781 if (err) 3782 goto free; 3783 3784 err = mv88e6xxx_detect(chip); 3785 if (err) 3786 goto free; 3787 3788 mutex_lock(&chip->reg_lock); 3789 err = mv88e6xxx_switch_reset(chip); 3790 mutex_unlock(&chip->reg_lock); 3791 if (err) 3792 goto free; 3793 3794 mv88e6xxx_phy_init(chip); 3795 3796 err = mv88e6xxx_mdios_register(chip, NULL); 3797 if (err) 3798 goto free; 3799 3800 *priv = chip; 3801 3802 return chip->info->name; 3803 free: 3804 devm_kfree(dsa_dev, chip); 3805 3806 return NULL; 3807 } 3808 #endif 3809 3810 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3811 const struct switchdev_obj_port_mdb *mdb) 3812 { 3813 /* We don't need any dynamic resource from the kernel (yet), 3814 * so skip the prepare phase. 3815 */ 3816 3817 return 0; 3818 } 3819 3820 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3821 const struct switchdev_obj_port_mdb *mdb) 3822 { 3823 struct mv88e6xxx_chip *chip = ds->priv; 3824 3825 mutex_lock(&chip->reg_lock); 3826 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3827 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3828 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3829 port); 3830 mutex_unlock(&chip->reg_lock); 3831 } 3832 3833 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3834 const struct switchdev_obj_port_mdb *mdb) 3835 { 3836 struct mv88e6xxx_chip *chip = ds->priv; 3837 int err; 3838 3839 mutex_lock(&chip->reg_lock); 3840 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3841 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3842 mutex_unlock(&chip->reg_lock); 3843 3844 return err; 3845 } 3846 3847 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3848 #if IS_ENABLED(CONFIG_NET_DSA_LEGACY) 3849 .probe = mv88e6xxx_drv_probe, 3850 #endif 3851 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3852 .setup = mv88e6xxx_setup, 3853 .adjust_link = mv88e6xxx_adjust_link, 3854 .get_strings = mv88e6xxx_get_strings, 3855 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3856 .get_sset_count = mv88e6xxx_get_sset_count, 3857 .port_enable = mv88e6xxx_port_enable, 3858 .port_disable = mv88e6xxx_port_disable, 3859 .get_mac_eee = mv88e6xxx_get_mac_eee, 3860 .set_mac_eee = mv88e6xxx_set_mac_eee, 3861 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3862 .get_eeprom = mv88e6xxx_get_eeprom, 3863 .set_eeprom = mv88e6xxx_set_eeprom, 3864 .get_regs_len = mv88e6xxx_get_regs_len, 3865 .get_regs = mv88e6xxx_get_regs, 3866 .set_ageing_time = mv88e6xxx_set_ageing_time, 3867 .port_bridge_join = mv88e6xxx_port_bridge_join, 3868 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3869 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3870 .port_fast_age = mv88e6xxx_port_fast_age, 3871 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3872 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3873 .port_vlan_add = mv88e6xxx_port_vlan_add, 3874 .port_vlan_del = mv88e6xxx_port_vlan_del, 3875 .port_fdb_add = mv88e6xxx_port_fdb_add, 3876 .port_fdb_del = mv88e6xxx_port_fdb_del, 3877 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3878 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3879 .port_mdb_add = mv88e6xxx_port_mdb_add, 3880 .port_mdb_del = mv88e6xxx_port_mdb_del, 3881 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 3882 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 3883 }; 3884 3885 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 3886 .ops = &mv88e6xxx_switch_ops, 3887 }; 3888 3889 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 3890 { 3891 struct device *dev = chip->dev; 3892 struct dsa_switch *ds; 3893 3894 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 3895 if (!ds) 3896 return -ENOMEM; 3897 3898 ds->priv = chip; 3899 ds->ops = &mv88e6xxx_switch_ops; 3900 ds->ageing_time_min = chip->info->age_time_coeff; 3901 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 3902 3903 dev_set_drvdata(dev, ds); 3904 3905 return dsa_register_switch(ds); 3906 } 3907 3908 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3909 { 3910 dsa_unregister_switch(chip->ds); 3911 } 3912 3913 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3914 { 3915 struct device *dev = &mdiodev->dev; 3916 struct device_node *np = dev->of_node; 3917 const struct mv88e6xxx_info *compat_info; 3918 struct mv88e6xxx_chip *chip; 3919 u32 eeprom_len; 3920 int err; 3921 3922 compat_info = of_device_get_match_data(dev); 3923 if (!compat_info) 3924 return -EINVAL; 3925 3926 chip = mv88e6xxx_alloc_chip(dev); 3927 if (!chip) 3928 return -ENOMEM; 3929 3930 chip->info = compat_info; 3931 3932 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3933 if (err) 3934 return err; 3935 3936 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 3937 if (IS_ERR(chip->reset)) 3938 return PTR_ERR(chip->reset); 3939 3940 err = mv88e6xxx_detect(chip); 3941 if (err) 3942 return err; 3943 3944 mv88e6xxx_phy_init(chip); 3945 3946 if (chip->info->ops->get_eeprom && 3947 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3948 chip->eeprom_len = eeprom_len; 3949 3950 mutex_lock(&chip->reg_lock); 3951 err = mv88e6xxx_switch_reset(chip); 3952 mutex_unlock(&chip->reg_lock); 3953 if (err) 3954 goto out; 3955 3956 chip->irq = of_irq_get(np, 0); 3957 if (chip->irq == -EPROBE_DEFER) { 3958 err = chip->irq; 3959 goto out; 3960 } 3961 3962 if (chip->irq > 0) { 3963 /* Has to be performed before the MDIO bus is created, 3964 * because the PHYs will link there interrupts to these 3965 * interrupt controllers 3966 */ 3967 mutex_lock(&chip->reg_lock); 3968 err = mv88e6xxx_g1_irq_setup(chip); 3969 mutex_unlock(&chip->reg_lock); 3970 3971 if (err) 3972 goto out; 3973 3974 if (chip->info->g2_irqs > 0) { 3975 err = mv88e6xxx_g2_irq_setup(chip); 3976 if (err) 3977 goto out_g1_irq; 3978 } 3979 3980 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 3981 if (err) 3982 goto out_g2_irq; 3983 3984 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 3985 if (err) 3986 goto out_g1_atu_prob_irq; 3987 } 3988 3989 err = mv88e6xxx_mdios_register(chip, np); 3990 if (err) 3991 goto out_g1_vtu_prob_irq; 3992 3993 err = mv88e6xxx_register_switch(chip); 3994 if (err) 3995 goto out_mdio; 3996 3997 return 0; 3998 3999 out_mdio: 4000 mv88e6xxx_mdios_unregister(chip); 4001 out_g1_vtu_prob_irq: 4002 if (chip->irq > 0) 4003 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4004 out_g1_atu_prob_irq: 4005 if (chip->irq > 0) 4006 mv88e6xxx_g1_atu_prob_irq_free(chip); 4007 out_g2_irq: 4008 if (chip->info->g2_irqs > 0 && chip->irq > 0) 4009 mv88e6xxx_g2_irq_free(chip); 4010 out_g1_irq: 4011 if (chip->irq > 0) { 4012 mutex_lock(&chip->reg_lock); 4013 mv88e6xxx_g1_irq_free(chip); 4014 mutex_unlock(&chip->reg_lock); 4015 } 4016 out: 4017 return err; 4018 } 4019 4020 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4021 { 4022 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4023 struct mv88e6xxx_chip *chip = ds->priv; 4024 4025 mv88e6xxx_phy_destroy(chip); 4026 mv88e6xxx_unregister_switch(chip); 4027 mv88e6xxx_mdios_unregister(chip); 4028 4029 if (chip->irq > 0) { 4030 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4031 mv88e6xxx_g1_atu_prob_irq_free(chip); 4032 if (chip->info->g2_irqs > 0) 4033 mv88e6xxx_g2_irq_free(chip); 4034 mutex_lock(&chip->reg_lock); 4035 mv88e6xxx_g1_irq_free(chip); 4036 mutex_unlock(&chip->reg_lock); 4037 } 4038 } 4039 4040 static const struct of_device_id mv88e6xxx_of_match[] = { 4041 { 4042 .compatible = "marvell,mv88e6085", 4043 .data = &mv88e6xxx_table[MV88E6085], 4044 }, 4045 { 4046 .compatible = "marvell,mv88e6190", 4047 .data = &mv88e6xxx_table[MV88E6190], 4048 }, 4049 { /* sentinel */ }, 4050 }; 4051 4052 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4053 4054 static struct mdio_driver mv88e6xxx_driver = { 4055 .probe = mv88e6xxx_probe, 4056 .remove = mv88e6xxx_remove, 4057 .mdiodrv.driver = { 4058 .name = "mv88e6085", 4059 .of_match_table = mv88e6xxx_of_match, 4060 }, 4061 }; 4062 4063 static int __init mv88e6xxx_init(void) 4064 { 4065 register_switch_driver(&mv88e6xxx_switch_drv); 4066 return mdio_driver_register(&mv88e6xxx_driver); 4067 } 4068 module_init(mv88e6xxx_init); 4069 4070 static void __exit mv88e6xxx_cleanup(void) 4071 { 4072 mdio_driver_unregister(&mv88e6xxx_driver); 4073 unregister_switch_driver(&mv88e6xxx_switch_drv); 4074 } 4075 module_exit(mv88e6xxx_cleanup); 4076 4077 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4078 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4079 MODULE_LICENSE("GPL"); 4080