1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "serdes.h" 42 43 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 44 { 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 46 dev_err(chip->dev, "Switch registers lock not held!\n"); 47 dump_stack(); 48 } 49 } 50 51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 53 * 54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 55 * is the only device connected to the SMI master. In this mode it responds to 56 * all 32 possible SMI addresses, and thus maps directly the internal devices. 57 * 58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 59 * multiple devices to share the SMI interface. In this mode it responds to only 60 * 2 registers, used to indirectly access the internal SMI devices. 61 */ 62 63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 *val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->read(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 val) 74 { 75 if (!chip->smi_ops) 76 return -EOPNOTSUPP; 77 78 return chip->smi_ops->write(chip, addr, reg, val); 79 } 80 81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 82 int addr, int reg, u16 *val) 83 { 84 int ret; 85 86 ret = mdiobus_read_nested(chip->bus, addr, reg); 87 if (ret < 0) 88 return ret; 89 90 *val = ret & 0xffff; 91 92 return 0; 93 } 94 95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 96 int addr, int reg, u16 val) 97 { 98 int ret; 99 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 101 if (ret < 0) 102 return ret; 103 104 return 0; 105 } 106 107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 108 .read = mv88e6xxx_smi_single_chip_read, 109 .write = mv88e6xxx_smi_single_chip_write, 110 }; 111 112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 113 { 114 int ret; 115 int i; 116 117 for (i = 0; i < 16; i++) { 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 119 if (ret < 0) 120 return ret; 121 122 if ((ret & SMI_CMD_BUSY) == 0) 123 return 0; 124 } 125 126 return -ETIMEDOUT; 127 } 128 129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 130 int addr, int reg, u16 *val) 131 { 132 int ret; 133 134 /* Wait for the bus to become free. */ 135 ret = mv88e6xxx_smi_multi_chip_wait(chip); 136 if (ret < 0) 137 return ret; 138 139 /* Transmit the read command. */ 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 141 SMI_CMD_OP_22_READ | (addr << 5) | reg); 142 if (ret < 0) 143 return ret; 144 145 /* Wait for the read command to complete. */ 146 ret = mv88e6xxx_smi_multi_chip_wait(chip); 147 if (ret < 0) 148 return ret; 149 150 /* Read the data. */ 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 152 if (ret < 0) 153 return ret; 154 155 *val = ret & 0xffff; 156 157 return 0; 158 } 159 160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 161 int addr, int reg, u16 val) 162 { 163 int ret; 164 165 /* Wait for the bus to become free. */ 166 ret = mv88e6xxx_smi_multi_chip_wait(chip); 167 if (ret < 0) 168 return ret; 169 170 /* Transmit the data to write. */ 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 172 if (ret < 0) 173 return ret; 174 175 /* Transmit the write command. */ 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 178 if (ret < 0) 179 return ret; 180 181 /* Wait for the write command to complete. */ 182 ret = mv88e6xxx_smi_multi_chip_wait(chip); 183 if (ret < 0) 184 return ret; 185 186 return 0; 187 } 188 189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 190 .read = mv88e6xxx_smi_multi_chip_read, 191 .write = mv88e6xxx_smi_multi_chip_write, 192 }; 193 194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 195 { 196 int err; 197 198 assert_reg_lock(chip); 199 200 err = mv88e6xxx_smi_read(chip, addr, reg, val); 201 if (err) 202 return err; 203 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 205 addr, reg, *val); 206 207 return 0; 208 } 209 210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 211 { 212 int err; 213 214 assert_reg_lock(chip); 215 216 err = mv88e6xxx_smi_write(chip, addr, reg, val); 217 if (err) 218 return err; 219 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 221 addr, reg, val); 222 223 return 0; 224 } 225 226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 227 { 228 struct mv88e6xxx_mdio_bus *mdio_bus; 229 230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 231 list); 232 if (!mdio_bus) 233 return NULL; 234 235 return mdio_bus->bus; 236 } 237 238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 239 { 240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 241 unsigned int n = d->hwirq; 242 243 chip->g1_irq.masked |= (1 << n); 244 } 245 246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 247 { 248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 249 unsigned int n = d->hwirq; 250 251 chip->g1_irq.masked &= ~(1 << n); 252 } 253 254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 255 { 256 struct mv88e6xxx_chip *chip = dev_id; 257 unsigned int nhandled = 0; 258 unsigned int sub_irq; 259 unsigned int n; 260 u16 reg; 261 int err; 262 263 mutex_lock(&chip->reg_lock); 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 265 mutex_unlock(&chip->reg_lock); 266 267 if (err) 268 goto out; 269 270 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 271 if (reg & (1 << n)) { 272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 273 handle_nested_irq(sub_irq); 274 ++nhandled; 275 } 276 } 277 out: 278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 279 } 280 281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 282 { 283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 284 285 mutex_lock(&chip->reg_lock); 286 } 287 288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 289 { 290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 292 u16 reg; 293 int err; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 296 if (err) 297 goto out; 298 299 reg &= ~mask; 300 reg |= (~chip->g1_irq.masked & mask); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 303 if (err) 304 goto out; 305 306 out: 307 mutex_unlock(&chip->reg_lock); 308 } 309 310 static struct irq_chip mv88e6xxx_g1_irq_chip = { 311 .name = "mv88e6xxx-g1", 312 .irq_mask = mv88e6xxx_g1_irq_mask, 313 .irq_unmask = mv88e6xxx_g1_irq_unmask, 314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 316 }; 317 318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 319 unsigned int irq, 320 irq_hw_number_t hwirq) 321 { 322 struct mv88e6xxx_chip *chip = d->host_data; 323 324 irq_set_chip_data(irq, d->host_data); 325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 326 irq_set_noprobe(irq); 327 328 return 0; 329 } 330 331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 332 .map = mv88e6xxx_g1_irq_domain_map, 333 .xlate = irq_domain_xlate_twocell, 334 }; 335 336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 337 { 338 int irq, virq; 339 u16 mask; 340 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 342 mask |= GENMASK(chip->g1_irq.nirqs, 0); 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 344 345 free_irq(chip->irq, chip); 346 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 348 virq = irq_find_mapping(chip->g1_irq.domain, irq); 349 irq_dispose_mapping(virq); 350 } 351 352 irq_domain_remove(chip->g1_irq.domain); 353 } 354 355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 356 { 357 int err, irq, virq; 358 u16 reg, mask; 359 360 chip->g1_irq.nirqs = chip->info->g1_irqs; 361 chip->g1_irq.domain = irq_domain_add_simple( 362 NULL, chip->g1_irq.nirqs, 0, 363 &mv88e6xxx_g1_irq_domain_ops, chip); 364 if (!chip->g1_irq.domain) 365 return -ENOMEM; 366 367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 368 irq_create_mapping(chip->g1_irq.domain, irq); 369 370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 371 chip->g1_irq.masked = ~0; 372 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 374 if (err) 375 goto out_mapping; 376 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 378 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 380 if (err) 381 goto out_disable; 382 383 /* Reading the interrupt status clears (most of) them */ 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 385 if (err) 386 goto out_disable; 387 388 err = request_threaded_irq(chip->irq, NULL, 389 mv88e6xxx_g1_irq_thread_fn, 390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 391 dev_name(chip->dev), chip); 392 if (err) 393 goto out_disable; 394 395 return 0; 396 397 out_disable: 398 mask |= GENMASK(chip->g1_irq.nirqs, 0); 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 400 401 out_mapping: 402 for (irq = 0; irq < 16; irq++) { 403 virq = irq_find_mapping(chip->g1_irq.domain, irq); 404 irq_dispose_mapping(virq); 405 } 406 407 irq_domain_remove(chip->g1_irq.domain); 408 409 return err; 410 } 411 412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 413 { 414 int i; 415 416 for (i = 0; i < 16; i++) { 417 u16 val; 418 int err; 419 420 err = mv88e6xxx_read(chip, addr, reg, &val); 421 if (err) 422 return err; 423 424 if (!(val & mask)) 425 return 0; 426 427 usleep_range(1000, 2000); 428 } 429 430 dev_err(chip->dev, "Timeout while waiting for switch\n"); 431 return -ETIMEDOUT; 432 } 433 434 /* Indirect write to single pointer-data register with an Update bit */ 435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 436 { 437 u16 val; 438 int err; 439 440 /* Wait until the previous operation is completed */ 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 442 if (err) 443 return err; 444 445 /* Set the Update bit to trigger a write operation */ 446 val = BIT(15) | update; 447 448 return mv88e6xxx_write(chip, addr, reg, val); 449 } 450 451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 452 int link, int speed, int duplex, 453 phy_interface_t mode) 454 { 455 int err; 456 457 if (!chip->info->ops->port_set_link) 458 return 0; 459 460 /* Port's MAC control must not be changed unless the link is down */ 461 err = chip->info->ops->port_set_link(chip, port, 0); 462 if (err) 463 return err; 464 465 if (chip->info->ops->port_set_speed) { 466 err = chip->info->ops->port_set_speed(chip, port, speed); 467 if (err && err != -EOPNOTSUPP) 468 goto restore_link; 469 } 470 471 if (chip->info->ops->port_set_duplex) { 472 err = chip->info->ops->port_set_duplex(chip, port, duplex); 473 if (err && err != -EOPNOTSUPP) 474 goto restore_link; 475 } 476 477 if (chip->info->ops->port_set_rgmii_delay) { 478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 479 if (err && err != -EOPNOTSUPP) 480 goto restore_link; 481 } 482 483 if (chip->info->ops->port_set_cmode) { 484 err = chip->info->ops->port_set_cmode(chip, port, mode); 485 if (err && err != -EOPNOTSUPP) 486 goto restore_link; 487 } 488 489 err = 0; 490 restore_link: 491 if (chip->info->ops->port_set_link(chip, port, link)) 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 493 494 return err; 495 } 496 497 /* We expect the switch to perform auto negotiation if there is a real 498 * phy. However, in the case of a fixed link phy, we force the port 499 * settings from the fixed link settings. 500 */ 501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 502 struct phy_device *phydev) 503 { 504 struct mv88e6xxx_chip *chip = ds->priv; 505 int err; 506 507 if (!phy_is_pseudo_fixed_link(phydev)) 508 return; 509 510 mutex_lock(&chip->reg_lock); 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 512 phydev->duplex, phydev->interface); 513 mutex_unlock(&chip->reg_lock); 514 515 if (err && err != -EOPNOTSUPP) 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 517 } 518 519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 if (!chip->info->ops->stats_snapshot) 522 return -EOPNOTSUPP; 523 524 return chip->info->ops->stats_snapshot(chip, port); 525 } 526 527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 548 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 551 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 587 }; 588 589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 590 struct mv88e6xxx_hw_stat *s, 591 int port, u16 bank1_select, 592 u16 histogram) 593 { 594 u32 low; 595 u32 high = 0; 596 u16 reg = 0; 597 int err; 598 u64 value; 599 600 switch (s->type) { 601 case STATS_TYPE_PORT: 602 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 603 if (err) 604 return UINT64_MAX; 605 606 low = reg; 607 if (s->sizeof_stat == 4) { 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 609 if (err) 610 return UINT64_MAX; 611 high = reg; 612 } 613 break; 614 case STATS_TYPE_BANK1: 615 reg = bank1_select; 616 /* fall through */ 617 case STATS_TYPE_BANK0: 618 reg |= s->reg | histogram; 619 mv88e6xxx_g1_stats_read(chip, reg, &low); 620 if (s->sizeof_stat == 8) 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 622 break; 623 default: 624 return UINT64_MAX; 625 } 626 value = (((u64)high) << 16) | low; 627 return value; 628 } 629 630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 631 uint8_t *data, int types) 632 { 633 struct mv88e6xxx_hw_stat *stat; 634 int i, j; 635 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 637 stat = &mv88e6xxx_hw_stats[i]; 638 if (stat->type & types) { 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 640 ETH_GSTRING_LEN); 641 j++; 642 } 643 } 644 } 645 646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 647 uint8_t *data) 648 { 649 mv88e6xxx_stats_get_strings(chip, data, 650 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 651 } 652 653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 654 uint8_t *data) 655 { 656 mv88e6xxx_stats_get_strings(chip, data, 657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 658 } 659 660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 661 uint8_t *data) 662 { 663 struct mv88e6xxx_chip *chip = ds->priv; 664 665 if (chip->info->ops->stats_get_strings) 666 chip->info->ops->stats_get_strings(chip, data); 667 } 668 669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 670 int types) 671 { 672 struct mv88e6xxx_hw_stat *stat; 673 int i, j; 674 675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 676 stat = &mv88e6xxx_hw_stats[i]; 677 if (stat->type & types) 678 j++; 679 } 680 return j; 681 } 682 683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 684 { 685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 686 STATS_TYPE_PORT); 687 } 688 689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 692 STATS_TYPE_BANK1); 693 } 694 695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 696 { 697 struct mv88e6xxx_chip *chip = ds->priv; 698 699 if (chip->info->ops->stats_get_sset_count) 700 return chip->info->ops->stats_get_sset_count(chip); 701 702 return 0; 703 } 704 705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 706 uint64_t *data, int types, 707 u16 bank1_select, u16 histogram) 708 { 709 struct mv88e6xxx_hw_stat *stat; 710 int i, j; 711 712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 713 stat = &mv88e6xxx_hw_stats[i]; 714 if (stat->type & types) { 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 716 bank1_select, 717 histogram); 718 j++; 719 } 720 } 721 } 722 723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 724 uint64_t *data) 725 { 726 return mv88e6xxx_stats_get_stats(chip, port, data, 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 729 } 730 731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 732 uint64_t *data) 733 { 734 return mv88e6xxx_stats_get_stats(chip, port, data, 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 738 } 739 740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 741 uint64_t *data) 742 { 743 return mv88e6xxx_stats_get_stats(chip, port, data, 744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 746 0); 747 } 748 749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 750 uint64_t *data) 751 { 752 if (chip->info->ops->stats_get_stats) 753 chip->info->ops->stats_get_stats(chip, port, data); 754 } 755 756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 757 uint64_t *data) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 int ret; 761 762 mutex_lock(&chip->reg_lock); 763 764 ret = mv88e6xxx_stats_snapshot(chip, port); 765 if (ret < 0) { 766 mutex_unlock(&chip->reg_lock); 767 return; 768 } 769 770 mv88e6xxx_get_stats(chip, port, data); 771 772 mutex_unlock(&chip->reg_lock); 773 } 774 775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 776 { 777 if (chip->info->ops->stats_set_histogram) 778 return chip->info->ops->stats_set_histogram(chip); 779 780 return 0; 781 } 782 783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 784 { 785 return 32 * sizeof(u16); 786 } 787 788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 789 struct ethtool_regs *regs, void *_p) 790 { 791 struct mv88e6xxx_chip *chip = ds->priv; 792 int err; 793 u16 reg; 794 u16 *p = _p; 795 int i; 796 797 regs->version = 0; 798 799 memset(p, 0xff, 32 * sizeof(u16)); 800 801 mutex_lock(&chip->reg_lock); 802 803 for (i = 0; i < 32; i++) { 804 805 err = mv88e6xxx_port_read(chip, port, i, ®); 806 if (!err) 807 p[i] = reg; 808 } 809 810 mutex_unlock(&chip->reg_lock); 811 } 812 813 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 814 struct ethtool_eee *e) 815 { 816 struct mv88e6xxx_chip *chip = ds->priv; 817 u16 reg; 818 int err; 819 820 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 821 return -EOPNOTSUPP; 822 823 mutex_lock(&chip->reg_lock); 824 825 err = mv88e6xxx_phy_read(chip, port, 16, ®); 826 if (err) 827 goto out; 828 829 e->eee_enabled = !!(reg & 0x0200); 830 e->tx_lpi_enabled = !!(reg & 0x0100); 831 832 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 833 if (err) 834 goto out; 835 836 e->eee_active = !!(reg & MV88E6352_PORT_STS_EEE); 837 out: 838 mutex_unlock(&chip->reg_lock); 839 840 return err; 841 } 842 843 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 844 struct phy_device *phydev, struct ethtool_eee *e) 845 { 846 struct mv88e6xxx_chip *chip = ds->priv; 847 u16 reg; 848 int err; 849 850 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 851 return -EOPNOTSUPP; 852 853 mutex_lock(&chip->reg_lock); 854 855 err = mv88e6xxx_phy_read(chip, port, 16, ®); 856 if (err) 857 goto out; 858 859 reg &= ~0x0300; 860 if (e->eee_enabled) 861 reg |= 0x0200; 862 if (e->tx_lpi_enabled) 863 reg |= 0x0100; 864 865 err = mv88e6xxx_phy_write(chip, port, 16, reg); 866 out: 867 mutex_unlock(&chip->reg_lock); 868 869 return err; 870 } 871 872 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 873 { 874 struct dsa_switch *ds = NULL; 875 struct net_device *br; 876 u16 pvlan; 877 int i; 878 879 if (dev < DSA_MAX_SWITCHES) 880 ds = chip->ds->dst->ds[dev]; 881 882 /* Prevent frames from unknown switch or port */ 883 if (!ds || port >= ds->num_ports) 884 return 0; 885 886 /* Frames from DSA links and CPU ports can egress any local port */ 887 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 888 return mv88e6xxx_port_mask(chip); 889 890 br = ds->ports[port].bridge_dev; 891 pvlan = 0; 892 893 /* Frames from user ports can egress any local DSA links and CPU ports, 894 * as well as any local member of their bridge group. 895 */ 896 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 897 if (dsa_is_cpu_port(chip->ds, i) || 898 dsa_is_dsa_port(chip->ds, i) || 899 (br && chip->ds->ports[i].bridge_dev == br)) 900 pvlan |= BIT(i); 901 902 return pvlan; 903 } 904 905 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 906 { 907 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 908 909 /* prevent frames from going back out of the port they came in on */ 910 output_ports &= ~BIT(port); 911 912 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 913 } 914 915 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 916 u8 state) 917 { 918 struct mv88e6xxx_chip *chip = ds->priv; 919 int err; 920 921 mutex_lock(&chip->reg_lock); 922 err = mv88e6xxx_port_set_state(chip, port, state); 923 mutex_unlock(&chip->reg_lock); 924 925 if (err) 926 dev_err(ds->dev, "p%d: failed to update state\n", port); 927 } 928 929 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 930 { 931 int err; 932 933 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 934 if (err) 935 return err; 936 937 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 938 if (err) 939 return err; 940 941 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 942 } 943 944 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 945 { 946 int port; 947 int err; 948 949 if (!chip->info->ops->irl_init_all) 950 return 0; 951 952 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 953 /* Disable ingress rate limiting by resetting all per port 954 * ingress rate limit resources to their initial state. 955 */ 956 err = chip->info->ops->irl_init_all(chip, port); 957 if (err) 958 return err; 959 } 960 961 return 0; 962 } 963 964 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 965 { 966 u16 pvlan = 0; 967 968 if (!mv88e6xxx_has_pvt(chip)) 969 return -EOPNOTSUPP; 970 971 /* Skip the local source device, which uses in-chip port VLAN */ 972 if (dev != chip->ds->index) 973 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 974 975 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 976 } 977 978 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 979 { 980 int dev, port; 981 int err; 982 983 if (!mv88e6xxx_has_pvt(chip)) 984 return 0; 985 986 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 987 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 988 */ 989 err = mv88e6xxx_g2_misc_4_bit_port(chip); 990 if (err) 991 return err; 992 993 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 994 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 995 err = mv88e6xxx_pvt_map(chip, dev, port); 996 if (err) 997 return err; 998 } 999 } 1000 1001 return 0; 1002 } 1003 1004 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1005 { 1006 struct mv88e6xxx_chip *chip = ds->priv; 1007 int err; 1008 1009 mutex_lock(&chip->reg_lock); 1010 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1011 mutex_unlock(&chip->reg_lock); 1012 1013 if (err) 1014 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1015 } 1016 1017 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1018 { 1019 if (!chip->info->max_vid) 1020 return 0; 1021 1022 return mv88e6xxx_g1_vtu_flush(chip); 1023 } 1024 1025 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1026 struct mv88e6xxx_vtu_entry *entry) 1027 { 1028 if (!chip->info->ops->vtu_getnext) 1029 return -EOPNOTSUPP; 1030 1031 return chip->info->ops->vtu_getnext(chip, entry); 1032 } 1033 1034 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1035 struct mv88e6xxx_vtu_entry *entry) 1036 { 1037 if (!chip->info->ops->vtu_loadpurge) 1038 return -EOPNOTSUPP; 1039 1040 return chip->info->ops->vtu_loadpurge(chip, entry); 1041 } 1042 1043 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, 1044 struct switchdev_obj_port_vlan *vlan, 1045 switchdev_obj_dump_cb_t *cb) 1046 { 1047 struct mv88e6xxx_chip *chip = ds->priv; 1048 struct mv88e6xxx_vtu_entry next = { 1049 .vid = chip->info->max_vid, 1050 }; 1051 u16 pvid; 1052 int err; 1053 1054 if (!chip->info->max_vid) 1055 return -EOPNOTSUPP; 1056 1057 mutex_lock(&chip->reg_lock); 1058 1059 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1060 if (err) 1061 goto unlock; 1062 1063 do { 1064 err = mv88e6xxx_vtu_getnext(chip, &next); 1065 if (err) 1066 break; 1067 1068 if (!next.valid) 1069 break; 1070 1071 if (next.member[port] == 1072 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1073 continue; 1074 1075 /* reinit and dump this VLAN obj */ 1076 vlan->vid_begin = next.vid; 1077 vlan->vid_end = next.vid; 1078 vlan->flags = 0; 1079 1080 if (next.member[port] == 1081 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED) 1082 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1083 1084 if (next.vid == pvid) 1085 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1086 1087 err = cb(&vlan->obj); 1088 if (err) 1089 break; 1090 } while (next.vid < chip->info->max_vid); 1091 1092 unlock: 1093 mutex_unlock(&chip->reg_lock); 1094 1095 return err; 1096 } 1097 1098 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1099 { 1100 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1101 struct mv88e6xxx_vtu_entry vlan = { 1102 .vid = chip->info->max_vid, 1103 }; 1104 int i, err; 1105 1106 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1107 1108 /* Set every FID bit used by the (un)bridged ports */ 1109 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1110 err = mv88e6xxx_port_get_fid(chip, i, fid); 1111 if (err) 1112 return err; 1113 1114 set_bit(*fid, fid_bitmap); 1115 } 1116 1117 /* Set every FID bit used by the VLAN entries */ 1118 do { 1119 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1120 if (err) 1121 return err; 1122 1123 if (!vlan.valid) 1124 break; 1125 1126 set_bit(vlan.fid, fid_bitmap); 1127 } while (vlan.vid < chip->info->max_vid); 1128 1129 /* The reset value 0x000 is used to indicate that multiple address 1130 * databases are not needed. Return the next positive available. 1131 */ 1132 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1133 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1134 return -ENOSPC; 1135 1136 /* Clear the database */ 1137 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1138 } 1139 1140 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1141 struct mv88e6xxx_vtu_entry *entry, bool new) 1142 { 1143 int err; 1144 1145 if (!vid) 1146 return -EINVAL; 1147 1148 entry->vid = vid - 1; 1149 entry->valid = false; 1150 1151 err = mv88e6xxx_vtu_getnext(chip, entry); 1152 if (err) 1153 return err; 1154 1155 if (entry->vid == vid && entry->valid) 1156 return 0; 1157 1158 if (new) { 1159 int i; 1160 1161 /* Initialize a fresh VLAN entry */ 1162 memset(entry, 0, sizeof(*entry)); 1163 entry->valid = true; 1164 entry->vid = vid; 1165 1166 /* Exclude all ports */ 1167 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1168 entry->member[i] = 1169 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1170 1171 return mv88e6xxx_atu_new(chip, &entry->fid); 1172 } 1173 1174 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1175 return -EOPNOTSUPP; 1176 } 1177 1178 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1179 u16 vid_begin, u16 vid_end) 1180 { 1181 struct mv88e6xxx_chip *chip = ds->priv; 1182 struct mv88e6xxx_vtu_entry vlan = { 1183 .vid = vid_begin - 1, 1184 }; 1185 int i, err; 1186 1187 if (!vid_begin) 1188 return -EOPNOTSUPP; 1189 1190 mutex_lock(&chip->reg_lock); 1191 1192 do { 1193 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1194 if (err) 1195 goto unlock; 1196 1197 if (!vlan.valid) 1198 break; 1199 1200 if (vlan.vid > vid_end) 1201 break; 1202 1203 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1204 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1205 continue; 1206 1207 if (!ds->ports[port].netdev) 1208 continue; 1209 1210 if (vlan.member[i] == 1211 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1212 continue; 1213 1214 if (ds->ports[i].bridge_dev == 1215 ds->ports[port].bridge_dev) 1216 break; /* same bridge, check next VLAN */ 1217 1218 if (!ds->ports[i].bridge_dev) 1219 continue; 1220 1221 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n", 1222 port, vlan.vid, 1223 netdev_name(ds->ports[i].bridge_dev)); 1224 err = -EOPNOTSUPP; 1225 goto unlock; 1226 } 1227 } while (vlan.vid < vid_end); 1228 1229 unlock: 1230 mutex_unlock(&chip->reg_lock); 1231 1232 return err; 1233 } 1234 1235 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1236 bool vlan_filtering) 1237 { 1238 struct mv88e6xxx_chip *chip = ds->priv; 1239 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1240 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1241 int err; 1242 1243 if (!chip->info->max_vid) 1244 return -EOPNOTSUPP; 1245 1246 mutex_lock(&chip->reg_lock); 1247 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1248 mutex_unlock(&chip->reg_lock); 1249 1250 return err; 1251 } 1252 1253 static int 1254 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1255 const struct switchdev_obj_port_vlan *vlan, 1256 struct switchdev_trans *trans) 1257 { 1258 struct mv88e6xxx_chip *chip = ds->priv; 1259 int err; 1260 1261 if (!chip->info->max_vid) 1262 return -EOPNOTSUPP; 1263 1264 /* If the requested port doesn't belong to the same bridge as the VLAN 1265 * members, do not support it (yet) and fallback to software VLAN. 1266 */ 1267 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1268 vlan->vid_end); 1269 if (err) 1270 return err; 1271 1272 /* We don't need any dynamic resource from the kernel (yet), 1273 * so skip the prepare phase. 1274 */ 1275 return 0; 1276 } 1277 1278 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1279 u16 vid, u8 member) 1280 { 1281 struct mv88e6xxx_vtu_entry vlan; 1282 int err; 1283 1284 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1285 if (err) 1286 return err; 1287 1288 vlan.member[port] = member; 1289 1290 return mv88e6xxx_vtu_loadpurge(chip, &vlan); 1291 } 1292 1293 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1294 const struct switchdev_obj_port_vlan *vlan, 1295 struct switchdev_trans *trans) 1296 { 1297 struct mv88e6xxx_chip *chip = ds->priv; 1298 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1299 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1300 u8 member; 1301 u16 vid; 1302 1303 if (!chip->info->max_vid) 1304 return; 1305 1306 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1307 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1308 else if (untagged) 1309 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1310 else 1311 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1312 1313 mutex_lock(&chip->reg_lock); 1314 1315 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1316 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1317 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1318 vid, untagged ? 'u' : 't'); 1319 1320 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1321 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1322 vlan->vid_end); 1323 1324 mutex_unlock(&chip->reg_lock); 1325 } 1326 1327 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1328 int port, u16 vid) 1329 { 1330 struct mv88e6xxx_vtu_entry vlan; 1331 int i, err; 1332 1333 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1334 if (err) 1335 return err; 1336 1337 /* Tell switchdev if this VLAN is handled in software */ 1338 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1339 return -EOPNOTSUPP; 1340 1341 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1342 1343 /* keep the VLAN unless all ports are excluded */ 1344 vlan.valid = false; 1345 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1346 if (vlan.member[i] != 1347 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1348 vlan.valid = true; 1349 break; 1350 } 1351 } 1352 1353 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1354 if (err) 1355 return err; 1356 1357 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1358 } 1359 1360 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1361 const struct switchdev_obj_port_vlan *vlan) 1362 { 1363 struct mv88e6xxx_chip *chip = ds->priv; 1364 u16 pvid, vid; 1365 int err = 0; 1366 1367 if (!chip->info->max_vid) 1368 return -EOPNOTSUPP; 1369 1370 mutex_lock(&chip->reg_lock); 1371 1372 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1373 if (err) 1374 goto unlock; 1375 1376 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1377 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1378 if (err) 1379 goto unlock; 1380 1381 if (vid == pvid) { 1382 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1383 if (err) 1384 goto unlock; 1385 } 1386 } 1387 1388 unlock: 1389 mutex_unlock(&chip->reg_lock); 1390 1391 return err; 1392 } 1393 1394 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1395 const unsigned char *addr, u16 vid, 1396 u8 state) 1397 { 1398 struct mv88e6xxx_vtu_entry vlan; 1399 struct mv88e6xxx_atu_entry entry; 1400 int err; 1401 1402 /* Null VLAN ID corresponds to the port private database */ 1403 if (vid == 0) 1404 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1405 else 1406 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1407 if (err) 1408 return err; 1409 1410 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1411 ether_addr_copy(entry.mac, addr); 1412 eth_addr_dec(entry.mac); 1413 1414 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1415 if (err) 1416 return err; 1417 1418 /* Initialize a fresh ATU entry if it isn't found */ 1419 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1420 !ether_addr_equal(entry.mac, addr)) { 1421 memset(&entry, 0, sizeof(entry)); 1422 ether_addr_copy(entry.mac, addr); 1423 } 1424 1425 /* Purge the ATU entry only if no port is using it anymore */ 1426 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1427 entry.portvec &= ~BIT(port); 1428 if (!entry.portvec) 1429 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1430 } else { 1431 entry.portvec |= BIT(port); 1432 entry.state = state; 1433 } 1434 1435 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1436 } 1437 1438 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 1439 const struct switchdev_obj_port_fdb *fdb, 1440 struct switchdev_trans *trans) 1441 { 1442 /* We don't need any dynamic resource from the kernel (yet), 1443 * so skip the prepare phase. 1444 */ 1445 return 0; 1446 } 1447 1448 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1449 const struct switchdev_obj_port_fdb *fdb, 1450 struct switchdev_trans *trans) 1451 { 1452 struct mv88e6xxx_chip *chip = ds->priv; 1453 1454 mutex_lock(&chip->reg_lock); 1455 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 1456 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC)) 1457 dev_err(ds->dev, "p%d: failed to load unicast MAC address\n", 1458 port); 1459 mutex_unlock(&chip->reg_lock); 1460 } 1461 1462 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1463 const struct switchdev_obj_port_fdb *fdb) 1464 { 1465 struct mv88e6xxx_chip *chip = ds->priv; 1466 int err; 1467 1468 mutex_lock(&chip->reg_lock); 1469 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 1470 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1471 mutex_unlock(&chip->reg_lock); 1472 1473 return err; 1474 } 1475 1476 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1477 u16 fid, u16 vid, int port, 1478 struct switchdev_obj *obj, 1479 switchdev_obj_dump_cb_t *cb) 1480 { 1481 struct mv88e6xxx_atu_entry addr; 1482 int err; 1483 1484 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1485 eth_broadcast_addr(addr.mac); 1486 1487 do { 1488 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1489 if (err) 1490 return err; 1491 1492 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1493 break; 1494 1495 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1496 continue; 1497 1498 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { 1499 struct switchdev_obj_port_fdb *fdb; 1500 1501 if (!is_unicast_ether_addr(addr.mac)) 1502 continue; 1503 1504 fdb = SWITCHDEV_OBJ_PORT_FDB(obj); 1505 fdb->vid = vid; 1506 ether_addr_copy(fdb->addr, addr.mac); 1507 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1508 fdb->ndm_state = NUD_NOARP; 1509 else 1510 fdb->ndm_state = NUD_REACHABLE; 1511 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { 1512 struct switchdev_obj_port_mdb *mdb; 1513 1514 if (!is_multicast_ether_addr(addr.mac)) 1515 continue; 1516 1517 mdb = SWITCHDEV_OBJ_PORT_MDB(obj); 1518 mdb->vid = vid; 1519 ether_addr_copy(mdb->addr, addr.mac); 1520 } else { 1521 return -EOPNOTSUPP; 1522 } 1523 1524 err = cb(obj); 1525 if (err) 1526 return err; 1527 } while (!is_broadcast_ether_addr(addr.mac)); 1528 1529 return err; 1530 } 1531 1532 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1533 struct switchdev_obj *obj, 1534 switchdev_obj_dump_cb_t *cb) 1535 { 1536 struct mv88e6xxx_vtu_entry vlan = { 1537 .vid = chip->info->max_vid, 1538 }; 1539 u16 fid; 1540 int err; 1541 1542 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1543 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1544 if (err) 1545 return err; 1546 1547 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); 1548 if (err) 1549 return err; 1550 1551 /* Dump VLANs' Filtering Information Databases */ 1552 do { 1553 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1554 if (err) 1555 return err; 1556 1557 if (!vlan.valid) 1558 break; 1559 1560 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1561 obj, cb); 1562 if (err) 1563 return err; 1564 } while (vlan.vid < chip->info->max_vid); 1565 1566 return err; 1567 } 1568 1569 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1570 struct switchdev_obj_port_fdb *fdb, 1571 switchdev_obj_dump_cb_t *cb) 1572 { 1573 struct mv88e6xxx_chip *chip = ds->priv; 1574 int err; 1575 1576 mutex_lock(&chip->reg_lock); 1577 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); 1578 mutex_unlock(&chip->reg_lock); 1579 1580 return err; 1581 } 1582 1583 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1584 struct net_device *br) 1585 { 1586 struct dsa_switch *ds; 1587 int port; 1588 int dev; 1589 int err; 1590 1591 /* Remap the Port VLAN of each local bridge group member */ 1592 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1593 if (chip->ds->ports[port].bridge_dev == br) { 1594 err = mv88e6xxx_port_vlan_map(chip, port); 1595 if (err) 1596 return err; 1597 } 1598 } 1599 1600 if (!mv88e6xxx_has_pvt(chip)) 1601 return 0; 1602 1603 /* Remap the Port VLAN of each cross-chip bridge group member */ 1604 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1605 ds = chip->ds->dst->ds[dev]; 1606 if (!ds) 1607 break; 1608 1609 for (port = 0; port < ds->num_ports; ++port) { 1610 if (ds->ports[port].bridge_dev == br) { 1611 err = mv88e6xxx_pvt_map(chip, dev, port); 1612 if (err) 1613 return err; 1614 } 1615 } 1616 } 1617 1618 return 0; 1619 } 1620 1621 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1622 struct net_device *br) 1623 { 1624 struct mv88e6xxx_chip *chip = ds->priv; 1625 int err; 1626 1627 mutex_lock(&chip->reg_lock); 1628 err = mv88e6xxx_bridge_map(chip, br); 1629 mutex_unlock(&chip->reg_lock); 1630 1631 return err; 1632 } 1633 1634 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1635 struct net_device *br) 1636 { 1637 struct mv88e6xxx_chip *chip = ds->priv; 1638 1639 mutex_lock(&chip->reg_lock); 1640 if (mv88e6xxx_bridge_map(chip, br) || 1641 mv88e6xxx_port_vlan_map(chip, port)) 1642 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1643 mutex_unlock(&chip->reg_lock); 1644 } 1645 1646 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1647 int port, struct net_device *br) 1648 { 1649 struct mv88e6xxx_chip *chip = ds->priv; 1650 int err; 1651 1652 if (!mv88e6xxx_has_pvt(chip)) 1653 return 0; 1654 1655 mutex_lock(&chip->reg_lock); 1656 err = mv88e6xxx_pvt_map(chip, dev, port); 1657 mutex_unlock(&chip->reg_lock); 1658 1659 return err; 1660 } 1661 1662 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1663 int port, struct net_device *br) 1664 { 1665 struct mv88e6xxx_chip *chip = ds->priv; 1666 1667 if (!mv88e6xxx_has_pvt(chip)) 1668 return; 1669 1670 mutex_lock(&chip->reg_lock); 1671 if (mv88e6xxx_pvt_map(chip, dev, port)) 1672 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1673 mutex_unlock(&chip->reg_lock); 1674 } 1675 1676 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1677 { 1678 if (chip->info->ops->reset) 1679 return chip->info->ops->reset(chip); 1680 1681 return 0; 1682 } 1683 1684 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1685 { 1686 struct gpio_desc *gpiod = chip->reset; 1687 1688 /* If there is a GPIO connected to the reset pin, toggle it */ 1689 if (gpiod) { 1690 gpiod_set_value_cansleep(gpiod, 1); 1691 usleep_range(10000, 20000); 1692 gpiod_set_value_cansleep(gpiod, 0); 1693 usleep_range(10000, 20000); 1694 } 1695 } 1696 1697 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1698 { 1699 int i, err; 1700 1701 /* Set all ports to the Disabled state */ 1702 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1703 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1704 if (err) 1705 return err; 1706 } 1707 1708 /* Wait for transmit queues to drain, 1709 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1710 */ 1711 usleep_range(2000, 4000); 1712 1713 return 0; 1714 } 1715 1716 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1717 { 1718 int err; 1719 1720 err = mv88e6xxx_disable_ports(chip); 1721 if (err) 1722 return err; 1723 1724 mv88e6xxx_hardware_reset(chip); 1725 1726 return mv88e6xxx_software_reset(chip); 1727 } 1728 1729 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1730 enum mv88e6xxx_frame_mode frame, 1731 enum mv88e6xxx_egress_mode egress, u16 etype) 1732 { 1733 int err; 1734 1735 if (!chip->info->ops->port_set_frame_mode) 1736 return -EOPNOTSUPP; 1737 1738 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1739 if (err) 1740 return err; 1741 1742 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1743 if (err) 1744 return err; 1745 1746 if (chip->info->ops->port_set_ether_type) 1747 return chip->info->ops->port_set_ether_type(chip, port, etype); 1748 1749 return 0; 1750 } 1751 1752 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1753 { 1754 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1755 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1756 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1757 } 1758 1759 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1760 { 1761 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1762 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1763 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1764 } 1765 1766 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1767 { 1768 return mv88e6xxx_set_port_mode(chip, port, 1769 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1770 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1771 ETH_P_EDSA); 1772 } 1773 1774 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1775 { 1776 if (dsa_is_dsa_port(chip->ds, port)) 1777 return mv88e6xxx_set_port_mode_dsa(chip, port); 1778 1779 if (dsa_is_normal_port(chip->ds, port)) 1780 return mv88e6xxx_set_port_mode_normal(chip, port); 1781 1782 /* Setup CPU port mode depending on its supported tag format */ 1783 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1784 return mv88e6xxx_set_port_mode_dsa(chip, port); 1785 1786 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1787 return mv88e6xxx_set_port_mode_edsa(chip, port); 1788 1789 return -EINVAL; 1790 } 1791 1792 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1793 { 1794 bool message = dsa_is_dsa_port(chip->ds, port); 1795 1796 return mv88e6xxx_port_set_message_port(chip, port, message); 1797 } 1798 1799 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1800 { 1801 bool flood = port == dsa_upstream_port(chip->ds); 1802 1803 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1804 if (chip->info->ops->port_set_egress_floods) 1805 return chip->info->ops->port_set_egress_floods(chip, port, 1806 flood, flood); 1807 1808 return 0; 1809 } 1810 1811 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1812 bool on) 1813 { 1814 if (chip->info->ops->serdes_power) 1815 return chip->info->ops->serdes_power(chip, port, on); 1816 1817 return 0; 1818 } 1819 1820 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1821 { 1822 struct dsa_switch *ds = chip->ds; 1823 int err; 1824 u16 reg; 1825 1826 /* MAC Forcing register: don't force link, speed, duplex or flow control 1827 * state to any particular values on physical ports, but force the CPU 1828 * port and all DSA ports to their maximum bandwidth and full duplex. 1829 */ 1830 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1831 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1832 SPEED_MAX, DUPLEX_FULL, 1833 PHY_INTERFACE_MODE_NA); 1834 else 1835 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1836 SPEED_UNFORCED, DUPLEX_UNFORCED, 1837 PHY_INTERFACE_MODE_NA); 1838 if (err) 1839 return err; 1840 1841 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1842 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1843 * tunneling, determine priority by looking at 802.1p and IP 1844 * priority fields (IP prio has precedence), and set STP state 1845 * to Forwarding. 1846 * 1847 * If this is the CPU link, use DSA or EDSA tagging depending 1848 * on which tagging mode was configured. 1849 * 1850 * If this is a link to another switch, use DSA tagging mode. 1851 * 1852 * If this is the upstream port for this switch, enable 1853 * forwarding of unknown unicasts and multicasts. 1854 */ 1855 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1856 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1857 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1858 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1859 if (err) 1860 return err; 1861 1862 err = mv88e6xxx_setup_port_mode(chip, port); 1863 if (err) 1864 return err; 1865 1866 err = mv88e6xxx_setup_egress_floods(chip, port); 1867 if (err) 1868 return err; 1869 1870 /* Enable the SERDES interface for DSA and CPU ports. Normal 1871 * ports SERDES are enabled when the port is enabled, thus 1872 * saving a bit of power. 1873 */ 1874 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1875 err = mv88e6xxx_serdes_power(chip, port, true); 1876 if (err) 1877 return err; 1878 } 1879 1880 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1881 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1882 * untagged frames on this port, do a destination address lookup on all 1883 * received packets as usual, disable ARP mirroring and don't send a 1884 * copy of all transmitted/received frames on this port to the CPU. 1885 */ 1886 err = mv88e6xxx_port_set_map_da(chip, port); 1887 if (err) 1888 return err; 1889 1890 reg = 0; 1891 if (chip->info->ops->port_set_upstream_port) { 1892 err = chip->info->ops->port_set_upstream_port( 1893 chip, port, dsa_upstream_port(ds)); 1894 if (err) 1895 return err; 1896 } 1897 1898 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1899 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1900 if (err) 1901 return err; 1902 1903 if (chip->info->ops->port_set_jumbo_size) { 1904 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1905 if (err) 1906 return err; 1907 } 1908 1909 /* Port Association Vector: when learning source addresses 1910 * of packets, add the address to the address database using 1911 * a port bitmap that has only the bit for this port set and 1912 * the other bits clear. 1913 */ 1914 reg = 1 << port; 1915 /* Disable learning for CPU port */ 1916 if (dsa_is_cpu_port(ds, port)) 1917 reg = 0; 1918 1919 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1920 reg); 1921 if (err) 1922 return err; 1923 1924 /* Egress rate control 2: disable egress rate control. */ 1925 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1926 0x0000); 1927 if (err) 1928 return err; 1929 1930 if (chip->info->ops->port_pause_limit) { 1931 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1932 if (err) 1933 return err; 1934 } 1935 1936 if (chip->info->ops->port_disable_learn_limit) { 1937 err = chip->info->ops->port_disable_learn_limit(chip, port); 1938 if (err) 1939 return err; 1940 } 1941 1942 if (chip->info->ops->port_disable_pri_override) { 1943 err = chip->info->ops->port_disable_pri_override(chip, port); 1944 if (err) 1945 return err; 1946 } 1947 1948 if (chip->info->ops->port_tag_remap) { 1949 err = chip->info->ops->port_tag_remap(chip, port); 1950 if (err) 1951 return err; 1952 } 1953 1954 if (chip->info->ops->port_egress_rate_limiting) { 1955 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1956 if (err) 1957 return err; 1958 } 1959 1960 err = mv88e6xxx_setup_message_port(chip, port); 1961 if (err) 1962 return err; 1963 1964 /* Port based VLAN map: give each port the same default address 1965 * database, and allow bidirectional communication between the 1966 * CPU and DSA port(s), and the other ports. 1967 */ 1968 err = mv88e6xxx_port_set_fid(chip, port, 0); 1969 if (err) 1970 return err; 1971 1972 err = mv88e6xxx_port_vlan_map(chip, port); 1973 if (err) 1974 return err; 1975 1976 /* Default VLAN ID and priority: don't set a default VLAN 1977 * ID, and set the default packet priority to zero. 1978 */ 1979 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 1980 } 1981 1982 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 1983 struct phy_device *phydev) 1984 { 1985 struct mv88e6xxx_chip *chip = ds->priv; 1986 int err; 1987 1988 mutex_lock(&chip->reg_lock); 1989 err = mv88e6xxx_serdes_power(chip, port, true); 1990 mutex_unlock(&chip->reg_lock); 1991 1992 return err; 1993 } 1994 1995 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 1996 struct phy_device *phydev) 1997 { 1998 struct mv88e6xxx_chip *chip = ds->priv; 1999 2000 mutex_lock(&chip->reg_lock); 2001 if (mv88e6xxx_serdes_power(chip, port, false)) 2002 dev_err(chip->dev, "failed to power off SERDES\n"); 2003 mutex_unlock(&chip->reg_lock); 2004 } 2005 2006 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2007 unsigned int ageing_time) 2008 { 2009 struct mv88e6xxx_chip *chip = ds->priv; 2010 int err; 2011 2012 mutex_lock(&chip->reg_lock); 2013 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2014 mutex_unlock(&chip->reg_lock); 2015 2016 return err; 2017 } 2018 2019 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2020 { 2021 struct dsa_switch *ds = chip->ds; 2022 u32 upstream_port = dsa_upstream_port(ds); 2023 int err; 2024 2025 if (chip->info->ops->set_cpu_port) { 2026 err = chip->info->ops->set_cpu_port(chip, upstream_port); 2027 if (err) 2028 return err; 2029 } 2030 2031 if (chip->info->ops->set_egress_port) { 2032 err = chip->info->ops->set_egress_port(chip, upstream_port); 2033 if (err) 2034 return err; 2035 } 2036 2037 /* Disable remote management, and set the switch's DSA device number. */ 2038 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 2039 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 2040 (ds->index & 0x1f)); 2041 if (err) 2042 return err; 2043 2044 /* Configure the IP ToS mapping registers. */ 2045 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 2046 if (err) 2047 return err; 2048 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 2049 if (err) 2050 return err; 2051 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 2052 if (err) 2053 return err; 2054 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 2055 if (err) 2056 return err; 2057 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 2058 if (err) 2059 return err; 2060 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 2061 if (err) 2062 return err; 2063 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 2064 if (err) 2065 return err; 2066 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 2067 if (err) 2068 return err; 2069 2070 /* Configure the IEEE 802.1p priority mapping register. */ 2071 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 2072 if (err) 2073 return err; 2074 2075 /* Initialize the statistics unit */ 2076 err = mv88e6xxx_stats_set_histogram(chip); 2077 if (err) 2078 return err; 2079 2080 /* Clear the statistics counters for all ports */ 2081 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 2082 MV88E6XXX_G1_STATS_OP_BUSY | 2083 MV88E6XXX_G1_STATS_OP_FLUSH_ALL); 2084 if (err) 2085 return err; 2086 2087 /* Wait for the flush to complete. */ 2088 err = mv88e6xxx_g1_stats_wait(chip); 2089 if (err) 2090 return err; 2091 2092 return 0; 2093 } 2094 2095 static int mv88e6xxx_setup(struct dsa_switch *ds) 2096 { 2097 struct mv88e6xxx_chip *chip = ds->priv; 2098 int err; 2099 int i; 2100 2101 chip->ds = ds; 2102 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2103 2104 mutex_lock(&chip->reg_lock); 2105 2106 /* Setup Switch Port Registers */ 2107 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2108 err = mv88e6xxx_setup_port(chip, i); 2109 if (err) 2110 goto unlock; 2111 } 2112 2113 /* Setup Switch Global 1 Registers */ 2114 err = mv88e6xxx_g1_setup(chip); 2115 if (err) 2116 goto unlock; 2117 2118 /* Setup Switch Global 2 Registers */ 2119 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 2120 err = mv88e6xxx_g2_setup(chip); 2121 if (err) 2122 goto unlock; 2123 } 2124 2125 err = mv88e6xxx_irl_setup(chip); 2126 if (err) 2127 goto unlock; 2128 2129 err = mv88e6xxx_phy_setup(chip); 2130 if (err) 2131 goto unlock; 2132 2133 err = mv88e6xxx_vtu_setup(chip); 2134 if (err) 2135 goto unlock; 2136 2137 err = mv88e6xxx_pvt_setup(chip); 2138 if (err) 2139 goto unlock; 2140 2141 err = mv88e6xxx_atu_setup(chip); 2142 if (err) 2143 goto unlock; 2144 2145 /* Some generations have the configuration of sending reserved 2146 * management frames to the CPU in global2, others in 2147 * global1. Hence it does not fit the two setup functions 2148 * above. 2149 */ 2150 if (chip->info->ops->mgmt_rsvd2cpu) { 2151 err = chip->info->ops->mgmt_rsvd2cpu(chip); 2152 if (err) 2153 goto unlock; 2154 } 2155 2156 unlock: 2157 mutex_unlock(&chip->reg_lock); 2158 2159 return err; 2160 } 2161 2162 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2163 { 2164 struct mv88e6xxx_chip *chip = ds->priv; 2165 int err; 2166 2167 if (!chip->info->ops->set_switch_mac) 2168 return -EOPNOTSUPP; 2169 2170 mutex_lock(&chip->reg_lock); 2171 err = chip->info->ops->set_switch_mac(chip, addr); 2172 mutex_unlock(&chip->reg_lock); 2173 2174 return err; 2175 } 2176 2177 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2178 { 2179 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2180 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2181 u16 val; 2182 int err; 2183 2184 if (!chip->info->ops->phy_read) 2185 return -EOPNOTSUPP; 2186 2187 mutex_lock(&chip->reg_lock); 2188 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2189 mutex_unlock(&chip->reg_lock); 2190 2191 if (reg == MII_PHYSID2) { 2192 /* Some internal PHYS don't have a model number. Use 2193 * the mv88e6390 family model number instead. 2194 */ 2195 if (!(val & 0x3f0)) 2196 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2197 } 2198 2199 return err ? err : val; 2200 } 2201 2202 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2203 { 2204 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2205 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2206 int err; 2207 2208 if (!chip->info->ops->phy_write) 2209 return -EOPNOTSUPP; 2210 2211 mutex_lock(&chip->reg_lock); 2212 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2213 mutex_unlock(&chip->reg_lock); 2214 2215 return err; 2216 } 2217 2218 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2219 struct device_node *np, 2220 bool external) 2221 { 2222 static int index; 2223 struct mv88e6xxx_mdio_bus *mdio_bus; 2224 struct mii_bus *bus; 2225 int err; 2226 2227 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2228 if (!bus) 2229 return -ENOMEM; 2230 2231 mdio_bus = bus->priv; 2232 mdio_bus->bus = bus; 2233 mdio_bus->chip = chip; 2234 INIT_LIST_HEAD(&mdio_bus->list); 2235 mdio_bus->external = external; 2236 2237 if (np) { 2238 bus->name = np->full_name; 2239 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 2240 } else { 2241 bus->name = "mv88e6xxx SMI"; 2242 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2243 } 2244 2245 bus->read = mv88e6xxx_mdio_read; 2246 bus->write = mv88e6xxx_mdio_write; 2247 bus->parent = chip->dev; 2248 2249 if (np) 2250 err = of_mdiobus_register(bus, np); 2251 else 2252 err = mdiobus_register(bus); 2253 if (err) { 2254 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2255 return err; 2256 } 2257 2258 if (external) 2259 list_add_tail(&mdio_bus->list, &chip->mdios); 2260 else 2261 list_add(&mdio_bus->list, &chip->mdios); 2262 2263 return 0; 2264 } 2265 2266 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2267 { .compatible = "marvell,mv88e6xxx-mdio-external", 2268 .data = (void *)true }, 2269 { }, 2270 }; 2271 2272 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2273 struct device_node *np) 2274 { 2275 const struct of_device_id *match; 2276 struct device_node *child; 2277 int err; 2278 2279 /* Always register one mdio bus for the internal/default mdio 2280 * bus. This maybe represented in the device tree, but is 2281 * optional. 2282 */ 2283 child = of_get_child_by_name(np, "mdio"); 2284 err = mv88e6xxx_mdio_register(chip, child, false); 2285 if (err) 2286 return err; 2287 2288 /* Walk the device tree, and see if there are any other nodes 2289 * which say they are compatible with the external mdio 2290 * bus. 2291 */ 2292 for_each_available_child_of_node(np, child) { 2293 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2294 if (match) { 2295 err = mv88e6xxx_mdio_register(chip, child, true); 2296 if (err) 2297 return err; 2298 } 2299 } 2300 2301 return 0; 2302 } 2303 2304 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2305 2306 { 2307 struct mv88e6xxx_mdio_bus *mdio_bus; 2308 struct mii_bus *bus; 2309 2310 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2311 bus = mdio_bus->bus; 2312 2313 mdiobus_unregister(bus); 2314 } 2315 } 2316 2317 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2318 { 2319 struct mv88e6xxx_chip *chip = ds->priv; 2320 2321 return chip->eeprom_len; 2322 } 2323 2324 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2325 struct ethtool_eeprom *eeprom, u8 *data) 2326 { 2327 struct mv88e6xxx_chip *chip = ds->priv; 2328 int err; 2329 2330 if (!chip->info->ops->get_eeprom) 2331 return -EOPNOTSUPP; 2332 2333 mutex_lock(&chip->reg_lock); 2334 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2335 mutex_unlock(&chip->reg_lock); 2336 2337 if (err) 2338 return err; 2339 2340 eeprom->magic = 0xc3ec4951; 2341 2342 return 0; 2343 } 2344 2345 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2346 struct ethtool_eeprom *eeprom, u8 *data) 2347 { 2348 struct mv88e6xxx_chip *chip = ds->priv; 2349 int err; 2350 2351 if (!chip->info->ops->set_eeprom) 2352 return -EOPNOTSUPP; 2353 2354 if (eeprom->magic != 0xc3ec4951) 2355 return -EINVAL; 2356 2357 mutex_lock(&chip->reg_lock); 2358 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2359 mutex_unlock(&chip->reg_lock); 2360 2361 return err; 2362 } 2363 2364 static const struct mv88e6xxx_ops mv88e6085_ops = { 2365 /* MV88E6XXX_FAMILY_6097 */ 2366 .irl_init_all = mv88e6352_g2_irl_init_all, 2367 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2368 .phy_read = mv88e6185_phy_ppu_read, 2369 .phy_write = mv88e6185_phy_ppu_write, 2370 .port_set_link = mv88e6xxx_port_set_link, 2371 .port_set_duplex = mv88e6xxx_port_set_duplex, 2372 .port_set_speed = mv88e6185_port_set_speed, 2373 .port_tag_remap = mv88e6095_port_tag_remap, 2374 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2375 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2376 .port_set_ether_type = mv88e6351_port_set_ether_type, 2377 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2378 .port_pause_limit = mv88e6097_port_pause_limit, 2379 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2380 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2381 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2382 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2383 .stats_get_strings = mv88e6095_stats_get_strings, 2384 .stats_get_stats = mv88e6095_stats_get_stats, 2385 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2386 .set_egress_port = mv88e6095_g1_set_egress_port, 2387 .watchdog_ops = &mv88e6097_watchdog_ops, 2388 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2389 .ppu_enable = mv88e6185_g1_ppu_enable, 2390 .ppu_disable = mv88e6185_g1_ppu_disable, 2391 .reset = mv88e6185_g1_reset, 2392 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2393 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2394 }; 2395 2396 static const struct mv88e6xxx_ops mv88e6095_ops = { 2397 /* MV88E6XXX_FAMILY_6095 */ 2398 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2399 .phy_read = mv88e6185_phy_ppu_read, 2400 .phy_write = mv88e6185_phy_ppu_write, 2401 .port_set_link = mv88e6xxx_port_set_link, 2402 .port_set_duplex = mv88e6xxx_port_set_duplex, 2403 .port_set_speed = mv88e6185_port_set_speed, 2404 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2405 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2406 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2407 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2408 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2409 .stats_get_strings = mv88e6095_stats_get_strings, 2410 .stats_get_stats = mv88e6095_stats_get_stats, 2411 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2412 .ppu_enable = mv88e6185_g1_ppu_enable, 2413 .ppu_disable = mv88e6185_g1_ppu_disable, 2414 .reset = mv88e6185_g1_reset, 2415 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2416 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2417 }; 2418 2419 static const struct mv88e6xxx_ops mv88e6097_ops = { 2420 /* MV88E6XXX_FAMILY_6097 */ 2421 .irl_init_all = mv88e6352_g2_irl_init_all, 2422 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2423 .phy_read = mv88e6xxx_g2_smi_phy_read, 2424 .phy_write = mv88e6xxx_g2_smi_phy_write, 2425 .port_set_link = mv88e6xxx_port_set_link, 2426 .port_set_duplex = mv88e6xxx_port_set_duplex, 2427 .port_set_speed = mv88e6185_port_set_speed, 2428 .port_tag_remap = mv88e6095_port_tag_remap, 2429 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2430 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2431 .port_set_ether_type = mv88e6351_port_set_ether_type, 2432 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2433 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2434 .port_pause_limit = mv88e6097_port_pause_limit, 2435 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2436 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2437 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2438 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2439 .stats_get_strings = mv88e6095_stats_get_strings, 2440 .stats_get_stats = mv88e6095_stats_get_stats, 2441 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2442 .set_egress_port = mv88e6095_g1_set_egress_port, 2443 .watchdog_ops = &mv88e6097_watchdog_ops, 2444 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2445 .reset = mv88e6352_g1_reset, 2446 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2447 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2448 }; 2449 2450 static const struct mv88e6xxx_ops mv88e6123_ops = { 2451 /* MV88E6XXX_FAMILY_6165 */ 2452 .irl_init_all = mv88e6352_g2_irl_init_all, 2453 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2454 .phy_read = mv88e6xxx_g2_smi_phy_read, 2455 .phy_write = mv88e6xxx_g2_smi_phy_write, 2456 .port_set_link = mv88e6xxx_port_set_link, 2457 .port_set_duplex = mv88e6xxx_port_set_duplex, 2458 .port_set_speed = mv88e6185_port_set_speed, 2459 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2460 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2463 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2464 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2465 .stats_get_strings = mv88e6095_stats_get_strings, 2466 .stats_get_stats = mv88e6095_stats_get_stats, 2467 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2468 .set_egress_port = mv88e6095_g1_set_egress_port, 2469 .watchdog_ops = &mv88e6097_watchdog_ops, 2470 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2471 .reset = mv88e6352_g1_reset, 2472 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2473 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2474 }; 2475 2476 static const struct mv88e6xxx_ops mv88e6131_ops = { 2477 /* MV88E6XXX_FAMILY_6185 */ 2478 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2479 .phy_read = mv88e6185_phy_ppu_read, 2480 .phy_write = mv88e6185_phy_ppu_write, 2481 .port_set_link = mv88e6xxx_port_set_link, 2482 .port_set_duplex = mv88e6xxx_port_set_duplex, 2483 .port_set_speed = mv88e6185_port_set_speed, 2484 .port_tag_remap = mv88e6095_port_tag_remap, 2485 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2486 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2487 .port_set_ether_type = mv88e6351_port_set_ether_type, 2488 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2489 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2490 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2491 .port_pause_limit = mv88e6097_port_pause_limit, 2492 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2493 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2494 .stats_get_strings = mv88e6095_stats_get_strings, 2495 .stats_get_stats = mv88e6095_stats_get_stats, 2496 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2497 .set_egress_port = mv88e6095_g1_set_egress_port, 2498 .watchdog_ops = &mv88e6097_watchdog_ops, 2499 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2500 .ppu_enable = mv88e6185_g1_ppu_enable, 2501 .ppu_disable = mv88e6185_g1_ppu_disable, 2502 .reset = mv88e6185_g1_reset, 2503 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2504 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2505 }; 2506 2507 static const struct mv88e6xxx_ops mv88e6141_ops = { 2508 /* MV88E6XXX_FAMILY_6341 */ 2509 .irl_init_all = mv88e6352_g2_irl_init_all, 2510 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2511 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2512 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2513 .phy_read = mv88e6xxx_g2_smi_phy_read, 2514 .phy_write = mv88e6xxx_g2_smi_phy_write, 2515 .port_set_link = mv88e6xxx_port_set_link, 2516 .port_set_duplex = mv88e6xxx_port_set_duplex, 2517 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2518 .port_set_speed = mv88e6390_port_set_speed, 2519 .port_tag_remap = mv88e6095_port_tag_remap, 2520 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2521 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2522 .port_set_ether_type = mv88e6351_port_set_ether_type, 2523 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2524 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2525 .port_pause_limit = mv88e6097_port_pause_limit, 2526 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2527 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2528 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2529 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2530 .stats_get_strings = mv88e6320_stats_get_strings, 2531 .stats_get_stats = mv88e6390_stats_get_stats, 2532 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2533 .set_egress_port = mv88e6390_g1_set_egress_port, 2534 .watchdog_ops = &mv88e6390_watchdog_ops, 2535 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2536 .reset = mv88e6352_g1_reset, 2537 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2538 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2539 }; 2540 2541 static const struct mv88e6xxx_ops mv88e6161_ops = { 2542 /* MV88E6XXX_FAMILY_6165 */ 2543 .irl_init_all = mv88e6352_g2_irl_init_all, 2544 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2545 .phy_read = mv88e6xxx_g2_smi_phy_read, 2546 .phy_write = mv88e6xxx_g2_smi_phy_write, 2547 .port_set_link = mv88e6xxx_port_set_link, 2548 .port_set_duplex = mv88e6xxx_port_set_duplex, 2549 .port_set_speed = mv88e6185_port_set_speed, 2550 .port_tag_remap = mv88e6095_port_tag_remap, 2551 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2552 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2553 .port_set_ether_type = mv88e6351_port_set_ether_type, 2554 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2555 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2556 .port_pause_limit = mv88e6097_port_pause_limit, 2557 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2558 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2559 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2560 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2561 .stats_get_strings = mv88e6095_stats_get_strings, 2562 .stats_get_stats = mv88e6095_stats_get_stats, 2563 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2564 .set_egress_port = mv88e6095_g1_set_egress_port, 2565 .watchdog_ops = &mv88e6097_watchdog_ops, 2566 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2567 .reset = mv88e6352_g1_reset, 2568 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2569 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2570 }; 2571 2572 static const struct mv88e6xxx_ops mv88e6165_ops = { 2573 /* MV88E6XXX_FAMILY_6165 */ 2574 .irl_init_all = mv88e6352_g2_irl_init_all, 2575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2576 .phy_read = mv88e6165_phy_read, 2577 .phy_write = mv88e6165_phy_write, 2578 .port_set_link = mv88e6xxx_port_set_link, 2579 .port_set_duplex = mv88e6xxx_port_set_duplex, 2580 .port_set_speed = mv88e6185_port_set_speed, 2581 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2582 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2583 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2584 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2585 .stats_get_strings = mv88e6095_stats_get_strings, 2586 .stats_get_stats = mv88e6095_stats_get_stats, 2587 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2588 .set_egress_port = mv88e6095_g1_set_egress_port, 2589 .watchdog_ops = &mv88e6097_watchdog_ops, 2590 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2591 .reset = mv88e6352_g1_reset, 2592 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2593 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2594 }; 2595 2596 static const struct mv88e6xxx_ops mv88e6171_ops = { 2597 /* MV88E6XXX_FAMILY_6351 */ 2598 .irl_init_all = mv88e6352_g2_irl_init_all, 2599 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2600 .phy_read = mv88e6xxx_g2_smi_phy_read, 2601 .phy_write = mv88e6xxx_g2_smi_phy_write, 2602 .port_set_link = mv88e6xxx_port_set_link, 2603 .port_set_duplex = mv88e6xxx_port_set_duplex, 2604 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2605 .port_set_speed = mv88e6185_port_set_speed, 2606 .port_tag_remap = mv88e6095_port_tag_remap, 2607 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2608 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2609 .port_set_ether_type = mv88e6351_port_set_ether_type, 2610 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2611 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2612 .port_pause_limit = mv88e6097_port_pause_limit, 2613 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2614 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2615 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2616 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2617 .stats_get_strings = mv88e6095_stats_get_strings, 2618 .stats_get_stats = mv88e6095_stats_get_stats, 2619 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2620 .set_egress_port = mv88e6095_g1_set_egress_port, 2621 .watchdog_ops = &mv88e6097_watchdog_ops, 2622 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2623 .reset = mv88e6352_g1_reset, 2624 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2625 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2626 }; 2627 2628 static const struct mv88e6xxx_ops mv88e6172_ops = { 2629 /* MV88E6XXX_FAMILY_6352 */ 2630 .irl_init_all = mv88e6352_g2_irl_init_all, 2631 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2632 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2634 .phy_read = mv88e6xxx_g2_smi_phy_read, 2635 .phy_write = mv88e6xxx_g2_smi_phy_write, 2636 .port_set_link = mv88e6xxx_port_set_link, 2637 .port_set_duplex = mv88e6xxx_port_set_duplex, 2638 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2639 .port_set_speed = mv88e6352_port_set_speed, 2640 .port_tag_remap = mv88e6095_port_tag_remap, 2641 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2642 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2643 .port_set_ether_type = mv88e6351_port_set_ether_type, 2644 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2645 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2646 .port_pause_limit = mv88e6097_port_pause_limit, 2647 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2648 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2649 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2650 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2651 .stats_get_strings = mv88e6095_stats_get_strings, 2652 .stats_get_stats = mv88e6095_stats_get_stats, 2653 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2654 .set_egress_port = mv88e6095_g1_set_egress_port, 2655 .watchdog_ops = &mv88e6097_watchdog_ops, 2656 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2657 .reset = mv88e6352_g1_reset, 2658 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2659 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2660 .serdes_power = mv88e6352_serdes_power, 2661 }; 2662 2663 static const struct mv88e6xxx_ops mv88e6175_ops = { 2664 /* MV88E6XXX_FAMILY_6351 */ 2665 .irl_init_all = mv88e6352_g2_irl_init_all, 2666 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2667 .phy_read = mv88e6xxx_g2_smi_phy_read, 2668 .phy_write = mv88e6xxx_g2_smi_phy_write, 2669 .port_set_link = mv88e6xxx_port_set_link, 2670 .port_set_duplex = mv88e6xxx_port_set_duplex, 2671 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2672 .port_set_speed = mv88e6185_port_set_speed, 2673 .port_tag_remap = mv88e6095_port_tag_remap, 2674 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2675 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2676 .port_set_ether_type = mv88e6351_port_set_ether_type, 2677 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2678 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2679 .port_pause_limit = mv88e6097_port_pause_limit, 2680 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2681 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2682 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2683 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2684 .stats_get_strings = mv88e6095_stats_get_strings, 2685 .stats_get_stats = mv88e6095_stats_get_stats, 2686 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2687 .set_egress_port = mv88e6095_g1_set_egress_port, 2688 .watchdog_ops = &mv88e6097_watchdog_ops, 2689 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2690 .reset = mv88e6352_g1_reset, 2691 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2692 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2693 }; 2694 2695 static const struct mv88e6xxx_ops mv88e6176_ops = { 2696 /* MV88E6XXX_FAMILY_6352 */ 2697 .irl_init_all = mv88e6352_g2_irl_init_all, 2698 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2699 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2700 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2701 .phy_read = mv88e6xxx_g2_smi_phy_read, 2702 .phy_write = mv88e6xxx_g2_smi_phy_write, 2703 .port_set_link = mv88e6xxx_port_set_link, 2704 .port_set_duplex = mv88e6xxx_port_set_duplex, 2705 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2706 .port_set_speed = mv88e6352_port_set_speed, 2707 .port_tag_remap = mv88e6095_port_tag_remap, 2708 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2709 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2710 .port_set_ether_type = mv88e6351_port_set_ether_type, 2711 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2712 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2713 .port_pause_limit = mv88e6097_port_pause_limit, 2714 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2715 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2716 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2717 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2718 .stats_get_strings = mv88e6095_stats_get_strings, 2719 .stats_get_stats = mv88e6095_stats_get_stats, 2720 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2721 .set_egress_port = mv88e6095_g1_set_egress_port, 2722 .watchdog_ops = &mv88e6097_watchdog_ops, 2723 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2724 .reset = mv88e6352_g1_reset, 2725 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2726 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2727 .serdes_power = mv88e6352_serdes_power, 2728 }; 2729 2730 static const struct mv88e6xxx_ops mv88e6185_ops = { 2731 /* MV88E6XXX_FAMILY_6185 */ 2732 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2733 .phy_read = mv88e6185_phy_ppu_read, 2734 .phy_write = mv88e6185_phy_ppu_write, 2735 .port_set_link = mv88e6xxx_port_set_link, 2736 .port_set_duplex = mv88e6xxx_port_set_duplex, 2737 .port_set_speed = mv88e6185_port_set_speed, 2738 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2739 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2740 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2741 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2742 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2743 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2744 .stats_get_strings = mv88e6095_stats_get_strings, 2745 .stats_get_stats = mv88e6095_stats_get_stats, 2746 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2747 .set_egress_port = mv88e6095_g1_set_egress_port, 2748 .watchdog_ops = &mv88e6097_watchdog_ops, 2749 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2750 .ppu_enable = mv88e6185_g1_ppu_enable, 2751 .ppu_disable = mv88e6185_g1_ppu_disable, 2752 .reset = mv88e6185_g1_reset, 2753 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2754 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2755 }; 2756 2757 static const struct mv88e6xxx_ops mv88e6190_ops = { 2758 /* MV88E6XXX_FAMILY_6390 */ 2759 .irl_init_all = mv88e6390_g2_irl_init_all, 2760 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2761 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2762 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2763 .phy_read = mv88e6xxx_g2_smi_phy_read, 2764 .phy_write = mv88e6xxx_g2_smi_phy_write, 2765 .port_set_link = mv88e6xxx_port_set_link, 2766 .port_set_duplex = mv88e6xxx_port_set_duplex, 2767 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2768 .port_set_speed = mv88e6390_port_set_speed, 2769 .port_tag_remap = mv88e6390_port_tag_remap, 2770 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2771 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2772 .port_set_ether_type = mv88e6351_port_set_ether_type, 2773 .port_pause_limit = mv88e6390_port_pause_limit, 2774 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2775 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2776 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2777 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2778 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2779 .stats_get_strings = mv88e6320_stats_get_strings, 2780 .stats_get_stats = mv88e6390_stats_get_stats, 2781 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2782 .set_egress_port = mv88e6390_g1_set_egress_port, 2783 .watchdog_ops = &mv88e6390_watchdog_ops, 2784 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2785 .reset = mv88e6352_g1_reset, 2786 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2787 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2788 .serdes_power = mv88e6390_serdes_power, 2789 }; 2790 2791 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2792 /* MV88E6XXX_FAMILY_6390 */ 2793 .irl_init_all = mv88e6390_g2_irl_init_all, 2794 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2795 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2796 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2797 .phy_read = mv88e6xxx_g2_smi_phy_read, 2798 .phy_write = mv88e6xxx_g2_smi_phy_write, 2799 .port_set_link = mv88e6xxx_port_set_link, 2800 .port_set_duplex = mv88e6xxx_port_set_duplex, 2801 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2802 .port_set_speed = mv88e6390x_port_set_speed, 2803 .port_tag_remap = mv88e6390_port_tag_remap, 2804 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2805 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2806 .port_set_ether_type = mv88e6351_port_set_ether_type, 2807 .port_pause_limit = mv88e6390_port_pause_limit, 2808 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2809 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2810 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2811 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2812 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2813 .stats_get_strings = mv88e6320_stats_get_strings, 2814 .stats_get_stats = mv88e6390_stats_get_stats, 2815 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2816 .set_egress_port = mv88e6390_g1_set_egress_port, 2817 .watchdog_ops = &mv88e6390_watchdog_ops, 2818 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2819 .reset = mv88e6352_g1_reset, 2820 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2821 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2822 .serdes_power = mv88e6390_serdes_power, 2823 }; 2824 2825 static const struct mv88e6xxx_ops mv88e6191_ops = { 2826 /* MV88E6XXX_FAMILY_6390 */ 2827 .irl_init_all = mv88e6390_g2_irl_init_all, 2828 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2829 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2830 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2831 .phy_read = mv88e6xxx_g2_smi_phy_read, 2832 .phy_write = mv88e6xxx_g2_smi_phy_write, 2833 .port_set_link = mv88e6xxx_port_set_link, 2834 .port_set_duplex = mv88e6xxx_port_set_duplex, 2835 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2836 .port_set_speed = mv88e6390_port_set_speed, 2837 .port_tag_remap = mv88e6390_port_tag_remap, 2838 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2839 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2840 .port_set_ether_type = mv88e6351_port_set_ether_type, 2841 .port_pause_limit = mv88e6390_port_pause_limit, 2842 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2843 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2844 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2845 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2846 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2847 .stats_get_strings = mv88e6320_stats_get_strings, 2848 .stats_get_stats = mv88e6390_stats_get_stats, 2849 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2850 .set_egress_port = mv88e6390_g1_set_egress_port, 2851 .watchdog_ops = &mv88e6390_watchdog_ops, 2852 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2853 .reset = mv88e6352_g1_reset, 2854 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2855 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2856 .serdes_power = mv88e6390_serdes_power, 2857 }; 2858 2859 static const struct mv88e6xxx_ops mv88e6240_ops = { 2860 /* MV88E6XXX_FAMILY_6352 */ 2861 .irl_init_all = mv88e6352_g2_irl_init_all, 2862 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2863 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2864 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2865 .phy_read = mv88e6xxx_g2_smi_phy_read, 2866 .phy_write = mv88e6xxx_g2_smi_phy_write, 2867 .port_set_link = mv88e6xxx_port_set_link, 2868 .port_set_duplex = mv88e6xxx_port_set_duplex, 2869 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2870 .port_set_speed = mv88e6352_port_set_speed, 2871 .port_tag_remap = mv88e6095_port_tag_remap, 2872 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2873 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2874 .port_set_ether_type = mv88e6351_port_set_ether_type, 2875 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2876 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2877 .port_pause_limit = mv88e6097_port_pause_limit, 2878 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2879 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2880 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2881 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2882 .stats_get_strings = mv88e6095_stats_get_strings, 2883 .stats_get_stats = mv88e6095_stats_get_stats, 2884 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2885 .set_egress_port = mv88e6095_g1_set_egress_port, 2886 .watchdog_ops = &mv88e6097_watchdog_ops, 2887 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2888 .reset = mv88e6352_g1_reset, 2889 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2890 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2891 .serdes_power = mv88e6352_serdes_power, 2892 }; 2893 2894 static const struct mv88e6xxx_ops mv88e6290_ops = { 2895 /* MV88E6XXX_FAMILY_6390 */ 2896 .irl_init_all = mv88e6390_g2_irl_init_all, 2897 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2898 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2899 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2900 .phy_read = mv88e6xxx_g2_smi_phy_read, 2901 .phy_write = mv88e6xxx_g2_smi_phy_write, 2902 .port_set_link = mv88e6xxx_port_set_link, 2903 .port_set_duplex = mv88e6xxx_port_set_duplex, 2904 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2905 .port_set_speed = mv88e6390_port_set_speed, 2906 .port_tag_remap = mv88e6390_port_tag_remap, 2907 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2908 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2909 .port_set_ether_type = mv88e6351_port_set_ether_type, 2910 .port_pause_limit = mv88e6390_port_pause_limit, 2911 .port_set_cmode = mv88e6390x_port_set_cmode, 2912 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2913 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2914 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2915 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2916 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2917 .stats_get_strings = mv88e6320_stats_get_strings, 2918 .stats_get_stats = mv88e6390_stats_get_stats, 2919 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2920 .set_egress_port = mv88e6390_g1_set_egress_port, 2921 .watchdog_ops = &mv88e6390_watchdog_ops, 2922 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2923 .reset = mv88e6352_g1_reset, 2924 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2925 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2926 .serdes_power = mv88e6390_serdes_power, 2927 }; 2928 2929 static const struct mv88e6xxx_ops mv88e6320_ops = { 2930 /* MV88E6XXX_FAMILY_6320 */ 2931 .irl_init_all = mv88e6352_g2_irl_init_all, 2932 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2933 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2934 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2935 .phy_read = mv88e6xxx_g2_smi_phy_read, 2936 .phy_write = mv88e6xxx_g2_smi_phy_write, 2937 .port_set_link = mv88e6xxx_port_set_link, 2938 .port_set_duplex = mv88e6xxx_port_set_duplex, 2939 .port_set_speed = mv88e6185_port_set_speed, 2940 .port_tag_remap = mv88e6095_port_tag_remap, 2941 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2942 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2943 .port_set_ether_type = mv88e6351_port_set_ether_type, 2944 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2945 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2946 .port_pause_limit = mv88e6097_port_pause_limit, 2947 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2948 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2949 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2950 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2951 .stats_get_strings = mv88e6320_stats_get_strings, 2952 .stats_get_stats = mv88e6320_stats_get_stats, 2953 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2954 .set_egress_port = mv88e6095_g1_set_egress_port, 2955 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 2956 .reset = mv88e6352_g1_reset, 2957 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2958 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2959 }; 2960 2961 static const struct mv88e6xxx_ops mv88e6321_ops = { 2962 /* MV88E6XXX_FAMILY_6321 */ 2963 .irl_init_all = mv88e6352_g2_irl_init_all, 2964 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2965 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2966 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2967 .phy_read = mv88e6xxx_g2_smi_phy_read, 2968 .phy_write = mv88e6xxx_g2_smi_phy_write, 2969 .port_set_link = mv88e6xxx_port_set_link, 2970 .port_set_duplex = mv88e6xxx_port_set_duplex, 2971 .port_set_speed = mv88e6185_port_set_speed, 2972 .port_tag_remap = mv88e6095_port_tag_remap, 2973 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2974 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2975 .port_set_ether_type = mv88e6351_port_set_ether_type, 2976 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2977 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2978 .port_pause_limit = mv88e6097_port_pause_limit, 2979 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2980 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2981 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2982 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2983 .stats_get_strings = mv88e6320_stats_get_strings, 2984 .stats_get_stats = mv88e6320_stats_get_stats, 2985 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2986 .set_egress_port = mv88e6095_g1_set_egress_port, 2987 .reset = mv88e6352_g1_reset, 2988 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2989 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2990 }; 2991 2992 static const struct mv88e6xxx_ops mv88e6341_ops = { 2993 /* MV88E6XXX_FAMILY_6341 */ 2994 .irl_init_all = mv88e6352_g2_irl_init_all, 2995 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2996 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2997 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2998 .phy_read = mv88e6xxx_g2_smi_phy_read, 2999 .phy_write = mv88e6xxx_g2_smi_phy_write, 3000 .port_set_link = mv88e6xxx_port_set_link, 3001 .port_set_duplex = mv88e6xxx_port_set_duplex, 3002 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3003 .port_set_speed = mv88e6390_port_set_speed, 3004 .port_tag_remap = mv88e6095_port_tag_remap, 3005 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3006 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3007 .port_set_ether_type = mv88e6351_port_set_ether_type, 3008 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3009 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3010 .port_pause_limit = mv88e6097_port_pause_limit, 3011 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3012 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3013 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3014 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3015 .stats_get_strings = mv88e6320_stats_get_strings, 3016 .stats_get_stats = mv88e6390_stats_get_stats, 3017 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3018 .set_egress_port = mv88e6390_g1_set_egress_port, 3019 .watchdog_ops = &mv88e6390_watchdog_ops, 3020 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3021 .reset = mv88e6352_g1_reset, 3022 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3023 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3024 }; 3025 3026 static const struct mv88e6xxx_ops mv88e6350_ops = { 3027 /* MV88E6XXX_FAMILY_6351 */ 3028 .irl_init_all = mv88e6352_g2_irl_init_all, 3029 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3030 .phy_read = mv88e6xxx_g2_smi_phy_read, 3031 .phy_write = mv88e6xxx_g2_smi_phy_write, 3032 .port_set_link = mv88e6xxx_port_set_link, 3033 .port_set_duplex = mv88e6xxx_port_set_duplex, 3034 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3035 .port_set_speed = mv88e6185_port_set_speed, 3036 .port_tag_remap = mv88e6095_port_tag_remap, 3037 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3038 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3039 .port_set_ether_type = mv88e6351_port_set_ether_type, 3040 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3041 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3042 .port_pause_limit = mv88e6097_port_pause_limit, 3043 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3044 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3045 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3046 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3047 .stats_get_strings = mv88e6095_stats_get_strings, 3048 .stats_get_stats = mv88e6095_stats_get_stats, 3049 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3050 .set_egress_port = mv88e6095_g1_set_egress_port, 3051 .watchdog_ops = &mv88e6097_watchdog_ops, 3052 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3053 .reset = mv88e6352_g1_reset, 3054 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3055 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3056 }; 3057 3058 static const struct mv88e6xxx_ops mv88e6351_ops = { 3059 /* MV88E6XXX_FAMILY_6351 */ 3060 .irl_init_all = mv88e6352_g2_irl_init_all, 3061 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3062 .phy_read = mv88e6xxx_g2_smi_phy_read, 3063 .phy_write = mv88e6xxx_g2_smi_phy_write, 3064 .port_set_link = mv88e6xxx_port_set_link, 3065 .port_set_duplex = mv88e6xxx_port_set_duplex, 3066 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3067 .port_set_speed = mv88e6185_port_set_speed, 3068 .port_tag_remap = mv88e6095_port_tag_remap, 3069 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3070 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3071 .port_set_ether_type = mv88e6351_port_set_ether_type, 3072 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3073 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3074 .port_pause_limit = mv88e6097_port_pause_limit, 3075 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3076 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3077 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3078 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3079 .stats_get_strings = mv88e6095_stats_get_strings, 3080 .stats_get_stats = mv88e6095_stats_get_stats, 3081 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3082 .set_egress_port = mv88e6095_g1_set_egress_port, 3083 .watchdog_ops = &mv88e6097_watchdog_ops, 3084 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3085 .reset = mv88e6352_g1_reset, 3086 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3087 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3088 }; 3089 3090 static const struct mv88e6xxx_ops mv88e6352_ops = { 3091 /* MV88E6XXX_FAMILY_6352 */ 3092 .irl_init_all = mv88e6352_g2_irl_init_all, 3093 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3094 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3095 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3096 .phy_read = mv88e6xxx_g2_smi_phy_read, 3097 .phy_write = mv88e6xxx_g2_smi_phy_write, 3098 .port_set_link = mv88e6xxx_port_set_link, 3099 .port_set_duplex = mv88e6xxx_port_set_duplex, 3100 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3101 .port_set_speed = mv88e6352_port_set_speed, 3102 .port_tag_remap = mv88e6095_port_tag_remap, 3103 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3104 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3105 .port_set_ether_type = mv88e6351_port_set_ether_type, 3106 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3107 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3108 .port_pause_limit = mv88e6097_port_pause_limit, 3109 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3110 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3111 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3112 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3113 .stats_get_strings = mv88e6095_stats_get_strings, 3114 .stats_get_stats = mv88e6095_stats_get_stats, 3115 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3116 .set_egress_port = mv88e6095_g1_set_egress_port, 3117 .watchdog_ops = &mv88e6097_watchdog_ops, 3118 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3119 .reset = mv88e6352_g1_reset, 3120 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3121 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3122 .serdes_power = mv88e6352_serdes_power, 3123 }; 3124 3125 static const struct mv88e6xxx_ops mv88e6390_ops = { 3126 /* MV88E6XXX_FAMILY_6390 */ 3127 .irl_init_all = mv88e6390_g2_irl_init_all, 3128 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3129 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3130 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3131 .phy_read = mv88e6xxx_g2_smi_phy_read, 3132 .phy_write = mv88e6xxx_g2_smi_phy_write, 3133 .port_set_link = mv88e6xxx_port_set_link, 3134 .port_set_duplex = mv88e6xxx_port_set_duplex, 3135 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3136 .port_set_speed = mv88e6390_port_set_speed, 3137 .port_tag_remap = mv88e6390_port_tag_remap, 3138 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3139 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3140 .port_set_ether_type = mv88e6351_port_set_ether_type, 3141 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3142 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3143 .port_pause_limit = mv88e6390_port_pause_limit, 3144 .port_set_cmode = mv88e6390x_port_set_cmode, 3145 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3146 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3147 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3148 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3149 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3150 .stats_get_strings = mv88e6320_stats_get_strings, 3151 .stats_get_stats = mv88e6390_stats_get_stats, 3152 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3153 .set_egress_port = mv88e6390_g1_set_egress_port, 3154 .watchdog_ops = &mv88e6390_watchdog_ops, 3155 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3156 .reset = mv88e6352_g1_reset, 3157 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3158 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3159 .serdes_power = mv88e6390_serdes_power, 3160 }; 3161 3162 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3163 /* MV88E6XXX_FAMILY_6390 */ 3164 .irl_init_all = mv88e6390_g2_irl_init_all, 3165 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3166 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3167 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3168 .phy_read = mv88e6xxx_g2_smi_phy_read, 3169 .phy_write = mv88e6xxx_g2_smi_phy_write, 3170 .port_set_link = mv88e6xxx_port_set_link, 3171 .port_set_duplex = mv88e6xxx_port_set_duplex, 3172 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3173 .port_set_speed = mv88e6390x_port_set_speed, 3174 .port_tag_remap = mv88e6390_port_tag_remap, 3175 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3176 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3177 .port_set_ether_type = mv88e6351_port_set_ether_type, 3178 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3179 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3180 .port_pause_limit = mv88e6390_port_pause_limit, 3181 .port_set_cmode = mv88e6390x_port_set_cmode, 3182 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3183 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3184 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3185 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3186 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3187 .stats_get_strings = mv88e6320_stats_get_strings, 3188 .stats_get_stats = mv88e6390_stats_get_stats, 3189 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3190 .set_egress_port = mv88e6390_g1_set_egress_port, 3191 .watchdog_ops = &mv88e6390_watchdog_ops, 3192 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3193 .reset = mv88e6352_g1_reset, 3194 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3195 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3196 .serdes_power = mv88e6390_serdes_power, 3197 }; 3198 3199 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3200 [MV88E6085] = { 3201 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3202 .family = MV88E6XXX_FAMILY_6097, 3203 .name = "Marvell 88E6085", 3204 .num_databases = 4096, 3205 .num_ports = 10, 3206 .max_vid = 4095, 3207 .port_base_addr = 0x10, 3208 .global1_addr = 0x1b, 3209 .age_time_coeff = 15000, 3210 .g1_irqs = 8, 3211 .atu_move_port_mask = 0xf, 3212 .pvt = true, 3213 .tag_protocol = DSA_TAG_PROTO_DSA, 3214 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3215 .ops = &mv88e6085_ops, 3216 }, 3217 3218 [MV88E6095] = { 3219 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3220 .family = MV88E6XXX_FAMILY_6095, 3221 .name = "Marvell 88E6095/88E6095F", 3222 .num_databases = 256, 3223 .num_ports = 11, 3224 .max_vid = 4095, 3225 .port_base_addr = 0x10, 3226 .global1_addr = 0x1b, 3227 .age_time_coeff = 15000, 3228 .g1_irqs = 8, 3229 .atu_move_port_mask = 0xf, 3230 .tag_protocol = DSA_TAG_PROTO_DSA, 3231 .flags = MV88E6XXX_FLAGS_FAMILY_6095, 3232 .ops = &mv88e6095_ops, 3233 }, 3234 3235 [MV88E6097] = { 3236 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3237 .family = MV88E6XXX_FAMILY_6097, 3238 .name = "Marvell 88E6097/88E6097F", 3239 .num_databases = 4096, 3240 .num_ports = 11, 3241 .max_vid = 4095, 3242 .port_base_addr = 0x10, 3243 .global1_addr = 0x1b, 3244 .age_time_coeff = 15000, 3245 .g1_irqs = 8, 3246 .atu_move_port_mask = 0xf, 3247 .pvt = true, 3248 .tag_protocol = DSA_TAG_PROTO_EDSA, 3249 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3250 .ops = &mv88e6097_ops, 3251 }, 3252 3253 [MV88E6123] = { 3254 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3255 .family = MV88E6XXX_FAMILY_6165, 3256 .name = "Marvell 88E6123", 3257 .num_databases = 4096, 3258 .num_ports = 3, 3259 .max_vid = 4095, 3260 .port_base_addr = 0x10, 3261 .global1_addr = 0x1b, 3262 .age_time_coeff = 15000, 3263 .g1_irqs = 9, 3264 .atu_move_port_mask = 0xf, 3265 .pvt = true, 3266 .tag_protocol = DSA_TAG_PROTO_EDSA, 3267 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3268 .ops = &mv88e6123_ops, 3269 }, 3270 3271 [MV88E6131] = { 3272 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3273 .family = MV88E6XXX_FAMILY_6185, 3274 .name = "Marvell 88E6131", 3275 .num_databases = 256, 3276 .num_ports = 8, 3277 .max_vid = 4095, 3278 .port_base_addr = 0x10, 3279 .global1_addr = 0x1b, 3280 .age_time_coeff = 15000, 3281 .g1_irqs = 9, 3282 .atu_move_port_mask = 0xf, 3283 .tag_protocol = DSA_TAG_PROTO_DSA, 3284 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3285 .ops = &mv88e6131_ops, 3286 }, 3287 3288 [MV88E6141] = { 3289 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3290 .family = MV88E6XXX_FAMILY_6341, 3291 .name = "Marvell 88E6341", 3292 .num_databases = 4096, 3293 .num_ports = 6, 3294 .max_vid = 4095, 3295 .port_base_addr = 0x10, 3296 .global1_addr = 0x1b, 3297 .age_time_coeff = 3750, 3298 .atu_move_port_mask = 0x1f, 3299 .pvt = true, 3300 .tag_protocol = DSA_TAG_PROTO_EDSA, 3301 .flags = MV88E6XXX_FLAGS_FAMILY_6341, 3302 .ops = &mv88e6141_ops, 3303 }, 3304 3305 [MV88E6161] = { 3306 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3307 .family = MV88E6XXX_FAMILY_6165, 3308 .name = "Marvell 88E6161", 3309 .num_databases = 4096, 3310 .num_ports = 6, 3311 .max_vid = 4095, 3312 .port_base_addr = 0x10, 3313 .global1_addr = 0x1b, 3314 .age_time_coeff = 15000, 3315 .g1_irqs = 9, 3316 .atu_move_port_mask = 0xf, 3317 .pvt = true, 3318 .tag_protocol = DSA_TAG_PROTO_EDSA, 3319 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3320 .ops = &mv88e6161_ops, 3321 }, 3322 3323 [MV88E6165] = { 3324 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3325 .family = MV88E6XXX_FAMILY_6165, 3326 .name = "Marvell 88E6165", 3327 .num_databases = 4096, 3328 .num_ports = 6, 3329 .max_vid = 4095, 3330 .port_base_addr = 0x10, 3331 .global1_addr = 0x1b, 3332 .age_time_coeff = 15000, 3333 .g1_irqs = 9, 3334 .atu_move_port_mask = 0xf, 3335 .pvt = true, 3336 .tag_protocol = DSA_TAG_PROTO_DSA, 3337 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3338 .ops = &mv88e6165_ops, 3339 }, 3340 3341 [MV88E6171] = { 3342 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3343 .family = MV88E6XXX_FAMILY_6351, 3344 .name = "Marvell 88E6171", 3345 .num_databases = 4096, 3346 .num_ports = 7, 3347 .max_vid = 4095, 3348 .port_base_addr = 0x10, 3349 .global1_addr = 0x1b, 3350 .age_time_coeff = 15000, 3351 .g1_irqs = 9, 3352 .atu_move_port_mask = 0xf, 3353 .pvt = true, 3354 .tag_protocol = DSA_TAG_PROTO_EDSA, 3355 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3356 .ops = &mv88e6171_ops, 3357 }, 3358 3359 [MV88E6172] = { 3360 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3361 .family = MV88E6XXX_FAMILY_6352, 3362 .name = "Marvell 88E6172", 3363 .num_databases = 4096, 3364 .num_ports = 7, 3365 .max_vid = 4095, 3366 .port_base_addr = 0x10, 3367 .global1_addr = 0x1b, 3368 .age_time_coeff = 15000, 3369 .g1_irqs = 9, 3370 .atu_move_port_mask = 0xf, 3371 .pvt = true, 3372 .tag_protocol = DSA_TAG_PROTO_EDSA, 3373 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3374 .ops = &mv88e6172_ops, 3375 }, 3376 3377 [MV88E6175] = { 3378 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3379 .family = MV88E6XXX_FAMILY_6351, 3380 .name = "Marvell 88E6175", 3381 .num_databases = 4096, 3382 .num_ports = 7, 3383 .max_vid = 4095, 3384 .port_base_addr = 0x10, 3385 .global1_addr = 0x1b, 3386 .age_time_coeff = 15000, 3387 .g1_irqs = 9, 3388 .atu_move_port_mask = 0xf, 3389 .pvt = true, 3390 .tag_protocol = DSA_TAG_PROTO_EDSA, 3391 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3392 .ops = &mv88e6175_ops, 3393 }, 3394 3395 [MV88E6176] = { 3396 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3397 .family = MV88E6XXX_FAMILY_6352, 3398 .name = "Marvell 88E6176", 3399 .num_databases = 4096, 3400 .num_ports = 7, 3401 .max_vid = 4095, 3402 .port_base_addr = 0x10, 3403 .global1_addr = 0x1b, 3404 .age_time_coeff = 15000, 3405 .g1_irqs = 9, 3406 .atu_move_port_mask = 0xf, 3407 .pvt = true, 3408 .tag_protocol = DSA_TAG_PROTO_EDSA, 3409 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3410 .ops = &mv88e6176_ops, 3411 }, 3412 3413 [MV88E6185] = { 3414 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3415 .family = MV88E6XXX_FAMILY_6185, 3416 .name = "Marvell 88E6185", 3417 .num_databases = 256, 3418 .num_ports = 10, 3419 .max_vid = 4095, 3420 .port_base_addr = 0x10, 3421 .global1_addr = 0x1b, 3422 .age_time_coeff = 15000, 3423 .g1_irqs = 8, 3424 .atu_move_port_mask = 0xf, 3425 .tag_protocol = DSA_TAG_PROTO_EDSA, 3426 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3427 .ops = &mv88e6185_ops, 3428 }, 3429 3430 [MV88E6190] = { 3431 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3432 .family = MV88E6XXX_FAMILY_6390, 3433 .name = "Marvell 88E6190", 3434 .num_databases = 4096, 3435 .num_ports = 11, /* 10 + Z80 */ 3436 .max_vid = 8191, 3437 .port_base_addr = 0x0, 3438 .global1_addr = 0x1b, 3439 .tag_protocol = DSA_TAG_PROTO_DSA, 3440 .age_time_coeff = 3750, 3441 .g1_irqs = 9, 3442 .pvt = true, 3443 .atu_move_port_mask = 0x1f, 3444 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 3445 .ops = &mv88e6190_ops, 3446 }, 3447 3448 [MV88E6190X] = { 3449 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3450 .family = MV88E6XXX_FAMILY_6390, 3451 .name = "Marvell 88E6190X", 3452 .num_databases = 4096, 3453 .num_ports = 11, /* 10 + Z80 */ 3454 .max_vid = 8191, 3455 .port_base_addr = 0x0, 3456 .global1_addr = 0x1b, 3457 .age_time_coeff = 3750, 3458 .g1_irqs = 9, 3459 .atu_move_port_mask = 0x1f, 3460 .pvt = true, 3461 .tag_protocol = DSA_TAG_PROTO_DSA, 3462 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 3463 .ops = &mv88e6190x_ops, 3464 }, 3465 3466 [MV88E6191] = { 3467 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3468 .family = MV88E6XXX_FAMILY_6390, 3469 .name = "Marvell 88E6191", 3470 .num_databases = 4096, 3471 .num_ports = 11, /* 10 + Z80 */ 3472 .max_vid = 8191, 3473 .port_base_addr = 0x0, 3474 .global1_addr = 0x1b, 3475 .age_time_coeff = 3750, 3476 .g1_irqs = 9, 3477 .atu_move_port_mask = 0x1f, 3478 .pvt = true, 3479 .tag_protocol = DSA_TAG_PROTO_DSA, 3480 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 3481 .ops = &mv88e6191_ops, 3482 }, 3483 3484 [MV88E6240] = { 3485 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3486 .family = MV88E6XXX_FAMILY_6352, 3487 .name = "Marvell 88E6240", 3488 .num_databases = 4096, 3489 .num_ports = 7, 3490 .max_vid = 4095, 3491 .port_base_addr = 0x10, 3492 .global1_addr = 0x1b, 3493 .age_time_coeff = 15000, 3494 .g1_irqs = 9, 3495 .atu_move_port_mask = 0xf, 3496 .pvt = true, 3497 .tag_protocol = DSA_TAG_PROTO_EDSA, 3498 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3499 .ops = &mv88e6240_ops, 3500 }, 3501 3502 [MV88E6290] = { 3503 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3504 .family = MV88E6XXX_FAMILY_6390, 3505 .name = "Marvell 88E6290", 3506 .num_databases = 4096, 3507 .num_ports = 11, /* 10 + Z80 */ 3508 .max_vid = 8191, 3509 .port_base_addr = 0x0, 3510 .global1_addr = 0x1b, 3511 .age_time_coeff = 3750, 3512 .g1_irqs = 9, 3513 .atu_move_port_mask = 0x1f, 3514 .pvt = true, 3515 .tag_protocol = DSA_TAG_PROTO_DSA, 3516 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 3517 .ops = &mv88e6290_ops, 3518 }, 3519 3520 [MV88E6320] = { 3521 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3522 .family = MV88E6XXX_FAMILY_6320, 3523 .name = "Marvell 88E6320", 3524 .num_databases = 4096, 3525 .num_ports = 7, 3526 .max_vid = 4095, 3527 .port_base_addr = 0x10, 3528 .global1_addr = 0x1b, 3529 .age_time_coeff = 15000, 3530 .g1_irqs = 8, 3531 .atu_move_port_mask = 0xf, 3532 .pvt = true, 3533 .tag_protocol = DSA_TAG_PROTO_EDSA, 3534 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 3535 .ops = &mv88e6320_ops, 3536 }, 3537 3538 [MV88E6321] = { 3539 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3540 .family = MV88E6XXX_FAMILY_6320, 3541 .name = "Marvell 88E6321", 3542 .num_databases = 4096, 3543 .num_ports = 7, 3544 .max_vid = 4095, 3545 .port_base_addr = 0x10, 3546 .global1_addr = 0x1b, 3547 .age_time_coeff = 15000, 3548 .g1_irqs = 8, 3549 .atu_move_port_mask = 0xf, 3550 .tag_protocol = DSA_TAG_PROTO_EDSA, 3551 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 3552 .ops = &mv88e6321_ops, 3553 }, 3554 3555 [MV88E6341] = { 3556 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3557 .family = MV88E6XXX_FAMILY_6341, 3558 .name = "Marvell 88E6341", 3559 .num_databases = 4096, 3560 .num_ports = 6, 3561 .max_vid = 4095, 3562 .port_base_addr = 0x10, 3563 .global1_addr = 0x1b, 3564 .age_time_coeff = 3750, 3565 .atu_move_port_mask = 0x1f, 3566 .pvt = true, 3567 .tag_protocol = DSA_TAG_PROTO_EDSA, 3568 .flags = MV88E6XXX_FLAGS_FAMILY_6341, 3569 .ops = &mv88e6341_ops, 3570 }, 3571 3572 [MV88E6350] = { 3573 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3574 .family = MV88E6XXX_FAMILY_6351, 3575 .name = "Marvell 88E6350", 3576 .num_databases = 4096, 3577 .num_ports = 7, 3578 .max_vid = 4095, 3579 .port_base_addr = 0x10, 3580 .global1_addr = 0x1b, 3581 .age_time_coeff = 15000, 3582 .g1_irqs = 9, 3583 .atu_move_port_mask = 0xf, 3584 .pvt = true, 3585 .tag_protocol = DSA_TAG_PROTO_EDSA, 3586 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3587 .ops = &mv88e6350_ops, 3588 }, 3589 3590 [MV88E6351] = { 3591 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3592 .family = MV88E6XXX_FAMILY_6351, 3593 .name = "Marvell 88E6351", 3594 .num_databases = 4096, 3595 .num_ports = 7, 3596 .max_vid = 4095, 3597 .port_base_addr = 0x10, 3598 .global1_addr = 0x1b, 3599 .age_time_coeff = 15000, 3600 .g1_irqs = 9, 3601 .atu_move_port_mask = 0xf, 3602 .pvt = true, 3603 .tag_protocol = DSA_TAG_PROTO_EDSA, 3604 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3605 .ops = &mv88e6351_ops, 3606 }, 3607 3608 [MV88E6352] = { 3609 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3610 .family = MV88E6XXX_FAMILY_6352, 3611 .name = "Marvell 88E6352", 3612 .num_databases = 4096, 3613 .num_ports = 7, 3614 .max_vid = 4095, 3615 .port_base_addr = 0x10, 3616 .global1_addr = 0x1b, 3617 .age_time_coeff = 15000, 3618 .g1_irqs = 9, 3619 .atu_move_port_mask = 0xf, 3620 .pvt = true, 3621 .tag_protocol = DSA_TAG_PROTO_EDSA, 3622 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3623 .ops = &mv88e6352_ops, 3624 }, 3625 [MV88E6390] = { 3626 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3627 .family = MV88E6XXX_FAMILY_6390, 3628 .name = "Marvell 88E6390", 3629 .num_databases = 4096, 3630 .num_ports = 11, /* 10 + Z80 */ 3631 .max_vid = 8191, 3632 .port_base_addr = 0x0, 3633 .global1_addr = 0x1b, 3634 .age_time_coeff = 3750, 3635 .g1_irqs = 9, 3636 .atu_move_port_mask = 0x1f, 3637 .pvt = true, 3638 .tag_protocol = DSA_TAG_PROTO_DSA, 3639 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 3640 .ops = &mv88e6390_ops, 3641 }, 3642 [MV88E6390X] = { 3643 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3644 .family = MV88E6XXX_FAMILY_6390, 3645 .name = "Marvell 88E6390X", 3646 .num_databases = 4096, 3647 .num_ports = 11, /* 10 + Z80 */ 3648 .max_vid = 8191, 3649 .port_base_addr = 0x0, 3650 .global1_addr = 0x1b, 3651 .age_time_coeff = 3750, 3652 .g1_irqs = 9, 3653 .atu_move_port_mask = 0x1f, 3654 .pvt = true, 3655 .tag_protocol = DSA_TAG_PROTO_DSA, 3656 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 3657 .ops = &mv88e6390x_ops, 3658 }, 3659 }; 3660 3661 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3662 { 3663 int i; 3664 3665 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3666 if (mv88e6xxx_table[i].prod_num == prod_num) 3667 return &mv88e6xxx_table[i]; 3668 3669 return NULL; 3670 } 3671 3672 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3673 { 3674 const struct mv88e6xxx_info *info; 3675 unsigned int prod_num, rev; 3676 u16 id; 3677 int err; 3678 3679 mutex_lock(&chip->reg_lock); 3680 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3681 mutex_unlock(&chip->reg_lock); 3682 if (err) 3683 return err; 3684 3685 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3686 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3687 3688 info = mv88e6xxx_lookup_info(prod_num); 3689 if (!info) 3690 return -ENODEV; 3691 3692 /* Update the compatible info with the probed one */ 3693 chip->info = info; 3694 3695 err = mv88e6xxx_g2_require(chip); 3696 if (err) 3697 return err; 3698 3699 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3700 chip->info->prod_num, chip->info->name, rev); 3701 3702 return 0; 3703 } 3704 3705 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3706 { 3707 struct mv88e6xxx_chip *chip; 3708 3709 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3710 if (!chip) 3711 return NULL; 3712 3713 chip->dev = dev; 3714 3715 mutex_init(&chip->reg_lock); 3716 INIT_LIST_HEAD(&chip->mdios); 3717 3718 return chip; 3719 } 3720 3721 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3722 struct mii_bus *bus, int sw_addr) 3723 { 3724 if (sw_addr == 0) 3725 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3726 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) 3727 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3728 else 3729 return -EINVAL; 3730 3731 chip->bus = bus; 3732 chip->sw_addr = sw_addr; 3733 3734 return 0; 3735 } 3736 3737 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 3738 { 3739 struct mv88e6xxx_chip *chip = ds->priv; 3740 3741 return chip->info->tag_protocol; 3742 } 3743 3744 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3745 struct device *host_dev, int sw_addr, 3746 void **priv) 3747 { 3748 struct mv88e6xxx_chip *chip; 3749 struct mii_bus *bus; 3750 int err; 3751 3752 bus = dsa_host_dev_to_mii_bus(host_dev); 3753 if (!bus) 3754 return NULL; 3755 3756 chip = mv88e6xxx_alloc_chip(dsa_dev); 3757 if (!chip) 3758 return NULL; 3759 3760 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3761 chip->info = &mv88e6xxx_table[MV88E6085]; 3762 3763 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3764 if (err) 3765 goto free; 3766 3767 err = mv88e6xxx_detect(chip); 3768 if (err) 3769 goto free; 3770 3771 mutex_lock(&chip->reg_lock); 3772 err = mv88e6xxx_switch_reset(chip); 3773 mutex_unlock(&chip->reg_lock); 3774 if (err) 3775 goto free; 3776 3777 mv88e6xxx_phy_init(chip); 3778 3779 err = mv88e6xxx_mdios_register(chip, NULL); 3780 if (err) 3781 goto free; 3782 3783 *priv = chip; 3784 3785 return chip->info->name; 3786 free: 3787 devm_kfree(dsa_dev, chip); 3788 3789 return NULL; 3790 } 3791 3792 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3793 const struct switchdev_obj_port_mdb *mdb, 3794 struct switchdev_trans *trans) 3795 { 3796 /* We don't need any dynamic resource from the kernel (yet), 3797 * so skip the prepare phase. 3798 */ 3799 3800 return 0; 3801 } 3802 3803 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3804 const struct switchdev_obj_port_mdb *mdb, 3805 struct switchdev_trans *trans) 3806 { 3807 struct mv88e6xxx_chip *chip = ds->priv; 3808 3809 mutex_lock(&chip->reg_lock); 3810 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3811 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3812 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3813 port); 3814 mutex_unlock(&chip->reg_lock); 3815 } 3816 3817 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3818 const struct switchdev_obj_port_mdb *mdb) 3819 { 3820 struct mv88e6xxx_chip *chip = ds->priv; 3821 int err; 3822 3823 mutex_lock(&chip->reg_lock); 3824 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3825 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3826 mutex_unlock(&chip->reg_lock); 3827 3828 return err; 3829 } 3830 3831 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, 3832 struct switchdev_obj_port_mdb *mdb, 3833 switchdev_obj_dump_cb_t *cb) 3834 { 3835 struct mv88e6xxx_chip *chip = ds->priv; 3836 int err; 3837 3838 mutex_lock(&chip->reg_lock); 3839 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); 3840 mutex_unlock(&chip->reg_lock); 3841 3842 return err; 3843 } 3844 3845 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3846 .probe = mv88e6xxx_drv_probe, 3847 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3848 .setup = mv88e6xxx_setup, 3849 .set_addr = mv88e6xxx_set_addr, 3850 .adjust_link = mv88e6xxx_adjust_link, 3851 .get_strings = mv88e6xxx_get_strings, 3852 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3853 .get_sset_count = mv88e6xxx_get_sset_count, 3854 .port_enable = mv88e6xxx_port_enable, 3855 .port_disable = mv88e6xxx_port_disable, 3856 .set_eee = mv88e6xxx_set_eee, 3857 .get_eee = mv88e6xxx_get_eee, 3858 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3859 .get_eeprom = mv88e6xxx_get_eeprom, 3860 .set_eeprom = mv88e6xxx_set_eeprom, 3861 .get_regs_len = mv88e6xxx_get_regs_len, 3862 .get_regs = mv88e6xxx_get_regs, 3863 .set_ageing_time = mv88e6xxx_set_ageing_time, 3864 .port_bridge_join = mv88e6xxx_port_bridge_join, 3865 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3866 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3867 .port_fast_age = mv88e6xxx_port_fast_age, 3868 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3869 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3870 .port_vlan_add = mv88e6xxx_port_vlan_add, 3871 .port_vlan_del = mv88e6xxx_port_vlan_del, 3872 .port_vlan_dump = mv88e6xxx_port_vlan_dump, 3873 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, 3874 .port_fdb_add = mv88e6xxx_port_fdb_add, 3875 .port_fdb_del = mv88e6xxx_port_fdb_del, 3876 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3877 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3878 .port_mdb_add = mv88e6xxx_port_mdb_add, 3879 .port_mdb_del = mv88e6xxx_port_mdb_del, 3880 .port_mdb_dump = mv88e6xxx_port_mdb_dump, 3881 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 3882 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 3883 }; 3884 3885 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 3886 .ops = &mv88e6xxx_switch_ops, 3887 }; 3888 3889 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 3890 { 3891 struct device *dev = chip->dev; 3892 struct dsa_switch *ds; 3893 3894 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 3895 if (!ds) 3896 return -ENOMEM; 3897 3898 ds->priv = chip; 3899 ds->ops = &mv88e6xxx_switch_ops; 3900 ds->ageing_time_min = chip->info->age_time_coeff; 3901 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 3902 3903 dev_set_drvdata(dev, ds); 3904 3905 return dsa_register_switch(ds); 3906 } 3907 3908 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3909 { 3910 dsa_unregister_switch(chip->ds); 3911 } 3912 3913 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3914 { 3915 struct device *dev = &mdiodev->dev; 3916 struct device_node *np = dev->of_node; 3917 const struct mv88e6xxx_info *compat_info; 3918 struct mv88e6xxx_chip *chip; 3919 u32 eeprom_len; 3920 int err; 3921 3922 compat_info = of_device_get_match_data(dev); 3923 if (!compat_info) 3924 return -EINVAL; 3925 3926 chip = mv88e6xxx_alloc_chip(dev); 3927 if (!chip) 3928 return -ENOMEM; 3929 3930 chip->info = compat_info; 3931 3932 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3933 if (err) 3934 return err; 3935 3936 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 3937 if (IS_ERR(chip->reset)) 3938 return PTR_ERR(chip->reset); 3939 3940 err = mv88e6xxx_detect(chip); 3941 if (err) 3942 return err; 3943 3944 mv88e6xxx_phy_init(chip); 3945 3946 if (chip->info->ops->get_eeprom && 3947 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3948 chip->eeprom_len = eeprom_len; 3949 3950 mutex_lock(&chip->reg_lock); 3951 err = mv88e6xxx_switch_reset(chip); 3952 mutex_unlock(&chip->reg_lock); 3953 if (err) 3954 goto out; 3955 3956 chip->irq = of_irq_get(np, 0); 3957 if (chip->irq == -EPROBE_DEFER) { 3958 err = chip->irq; 3959 goto out; 3960 } 3961 3962 if (chip->irq > 0) { 3963 /* Has to be performed before the MDIO bus is created, 3964 * because the PHYs will link there interrupts to these 3965 * interrupt controllers 3966 */ 3967 mutex_lock(&chip->reg_lock); 3968 err = mv88e6xxx_g1_irq_setup(chip); 3969 mutex_unlock(&chip->reg_lock); 3970 3971 if (err) 3972 goto out; 3973 3974 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { 3975 err = mv88e6xxx_g2_irq_setup(chip); 3976 if (err) 3977 goto out_g1_irq; 3978 } 3979 } 3980 3981 err = mv88e6xxx_mdios_register(chip, np); 3982 if (err) 3983 goto out_g2_irq; 3984 3985 err = mv88e6xxx_register_switch(chip); 3986 if (err) 3987 goto out_mdio; 3988 3989 return 0; 3990 3991 out_mdio: 3992 mv88e6xxx_mdios_unregister(chip); 3993 out_g2_irq: 3994 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) 3995 mv88e6xxx_g2_irq_free(chip); 3996 out_g1_irq: 3997 if (chip->irq > 0) { 3998 mutex_lock(&chip->reg_lock); 3999 mv88e6xxx_g1_irq_free(chip); 4000 mutex_unlock(&chip->reg_lock); 4001 } 4002 out: 4003 return err; 4004 } 4005 4006 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4007 { 4008 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4009 struct mv88e6xxx_chip *chip = ds->priv; 4010 4011 mv88e6xxx_phy_destroy(chip); 4012 mv88e6xxx_unregister_switch(chip); 4013 mv88e6xxx_mdios_unregister(chip); 4014 4015 if (chip->irq > 0) { 4016 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) 4017 mv88e6xxx_g2_irq_free(chip); 4018 mv88e6xxx_g1_irq_free(chip); 4019 } 4020 } 4021 4022 static const struct of_device_id mv88e6xxx_of_match[] = { 4023 { 4024 .compatible = "marvell,mv88e6085", 4025 .data = &mv88e6xxx_table[MV88E6085], 4026 }, 4027 { 4028 .compatible = "marvell,mv88e6190", 4029 .data = &mv88e6xxx_table[MV88E6190], 4030 }, 4031 { /* sentinel */ }, 4032 }; 4033 4034 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4035 4036 static struct mdio_driver mv88e6xxx_driver = { 4037 .probe = mv88e6xxx_probe, 4038 .remove = mv88e6xxx_remove, 4039 .mdiodrv.driver = { 4040 .name = "mv88e6085", 4041 .of_match_table = mv88e6xxx_of_match, 4042 }, 4043 }; 4044 4045 static int __init mv88e6xxx_init(void) 4046 { 4047 register_switch_driver(&mv88e6xxx_switch_drv); 4048 return mdio_driver_register(&mv88e6xxx_driver); 4049 } 4050 module_init(mv88e6xxx_init); 4051 4052 static void __exit mv88e6xxx_cleanup(void) 4053 { 4054 mdio_driver_unregister(&mv88e6xxx_driver); 4055 unregister_switch_driver(&mv88e6xxx_switch_drv); 4056 } 4057 module_exit(mv88e6xxx_cleanup); 4058 4059 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4060 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4061 MODULE_LICENSE("GPL"); 4062