1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 mv88e6xxx_reg_unlock(chip); 344 err = request_threaded_irq(chip->irq, NULL, 345 mv88e6xxx_g1_irq_thread_fn, 346 IRQF_ONESHOT | IRQF_SHARED, 347 dev_name(chip->dev), chip); 348 mv88e6xxx_reg_lock(chip); 349 if (err) 350 mv88e6xxx_g1_irq_free_common(chip); 351 352 return err; 353 } 354 355 static void mv88e6xxx_irq_poll(struct kthread_work *work) 356 { 357 struct mv88e6xxx_chip *chip = container_of(work, 358 struct mv88e6xxx_chip, 359 irq_poll_work.work); 360 mv88e6xxx_g1_irq_thread_work(chip); 361 362 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 363 msecs_to_jiffies(100)); 364 } 365 366 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 367 { 368 int err; 369 370 err = mv88e6xxx_g1_irq_setup_common(chip); 371 if (err) 372 return err; 373 374 kthread_init_delayed_work(&chip->irq_poll_work, 375 mv88e6xxx_irq_poll); 376 377 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 378 if (IS_ERR(chip->kworker)) 379 return PTR_ERR(chip->kworker); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 384 return 0; 385 } 386 387 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 388 { 389 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 390 kthread_destroy_worker(chip->kworker); 391 392 mv88e6xxx_reg_lock(chip); 393 mv88e6xxx_g1_irq_free_common(chip); 394 mv88e6xxx_reg_unlock(chip); 395 } 396 397 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 398 int speed, int duplex, int pause, 399 phy_interface_t mode) 400 { 401 struct phylink_link_state state; 402 int err; 403 404 if (!chip->info->ops->port_set_link) 405 return 0; 406 407 if (!chip->info->ops->port_link_state) 408 return 0; 409 410 err = chip->info->ops->port_link_state(chip, port, &state); 411 if (err) 412 return err; 413 414 /* Has anything actually changed? We don't expect the 415 * interface mode to change without one of the other 416 * parameters also changing 417 */ 418 if (state.link == link && 419 state.speed == speed && 420 state.duplex == duplex && 421 (state.interface == mode || 422 state.interface == PHY_INTERFACE_MODE_NA)) 423 return 0; 424 425 /* Port's MAC control must not be changed unless the link is down */ 426 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 427 if (err) 428 return err; 429 430 if (chip->info->ops->port_set_speed) { 431 err = chip->info->ops->port_set_speed(chip, port, speed); 432 if (err && err != -EOPNOTSUPP) 433 goto restore_link; 434 } 435 436 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 437 mode = chip->info->ops->port_max_speed_mode(port); 438 439 if (chip->info->ops->port_set_pause) { 440 err = chip->info->ops->port_set_pause(chip, port, pause); 441 if (err) 442 goto restore_link; 443 } 444 445 if (chip->info->ops->port_set_duplex) { 446 err = chip->info->ops->port_set_duplex(chip, port, duplex); 447 if (err && err != -EOPNOTSUPP) 448 goto restore_link; 449 } 450 451 if (chip->info->ops->port_set_rgmii_delay) { 452 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 453 if (err && err != -EOPNOTSUPP) 454 goto restore_link; 455 } 456 457 if (chip->info->ops->port_set_cmode) { 458 err = chip->info->ops->port_set_cmode(chip, port, mode); 459 if (err && err != -EOPNOTSUPP) 460 goto restore_link; 461 } 462 463 err = 0; 464 restore_link: 465 if (chip->info->ops->port_set_link(chip, port, link)) 466 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 467 468 return err; 469 } 470 471 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 472 { 473 struct mv88e6xxx_chip *chip = ds->priv; 474 475 return port < chip->info->num_internal_phys; 476 } 477 478 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 479 unsigned long *mask, 480 struct phylink_link_state *state) 481 { 482 if (!phy_interface_mode_is_8023z(state->interface)) { 483 /* 10M and 100M are only supported in non-802.3z mode */ 484 phylink_set(mask, 10baseT_Half); 485 phylink_set(mask, 10baseT_Full); 486 phylink_set(mask, 100baseT_Half); 487 phylink_set(mask, 100baseT_Full); 488 } 489 } 490 491 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 492 unsigned long *mask, 493 struct phylink_link_state *state) 494 { 495 /* FIXME: if the port is in 1000Base-X mode, then it only supports 496 * 1000M FD speeds. In this case, CMODE will indicate 5. 497 */ 498 phylink_set(mask, 1000baseT_Full); 499 phylink_set(mask, 1000baseX_Full); 500 501 mv88e6065_phylink_validate(chip, port, mask, state); 502 } 503 504 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 505 unsigned long *mask, 506 struct phylink_link_state *state) 507 { 508 if (port >= 5) 509 phylink_set(mask, 2500baseX_Full); 510 511 /* No ethtool bits for 200Mbps */ 512 phylink_set(mask, 1000baseT_Full); 513 phylink_set(mask, 1000baseX_Full); 514 515 mv88e6065_phylink_validate(chip, port, mask, state); 516 } 517 518 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 519 unsigned long *mask, 520 struct phylink_link_state *state) 521 { 522 /* No ethtool bits for 200Mbps */ 523 phylink_set(mask, 1000baseT_Full); 524 phylink_set(mask, 1000baseX_Full); 525 526 mv88e6065_phylink_validate(chip, port, mask, state); 527 } 528 529 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 530 unsigned long *mask, 531 struct phylink_link_state *state) 532 { 533 if (port >= 9) { 534 phylink_set(mask, 2500baseX_Full); 535 phylink_set(mask, 2500baseT_Full); 536 } 537 538 /* No ethtool bits for 200Mbps */ 539 phylink_set(mask, 1000baseT_Full); 540 phylink_set(mask, 1000baseX_Full); 541 542 mv88e6065_phylink_validate(chip, port, mask, state); 543 } 544 545 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 546 unsigned long *mask, 547 struct phylink_link_state *state) 548 { 549 if (port >= 9) { 550 phylink_set(mask, 10000baseT_Full); 551 phylink_set(mask, 10000baseKR_Full); 552 } 553 554 mv88e6390_phylink_validate(chip, port, mask, state); 555 } 556 557 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 558 unsigned long *supported, 559 struct phylink_link_state *state) 560 { 561 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 562 struct mv88e6xxx_chip *chip = ds->priv; 563 564 /* Allow all the expected bits */ 565 phylink_set(mask, Autoneg); 566 phylink_set(mask, Pause); 567 phylink_set_port_modes(mask); 568 569 if (chip->info->ops->phylink_validate) 570 chip->info->ops->phylink_validate(chip, port, mask, state); 571 572 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 573 bitmap_and(state->advertising, state->advertising, mask, 574 __ETHTOOL_LINK_MODE_MASK_NBITS); 575 576 /* We can only operate at 2500BaseX or 1000BaseX. If requested 577 * to advertise both, only report advertising at 2500BaseX. 578 */ 579 phylink_helper_basex_speed(state); 580 } 581 582 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 583 struct phylink_link_state *state) 584 { 585 struct mv88e6xxx_chip *chip = ds->priv; 586 int err; 587 588 mv88e6xxx_reg_lock(chip); 589 if (chip->info->ops->port_link_state) 590 err = chip->info->ops->port_link_state(chip, port, state); 591 else 592 err = -EOPNOTSUPP; 593 mv88e6xxx_reg_unlock(chip); 594 595 return err; 596 } 597 598 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 599 unsigned int mode, 600 const struct phylink_link_state *state) 601 { 602 struct mv88e6xxx_chip *chip = ds->priv; 603 int speed, duplex, link, pause, err; 604 605 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 606 return; 607 608 if (mode == MLO_AN_FIXED) { 609 link = LINK_FORCED_UP; 610 speed = state->speed; 611 duplex = state->duplex; 612 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 613 link = state->link; 614 speed = state->speed; 615 duplex = state->duplex; 616 } else { 617 speed = SPEED_UNFORCED; 618 duplex = DUPLEX_UNFORCED; 619 link = LINK_UNFORCED; 620 } 621 pause = !!phylink_test(state->advertising, Pause); 622 623 mv88e6xxx_reg_lock(chip); 624 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 625 state->interface); 626 mv88e6xxx_reg_unlock(chip); 627 628 if (err && err != -EOPNOTSUPP) 629 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 630 } 631 632 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 633 { 634 struct mv88e6xxx_chip *chip = ds->priv; 635 int err; 636 637 mv88e6xxx_reg_lock(chip); 638 err = chip->info->ops->port_set_link(chip, port, link); 639 mv88e6xxx_reg_unlock(chip); 640 641 if (err) 642 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 643 } 644 645 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 646 unsigned int mode, 647 phy_interface_t interface) 648 { 649 if (mode == MLO_AN_FIXED) 650 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 651 } 652 653 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 654 unsigned int mode, phy_interface_t interface, 655 struct phy_device *phydev) 656 { 657 if (mode == MLO_AN_FIXED) 658 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 659 } 660 661 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 662 { 663 if (!chip->info->ops->stats_snapshot) 664 return -EOPNOTSUPP; 665 666 return chip->info->ops->stats_snapshot(chip, port); 667 } 668 669 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 670 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 671 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 672 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 673 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 674 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 675 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 676 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 677 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 678 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 679 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 680 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 681 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 682 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 683 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 684 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 685 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 686 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 687 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 688 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 689 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 690 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 691 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 692 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 693 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 694 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 695 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 696 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 697 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 698 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 699 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 700 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 701 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 702 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 703 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 704 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 705 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 706 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 707 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 708 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 709 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 710 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 711 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 712 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 713 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 714 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 715 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 716 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 717 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 718 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 719 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 720 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 721 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 722 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 723 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 724 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 725 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 726 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 727 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 728 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 729 }; 730 731 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 732 struct mv88e6xxx_hw_stat *s, 733 int port, u16 bank1_select, 734 u16 histogram) 735 { 736 u32 low; 737 u32 high = 0; 738 u16 reg = 0; 739 int err; 740 u64 value; 741 742 switch (s->type) { 743 case STATS_TYPE_PORT: 744 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 745 if (err) 746 return U64_MAX; 747 748 low = reg; 749 if (s->size == 4) { 750 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 751 if (err) 752 return U64_MAX; 753 low |= ((u32)reg) << 16; 754 } 755 break; 756 case STATS_TYPE_BANK1: 757 reg = bank1_select; 758 /* fall through */ 759 case STATS_TYPE_BANK0: 760 reg |= s->reg | histogram; 761 mv88e6xxx_g1_stats_read(chip, reg, &low); 762 if (s->size == 8) 763 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 764 break; 765 default: 766 return U64_MAX; 767 } 768 value = (((u64)high) << 32) | low; 769 return value; 770 } 771 772 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 773 uint8_t *data, int types) 774 { 775 struct mv88e6xxx_hw_stat *stat; 776 int i, j; 777 778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 779 stat = &mv88e6xxx_hw_stats[i]; 780 if (stat->type & types) { 781 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 782 ETH_GSTRING_LEN); 783 j++; 784 } 785 } 786 787 return j; 788 } 789 790 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 791 uint8_t *data) 792 { 793 return mv88e6xxx_stats_get_strings(chip, data, 794 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 795 } 796 797 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 798 uint8_t *data) 799 { 800 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 801 } 802 803 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 804 uint8_t *data) 805 { 806 return mv88e6xxx_stats_get_strings(chip, data, 807 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 808 } 809 810 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 811 "atu_member_violation", 812 "atu_miss_violation", 813 "atu_full_violation", 814 "vtu_member_violation", 815 "vtu_miss_violation", 816 }; 817 818 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 819 { 820 unsigned int i; 821 822 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 823 strlcpy(data + i * ETH_GSTRING_LEN, 824 mv88e6xxx_atu_vtu_stats_strings[i], 825 ETH_GSTRING_LEN); 826 } 827 828 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 829 u32 stringset, uint8_t *data) 830 { 831 struct mv88e6xxx_chip *chip = ds->priv; 832 int count = 0; 833 834 if (stringset != ETH_SS_STATS) 835 return; 836 837 mv88e6xxx_reg_lock(chip); 838 839 if (chip->info->ops->stats_get_strings) 840 count = chip->info->ops->stats_get_strings(chip, data); 841 842 if (chip->info->ops->serdes_get_strings) { 843 data += count * ETH_GSTRING_LEN; 844 count = chip->info->ops->serdes_get_strings(chip, port, data); 845 } 846 847 data += count * ETH_GSTRING_LEN; 848 mv88e6xxx_atu_vtu_get_strings(data); 849 850 mv88e6xxx_reg_unlock(chip); 851 } 852 853 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 854 int types) 855 { 856 struct mv88e6xxx_hw_stat *stat; 857 int i, j; 858 859 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 860 stat = &mv88e6xxx_hw_stats[i]; 861 if (stat->type & types) 862 j++; 863 } 864 return j; 865 } 866 867 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 868 { 869 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 870 STATS_TYPE_PORT); 871 } 872 873 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 874 { 875 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 876 } 877 878 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 879 { 880 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 881 STATS_TYPE_BANK1); 882 } 883 884 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 885 { 886 struct mv88e6xxx_chip *chip = ds->priv; 887 int serdes_count = 0; 888 int count = 0; 889 890 if (sset != ETH_SS_STATS) 891 return 0; 892 893 mv88e6xxx_reg_lock(chip); 894 if (chip->info->ops->stats_get_sset_count) 895 count = chip->info->ops->stats_get_sset_count(chip); 896 if (count < 0) 897 goto out; 898 899 if (chip->info->ops->serdes_get_sset_count) 900 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 901 port); 902 if (serdes_count < 0) { 903 count = serdes_count; 904 goto out; 905 } 906 count += serdes_count; 907 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 908 909 out: 910 mv88e6xxx_reg_unlock(chip); 911 912 return count; 913 } 914 915 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 916 uint64_t *data, int types, 917 u16 bank1_select, u16 histogram) 918 { 919 struct mv88e6xxx_hw_stat *stat; 920 int i, j; 921 922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 923 stat = &mv88e6xxx_hw_stats[i]; 924 if (stat->type & types) { 925 mv88e6xxx_reg_lock(chip); 926 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 927 bank1_select, 928 histogram); 929 mv88e6xxx_reg_unlock(chip); 930 931 j++; 932 } 933 } 934 return j; 935 } 936 937 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 938 uint64_t *data) 939 { 940 return mv88e6xxx_stats_get_stats(chip, port, data, 941 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 942 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 943 } 944 945 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 946 uint64_t *data) 947 { 948 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 949 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 950 } 951 952 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 953 uint64_t *data) 954 { 955 return mv88e6xxx_stats_get_stats(chip, port, data, 956 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 957 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 958 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 959 } 960 961 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 962 uint64_t *data) 963 { 964 return mv88e6xxx_stats_get_stats(chip, port, data, 965 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 966 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 967 0); 968 } 969 970 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 971 uint64_t *data) 972 { 973 *data++ = chip->ports[port].atu_member_violation; 974 *data++ = chip->ports[port].atu_miss_violation; 975 *data++ = chip->ports[port].atu_full_violation; 976 *data++ = chip->ports[port].vtu_member_violation; 977 *data++ = chip->ports[port].vtu_miss_violation; 978 } 979 980 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 981 uint64_t *data) 982 { 983 int count = 0; 984 985 if (chip->info->ops->stats_get_stats) 986 count = chip->info->ops->stats_get_stats(chip, port, data); 987 988 mv88e6xxx_reg_lock(chip); 989 if (chip->info->ops->serdes_get_stats) { 990 data += count; 991 count = chip->info->ops->serdes_get_stats(chip, port, data); 992 } 993 data += count; 994 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 995 mv88e6xxx_reg_unlock(chip); 996 } 997 998 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 999 uint64_t *data) 1000 { 1001 struct mv88e6xxx_chip *chip = ds->priv; 1002 int ret; 1003 1004 mv88e6xxx_reg_lock(chip); 1005 1006 ret = mv88e6xxx_stats_snapshot(chip, port); 1007 mv88e6xxx_reg_unlock(chip); 1008 1009 if (ret < 0) 1010 return; 1011 1012 mv88e6xxx_get_stats(chip, port, data); 1013 1014 } 1015 1016 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1017 { 1018 return 32 * sizeof(u16); 1019 } 1020 1021 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1022 struct ethtool_regs *regs, void *_p) 1023 { 1024 struct mv88e6xxx_chip *chip = ds->priv; 1025 int err; 1026 u16 reg; 1027 u16 *p = _p; 1028 int i; 1029 1030 regs->version = chip->info->prod_num; 1031 1032 memset(p, 0xff, 32 * sizeof(u16)); 1033 1034 mv88e6xxx_reg_lock(chip); 1035 1036 for (i = 0; i < 32; i++) { 1037 1038 err = mv88e6xxx_port_read(chip, port, i, ®); 1039 if (!err) 1040 p[i] = reg; 1041 } 1042 1043 mv88e6xxx_reg_unlock(chip); 1044 } 1045 1046 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1047 struct ethtool_eee *e) 1048 { 1049 /* Nothing to do on the port's MAC */ 1050 return 0; 1051 } 1052 1053 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1054 struct ethtool_eee *e) 1055 { 1056 /* Nothing to do on the port's MAC */ 1057 return 0; 1058 } 1059 1060 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1061 { 1062 struct dsa_switch *ds = NULL; 1063 struct net_device *br; 1064 u16 pvlan; 1065 int i; 1066 1067 if (dev < DSA_MAX_SWITCHES) 1068 ds = chip->ds->dst->ds[dev]; 1069 1070 /* Prevent frames from unknown switch or port */ 1071 if (!ds || port >= ds->num_ports) 1072 return 0; 1073 1074 /* Frames from DSA links and CPU ports can egress any local port */ 1075 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1076 return mv88e6xxx_port_mask(chip); 1077 1078 br = ds->ports[port].bridge_dev; 1079 pvlan = 0; 1080 1081 /* Frames from user ports can egress any local DSA links and CPU ports, 1082 * as well as any local member of their bridge group. 1083 */ 1084 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1085 if (dsa_is_cpu_port(chip->ds, i) || 1086 dsa_is_dsa_port(chip->ds, i) || 1087 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1088 pvlan |= BIT(i); 1089 1090 return pvlan; 1091 } 1092 1093 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1094 { 1095 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1096 1097 /* prevent frames from going back out of the port they came in on */ 1098 output_ports &= ~BIT(port); 1099 1100 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1101 } 1102 1103 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1104 u8 state) 1105 { 1106 struct mv88e6xxx_chip *chip = ds->priv; 1107 int err; 1108 1109 mv88e6xxx_reg_lock(chip); 1110 err = mv88e6xxx_port_set_state(chip, port, state); 1111 mv88e6xxx_reg_unlock(chip); 1112 1113 if (err) 1114 dev_err(ds->dev, "p%d: failed to update state\n", port); 1115 } 1116 1117 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1118 { 1119 int err; 1120 1121 if (chip->info->ops->ieee_pri_map) { 1122 err = chip->info->ops->ieee_pri_map(chip); 1123 if (err) 1124 return err; 1125 } 1126 1127 if (chip->info->ops->ip_pri_map) { 1128 err = chip->info->ops->ip_pri_map(chip); 1129 if (err) 1130 return err; 1131 } 1132 1133 return 0; 1134 } 1135 1136 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1137 { 1138 int target, port; 1139 int err; 1140 1141 if (!chip->info->global2_addr) 1142 return 0; 1143 1144 /* Initialize the routing port to the 32 possible target devices */ 1145 for (target = 0; target < 32; target++) { 1146 port = 0x1f; 1147 if (target < DSA_MAX_SWITCHES) 1148 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1149 port = chip->ds->rtable[target]; 1150 1151 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1152 if (err) 1153 return err; 1154 } 1155 1156 if (chip->info->ops->set_cascade_port) { 1157 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1158 err = chip->info->ops->set_cascade_port(chip, port); 1159 if (err) 1160 return err; 1161 } 1162 1163 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1164 if (err) 1165 return err; 1166 1167 return 0; 1168 } 1169 1170 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1171 { 1172 /* Clear all trunk masks and mapping */ 1173 if (chip->info->global2_addr) 1174 return mv88e6xxx_g2_trunk_clear(chip); 1175 1176 return 0; 1177 } 1178 1179 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1180 { 1181 if (chip->info->ops->rmu_disable) 1182 return chip->info->ops->rmu_disable(chip); 1183 1184 return 0; 1185 } 1186 1187 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1188 { 1189 if (chip->info->ops->pot_clear) 1190 return chip->info->ops->pot_clear(chip); 1191 1192 return 0; 1193 } 1194 1195 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1196 { 1197 if (chip->info->ops->mgmt_rsvd2cpu) 1198 return chip->info->ops->mgmt_rsvd2cpu(chip); 1199 1200 return 0; 1201 } 1202 1203 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1204 { 1205 int err; 1206 1207 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1208 if (err) 1209 return err; 1210 1211 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1212 if (err) 1213 return err; 1214 1215 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1216 } 1217 1218 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1219 { 1220 int port; 1221 int err; 1222 1223 if (!chip->info->ops->irl_init_all) 1224 return 0; 1225 1226 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1227 /* Disable ingress rate limiting by resetting all per port 1228 * ingress rate limit resources to their initial state. 1229 */ 1230 err = chip->info->ops->irl_init_all(chip, port); 1231 if (err) 1232 return err; 1233 } 1234 1235 return 0; 1236 } 1237 1238 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1239 { 1240 if (chip->info->ops->set_switch_mac) { 1241 u8 addr[ETH_ALEN]; 1242 1243 eth_random_addr(addr); 1244 1245 return chip->info->ops->set_switch_mac(chip, addr); 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1252 { 1253 u16 pvlan = 0; 1254 1255 if (!mv88e6xxx_has_pvt(chip)) 1256 return -EOPNOTSUPP; 1257 1258 /* Skip the local source device, which uses in-chip port VLAN */ 1259 if (dev != chip->ds->index) 1260 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1261 1262 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1263 } 1264 1265 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1266 { 1267 int dev, port; 1268 int err; 1269 1270 if (!mv88e6xxx_has_pvt(chip)) 1271 return 0; 1272 1273 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1274 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1275 */ 1276 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1277 if (err) 1278 return err; 1279 1280 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1281 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1282 err = mv88e6xxx_pvt_map(chip, dev, port); 1283 if (err) 1284 return err; 1285 } 1286 } 1287 1288 return 0; 1289 } 1290 1291 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1292 { 1293 struct mv88e6xxx_chip *chip = ds->priv; 1294 int err; 1295 1296 mv88e6xxx_reg_lock(chip); 1297 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1298 mv88e6xxx_reg_unlock(chip); 1299 1300 if (err) 1301 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1302 } 1303 1304 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1305 { 1306 if (!chip->info->max_vid) 1307 return 0; 1308 1309 return mv88e6xxx_g1_vtu_flush(chip); 1310 } 1311 1312 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1313 struct mv88e6xxx_vtu_entry *entry) 1314 { 1315 if (!chip->info->ops->vtu_getnext) 1316 return -EOPNOTSUPP; 1317 1318 return chip->info->ops->vtu_getnext(chip, entry); 1319 } 1320 1321 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1322 struct mv88e6xxx_vtu_entry *entry) 1323 { 1324 if (!chip->info->ops->vtu_loadpurge) 1325 return -EOPNOTSUPP; 1326 1327 return chip->info->ops->vtu_loadpurge(chip, entry); 1328 } 1329 1330 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1331 { 1332 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1333 struct mv88e6xxx_vtu_entry vlan; 1334 int i, err; 1335 1336 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1337 1338 /* Set every FID bit used by the (un)bridged ports */ 1339 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1340 err = mv88e6xxx_port_get_fid(chip, i, fid); 1341 if (err) 1342 return err; 1343 1344 set_bit(*fid, fid_bitmap); 1345 } 1346 1347 /* Set every FID bit used by the VLAN entries */ 1348 vlan.vid = chip->info->max_vid; 1349 vlan.valid = false; 1350 1351 do { 1352 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1353 if (err) 1354 return err; 1355 1356 if (!vlan.valid) 1357 break; 1358 1359 set_bit(vlan.fid, fid_bitmap); 1360 } while (vlan.vid < chip->info->max_vid); 1361 1362 /* The reset value 0x000 is used to indicate that multiple address 1363 * databases are not needed. Return the next positive available. 1364 */ 1365 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1366 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1367 return -ENOSPC; 1368 1369 /* Clear the database */ 1370 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1371 } 1372 1373 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1374 u16 vid_begin, u16 vid_end) 1375 { 1376 struct mv88e6xxx_chip *chip = ds->priv; 1377 struct mv88e6xxx_vtu_entry vlan; 1378 int i, err; 1379 1380 /* DSA and CPU ports have to be members of multiple vlans */ 1381 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1382 return 0; 1383 1384 if (!vid_begin) 1385 return -EOPNOTSUPP; 1386 1387 vlan.vid = vid_begin - 1; 1388 vlan.valid = false; 1389 1390 do { 1391 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1392 if (err) 1393 return err; 1394 1395 if (!vlan.valid) 1396 break; 1397 1398 if (vlan.vid > vid_end) 1399 break; 1400 1401 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1402 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1403 continue; 1404 1405 if (!ds->ports[i].slave) 1406 continue; 1407 1408 if (vlan.member[i] == 1409 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1410 continue; 1411 1412 if (dsa_to_port(ds, i)->bridge_dev == 1413 ds->ports[port].bridge_dev) 1414 break; /* same bridge, check next VLAN */ 1415 1416 if (!dsa_to_port(ds, i)->bridge_dev) 1417 continue; 1418 1419 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1420 port, vlan.vid, i, 1421 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1422 return -EOPNOTSUPP; 1423 } 1424 } while (vlan.vid < vid_end); 1425 1426 return 0; 1427 } 1428 1429 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1430 bool vlan_filtering) 1431 { 1432 struct mv88e6xxx_chip *chip = ds->priv; 1433 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1434 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1435 int err; 1436 1437 if (!chip->info->max_vid) 1438 return -EOPNOTSUPP; 1439 1440 mv88e6xxx_reg_lock(chip); 1441 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1442 mv88e6xxx_reg_unlock(chip); 1443 1444 return err; 1445 } 1446 1447 static int 1448 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1449 const struct switchdev_obj_port_vlan *vlan) 1450 { 1451 struct mv88e6xxx_chip *chip = ds->priv; 1452 int err; 1453 1454 if (!chip->info->max_vid) 1455 return -EOPNOTSUPP; 1456 1457 /* If the requested port doesn't belong to the same bridge as the VLAN 1458 * members, do not support it (yet) and fallback to software VLAN. 1459 */ 1460 mv88e6xxx_reg_lock(chip); 1461 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1462 vlan->vid_end); 1463 mv88e6xxx_reg_unlock(chip); 1464 1465 /* We don't need any dynamic resource from the kernel (yet), 1466 * so skip the prepare phase. 1467 */ 1468 return err; 1469 } 1470 1471 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1472 const unsigned char *addr, u16 vid, 1473 u8 state) 1474 { 1475 struct mv88e6xxx_atu_entry entry; 1476 struct mv88e6xxx_vtu_entry vlan; 1477 u16 fid; 1478 int err; 1479 1480 /* Null VLAN ID corresponds to the port private database */ 1481 if (vid == 0) { 1482 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1483 if (err) 1484 return err; 1485 } else { 1486 vlan.vid = vid - 1; 1487 vlan.valid = false; 1488 1489 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1490 if (err) 1491 return err; 1492 1493 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1494 if (vlan.vid != vid || !vlan.valid) 1495 return -EOPNOTSUPP; 1496 1497 fid = vlan.fid; 1498 } 1499 1500 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1501 ether_addr_copy(entry.mac, addr); 1502 eth_addr_dec(entry.mac); 1503 1504 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1505 if (err) 1506 return err; 1507 1508 /* Initialize a fresh ATU entry if it isn't found */ 1509 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1510 !ether_addr_equal(entry.mac, addr)) { 1511 memset(&entry, 0, sizeof(entry)); 1512 ether_addr_copy(entry.mac, addr); 1513 } 1514 1515 /* Purge the ATU entry only if no port is using it anymore */ 1516 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1517 entry.portvec &= ~BIT(port); 1518 if (!entry.portvec) 1519 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1520 } else { 1521 entry.portvec |= BIT(port); 1522 entry.state = state; 1523 } 1524 1525 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1526 } 1527 1528 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1529 u16 vid) 1530 { 1531 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1532 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1533 1534 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1535 } 1536 1537 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1538 { 1539 int port; 1540 int err; 1541 1542 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1543 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1544 if (err) 1545 return err; 1546 } 1547 1548 return 0; 1549 } 1550 1551 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1552 u16 vid, u8 member) 1553 { 1554 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1555 struct mv88e6xxx_vtu_entry vlan; 1556 int i, err; 1557 1558 if (!vid) 1559 return -EOPNOTSUPP; 1560 1561 vlan.vid = vid - 1; 1562 vlan.valid = false; 1563 1564 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1565 if (err) 1566 return err; 1567 1568 if (vlan.vid != vid || !vlan.valid) { 1569 memset(&vlan, 0, sizeof(vlan)); 1570 1571 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1572 if (err) 1573 return err; 1574 1575 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1576 if (i == port) 1577 vlan.member[i] = member; 1578 else 1579 vlan.member[i] = non_member; 1580 1581 vlan.vid = vid; 1582 vlan.valid = true; 1583 1584 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1585 if (err) 1586 return err; 1587 1588 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1589 if (err) 1590 return err; 1591 } else if (vlan.member[port] != member) { 1592 vlan.member[port] = member; 1593 1594 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1595 if (err) 1596 return err; 1597 } else { 1598 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1599 port, vid); 1600 } 1601 1602 return 0; 1603 } 1604 1605 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1606 const struct switchdev_obj_port_vlan *vlan) 1607 { 1608 struct mv88e6xxx_chip *chip = ds->priv; 1609 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1610 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1611 u8 member; 1612 u16 vid; 1613 1614 if (!chip->info->max_vid) 1615 return; 1616 1617 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1618 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1619 else if (untagged) 1620 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1621 else 1622 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1623 1624 mv88e6xxx_reg_lock(chip); 1625 1626 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1627 if (mv88e6xxx_port_vlan_join(chip, port, vid, member)) 1628 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1629 vid, untagged ? 'u' : 't'); 1630 1631 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1632 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1633 vlan->vid_end); 1634 1635 mv88e6xxx_reg_unlock(chip); 1636 } 1637 1638 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1639 int port, u16 vid) 1640 { 1641 struct mv88e6xxx_vtu_entry vlan; 1642 int i, err; 1643 1644 if (!vid) 1645 return -EOPNOTSUPP; 1646 1647 vlan.vid = vid - 1; 1648 vlan.valid = false; 1649 1650 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1651 if (err) 1652 return err; 1653 1654 /* If the VLAN doesn't exist in hardware or the port isn't a member, 1655 * tell switchdev that this VLAN is likely handled in software. 1656 */ 1657 if (vlan.vid != vid || !vlan.valid || 1658 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1659 return -EOPNOTSUPP; 1660 1661 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1662 1663 /* keep the VLAN unless all ports are excluded */ 1664 vlan.valid = false; 1665 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1666 if (vlan.member[i] != 1667 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1668 vlan.valid = true; 1669 break; 1670 } 1671 } 1672 1673 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1674 if (err) 1675 return err; 1676 1677 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1678 } 1679 1680 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1681 const struct switchdev_obj_port_vlan *vlan) 1682 { 1683 struct mv88e6xxx_chip *chip = ds->priv; 1684 u16 pvid, vid; 1685 int err = 0; 1686 1687 if (!chip->info->max_vid) 1688 return -EOPNOTSUPP; 1689 1690 mv88e6xxx_reg_lock(chip); 1691 1692 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1693 if (err) 1694 goto unlock; 1695 1696 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1697 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 1698 if (err) 1699 goto unlock; 1700 1701 if (vid == pvid) { 1702 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1703 if (err) 1704 goto unlock; 1705 } 1706 } 1707 1708 unlock: 1709 mv88e6xxx_reg_unlock(chip); 1710 1711 return err; 1712 } 1713 1714 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1715 const unsigned char *addr, u16 vid) 1716 { 1717 struct mv88e6xxx_chip *chip = ds->priv; 1718 int err; 1719 1720 mv88e6xxx_reg_lock(chip); 1721 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1722 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1723 mv88e6xxx_reg_unlock(chip); 1724 1725 return err; 1726 } 1727 1728 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1729 const unsigned char *addr, u16 vid) 1730 { 1731 struct mv88e6xxx_chip *chip = ds->priv; 1732 int err; 1733 1734 mv88e6xxx_reg_lock(chip); 1735 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1736 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1737 mv88e6xxx_reg_unlock(chip); 1738 1739 return err; 1740 } 1741 1742 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1743 u16 fid, u16 vid, int port, 1744 dsa_fdb_dump_cb_t *cb, void *data) 1745 { 1746 struct mv88e6xxx_atu_entry addr; 1747 bool is_static; 1748 int err; 1749 1750 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1751 eth_broadcast_addr(addr.mac); 1752 1753 do { 1754 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1755 if (err) 1756 return err; 1757 1758 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1759 break; 1760 1761 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1762 continue; 1763 1764 if (!is_unicast_ether_addr(addr.mac)) 1765 continue; 1766 1767 is_static = (addr.state == 1768 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1769 err = cb(addr.mac, vid, is_static, data); 1770 if (err) 1771 return err; 1772 } while (!is_broadcast_ether_addr(addr.mac)); 1773 1774 return err; 1775 } 1776 1777 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1778 dsa_fdb_dump_cb_t *cb, void *data) 1779 { 1780 struct mv88e6xxx_vtu_entry vlan; 1781 u16 fid; 1782 int err; 1783 1784 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1785 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1786 if (err) 1787 return err; 1788 1789 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1790 if (err) 1791 return err; 1792 1793 /* Dump VLANs' Filtering Information Databases */ 1794 vlan.vid = chip->info->max_vid; 1795 vlan.valid = false; 1796 1797 do { 1798 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1799 if (err) 1800 return err; 1801 1802 if (!vlan.valid) 1803 break; 1804 1805 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1806 cb, data); 1807 if (err) 1808 return err; 1809 } while (vlan.vid < chip->info->max_vid); 1810 1811 return err; 1812 } 1813 1814 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1815 dsa_fdb_dump_cb_t *cb, void *data) 1816 { 1817 struct mv88e6xxx_chip *chip = ds->priv; 1818 int err; 1819 1820 mv88e6xxx_reg_lock(chip); 1821 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1822 mv88e6xxx_reg_unlock(chip); 1823 1824 return err; 1825 } 1826 1827 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1828 struct net_device *br) 1829 { 1830 struct dsa_switch *ds; 1831 int port; 1832 int dev; 1833 int err; 1834 1835 /* Remap the Port VLAN of each local bridge group member */ 1836 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1837 if (chip->ds->ports[port].bridge_dev == br) { 1838 err = mv88e6xxx_port_vlan_map(chip, port); 1839 if (err) 1840 return err; 1841 } 1842 } 1843 1844 if (!mv88e6xxx_has_pvt(chip)) 1845 return 0; 1846 1847 /* Remap the Port VLAN of each cross-chip bridge group member */ 1848 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1849 ds = chip->ds->dst->ds[dev]; 1850 if (!ds) 1851 break; 1852 1853 for (port = 0; port < ds->num_ports; ++port) { 1854 if (ds->ports[port].bridge_dev == br) { 1855 err = mv88e6xxx_pvt_map(chip, dev, port); 1856 if (err) 1857 return err; 1858 } 1859 } 1860 } 1861 1862 return 0; 1863 } 1864 1865 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1866 struct net_device *br) 1867 { 1868 struct mv88e6xxx_chip *chip = ds->priv; 1869 int err; 1870 1871 mv88e6xxx_reg_lock(chip); 1872 err = mv88e6xxx_bridge_map(chip, br); 1873 mv88e6xxx_reg_unlock(chip); 1874 1875 return err; 1876 } 1877 1878 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1879 struct net_device *br) 1880 { 1881 struct mv88e6xxx_chip *chip = ds->priv; 1882 1883 mv88e6xxx_reg_lock(chip); 1884 if (mv88e6xxx_bridge_map(chip, br) || 1885 mv88e6xxx_port_vlan_map(chip, port)) 1886 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1887 mv88e6xxx_reg_unlock(chip); 1888 } 1889 1890 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1891 int port, struct net_device *br) 1892 { 1893 struct mv88e6xxx_chip *chip = ds->priv; 1894 int err; 1895 1896 if (!mv88e6xxx_has_pvt(chip)) 1897 return 0; 1898 1899 mv88e6xxx_reg_lock(chip); 1900 err = mv88e6xxx_pvt_map(chip, dev, port); 1901 mv88e6xxx_reg_unlock(chip); 1902 1903 return err; 1904 } 1905 1906 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1907 int port, struct net_device *br) 1908 { 1909 struct mv88e6xxx_chip *chip = ds->priv; 1910 1911 if (!mv88e6xxx_has_pvt(chip)) 1912 return; 1913 1914 mv88e6xxx_reg_lock(chip); 1915 if (mv88e6xxx_pvt_map(chip, dev, port)) 1916 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1917 mv88e6xxx_reg_unlock(chip); 1918 } 1919 1920 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1921 { 1922 if (chip->info->ops->reset) 1923 return chip->info->ops->reset(chip); 1924 1925 return 0; 1926 } 1927 1928 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1929 { 1930 struct gpio_desc *gpiod = chip->reset; 1931 1932 /* If there is a GPIO connected to the reset pin, toggle it */ 1933 if (gpiod) { 1934 gpiod_set_value_cansleep(gpiod, 1); 1935 usleep_range(10000, 20000); 1936 gpiod_set_value_cansleep(gpiod, 0); 1937 usleep_range(10000, 20000); 1938 } 1939 } 1940 1941 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1942 { 1943 int i, err; 1944 1945 /* Set all ports to the Disabled state */ 1946 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1947 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1948 if (err) 1949 return err; 1950 } 1951 1952 /* Wait for transmit queues to drain, 1953 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1954 */ 1955 usleep_range(2000, 4000); 1956 1957 return 0; 1958 } 1959 1960 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1961 { 1962 int err; 1963 1964 err = mv88e6xxx_disable_ports(chip); 1965 if (err) 1966 return err; 1967 1968 mv88e6xxx_hardware_reset(chip); 1969 1970 return mv88e6xxx_software_reset(chip); 1971 } 1972 1973 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1974 enum mv88e6xxx_frame_mode frame, 1975 enum mv88e6xxx_egress_mode egress, u16 etype) 1976 { 1977 int err; 1978 1979 if (!chip->info->ops->port_set_frame_mode) 1980 return -EOPNOTSUPP; 1981 1982 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1983 if (err) 1984 return err; 1985 1986 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1987 if (err) 1988 return err; 1989 1990 if (chip->info->ops->port_set_ether_type) 1991 return chip->info->ops->port_set_ether_type(chip, port, etype); 1992 1993 return 0; 1994 } 1995 1996 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1997 { 1998 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1999 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2000 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2001 } 2002 2003 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2004 { 2005 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2006 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2007 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2008 } 2009 2010 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2011 { 2012 return mv88e6xxx_set_port_mode(chip, port, 2013 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2014 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2015 ETH_P_EDSA); 2016 } 2017 2018 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2019 { 2020 if (dsa_is_dsa_port(chip->ds, port)) 2021 return mv88e6xxx_set_port_mode_dsa(chip, port); 2022 2023 if (dsa_is_user_port(chip->ds, port)) 2024 return mv88e6xxx_set_port_mode_normal(chip, port); 2025 2026 /* Setup CPU port mode depending on its supported tag format */ 2027 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2028 return mv88e6xxx_set_port_mode_dsa(chip, port); 2029 2030 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2031 return mv88e6xxx_set_port_mode_edsa(chip, port); 2032 2033 return -EINVAL; 2034 } 2035 2036 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2037 { 2038 bool message = dsa_is_dsa_port(chip->ds, port); 2039 2040 return mv88e6xxx_port_set_message_port(chip, port, message); 2041 } 2042 2043 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2044 { 2045 struct dsa_switch *ds = chip->ds; 2046 bool flood; 2047 2048 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2049 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2050 if (chip->info->ops->port_set_egress_floods) 2051 return chip->info->ops->port_set_egress_floods(chip, port, 2052 flood, flood); 2053 2054 return 0; 2055 } 2056 2057 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2058 { 2059 struct mv88e6xxx_port *mvp = dev_id; 2060 struct mv88e6xxx_chip *chip = mvp->chip; 2061 irqreturn_t ret = IRQ_NONE; 2062 int port = mvp->port; 2063 u8 lane; 2064 2065 mv88e6xxx_reg_lock(chip); 2066 lane = mv88e6xxx_serdes_get_lane(chip, port); 2067 if (lane) 2068 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2069 mv88e6xxx_reg_unlock(chip); 2070 2071 return ret; 2072 } 2073 2074 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2075 u8 lane) 2076 { 2077 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2078 unsigned int irq; 2079 int err; 2080 2081 /* Nothing to request if this SERDES port has no IRQ */ 2082 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2083 if (!irq) 2084 return 0; 2085 2086 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2087 mv88e6xxx_reg_unlock(chip); 2088 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2089 IRQF_ONESHOT, "mv88e6xxx-serdes", dev_id); 2090 mv88e6xxx_reg_lock(chip); 2091 if (err) 2092 return err; 2093 2094 dev_id->serdes_irq = irq; 2095 2096 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2097 } 2098 2099 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2100 u8 lane) 2101 { 2102 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2103 unsigned int irq = dev_id->serdes_irq; 2104 int err; 2105 2106 /* Nothing to free if no IRQ has been requested */ 2107 if (!irq) 2108 return 0; 2109 2110 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2111 2112 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2113 mv88e6xxx_reg_unlock(chip); 2114 free_irq(irq, dev_id); 2115 mv88e6xxx_reg_lock(chip); 2116 2117 dev_id->serdes_irq = 0; 2118 2119 return err; 2120 } 2121 2122 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2123 bool on) 2124 { 2125 u8 lane; 2126 int err; 2127 2128 lane = mv88e6xxx_serdes_get_lane(chip, port); 2129 if (!lane) 2130 return 0; 2131 2132 if (on) { 2133 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2134 if (err) 2135 return err; 2136 2137 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2138 } else { 2139 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2140 if (err) 2141 return err; 2142 2143 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2144 } 2145 2146 return err; 2147 } 2148 2149 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2150 { 2151 struct dsa_switch *ds = chip->ds; 2152 int upstream_port; 2153 int err; 2154 2155 upstream_port = dsa_upstream_port(ds, port); 2156 if (chip->info->ops->port_set_upstream_port) { 2157 err = chip->info->ops->port_set_upstream_port(chip, port, 2158 upstream_port); 2159 if (err) 2160 return err; 2161 } 2162 2163 if (port == upstream_port) { 2164 if (chip->info->ops->set_cpu_port) { 2165 err = chip->info->ops->set_cpu_port(chip, 2166 upstream_port); 2167 if (err) 2168 return err; 2169 } 2170 2171 if (chip->info->ops->set_egress_port) { 2172 err = chip->info->ops->set_egress_port(chip, 2173 upstream_port); 2174 if (err) 2175 return err; 2176 } 2177 } 2178 2179 return 0; 2180 } 2181 2182 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2183 { 2184 struct dsa_switch *ds = chip->ds; 2185 int err; 2186 u16 reg; 2187 2188 chip->ports[port].chip = chip; 2189 chip->ports[port].port = port; 2190 2191 /* MAC Forcing register: don't force link, speed, duplex or flow control 2192 * state to any particular values on physical ports, but force the CPU 2193 * port and all DSA ports to their maximum bandwidth and full duplex. 2194 */ 2195 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2196 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2197 SPEED_MAX, DUPLEX_FULL, 2198 PAUSE_OFF, 2199 PHY_INTERFACE_MODE_NA); 2200 else 2201 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2202 SPEED_UNFORCED, DUPLEX_UNFORCED, 2203 PAUSE_ON, 2204 PHY_INTERFACE_MODE_NA); 2205 if (err) 2206 return err; 2207 2208 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2209 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2210 * tunneling, determine priority by looking at 802.1p and IP 2211 * priority fields (IP prio has precedence), and set STP state 2212 * to Forwarding. 2213 * 2214 * If this is the CPU link, use DSA or EDSA tagging depending 2215 * on which tagging mode was configured. 2216 * 2217 * If this is a link to another switch, use DSA tagging mode. 2218 * 2219 * If this is the upstream port for this switch, enable 2220 * forwarding of unknown unicasts and multicasts. 2221 */ 2222 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2223 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2224 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2225 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2226 if (err) 2227 return err; 2228 2229 err = mv88e6xxx_setup_port_mode(chip, port); 2230 if (err) 2231 return err; 2232 2233 err = mv88e6xxx_setup_egress_floods(chip, port); 2234 if (err) 2235 return err; 2236 2237 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2238 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2239 * untagged frames on this port, do a destination address lookup on all 2240 * received packets as usual, disable ARP mirroring and don't send a 2241 * copy of all transmitted/received frames on this port to the CPU. 2242 */ 2243 err = mv88e6xxx_port_set_map_da(chip, port); 2244 if (err) 2245 return err; 2246 2247 err = mv88e6xxx_setup_upstream_port(chip, port); 2248 if (err) 2249 return err; 2250 2251 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2252 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2253 if (err) 2254 return err; 2255 2256 if (chip->info->ops->port_set_jumbo_size) { 2257 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2258 if (err) 2259 return err; 2260 } 2261 2262 /* Port Association Vector: when learning source addresses 2263 * of packets, add the address to the address database using 2264 * a port bitmap that has only the bit for this port set and 2265 * the other bits clear. 2266 */ 2267 reg = 1 << port; 2268 /* Disable learning for CPU port */ 2269 if (dsa_is_cpu_port(ds, port)) 2270 reg = 0; 2271 2272 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2273 reg); 2274 if (err) 2275 return err; 2276 2277 /* Egress rate control 2: disable egress rate control. */ 2278 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2279 0x0000); 2280 if (err) 2281 return err; 2282 2283 if (chip->info->ops->port_pause_limit) { 2284 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2285 if (err) 2286 return err; 2287 } 2288 2289 if (chip->info->ops->port_disable_learn_limit) { 2290 err = chip->info->ops->port_disable_learn_limit(chip, port); 2291 if (err) 2292 return err; 2293 } 2294 2295 if (chip->info->ops->port_disable_pri_override) { 2296 err = chip->info->ops->port_disable_pri_override(chip, port); 2297 if (err) 2298 return err; 2299 } 2300 2301 if (chip->info->ops->port_tag_remap) { 2302 err = chip->info->ops->port_tag_remap(chip, port); 2303 if (err) 2304 return err; 2305 } 2306 2307 if (chip->info->ops->port_egress_rate_limiting) { 2308 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2309 if (err) 2310 return err; 2311 } 2312 2313 if (chip->info->ops->port_setup_message_port) { 2314 err = chip->info->ops->port_setup_message_port(chip, port); 2315 if (err) 2316 return err; 2317 } 2318 2319 /* Port based VLAN map: give each port the same default address 2320 * database, and allow bidirectional communication between the 2321 * CPU and DSA port(s), and the other ports. 2322 */ 2323 err = mv88e6xxx_port_set_fid(chip, port, 0); 2324 if (err) 2325 return err; 2326 2327 err = mv88e6xxx_port_vlan_map(chip, port); 2328 if (err) 2329 return err; 2330 2331 /* Default VLAN ID and priority: don't set a default VLAN 2332 * ID, and set the default packet priority to zero. 2333 */ 2334 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2335 } 2336 2337 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2338 struct phy_device *phydev) 2339 { 2340 struct mv88e6xxx_chip *chip = ds->priv; 2341 int err; 2342 2343 mv88e6xxx_reg_lock(chip); 2344 err = mv88e6xxx_serdes_power(chip, port, true); 2345 mv88e6xxx_reg_unlock(chip); 2346 2347 return err; 2348 } 2349 2350 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2351 { 2352 struct mv88e6xxx_chip *chip = ds->priv; 2353 2354 mv88e6xxx_reg_lock(chip); 2355 if (mv88e6xxx_serdes_power(chip, port, false)) 2356 dev_err(chip->dev, "failed to power off SERDES\n"); 2357 mv88e6xxx_reg_unlock(chip); 2358 } 2359 2360 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2361 unsigned int ageing_time) 2362 { 2363 struct mv88e6xxx_chip *chip = ds->priv; 2364 int err; 2365 2366 mv88e6xxx_reg_lock(chip); 2367 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2368 mv88e6xxx_reg_unlock(chip); 2369 2370 return err; 2371 } 2372 2373 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2374 { 2375 int err; 2376 2377 /* Initialize the statistics unit */ 2378 if (chip->info->ops->stats_set_histogram) { 2379 err = chip->info->ops->stats_set_histogram(chip); 2380 if (err) 2381 return err; 2382 } 2383 2384 return mv88e6xxx_g1_stats_clear(chip); 2385 } 2386 2387 /* Check if the errata has already been applied. */ 2388 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2389 { 2390 int port; 2391 int err; 2392 u16 val; 2393 2394 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2395 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2396 if (err) { 2397 dev_err(chip->dev, 2398 "Error reading hidden register: %d\n", err); 2399 return false; 2400 } 2401 if (val != 0x01c0) 2402 return false; 2403 } 2404 2405 return true; 2406 } 2407 2408 /* The 6390 copper ports have an errata which require poking magic 2409 * values into undocumented hidden registers and then performing a 2410 * software reset. 2411 */ 2412 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2413 { 2414 int port; 2415 int err; 2416 2417 if (mv88e6390_setup_errata_applied(chip)) 2418 return 0; 2419 2420 /* Set the ports into blocking mode */ 2421 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2422 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2423 if (err) 2424 return err; 2425 } 2426 2427 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2428 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2429 if (err) 2430 return err; 2431 } 2432 2433 return mv88e6xxx_software_reset(chip); 2434 } 2435 2436 static int mv88e6xxx_setup(struct dsa_switch *ds) 2437 { 2438 struct mv88e6xxx_chip *chip = ds->priv; 2439 u8 cmode; 2440 int err; 2441 int i; 2442 2443 chip->ds = ds; 2444 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2445 2446 mv88e6xxx_reg_lock(chip); 2447 2448 if (chip->info->ops->setup_errata) { 2449 err = chip->info->ops->setup_errata(chip); 2450 if (err) 2451 goto unlock; 2452 } 2453 2454 /* Cache the cmode of each port. */ 2455 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2456 if (chip->info->ops->port_get_cmode) { 2457 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2458 if (err) 2459 goto unlock; 2460 2461 chip->ports[i].cmode = cmode; 2462 } 2463 } 2464 2465 /* Setup Switch Port Registers */ 2466 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2467 if (dsa_is_unused_port(ds, i)) 2468 continue; 2469 2470 /* Prevent the use of an invalid port. */ 2471 if (mv88e6xxx_is_invalid_port(chip, i)) { 2472 dev_err(chip->dev, "port %d is invalid\n", i); 2473 err = -EINVAL; 2474 goto unlock; 2475 } 2476 2477 err = mv88e6xxx_setup_port(chip, i); 2478 if (err) 2479 goto unlock; 2480 } 2481 2482 err = mv88e6xxx_irl_setup(chip); 2483 if (err) 2484 goto unlock; 2485 2486 err = mv88e6xxx_mac_setup(chip); 2487 if (err) 2488 goto unlock; 2489 2490 err = mv88e6xxx_phy_setup(chip); 2491 if (err) 2492 goto unlock; 2493 2494 err = mv88e6xxx_vtu_setup(chip); 2495 if (err) 2496 goto unlock; 2497 2498 err = mv88e6xxx_pvt_setup(chip); 2499 if (err) 2500 goto unlock; 2501 2502 err = mv88e6xxx_atu_setup(chip); 2503 if (err) 2504 goto unlock; 2505 2506 err = mv88e6xxx_broadcast_setup(chip, 0); 2507 if (err) 2508 goto unlock; 2509 2510 err = mv88e6xxx_pot_setup(chip); 2511 if (err) 2512 goto unlock; 2513 2514 err = mv88e6xxx_rmu_setup(chip); 2515 if (err) 2516 goto unlock; 2517 2518 err = mv88e6xxx_rsvd2cpu_setup(chip); 2519 if (err) 2520 goto unlock; 2521 2522 err = mv88e6xxx_trunk_setup(chip); 2523 if (err) 2524 goto unlock; 2525 2526 err = mv88e6xxx_devmap_setup(chip); 2527 if (err) 2528 goto unlock; 2529 2530 err = mv88e6xxx_pri_setup(chip); 2531 if (err) 2532 goto unlock; 2533 2534 /* Setup PTP Hardware Clock and timestamping */ 2535 if (chip->info->ptp_support) { 2536 err = mv88e6xxx_ptp_setup(chip); 2537 if (err) 2538 goto unlock; 2539 2540 err = mv88e6xxx_hwtstamp_setup(chip); 2541 if (err) 2542 goto unlock; 2543 } 2544 2545 err = mv88e6xxx_stats_setup(chip); 2546 if (err) 2547 goto unlock; 2548 2549 unlock: 2550 mv88e6xxx_reg_unlock(chip); 2551 2552 return err; 2553 } 2554 2555 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2556 { 2557 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2558 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2559 u16 val; 2560 int err; 2561 2562 if (!chip->info->ops->phy_read) 2563 return -EOPNOTSUPP; 2564 2565 mv88e6xxx_reg_lock(chip); 2566 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2567 mv88e6xxx_reg_unlock(chip); 2568 2569 if (reg == MII_PHYSID2) { 2570 /* Some internal PHYs don't have a model number. */ 2571 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2572 /* Then there is the 6165 family. It gets is 2573 * PHYs correct. But it can also have two 2574 * SERDES interfaces in the PHY address 2575 * space. And these don't have a model 2576 * number. But they are not PHYs, so we don't 2577 * want to give them something a PHY driver 2578 * will recognise. 2579 * 2580 * Use the mv88e6390 family model number 2581 * instead, for anything which really could be 2582 * a PHY, 2583 */ 2584 if (!(val & 0x3f0)) 2585 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2586 } 2587 2588 return err ? err : val; 2589 } 2590 2591 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2592 { 2593 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2594 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2595 int err; 2596 2597 if (!chip->info->ops->phy_write) 2598 return -EOPNOTSUPP; 2599 2600 mv88e6xxx_reg_lock(chip); 2601 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2602 mv88e6xxx_reg_unlock(chip); 2603 2604 return err; 2605 } 2606 2607 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2608 struct device_node *np, 2609 bool external) 2610 { 2611 static int index; 2612 struct mv88e6xxx_mdio_bus *mdio_bus; 2613 struct mii_bus *bus; 2614 int err; 2615 2616 if (external) { 2617 mv88e6xxx_reg_lock(chip); 2618 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2619 mv88e6xxx_reg_unlock(chip); 2620 2621 if (err) 2622 return err; 2623 } 2624 2625 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2626 if (!bus) 2627 return -ENOMEM; 2628 2629 mdio_bus = bus->priv; 2630 mdio_bus->bus = bus; 2631 mdio_bus->chip = chip; 2632 INIT_LIST_HEAD(&mdio_bus->list); 2633 mdio_bus->external = external; 2634 2635 if (np) { 2636 bus->name = np->full_name; 2637 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2638 } else { 2639 bus->name = "mv88e6xxx SMI"; 2640 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2641 } 2642 2643 bus->read = mv88e6xxx_mdio_read; 2644 bus->write = mv88e6xxx_mdio_write; 2645 bus->parent = chip->dev; 2646 2647 if (!external) { 2648 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2649 if (err) 2650 return err; 2651 } 2652 2653 err = of_mdiobus_register(bus, np); 2654 if (err) { 2655 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2656 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2657 return err; 2658 } 2659 2660 if (external) 2661 list_add_tail(&mdio_bus->list, &chip->mdios); 2662 else 2663 list_add(&mdio_bus->list, &chip->mdios); 2664 2665 return 0; 2666 } 2667 2668 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2669 { .compatible = "marvell,mv88e6xxx-mdio-external", 2670 .data = (void *)true }, 2671 { }, 2672 }; 2673 2674 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2675 2676 { 2677 struct mv88e6xxx_mdio_bus *mdio_bus; 2678 struct mii_bus *bus; 2679 2680 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2681 bus = mdio_bus->bus; 2682 2683 if (!mdio_bus->external) 2684 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2685 2686 mdiobus_unregister(bus); 2687 } 2688 } 2689 2690 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2691 struct device_node *np) 2692 { 2693 const struct of_device_id *match; 2694 struct device_node *child; 2695 int err; 2696 2697 /* Always register one mdio bus for the internal/default mdio 2698 * bus. This maybe represented in the device tree, but is 2699 * optional. 2700 */ 2701 child = of_get_child_by_name(np, "mdio"); 2702 err = mv88e6xxx_mdio_register(chip, child, false); 2703 if (err) 2704 return err; 2705 2706 /* Walk the device tree, and see if there are any other nodes 2707 * which say they are compatible with the external mdio 2708 * bus. 2709 */ 2710 for_each_available_child_of_node(np, child) { 2711 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2712 if (match) { 2713 err = mv88e6xxx_mdio_register(chip, child, true); 2714 if (err) { 2715 mv88e6xxx_mdios_unregister(chip); 2716 of_node_put(child); 2717 return err; 2718 } 2719 } 2720 } 2721 2722 return 0; 2723 } 2724 2725 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2726 { 2727 struct mv88e6xxx_chip *chip = ds->priv; 2728 2729 return chip->eeprom_len; 2730 } 2731 2732 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2733 struct ethtool_eeprom *eeprom, u8 *data) 2734 { 2735 struct mv88e6xxx_chip *chip = ds->priv; 2736 int err; 2737 2738 if (!chip->info->ops->get_eeprom) 2739 return -EOPNOTSUPP; 2740 2741 mv88e6xxx_reg_lock(chip); 2742 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2743 mv88e6xxx_reg_unlock(chip); 2744 2745 if (err) 2746 return err; 2747 2748 eeprom->magic = 0xc3ec4951; 2749 2750 return 0; 2751 } 2752 2753 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2754 struct ethtool_eeprom *eeprom, u8 *data) 2755 { 2756 struct mv88e6xxx_chip *chip = ds->priv; 2757 int err; 2758 2759 if (!chip->info->ops->set_eeprom) 2760 return -EOPNOTSUPP; 2761 2762 if (eeprom->magic != 0xc3ec4951) 2763 return -EINVAL; 2764 2765 mv88e6xxx_reg_lock(chip); 2766 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2767 mv88e6xxx_reg_unlock(chip); 2768 2769 return err; 2770 } 2771 2772 static const struct mv88e6xxx_ops mv88e6085_ops = { 2773 /* MV88E6XXX_FAMILY_6097 */ 2774 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2775 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2776 .irl_init_all = mv88e6352_g2_irl_init_all, 2777 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2778 .phy_read = mv88e6185_phy_ppu_read, 2779 .phy_write = mv88e6185_phy_ppu_write, 2780 .port_set_link = mv88e6xxx_port_set_link, 2781 .port_set_duplex = mv88e6xxx_port_set_duplex, 2782 .port_set_speed = mv88e6185_port_set_speed, 2783 .port_tag_remap = mv88e6095_port_tag_remap, 2784 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2785 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2786 .port_set_ether_type = mv88e6351_port_set_ether_type, 2787 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2788 .port_pause_limit = mv88e6097_port_pause_limit, 2789 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2790 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2791 .port_link_state = mv88e6352_port_link_state, 2792 .port_get_cmode = mv88e6185_port_get_cmode, 2793 .port_setup_message_port = mv88e6xxx_setup_message_port, 2794 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2795 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2796 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2797 .stats_get_strings = mv88e6095_stats_get_strings, 2798 .stats_get_stats = mv88e6095_stats_get_stats, 2799 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2800 .set_egress_port = mv88e6095_g1_set_egress_port, 2801 .watchdog_ops = &mv88e6097_watchdog_ops, 2802 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2803 .pot_clear = mv88e6xxx_g2_pot_clear, 2804 .ppu_enable = mv88e6185_g1_ppu_enable, 2805 .ppu_disable = mv88e6185_g1_ppu_disable, 2806 .reset = mv88e6185_g1_reset, 2807 .rmu_disable = mv88e6085_g1_rmu_disable, 2808 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2809 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2810 .phylink_validate = mv88e6185_phylink_validate, 2811 }; 2812 2813 static const struct mv88e6xxx_ops mv88e6095_ops = { 2814 /* MV88E6XXX_FAMILY_6095 */ 2815 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2816 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2817 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2818 .phy_read = mv88e6185_phy_ppu_read, 2819 .phy_write = mv88e6185_phy_ppu_write, 2820 .port_set_link = mv88e6xxx_port_set_link, 2821 .port_set_duplex = mv88e6xxx_port_set_duplex, 2822 .port_set_speed = mv88e6185_port_set_speed, 2823 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2824 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2825 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2826 .port_link_state = mv88e6185_port_link_state, 2827 .port_get_cmode = mv88e6185_port_get_cmode, 2828 .port_setup_message_port = mv88e6xxx_setup_message_port, 2829 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2830 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2831 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2832 .stats_get_strings = mv88e6095_stats_get_strings, 2833 .stats_get_stats = mv88e6095_stats_get_stats, 2834 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2835 .ppu_enable = mv88e6185_g1_ppu_enable, 2836 .ppu_disable = mv88e6185_g1_ppu_disable, 2837 .reset = mv88e6185_g1_reset, 2838 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2839 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2840 .phylink_validate = mv88e6185_phylink_validate, 2841 }; 2842 2843 static const struct mv88e6xxx_ops mv88e6097_ops = { 2844 /* MV88E6XXX_FAMILY_6097 */ 2845 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2846 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2847 .irl_init_all = mv88e6352_g2_irl_init_all, 2848 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2849 .phy_read = mv88e6xxx_g2_smi_phy_read, 2850 .phy_write = mv88e6xxx_g2_smi_phy_write, 2851 .port_set_link = mv88e6xxx_port_set_link, 2852 .port_set_duplex = mv88e6xxx_port_set_duplex, 2853 .port_set_speed = mv88e6185_port_set_speed, 2854 .port_tag_remap = mv88e6095_port_tag_remap, 2855 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2856 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2857 .port_set_ether_type = mv88e6351_port_set_ether_type, 2858 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2859 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2860 .port_pause_limit = mv88e6097_port_pause_limit, 2861 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2862 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2863 .port_link_state = mv88e6352_port_link_state, 2864 .port_get_cmode = mv88e6185_port_get_cmode, 2865 .port_setup_message_port = mv88e6xxx_setup_message_port, 2866 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2867 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2868 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2869 .stats_get_strings = mv88e6095_stats_get_strings, 2870 .stats_get_stats = mv88e6095_stats_get_stats, 2871 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2872 .set_egress_port = mv88e6095_g1_set_egress_port, 2873 .watchdog_ops = &mv88e6097_watchdog_ops, 2874 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2875 .pot_clear = mv88e6xxx_g2_pot_clear, 2876 .reset = mv88e6352_g1_reset, 2877 .rmu_disable = mv88e6085_g1_rmu_disable, 2878 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2879 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2880 .phylink_validate = mv88e6185_phylink_validate, 2881 }; 2882 2883 static const struct mv88e6xxx_ops mv88e6123_ops = { 2884 /* MV88E6XXX_FAMILY_6165 */ 2885 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2886 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2887 .irl_init_all = mv88e6352_g2_irl_init_all, 2888 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2889 .phy_read = mv88e6xxx_g2_smi_phy_read, 2890 .phy_write = mv88e6xxx_g2_smi_phy_write, 2891 .port_set_link = mv88e6xxx_port_set_link, 2892 .port_set_duplex = mv88e6xxx_port_set_duplex, 2893 .port_set_speed = mv88e6185_port_set_speed, 2894 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2895 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2896 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2897 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2898 .port_link_state = mv88e6352_port_link_state, 2899 .port_get_cmode = mv88e6185_port_get_cmode, 2900 .port_setup_message_port = mv88e6xxx_setup_message_port, 2901 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2902 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2903 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2904 .stats_get_strings = mv88e6095_stats_get_strings, 2905 .stats_get_stats = mv88e6095_stats_get_stats, 2906 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2907 .set_egress_port = mv88e6095_g1_set_egress_port, 2908 .watchdog_ops = &mv88e6097_watchdog_ops, 2909 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2910 .pot_clear = mv88e6xxx_g2_pot_clear, 2911 .reset = mv88e6352_g1_reset, 2912 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2913 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2914 .phylink_validate = mv88e6185_phylink_validate, 2915 }; 2916 2917 static const struct mv88e6xxx_ops mv88e6131_ops = { 2918 /* MV88E6XXX_FAMILY_6185 */ 2919 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2920 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2921 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2922 .phy_read = mv88e6185_phy_ppu_read, 2923 .phy_write = mv88e6185_phy_ppu_write, 2924 .port_set_link = mv88e6xxx_port_set_link, 2925 .port_set_duplex = mv88e6xxx_port_set_duplex, 2926 .port_set_speed = mv88e6185_port_set_speed, 2927 .port_tag_remap = mv88e6095_port_tag_remap, 2928 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2929 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2930 .port_set_ether_type = mv88e6351_port_set_ether_type, 2931 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2932 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2933 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2934 .port_pause_limit = mv88e6097_port_pause_limit, 2935 .port_set_pause = mv88e6185_port_set_pause, 2936 .port_link_state = mv88e6352_port_link_state, 2937 .port_get_cmode = mv88e6185_port_get_cmode, 2938 .port_setup_message_port = mv88e6xxx_setup_message_port, 2939 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2940 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2941 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2942 .stats_get_strings = mv88e6095_stats_get_strings, 2943 .stats_get_stats = mv88e6095_stats_get_stats, 2944 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2945 .set_egress_port = mv88e6095_g1_set_egress_port, 2946 .watchdog_ops = &mv88e6097_watchdog_ops, 2947 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2948 .ppu_enable = mv88e6185_g1_ppu_enable, 2949 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2950 .ppu_disable = mv88e6185_g1_ppu_disable, 2951 .reset = mv88e6185_g1_reset, 2952 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2953 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2954 .phylink_validate = mv88e6185_phylink_validate, 2955 }; 2956 2957 static const struct mv88e6xxx_ops mv88e6141_ops = { 2958 /* MV88E6XXX_FAMILY_6341 */ 2959 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2960 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2961 .irl_init_all = mv88e6352_g2_irl_init_all, 2962 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2963 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2964 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2965 .phy_read = mv88e6xxx_g2_smi_phy_read, 2966 .phy_write = mv88e6xxx_g2_smi_phy_write, 2967 .port_set_link = mv88e6xxx_port_set_link, 2968 .port_set_duplex = mv88e6xxx_port_set_duplex, 2969 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2970 .port_set_speed = mv88e6341_port_set_speed, 2971 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 2972 .port_tag_remap = mv88e6095_port_tag_remap, 2973 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2974 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2975 .port_set_ether_type = mv88e6351_port_set_ether_type, 2976 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2977 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2978 .port_pause_limit = mv88e6097_port_pause_limit, 2979 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2980 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2981 .port_link_state = mv88e6352_port_link_state, 2982 .port_get_cmode = mv88e6352_port_get_cmode, 2983 .port_set_cmode = mv88e6341_port_set_cmode, 2984 .port_setup_message_port = mv88e6xxx_setup_message_port, 2985 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2986 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2987 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2988 .stats_get_strings = mv88e6320_stats_get_strings, 2989 .stats_get_stats = mv88e6390_stats_get_stats, 2990 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2991 .set_egress_port = mv88e6390_g1_set_egress_port, 2992 .watchdog_ops = &mv88e6390_watchdog_ops, 2993 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2994 .pot_clear = mv88e6xxx_g2_pot_clear, 2995 .reset = mv88e6352_g1_reset, 2996 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2997 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2998 .serdes_power = mv88e6390_serdes_power, 2999 .serdes_get_lane = mv88e6341_serdes_get_lane, 3000 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3001 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3002 .serdes_irq_status = mv88e6390_serdes_irq_status, 3003 .gpio_ops = &mv88e6352_gpio_ops, 3004 .phylink_validate = mv88e6341_phylink_validate, 3005 }; 3006 3007 static const struct mv88e6xxx_ops mv88e6161_ops = { 3008 /* MV88E6XXX_FAMILY_6165 */ 3009 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3010 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3011 .irl_init_all = mv88e6352_g2_irl_init_all, 3012 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3013 .phy_read = mv88e6xxx_g2_smi_phy_read, 3014 .phy_write = mv88e6xxx_g2_smi_phy_write, 3015 .port_set_link = mv88e6xxx_port_set_link, 3016 .port_set_duplex = mv88e6xxx_port_set_duplex, 3017 .port_set_speed = mv88e6185_port_set_speed, 3018 .port_tag_remap = mv88e6095_port_tag_remap, 3019 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3020 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3021 .port_set_ether_type = mv88e6351_port_set_ether_type, 3022 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3023 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3024 .port_pause_limit = mv88e6097_port_pause_limit, 3025 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3026 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3027 .port_link_state = mv88e6352_port_link_state, 3028 .port_get_cmode = mv88e6185_port_get_cmode, 3029 .port_setup_message_port = mv88e6xxx_setup_message_port, 3030 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3031 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3032 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3033 .stats_get_strings = mv88e6095_stats_get_strings, 3034 .stats_get_stats = mv88e6095_stats_get_stats, 3035 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3036 .set_egress_port = mv88e6095_g1_set_egress_port, 3037 .watchdog_ops = &mv88e6097_watchdog_ops, 3038 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3039 .pot_clear = mv88e6xxx_g2_pot_clear, 3040 .reset = mv88e6352_g1_reset, 3041 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3042 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3043 .avb_ops = &mv88e6165_avb_ops, 3044 .ptp_ops = &mv88e6165_ptp_ops, 3045 .phylink_validate = mv88e6185_phylink_validate, 3046 }; 3047 3048 static const struct mv88e6xxx_ops mv88e6165_ops = { 3049 /* MV88E6XXX_FAMILY_6165 */ 3050 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3051 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3052 .irl_init_all = mv88e6352_g2_irl_init_all, 3053 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3054 .phy_read = mv88e6165_phy_read, 3055 .phy_write = mv88e6165_phy_write, 3056 .port_set_link = mv88e6xxx_port_set_link, 3057 .port_set_duplex = mv88e6xxx_port_set_duplex, 3058 .port_set_speed = mv88e6185_port_set_speed, 3059 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3060 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3061 .port_link_state = mv88e6352_port_link_state, 3062 .port_get_cmode = mv88e6185_port_get_cmode, 3063 .port_setup_message_port = mv88e6xxx_setup_message_port, 3064 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3065 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3066 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3067 .stats_get_strings = mv88e6095_stats_get_strings, 3068 .stats_get_stats = mv88e6095_stats_get_stats, 3069 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3070 .set_egress_port = mv88e6095_g1_set_egress_port, 3071 .watchdog_ops = &mv88e6097_watchdog_ops, 3072 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3073 .pot_clear = mv88e6xxx_g2_pot_clear, 3074 .reset = mv88e6352_g1_reset, 3075 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3076 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3077 .avb_ops = &mv88e6165_avb_ops, 3078 .ptp_ops = &mv88e6165_ptp_ops, 3079 .phylink_validate = mv88e6185_phylink_validate, 3080 }; 3081 3082 static const struct mv88e6xxx_ops mv88e6171_ops = { 3083 /* MV88E6XXX_FAMILY_6351 */ 3084 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3085 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3086 .irl_init_all = mv88e6352_g2_irl_init_all, 3087 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3088 .phy_read = mv88e6xxx_g2_smi_phy_read, 3089 .phy_write = mv88e6xxx_g2_smi_phy_write, 3090 .port_set_link = mv88e6xxx_port_set_link, 3091 .port_set_duplex = mv88e6xxx_port_set_duplex, 3092 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3093 .port_set_speed = mv88e6185_port_set_speed, 3094 .port_tag_remap = mv88e6095_port_tag_remap, 3095 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3096 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3097 .port_set_ether_type = mv88e6351_port_set_ether_type, 3098 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3099 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3100 .port_pause_limit = mv88e6097_port_pause_limit, 3101 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3102 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3103 .port_link_state = mv88e6352_port_link_state, 3104 .port_get_cmode = mv88e6352_port_get_cmode, 3105 .port_setup_message_port = mv88e6xxx_setup_message_port, 3106 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3107 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3108 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3109 .stats_get_strings = mv88e6095_stats_get_strings, 3110 .stats_get_stats = mv88e6095_stats_get_stats, 3111 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3112 .set_egress_port = mv88e6095_g1_set_egress_port, 3113 .watchdog_ops = &mv88e6097_watchdog_ops, 3114 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3115 .pot_clear = mv88e6xxx_g2_pot_clear, 3116 .reset = mv88e6352_g1_reset, 3117 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3118 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3119 .phylink_validate = mv88e6185_phylink_validate, 3120 }; 3121 3122 static const struct mv88e6xxx_ops mv88e6172_ops = { 3123 /* MV88E6XXX_FAMILY_6352 */ 3124 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3125 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3126 .irl_init_all = mv88e6352_g2_irl_init_all, 3127 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3128 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3129 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3130 .phy_read = mv88e6xxx_g2_smi_phy_read, 3131 .phy_write = mv88e6xxx_g2_smi_phy_write, 3132 .port_set_link = mv88e6xxx_port_set_link, 3133 .port_set_duplex = mv88e6xxx_port_set_duplex, 3134 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3135 .port_set_speed = mv88e6352_port_set_speed, 3136 .port_tag_remap = mv88e6095_port_tag_remap, 3137 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3138 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3139 .port_set_ether_type = mv88e6351_port_set_ether_type, 3140 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3141 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3142 .port_pause_limit = mv88e6097_port_pause_limit, 3143 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3144 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3145 .port_link_state = mv88e6352_port_link_state, 3146 .port_get_cmode = mv88e6352_port_get_cmode, 3147 .port_setup_message_port = mv88e6xxx_setup_message_port, 3148 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3149 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3150 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3151 .stats_get_strings = mv88e6095_stats_get_strings, 3152 .stats_get_stats = mv88e6095_stats_get_stats, 3153 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3154 .set_egress_port = mv88e6095_g1_set_egress_port, 3155 .watchdog_ops = &mv88e6097_watchdog_ops, 3156 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3157 .pot_clear = mv88e6xxx_g2_pot_clear, 3158 .reset = mv88e6352_g1_reset, 3159 .rmu_disable = mv88e6352_g1_rmu_disable, 3160 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3161 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3162 .serdes_get_lane = mv88e6352_serdes_get_lane, 3163 .serdes_power = mv88e6352_serdes_power, 3164 .gpio_ops = &mv88e6352_gpio_ops, 3165 .phylink_validate = mv88e6352_phylink_validate, 3166 }; 3167 3168 static const struct mv88e6xxx_ops mv88e6175_ops = { 3169 /* MV88E6XXX_FAMILY_6351 */ 3170 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3171 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3172 .irl_init_all = mv88e6352_g2_irl_init_all, 3173 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3174 .phy_read = mv88e6xxx_g2_smi_phy_read, 3175 .phy_write = mv88e6xxx_g2_smi_phy_write, 3176 .port_set_link = mv88e6xxx_port_set_link, 3177 .port_set_duplex = mv88e6xxx_port_set_duplex, 3178 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3179 .port_set_speed = mv88e6185_port_set_speed, 3180 .port_tag_remap = mv88e6095_port_tag_remap, 3181 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3182 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3183 .port_set_ether_type = mv88e6351_port_set_ether_type, 3184 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3185 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3186 .port_pause_limit = mv88e6097_port_pause_limit, 3187 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3188 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3189 .port_link_state = mv88e6352_port_link_state, 3190 .port_get_cmode = mv88e6352_port_get_cmode, 3191 .port_setup_message_port = mv88e6xxx_setup_message_port, 3192 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3193 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3194 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3195 .stats_get_strings = mv88e6095_stats_get_strings, 3196 .stats_get_stats = mv88e6095_stats_get_stats, 3197 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3198 .set_egress_port = mv88e6095_g1_set_egress_port, 3199 .watchdog_ops = &mv88e6097_watchdog_ops, 3200 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3201 .pot_clear = mv88e6xxx_g2_pot_clear, 3202 .reset = mv88e6352_g1_reset, 3203 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3204 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3205 .phylink_validate = mv88e6185_phylink_validate, 3206 }; 3207 3208 static const struct mv88e6xxx_ops mv88e6176_ops = { 3209 /* MV88E6XXX_FAMILY_6352 */ 3210 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3211 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3212 .irl_init_all = mv88e6352_g2_irl_init_all, 3213 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3214 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3215 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3216 .phy_read = mv88e6xxx_g2_smi_phy_read, 3217 .phy_write = mv88e6xxx_g2_smi_phy_write, 3218 .port_set_link = mv88e6xxx_port_set_link, 3219 .port_set_duplex = mv88e6xxx_port_set_duplex, 3220 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3221 .port_set_speed = mv88e6352_port_set_speed, 3222 .port_tag_remap = mv88e6095_port_tag_remap, 3223 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3224 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3225 .port_set_ether_type = mv88e6351_port_set_ether_type, 3226 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3227 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3228 .port_pause_limit = mv88e6097_port_pause_limit, 3229 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3230 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3231 .port_link_state = mv88e6352_port_link_state, 3232 .port_get_cmode = mv88e6352_port_get_cmode, 3233 .port_setup_message_port = mv88e6xxx_setup_message_port, 3234 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3235 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3236 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3237 .stats_get_strings = mv88e6095_stats_get_strings, 3238 .stats_get_stats = mv88e6095_stats_get_stats, 3239 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3240 .set_egress_port = mv88e6095_g1_set_egress_port, 3241 .watchdog_ops = &mv88e6097_watchdog_ops, 3242 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3243 .pot_clear = mv88e6xxx_g2_pot_clear, 3244 .reset = mv88e6352_g1_reset, 3245 .rmu_disable = mv88e6352_g1_rmu_disable, 3246 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3247 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3248 .serdes_get_lane = mv88e6352_serdes_get_lane, 3249 .serdes_power = mv88e6352_serdes_power, 3250 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3251 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3252 .serdes_irq_status = mv88e6352_serdes_irq_status, 3253 .gpio_ops = &mv88e6352_gpio_ops, 3254 .phylink_validate = mv88e6352_phylink_validate, 3255 }; 3256 3257 static const struct mv88e6xxx_ops mv88e6185_ops = { 3258 /* MV88E6XXX_FAMILY_6185 */ 3259 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3260 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3261 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3262 .phy_read = mv88e6185_phy_ppu_read, 3263 .phy_write = mv88e6185_phy_ppu_write, 3264 .port_set_link = mv88e6xxx_port_set_link, 3265 .port_set_duplex = mv88e6xxx_port_set_duplex, 3266 .port_set_speed = mv88e6185_port_set_speed, 3267 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3268 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3269 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3270 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3271 .port_set_pause = mv88e6185_port_set_pause, 3272 .port_link_state = mv88e6185_port_link_state, 3273 .port_get_cmode = mv88e6185_port_get_cmode, 3274 .port_setup_message_port = mv88e6xxx_setup_message_port, 3275 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3276 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3277 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3278 .stats_get_strings = mv88e6095_stats_get_strings, 3279 .stats_get_stats = mv88e6095_stats_get_stats, 3280 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3281 .set_egress_port = mv88e6095_g1_set_egress_port, 3282 .watchdog_ops = &mv88e6097_watchdog_ops, 3283 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3284 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3285 .ppu_enable = mv88e6185_g1_ppu_enable, 3286 .ppu_disable = mv88e6185_g1_ppu_disable, 3287 .reset = mv88e6185_g1_reset, 3288 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3289 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3290 .phylink_validate = mv88e6185_phylink_validate, 3291 }; 3292 3293 static const struct mv88e6xxx_ops mv88e6190_ops = { 3294 /* MV88E6XXX_FAMILY_6390 */ 3295 .setup_errata = mv88e6390_setup_errata, 3296 .irl_init_all = mv88e6390_g2_irl_init_all, 3297 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3298 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3299 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3300 .phy_read = mv88e6xxx_g2_smi_phy_read, 3301 .phy_write = mv88e6xxx_g2_smi_phy_write, 3302 .port_set_link = mv88e6xxx_port_set_link, 3303 .port_set_duplex = mv88e6xxx_port_set_duplex, 3304 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3305 .port_set_speed = mv88e6390_port_set_speed, 3306 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3307 .port_tag_remap = mv88e6390_port_tag_remap, 3308 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3309 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3310 .port_set_ether_type = mv88e6351_port_set_ether_type, 3311 .port_pause_limit = mv88e6390_port_pause_limit, 3312 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3313 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3314 .port_link_state = mv88e6352_port_link_state, 3315 .port_get_cmode = mv88e6352_port_get_cmode, 3316 .port_set_cmode = mv88e6390_port_set_cmode, 3317 .port_setup_message_port = mv88e6xxx_setup_message_port, 3318 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3319 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3320 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3321 .stats_get_strings = mv88e6320_stats_get_strings, 3322 .stats_get_stats = mv88e6390_stats_get_stats, 3323 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3324 .set_egress_port = mv88e6390_g1_set_egress_port, 3325 .watchdog_ops = &mv88e6390_watchdog_ops, 3326 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3327 .pot_clear = mv88e6xxx_g2_pot_clear, 3328 .reset = mv88e6352_g1_reset, 3329 .rmu_disable = mv88e6390_g1_rmu_disable, 3330 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3331 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3332 .serdes_power = mv88e6390_serdes_power, 3333 .serdes_get_lane = mv88e6390_serdes_get_lane, 3334 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3335 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3336 .serdes_irq_status = mv88e6390_serdes_irq_status, 3337 .gpio_ops = &mv88e6352_gpio_ops, 3338 .phylink_validate = mv88e6390_phylink_validate, 3339 }; 3340 3341 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3342 /* MV88E6XXX_FAMILY_6390 */ 3343 .setup_errata = mv88e6390_setup_errata, 3344 .irl_init_all = mv88e6390_g2_irl_init_all, 3345 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3346 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3347 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3348 .phy_read = mv88e6xxx_g2_smi_phy_read, 3349 .phy_write = mv88e6xxx_g2_smi_phy_write, 3350 .port_set_link = mv88e6xxx_port_set_link, 3351 .port_set_duplex = mv88e6xxx_port_set_duplex, 3352 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3353 .port_set_speed = mv88e6390x_port_set_speed, 3354 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3355 .port_tag_remap = mv88e6390_port_tag_remap, 3356 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3357 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3358 .port_set_ether_type = mv88e6351_port_set_ether_type, 3359 .port_pause_limit = mv88e6390_port_pause_limit, 3360 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3361 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3362 .port_link_state = mv88e6352_port_link_state, 3363 .port_get_cmode = mv88e6352_port_get_cmode, 3364 .port_set_cmode = mv88e6390x_port_set_cmode, 3365 .port_setup_message_port = mv88e6xxx_setup_message_port, 3366 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3367 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3368 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3369 .stats_get_strings = mv88e6320_stats_get_strings, 3370 .stats_get_stats = mv88e6390_stats_get_stats, 3371 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3372 .set_egress_port = mv88e6390_g1_set_egress_port, 3373 .watchdog_ops = &mv88e6390_watchdog_ops, 3374 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3375 .pot_clear = mv88e6xxx_g2_pot_clear, 3376 .reset = mv88e6352_g1_reset, 3377 .rmu_disable = mv88e6390_g1_rmu_disable, 3378 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3379 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3380 .serdes_power = mv88e6390_serdes_power, 3381 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3382 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3383 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3384 .serdes_irq_status = mv88e6390_serdes_irq_status, 3385 .gpio_ops = &mv88e6352_gpio_ops, 3386 .phylink_validate = mv88e6390x_phylink_validate, 3387 }; 3388 3389 static const struct mv88e6xxx_ops mv88e6191_ops = { 3390 /* MV88E6XXX_FAMILY_6390 */ 3391 .setup_errata = mv88e6390_setup_errata, 3392 .irl_init_all = mv88e6390_g2_irl_init_all, 3393 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3394 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3395 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3396 .phy_read = mv88e6xxx_g2_smi_phy_read, 3397 .phy_write = mv88e6xxx_g2_smi_phy_write, 3398 .port_set_link = mv88e6xxx_port_set_link, 3399 .port_set_duplex = mv88e6xxx_port_set_duplex, 3400 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3401 .port_set_speed = mv88e6390_port_set_speed, 3402 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3403 .port_tag_remap = mv88e6390_port_tag_remap, 3404 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3405 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3406 .port_set_ether_type = mv88e6351_port_set_ether_type, 3407 .port_pause_limit = mv88e6390_port_pause_limit, 3408 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3409 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3410 .port_link_state = mv88e6352_port_link_state, 3411 .port_get_cmode = mv88e6352_port_get_cmode, 3412 .port_set_cmode = mv88e6390_port_set_cmode, 3413 .port_setup_message_port = mv88e6xxx_setup_message_port, 3414 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3415 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3416 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3417 .stats_get_strings = mv88e6320_stats_get_strings, 3418 .stats_get_stats = mv88e6390_stats_get_stats, 3419 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3420 .set_egress_port = mv88e6390_g1_set_egress_port, 3421 .watchdog_ops = &mv88e6390_watchdog_ops, 3422 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3423 .pot_clear = mv88e6xxx_g2_pot_clear, 3424 .reset = mv88e6352_g1_reset, 3425 .rmu_disable = mv88e6390_g1_rmu_disable, 3426 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3427 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3428 .serdes_power = mv88e6390_serdes_power, 3429 .serdes_get_lane = mv88e6390_serdes_get_lane, 3430 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3431 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3432 .serdes_irq_status = mv88e6390_serdes_irq_status, 3433 .avb_ops = &mv88e6390_avb_ops, 3434 .ptp_ops = &mv88e6352_ptp_ops, 3435 .phylink_validate = mv88e6390_phylink_validate, 3436 }; 3437 3438 static const struct mv88e6xxx_ops mv88e6240_ops = { 3439 /* MV88E6XXX_FAMILY_6352 */ 3440 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3441 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3442 .irl_init_all = mv88e6352_g2_irl_init_all, 3443 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3444 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3445 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3446 .phy_read = mv88e6xxx_g2_smi_phy_read, 3447 .phy_write = mv88e6xxx_g2_smi_phy_write, 3448 .port_set_link = mv88e6xxx_port_set_link, 3449 .port_set_duplex = mv88e6xxx_port_set_duplex, 3450 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3451 .port_set_speed = mv88e6352_port_set_speed, 3452 .port_tag_remap = mv88e6095_port_tag_remap, 3453 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3454 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3455 .port_set_ether_type = mv88e6351_port_set_ether_type, 3456 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3457 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3458 .port_pause_limit = mv88e6097_port_pause_limit, 3459 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3460 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3461 .port_link_state = mv88e6352_port_link_state, 3462 .port_get_cmode = mv88e6352_port_get_cmode, 3463 .port_setup_message_port = mv88e6xxx_setup_message_port, 3464 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3465 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3466 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3467 .stats_get_strings = mv88e6095_stats_get_strings, 3468 .stats_get_stats = mv88e6095_stats_get_stats, 3469 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3470 .set_egress_port = mv88e6095_g1_set_egress_port, 3471 .watchdog_ops = &mv88e6097_watchdog_ops, 3472 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3473 .pot_clear = mv88e6xxx_g2_pot_clear, 3474 .reset = mv88e6352_g1_reset, 3475 .rmu_disable = mv88e6352_g1_rmu_disable, 3476 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3477 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3478 .serdes_get_lane = mv88e6352_serdes_get_lane, 3479 .serdes_power = mv88e6352_serdes_power, 3480 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3481 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3482 .serdes_irq_status = mv88e6352_serdes_irq_status, 3483 .gpio_ops = &mv88e6352_gpio_ops, 3484 .avb_ops = &mv88e6352_avb_ops, 3485 .ptp_ops = &mv88e6352_ptp_ops, 3486 .phylink_validate = mv88e6352_phylink_validate, 3487 }; 3488 3489 static const struct mv88e6xxx_ops mv88e6250_ops = { 3490 /* MV88E6XXX_FAMILY_6250 */ 3491 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 3492 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3493 .irl_init_all = mv88e6352_g2_irl_init_all, 3494 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3495 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3496 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3497 .phy_read = mv88e6xxx_g2_smi_phy_read, 3498 .phy_write = mv88e6xxx_g2_smi_phy_write, 3499 .port_set_link = mv88e6xxx_port_set_link, 3500 .port_set_duplex = mv88e6xxx_port_set_duplex, 3501 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3502 .port_set_speed = mv88e6250_port_set_speed, 3503 .port_tag_remap = mv88e6095_port_tag_remap, 3504 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3505 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3506 .port_set_ether_type = mv88e6351_port_set_ether_type, 3507 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3508 .port_pause_limit = mv88e6097_port_pause_limit, 3509 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3510 .port_link_state = mv88e6250_port_link_state, 3511 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3512 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3513 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 3514 .stats_get_strings = mv88e6250_stats_get_strings, 3515 .stats_get_stats = mv88e6250_stats_get_stats, 3516 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3517 .set_egress_port = mv88e6095_g1_set_egress_port, 3518 .watchdog_ops = &mv88e6250_watchdog_ops, 3519 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3520 .pot_clear = mv88e6xxx_g2_pot_clear, 3521 .reset = mv88e6250_g1_reset, 3522 .vtu_getnext = mv88e6250_g1_vtu_getnext, 3523 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 3524 .avb_ops = &mv88e6352_avb_ops, 3525 .ptp_ops = &mv88e6250_ptp_ops, 3526 .phylink_validate = mv88e6065_phylink_validate, 3527 }; 3528 3529 static const struct mv88e6xxx_ops mv88e6290_ops = { 3530 /* MV88E6XXX_FAMILY_6390 */ 3531 .setup_errata = mv88e6390_setup_errata, 3532 .irl_init_all = mv88e6390_g2_irl_init_all, 3533 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3534 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3535 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3536 .phy_read = mv88e6xxx_g2_smi_phy_read, 3537 .phy_write = mv88e6xxx_g2_smi_phy_write, 3538 .port_set_link = mv88e6xxx_port_set_link, 3539 .port_set_duplex = mv88e6xxx_port_set_duplex, 3540 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3541 .port_set_speed = mv88e6390_port_set_speed, 3542 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3543 .port_tag_remap = mv88e6390_port_tag_remap, 3544 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3545 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3546 .port_set_ether_type = mv88e6351_port_set_ether_type, 3547 .port_pause_limit = mv88e6390_port_pause_limit, 3548 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3549 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3550 .port_link_state = mv88e6352_port_link_state, 3551 .port_get_cmode = mv88e6352_port_get_cmode, 3552 .port_set_cmode = mv88e6390_port_set_cmode, 3553 .port_setup_message_port = mv88e6xxx_setup_message_port, 3554 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3555 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3556 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3557 .stats_get_strings = mv88e6320_stats_get_strings, 3558 .stats_get_stats = mv88e6390_stats_get_stats, 3559 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3560 .set_egress_port = mv88e6390_g1_set_egress_port, 3561 .watchdog_ops = &mv88e6390_watchdog_ops, 3562 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3563 .pot_clear = mv88e6xxx_g2_pot_clear, 3564 .reset = mv88e6352_g1_reset, 3565 .rmu_disable = mv88e6390_g1_rmu_disable, 3566 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3567 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3568 .serdes_power = mv88e6390_serdes_power, 3569 .serdes_get_lane = mv88e6390_serdes_get_lane, 3570 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3571 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3572 .serdes_irq_status = mv88e6390_serdes_irq_status, 3573 .gpio_ops = &mv88e6352_gpio_ops, 3574 .avb_ops = &mv88e6390_avb_ops, 3575 .ptp_ops = &mv88e6352_ptp_ops, 3576 .phylink_validate = mv88e6390_phylink_validate, 3577 }; 3578 3579 static const struct mv88e6xxx_ops mv88e6320_ops = { 3580 /* MV88E6XXX_FAMILY_6320 */ 3581 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3582 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3583 .irl_init_all = mv88e6352_g2_irl_init_all, 3584 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3585 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3586 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3587 .phy_read = mv88e6xxx_g2_smi_phy_read, 3588 .phy_write = mv88e6xxx_g2_smi_phy_write, 3589 .port_set_link = mv88e6xxx_port_set_link, 3590 .port_set_duplex = mv88e6xxx_port_set_duplex, 3591 .port_set_speed = mv88e6185_port_set_speed, 3592 .port_tag_remap = mv88e6095_port_tag_remap, 3593 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3594 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3595 .port_set_ether_type = mv88e6351_port_set_ether_type, 3596 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3597 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3598 .port_pause_limit = mv88e6097_port_pause_limit, 3599 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3600 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3601 .port_link_state = mv88e6352_port_link_state, 3602 .port_get_cmode = mv88e6352_port_get_cmode, 3603 .port_setup_message_port = mv88e6xxx_setup_message_port, 3604 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3605 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3606 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3607 .stats_get_strings = mv88e6320_stats_get_strings, 3608 .stats_get_stats = mv88e6320_stats_get_stats, 3609 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3610 .set_egress_port = mv88e6095_g1_set_egress_port, 3611 .watchdog_ops = &mv88e6390_watchdog_ops, 3612 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3613 .pot_clear = mv88e6xxx_g2_pot_clear, 3614 .reset = mv88e6352_g1_reset, 3615 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3616 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3617 .gpio_ops = &mv88e6352_gpio_ops, 3618 .avb_ops = &mv88e6352_avb_ops, 3619 .ptp_ops = &mv88e6352_ptp_ops, 3620 .phylink_validate = mv88e6185_phylink_validate, 3621 }; 3622 3623 static const struct mv88e6xxx_ops mv88e6321_ops = { 3624 /* MV88E6XXX_FAMILY_6320 */ 3625 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3626 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3627 .irl_init_all = mv88e6352_g2_irl_init_all, 3628 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3629 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3630 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3631 .phy_read = mv88e6xxx_g2_smi_phy_read, 3632 .phy_write = mv88e6xxx_g2_smi_phy_write, 3633 .port_set_link = mv88e6xxx_port_set_link, 3634 .port_set_duplex = mv88e6xxx_port_set_duplex, 3635 .port_set_speed = mv88e6185_port_set_speed, 3636 .port_tag_remap = mv88e6095_port_tag_remap, 3637 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3638 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3639 .port_set_ether_type = mv88e6351_port_set_ether_type, 3640 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3641 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3642 .port_pause_limit = mv88e6097_port_pause_limit, 3643 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3644 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3645 .port_link_state = mv88e6352_port_link_state, 3646 .port_get_cmode = mv88e6352_port_get_cmode, 3647 .port_setup_message_port = mv88e6xxx_setup_message_port, 3648 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3649 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3650 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3651 .stats_get_strings = mv88e6320_stats_get_strings, 3652 .stats_get_stats = mv88e6320_stats_get_stats, 3653 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3654 .set_egress_port = mv88e6095_g1_set_egress_port, 3655 .watchdog_ops = &mv88e6390_watchdog_ops, 3656 .reset = mv88e6352_g1_reset, 3657 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3658 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3659 .gpio_ops = &mv88e6352_gpio_ops, 3660 .avb_ops = &mv88e6352_avb_ops, 3661 .ptp_ops = &mv88e6352_ptp_ops, 3662 .phylink_validate = mv88e6185_phylink_validate, 3663 }; 3664 3665 static const struct mv88e6xxx_ops mv88e6341_ops = { 3666 /* MV88E6XXX_FAMILY_6341 */ 3667 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3668 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3669 .irl_init_all = mv88e6352_g2_irl_init_all, 3670 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3671 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3672 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3673 .phy_read = mv88e6xxx_g2_smi_phy_read, 3674 .phy_write = mv88e6xxx_g2_smi_phy_write, 3675 .port_set_link = mv88e6xxx_port_set_link, 3676 .port_set_duplex = mv88e6xxx_port_set_duplex, 3677 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3678 .port_set_speed = mv88e6341_port_set_speed, 3679 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3680 .port_tag_remap = mv88e6095_port_tag_remap, 3681 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3682 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3683 .port_set_ether_type = mv88e6351_port_set_ether_type, 3684 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3685 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3686 .port_pause_limit = mv88e6097_port_pause_limit, 3687 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3688 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3689 .port_link_state = mv88e6352_port_link_state, 3690 .port_get_cmode = mv88e6352_port_get_cmode, 3691 .port_set_cmode = mv88e6341_port_set_cmode, 3692 .port_setup_message_port = mv88e6xxx_setup_message_port, 3693 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3694 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3695 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3696 .stats_get_strings = mv88e6320_stats_get_strings, 3697 .stats_get_stats = mv88e6390_stats_get_stats, 3698 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3699 .set_egress_port = mv88e6390_g1_set_egress_port, 3700 .watchdog_ops = &mv88e6390_watchdog_ops, 3701 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3702 .pot_clear = mv88e6xxx_g2_pot_clear, 3703 .reset = mv88e6352_g1_reset, 3704 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3705 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3706 .serdes_power = mv88e6390_serdes_power, 3707 .serdes_get_lane = mv88e6341_serdes_get_lane, 3708 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3709 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3710 .serdes_irq_status = mv88e6390_serdes_irq_status, 3711 .gpio_ops = &mv88e6352_gpio_ops, 3712 .avb_ops = &mv88e6390_avb_ops, 3713 .ptp_ops = &mv88e6352_ptp_ops, 3714 .phylink_validate = mv88e6341_phylink_validate, 3715 }; 3716 3717 static const struct mv88e6xxx_ops mv88e6350_ops = { 3718 /* MV88E6XXX_FAMILY_6351 */ 3719 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3720 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3721 .irl_init_all = mv88e6352_g2_irl_init_all, 3722 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3723 .phy_read = mv88e6xxx_g2_smi_phy_read, 3724 .phy_write = mv88e6xxx_g2_smi_phy_write, 3725 .port_set_link = mv88e6xxx_port_set_link, 3726 .port_set_duplex = mv88e6xxx_port_set_duplex, 3727 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3728 .port_set_speed = mv88e6185_port_set_speed, 3729 .port_tag_remap = mv88e6095_port_tag_remap, 3730 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3731 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3732 .port_set_ether_type = mv88e6351_port_set_ether_type, 3733 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3734 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3735 .port_pause_limit = mv88e6097_port_pause_limit, 3736 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3737 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3738 .port_link_state = mv88e6352_port_link_state, 3739 .port_get_cmode = mv88e6352_port_get_cmode, 3740 .port_setup_message_port = mv88e6xxx_setup_message_port, 3741 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3742 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3743 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3744 .stats_get_strings = mv88e6095_stats_get_strings, 3745 .stats_get_stats = mv88e6095_stats_get_stats, 3746 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3747 .set_egress_port = mv88e6095_g1_set_egress_port, 3748 .watchdog_ops = &mv88e6097_watchdog_ops, 3749 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3750 .pot_clear = mv88e6xxx_g2_pot_clear, 3751 .reset = mv88e6352_g1_reset, 3752 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3753 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3754 .phylink_validate = mv88e6185_phylink_validate, 3755 }; 3756 3757 static const struct mv88e6xxx_ops mv88e6351_ops = { 3758 /* MV88E6XXX_FAMILY_6351 */ 3759 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3760 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3761 .irl_init_all = mv88e6352_g2_irl_init_all, 3762 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3763 .phy_read = mv88e6xxx_g2_smi_phy_read, 3764 .phy_write = mv88e6xxx_g2_smi_phy_write, 3765 .port_set_link = mv88e6xxx_port_set_link, 3766 .port_set_duplex = mv88e6xxx_port_set_duplex, 3767 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3768 .port_set_speed = mv88e6185_port_set_speed, 3769 .port_tag_remap = mv88e6095_port_tag_remap, 3770 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3771 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3772 .port_set_ether_type = mv88e6351_port_set_ether_type, 3773 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3774 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3775 .port_pause_limit = mv88e6097_port_pause_limit, 3776 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3777 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3778 .port_link_state = mv88e6352_port_link_state, 3779 .port_get_cmode = mv88e6352_port_get_cmode, 3780 .port_setup_message_port = mv88e6xxx_setup_message_port, 3781 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3782 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3783 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3784 .stats_get_strings = mv88e6095_stats_get_strings, 3785 .stats_get_stats = mv88e6095_stats_get_stats, 3786 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3787 .set_egress_port = mv88e6095_g1_set_egress_port, 3788 .watchdog_ops = &mv88e6097_watchdog_ops, 3789 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3790 .pot_clear = mv88e6xxx_g2_pot_clear, 3791 .reset = mv88e6352_g1_reset, 3792 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3793 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3794 .avb_ops = &mv88e6352_avb_ops, 3795 .ptp_ops = &mv88e6352_ptp_ops, 3796 .phylink_validate = mv88e6185_phylink_validate, 3797 }; 3798 3799 static const struct mv88e6xxx_ops mv88e6352_ops = { 3800 /* MV88E6XXX_FAMILY_6352 */ 3801 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3802 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3803 .irl_init_all = mv88e6352_g2_irl_init_all, 3804 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3805 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3806 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3807 .phy_read = mv88e6xxx_g2_smi_phy_read, 3808 .phy_write = mv88e6xxx_g2_smi_phy_write, 3809 .port_set_link = mv88e6xxx_port_set_link, 3810 .port_set_duplex = mv88e6xxx_port_set_duplex, 3811 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3812 .port_set_speed = mv88e6352_port_set_speed, 3813 .port_tag_remap = mv88e6095_port_tag_remap, 3814 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3815 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3816 .port_set_ether_type = mv88e6351_port_set_ether_type, 3817 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3818 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3819 .port_pause_limit = mv88e6097_port_pause_limit, 3820 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3821 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3822 .port_link_state = mv88e6352_port_link_state, 3823 .port_get_cmode = mv88e6352_port_get_cmode, 3824 .port_setup_message_port = mv88e6xxx_setup_message_port, 3825 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3826 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3827 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3828 .stats_get_strings = mv88e6095_stats_get_strings, 3829 .stats_get_stats = mv88e6095_stats_get_stats, 3830 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3831 .set_egress_port = mv88e6095_g1_set_egress_port, 3832 .watchdog_ops = &mv88e6097_watchdog_ops, 3833 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3834 .pot_clear = mv88e6xxx_g2_pot_clear, 3835 .reset = mv88e6352_g1_reset, 3836 .rmu_disable = mv88e6352_g1_rmu_disable, 3837 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3838 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3839 .serdes_get_lane = mv88e6352_serdes_get_lane, 3840 .serdes_power = mv88e6352_serdes_power, 3841 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3842 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3843 .serdes_irq_status = mv88e6352_serdes_irq_status, 3844 .gpio_ops = &mv88e6352_gpio_ops, 3845 .avb_ops = &mv88e6352_avb_ops, 3846 .ptp_ops = &mv88e6352_ptp_ops, 3847 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3848 .serdes_get_strings = mv88e6352_serdes_get_strings, 3849 .serdes_get_stats = mv88e6352_serdes_get_stats, 3850 .phylink_validate = mv88e6352_phylink_validate, 3851 }; 3852 3853 static const struct mv88e6xxx_ops mv88e6390_ops = { 3854 /* MV88E6XXX_FAMILY_6390 */ 3855 .setup_errata = mv88e6390_setup_errata, 3856 .irl_init_all = mv88e6390_g2_irl_init_all, 3857 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3858 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3859 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3860 .phy_read = mv88e6xxx_g2_smi_phy_read, 3861 .phy_write = mv88e6xxx_g2_smi_phy_write, 3862 .port_set_link = mv88e6xxx_port_set_link, 3863 .port_set_duplex = mv88e6xxx_port_set_duplex, 3864 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3865 .port_set_speed = mv88e6390_port_set_speed, 3866 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3867 .port_tag_remap = mv88e6390_port_tag_remap, 3868 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3869 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3870 .port_set_ether_type = mv88e6351_port_set_ether_type, 3871 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3872 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3873 .port_pause_limit = mv88e6390_port_pause_limit, 3874 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3875 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3876 .port_link_state = mv88e6352_port_link_state, 3877 .port_get_cmode = mv88e6352_port_get_cmode, 3878 .port_set_cmode = mv88e6390_port_set_cmode, 3879 .port_setup_message_port = mv88e6xxx_setup_message_port, 3880 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3881 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3882 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3883 .stats_get_strings = mv88e6320_stats_get_strings, 3884 .stats_get_stats = mv88e6390_stats_get_stats, 3885 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3886 .set_egress_port = mv88e6390_g1_set_egress_port, 3887 .watchdog_ops = &mv88e6390_watchdog_ops, 3888 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3889 .pot_clear = mv88e6xxx_g2_pot_clear, 3890 .reset = mv88e6352_g1_reset, 3891 .rmu_disable = mv88e6390_g1_rmu_disable, 3892 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3893 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3894 .serdes_power = mv88e6390_serdes_power, 3895 .serdes_get_lane = mv88e6390_serdes_get_lane, 3896 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3897 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3898 .serdes_irq_status = mv88e6390_serdes_irq_status, 3899 .gpio_ops = &mv88e6352_gpio_ops, 3900 .avb_ops = &mv88e6390_avb_ops, 3901 .ptp_ops = &mv88e6352_ptp_ops, 3902 .phylink_validate = mv88e6390_phylink_validate, 3903 }; 3904 3905 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3906 /* MV88E6XXX_FAMILY_6390 */ 3907 .setup_errata = mv88e6390_setup_errata, 3908 .irl_init_all = mv88e6390_g2_irl_init_all, 3909 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3910 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3911 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3912 .phy_read = mv88e6xxx_g2_smi_phy_read, 3913 .phy_write = mv88e6xxx_g2_smi_phy_write, 3914 .port_set_link = mv88e6xxx_port_set_link, 3915 .port_set_duplex = mv88e6xxx_port_set_duplex, 3916 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3917 .port_set_speed = mv88e6390x_port_set_speed, 3918 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3919 .port_tag_remap = mv88e6390_port_tag_remap, 3920 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3921 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3922 .port_set_ether_type = mv88e6351_port_set_ether_type, 3923 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3924 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3925 .port_pause_limit = mv88e6390_port_pause_limit, 3926 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3927 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3928 .port_link_state = mv88e6352_port_link_state, 3929 .port_get_cmode = mv88e6352_port_get_cmode, 3930 .port_set_cmode = mv88e6390x_port_set_cmode, 3931 .port_setup_message_port = mv88e6xxx_setup_message_port, 3932 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3933 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3934 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3935 .stats_get_strings = mv88e6320_stats_get_strings, 3936 .stats_get_stats = mv88e6390_stats_get_stats, 3937 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3938 .set_egress_port = mv88e6390_g1_set_egress_port, 3939 .watchdog_ops = &mv88e6390_watchdog_ops, 3940 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3941 .pot_clear = mv88e6xxx_g2_pot_clear, 3942 .reset = mv88e6352_g1_reset, 3943 .rmu_disable = mv88e6390_g1_rmu_disable, 3944 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3945 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3946 .serdes_power = mv88e6390_serdes_power, 3947 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3948 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3949 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3950 .serdes_irq_status = mv88e6390_serdes_irq_status, 3951 .gpio_ops = &mv88e6352_gpio_ops, 3952 .avb_ops = &mv88e6390_avb_ops, 3953 .ptp_ops = &mv88e6352_ptp_ops, 3954 .phylink_validate = mv88e6390x_phylink_validate, 3955 }; 3956 3957 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3958 [MV88E6085] = { 3959 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3960 .family = MV88E6XXX_FAMILY_6097, 3961 .name = "Marvell 88E6085", 3962 .num_databases = 4096, 3963 .num_ports = 10, 3964 .num_internal_phys = 5, 3965 .max_vid = 4095, 3966 .port_base_addr = 0x10, 3967 .phy_base_addr = 0x0, 3968 .global1_addr = 0x1b, 3969 .global2_addr = 0x1c, 3970 .age_time_coeff = 15000, 3971 .g1_irqs = 8, 3972 .g2_irqs = 10, 3973 .atu_move_port_mask = 0xf, 3974 .pvt = true, 3975 .multi_chip = true, 3976 .tag_protocol = DSA_TAG_PROTO_DSA, 3977 .ops = &mv88e6085_ops, 3978 }, 3979 3980 [MV88E6095] = { 3981 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3982 .family = MV88E6XXX_FAMILY_6095, 3983 .name = "Marvell 88E6095/88E6095F", 3984 .num_databases = 256, 3985 .num_ports = 11, 3986 .num_internal_phys = 0, 3987 .max_vid = 4095, 3988 .port_base_addr = 0x10, 3989 .phy_base_addr = 0x0, 3990 .global1_addr = 0x1b, 3991 .global2_addr = 0x1c, 3992 .age_time_coeff = 15000, 3993 .g1_irqs = 8, 3994 .atu_move_port_mask = 0xf, 3995 .multi_chip = true, 3996 .tag_protocol = DSA_TAG_PROTO_DSA, 3997 .ops = &mv88e6095_ops, 3998 }, 3999 4000 [MV88E6097] = { 4001 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4002 .family = MV88E6XXX_FAMILY_6097, 4003 .name = "Marvell 88E6097/88E6097F", 4004 .num_databases = 4096, 4005 .num_ports = 11, 4006 .num_internal_phys = 8, 4007 .max_vid = 4095, 4008 .port_base_addr = 0x10, 4009 .phy_base_addr = 0x0, 4010 .global1_addr = 0x1b, 4011 .global2_addr = 0x1c, 4012 .age_time_coeff = 15000, 4013 .g1_irqs = 8, 4014 .g2_irqs = 10, 4015 .atu_move_port_mask = 0xf, 4016 .pvt = true, 4017 .multi_chip = true, 4018 .tag_protocol = DSA_TAG_PROTO_EDSA, 4019 .ops = &mv88e6097_ops, 4020 }, 4021 4022 [MV88E6123] = { 4023 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4024 .family = MV88E6XXX_FAMILY_6165, 4025 .name = "Marvell 88E6123", 4026 .num_databases = 4096, 4027 .num_ports = 3, 4028 .num_internal_phys = 5, 4029 .max_vid = 4095, 4030 .port_base_addr = 0x10, 4031 .phy_base_addr = 0x0, 4032 .global1_addr = 0x1b, 4033 .global2_addr = 0x1c, 4034 .age_time_coeff = 15000, 4035 .g1_irqs = 9, 4036 .g2_irqs = 10, 4037 .atu_move_port_mask = 0xf, 4038 .pvt = true, 4039 .multi_chip = true, 4040 .tag_protocol = DSA_TAG_PROTO_EDSA, 4041 .ops = &mv88e6123_ops, 4042 }, 4043 4044 [MV88E6131] = { 4045 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4046 .family = MV88E6XXX_FAMILY_6185, 4047 .name = "Marvell 88E6131", 4048 .num_databases = 256, 4049 .num_ports = 8, 4050 .num_internal_phys = 0, 4051 .max_vid = 4095, 4052 .port_base_addr = 0x10, 4053 .phy_base_addr = 0x0, 4054 .global1_addr = 0x1b, 4055 .global2_addr = 0x1c, 4056 .age_time_coeff = 15000, 4057 .g1_irqs = 9, 4058 .atu_move_port_mask = 0xf, 4059 .multi_chip = true, 4060 .tag_protocol = DSA_TAG_PROTO_DSA, 4061 .ops = &mv88e6131_ops, 4062 }, 4063 4064 [MV88E6141] = { 4065 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4066 .family = MV88E6XXX_FAMILY_6341, 4067 .name = "Marvell 88E6141", 4068 .num_databases = 4096, 4069 .num_ports = 6, 4070 .num_internal_phys = 5, 4071 .num_gpio = 11, 4072 .max_vid = 4095, 4073 .port_base_addr = 0x10, 4074 .phy_base_addr = 0x10, 4075 .global1_addr = 0x1b, 4076 .global2_addr = 0x1c, 4077 .age_time_coeff = 3750, 4078 .atu_move_port_mask = 0x1f, 4079 .g1_irqs = 9, 4080 .g2_irqs = 10, 4081 .pvt = true, 4082 .multi_chip = true, 4083 .tag_protocol = DSA_TAG_PROTO_EDSA, 4084 .ops = &mv88e6141_ops, 4085 }, 4086 4087 [MV88E6161] = { 4088 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4089 .family = MV88E6XXX_FAMILY_6165, 4090 .name = "Marvell 88E6161", 4091 .num_databases = 4096, 4092 .num_ports = 6, 4093 .num_internal_phys = 5, 4094 .max_vid = 4095, 4095 .port_base_addr = 0x10, 4096 .phy_base_addr = 0x0, 4097 .global1_addr = 0x1b, 4098 .global2_addr = 0x1c, 4099 .age_time_coeff = 15000, 4100 .g1_irqs = 9, 4101 .g2_irqs = 10, 4102 .atu_move_port_mask = 0xf, 4103 .pvt = true, 4104 .multi_chip = true, 4105 .tag_protocol = DSA_TAG_PROTO_EDSA, 4106 .ptp_support = true, 4107 .ops = &mv88e6161_ops, 4108 }, 4109 4110 [MV88E6165] = { 4111 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4112 .family = MV88E6XXX_FAMILY_6165, 4113 .name = "Marvell 88E6165", 4114 .num_databases = 4096, 4115 .num_ports = 6, 4116 .num_internal_phys = 0, 4117 .max_vid = 4095, 4118 .port_base_addr = 0x10, 4119 .phy_base_addr = 0x0, 4120 .global1_addr = 0x1b, 4121 .global2_addr = 0x1c, 4122 .age_time_coeff = 15000, 4123 .g1_irqs = 9, 4124 .g2_irqs = 10, 4125 .atu_move_port_mask = 0xf, 4126 .pvt = true, 4127 .multi_chip = true, 4128 .tag_protocol = DSA_TAG_PROTO_DSA, 4129 .ptp_support = true, 4130 .ops = &mv88e6165_ops, 4131 }, 4132 4133 [MV88E6171] = { 4134 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4135 .family = MV88E6XXX_FAMILY_6351, 4136 .name = "Marvell 88E6171", 4137 .num_databases = 4096, 4138 .num_ports = 7, 4139 .num_internal_phys = 5, 4140 .max_vid = 4095, 4141 .port_base_addr = 0x10, 4142 .phy_base_addr = 0x0, 4143 .global1_addr = 0x1b, 4144 .global2_addr = 0x1c, 4145 .age_time_coeff = 15000, 4146 .g1_irqs = 9, 4147 .g2_irqs = 10, 4148 .atu_move_port_mask = 0xf, 4149 .pvt = true, 4150 .multi_chip = true, 4151 .tag_protocol = DSA_TAG_PROTO_EDSA, 4152 .ops = &mv88e6171_ops, 4153 }, 4154 4155 [MV88E6172] = { 4156 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4157 .family = MV88E6XXX_FAMILY_6352, 4158 .name = "Marvell 88E6172", 4159 .num_databases = 4096, 4160 .num_ports = 7, 4161 .num_internal_phys = 5, 4162 .num_gpio = 15, 4163 .max_vid = 4095, 4164 .port_base_addr = 0x10, 4165 .phy_base_addr = 0x0, 4166 .global1_addr = 0x1b, 4167 .global2_addr = 0x1c, 4168 .age_time_coeff = 15000, 4169 .g1_irqs = 9, 4170 .g2_irqs = 10, 4171 .atu_move_port_mask = 0xf, 4172 .pvt = true, 4173 .multi_chip = true, 4174 .tag_protocol = DSA_TAG_PROTO_EDSA, 4175 .ops = &mv88e6172_ops, 4176 }, 4177 4178 [MV88E6175] = { 4179 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4180 .family = MV88E6XXX_FAMILY_6351, 4181 .name = "Marvell 88E6175", 4182 .num_databases = 4096, 4183 .num_ports = 7, 4184 .num_internal_phys = 5, 4185 .max_vid = 4095, 4186 .port_base_addr = 0x10, 4187 .phy_base_addr = 0x0, 4188 .global1_addr = 0x1b, 4189 .global2_addr = 0x1c, 4190 .age_time_coeff = 15000, 4191 .g1_irqs = 9, 4192 .g2_irqs = 10, 4193 .atu_move_port_mask = 0xf, 4194 .pvt = true, 4195 .multi_chip = true, 4196 .tag_protocol = DSA_TAG_PROTO_EDSA, 4197 .ops = &mv88e6175_ops, 4198 }, 4199 4200 [MV88E6176] = { 4201 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4202 .family = MV88E6XXX_FAMILY_6352, 4203 .name = "Marvell 88E6176", 4204 .num_databases = 4096, 4205 .num_ports = 7, 4206 .num_internal_phys = 5, 4207 .num_gpio = 15, 4208 .max_vid = 4095, 4209 .port_base_addr = 0x10, 4210 .phy_base_addr = 0x0, 4211 .global1_addr = 0x1b, 4212 .global2_addr = 0x1c, 4213 .age_time_coeff = 15000, 4214 .g1_irqs = 9, 4215 .g2_irqs = 10, 4216 .atu_move_port_mask = 0xf, 4217 .pvt = true, 4218 .multi_chip = true, 4219 .tag_protocol = DSA_TAG_PROTO_EDSA, 4220 .ops = &mv88e6176_ops, 4221 }, 4222 4223 [MV88E6185] = { 4224 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4225 .family = MV88E6XXX_FAMILY_6185, 4226 .name = "Marvell 88E6185", 4227 .num_databases = 256, 4228 .num_ports = 10, 4229 .num_internal_phys = 0, 4230 .max_vid = 4095, 4231 .port_base_addr = 0x10, 4232 .phy_base_addr = 0x0, 4233 .global1_addr = 0x1b, 4234 .global2_addr = 0x1c, 4235 .age_time_coeff = 15000, 4236 .g1_irqs = 8, 4237 .atu_move_port_mask = 0xf, 4238 .multi_chip = true, 4239 .tag_protocol = DSA_TAG_PROTO_EDSA, 4240 .ops = &mv88e6185_ops, 4241 }, 4242 4243 [MV88E6190] = { 4244 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4245 .family = MV88E6XXX_FAMILY_6390, 4246 .name = "Marvell 88E6190", 4247 .num_databases = 4096, 4248 .num_ports = 11, /* 10 + Z80 */ 4249 .num_internal_phys = 9, 4250 .num_gpio = 16, 4251 .max_vid = 8191, 4252 .port_base_addr = 0x0, 4253 .phy_base_addr = 0x0, 4254 .global1_addr = 0x1b, 4255 .global2_addr = 0x1c, 4256 .tag_protocol = DSA_TAG_PROTO_DSA, 4257 .age_time_coeff = 3750, 4258 .g1_irqs = 9, 4259 .g2_irqs = 14, 4260 .pvt = true, 4261 .multi_chip = true, 4262 .atu_move_port_mask = 0x1f, 4263 .ops = &mv88e6190_ops, 4264 }, 4265 4266 [MV88E6190X] = { 4267 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4268 .family = MV88E6XXX_FAMILY_6390, 4269 .name = "Marvell 88E6190X", 4270 .num_databases = 4096, 4271 .num_ports = 11, /* 10 + Z80 */ 4272 .num_internal_phys = 9, 4273 .num_gpio = 16, 4274 .max_vid = 8191, 4275 .port_base_addr = 0x0, 4276 .phy_base_addr = 0x0, 4277 .global1_addr = 0x1b, 4278 .global2_addr = 0x1c, 4279 .age_time_coeff = 3750, 4280 .g1_irqs = 9, 4281 .g2_irqs = 14, 4282 .atu_move_port_mask = 0x1f, 4283 .pvt = true, 4284 .multi_chip = true, 4285 .tag_protocol = DSA_TAG_PROTO_DSA, 4286 .ops = &mv88e6190x_ops, 4287 }, 4288 4289 [MV88E6191] = { 4290 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4291 .family = MV88E6XXX_FAMILY_6390, 4292 .name = "Marvell 88E6191", 4293 .num_databases = 4096, 4294 .num_ports = 11, /* 10 + Z80 */ 4295 .num_internal_phys = 9, 4296 .max_vid = 8191, 4297 .port_base_addr = 0x0, 4298 .phy_base_addr = 0x0, 4299 .global1_addr = 0x1b, 4300 .global2_addr = 0x1c, 4301 .age_time_coeff = 3750, 4302 .g1_irqs = 9, 4303 .g2_irqs = 14, 4304 .atu_move_port_mask = 0x1f, 4305 .pvt = true, 4306 .multi_chip = true, 4307 .tag_protocol = DSA_TAG_PROTO_DSA, 4308 .ptp_support = true, 4309 .ops = &mv88e6191_ops, 4310 }, 4311 4312 [MV88E6220] = { 4313 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4314 .family = MV88E6XXX_FAMILY_6250, 4315 .name = "Marvell 88E6220", 4316 .num_databases = 64, 4317 4318 /* Ports 2-4 are not routed to pins 4319 * => usable ports 0, 1, 5, 6 4320 */ 4321 .num_ports = 7, 4322 .num_internal_phys = 2, 4323 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4324 .max_vid = 4095, 4325 .port_base_addr = 0x08, 4326 .phy_base_addr = 0x00, 4327 .global1_addr = 0x0f, 4328 .global2_addr = 0x07, 4329 .age_time_coeff = 15000, 4330 .g1_irqs = 9, 4331 .g2_irqs = 10, 4332 .atu_move_port_mask = 0xf, 4333 .dual_chip = true, 4334 .tag_protocol = DSA_TAG_PROTO_DSA, 4335 .ptp_support = true, 4336 .ops = &mv88e6250_ops, 4337 }, 4338 4339 [MV88E6240] = { 4340 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4341 .family = MV88E6XXX_FAMILY_6352, 4342 .name = "Marvell 88E6240", 4343 .num_databases = 4096, 4344 .num_ports = 7, 4345 .num_internal_phys = 5, 4346 .num_gpio = 15, 4347 .max_vid = 4095, 4348 .port_base_addr = 0x10, 4349 .phy_base_addr = 0x0, 4350 .global1_addr = 0x1b, 4351 .global2_addr = 0x1c, 4352 .age_time_coeff = 15000, 4353 .g1_irqs = 9, 4354 .g2_irqs = 10, 4355 .atu_move_port_mask = 0xf, 4356 .pvt = true, 4357 .multi_chip = true, 4358 .tag_protocol = DSA_TAG_PROTO_EDSA, 4359 .ptp_support = true, 4360 .ops = &mv88e6240_ops, 4361 }, 4362 4363 [MV88E6250] = { 4364 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4365 .family = MV88E6XXX_FAMILY_6250, 4366 .name = "Marvell 88E6250", 4367 .num_databases = 64, 4368 .num_ports = 7, 4369 .num_internal_phys = 5, 4370 .max_vid = 4095, 4371 .port_base_addr = 0x08, 4372 .phy_base_addr = 0x00, 4373 .global1_addr = 0x0f, 4374 .global2_addr = 0x07, 4375 .age_time_coeff = 15000, 4376 .g1_irqs = 9, 4377 .g2_irqs = 10, 4378 .atu_move_port_mask = 0xf, 4379 .dual_chip = true, 4380 .tag_protocol = DSA_TAG_PROTO_DSA, 4381 .ptp_support = true, 4382 .ops = &mv88e6250_ops, 4383 }, 4384 4385 [MV88E6290] = { 4386 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4387 .family = MV88E6XXX_FAMILY_6390, 4388 .name = "Marvell 88E6290", 4389 .num_databases = 4096, 4390 .num_ports = 11, /* 10 + Z80 */ 4391 .num_internal_phys = 9, 4392 .num_gpio = 16, 4393 .max_vid = 8191, 4394 .port_base_addr = 0x0, 4395 .phy_base_addr = 0x0, 4396 .global1_addr = 0x1b, 4397 .global2_addr = 0x1c, 4398 .age_time_coeff = 3750, 4399 .g1_irqs = 9, 4400 .g2_irqs = 14, 4401 .atu_move_port_mask = 0x1f, 4402 .pvt = true, 4403 .multi_chip = true, 4404 .tag_protocol = DSA_TAG_PROTO_DSA, 4405 .ptp_support = true, 4406 .ops = &mv88e6290_ops, 4407 }, 4408 4409 [MV88E6320] = { 4410 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4411 .family = MV88E6XXX_FAMILY_6320, 4412 .name = "Marvell 88E6320", 4413 .num_databases = 4096, 4414 .num_ports = 7, 4415 .num_internal_phys = 5, 4416 .num_gpio = 15, 4417 .max_vid = 4095, 4418 .port_base_addr = 0x10, 4419 .phy_base_addr = 0x0, 4420 .global1_addr = 0x1b, 4421 .global2_addr = 0x1c, 4422 .age_time_coeff = 15000, 4423 .g1_irqs = 8, 4424 .g2_irqs = 10, 4425 .atu_move_port_mask = 0xf, 4426 .pvt = true, 4427 .multi_chip = true, 4428 .tag_protocol = DSA_TAG_PROTO_EDSA, 4429 .ptp_support = true, 4430 .ops = &mv88e6320_ops, 4431 }, 4432 4433 [MV88E6321] = { 4434 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4435 .family = MV88E6XXX_FAMILY_6320, 4436 .name = "Marvell 88E6321", 4437 .num_databases = 4096, 4438 .num_ports = 7, 4439 .num_internal_phys = 5, 4440 .num_gpio = 15, 4441 .max_vid = 4095, 4442 .port_base_addr = 0x10, 4443 .phy_base_addr = 0x0, 4444 .global1_addr = 0x1b, 4445 .global2_addr = 0x1c, 4446 .age_time_coeff = 15000, 4447 .g1_irqs = 8, 4448 .g2_irqs = 10, 4449 .atu_move_port_mask = 0xf, 4450 .multi_chip = true, 4451 .tag_protocol = DSA_TAG_PROTO_EDSA, 4452 .ptp_support = true, 4453 .ops = &mv88e6321_ops, 4454 }, 4455 4456 [MV88E6341] = { 4457 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4458 .family = MV88E6XXX_FAMILY_6341, 4459 .name = "Marvell 88E6341", 4460 .num_databases = 4096, 4461 .num_internal_phys = 5, 4462 .num_ports = 6, 4463 .num_gpio = 11, 4464 .max_vid = 4095, 4465 .port_base_addr = 0x10, 4466 .phy_base_addr = 0x10, 4467 .global1_addr = 0x1b, 4468 .global2_addr = 0x1c, 4469 .age_time_coeff = 3750, 4470 .atu_move_port_mask = 0x1f, 4471 .g1_irqs = 9, 4472 .g2_irqs = 10, 4473 .pvt = true, 4474 .multi_chip = true, 4475 .tag_protocol = DSA_TAG_PROTO_EDSA, 4476 .ptp_support = true, 4477 .ops = &mv88e6341_ops, 4478 }, 4479 4480 [MV88E6350] = { 4481 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4482 .family = MV88E6XXX_FAMILY_6351, 4483 .name = "Marvell 88E6350", 4484 .num_databases = 4096, 4485 .num_ports = 7, 4486 .num_internal_phys = 5, 4487 .max_vid = 4095, 4488 .port_base_addr = 0x10, 4489 .phy_base_addr = 0x0, 4490 .global1_addr = 0x1b, 4491 .global2_addr = 0x1c, 4492 .age_time_coeff = 15000, 4493 .g1_irqs = 9, 4494 .g2_irqs = 10, 4495 .atu_move_port_mask = 0xf, 4496 .pvt = true, 4497 .multi_chip = true, 4498 .tag_protocol = DSA_TAG_PROTO_EDSA, 4499 .ops = &mv88e6350_ops, 4500 }, 4501 4502 [MV88E6351] = { 4503 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4504 .family = MV88E6XXX_FAMILY_6351, 4505 .name = "Marvell 88E6351", 4506 .num_databases = 4096, 4507 .num_ports = 7, 4508 .num_internal_phys = 5, 4509 .max_vid = 4095, 4510 .port_base_addr = 0x10, 4511 .phy_base_addr = 0x0, 4512 .global1_addr = 0x1b, 4513 .global2_addr = 0x1c, 4514 .age_time_coeff = 15000, 4515 .g1_irqs = 9, 4516 .g2_irqs = 10, 4517 .atu_move_port_mask = 0xf, 4518 .pvt = true, 4519 .multi_chip = true, 4520 .tag_protocol = DSA_TAG_PROTO_EDSA, 4521 .ops = &mv88e6351_ops, 4522 }, 4523 4524 [MV88E6352] = { 4525 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4526 .family = MV88E6XXX_FAMILY_6352, 4527 .name = "Marvell 88E6352", 4528 .num_databases = 4096, 4529 .num_ports = 7, 4530 .num_internal_phys = 5, 4531 .num_gpio = 15, 4532 .max_vid = 4095, 4533 .port_base_addr = 0x10, 4534 .phy_base_addr = 0x0, 4535 .global1_addr = 0x1b, 4536 .global2_addr = 0x1c, 4537 .age_time_coeff = 15000, 4538 .g1_irqs = 9, 4539 .g2_irqs = 10, 4540 .atu_move_port_mask = 0xf, 4541 .pvt = true, 4542 .multi_chip = true, 4543 .tag_protocol = DSA_TAG_PROTO_EDSA, 4544 .ptp_support = true, 4545 .ops = &mv88e6352_ops, 4546 }, 4547 [MV88E6390] = { 4548 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4549 .family = MV88E6XXX_FAMILY_6390, 4550 .name = "Marvell 88E6390", 4551 .num_databases = 4096, 4552 .num_ports = 11, /* 10 + Z80 */ 4553 .num_internal_phys = 9, 4554 .num_gpio = 16, 4555 .max_vid = 8191, 4556 .port_base_addr = 0x0, 4557 .phy_base_addr = 0x0, 4558 .global1_addr = 0x1b, 4559 .global2_addr = 0x1c, 4560 .age_time_coeff = 3750, 4561 .g1_irqs = 9, 4562 .g2_irqs = 14, 4563 .atu_move_port_mask = 0x1f, 4564 .pvt = true, 4565 .multi_chip = true, 4566 .tag_protocol = DSA_TAG_PROTO_DSA, 4567 .ptp_support = true, 4568 .ops = &mv88e6390_ops, 4569 }, 4570 [MV88E6390X] = { 4571 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4572 .family = MV88E6XXX_FAMILY_6390, 4573 .name = "Marvell 88E6390X", 4574 .num_databases = 4096, 4575 .num_ports = 11, /* 10 + Z80 */ 4576 .num_internal_phys = 9, 4577 .num_gpio = 16, 4578 .max_vid = 8191, 4579 .port_base_addr = 0x0, 4580 .phy_base_addr = 0x0, 4581 .global1_addr = 0x1b, 4582 .global2_addr = 0x1c, 4583 .age_time_coeff = 3750, 4584 .g1_irqs = 9, 4585 .g2_irqs = 14, 4586 .atu_move_port_mask = 0x1f, 4587 .pvt = true, 4588 .multi_chip = true, 4589 .tag_protocol = DSA_TAG_PROTO_DSA, 4590 .ptp_support = true, 4591 .ops = &mv88e6390x_ops, 4592 }, 4593 }; 4594 4595 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4596 { 4597 int i; 4598 4599 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4600 if (mv88e6xxx_table[i].prod_num == prod_num) 4601 return &mv88e6xxx_table[i]; 4602 4603 return NULL; 4604 } 4605 4606 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4607 { 4608 const struct mv88e6xxx_info *info; 4609 unsigned int prod_num, rev; 4610 u16 id; 4611 int err; 4612 4613 mv88e6xxx_reg_lock(chip); 4614 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4615 mv88e6xxx_reg_unlock(chip); 4616 if (err) 4617 return err; 4618 4619 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4620 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4621 4622 info = mv88e6xxx_lookup_info(prod_num); 4623 if (!info) 4624 return -ENODEV; 4625 4626 /* Update the compatible info with the probed one */ 4627 chip->info = info; 4628 4629 err = mv88e6xxx_g2_require(chip); 4630 if (err) 4631 return err; 4632 4633 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4634 chip->info->prod_num, chip->info->name, rev); 4635 4636 return 0; 4637 } 4638 4639 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4640 { 4641 struct mv88e6xxx_chip *chip; 4642 4643 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4644 if (!chip) 4645 return NULL; 4646 4647 chip->dev = dev; 4648 4649 mutex_init(&chip->reg_lock); 4650 INIT_LIST_HEAD(&chip->mdios); 4651 4652 return chip; 4653 } 4654 4655 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4656 int port) 4657 { 4658 struct mv88e6xxx_chip *chip = ds->priv; 4659 4660 return chip->info->tag_protocol; 4661 } 4662 4663 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4664 const struct switchdev_obj_port_mdb *mdb) 4665 { 4666 /* We don't need any dynamic resource from the kernel (yet), 4667 * so skip the prepare phase. 4668 */ 4669 4670 return 0; 4671 } 4672 4673 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4674 const struct switchdev_obj_port_mdb *mdb) 4675 { 4676 struct mv88e6xxx_chip *chip = ds->priv; 4677 4678 mv88e6xxx_reg_lock(chip); 4679 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4680 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4681 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4682 port); 4683 mv88e6xxx_reg_unlock(chip); 4684 } 4685 4686 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4687 const struct switchdev_obj_port_mdb *mdb) 4688 { 4689 struct mv88e6xxx_chip *chip = ds->priv; 4690 int err; 4691 4692 mv88e6xxx_reg_lock(chip); 4693 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4694 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4695 mv88e6xxx_reg_unlock(chip); 4696 4697 return err; 4698 } 4699 4700 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 4701 bool unicast, bool multicast) 4702 { 4703 struct mv88e6xxx_chip *chip = ds->priv; 4704 int err = -EOPNOTSUPP; 4705 4706 mv88e6xxx_reg_lock(chip); 4707 if (chip->info->ops->port_set_egress_floods) 4708 err = chip->info->ops->port_set_egress_floods(chip, port, 4709 unicast, 4710 multicast); 4711 mv88e6xxx_reg_unlock(chip); 4712 4713 return err; 4714 } 4715 4716 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4717 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4718 .setup = mv88e6xxx_setup, 4719 .phylink_validate = mv88e6xxx_validate, 4720 .phylink_mac_link_state = mv88e6xxx_link_state, 4721 .phylink_mac_config = mv88e6xxx_mac_config, 4722 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4723 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4724 .get_strings = mv88e6xxx_get_strings, 4725 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4726 .get_sset_count = mv88e6xxx_get_sset_count, 4727 .port_enable = mv88e6xxx_port_enable, 4728 .port_disable = mv88e6xxx_port_disable, 4729 .get_mac_eee = mv88e6xxx_get_mac_eee, 4730 .set_mac_eee = mv88e6xxx_set_mac_eee, 4731 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4732 .get_eeprom = mv88e6xxx_get_eeprom, 4733 .set_eeprom = mv88e6xxx_set_eeprom, 4734 .get_regs_len = mv88e6xxx_get_regs_len, 4735 .get_regs = mv88e6xxx_get_regs, 4736 .set_ageing_time = mv88e6xxx_set_ageing_time, 4737 .port_bridge_join = mv88e6xxx_port_bridge_join, 4738 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4739 .port_egress_floods = mv88e6xxx_port_egress_floods, 4740 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4741 .port_fast_age = mv88e6xxx_port_fast_age, 4742 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4743 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4744 .port_vlan_add = mv88e6xxx_port_vlan_add, 4745 .port_vlan_del = mv88e6xxx_port_vlan_del, 4746 .port_fdb_add = mv88e6xxx_port_fdb_add, 4747 .port_fdb_del = mv88e6xxx_port_fdb_del, 4748 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4749 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4750 .port_mdb_add = mv88e6xxx_port_mdb_add, 4751 .port_mdb_del = mv88e6xxx_port_mdb_del, 4752 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4753 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4754 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4755 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4756 .port_txtstamp = mv88e6xxx_port_txtstamp, 4757 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4758 .get_ts_info = mv88e6xxx_get_ts_info, 4759 }; 4760 4761 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4762 { 4763 struct device *dev = chip->dev; 4764 struct dsa_switch *ds; 4765 4766 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4767 if (!ds) 4768 return -ENOMEM; 4769 4770 ds->priv = chip; 4771 ds->dev = dev; 4772 ds->ops = &mv88e6xxx_switch_ops; 4773 ds->ageing_time_min = chip->info->age_time_coeff; 4774 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4775 4776 dev_set_drvdata(dev, ds); 4777 4778 return dsa_register_switch(ds); 4779 } 4780 4781 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4782 { 4783 dsa_unregister_switch(chip->ds); 4784 } 4785 4786 static const void *pdata_device_get_match_data(struct device *dev) 4787 { 4788 const struct of_device_id *matches = dev->driver->of_match_table; 4789 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4790 4791 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4792 matches++) { 4793 if (!strcmp(pdata->compatible, matches->compatible)) 4794 return matches->data; 4795 } 4796 return NULL; 4797 } 4798 4799 /* There is no suspend to RAM support at DSA level yet, the switch configuration 4800 * would be lost after a power cycle so prevent it to be suspended. 4801 */ 4802 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 4803 { 4804 return -EOPNOTSUPP; 4805 } 4806 4807 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 4808 { 4809 return 0; 4810 } 4811 4812 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 4813 4814 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4815 { 4816 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4817 const struct mv88e6xxx_info *compat_info = NULL; 4818 struct device *dev = &mdiodev->dev; 4819 struct device_node *np = dev->of_node; 4820 struct mv88e6xxx_chip *chip; 4821 int port; 4822 int err; 4823 4824 if (!np && !pdata) 4825 return -EINVAL; 4826 4827 if (np) 4828 compat_info = of_device_get_match_data(dev); 4829 4830 if (pdata) { 4831 compat_info = pdata_device_get_match_data(dev); 4832 4833 if (!pdata->netdev) 4834 return -EINVAL; 4835 4836 for (port = 0; port < DSA_MAX_PORTS; port++) { 4837 if (!(pdata->enabled_ports & (1 << port))) 4838 continue; 4839 if (strcmp(pdata->cd.port_names[port], "cpu")) 4840 continue; 4841 pdata->cd.netdev[port] = &pdata->netdev->dev; 4842 break; 4843 } 4844 } 4845 4846 if (!compat_info) 4847 return -EINVAL; 4848 4849 chip = mv88e6xxx_alloc_chip(dev); 4850 if (!chip) { 4851 err = -ENOMEM; 4852 goto out; 4853 } 4854 4855 chip->info = compat_info; 4856 4857 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4858 if (err) 4859 goto out; 4860 4861 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4862 if (IS_ERR(chip->reset)) { 4863 err = PTR_ERR(chip->reset); 4864 goto out; 4865 } 4866 if (chip->reset) 4867 usleep_range(1000, 2000); 4868 4869 err = mv88e6xxx_detect(chip); 4870 if (err) 4871 goto out; 4872 4873 mv88e6xxx_phy_init(chip); 4874 4875 if (chip->info->ops->get_eeprom) { 4876 if (np) 4877 of_property_read_u32(np, "eeprom-length", 4878 &chip->eeprom_len); 4879 else 4880 chip->eeprom_len = pdata->eeprom_len; 4881 } 4882 4883 mv88e6xxx_reg_lock(chip); 4884 err = mv88e6xxx_switch_reset(chip); 4885 mv88e6xxx_reg_unlock(chip); 4886 if (err) 4887 goto out; 4888 4889 if (np) { 4890 chip->irq = of_irq_get(np, 0); 4891 if (chip->irq == -EPROBE_DEFER) { 4892 err = chip->irq; 4893 goto out; 4894 } 4895 } 4896 4897 if (pdata) 4898 chip->irq = pdata->irq; 4899 4900 /* Has to be performed before the MDIO bus is created, because 4901 * the PHYs will link their interrupts to these interrupt 4902 * controllers 4903 */ 4904 mv88e6xxx_reg_lock(chip); 4905 if (chip->irq > 0) 4906 err = mv88e6xxx_g1_irq_setup(chip); 4907 else 4908 err = mv88e6xxx_irq_poll_setup(chip); 4909 mv88e6xxx_reg_unlock(chip); 4910 4911 if (err) 4912 goto out; 4913 4914 if (chip->info->g2_irqs > 0) { 4915 err = mv88e6xxx_g2_irq_setup(chip); 4916 if (err) 4917 goto out_g1_irq; 4918 } 4919 4920 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4921 if (err) 4922 goto out_g2_irq; 4923 4924 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4925 if (err) 4926 goto out_g1_atu_prob_irq; 4927 4928 err = mv88e6xxx_mdios_register(chip, np); 4929 if (err) 4930 goto out_g1_vtu_prob_irq; 4931 4932 err = mv88e6xxx_register_switch(chip); 4933 if (err) 4934 goto out_mdio; 4935 4936 return 0; 4937 4938 out_mdio: 4939 mv88e6xxx_mdios_unregister(chip); 4940 out_g1_vtu_prob_irq: 4941 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4942 out_g1_atu_prob_irq: 4943 mv88e6xxx_g1_atu_prob_irq_free(chip); 4944 out_g2_irq: 4945 if (chip->info->g2_irqs > 0) 4946 mv88e6xxx_g2_irq_free(chip); 4947 out_g1_irq: 4948 if (chip->irq > 0) 4949 mv88e6xxx_g1_irq_free(chip); 4950 else 4951 mv88e6xxx_irq_poll_free(chip); 4952 out: 4953 if (pdata) 4954 dev_put(pdata->netdev); 4955 4956 return err; 4957 } 4958 4959 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4960 { 4961 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4962 struct mv88e6xxx_chip *chip = ds->priv; 4963 4964 if (chip->info->ptp_support) { 4965 mv88e6xxx_hwtstamp_free(chip); 4966 mv88e6xxx_ptp_free(chip); 4967 } 4968 4969 mv88e6xxx_phy_destroy(chip); 4970 mv88e6xxx_unregister_switch(chip); 4971 mv88e6xxx_mdios_unregister(chip); 4972 4973 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4974 mv88e6xxx_g1_atu_prob_irq_free(chip); 4975 4976 if (chip->info->g2_irqs > 0) 4977 mv88e6xxx_g2_irq_free(chip); 4978 4979 if (chip->irq > 0) 4980 mv88e6xxx_g1_irq_free(chip); 4981 else 4982 mv88e6xxx_irq_poll_free(chip); 4983 } 4984 4985 static const struct of_device_id mv88e6xxx_of_match[] = { 4986 { 4987 .compatible = "marvell,mv88e6085", 4988 .data = &mv88e6xxx_table[MV88E6085], 4989 }, 4990 { 4991 .compatible = "marvell,mv88e6190", 4992 .data = &mv88e6xxx_table[MV88E6190], 4993 }, 4994 { 4995 .compatible = "marvell,mv88e6250", 4996 .data = &mv88e6xxx_table[MV88E6250], 4997 }, 4998 { /* sentinel */ }, 4999 }; 5000 5001 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5002 5003 static struct mdio_driver mv88e6xxx_driver = { 5004 .probe = mv88e6xxx_probe, 5005 .remove = mv88e6xxx_remove, 5006 .mdiodrv.driver = { 5007 .name = "mv88e6085", 5008 .of_match_table = mv88e6xxx_of_match, 5009 .pm = &mv88e6xxx_pm_ops, 5010 }, 5011 }; 5012 5013 mdio_module_driver(mv88e6xxx_driver); 5014 5015 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5016 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5017 MODULE_LICENSE("GPL"); 5018