1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2015 CMC Electronics, Inc. 7 * Added support for VLAN Table Unit operations 8 * 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_mdio.h> 27 #include <linux/netdevice.h> 28 #include <linux/gpio/consumer.h> 29 #include <linux/phy.h> 30 #include <net/dsa.h> 31 #include <net/switchdev.h> 32 33 #include "mv88e6xxx.h" 34 #include "global1.h" 35 #include "global2.h" 36 37 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 38 { 39 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 40 dev_err(chip->dev, "Switch registers lock not held!\n"); 41 dump_stack(); 42 } 43 } 44 45 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 46 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 47 * 48 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 49 * is the only device connected to the SMI master. In this mode it responds to 50 * all 32 possible SMI addresses, and thus maps directly the internal devices. 51 * 52 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 53 * multiple devices to share the SMI interface. In this mode it responds to only 54 * 2 registers, used to indirectly access the internal SMI devices. 55 */ 56 57 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 58 int addr, int reg, u16 *val) 59 { 60 if (!chip->smi_ops) 61 return -EOPNOTSUPP; 62 63 return chip->smi_ops->read(chip, addr, reg, val); 64 } 65 66 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 67 int addr, int reg, u16 val) 68 { 69 if (!chip->smi_ops) 70 return -EOPNOTSUPP; 71 72 return chip->smi_ops->write(chip, addr, reg, val); 73 } 74 75 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 76 int addr, int reg, u16 *val) 77 { 78 int ret; 79 80 ret = mdiobus_read_nested(chip->bus, addr, reg); 81 if (ret < 0) 82 return ret; 83 84 *val = ret & 0xffff; 85 86 return 0; 87 } 88 89 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 90 int addr, int reg, u16 val) 91 { 92 int ret; 93 94 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 95 if (ret < 0) 96 return ret; 97 98 return 0; 99 } 100 101 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 102 .read = mv88e6xxx_smi_single_chip_read, 103 .write = mv88e6xxx_smi_single_chip_write, 104 }; 105 106 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 107 { 108 int ret; 109 int i; 110 111 for (i = 0; i < 16; i++) { 112 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 113 if (ret < 0) 114 return ret; 115 116 if ((ret & SMI_CMD_BUSY) == 0) 117 return 0; 118 } 119 120 return -ETIMEDOUT; 121 } 122 123 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 124 int addr, int reg, u16 *val) 125 { 126 int ret; 127 128 /* Wait for the bus to become free. */ 129 ret = mv88e6xxx_smi_multi_chip_wait(chip); 130 if (ret < 0) 131 return ret; 132 133 /* Transmit the read command. */ 134 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 135 SMI_CMD_OP_22_READ | (addr << 5) | reg); 136 if (ret < 0) 137 return ret; 138 139 /* Wait for the read command to complete. */ 140 ret = mv88e6xxx_smi_multi_chip_wait(chip); 141 if (ret < 0) 142 return ret; 143 144 /* Read the data. */ 145 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 146 if (ret < 0) 147 return ret; 148 149 *val = ret & 0xffff; 150 151 return 0; 152 } 153 154 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 155 int addr, int reg, u16 val) 156 { 157 int ret; 158 159 /* Wait for the bus to become free. */ 160 ret = mv88e6xxx_smi_multi_chip_wait(chip); 161 if (ret < 0) 162 return ret; 163 164 /* Transmit the data to write. */ 165 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 166 if (ret < 0) 167 return ret; 168 169 /* Transmit the write command. */ 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 171 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 172 if (ret < 0) 173 return ret; 174 175 /* Wait for the write command to complete. */ 176 ret = mv88e6xxx_smi_multi_chip_wait(chip); 177 if (ret < 0) 178 return ret; 179 180 return 0; 181 } 182 183 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 184 .read = mv88e6xxx_smi_multi_chip_read, 185 .write = mv88e6xxx_smi_multi_chip_write, 186 }; 187 188 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 189 { 190 int err; 191 192 assert_reg_lock(chip); 193 194 err = mv88e6xxx_smi_read(chip, addr, reg, val); 195 if (err) 196 return err; 197 198 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 199 addr, reg, *val); 200 201 return 0; 202 } 203 204 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 205 { 206 int err; 207 208 assert_reg_lock(chip); 209 210 err = mv88e6xxx_smi_write(chip, addr, reg, val); 211 if (err) 212 return err; 213 214 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 215 addr, reg, val); 216 217 return 0; 218 } 219 220 static int mv88e6xxx_port_read(struct mv88e6xxx_chip *chip, int port, int reg, 221 u16 *val) 222 { 223 int addr = chip->info->port_base_addr + port; 224 225 return mv88e6xxx_read(chip, addr, reg, val); 226 } 227 228 static int mv88e6xxx_port_write(struct mv88e6xxx_chip *chip, int port, int reg, 229 u16 val) 230 { 231 int addr = chip->info->port_base_addr + port; 232 233 return mv88e6xxx_write(chip, addr, reg, val); 234 } 235 236 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, 237 int reg, u16 *val) 238 { 239 int addr = phy; /* PHY devices addresses start at 0x0 */ 240 241 if (!chip->info->ops->phy_read) 242 return -EOPNOTSUPP; 243 244 return chip->info->ops->phy_read(chip, addr, reg, val); 245 } 246 247 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 248 int reg, u16 val) 249 { 250 int addr = phy; /* PHY devices addresses start at 0x0 */ 251 252 if (!chip->info->ops->phy_write) 253 return -EOPNOTSUPP; 254 255 return chip->info->ops->phy_write(chip, addr, reg, val); 256 } 257 258 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) 259 { 260 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) 261 return -EOPNOTSUPP; 262 263 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 264 } 265 266 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) 267 { 268 int err; 269 270 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ 271 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); 272 if (unlikely(err)) { 273 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", 274 phy, err); 275 } 276 } 277 278 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 279 u8 page, int reg, u16 *val) 280 { 281 int err; 282 283 /* There is no paging for registers 22 */ 284 if (reg == PHY_PAGE) 285 return -EINVAL; 286 287 err = mv88e6xxx_phy_page_get(chip, phy, page); 288 if (!err) { 289 err = mv88e6xxx_phy_read(chip, phy, reg, val); 290 mv88e6xxx_phy_page_put(chip, phy); 291 } 292 293 return err; 294 } 295 296 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, 297 u8 page, int reg, u16 val) 298 { 299 int err; 300 301 /* There is no paging for registers 22 */ 302 if (reg == PHY_PAGE) 303 return -EINVAL; 304 305 err = mv88e6xxx_phy_page_get(chip, phy, page); 306 if (!err) { 307 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 308 mv88e6xxx_phy_page_put(chip, phy); 309 } 310 311 return err; 312 } 313 314 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 315 { 316 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 317 reg, val); 318 } 319 320 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 321 { 322 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 323 reg, val); 324 } 325 326 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 327 { 328 int i; 329 330 for (i = 0; i < 16; i++) { 331 u16 val; 332 int err; 333 334 err = mv88e6xxx_read(chip, addr, reg, &val); 335 if (err) 336 return err; 337 338 if (!(val & mask)) 339 return 0; 340 341 usleep_range(1000, 2000); 342 } 343 344 dev_err(chip->dev, "Timeout while waiting for switch\n"); 345 return -ETIMEDOUT; 346 } 347 348 /* Indirect write to single pointer-data register with an Update bit */ 349 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 350 { 351 u16 val; 352 int err; 353 354 /* Wait until the previous operation is completed */ 355 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 356 if (err) 357 return err; 358 359 /* Set the Update bit to trigger a write operation */ 360 val = BIT(15) | update; 361 362 return mv88e6xxx_write(chip, addr, reg, val); 363 } 364 365 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) 366 { 367 u16 val; 368 int i, err; 369 370 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); 371 if (err) 372 return err; 373 374 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, 375 val & ~GLOBAL_CONTROL_PPU_ENABLE); 376 if (err) 377 return err; 378 379 for (i = 0; i < 16; i++) { 380 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); 381 if (err) 382 return err; 383 384 usleep_range(1000, 2000); 385 if ((val & GLOBAL_STATUS_PPU_MASK) != GLOBAL_STATUS_PPU_POLLING) 386 return 0; 387 } 388 389 return -ETIMEDOUT; 390 } 391 392 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) 393 { 394 u16 val; 395 int i, err; 396 397 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &val); 398 if (err) 399 return err; 400 401 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, 402 val | GLOBAL_CONTROL_PPU_ENABLE); 403 if (err) 404 return err; 405 406 for (i = 0; i < 16; i++) { 407 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, &val); 408 if (err) 409 return err; 410 411 usleep_range(1000, 2000); 412 if ((val & GLOBAL_STATUS_PPU_MASK) == GLOBAL_STATUS_PPU_POLLING) 413 return 0; 414 } 415 416 return -ETIMEDOUT; 417 } 418 419 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) 420 { 421 struct mv88e6xxx_chip *chip; 422 423 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); 424 425 mutex_lock(&chip->reg_lock); 426 427 if (mutex_trylock(&chip->ppu_mutex)) { 428 if (mv88e6xxx_ppu_enable(chip) == 0) 429 chip->ppu_disabled = 0; 430 mutex_unlock(&chip->ppu_mutex); 431 } 432 433 mutex_unlock(&chip->reg_lock); 434 } 435 436 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) 437 { 438 struct mv88e6xxx_chip *chip = (void *)_ps; 439 440 schedule_work(&chip->ppu_work); 441 } 442 443 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) 444 { 445 int ret; 446 447 mutex_lock(&chip->ppu_mutex); 448 449 /* If the PHY polling unit is enabled, disable it so that 450 * we can access the PHY registers. If it was already 451 * disabled, cancel the timer that is going to re-enable 452 * it. 453 */ 454 if (!chip->ppu_disabled) { 455 ret = mv88e6xxx_ppu_disable(chip); 456 if (ret < 0) { 457 mutex_unlock(&chip->ppu_mutex); 458 return ret; 459 } 460 chip->ppu_disabled = 1; 461 } else { 462 del_timer(&chip->ppu_timer); 463 ret = 0; 464 } 465 466 return ret; 467 } 468 469 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) 470 { 471 /* Schedule a timer to re-enable the PHY polling unit. */ 472 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); 473 mutex_unlock(&chip->ppu_mutex); 474 } 475 476 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) 477 { 478 mutex_init(&chip->ppu_mutex); 479 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); 480 init_timer(&chip->ppu_timer); 481 chip->ppu_timer.data = (unsigned long)chip; 482 chip->ppu_timer.function = mv88e6xxx_ppu_reenable_timer; 483 } 484 485 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) 486 { 487 del_timer_sync(&chip->ppu_timer); 488 } 489 490 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, int addr, 491 int reg, u16 *val) 492 { 493 int err; 494 495 err = mv88e6xxx_ppu_access_get(chip); 496 if (!err) { 497 err = mv88e6xxx_read(chip, addr, reg, val); 498 mv88e6xxx_ppu_access_put(chip); 499 } 500 501 return err; 502 } 503 504 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, int addr, 505 int reg, u16 val) 506 { 507 int err; 508 509 err = mv88e6xxx_ppu_access_get(chip); 510 if (!err) { 511 err = mv88e6xxx_write(chip, addr, reg, val); 512 mv88e6xxx_ppu_access_put(chip); 513 } 514 515 return err; 516 } 517 518 static bool mv88e6xxx_6065_family(struct mv88e6xxx_chip *chip) 519 { 520 return chip->info->family == MV88E6XXX_FAMILY_6065; 521 } 522 523 static bool mv88e6xxx_6095_family(struct mv88e6xxx_chip *chip) 524 { 525 return chip->info->family == MV88E6XXX_FAMILY_6095; 526 } 527 528 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) 529 { 530 return chip->info->family == MV88E6XXX_FAMILY_6097; 531 } 532 533 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) 534 { 535 return chip->info->family == MV88E6XXX_FAMILY_6165; 536 } 537 538 static bool mv88e6xxx_6185_family(struct mv88e6xxx_chip *chip) 539 { 540 return chip->info->family == MV88E6XXX_FAMILY_6185; 541 } 542 543 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) 544 { 545 return chip->info->family == MV88E6XXX_FAMILY_6320; 546 } 547 548 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) 549 { 550 return chip->info->family == MV88E6XXX_FAMILY_6351; 551 } 552 553 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) 554 { 555 return chip->info->family == MV88E6XXX_FAMILY_6352; 556 } 557 558 /* We expect the switch to perform auto negotiation if there is a real 559 * phy. However, in the case of a fixed link phy, we force the port 560 * settings from the fixed link settings. 561 */ 562 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 563 struct phy_device *phydev) 564 { 565 struct mv88e6xxx_chip *chip = ds->priv; 566 u16 reg; 567 int err; 568 569 if (!phy_is_pseudo_fixed_link(phydev)) 570 return; 571 572 mutex_lock(&chip->reg_lock); 573 574 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); 575 if (err) 576 goto out; 577 578 reg &= ~(PORT_PCS_CTRL_LINK_UP | 579 PORT_PCS_CTRL_FORCE_LINK | 580 PORT_PCS_CTRL_DUPLEX_FULL | 581 PORT_PCS_CTRL_FORCE_DUPLEX | 582 PORT_PCS_CTRL_UNFORCED); 583 584 reg |= PORT_PCS_CTRL_FORCE_LINK; 585 if (phydev->link) 586 reg |= PORT_PCS_CTRL_LINK_UP; 587 588 if (mv88e6xxx_6065_family(chip) && phydev->speed > SPEED_100) 589 goto out; 590 591 switch (phydev->speed) { 592 case SPEED_1000: 593 reg |= PORT_PCS_CTRL_1000; 594 break; 595 case SPEED_100: 596 reg |= PORT_PCS_CTRL_100; 597 break; 598 case SPEED_10: 599 reg |= PORT_PCS_CTRL_10; 600 break; 601 default: 602 pr_info("Unknown speed"); 603 goto out; 604 } 605 606 reg |= PORT_PCS_CTRL_FORCE_DUPLEX; 607 if (phydev->duplex == DUPLEX_FULL) 608 reg |= PORT_PCS_CTRL_DUPLEX_FULL; 609 610 if ((mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip)) && 611 (port >= mv88e6xxx_num_ports(chip) - 2)) { 612 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_RXID) 613 reg |= PORT_PCS_CTRL_RGMII_DELAY_RXCLK; 614 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_TXID) 615 reg |= PORT_PCS_CTRL_RGMII_DELAY_TXCLK; 616 if (phydev->interface == PHY_INTERFACE_MODE_RGMII_ID) 617 reg |= (PORT_PCS_CTRL_RGMII_DELAY_RXCLK | 618 PORT_PCS_CTRL_RGMII_DELAY_TXCLK); 619 } 620 mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); 621 622 out: 623 mutex_unlock(&chip->reg_lock); 624 } 625 626 static int _mv88e6xxx_stats_wait(struct mv88e6xxx_chip *chip) 627 { 628 u16 val; 629 int i, err; 630 631 for (i = 0; i < 10; i++) { 632 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_OP, &val); 633 if ((val & GLOBAL_STATS_OP_BUSY) == 0) 634 return 0; 635 } 636 637 return -ETIMEDOUT; 638 } 639 640 static int _mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 641 { 642 int err; 643 644 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) 645 port = (port + 1) << 5; 646 647 /* Snapshot the hardware statistics counters for this port. */ 648 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 649 GLOBAL_STATS_OP_CAPTURE_PORT | 650 GLOBAL_STATS_OP_HIST_RX_TX | port); 651 if (err) 652 return err; 653 654 /* Wait for the snapshotting to complete. */ 655 return _mv88e6xxx_stats_wait(chip); 656 } 657 658 static void _mv88e6xxx_stats_read(struct mv88e6xxx_chip *chip, 659 int stat, u32 *val) 660 { 661 u32 value; 662 u16 reg; 663 int err; 664 665 *val = 0; 666 667 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 668 GLOBAL_STATS_OP_READ_CAPTURED | 669 GLOBAL_STATS_OP_HIST_RX_TX | stat); 670 if (err) 671 return; 672 673 err = _mv88e6xxx_stats_wait(chip); 674 if (err) 675 return; 676 677 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_32, ®); 678 if (err) 679 return; 680 681 value = reg << 16; 682 683 err = mv88e6xxx_g1_read(chip, GLOBAL_STATS_COUNTER_01, ®); 684 if (err) 685 return; 686 687 *val = value | reg; 688 } 689 690 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 691 { "in_good_octets", 8, 0x00, BANK0, }, 692 { "in_bad_octets", 4, 0x02, BANK0, }, 693 { "in_unicast", 4, 0x04, BANK0, }, 694 { "in_broadcasts", 4, 0x06, BANK0, }, 695 { "in_multicasts", 4, 0x07, BANK0, }, 696 { "in_pause", 4, 0x16, BANK0, }, 697 { "in_undersize", 4, 0x18, BANK0, }, 698 { "in_fragments", 4, 0x19, BANK0, }, 699 { "in_oversize", 4, 0x1a, BANK0, }, 700 { "in_jabber", 4, 0x1b, BANK0, }, 701 { "in_rx_error", 4, 0x1c, BANK0, }, 702 { "in_fcs_error", 4, 0x1d, BANK0, }, 703 { "out_octets", 8, 0x0e, BANK0, }, 704 { "out_unicast", 4, 0x10, BANK0, }, 705 { "out_broadcasts", 4, 0x13, BANK0, }, 706 { "out_multicasts", 4, 0x12, BANK0, }, 707 { "out_pause", 4, 0x15, BANK0, }, 708 { "excessive", 4, 0x11, BANK0, }, 709 { "collisions", 4, 0x1e, BANK0, }, 710 { "deferred", 4, 0x05, BANK0, }, 711 { "single", 4, 0x14, BANK0, }, 712 { "multiple", 4, 0x17, BANK0, }, 713 { "out_fcs_error", 4, 0x03, BANK0, }, 714 { "late", 4, 0x1f, BANK0, }, 715 { "hist_64bytes", 4, 0x08, BANK0, }, 716 { "hist_65_127bytes", 4, 0x09, BANK0, }, 717 { "hist_128_255bytes", 4, 0x0a, BANK0, }, 718 { "hist_256_511bytes", 4, 0x0b, BANK0, }, 719 { "hist_512_1023bytes", 4, 0x0c, BANK0, }, 720 { "hist_1024_max_bytes", 4, 0x0d, BANK0, }, 721 { "sw_in_discards", 4, 0x10, PORT, }, 722 { "sw_in_filtered", 2, 0x12, PORT, }, 723 { "sw_out_filtered", 2, 0x13, PORT, }, 724 { "in_discards", 4, 0x00 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 725 { "in_filtered", 4, 0x01 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 726 { "in_accepted", 4, 0x02 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 727 { "in_bad_accepted", 4, 0x03 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 728 { "in_good_avb_class_a", 4, 0x04 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 729 { "in_good_avb_class_b", 4, 0x05 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 730 { "in_bad_avb_class_a", 4, 0x06 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 731 { "in_bad_avb_class_b", 4, 0x07 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 732 { "tcam_counter_0", 4, 0x08 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 733 { "tcam_counter_1", 4, 0x09 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 734 { "tcam_counter_2", 4, 0x0a | GLOBAL_STATS_OP_BANK_1, BANK1, }, 735 { "tcam_counter_3", 4, 0x0b | GLOBAL_STATS_OP_BANK_1, BANK1, }, 736 { "in_da_unknown", 4, 0x0e | GLOBAL_STATS_OP_BANK_1, BANK1, }, 737 { "in_management", 4, 0x0f | GLOBAL_STATS_OP_BANK_1, BANK1, }, 738 { "out_queue_0", 4, 0x10 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 739 { "out_queue_1", 4, 0x11 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 740 { "out_queue_2", 4, 0x12 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 741 { "out_queue_3", 4, 0x13 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 742 { "out_queue_4", 4, 0x14 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 743 { "out_queue_5", 4, 0x15 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 744 { "out_queue_6", 4, 0x16 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 745 { "out_queue_7", 4, 0x17 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 746 { "out_cut_through", 4, 0x18 | GLOBAL_STATS_OP_BANK_1, BANK1, }, 747 { "out_octets_a", 4, 0x1a | GLOBAL_STATS_OP_BANK_1, BANK1, }, 748 { "out_octets_b", 4, 0x1b | GLOBAL_STATS_OP_BANK_1, BANK1, }, 749 { "out_management", 4, 0x1f | GLOBAL_STATS_OP_BANK_1, BANK1, }, 750 }; 751 752 static bool mv88e6xxx_has_stat(struct mv88e6xxx_chip *chip, 753 struct mv88e6xxx_hw_stat *stat) 754 { 755 switch (stat->type) { 756 case BANK0: 757 return true; 758 case BANK1: 759 return mv88e6xxx_6320_family(chip); 760 case PORT: 761 return mv88e6xxx_6095_family(chip) || 762 mv88e6xxx_6185_family(chip) || 763 mv88e6xxx_6097_family(chip) || 764 mv88e6xxx_6165_family(chip) || 765 mv88e6xxx_6351_family(chip) || 766 mv88e6xxx_6352_family(chip); 767 } 768 return false; 769 } 770 771 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 772 struct mv88e6xxx_hw_stat *s, 773 int port) 774 { 775 u32 low; 776 u32 high = 0; 777 int err; 778 u16 reg; 779 u64 value; 780 781 switch (s->type) { 782 case PORT: 783 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 784 if (err) 785 return UINT64_MAX; 786 787 low = reg; 788 if (s->sizeof_stat == 4) { 789 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 790 if (err) 791 return UINT64_MAX; 792 high = reg; 793 } 794 break; 795 case BANK0: 796 case BANK1: 797 _mv88e6xxx_stats_read(chip, s->reg, &low); 798 if (s->sizeof_stat == 8) 799 _mv88e6xxx_stats_read(chip, s->reg + 1, &high); 800 } 801 value = (((u64)high) << 16) | low; 802 return value; 803 } 804 805 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 806 uint8_t *data) 807 { 808 struct mv88e6xxx_chip *chip = ds->priv; 809 struct mv88e6xxx_hw_stat *stat; 810 int i, j; 811 812 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 813 stat = &mv88e6xxx_hw_stats[i]; 814 if (mv88e6xxx_has_stat(chip, stat)) { 815 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 816 ETH_GSTRING_LEN); 817 j++; 818 } 819 } 820 } 821 822 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 823 { 824 struct mv88e6xxx_chip *chip = ds->priv; 825 struct mv88e6xxx_hw_stat *stat; 826 int i, j; 827 828 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 829 stat = &mv88e6xxx_hw_stats[i]; 830 if (mv88e6xxx_has_stat(chip, stat)) 831 j++; 832 } 833 return j; 834 } 835 836 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 837 uint64_t *data) 838 { 839 struct mv88e6xxx_chip *chip = ds->priv; 840 struct mv88e6xxx_hw_stat *stat; 841 int ret; 842 int i, j; 843 844 mutex_lock(&chip->reg_lock); 845 846 ret = _mv88e6xxx_stats_snapshot(chip, port); 847 if (ret < 0) { 848 mutex_unlock(&chip->reg_lock); 849 return; 850 } 851 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 852 stat = &mv88e6xxx_hw_stats[i]; 853 if (mv88e6xxx_has_stat(chip, stat)) { 854 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port); 855 j++; 856 } 857 } 858 859 mutex_unlock(&chip->reg_lock); 860 } 861 862 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 863 { 864 return 32 * sizeof(u16); 865 } 866 867 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 868 struct ethtool_regs *regs, void *_p) 869 { 870 struct mv88e6xxx_chip *chip = ds->priv; 871 int err; 872 u16 reg; 873 u16 *p = _p; 874 int i; 875 876 regs->version = 0; 877 878 memset(p, 0xff, 32 * sizeof(u16)); 879 880 mutex_lock(&chip->reg_lock); 881 882 for (i = 0; i < 32; i++) { 883 884 err = mv88e6xxx_port_read(chip, port, i, ®); 885 if (!err) 886 p[i] = reg; 887 } 888 889 mutex_unlock(&chip->reg_lock); 890 } 891 892 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) 893 { 894 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); 895 } 896 897 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 898 struct ethtool_eee *e) 899 { 900 struct mv88e6xxx_chip *chip = ds->priv; 901 u16 reg; 902 int err; 903 904 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 905 return -EOPNOTSUPP; 906 907 mutex_lock(&chip->reg_lock); 908 909 err = mv88e6xxx_phy_read(chip, port, 16, ®); 910 if (err) 911 goto out; 912 913 e->eee_enabled = !!(reg & 0x0200); 914 e->tx_lpi_enabled = !!(reg & 0x0100); 915 916 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 917 if (err) 918 goto out; 919 920 e->eee_active = !!(reg & PORT_STATUS_EEE); 921 out: 922 mutex_unlock(&chip->reg_lock); 923 924 return err; 925 } 926 927 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 928 struct phy_device *phydev, struct ethtool_eee *e) 929 { 930 struct mv88e6xxx_chip *chip = ds->priv; 931 u16 reg; 932 int err; 933 934 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 935 return -EOPNOTSUPP; 936 937 mutex_lock(&chip->reg_lock); 938 939 err = mv88e6xxx_phy_read(chip, port, 16, ®); 940 if (err) 941 goto out; 942 943 reg &= ~0x0300; 944 if (e->eee_enabled) 945 reg |= 0x0200; 946 if (e->tx_lpi_enabled) 947 reg |= 0x0100; 948 949 err = mv88e6xxx_phy_write(chip, port, 16, reg); 950 out: 951 mutex_unlock(&chip->reg_lock); 952 953 return err; 954 } 955 956 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) 957 { 958 u16 val; 959 int err; 960 961 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { 962 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); 963 if (err) 964 return err; 965 } else if (mv88e6xxx_num_databases(chip) == 256) { 966 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 967 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 968 if (err) 969 return err; 970 971 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 972 (val & 0xfff) | ((fid << 8) & 0xf000)); 973 if (err) 974 return err; 975 976 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 977 cmd |= fid & 0xf; 978 } 979 980 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); 981 if (err) 982 return err; 983 984 return _mv88e6xxx_atu_wait(chip); 985 } 986 987 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, 988 struct mv88e6xxx_atu_entry *entry) 989 { 990 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; 991 992 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { 993 unsigned int mask, shift; 994 995 if (entry->trunk) { 996 data |= GLOBAL_ATU_DATA_TRUNK; 997 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 998 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 999 } else { 1000 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 1001 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 1002 } 1003 1004 data |= (entry->portv_trunkid << shift) & mask; 1005 } 1006 1007 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); 1008 } 1009 1010 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, 1011 struct mv88e6xxx_atu_entry *entry, 1012 bool static_too) 1013 { 1014 int op; 1015 int err; 1016 1017 err = _mv88e6xxx_atu_wait(chip); 1018 if (err) 1019 return err; 1020 1021 err = _mv88e6xxx_atu_data_write(chip, entry); 1022 if (err) 1023 return err; 1024 1025 if (entry->fid) { 1026 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : 1027 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 1028 } else { 1029 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : 1030 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; 1031 } 1032 1033 return _mv88e6xxx_atu_cmd(chip, entry->fid, op); 1034 } 1035 1036 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, 1037 u16 fid, bool static_too) 1038 { 1039 struct mv88e6xxx_atu_entry entry = { 1040 .fid = fid, 1041 .state = 0, /* EntryState bits must be 0 */ 1042 }; 1043 1044 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1045 } 1046 1047 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 1048 int from_port, int to_port, bool static_too) 1049 { 1050 struct mv88e6xxx_atu_entry entry = { 1051 .trunk = false, 1052 .fid = fid, 1053 }; 1054 1055 /* EntryState bits must be 0xF */ 1056 entry.state = GLOBAL_ATU_DATA_STATE_MASK; 1057 1058 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ 1059 entry.portv_trunkid = (to_port & 0x0f) << 4; 1060 entry.portv_trunkid |= from_port & 0x0f; 1061 1062 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1063 } 1064 1065 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, 1066 int port, bool static_too) 1067 { 1068 /* Destination port 0xF means remove the entries */ 1069 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); 1070 } 1071 1072 static const char * const mv88e6xxx_port_state_names[] = { 1073 [PORT_CONTROL_STATE_DISABLED] = "Disabled", 1074 [PORT_CONTROL_STATE_BLOCKING] = "Blocking/Listening", 1075 [PORT_CONTROL_STATE_LEARNING] = "Learning", 1076 [PORT_CONTROL_STATE_FORWARDING] = "Forwarding", 1077 }; 1078 1079 static int _mv88e6xxx_port_state(struct mv88e6xxx_chip *chip, int port, 1080 u8 state) 1081 { 1082 struct dsa_switch *ds = chip->ds; 1083 u16 reg; 1084 int err; 1085 u8 oldstate; 1086 1087 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL, ®); 1088 if (err) 1089 return err; 1090 1091 oldstate = reg & PORT_CONTROL_STATE_MASK; 1092 1093 reg &= ~PORT_CONTROL_STATE_MASK; 1094 reg |= state; 1095 1096 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 1097 if (err) 1098 return err; 1099 1100 netdev_dbg(ds->ports[port].netdev, "PortState %s (was %s)\n", 1101 mv88e6xxx_port_state_names[state], 1102 mv88e6xxx_port_state_names[oldstate]); 1103 1104 return 0; 1105 } 1106 1107 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) 1108 { 1109 struct net_device *bridge = chip->ports[port].bridge_dev; 1110 const u16 mask = (1 << mv88e6xxx_num_ports(chip)) - 1; 1111 struct dsa_switch *ds = chip->ds; 1112 u16 output_ports = 0; 1113 u16 reg; 1114 int err; 1115 int i; 1116 1117 /* allow CPU port or DSA link(s) to send frames to every port */ 1118 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 1119 output_ports = mask; 1120 } else { 1121 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1122 /* allow sending frames to every group member */ 1123 if (bridge && chip->ports[i].bridge_dev == bridge) 1124 output_ports |= BIT(i); 1125 1126 /* allow sending frames to CPU port and DSA link(s) */ 1127 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1128 output_ports |= BIT(i); 1129 } 1130 } 1131 1132 /* prevent frames from going back out of the port they came in on */ 1133 output_ports &= ~BIT(port); 1134 1135 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®); 1136 if (err) 1137 return err; 1138 1139 reg &= ~mask; 1140 reg |= output_ports & mask; 1141 1142 return mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg); 1143 } 1144 1145 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1146 u8 state) 1147 { 1148 struct mv88e6xxx_chip *chip = ds->priv; 1149 int stp_state; 1150 int err; 1151 1152 switch (state) { 1153 case BR_STATE_DISABLED: 1154 stp_state = PORT_CONTROL_STATE_DISABLED; 1155 break; 1156 case BR_STATE_BLOCKING: 1157 case BR_STATE_LISTENING: 1158 stp_state = PORT_CONTROL_STATE_BLOCKING; 1159 break; 1160 case BR_STATE_LEARNING: 1161 stp_state = PORT_CONTROL_STATE_LEARNING; 1162 break; 1163 case BR_STATE_FORWARDING: 1164 default: 1165 stp_state = PORT_CONTROL_STATE_FORWARDING; 1166 break; 1167 } 1168 1169 mutex_lock(&chip->reg_lock); 1170 err = _mv88e6xxx_port_state(chip, port, stp_state); 1171 mutex_unlock(&chip->reg_lock); 1172 1173 if (err) 1174 netdev_err(ds->ports[port].netdev, 1175 "failed to update state to %s\n", 1176 mv88e6xxx_port_state_names[stp_state]); 1177 } 1178 1179 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1180 { 1181 struct mv88e6xxx_chip *chip = ds->priv; 1182 int err; 1183 1184 mutex_lock(&chip->reg_lock); 1185 err = _mv88e6xxx_atu_remove(chip, 0, port, false); 1186 mutex_unlock(&chip->reg_lock); 1187 1188 if (err) 1189 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); 1190 } 1191 1192 static int _mv88e6xxx_port_pvid(struct mv88e6xxx_chip *chip, int port, 1193 u16 *new, u16 *old) 1194 { 1195 struct dsa_switch *ds = chip->ds; 1196 u16 pvid, reg; 1197 int err; 1198 1199 err = mv88e6xxx_port_read(chip, port, PORT_DEFAULT_VLAN, ®); 1200 if (err) 1201 return err; 1202 1203 pvid = reg & PORT_DEFAULT_VLAN_MASK; 1204 1205 if (new) { 1206 reg &= ~PORT_DEFAULT_VLAN_MASK; 1207 reg |= *new & PORT_DEFAULT_VLAN_MASK; 1208 1209 err = mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, reg); 1210 if (err) 1211 return err; 1212 1213 netdev_dbg(ds->ports[port].netdev, 1214 "DefaultVID %d (was %d)\n", *new, pvid); 1215 } 1216 1217 if (old) 1218 *old = pvid; 1219 1220 return 0; 1221 } 1222 1223 static int _mv88e6xxx_port_pvid_get(struct mv88e6xxx_chip *chip, 1224 int port, u16 *pvid) 1225 { 1226 return _mv88e6xxx_port_pvid(chip, port, NULL, pvid); 1227 } 1228 1229 static int _mv88e6xxx_port_pvid_set(struct mv88e6xxx_chip *chip, 1230 int port, u16 pvid) 1231 { 1232 return _mv88e6xxx_port_pvid(chip, port, &pvid, NULL); 1233 } 1234 1235 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) 1236 { 1237 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); 1238 } 1239 1240 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) 1241 { 1242 int err; 1243 1244 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); 1245 if (err) 1246 return err; 1247 1248 return _mv88e6xxx_vtu_wait(chip); 1249 } 1250 1251 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) 1252 { 1253 int ret; 1254 1255 ret = _mv88e6xxx_vtu_wait(chip); 1256 if (ret < 0) 1257 return ret; 1258 1259 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); 1260 } 1261 1262 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, 1263 struct mv88e6xxx_vtu_entry *entry, 1264 unsigned int nibble_offset) 1265 { 1266 u16 regs[3]; 1267 int i, err; 1268 1269 for (i = 0; i < 3; ++i) { 1270 u16 *reg = ®s[i]; 1271 1272 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1273 if (err) 1274 return err; 1275 } 1276 1277 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1278 unsigned int shift = (i % 4) * 4 + nibble_offset; 1279 u16 reg = regs[i / 4]; 1280 1281 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; 1282 } 1283 1284 return 0; 1285 } 1286 1287 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, 1288 struct mv88e6xxx_vtu_entry *entry) 1289 { 1290 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); 1291 } 1292 1293 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, 1294 struct mv88e6xxx_vtu_entry *entry) 1295 { 1296 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); 1297 } 1298 1299 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, 1300 struct mv88e6xxx_vtu_entry *entry, 1301 unsigned int nibble_offset) 1302 { 1303 u16 regs[3] = { 0 }; 1304 int i, err; 1305 1306 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1307 unsigned int shift = (i % 4) * 4 + nibble_offset; 1308 u8 data = entry->data[i]; 1309 1310 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; 1311 } 1312 1313 for (i = 0; i < 3; ++i) { 1314 u16 reg = regs[i]; 1315 1316 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1317 if (err) 1318 return err; 1319 } 1320 1321 return 0; 1322 } 1323 1324 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, 1325 struct mv88e6xxx_vtu_entry *entry) 1326 { 1327 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); 1328 } 1329 1330 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, 1331 struct mv88e6xxx_vtu_entry *entry) 1332 { 1333 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); 1334 } 1335 1336 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) 1337 { 1338 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, 1339 vid & GLOBAL_VTU_VID_MASK); 1340 } 1341 1342 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1343 struct mv88e6xxx_vtu_entry *entry) 1344 { 1345 struct mv88e6xxx_vtu_entry next = { 0 }; 1346 u16 val; 1347 int err; 1348 1349 err = _mv88e6xxx_vtu_wait(chip); 1350 if (err) 1351 return err; 1352 1353 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); 1354 if (err) 1355 return err; 1356 1357 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1358 if (err) 1359 return err; 1360 1361 next.vid = val & GLOBAL_VTU_VID_MASK; 1362 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1363 1364 if (next.valid) { 1365 err = mv88e6xxx_vtu_data_read(chip, &next); 1366 if (err) 1367 return err; 1368 1369 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1370 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); 1371 if (err) 1372 return err; 1373 1374 next.fid = val & GLOBAL_VTU_FID_MASK; 1375 } else if (mv88e6xxx_num_databases(chip) == 256) { 1376 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1377 * VTU DBNum[3:0] are located in VTU Operation 3:0 1378 */ 1379 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); 1380 if (err) 1381 return err; 1382 1383 next.fid = (val & 0xf00) >> 4; 1384 next.fid |= val & 0xf; 1385 } 1386 1387 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1388 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1389 if (err) 1390 return err; 1391 1392 next.sid = val & GLOBAL_VTU_SID_MASK; 1393 } 1394 } 1395 1396 *entry = next; 1397 return 0; 1398 } 1399 1400 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, 1401 struct switchdev_obj_port_vlan *vlan, 1402 int (*cb)(struct switchdev_obj *obj)) 1403 { 1404 struct mv88e6xxx_chip *chip = ds->priv; 1405 struct mv88e6xxx_vtu_entry next; 1406 u16 pvid; 1407 int err; 1408 1409 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1410 return -EOPNOTSUPP; 1411 1412 mutex_lock(&chip->reg_lock); 1413 1414 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); 1415 if (err) 1416 goto unlock; 1417 1418 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1419 if (err) 1420 goto unlock; 1421 1422 do { 1423 err = _mv88e6xxx_vtu_getnext(chip, &next); 1424 if (err) 1425 break; 1426 1427 if (!next.valid) 1428 break; 1429 1430 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1431 continue; 1432 1433 /* reinit and dump this VLAN obj */ 1434 vlan->vid_begin = next.vid; 1435 vlan->vid_end = next.vid; 1436 vlan->flags = 0; 1437 1438 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) 1439 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1440 1441 if (next.vid == pvid) 1442 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1443 1444 err = cb(&vlan->obj); 1445 if (err) 1446 break; 1447 } while (next.vid < GLOBAL_VTU_VID_MASK); 1448 1449 unlock: 1450 mutex_unlock(&chip->reg_lock); 1451 1452 return err; 1453 } 1454 1455 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1456 struct mv88e6xxx_vtu_entry *entry) 1457 { 1458 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; 1459 u16 reg = 0; 1460 int err; 1461 1462 err = _mv88e6xxx_vtu_wait(chip); 1463 if (err) 1464 return err; 1465 1466 if (!entry->valid) 1467 goto loadpurge; 1468 1469 /* Write port member tags */ 1470 err = mv88e6xxx_vtu_data_write(chip, entry); 1471 if (err) 1472 return err; 1473 1474 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1475 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1476 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1477 if (err) 1478 return err; 1479 } 1480 1481 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1482 reg = entry->fid & GLOBAL_VTU_FID_MASK; 1483 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); 1484 if (err) 1485 return err; 1486 } else if (mv88e6xxx_num_databases(chip) == 256) { 1487 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1488 * VTU DBNum[3:0] are located in VTU Operation 3:0 1489 */ 1490 op |= (entry->fid & 0xf0) << 8; 1491 op |= entry->fid & 0xf; 1492 } 1493 1494 reg = GLOBAL_VTU_VID_VALID; 1495 loadpurge: 1496 reg |= entry->vid & GLOBAL_VTU_VID_MASK; 1497 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1498 if (err) 1499 return err; 1500 1501 return _mv88e6xxx_vtu_cmd(chip, op); 1502 } 1503 1504 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, 1505 struct mv88e6xxx_vtu_entry *entry) 1506 { 1507 struct mv88e6xxx_vtu_entry next = { 0 }; 1508 u16 val; 1509 int err; 1510 1511 err = _mv88e6xxx_vtu_wait(chip); 1512 if (err) 1513 return err; 1514 1515 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, 1516 sid & GLOBAL_VTU_SID_MASK); 1517 if (err) 1518 return err; 1519 1520 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); 1521 if (err) 1522 return err; 1523 1524 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1525 if (err) 1526 return err; 1527 1528 next.sid = val & GLOBAL_VTU_SID_MASK; 1529 1530 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1531 if (err) 1532 return err; 1533 1534 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1535 1536 if (next.valid) { 1537 err = mv88e6xxx_stu_data_read(chip, &next); 1538 if (err) 1539 return err; 1540 } 1541 1542 *entry = next; 1543 return 0; 1544 } 1545 1546 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1547 struct mv88e6xxx_vtu_entry *entry) 1548 { 1549 u16 reg = 0; 1550 int err; 1551 1552 err = _mv88e6xxx_vtu_wait(chip); 1553 if (err) 1554 return err; 1555 1556 if (!entry->valid) 1557 goto loadpurge; 1558 1559 /* Write port states */ 1560 err = mv88e6xxx_stu_data_write(chip, entry); 1561 if (err) 1562 return err; 1563 1564 reg = GLOBAL_VTU_VID_VALID; 1565 loadpurge: 1566 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1567 if (err) 1568 return err; 1569 1570 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1571 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1572 if (err) 1573 return err; 1574 1575 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); 1576 } 1577 1578 static int _mv88e6xxx_port_fid(struct mv88e6xxx_chip *chip, int port, 1579 u16 *new, u16 *old) 1580 { 1581 struct dsa_switch *ds = chip->ds; 1582 u16 upper_mask; 1583 u16 fid; 1584 u16 reg; 1585 int err; 1586 1587 if (mv88e6xxx_num_databases(chip) == 4096) 1588 upper_mask = 0xff; 1589 else if (mv88e6xxx_num_databases(chip) == 256) 1590 upper_mask = 0xf; 1591 else 1592 return -EOPNOTSUPP; 1593 1594 /* Port's default FID bits 3:0 are located in reg 0x06, offset 12 */ 1595 err = mv88e6xxx_port_read(chip, port, PORT_BASE_VLAN, ®); 1596 if (err) 1597 return err; 1598 1599 fid = (reg & PORT_BASE_VLAN_FID_3_0_MASK) >> 12; 1600 1601 if (new) { 1602 reg &= ~PORT_BASE_VLAN_FID_3_0_MASK; 1603 reg |= (*new << 12) & PORT_BASE_VLAN_FID_3_0_MASK; 1604 1605 err = mv88e6xxx_port_write(chip, port, PORT_BASE_VLAN, reg); 1606 if (err) 1607 return err; 1608 } 1609 1610 /* Port's default FID bits 11:4 are located in reg 0x05, offset 0 */ 1611 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_1, ®); 1612 if (err) 1613 return err; 1614 1615 fid |= (reg & upper_mask) << 4; 1616 1617 if (new) { 1618 reg &= ~upper_mask; 1619 reg |= (*new >> 4) & upper_mask; 1620 1621 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, reg); 1622 if (err) 1623 return err; 1624 1625 netdev_dbg(ds->ports[port].netdev, 1626 "FID %d (was %d)\n", *new, fid); 1627 } 1628 1629 if (old) 1630 *old = fid; 1631 1632 return 0; 1633 } 1634 1635 static int _mv88e6xxx_port_fid_get(struct mv88e6xxx_chip *chip, 1636 int port, u16 *fid) 1637 { 1638 return _mv88e6xxx_port_fid(chip, port, NULL, fid); 1639 } 1640 1641 static int _mv88e6xxx_port_fid_set(struct mv88e6xxx_chip *chip, 1642 int port, u16 fid) 1643 { 1644 return _mv88e6xxx_port_fid(chip, port, &fid, NULL); 1645 } 1646 1647 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) 1648 { 1649 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1650 struct mv88e6xxx_vtu_entry vlan; 1651 int i, err; 1652 1653 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1654 1655 /* Set every FID bit used by the (un)bridged ports */ 1656 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1657 err = _mv88e6xxx_port_fid_get(chip, i, fid); 1658 if (err) 1659 return err; 1660 1661 set_bit(*fid, fid_bitmap); 1662 } 1663 1664 /* Set every FID bit used by the VLAN entries */ 1665 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1666 if (err) 1667 return err; 1668 1669 do { 1670 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1671 if (err) 1672 return err; 1673 1674 if (!vlan.valid) 1675 break; 1676 1677 set_bit(vlan.fid, fid_bitmap); 1678 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 1679 1680 /* The reset value 0x000 is used to indicate that multiple address 1681 * databases are not needed. Return the next positive available. 1682 */ 1683 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1684 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1685 return -ENOSPC; 1686 1687 /* Clear the database */ 1688 return _mv88e6xxx_atu_flush(chip, *fid, true); 1689 } 1690 1691 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, 1692 struct mv88e6xxx_vtu_entry *entry) 1693 { 1694 struct dsa_switch *ds = chip->ds; 1695 struct mv88e6xxx_vtu_entry vlan = { 1696 .valid = true, 1697 .vid = vid, 1698 }; 1699 int i, err; 1700 1701 err = _mv88e6xxx_fid_new(chip, &vlan.fid); 1702 if (err) 1703 return err; 1704 1705 /* exclude all ports except the CPU and DSA ports */ 1706 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1707 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) 1708 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 1709 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1710 1711 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || 1712 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip)) { 1713 struct mv88e6xxx_vtu_entry vstp; 1714 1715 /* Adding a VTU entry requires a valid STU entry. As VSTP is not 1716 * implemented, only one STU entry is needed to cover all VTU 1717 * entries. Thus, validate the SID 0. 1718 */ 1719 vlan.sid = 0; 1720 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); 1721 if (err) 1722 return err; 1723 1724 if (vstp.sid != vlan.sid || !vstp.valid) { 1725 memset(&vstp, 0, sizeof(vstp)); 1726 vstp.valid = true; 1727 vstp.sid = vlan.sid; 1728 1729 err = _mv88e6xxx_stu_loadpurge(chip, &vstp); 1730 if (err) 1731 return err; 1732 } 1733 } 1734 1735 *entry = vlan; 1736 return 0; 1737 } 1738 1739 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1740 struct mv88e6xxx_vtu_entry *entry, bool creat) 1741 { 1742 int err; 1743 1744 if (!vid) 1745 return -EINVAL; 1746 1747 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); 1748 if (err) 1749 return err; 1750 1751 err = _mv88e6xxx_vtu_getnext(chip, entry); 1752 if (err) 1753 return err; 1754 1755 if (entry->vid != vid || !entry->valid) { 1756 if (!creat) 1757 return -EOPNOTSUPP; 1758 /* -ENOENT would've been more appropriate, but switchdev expects 1759 * -EOPNOTSUPP to inform bridge about an eventual software VLAN. 1760 */ 1761 1762 err = _mv88e6xxx_vtu_new(chip, vid, entry); 1763 } 1764 1765 return err; 1766 } 1767 1768 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1769 u16 vid_begin, u16 vid_end) 1770 { 1771 struct mv88e6xxx_chip *chip = ds->priv; 1772 struct mv88e6xxx_vtu_entry vlan; 1773 int i, err; 1774 1775 if (!vid_begin) 1776 return -EOPNOTSUPP; 1777 1778 mutex_lock(&chip->reg_lock); 1779 1780 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); 1781 if (err) 1782 goto unlock; 1783 1784 do { 1785 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1786 if (err) 1787 goto unlock; 1788 1789 if (!vlan.valid) 1790 break; 1791 1792 if (vlan.vid > vid_end) 1793 break; 1794 1795 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1796 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1797 continue; 1798 1799 if (vlan.data[i] == 1800 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1801 continue; 1802 1803 if (chip->ports[i].bridge_dev == 1804 chip->ports[port].bridge_dev) 1805 break; /* same bridge, check next VLAN */ 1806 1807 netdev_warn(ds->ports[port].netdev, 1808 "hardware VLAN %d already used by %s\n", 1809 vlan.vid, 1810 netdev_name(chip->ports[i].bridge_dev)); 1811 err = -EOPNOTSUPP; 1812 goto unlock; 1813 } 1814 } while (vlan.vid < vid_end); 1815 1816 unlock: 1817 mutex_unlock(&chip->reg_lock); 1818 1819 return err; 1820 } 1821 1822 static const char * const mv88e6xxx_port_8021q_mode_names[] = { 1823 [PORT_CONTROL_2_8021Q_DISABLED] = "Disabled", 1824 [PORT_CONTROL_2_8021Q_FALLBACK] = "Fallback", 1825 [PORT_CONTROL_2_8021Q_CHECK] = "Check", 1826 [PORT_CONTROL_2_8021Q_SECURE] = "Secure", 1827 }; 1828 1829 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1830 bool vlan_filtering) 1831 { 1832 struct mv88e6xxx_chip *chip = ds->priv; 1833 u16 old, new = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : 1834 PORT_CONTROL_2_8021Q_DISABLED; 1835 u16 reg; 1836 int err; 1837 1838 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1839 return -EOPNOTSUPP; 1840 1841 mutex_lock(&chip->reg_lock); 1842 1843 err = mv88e6xxx_port_read(chip, port, PORT_CONTROL_2, ®); 1844 if (err) 1845 goto unlock; 1846 1847 old = reg & PORT_CONTROL_2_8021Q_MASK; 1848 1849 if (new != old) { 1850 reg &= ~PORT_CONTROL_2_8021Q_MASK; 1851 reg |= new & PORT_CONTROL_2_8021Q_MASK; 1852 1853 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); 1854 if (err) 1855 goto unlock; 1856 1857 netdev_dbg(ds->ports[port].netdev, "802.1Q Mode %s (was %s)\n", 1858 mv88e6xxx_port_8021q_mode_names[new], 1859 mv88e6xxx_port_8021q_mode_names[old]); 1860 } 1861 1862 err = 0; 1863 unlock: 1864 mutex_unlock(&chip->reg_lock); 1865 1866 return err; 1867 } 1868 1869 static int 1870 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1871 const struct switchdev_obj_port_vlan *vlan, 1872 struct switchdev_trans *trans) 1873 { 1874 struct mv88e6xxx_chip *chip = ds->priv; 1875 int err; 1876 1877 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1878 return -EOPNOTSUPP; 1879 1880 /* If the requested port doesn't belong to the same bridge as the VLAN 1881 * members, do not support it (yet) and fallback to software VLAN. 1882 */ 1883 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1884 vlan->vid_end); 1885 if (err) 1886 return err; 1887 1888 /* We don't need any dynamic resource from the kernel (yet), 1889 * so skip the prepare phase. 1890 */ 1891 return 0; 1892 } 1893 1894 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1895 u16 vid, bool untagged) 1896 { 1897 struct mv88e6xxx_vtu_entry vlan; 1898 int err; 1899 1900 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1901 if (err) 1902 return err; 1903 1904 vlan.data[port] = untagged ? 1905 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : 1906 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; 1907 1908 return _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1909 } 1910 1911 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1912 const struct switchdev_obj_port_vlan *vlan, 1913 struct switchdev_trans *trans) 1914 { 1915 struct mv88e6xxx_chip *chip = ds->priv; 1916 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1917 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1918 u16 vid; 1919 1920 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1921 return; 1922 1923 mutex_lock(&chip->reg_lock); 1924 1925 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1926 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) 1927 netdev_err(ds->ports[port].netdev, 1928 "failed to add VLAN %d%c\n", 1929 vid, untagged ? 'u' : 't'); 1930 1931 if (pvid && _mv88e6xxx_port_pvid_set(chip, port, vlan->vid_end)) 1932 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", 1933 vlan->vid_end); 1934 1935 mutex_unlock(&chip->reg_lock); 1936 } 1937 1938 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1939 int port, u16 vid) 1940 { 1941 struct dsa_switch *ds = chip->ds; 1942 struct mv88e6xxx_vtu_entry vlan; 1943 int i, err; 1944 1945 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1946 if (err) 1947 return err; 1948 1949 /* Tell switchdev if this VLAN is handled in software */ 1950 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1951 return -EOPNOTSUPP; 1952 1953 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1954 1955 /* keep the VLAN unless all ports are excluded */ 1956 vlan.valid = false; 1957 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1958 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1959 continue; 1960 1961 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1962 vlan.valid = true; 1963 break; 1964 } 1965 } 1966 1967 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1968 if (err) 1969 return err; 1970 1971 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); 1972 } 1973 1974 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1975 const struct switchdev_obj_port_vlan *vlan) 1976 { 1977 struct mv88e6xxx_chip *chip = ds->priv; 1978 u16 pvid, vid; 1979 int err = 0; 1980 1981 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1982 return -EOPNOTSUPP; 1983 1984 mutex_lock(&chip->reg_lock); 1985 1986 err = _mv88e6xxx_port_pvid_get(chip, port, &pvid); 1987 if (err) 1988 goto unlock; 1989 1990 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1991 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1992 if (err) 1993 goto unlock; 1994 1995 if (vid == pvid) { 1996 err = _mv88e6xxx_port_pvid_set(chip, port, 0); 1997 if (err) 1998 goto unlock; 1999 } 2000 } 2001 2002 unlock: 2003 mutex_unlock(&chip->reg_lock); 2004 2005 return err; 2006 } 2007 2008 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, 2009 const unsigned char *addr) 2010 { 2011 int i, err; 2012 2013 for (i = 0; i < 3; i++) { 2014 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, 2015 (addr[i * 2] << 8) | addr[i * 2 + 1]); 2016 if (err) 2017 return err; 2018 } 2019 2020 return 0; 2021 } 2022 2023 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, 2024 unsigned char *addr) 2025 { 2026 u16 val; 2027 int i, err; 2028 2029 for (i = 0; i < 3; i++) { 2030 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); 2031 if (err) 2032 return err; 2033 2034 addr[i * 2] = val >> 8; 2035 addr[i * 2 + 1] = val & 0xff; 2036 } 2037 2038 return 0; 2039 } 2040 2041 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, 2042 struct mv88e6xxx_atu_entry *entry) 2043 { 2044 int ret; 2045 2046 ret = _mv88e6xxx_atu_wait(chip); 2047 if (ret < 0) 2048 return ret; 2049 2050 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); 2051 if (ret < 0) 2052 return ret; 2053 2054 ret = _mv88e6xxx_atu_data_write(chip, entry); 2055 if (ret < 0) 2056 return ret; 2057 2058 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); 2059 } 2060 2061 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2062 struct mv88e6xxx_atu_entry *entry); 2063 2064 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, 2065 const u8 *addr, struct mv88e6xxx_atu_entry *entry) 2066 { 2067 struct mv88e6xxx_atu_entry next; 2068 int err; 2069 2070 eth_broadcast_addr(next.mac); 2071 2072 err = _mv88e6xxx_atu_mac_write(chip, next.mac); 2073 if (err) 2074 return err; 2075 2076 do { 2077 err = _mv88e6xxx_atu_getnext(chip, fid, &next); 2078 if (err) 2079 return err; 2080 2081 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2082 break; 2083 2084 if (ether_addr_equal(next.mac, addr)) { 2085 *entry = next; 2086 return 0; 2087 } 2088 } while (!is_broadcast_ether_addr(next.mac)); 2089 2090 memset(entry, 0, sizeof(*entry)); 2091 entry->fid = fid; 2092 ether_addr_copy(entry->mac, addr); 2093 2094 return 0; 2095 } 2096 2097 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2098 const unsigned char *addr, u16 vid, 2099 u8 state) 2100 { 2101 struct mv88e6xxx_vtu_entry vlan; 2102 struct mv88e6xxx_atu_entry entry; 2103 int err; 2104 2105 /* Null VLAN ID corresponds to the port private database */ 2106 if (vid == 0) 2107 err = _mv88e6xxx_port_fid_get(chip, port, &vlan.fid); 2108 else 2109 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 2110 if (err) 2111 return err; 2112 2113 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); 2114 if (err) 2115 return err; 2116 2117 /* Purge the ATU entry only if no port is using it anymore */ 2118 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { 2119 entry.portv_trunkid &= ~BIT(port); 2120 if (!entry.portv_trunkid) 2121 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; 2122 } else { 2123 entry.portv_trunkid |= BIT(port); 2124 entry.state = state; 2125 } 2126 2127 return _mv88e6xxx_atu_load(chip, &entry); 2128 } 2129 2130 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 2131 const struct switchdev_obj_port_fdb *fdb, 2132 struct switchdev_trans *trans) 2133 { 2134 /* We don't need any dynamic resource from the kernel (yet), 2135 * so skip the prepare phase. 2136 */ 2137 return 0; 2138 } 2139 2140 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2141 const struct switchdev_obj_port_fdb *fdb, 2142 struct switchdev_trans *trans) 2143 { 2144 struct mv88e6xxx_chip *chip = ds->priv; 2145 2146 mutex_lock(&chip->reg_lock); 2147 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2148 GLOBAL_ATU_DATA_STATE_UC_STATIC)) 2149 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); 2150 mutex_unlock(&chip->reg_lock); 2151 } 2152 2153 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2154 const struct switchdev_obj_port_fdb *fdb) 2155 { 2156 struct mv88e6xxx_chip *chip = ds->priv; 2157 int err; 2158 2159 mutex_lock(&chip->reg_lock); 2160 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2161 GLOBAL_ATU_DATA_STATE_UNUSED); 2162 mutex_unlock(&chip->reg_lock); 2163 2164 return err; 2165 } 2166 2167 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2168 struct mv88e6xxx_atu_entry *entry) 2169 { 2170 struct mv88e6xxx_atu_entry next = { 0 }; 2171 u16 val; 2172 int err; 2173 2174 next.fid = fid; 2175 2176 err = _mv88e6xxx_atu_wait(chip); 2177 if (err) 2178 return err; 2179 2180 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); 2181 if (err) 2182 return err; 2183 2184 err = _mv88e6xxx_atu_mac_read(chip, next.mac); 2185 if (err) 2186 return err; 2187 2188 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); 2189 if (err) 2190 return err; 2191 2192 next.state = val & GLOBAL_ATU_DATA_STATE_MASK; 2193 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { 2194 unsigned int mask, shift; 2195 2196 if (val & GLOBAL_ATU_DATA_TRUNK) { 2197 next.trunk = true; 2198 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 2199 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 2200 } else { 2201 next.trunk = false; 2202 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 2203 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 2204 } 2205 2206 next.portv_trunkid = (val & mask) >> shift; 2207 } 2208 2209 *entry = next; 2210 return 0; 2211 } 2212 2213 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2214 u16 fid, u16 vid, int port, 2215 struct switchdev_obj *obj, 2216 int (*cb)(struct switchdev_obj *obj)) 2217 { 2218 struct mv88e6xxx_atu_entry addr = { 2219 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 2220 }; 2221 int err; 2222 2223 err = _mv88e6xxx_atu_mac_write(chip, addr.mac); 2224 if (err) 2225 return err; 2226 2227 do { 2228 err = _mv88e6xxx_atu_getnext(chip, fid, &addr); 2229 if (err) 2230 return err; 2231 2232 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2233 break; 2234 2235 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) 2236 continue; 2237 2238 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { 2239 struct switchdev_obj_port_fdb *fdb; 2240 2241 if (!is_unicast_ether_addr(addr.mac)) 2242 continue; 2243 2244 fdb = SWITCHDEV_OBJ_PORT_FDB(obj); 2245 fdb->vid = vid; 2246 ether_addr_copy(fdb->addr, addr.mac); 2247 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) 2248 fdb->ndm_state = NUD_NOARP; 2249 else 2250 fdb->ndm_state = NUD_REACHABLE; 2251 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { 2252 struct switchdev_obj_port_mdb *mdb; 2253 2254 if (!is_multicast_ether_addr(addr.mac)) 2255 continue; 2256 2257 mdb = SWITCHDEV_OBJ_PORT_MDB(obj); 2258 mdb->vid = vid; 2259 ether_addr_copy(mdb->addr, addr.mac); 2260 } else { 2261 return -EOPNOTSUPP; 2262 } 2263 2264 err = cb(obj); 2265 if (err) 2266 return err; 2267 } while (!is_broadcast_ether_addr(addr.mac)); 2268 2269 return err; 2270 } 2271 2272 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2273 struct switchdev_obj *obj, 2274 int (*cb)(struct switchdev_obj *obj)) 2275 { 2276 struct mv88e6xxx_vtu_entry vlan = { 2277 .vid = GLOBAL_VTU_VID_MASK, /* all ones */ 2278 }; 2279 u16 fid; 2280 int err; 2281 2282 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2283 err = _mv88e6xxx_port_fid_get(chip, port, &fid); 2284 if (err) 2285 return err; 2286 2287 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); 2288 if (err) 2289 return err; 2290 2291 /* Dump VLANs' Filtering Information Databases */ 2292 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); 2293 if (err) 2294 return err; 2295 2296 do { 2297 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 2298 if (err) 2299 return err; 2300 2301 if (!vlan.valid) 2302 break; 2303 2304 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2305 obj, cb); 2306 if (err) 2307 return err; 2308 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 2309 2310 return err; 2311 } 2312 2313 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2314 struct switchdev_obj_port_fdb *fdb, 2315 int (*cb)(struct switchdev_obj *obj)) 2316 { 2317 struct mv88e6xxx_chip *chip = ds->priv; 2318 int err; 2319 2320 mutex_lock(&chip->reg_lock); 2321 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); 2322 mutex_unlock(&chip->reg_lock); 2323 2324 return err; 2325 } 2326 2327 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2328 struct net_device *bridge) 2329 { 2330 struct mv88e6xxx_chip *chip = ds->priv; 2331 int i, err = 0; 2332 2333 mutex_lock(&chip->reg_lock); 2334 2335 /* Assign the bridge and remap each port's VLANTable */ 2336 chip->ports[port].bridge_dev = bridge; 2337 2338 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2339 if (chip->ports[i].bridge_dev == bridge) { 2340 err = _mv88e6xxx_port_based_vlan_map(chip, i); 2341 if (err) 2342 break; 2343 } 2344 } 2345 2346 mutex_unlock(&chip->reg_lock); 2347 2348 return err; 2349 } 2350 2351 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port) 2352 { 2353 struct mv88e6xxx_chip *chip = ds->priv; 2354 struct net_device *bridge = chip->ports[port].bridge_dev; 2355 int i; 2356 2357 mutex_lock(&chip->reg_lock); 2358 2359 /* Unassign the bridge and remap each port's VLANTable */ 2360 chip->ports[port].bridge_dev = NULL; 2361 2362 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2363 if (i == port || chip->ports[i].bridge_dev == bridge) 2364 if (_mv88e6xxx_port_based_vlan_map(chip, i)) 2365 netdev_warn(ds->ports[i].netdev, 2366 "failed to remap\n"); 2367 2368 mutex_unlock(&chip->reg_lock); 2369 } 2370 2371 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2372 { 2373 bool ppu_active = mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE); 2374 u16 is_reset = (ppu_active ? 0x8800 : 0xc800); 2375 struct gpio_desc *gpiod = chip->reset; 2376 unsigned long timeout; 2377 u16 reg; 2378 int err; 2379 int i; 2380 2381 /* Set all ports to the disabled state. */ 2382 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2383 err = mv88e6xxx_port_read(chip, i, PORT_CONTROL, ®); 2384 if (err) 2385 return err; 2386 2387 err = mv88e6xxx_port_write(chip, i, PORT_CONTROL, 2388 reg & 0xfffc); 2389 if (err) 2390 return err; 2391 } 2392 2393 /* Wait for transmit queues to drain. */ 2394 usleep_range(2000, 4000); 2395 2396 /* If there is a gpio connected to the reset pin, toggle it */ 2397 if (gpiod) { 2398 gpiod_set_value_cansleep(gpiod, 1); 2399 usleep_range(10000, 20000); 2400 gpiod_set_value_cansleep(gpiod, 0); 2401 usleep_range(10000, 20000); 2402 } 2403 2404 /* Reset the switch. Keep the PPU active if requested. The PPU 2405 * needs to be active to support indirect phy register access 2406 * through global registers 0x18 and 0x19. 2407 */ 2408 if (ppu_active) 2409 err = mv88e6xxx_g1_write(chip, 0x04, 0xc000); 2410 else 2411 err = mv88e6xxx_g1_write(chip, 0x04, 0xc400); 2412 if (err) 2413 return err; 2414 2415 /* Wait up to one second for reset to complete. */ 2416 timeout = jiffies + 1 * HZ; 2417 while (time_before(jiffies, timeout)) { 2418 err = mv88e6xxx_g1_read(chip, 0x00, ®); 2419 if (err) 2420 return err; 2421 2422 if ((reg & is_reset) == is_reset) 2423 break; 2424 usleep_range(1000, 2000); 2425 } 2426 if (time_after(jiffies, timeout)) 2427 err = -ETIMEDOUT; 2428 else 2429 err = 0; 2430 2431 return err; 2432 } 2433 2434 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) 2435 { 2436 u16 val; 2437 int err; 2438 2439 /* Clear Power Down bit */ 2440 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); 2441 if (err) 2442 return err; 2443 2444 if (val & BMCR_PDOWN) { 2445 val &= ~BMCR_PDOWN; 2446 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); 2447 } 2448 2449 return err; 2450 } 2451 2452 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2453 { 2454 struct dsa_switch *ds = chip->ds; 2455 int err; 2456 u16 reg; 2457 2458 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2459 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2460 mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip) || 2461 mv88e6xxx_6065_family(chip) || mv88e6xxx_6320_family(chip)) { 2462 /* MAC Forcing register: don't force link, speed, 2463 * duplex or flow control state to any particular 2464 * values on physical ports, but force the CPU port 2465 * and all DSA ports to their maximum bandwidth and 2466 * full duplex. 2467 */ 2468 err = mv88e6xxx_port_read(chip, port, PORT_PCS_CTRL, ®); 2469 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 2470 reg &= ~PORT_PCS_CTRL_UNFORCED; 2471 reg |= PORT_PCS_CTRL_FORCE_LINK | 2472 PORT_PCS_CTRL_LINK_UP | 2473 PORT_PCS_CTRL_DUPLEX_FULL | 2474 PORT_PCS_CTRL_FORCE_DUPLEX; 2475 if (mv88e6xxx_6065_family(chip)) 2476 reg |= PORT_PCS_CTRL_100; 2477 else 2478 reg |= PORT_PCS_CTRL_1000; 2479 } else { 2480 reg |= PORT_PCS_CTRL_UNFORCED; 2481 } 2482 2483 err = mv88e6xxx_port_write(chip, port, PORT_PCS_CTRL, reg); 2484 if (err) 2485 return err; 2486 } 2487 2488 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2489 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2490 * tunneling, determine priority by looking at 802.1p and IP 2491 * priority fields (IP prio has precedence), and set STP state 2492 * to Forwarding. 2493 * 2494 * If this is the CPU link, use DSA or EDSA tagging depending 2495 * on which tagging mode was configured. 2496 * 2497 * If this is a link to another switch, use DSA tagging mode. 2498 * 2499 * If this is the upstream port for this switch, enable 2500 * forwarding of unknown unicasts and multicasts. 2501 */ 2502 reg = 0; 2503 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2504 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2505 mv88e6xxx_6095_family(chip) || mv88e6xxx_6065_family(chip) || 2506 mv88e6xxx_6185_family(chip) || mv88e6xxx_6320_family(chip)) 2507 reg = PORT_CONTROL_IGMP_MLD_SNOOP | 2508 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | 2509 PORT_CONTROL_STATE_FORWARDING; 2510 if (dsa_is_cpu_port(ds, port)) { 2511 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) 2512 reg |= PORT_CONTROL_FRAME_ETHER_TYPE_DSA | 2513 PORT_CONTROL_FORWARD_UNKNOWN_MC; 2514 else 2515 reg |= PORT_CONTROL_DSA_TAG; 2516 reg |= PORT_CONTROL_EGRESS_ADD_TAG | 2517 PORT_CONTROL_FORWARD_UNKNOWN; 2518 } 2519 if (dsa_is_dsa_port(ds, port)) { 2520 if (mv88e6xxx_6095_family(chip) || 2521 mv88e6xxx_6185_family(chip)) 2522 reg |= PORT_CONTROL_DSA_TAG; 2523 if (mv88e6xxx_6352_family(chip) || 2524 mv88e6xxx_6351_family(chip) || 2525 mv88e6xxx_6165_family(chip) || 2526 mv88e6xxx_6097_family(chip) || 2527 mv88e6xxx_6320_family(chip)) { 2528 reg |= PORT_CONTROL_FRAME_MODE_DSA; 2529 } 2530 2531 if (port == dsa_upstream_port(ds)) 2532 reg |= PORT_CONTROL_FORWARD_UNKNOWN | 2533 PORT_CONTROL_FORWARD_UNKNOWN_MC; 2534 } 2535 if (reg) { 2536 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 2537 if (err) 2538 return err; 2539 } 2540 2541 /* If this port is connected to a SerDes, make sure the SerDes is not 2542 * powered down. 2543 */ 2544 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { 2545 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 2546 if (err) 2547 return err; 2548 reg &= PORT_STATUS_CMODE_MASK; 2549 if ((reg == PORT_STATUS_CMODE_100BASE_X) || 2550 (reg == PORT_STATUS_CMODE_1000BASE_X) || 2551 (reg == PORT_STATUS_CMODE_SGMII)) { 2552 err = mv88e6xxx_serdes_power_on(chip); 2553 if (err < 0) 2554 return err; 2555 } 2556 } 2557 2558 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2559 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2560 * untagged frames on this port, do a destination address lookup on all 2561 * received packets as usual, disable ARP mirroring and don't send a 2562 * copy of all transmitted/received frames on this port to the CPU. 2563 */ 2564 reg = 0; 2565 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2566 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2567 mv88e6xxx_6095_family(chip) || mv88e6xxx_6320_family(chip) || 2568 mv88e6xxx_6185_family(chip)) 2569 reg = PORT_CONTROL_2_MAP_DA; 2570 2571 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2572 mv88e6xxx_6165_family(chip) || mv88e6xxx_6320_family(chip)) 2573 reg |= PORT_CONTROL_2_JUMBO_10240; 2574 2575 if (mv88e6xxx_6095_family(chip) || mv88e6xxx_6185_family(chip)) { 2576 /* Set the upstream port this port should use */ 2577 reg |= dsa_upstream_port(ds); 2578 /* enable forwarding of unknown multicast addresses to 2579 * the upstream port 2580 */ 2581 if (port == dsa_upstream_port(ds)) 2582 reg |= PORT_CONTROL_2_FORWARD_UNKNOWN; 2583 } 2584 2585 reg |= PORT_CONTROL_2_8021Q_DISABLED; 2586 2587 if (reg) { 2588 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_2, reg); 2589 if (err) 2590 return err; 2591 } 2592 2593 /* Port Association Vector: when learning source addresses 2594 * of packets, add the address to the address database using 2595 * a port bitmap that has only the bit for this port set and 2596 * the other bits clear. 2597 */ 2598 reg = 1 << port; 2599 /* Disable learning for CPU port */ 2600 if (dsa_is_cpu_port(ds, port)) 2601 reg = 0; 2602 2603 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); 2604 if (err) 2605 return err; 2606 2607 /* Egress rate control 2: disable egress rate control. */ 2608 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); 2609 if (err) 2610 return err; 2611 2612 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2613 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2614 mv88e6xxx_6320_family(chip)) { 2615 /* Do not limit the period of time that this port can 2616 * be paused for by the remote end or the period of 2617 * time that this port can pause the remote end. 2618 */ 2619 err = mv88e6xxx_port_write(chip, port, PORT_PAUSE_CTRL, 0x0000); 2620 if (err) 2621 return err; 2622 2623 /* Port ATU control: disable limiting the number of 2624 * address database entries that this port is allowed 2625 * to use. 2626 */ 2627 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 2628 0x0000); 2629 /* Priority Override: disable DA, SA and VTU priority 2630 * override. 2631 */ 2632 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 2633 0x0000); 2634 if (err) 2635 return err; 2636 2637 /* Port Ethertype: use the Ethertype DSA Ethertype 2638 * value. 2639 */ 2640 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) { 2641 err = mv88e6xxx_port_write(chip, port, PORT_ETH_TYPE, 2642 ETH_P_EDSA); 2643 if (err) 2644 return err; 2645 } 2646 2647 /* Tag Remap: use an identity 802.1p prio -> switch 2648 * prio mapping. 2649 */ 2650 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_0123, 2651 0x3210); 2652 if (err) 2653 return err; 2654 2655 /* Tag Remap 2: use an identity 802.1p prio -> switch 2656 * prio mapping. 2657 */ 2658 err = mv88e6xxx_port_write(chip, port, PORT_TAG_REGMAP_4567, 2659 0x7654); 2660 if (err) 2661 return err; 2662 } 2663 2664 /* Rate Control: disable ingress rate limiting. */ 2665 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2666 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2667 mv88e6xxx_6320_family(chip)) { 2668 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 2669 0x0001); 2670 if (err) 2671 return err; 2672 } else if (mv88e6xxx_6185_family(chip) || mv88e6xxx_6095_family(chip)) { 2673 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL, 2674 0x0000); 2675 if (err) 2676 return err; 2677 } 2678 2679 /* Port Control 1: disable trunking, disable sending 2680 * learning messages to this port. 2681 */ 2682 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); 2683 if (err) 2684 return err; 2685 2686 /* Port based VLAN map: give each port the same default address 2687 * database, and allow bidirectional communication between the 2688 * CPU and DSA port(s), and the other ports. 2689 */ 2690 err = _mv88e6xxx_port_fid_set(chip, port, 0); 2691 if (err) 2692 return err; 2693 2694 err = _mv88e6xxx_port_based_vlan_map(chip, port); 2695 if (err) 2696 return err; 2697 2698 /* Default VLAN ID and priority: don't set a default VLAN 2699 * ID, and set the default packet priority to zero. 2700 */ 2701 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); 2702 } 2703 2704 int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 2705 { 2706 int err; 2707 2708 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); 2709 if (err) 2710 return err; 2711 2712 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); 2713 if (err) 2714 return err; 2715 2716 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); 2717 if (err) 2718 return err; 2719 2720 return 0; 2721 } 2722 2723 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, 2724 unsigned int msecs) 2725 { 2726 const unsigned int coeff = chip->info->age_time_coeff; 2727 const unsigned int min = 0x01 * coeff; 2728 const unsigned int max = 0xff * coeff; 2729 u8 age_time; 2730 u16 val; 2731 int err; 2732 2733 if (msecs < min || msecs > max) 2734 return -ERANGE; 2735 2736 /* Round to nearest multiple of coeff */ 2737 age_time = (msecs + coeff / 2) / coeff; 2738 2739 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 2740 if (err) 2741 return err; 2742 2743 /* AgeTime is 11:4 bits */ 2744 val &= ~0xff0; 2745 val |= age_time << 4; 2746 2747 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); 2748 } 2749 2750 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2751 unsigned int ageing_time) 2752 { 2753 struct mv88e6xxx_chip *chip = ds->priv; 2754 int err; 2755 2756 mutex_lock(&chip->reg_lock); 2757 err = mv88e6xxx_g1_set_age_time(chip, ageing_time); 2758 mutex_unlock(&chip->reg_lock); 2759 2760 return err; 2761 } 2762 2763 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2764 { 2765 struct dsa_switch *ds = chip->ds; 2766 u32 upstream_port = dsa_upstream_port(ds); 2767 u16 reg; 2768 int err; 2769 2770 /* Enable the PHY Polling Unit if present, don't discard any packets, 2771 * and mask all interrupt sources. 2772 */ 2773 reg = 0; 2774 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU) || 2775 mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU_ACTIVE)) 2776 reg |= GLOBAL_CONTROL_PPU_ENABLE; 2777 2778 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); 2779 if (err) 2780 return err; 2781 2782 /* Configure the upstream port, and configure it as the port to which 2783 * ingress and egress and ARP monitor frames are to be sent. 2784 */ 2785 reg = upstream_port << GLOBAL_MONITOR_CONTROL_INGRESS_SHIFT | 2786 upstream_port << GLOBAL_MONITOR_CONTROL_EGRESS_SHIFT | 2787 upstream_port << GLOBAL_MONITOR_CONTROL_ARP_SHIFT; 2788 err = mv88e6xxx_g1_write(chip, GLOBAL_MONITOR_CONTROL, reg); 2789 if (err) 2790 return err; 2791 2792 /* Disable remote management, and set the switch's DSA device number. */ 2793 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, 2794 GLOBAL_CONTROL_2_MULTIPLE_CASCADE | 2795 (ds->index & 0x1f)); 2796 if (err) 2797 return err; 2798 2799 /* Clear all the VTU and STU entries */ 2800 err = _mv88e6xxx_vtu_stu_flush(chip); 2801 if (err < 0) 2802 return err; 2803 2804 /* Set the default address aging time to 5 minutes, and 2805 * enable address learn messages to be sent to all message 2806 * ports. 2807 */ 2808 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 2809 GLOBAL_ATU_CONTROL_LEARN2ALL); 2810 if (err) 2811 return err; 2812 2813 err = mv88e6xxx_g1_set_age_time(chip, 300000); 2814 if (err) 2815 return err; 2816 2817 /* Clear all ATU entries */ 2818 err = _mv88e6xxx_atu_flush(chip, 0, true); 2819 if (err) 2820 return err; 2821 2822 /* Configure the IP ToS mapping registers. */ 2823 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); 2824 if (err) 2825 return err; 2826 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); 2827 if (err) 2828 return err; 2829 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); 2830 if (err) 2831 return err; 2832 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); 2833 if (err) 2834 return err; 2835 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); 2836 if (err) 2837 return err; 2838 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); 2839 if (err) 2840 return err; 2841 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); 2842 if (err) 2843 return err; 2844 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); 2845 if (err) 2846 return err; 2847 2848 /* Configure the IEEE 802.1p priority mapping register. */ 2849 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); 2850 if (err) 2851 return err; 2852 2853 /* Clear the statistics counters for all ports */ 2854 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 2855 GLOBAL_STATS_OP_FLUSH_ALL); 2856 if (err) 2857 return err; 2858 2859 /* Wait for the flush to complete. */ 2860 err = _mv88e6xxx_stats_wait(chip); 2861 if (err) 2862 return err; 2863 2864 return 0; 2865 } 2866 2867 static int mv88e6xxx_setup(struct dsa_switch *ds) 2868 { 2869 struct mv88e6xxx_chip *chip = ds->priv; 2870 int err; 2871 int i; 2872 2873 chip->ds = ds; 2874 ds->slave_mii_bus = chip->mdio_bus; 2875 2876 mutex_lock(&chip->reg_lock); 2877 2878 err = mv88e6xxx_switch_reset(chip); 2879 if (err) 2880 goto unlock; 2881 2882 /* Setup Switch Port Registers */ 2883 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2884 err = mv88e6xxx_setup_port(chip, i); 2885 if (err) 2886 goto unlock; 2887 } 2888 2889 /* Setup Switch Global 1 Registers */ 2890 err = mv88e6xxx_g1_setup(chip); 2891 if (err) 2892 goto unlock; 2893 2894 /* Setup Switch Global 2 Registers */ 2895 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 2896 err = mv88e6xxx_g2_setup(chip); 2897 if (err) 2898 goto unlock; 2899 } 2900 2901 unlock: 2902 mutex_unlock(&chip->reg_lock); 2903 2904 return err; 2905 } 2906 2907 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2908 { 2909 struct mv88e6xxx_chip *chip = ds->priv; 2910 int err; 2911 2912 if (!chip->info->ops->set_switch_mac) 2913 return -EOPNOTSUPP; 2914 2915 mutex_lock(&chip->reg_lock); 2916 err = chip->info->ops->set_switch_mac(chip, addr); 2917 mutex_unlock(&chip->reg_lock); 2918 2919 return err; 2920 } 2921 2922 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2923 { 2924 struct mv88e6xxx_chip *chip = bus->priv; 2925 u16 val; 2926 int err; 2927 2928 if (phy >= mv88e6xxx_num_ports(chip)) 2929 return 0xffff; 2930 2931 mutex_lock(&chip->reg_lock); 2932 err = mv88e6xxx_phy_read(chip, phy, reg, &val); 2933 mutex_unlock(&chip->reg_lock); 2934 2935 return err ? err : val; 2936 } 2937 2938 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2939 { 2940 struct mv88e6xxx_chip *chip = bus->priv; 2941 int err; 2942 2943 if (phy >= mv88e6xxx_num_ports(chip)) 2944 return 0xffff; 2945 2946 mutex_lock(&chip->reg_lock); 2947 err = mv88e6xxx_phy_write(chip, phy, reg, val); 2948 mutex_unlock(&chip->reg_lock); 2949 2950 return err; 2951 } 2952 2953 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2954 struct device_node *np) 2955 { 2956 static int index; 2957 struct mii_bus *bus; 2958 int err; 2959 2960 if (np) 2961 chip->mdio_np = of_get_child_by_name(np, "mdio"); 2962 2963 bus = devm_mdiobus_alloc(chip->dev); 2964 if (!bus) 2965 return -ENOMEM; 2966 2967 bus->priv = (void *)chip; 2968 if (np) { 2969 bus->name = np->full_name; 2970 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 2971 } else { 2972 bus->name = "mv88e6xxx SMI"; 2973 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2974 } 2975 2976 bus->read = mv88e6xxx_mdio_read; 2977 bus->write = mv88e6xxx_mdio_write; 2978 bus->parent = chip->dev; 2979 2980 if (chip->mdio_np) 2981 err = of_mdiobus_register(bus, chip->mdio_np); 2982 else 2983 err = mdiobus_register(bus); 2984 if (err) { 2985 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2986 goto out; 2987 } 2988 chip->mdio_bus = bus; 2989 2990 return 0; 2991 2992 out: 2993 if (chip->mdio_np) 2994 of_node_put(chip->mdio_np); 2995 2996 return err; 2997 } 2998 2999 static void mv88e6xxx_mdio_unregister(struct mv88e6xxx_chip *chip) 3000 3001 { 3002 struct mii_bus *bus = chip->mdio_bus; 3003 3004 mdiobus_unregister(bus); 3005 3006 if (chip->mdio_np) 3007 of_node_put(chip->mdio_np); 3008 } 3009 3010 #ifdef CONFIG_NET_DSA_HWMON 3011 3012 static int mv88e61xx_get_temp(struct dsa_switch *ds, int *temp) 3013 { 3014 struct mv88e6xxx_chip *chip = ds->priv; 3015 u16 val; 3016 int ret; 3017 3018 *temp = 0; 3019 3020 mutex_lock(&chip->reg_lock); 3021 3022 ret = mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x6); 3023 if (ret < 0) 3024 goto error; 3025 3026 /* Enable temperature sensor */ 3027 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 3028 if (ret < 0) 3029 goto error; 3030 3031 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val | (1 << 5)); 3032 if (ret < 0) 3033 goto error; 3034 3035 /* Wait for temperature to stabilize */ 3036 usleep_range(10000, 12000); 3037 3038 ret = mv88e6xxx_phy_read(chip, 0x0, 0x1a, &val); 3039 if (ret < 0) 3040 goto error; 3041 3042 /* Disable temperature sensor */ 3043 ret = mv88e6xxx_phy_write(chip, 0x0, 0x1a, val & ~(1 << 5)); 3044 if (ret < 0) 3045 goto error; 3046 3047 *temp = ((val & 0x1f) - 5) * 5; 3048 3049 error: 3050 mv88e6xxx_phy_write(chip, 0x0, 0x16, 0x0); 3051 mutex_unlock(&chip->reg_lock); 3052 return ret; 3053 } 3054 3055 static int mv88e63xx_get_temp(struct dsa_switch *ds, int *temp) 3056 { 3057 struct mv88e6xxx_chip *chip = ds->priv; 3058 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3059 u16 val; 3060 int ret; 3061 3062 *temp = 0; 3063 3064 mutex_lock(&chip->reg_lock); 3065 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 27, &val); 3066 mutex_unlock(&chip->reg_lock); 3067 if (ret < 0) 3068 return ret; 3069 3070 *temp = (val & 0xff) - 25; 3071 3072 return 0; 3073 } 3074 3075 static int mv88e6xxx_get_temp(struct dsa_switch *ds, int *temp) 3076 { 3077 struct mv88e6xxx_chip *chip = ds->priv; 3078 3079 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP)) 3080 return -EOPNOTSUPP; 3081 3082 if (mv88e6xxx_6320_family(chip) || mv88e6xxx_6352_family(chip)) 3083 return mv88e63xx_get_temp(ds, temp); 3084 3085 return mv88e61xx_get_temp(ds, temp); 3086 } 3087 3088 static int mv88e6xxx_get_temp_limit(struct dsa_switch *ds, int *temp) 3089 { 3090 struct mv88e6xxx_chip *chip = ds->priv; 3091 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3092 u16 val; 3093 int ret; 3094 3095 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3096 return -EOPNOTSUPP; 3097 3098 *temp = 0; 3099 3100 mutex_lock(&chip->reg_lock); 3101 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3102 mutex_unlock(&chip->reg_lock); 3103 if (ret < 0) 3104 return ret; 3105 3106 *temp = (((val >> 8) & 0x1f) * 5) - 25; 3107 3108 return 0; 3109 } 3110 3111 static int mv88e6xxx_set_temp_limit(struct dsa_switch *ds, int temp) 3112 { 3113 struct mv88e6xxx_chip *chip = ds->priv; 3114 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3115 u16 val; 3116 int err; 3117 3118 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3119 return -EOPNOTSUPP; 3120 3121 mutex_lock(&chip->reg_lock); 3122 err = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3123 if (err) 3124 goto unlock; 3125 temp = clamp_val(DIV_ROUND_CLOSEST(temp, 5) + 5, 0, 0x1f); 3126 err = mv88e6xxx_phy_page_write(chip, phy, 6, 26, 3127 (val & 0xe0ff) | (temp << 8)); 3128 unlock: 3129 mutex_unlock(&chip->reg_lock); 3130 3131 return err; 3132 } 3133 3134 static int mv88e6xxx_get_temp_alarm(struct dsa_switch *ds, bool *alarm) 3135 { 3136 struct mv88e6xxx_chip *chip = ds->priv; 3137 int phy = mv88e6xxx_6320_family(chip) ? 3 : 0; 3138 u16 val; 3139 int ret; 3140 3141 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_TEMP_LIMIT)) 3142 return -EOPNOTSUPP; 3143 3144 *alarm = false; 3145 3146 mutex_lock(&chip->reg_lock); 3147 ret = mv88e6xxx_phy_page_read(chip, phy, 6, 26, &val); 3148 mutex_unlock(&chip->reg_lock); 3149 if (ret < 0) 3150 return ret; 3151 3152 *alarm = !!(val & 0x40); 3153 3154 return 0; 3155 } 3156 #endif /* CONFIG_NET_DSA_HWMON */ 3157 3158 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3159 { 3160 struct mv88e6xxx_chip *chip = ds->priv; 3161 3162 return chip->eeprom_len; 3163 } 3164 3165 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3166 struct ethtool_eeprom *eeprom, u8 *data) 3167 { 3168 struct mv88e6xxx_chip *chip = ds->priv; 3169 int err; 3170 3171 if (!chip->info->ops->get_eeprom) 3172 return -EOPNOTSUPP; 3173 3174 mutex_lock(&chip->reg_lock); 3175 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3176 mutex_unlock(&chip->reg_lock); 3177 3178 if (err) 3179 return err; 3180 3181 eeprom->magic = 0xc3ec4951; 3182 3183 return 0; 3184 } 3185 3186 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3187 struct ethtool_eeprom *eeprom, u8 *data) 3188 { 3189 struct mv88e6xxx_chip *chip = ds->priv; 3190 int err; 3191 3192 if (!chip->info->ops->set_eeprom) 3193 return -EOPNOTSUPP; 3194 3195 if (eeprom->magic != 0xc3ec4951) 3196 return -EINVAL; 3197 3198 mutex_lock(&chip->reg_lock); 3199 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3200 mutex_unlock(&chip->reg_lock); 3201 3202 return err; 3203 } 3204 3205 static const struct mv88e6xxx_ops mv88e6085_ops = { 3206 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3207 .phy_read = mv88e6xxx_phy_ppu_read, 3208 .phy_write = mv88e6xxx_phy_ppu_write, 3209 }; 3210 3211 static const struct mv88e6xxx_ops mv88e6095_ops = { 3212 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3213 .phy_read = mv88e6xxx_phy_ppu_read, 3214 .phy_write = mv88e6xxx_phy_ppu_write, 3215 }; 3216 3217 static const struct mv88e6xxx_ops mv88e6123_ops = { 3218 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3219 .phy_read = mv88e6xxx_read, 3220 .phy_write = mv88e6xxx_write, 3221 }; 3222 3223 static const struct mv88e6xxx_ops mv88e6131_ops = { 3224 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3225 .phy_read = mv88e6xxx_phy_ppu_read, 3226 .phy_write = mv88e6xxx_phy_ppu_write, 3227 }; 3228 3229 static const struct mv88e6xxx_ops mv88e6161_ops = { 3230 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3231 .phy_read = mv88e6xxx_read, 3232 .phy_write = mv88e6xxx_write, 3233 }; 3234 3235 static const struct mv88e6xxx_ops mv88e6165_ops = { 3236 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3237 .phy_read = mv88e6xxx_read, 3238 .phy_write = mv88e6xxx_write, 3239 }; 3240 3241 static const struct mv88e6xxx_ops mv88e6171_ops = { 3242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3243 .phy_read = mv88e6xxx_g2_smi_phy_read, 3244 .phy_write = mv88e6xxx_g2_smi_phy_write, 3245 }; 3246 3247 static const struct mv88e6xxx_ops mv88e6172_ops = { 3248 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3249 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3250 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3251 .phy_read = mv88e6xxx_g2_smi_phy_read, 3252 .phy_write = mv88e6xxx_g2_smi_phy_write, 3253 }; 3254 3255 static const struct mv88e6xxx_ops mv88e6175_ops = { 3256 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3257 .phy_read = mv88e6xxx_g2_smi_phy_read, 3258 .phy_write = mv88e6xxx_g2_smi_phy_write, 3259 }; 3260 3261 static const struct mv88e6xxx_ops mv88e6176_ops = { 3262 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3263 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3265 .phy_read = mv88e6xxx_g2_smi_phy_read, 3266 .phy_write = mv88e6xxx_g2_smi_phy_write, 3267 }; 3268 3269 static const struct mv88e6xxx_ops mv88e6185_ops = { 3270 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3271 .phy_read = mv88e6xxx_phy_ppu_read, 3272 .phy_write = mv88e6xxx_phy_ppu_write, 3273 }; 3274 3275 static const struct mv88e6xxx_ops mv88e6240_ops = { 3276 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3277 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3278 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3279 .phy_read = mv88e6xxx_g2_smi_phy_read, 3280 .phy_write = mv88e6xxx_g2_smi_phy_write, 3281 }; 3282 3283 static const struct mv88e6xxx_ops mv88e6320_ops = { 3284 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3285 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3286 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3287 .phy_read = mv88e6xxx_g2_smi_phy_read, 3288 .phy_write = mv88e6xxx_g2_smi_phy_write, 3289 }; 3290 3291 static const struct mv88e6xxx_ops mv88e6321_ops = { 3292 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3293 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3295 .phy_read = mv88e6xxx_g2_smi_phy_read, 3296 .phy_write = mv88e6xxx_g2_smi_phy_write, 3297 }; 3298 3299 static const struct mv88e6xxx_ops mv88e6350_ops = { 3300 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3301 .phy_read = mv88e6xxx_g2_smi_phy_read, 3302 .phy_write = mv88e6xxx_g2_smi_phy_write, 3303 }; 3304 3305 static const struct mv88e6xxx_ops mv88e6351_ops = { 3306 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3307 .phy_read = mv88e6xxx_g2_smi_phy_read, 3308 .phy_write = mv88e6xxx_g2_smi_phy_write, 3309 }; 3310 3311 static const struct mv88e6xxx_ops mv88e6352_ops = { 3312 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3313 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3314 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3315 .phy_read = mv88e6xxx_g2_smi_phy_read, 3316 .phy_write = mv88e6xxx_g2_smi_phy_write, 3317 }; 3318 3319 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3320 [MV88E6085] = { 3321 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, 3322 .family = MV88E6XXX_FAMILY_6097, 3323 .name = "Marvell 88E6085", 3324 .num_databases = 4096, 3325 .num_ports = 10, 3326 .port_base_addr = 0x10, 3327 .global1_addr = 0x1b, 3328 .age_time_coeff = 15000, 3329 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3330 .ops = &mv88e6085_ops, 3331 }, 3332 3333 [MV88E6095] = { 3334 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, 3335 .family = MV88E6XXX_FAMILY_6095, 3336 .name = "Marvell 88E6095/88E6095F", 3337 .num_databases = 256, 3338 .num_ports = 11, 3339 .port_base_addr = 0x10, 3340 .global1_addr = 0x1b, 3341 .age_time_coeff = 15000, 3342 .flags = MV88E6XXX_FLAGS_FAMILY_6095, 3343 .ops = &mv88e6095_ops, 3344 }, 3345 3346 [MV88E6123] = { 3347 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, 3348 .family = MV88E6XXX_FAMILY_6165, 3349 .name = "Marvell 88E6123", 3350 .num_databases = 4096, 3351 .num_ports = 3, 3352 .port_base_addr = 0x10, 3353 .global1_addr = 0x1b, 3354 .age_time_coeff = 15000, 3355 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3356 .ops = &mv88e6123_ops, 3357 }, 3358 3359 [MV88E6131] = { 3360 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, 3361 .family = MV88E6XXX_FAMILY_6185, 3362 .name = "Marvell 88E6131", 3363 .num_databases = 256, 3364 .num_ports = 8, 3365 .port_base_addr = 0x10, 3366 .global1_addr = 0x1b, 3367 .age_time_coeff = 15000, 3368 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3369 .ops = &mv88e6131_ops, 3370 }, 3371 3372 [MV88E6161] = { 3373 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, 3374 .family = MV88E6XXX_FAMILY_6165, 3375 .name = "Marvell 88E6161", 3376 .num_databases = 4096, 3377 .num_ports = 6, 3378 .port_base_addr = 0x10, 3379 .global1_addr = 0x1b, 3380 .age_time_coeff = 15000, 3381 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3382 .ops = &mv88e6161_ops, 3383 }, 3384 3385 [MV88E6165] = { 3386 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, 3387 .family = MV88E6XXX_FAMILY_6165, 3388 .name = "Marvell 88E6165", 3389 .num_databases = 4096, 3390 .num_ports = 6, 3391 .port_base_addr = 0x10, 3392 .global1_addr = 0x1b, 3393 .age_time_coeff = 15000, 3394 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3395 .ops = &mv88e6165_ops, 3396 }, 3397 3398 [MV88E6171] = { 3399 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, 3400 .family = MV88E6XXX_FAMILY_6351, 3401 .name = "Marvell 88E6171", 3402 .num_databases = 4096, 3403 .num_ports = 7, 3404 .port_base_addr = 0x10, 3405 .global1_addr = 0x1b, 3406 .age_time_coeff = 15000, 3407 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3408 .ops = &mv88e6171_ops, 3409 }, 3410 3411 [MV88E6172] = { 3412 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, 3413 .family = MV88E6XXX_FAMILY_6352, 3414 .name = "Marvell 88E6172", 3415 .num_databases = 4096, 3416 .num_ports = 7, 3417 .port_base_addr = 0x10, 3418 .global1_addr = 0x1b, 3419 .age_time_coeff = 15000, 3420 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3421 .ops = &mv88e6172_ops, 3422 }, 3423 3424 [MV88E6175] = { 3425 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, 3426 .family = MV88E6XXX_FAMILY_6351, 3427 .name = "Marvell 88E6175", 3428 .num_databases = 4096, 3429 .num_ports = 7, 3430 .port_base_addr = 0x10, 3431 .global1_addr = 0x1b, 3432 .age_time_coeff = 15000, 3433 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3434 .ops = &mv88e6175_ops, 3435 }, 3436 3437 [MV88E6176] = { 3438 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, 3439 .family = MV88E6XXX_FAMILY_6352, 3440 .name = "Marvell 88E6176", 3441 .num_databases = 4096, 3442 .num_ports = 7, 3443 .port_base_addr = 0x10, 3444 .global1_addr = 0x1b, 3445 .age_time_coeff = 15000, 3446 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3447 .ops = &mv88e6176_ops, 3448 }, 3449 3450 [MV88E6185] = { 3451 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, 3452 .family = MV88E6XXX_FAMILY_6185, 3453 .name = "Marvell 88E6185", 3454 .num_databases = 256, 3455 .num_ports = 10, 3456 .port_base_addr = 0x10, 3457 .global1_addr = 0x1b, 3458 .age_time_coeff = 15000, 3459 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3460 .ops = &mv88e6185_ops, 3461 }, 3462 3463 [MV88E6240] = { 3464 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, 3465 .family = MV88E6XXX_FAMILY_6352, 3466 .name = "Marvell 88E6240", 3467 .num_databases = 4096, 3468 .num_ports = 7, 3469 .port_base_addr = 0x10, 3470 .global1_addr = 0x1b, 3471 .age_time_coeff = 15000, 3472 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3473 .ops = &mv88e6240_ops, 3474 }, 3475 3476 [MV88E6320] = { 3477 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, 3478 .family = MV88E6XXX_FAMILY_6320, 3479 .name = "Marvell 88E6320", 3480 .num_databases = 4096, 3481 .num_ports = 7, 3482 .port_base_addr = 0x10, 3483 .global1_addr = 0x1b, 3484 .age_time_coeff = 15000, 3485 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 3486 .ops = &mv88e6320_ops, 3487 }, 3488 3489 [MV88E6321] = { 3490 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, 3491 .family = MV88E6XXX_FAMILY_6320, 3492 .name = "Marvell 88E6321", 3493 .num_databases = 4096, 3494 .num_ports = 7, 3495 .port_base_addr = 0x10, 3496 .global1_addr = 0x1b, 3497 .age_time_coeff = 15000, 3498 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 3499 .ops = &mv88e6321_ops, 3500 }, 3501 3502 [MV88E6350] = { 3503 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, 3504 .family = MV88E6XXX_FAMILY_6351, 3505 .name = "Marvell 88E6350", 3506 .num_databases = 4096, 3507 .num_ports = 7, 3508 .port_base_addr = 0x10, 3509 .global1_addr = 0x1b, 3510 .age_time_coeff = 15000, 3511 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3512 .ops = &mv88e6350_ops, 3513 }, 3514 3515 [MV88E6351] = { 3516 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, 3517 .family = MV88E6XXX_FAMILY_6351, 3518 .name = "Marvell 88E6351", 3519 .num_databases = 4096, 3520 .num_ports = 7, 3521 .port_base_addr = 0x10, 3522 .global1_addr = 0x1b, 3523 .age_time_coeff = 15000, 3524 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3525 .ops = &mv88e6351_ops, 3526 }, 3527 3528 [MV88E6352] = { 3529 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, 3530 .family = MV88E6XXX_FAMILY_6352, 3531 .name = "Marvell 88E6352", 3532 .num_databases = 4096, 3533 .num_ports = 7, 3534 .port_base_addr = 0x10, 3535 .global1_addr = 0x1b, 3536 .age_time_coeff = 15000, 3537 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3538 .ops = &mv88e6352_ops, 3539 }, 3540 }; 3541 3542 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3543 { 3544 int i; 3545 3546 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3547 if (mv88e6xxx_table[i].prod_num == prod_num) 3548 return &mv88e6xxx_table[i]; 3549 3550 return NULL; 3551 } 3552 3553 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3554 { 3555 const struct mv88e6xxx_info *info; 3556 unsigned int prod_num, rev; 3557 u16 id; 3558 int err; 3559 3560 mutex_lock(&chip->reg_lock); 3561 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); 3562 mutex_unlock(&chip->reg_lock); 3563 if (err) 3564 return err; 3565 3566 prod_num = (id & 0xfff0) >> 4; 3567 rev = id & 0x000f; 3568 3569 info = mv88e6xxx_lookup_info(prod_num); 3570 if (!info) 3571 return -ENODEV; 3572 3573 /* Update the compatible info with the probed one */ 3574 chip->info = info; 3575 3576 err = mv88e6xxx_g2_require(chip); 3577 if (err) 3578 return err; 3579 3580 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3581 chip->info->prod_num, chip->info->name, rev); 3582 3583 return 0; 3584 } 3585 3586 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3587 { 3588 struct mv88e6xxx_chip *chip; 3589 3590 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3591 if (!chip) 3592 return NULL; 3593 3594 chip->dev = dev; 3595 3596 mutex_init(&chip->reg_lock); 3597 3598 return chip; 3599 } 3600 3601 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) 3602 { 3603 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) 3604 mv88e6xxx_ppu_state_init(chip); 3605 } 3606 3607 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) 3608 { 3609 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_PPU)) 3610 mv88e6xxx_ppu_state_destroy(chip); 3611 } 3612 3613 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3614 struct mii_bus *bus, int sw_addr) 3615 { 3616 /* ADDR[0] pin is unavailable externally and considered zero */ 3617 if (sw_addr & 0x1) 3618 return -EINVAL; 3619 3620 if (sw_addr == 0) 3621 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3622 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) 3623 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3624 else 3625 return -EINVAL; 3626 3627 chip->bus = bus; 3628 chip->sw_addr = sw_addr; 3629 3630 return 0; 3631 } 3632 3633 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 3634 { 3635 struct mv88e6xxx_chip *chip = ds->priv; 3636 3637 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_EDSA)) 3638 return DSA_TAG_PROTO_EDSA; 3639 3640 return DSA_TAG_PROTO_DSA; 3641 } 3642 3643 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3644 struct device *host_dev, int sw_addr, 3645 void **priv) 3646 { 3647 struct mv88e6xxx_chip *chip; 3648 struct mii_bus *bus; 3649 int err; 3650 3651 bus = dsa_host_dev_to_mii_bus(host_dev); 3652 if (!bus) 3653 return NULL; 3654 3655 chip = mv88e6xxx_alloc_chip(dsa_dev); 3656 if (!chip) 3657 return NULL; 3658 3659 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3660 chip->info = &mv88e6xxx_table[MV88E6085]; 3661 3662 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3663 if (err) 3664 goto free; 3665 3666 err = mv88e6xxx_detect(chip); 3667 if (err) 3668 goto free; 3669 3670 mv88e6xxx_phy_init(chip); 3671 3672 err = mv88e6xxx_mdio_register(chip, NULL); 3673 if (err) 3674 goto free; 3675 3676 *priv = chip; 3677 3678 return chip->info->name; 3679 free: 3680 devm_kfree(dsa_dev, chip); 3681 3682 return NULL; 3683 } 3684 3685 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3686 const struct switchdev_obj_port_mdb *mdb, 3687 struct switchdev_trans *trans) 3688 { 3689 /* We don't need any dynamic resource from the kernel (yet), 3690 * so skip the prepare phase. 3691 */ 3692 3693 return 0; 3694 } 3695 3696 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3697 const struct switchdev_obj_port_mdb *mdb, 3698 struct switchdev_trans *trans) 3699 { 3700 struct mv88e6xxx_chip *chip = ds->priv; 3701 3702 mutex_lock(&chip->reg_lock); 3703 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3704 GLOBAL_ATU_DATA_STATE_MC_STATIC)) 3705 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); 3706 mutex_unlock(&chip->reg_lock); 3707 } 3708 3709 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3710 const struct switchdev_obj_port_mdb *mdb) 3711 { 3712 struct mv88e6xxx_chip *chip = ds->priv; 3713 int err; 3714 3715 mutex_lock(&chip->reg_lock); 3716 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3717 GLOBAL_ATU_DATA_STATE_UNUSED); 3718 mutex_unlock(&chip->reg_lock); 3719 3720 return err; 3721 } 3722 3723 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, 3724 struct switchdev_obj_port_mdb *mdb, 3725 int (*cb)(struct switchdev_obj *obj)) 3726 { 3727 struct mv88e6xxx_chip *chip = ds->priv; 3728 int err; 3729 3730 mutex_lock(&chip->reg_lock); 3731 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); 3732 mutex_unlock(&chip->reg_lock); 3733 3734 return err; 3735 } 3736 3737 static struct dsa_switch_ops mv88e6xxx_switch_ops = { 3738 .probe = mv88e6xxx_drv_probe, 3739 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3740 .setup = mv88e6xxx_setup, 3741 .set_addr = mv88e6xxx_set_addr, 3742 .adjust_link = mv88e6xxx_adjust_link, 3743 .get_strings = mv88e6xxx_get_strings, 3744 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3745 .get_sset_count = mv88e6xxx_get_sset_count, 3746 .set_eee = mv88e6xxx_set_eee, 3747 .get_eee = mv88e6xxx_get_eee, 3748 #ifdef CONFIG_NET_DSA_HWMON 3749 .get_temp = mv88e6xxx_get_temp, 3750 .get_temp_limit = mv88e6xxx_get_temp_limit, 3751 .set_temp_limit = mv88e6xxx_set_temp_limit, 3752 .get_temp_alarm = mv88e6xxx_get_temp_alarm, 3753 #endif 3754 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3755 .get_eeprom = mv88e6xxx_get_eeprom, 3756 .set_eeprom = mv88e6xxx_set_eeprom, 3757 .get_regs_len = mv88e6xxx_get_regs_len, 3758 .get_regs = mv88e6xxx_get_regs, 3759 .set_ageing_time = mv88e6xxx_set_ageing_time, 3760 .port_bridge_join = mv88e6xxx_port_bridge_join, 3761 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3762 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3763 .port_fast_age = mv88e6xxx_port_fast_age, 3764 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3765 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3766 .port_vlan_add = mv88e6xxx_port_vlan_add, 3767 .port_vlan_del = mv88e6xxx_port_vlan_del, 3768 .port_vlan_dump = mv88e6xxx_port_vlan_dump, 3769 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, 3770 .port_fdb_add = mv88e6xxx_port_fdb_add, 3771 .port_fdb_del = mv88e6xxx_port_fdb_del, 3772 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3773 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3774 .port_mdb_add = mv88e6xxx_port_mdb_add, 3775 .port_mdb_del = mv88e6xxx_port_mdb_del, 3776 .port_mdb_dump = mv88e6xxx_port_mdb_dump, 3777 }; 3778 3779 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip, 3780 struct device_node *np) 3781 { 3782 struct device *dev = chip->dev; 3783 struct dsa_switch *ds; 3784 3785 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 3786 if (!ds) 3787 return -ENOMEM; 3788 3789 ds->dev = dev; 3790 ds->priv = chip; 3791 ds->ops = &mv88e6xxx_switch_ops; 3792 3793 dev_set_drvdata(dev, ds); 3794 3795 return dsa_register_switch(ds, np); 3796 } 3797 3798 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3799 { 3800 dsa_unregister_switch(chip->ds); 3801 } 3802 3803 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3804 { 3805 struct device *dev = &mdiodev->dev; 3806 struct device_node *np = dev->of_node; 3807 const struct mv88e6xxx_info *compat_info; 3808 struct mv88e6xxx_chip *chip; 3809 u32 eeprom_len; 3810 int err; 3811 3812 compat_info = of_device_get_match_data(dev); 3813 if (!compat_info) 3814 return -EINVAL; 3815 3816 chip = mv88e6xxx_alloc_chip(dev); 3817 if (!chip) 3818 return -ENOMEM; 3819 3820 chip->info = compat_info; 3821 3822 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3823 if (err) 3824 return err; 3825 3826 err = mv88e6xxx_detect(chip); 3827 if (err) 3828 return err; 3829 3830 mv88e6xxx_phy_init(chip); 3831 3832 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_ASIS); 3833 if (IS_ERR(chip->reset)) 3834 return PTR_ERR(chip->reset); 3835 3836 if (chip->info->ops->get_eeprom && 3837 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3838 chip->eeprom_len = eeprom_len; 3839 3840 err = mv88e6xxx_mdio_register(chip, np); 3841 if (err) 3842 return err; 3843 3844 err = mv88e6xxx_register_switch(chip, np); 3845 if (err) { 3846 mv88e6xxx_mdio_unregister(chip); 3847 return err; 3848 } 3849 3850 return 0; 3851 } 3852 3853 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 3854 { 3855 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 3856 struct mv88e6xxx_chip *chip = ds->priv; 3857 3858 mv88e6xxx_phy_destroy(chip); 3859 mv88e6xxx_unregister_switch(chip); 3860 mv88e6xxx_mdio_unregister(chip); 3861 } 3862 3863 static const struct of_device_id mv88e6xxx_of_match[] = { 3864 { 3865 .compatible = "marvell,mv88e6085", 3866 .data = &mv88e6xxx_table[MV88E6085], 3867 }, 3868 { /* sentinel */ }, 3869 }; 3870 3871 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 3872 3873 static struct mdio_driver mv88e6xxx_driver = { 3874 .probe = mv88e6xxx_probe, 3875 .remove = mv88e6xxx_remove, 3876 .mdiodrv.driver = { 3877 .name = "mv88e6085", 3878 .of_match_table = mv88e6xxx_of_match, 3879 }, 3880 }; 3881 3882 static int __init mv88e6xxx_init(void) 3883 { 3884 register_switch_driver(&mv88e6xxx_switch_ops); 3885 return mdio_driver_register(&mv88e6xxx_driver); 3886 } 3887 module_init(mv88e6xxx_init); 3888 3889 static void __exit mv88e6xxx_cleanup(void) 3890 { 3891 mdio_driver_unregister(&mv88e6xxx_driver); 3892 unregister_switch_driver(&mv88e6xxx_switch_ops); 3893 } 3894 module_exit(mv88e6xxx_cleanup); 3895 3896 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 3897 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 3898 MODULE_LICENSE("GPL"); 3899