1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_pause) { 453 err = chip->info->ops->port_set_pause(chip, port, pause); 454 if (err) 455 goto restore_link; 456 } 457 458 err = mv88e6xxx_port_config_interface(chip, port, mode); 459 restore_link: 460 if (chip->info->ops->port_set_link(chip, port, link)) 461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 462 463 return err; 464 } 465 466 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 467 { 468 struct mv88e6xxx_chip *chip = ds->priv; 469 470 return port < chip->info->num_internal_phys; 471 } 472 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 474 { 475 u16 reg; 476 int err; 477 478 /* The 88e6250 family does not have the PHY detect bit. Instead, 479 * report whether the port is internal. 480 */ 481 if (chip->info->family == MV88E6XXX_FAMILY_6250) 482 return port < chip->info->num_internal_phys; 483 484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 485 if (err) { 486 dev_err(chip->dev, 487 "p%d: %s: failed to read port status\n", 488 port, __func__); 489 return err; 490 } 491 492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 493 } 494 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 496 struct phylink_link_state *state) 497 { 498 struct mv88e6xxx_chip *chip = ds->priv; 499 int lane; 500 int err; 501 502 mv88e6xxx_reg_lock(chip); 503 lane = mv88e6xxx_serdes_get_lane(chip, port); 504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 506 state); 507 else 508 err = -EOPNOTSUPP; 509 mv88e6xxx_reg_unlock(chip); 510 511 return err; 512 } 513 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 515 unsigned int mode, 516 phy_interface_t interface, 517 const unsigned long *advertise) 518 { 519 const struct mv88e6xxx_ops *ops = chip->info->ops; 520 int lane; 521 522 if (ops->serdes_pcs_config) { 523 lane = mv88e6xxx_serdes_get_lane(chip, port); 524 if (lane >= 0) 525 return ops->serdes_pcs_config(chip, port, lane, mode, 526 interface, advertise); 527 } 528 529 return 0; 530 } 531 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 533 { 534 struct mv88e6xxx_chip *chip = ds->priv; 535 const struct mv88e6xxx_ops *ops; 536 int err = 0; 537 int lane; 538 539 ops = chip->info->ops; 540 541 if (ops->serdes_pcs_an_restart) { 542 mv88e6xxx_reg_lock(chip); 543 lane = mv88e6xxx_serdes_get_lane(chip, port); 544 if (lane >= 0) 545 err = ops->serdes_pcs_an_restart(chip, port, lane); 546 mv88e6xxx_reg_unlock(chip); 547 548 if (err) 549 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 550 } 551 } 552 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 554 unsigned int mode, 555 int speed, int duplex) 556 { 557 const struct mv88e6xxx_ops *ops = chip->info->ops; 558 int lane; 559 560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 561 lane = mv88e6xxx_serdes_get_lane(chip, port); 562 if (lane >= 0) 563 return ops->serdes_pcs_link_up(chip, port, lane, 564 speed, duplex); 565 } 566 567 return 0; 568 } 569 570 static const u8 mv88e6185_phy_interface_modes[] = { 571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 578 }; 579 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 u8 cmode = chip->ports[port].cmode; 584 585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 586 587 if (mv88e6xxx_phy_is_internal(chip->ds, port)) { 588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 589 } else { 590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 591 mv88e6185_phy_interface_modes[cmode]) 592 __set_bit(mv88e6185_phy_interface_modes[cmode], 593 config->supported_interfaces); 594 595 config->mac_capabilities |= MAC_1000FD; 596 } 597 } 598 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 600 struct phylink_config *config) 601 { 602 u8 cmode = chip->ports[port].cmode; 603 604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 605 mv88e6185_phy_interface_modes[cmode]) 606 __set_bit(mv88e6185_phy_interface_modes[cmode], 607 config->supported_interfaces); 608 609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 610 MAC_1000FD; 611 } 612 613 static const u8 mv88e6xxx_phy_interface_modes[] = { 614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 622 /* higher interface modes are not needed here, since ports supporting 623 * them are writable, and so the supported interfaces are filled in the 624 * corresponding .phylink_set_interfaces() implementation below 625 */ 626 }; 627 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 629 { 630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 631 mv88e6xxx_phy_interface_modes[cmode]) 632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 634 phy_interface_set_rgmii(supported); 635 } 636 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 638 struct phylink_config *config) 639 { 640 unsigned long *supported = config->supported_interfaces; 641 642 /* Translate the default cmode */ 643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 644 645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 646 } 647 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 649 { 650 u16 reg, val; 651 int err; 652 653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 654 if (err) 655 return err; 656 657 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 659 return 0xf; 660 661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 663 if (err) 664 return err; 665 666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 667 if (err) 668 return err; 669 670 /* Restore PHY_DETECT value */ 671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 672 if (err) 673 return err; 674 675 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 676 } 677 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config) 680 { 681 unsigned long *supported = config->supported_interfaces; 682 int err, cmode; 683 684 /* Translate the default cmode */ 685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 686 687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 688 MAC_1000FD; 689 690 /* Port 4 supports automedia if the serdes is associated with it. */ 691 if (port == 4) { 692 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 693 if (err < 0) 694 dev_err(chip->dev, "p%d: failed to read scratch\n", 695 port); 696 if (err <= 0) 697 return; 698 699 cmode = mv88e6352_get_port4_serdes_cmode(chip); 700 if (cmode < 0) 701 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 702 port); 703 else 704 mv88e6xxx_translate_cmode(cmode, supported); 705 } 706 } 707 708 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 709 struct phylink_config *config) 710 { 711 unsigned long *supported = config->supported_interfaces; 712 713 /* Translate the default cmode */ 714 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 715 716 /* No ethtool bits for 200Mbps */ 717 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 718 MAC_1000FD; 719 720 /* The C_Mode field is programmable on port 5 */ 721 if (port == 5) { 722 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 724 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 725 726 config->mac_capabilities |= MAC_2500FD; 727 } 728 } 729 730 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 731 struct phylink_config *config) 732 { 733 unsigned long *supported = config->supported_interfaces; 734 735 /* Translate the default cmode */ 736 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 737 738 /* No ethtool bits for 200Mbps */ 739 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 740 MAC_1000FD; 741 742 /* The C_Mode field is programmable on ports 9 and 10 */ 743 if (port == 9 || port == 10) { 744 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 745 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 746 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 747 748 config->mac_capabilities |= MAC_2500FD; 749 } 750 } 751 752 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 753 struct phylink_config *config) 754 { 755 unsigned long *supported = config->supported_interfaces; 756 757 mv88e6390_phylink_get_caps(chip, port, config); 758 759 /* For the 6x90X, ports 2-7 can be in automedia mode. 760 * (Note that 6x90 doesn't support RXAUI nor XAUI). 761 * 762 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 763 * configured for 1000BASE-X, SGMII or 2500BASE-X. 764 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 765 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 766 * 767 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 768 * configured for 1000BASE-X, SGMII or 2500BASE-X. 769 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 770 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 771 * 772 * For now, be permissive (as the old code was) and allow 1000BASE-X 773 * on ports 2..7. 774 */ 775 if (port >= 2 && port <= 7) 776 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 777 778 /* The C_Mode field can also be programmed for 10G speeds */ 779 if (port == 9 || port == 10) { 780 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 781 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 782 783 config->mac_capabilities |= MAC_10000FD; 784 } 785 } 786 787 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 788 struct phylink_config *config) 789 { 790 unsigned long *supported = config->supported_interfaces; 791 bool is_6191x = 792 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 793 794 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 795 796 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 797 MAC_1000FD; 798 799 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 800 if (port == 0 || port == 9 || port == 10) { 801 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 802 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 803 804 /* 6191X supports >1G modes only on port 10 */ 805 if (!is_6191x || port == 10) { 806 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 807 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 808 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 809 /* FIXME: USXGMII is not supported yet */ 810 /* __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); */ 811 812 config->mac_capabilities |= MAC_2500FD | MAC_5000FD | 813 MAC_10000FD; 814 } 815 } 816 817 if (port == 0) { 818 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 819 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 820 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 821 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 822 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 823 } 824 } 825 826 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 827 struct phylink_config *config) 828 { 829 struct mv88e6xxx_chip *chip = ds->priv; 830 831 mv88e6xxx_reg_lock(chip); 832 chip->info->ops->phylink_get_caps(chip, port, config); 833 mv88e6xxx_reg_unlock(chip); 834 835 if (mv88e6xxx_phy_is_internal(ds, port)) { 836 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 837 config->supported_interfaces); 838 /* Internal ports with no phy-mode need GMII for PHYLIB */ 839 __set_bit(PHY_INTERFACE_MODE_GMII, 840 config->supported_interfaces); 841 } 842 } 843 844 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 845 unsigned int mode, 846 const struct phylink_link_state *state) 847 { 848 struct mv88e6xxx_chip *chip = ds->priv; 849 struct mv88e6xxx_port *p; 850 int err = 0; 851 852 p = &chip->ports[port]; 853 854 mv88e6xxx_reg_lock(chip); 855 856 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 857 /* In inband mode, the link may come up at any time while the 858 * link is not forced down. Force the link down while we 859 * reconfigure the interface mode. 860 */ 861 if (mode == MLO_AN_INBAND && 862 p->interface != state->interface && 863 chip->info->ops->port_set_link) 864 chip->info->ops->port_set_link(chip, port, 865 LINK_FORCED_DOWN); 866 867 err = mv88e6xxx_port_config_interface(chip, port, 868 state->interface); 869 if (err && err != -EOPNOTSUPP) 870 goto err_unlock; 871 872 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 873 state->interface, 874 state->advertising); 875 /* FIXME: we should restart negotiation if something changed - 876 * which is something we get if we convert to using phylinks 877 * PCS operations. 878 */ 879 if (err > 0) 880 err = 0; 881 } 882 883 /* Undo the forced down state above after completing configuration 884 * irrespective of its state on entry, which allows the link to come 885 * up in the in-band case where there is no separate SERDES. Also 886 * ensure that the link can come up if the PPU is in use and we are 887 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 888 */ 889 if (chip->info->ops->port_set_link && 890 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 891 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 892 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 893 894 p->interface = state->interface; 895 896 err_unlock: 897 mv88e6xxx_reg_unlock(chip); 898 899 if (err && err != -EOPNOTSUPP) 900 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 901 } 902 903 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 904 unsigned int mode, 905 phy_interface_t interface) 906 { 907 struct mv88e6xxx_chip *chip = ds->priv; 908 const struct mv88e6xxx_ops *ops; 909 int err = 0; 910 911 ops = chip->info->ops; 912 913 mv88e6xxx_reg_lock(chip); 914 /* Force the link down if we know the port may not be automatically 915 * updated by the switch or if we are using fixed-link mode. 916 */ 917 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 918 mode == MLO_AN_FIXED) && ops->port_sync_link) 919 err = ops->port_sync_link(chip, port, mode, false); 920 921 if (!err && ops->port_set_speed_duplex) 922 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 923 DUPLEX_UNFORCED); 924 mv88e6xxx_reg_unlock(chip); 925 926 if (err) 927 dev_err(chip->dev, 928 "p%d: failed to force MAC link down\n", port); 929 } 930 931 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 932 unsigned int mode, phy_interface_t interface, 933 struct phy_device *phydev, 934 int speed, int duplex, 935 bool tx_pause, bool rx_pause) 936 { 937 struct mv88e6xxx_chip *chip = ds->priv; 938 const struct mv88e6xxx_ops *ops; 939 int err = 0; 940 941 ops = chip->info->ops; 942 943 mv88e6xxx_reg_lock(chip); 944 /* Configure and force the link up if we know that the port may not 945 * automatically updated by the switch or if we are using fixed-link 946 * mode. 947 */ 948 if (!mv88e6xxx_port_ppu_updates(chip, port) || 949 mode == MLO_AN_FIXED) { 950 /* FIXME: for an automedia port, should we force the link 951 * down here - what if the link comes up due to "other" media 952 * while we're bringing the port up, how is the exclusivity 953 * handled in the Marvell hardware? E.g. port 2 on 88E6390 954 * shared between internal PHY and Serdes. 955 */ 956 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 957 duplex); 958 if (err) 959 goto error; 960 961 if (ops->port_set_speed_duplex) { 962 err = ops->port_set_speed_duplex(chip, port, 963 speed, duplex); 964 if (err && err != -EOPNOTSUPP) 965 goto error; 966 } 967 968 if (ops->port_sync_link) 969 err = ops->port_sync_link(chip, port, mode, true); 970 } 971 error: 972 mv88e6xxx_reg_unlock(chip); 973 974 if (err && err != -EOPNOTSUPP) 975 dev_err(ds->dev, 976 "p%d: failed to configure MAC link up\n", port); 977 } 978 979 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 980 { 981 if (!chip->info->ops->stats_snapshot) 982 return -EOPNOTSUPP; 983 984 return chip->info->ops->stats_snapshot(chip, port); 985 } 986 987 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 988 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 989 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 990 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 991 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 992 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 993 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 994 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 995 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 996 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 997 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 998 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 999 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1000 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1001 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1002 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1003 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1004 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1005 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1006 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1007 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1008 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1009 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1010 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1011 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1012 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1013 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1014 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1015 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1016 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1017 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1018 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1019 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1020 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1021 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1022 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1023 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1024 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1025 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1026 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1027 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1028 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1029 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1030 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1031 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1032 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1033 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1034 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1035 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1036 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1037 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1038 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1039 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1040 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1041 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1042 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1043 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1044 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1045 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1046 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1047 }; 1048 1049 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1050 struct mv88e6xxx_hw_stat *s, 1051 int port, u16 bank1_select, 1052 u16 histogram) 1053 { 1054 u32 low; 1055 u32 high = 0; 1056 u16 reg = 0; 1057 int err; 1058 u64 value; 1059 1060 switch (s->type) { 1061 case STATS_TYPE_PORT: 1062 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1063 if (err) 1064 return U64_MAX; 1065 1066 low = reg; 1067 if (s->size == 4) { 1068 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1069 if (err) 1070 return U64_MAX; 1071 low |= ((u32)reg) << 16; 1072 } 1073 break; 1074 case STATS_TYPE_BANK1: 1075 reg = bank1_select; 1076 fallthrough; 1077 case STATS_TYPE_BANK0: 1078 reg |= s->reg | histogram; 1079 mv88e6xxx_g1_stats_read(chip, reg, &low); 1080 if (s->size == 8) 1081 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1082 break; 1083 default: 1084 return U64_MAX; 1085 } 1086 value = (((u64)high) << 32) | low; 1087 return value; 1088 } 1089 1090 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1091 uint8_t *data, int types) 1092 { 1093 struct mv88e6xxx_hw_stat *stat; 1094 int i, j; 1095 1096 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1097 stat = &mv88e6xxx_hw_stats[i]; 1098 if (stat->type & types) { 1099 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1100 ETH_GSTRING_LEN); 1101 j++; 1102 } 1103 } 1104 1105 return j; 1106 } 1107 1108 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1109 uint8_t *data) 1110 { 1111 return mv88e6xxx_stats_get_strings(chip, data, 1112 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1113 } 1114 1115 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1116 uint8_t *data) 1117 { 1118 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1119 } 1120 1121 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1122 uint8_t *data) 1123 { 1124 return mv88e6xxx_stats_get_strings(chip, data, 1125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1126 } 1127 1128 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1129 "atu_member_violation", 1130 "atu_miss_violation", 1131 "atu_full_violation", 1132 "vtu_member_violation", 1133 "vtu_miss_violation", 1134 }; 1135 1136 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1137 { 1138 unsigned int i; 1139 1140 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1141 strscpy(data + i * ETH_GSTRING_LEN, 1142 mv88e6xxx_atu_vtu_stats_strings[i], 1143 ETH_GSTRING_LEN); 1144 } 1145 1146 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1147 u32 stringset, uint8_t *data) 1148 { 1149 struct mv88e6xxx_chip *chip = ds->priv; 1150 int count = 0; 1151 1152 if (stringset != ETH_SS_STATS) 1153 return; 1154 1155 mv88e6xxx_reg_lock(chip); 1156 1157 if (chip->info->ops->stats_get_strings) 1158 count = chip->info->ops->stats_get_strings(chip, data); 1159 1160 if (chip->info->ops->serdes_get_strings) { 1161 data += count * ETH_GSTRING_LEN; 1162 count = chip->info->ops->serdes_get_strings(chip, port, data); 1163 } 1164 1165 data += count * ETH_GSTRING_LEN; 1166 mv88e6xxx_atu_vtu_get_strings(data); 1167 1168 mv88e6xxx_reg_unlock(chip); 1169 } 1170 1171 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1172 int types) 1173 { 1174 struct mv88e6xxx_hw_stat *stat; 1175 int i, j; 1176 1177 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1178 stat = &mv88e6xxx_hw_stats[i]; 1179 if (stat->type & types) 1180 j++; 1181 } 1182 return j; 1183 } 1184 1185 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1186 { 1187 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1188 STATS_TYPE_PORT); 1189 } 1190 1191 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1192 { 1193 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1194 } 1195 1196 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1197 { 1198 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1199 STATS_TYPE_BANK1); 1200 } 1201 1202 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1203 { 1204 struct mv88e6xxx_chip *chip = ds->priv; 1205 int serdes_count = 0; 1206 int count = 0; 1207 1208 if (sset != ETH_SS_STATS) 1209 return 0; 1210 1211 mv88e6xxx_reg_lock(chip); 1212 if (chip->info->ops->stats_get_sset_count) 1213 count = chip->info->ops->stats_get_sset_count(chip); 1214 if (count < 0) 1215 goto out; 1216 1217 if (chip->info->ops->serdes_get_sset_count) 1218 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1219 port); 1220 if (serdes_count < 0) { 1221 count = serdes_count; 1222 goto out; 1223 } 1224 count += serdes_count; 1225 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1226 1227 out: 1228 mv88e6xxx_reg_unlock(chip); 1229 1230 return count; 1231 } 1232 1233 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1234 uint64_t *data, int types, 1235 u16 bank1_select, u16 histogram) 1236 { 1237 struct mv88e6xxx_hw_stat *stat; 1238 int i, j; 1239 1240 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1241 stat = &mv88e6xxx_hw_stats[i]; 1242 if (stat->type & types) { 1243 mv88e6xxx_reg_lock(chip); 1244 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1245 bank1_select, 1246 histogram); 1247 mv88e6xxx_reg_unlock(chip); 1248 1249 j++; 1250 } 1251 } 1252 return j; 1253 } 1254 1255 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1256 uint64_t *data) 1257 { 1258 return mv88e6xxx_stats_get_stats(chip, port, data, 1259 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1260 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1261 } 1262 1263 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1264 uint64_t *data) 1265 { 1266 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1267 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1268 } 1269 1270 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1271 uint64_t *data) 1272 { 1273 return mv88e6xxx_stats_get_stats(chip, port, data, 1274 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1275 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1276 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1277 } 1278 1279 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1280 uint64_t *data) 1281 { 1282 return mv88e6xxx_stats_get_stats(chip, port, data, 1283 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1284 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1285 0); 1286 } 1287 1288 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1289 uint64_t *data) 1290 { 1291 *data++ = chip->ports[port].atu_member_violation; 1292 *data++ = chip->ports[port].atu_miss_violation; 1293 *data++ = chip->ports[port].atu_full_violation; 1294 *data++ = chip->ports[port].vtu_member_violation; 1295 *data++ = chip->ports[port].vtu_miss_violation; 1296 } 1297 1298 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1299 uint64_t *data) 1300 { 1301 int count = 0; 1302 1303 if (chip->info->ops->stats_get_stats) 1304 count = chip->info->ops->stats_get_stats(chip, port, data); 1305 1306 mv88e6xxx_reg_lock(chip); 1307 if (chip->info->ops->serdes_get_stats) { 1308 data += count; 1309 count = chip->info->ops->serdes_get_stats(chip, port, data); 1310 } 1311 data += count; 1312 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1313 mv88e6xxx_reg_unlock(chip); 1314 } 1315 1316 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1317 uint64_t *data) 1318 { 1319 struct mv88e6xxx_chip *chip = ds->priv; 1320 int ret; 1321 1322 mv88e6xxx_reg_lock(chip); 1323 1324 ret = mv88e6xxx_stats_snapshot(chip, port); 1325 mv88e6xxx_reg_unlock(chip); 1326 1327 if (ret < 0) 1328 return; 1329 1330 mv88e6xxx_get_stats(chip, port, data); 1331 1332 } 1333 1334 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1335 { 1336 struct mv88e6xxx_chip *chip = ds->priv; 1337 int len; 1338 1339 len = 32 * sizeof(u16); 1340 if (chip->info->ops->serdes_get_regs_len) 1341 len += chip->info->ops->serdes_get_regs_len(chip, port); 1342 1343 return len; 1344 } 1345 1346 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1347 struct ethtool_regs *regs, void *_p) 1348 { 1349 struct mv88e6xxx_chip *chip = ds->priv; 1350 int err; 1351 u16 reg; 1352 u16 *p = _p; 1353 int i; 1354 1355 regs->version = chip->info->prod_num; 1356 1357 memset(p, 0xff, 32 * sizeof(u16)); 1358 1359 mv88e6xxx_reg_lock(chip); 1360 1361 for (i = 0; i < 32; i++) { 1362 1363 err = mv88e6xxx_port_read(chip, port, i, ®); 1364 if (!err) 1365 p[i] = reg; 1366 } 1367 1368 if (chip->info->ops->serdes_get_regs) 1369 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1370 1371 mv88e6xxx_reg_unlock(chip); 1372 } 1373 1374 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1375 struct ethtool_eee *e) 1376 { 1377 /* Nothing to do on the port's MAC */ 1378 return 0; 1379 } 1380 1381 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1382 struct ethtool_eee *e) 1383 { 1384 /* Nothing to do on the port's MAC */ 1385 return 0; 1386 } 1387 1388 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1389 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1390 { 1391 struct dsa_switch *ds = chip->ds; 1392 struct dsa_switch_tree *dst = ds->dst; 1393 struct dsa_port *dp, *other_dp; 1394 bool found = false; 1395 u16 pvlan; 1396 1397 /* dev is a physical switch */ 1398 if (dev <= dst->last_switch) { 1399 list_for_each_entry(dp, &dst->ports, list) { 1400 if (dp->ds->index == dev && dp->index == port) { 1401 /* dp might be a DSA link or a user port, so it 1402 * might or might not have a bridge. 1403 * Use the "found" variable for both cases. 1404 */ 1405 found = true; 1406 break; 1407 } 1408 } 1409 /* dev is a virtual bridge */ 1410 } else { 1411 list_for_each_entry(dp, &dst->ports, list) { 1412 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1413 1414 if (!bridge_num) 1415 continue; 1416 1417 if (bridge_num + dst->last_switch != dev) 1418 continue; 1419 1420 found = true; 1421 break; 1422 } 1423 } 1424 1425 /* Prevent frames from unknown switch or virtual bridge */ 1426 if (!found) 1427 return 0; 1428 1429 /* Frames from DSA links and CPU ports can egress any local port */ 1430 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1431 return mv88e6xxx_port_mask(chip); 1432 1433 pvlan = 0; 1434 1435 /* Frames from standalone user ports can only egress on the 1436 * upstream port. 1437 */ 1438 if (!dsa_port_bridge_dev_get(dp)) 1439 return BIT(dsa_switch_upstream_port(ds)); 1440 1441 /* Frames from bridged user ports can egress any local DSA 1442 * links and CPU ports, as well as any local member of their 1443 * bridge group. 1444 */ 1445 dsa_switch_for_each_port(other_dp, ds) 1446 if (other_dp->type == DSA_PORT_TYPE_CPU || 1447 other_dp->type == DSA_PORT_TYPE_DSA || 1448 dsa_port_bridge_same(dp, other_dp)) 1449 pvlan |= BIT(other_dp->index); 1450 1451 return pvlan; 1452 } 1453 1454 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1455 { 1456 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1457 1458 /* prevent frames from going back out of the port they came in on */ 1459 output_ports &= ~BIT(port); 1460 1461 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1462 } 1463 1464 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1465 u8 state) 1466 { 1467 struct mv88e6xxx_chip *chip = ds->priv; 1468 int err; 1469 1470 mv88e6xxx_reg_lock(chip); 1471 err = mv88e6xxx_port_set_state(chip, port, state); 1472 mv88e6xxx_reg_unlock(chip); 1473 1474 if (err) 1475 dev_err(ds->dev, "p%d: failed to update state\n", port); 1476 } 1477 1478 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1479 { 1480 int err; 1481 1482 if (chip->info->ops->ieee_pri_map) { 1483 err = chip->info->ops->ieee_pri_map(chip); 1484 if (err) 1485 return err; 1486 } 1487 1488 if (chip->info->ops->ip_pri_map) { 1489 err = chip->info->ops->ip_pri_map(chip); 1490 if (err) 1491 return err; 1492 } 1493 1494 return 0; 1495 } 1496 1497 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1498 { 1499 struct dsa_switch *ds = chip->ds; 1500 int target, port; 1501 int err; 1502 1503 if (!chip->info->global2_addr) 1504 return 0; 1505 1506 /* Initialize the routing port to the 32 possible target devices */ 1507 for (target = 0; target < 32; target++) { 1508 port = dsa_routing_port(ds, target); 1509 if (port == ds->num_ports) 1510 port = 0x1f; 1511 1512 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1513 if (err) 1514 return err; 1515 } 1516 1517 if (chip->info->ops->set_cascade_port) { 1518 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1519 err = chip->info->ops->set_cascade_port(chip, port); 1520 if (err) 1521 return err; 1522 } 1523 1524 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1525 if (err) 1526 return err; 1527 1528 return 0; 1529 } 1530 1531 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1532 { 1533 /* Clear all trunk masks and mapping */ 1534 if (chip->info->global2_addr) 1535 return mv88e6xxx_g2_trunk_clear(chip); 1536 1537 return 0; 1538 } 1539 1540 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1541 { 1542 if (chip->info->ops->rmu_disable) 1543 return chip->info->ops->rmu_disable(chip); 1544 1545 return 0; 1546 } 1547 1548 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1549 { 1550 if (chip->info->ops->pot_clear) 1551 return chip->info->ops->pot_clear(chip); 1552 1553 return 0; 1554 } 1555 1556 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1557 { 1558 if (chip->info->ops->mgmt_rsvd2cpu) 1559 return chip->info->ops->mgmt_rsvd2cpu(chip); 1560 1561 return 0; 1562 } 1563 1564 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1565 { 1566 int err; 1567 1568 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1569 if (err) 1570 return err; 1571 1572 /* The chips that have a "learn2all" bit in Global1, ATU 1573 * Control are precisely those whose port registers have a 1574 * Message Port bit in Port Control 1 and hence implement 1575 * ->port_setup_message_port. 1576 */ 1577 if (chip->info->ops->port_setup_message_port) { 1578 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1579 if (err) 1580 return err; 1581 } 1582 1583 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1584 } 1585 1586 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1587 { 1588 int port; 1589 int err; 1590 1591 if (!chip->info->ops->irl_init_all) 1592 return 0; 1593 1594 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1595 /* Disable ingress rate limiting by resetting all per port 1596 * ingress rate limit resources to their initial state. 1597 */ 1598 err = chip->info->ops->irl_init_all(chip, port); 1599 if (err) 1600 return err; 1601 } 1602 1603 return 0; 1604 } 1605 1606 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1607 { 1608 if (chip->info->ops->set_switch_mac) { 1609 u8 addr[ETH_ALEN]; 1610 1611 eth_random_addr(addr); 1612 1613 return chip->info->ops->set_switch_mac(chip, addr); 1614 } 1615 1616 return 0; 1617 } 1618 1619 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1620 { 1621 struct dsa_switch_tree *dst = chip->ds->dst; 1622 struct dsa_switch *ds; 1623 struct dsa_port *dp; 1624 u16 pvlan = 0; 1625 1626 if (!mv88e6xxx_has_pvt(chip)) 1627 return 0; 1628 1629 /* Skip the local source device, which uses in-chip port VLAN */ 1630 if (dev != chip->ds->index) { 1631 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1632 1633 ds = dsa_switch_find(dst->index, dev); 1634 dp = ds ? dsa_to_port(ds, port) : NULL; 1635 if (dp && dp->lag) { 1636 /* As the PVT is used to limit flooding of 1637 * FORWARD frames, which use the LAG ID as the 1638 * source port, we must translate dev/port to 1639 * the special "LAG device" in the PVT, using 1640 * the LAG ID (one-based) as the port number 1641 * (zero-based). 1642 */ 1643 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1644 port = dsa_port_lag_id_get(dp) - 1; 1645 } 1646 } 1647 1648 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1649 } 1650 1651 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1652 { 1653 int dev, port; 1654 int err; 1655 1656 if (!mv88e6xxx_has_pvt(chip)) 1657 return 0; 1658 1659 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1660 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1661 */ 1662 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1663 if (err) 1664 return err; 1665 1666 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1667 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1668 err = mv88e6xxx_pvt_map(chip, dev, port); 1669 if (err) 1670 return err; 1671 } 1672 } 1673 1674 return 0; 1675 } 1676 1677 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1678 u16 fid) 1679 { 1680 if (dsa_to_port(chip->ds, port)->lag) 1681 /* Hardware is incapable of fast-aging a LAG through a 1682 * regular ATU move operation. Until we have something 1683 * more fancy in place this is a no-op. 1684 */ 1685 return -EOPNOTSUPP; 1686 1687 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1688 } 1689 1690 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1691 { 1692 struct mv88e6xxx_chip *chip = ds->priv; 1693 int err; 1694 1695 mv88e6xxx_reg_lock(chip); 1696 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1697 mv88e6xxx_reg_unlock(chip); 1698 1699 if (err) 1700 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1701 port, err); 1702 } 1703 1704 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1705 { 1706 if (!mv88e6xxx_max_vid(chip)) 1707 return 0; 1708 1709 return mv88e6xxx_g1_vtu_flush(chip); 1710 } 1711 1712 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1713 struct mv88e6xxx_vtu_entry *entry) 1714 { 1715 int err; 1716 1717 if (!chip->info->ops->vtu_getnext) 1718 return -EOPNOTSUPP; 1719 1720 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1721 entry->valid = false; 1722 1723 err = chip->info->ops->vtu_getnext(chip, entry); 1724 1725 if (entry->vid != vid) 1726 entry->valid = false; 1727 1728 return err; 1729 } 1730 1731 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1732 int (*cb)(struct mv88e6xxx_chip *chip, 1733 const struct mv88e6xxx_vtu_entry *entry, 1734 void *priv), 1735 void *priv) 1736 { 1737 struct mv88e6xxx_vtu_entry entry = { 1738 .vid = mv88e6xxx_max_vid(chip), 1739 .valid = false, 1740 }; 1741 int err; 1742 1743 if (!chip->info->ops->vtu_getnext) 1744 return -EOPNOTSUPP; 1745 1746 do { 1747 err = chip->info->ops->vtu_getnext(chip, &entry); 1748 if (err) 1749 return err; 1750 1751 if (!entry.valid) 1752 break; 1753 1754 err = cb(chip, &entry, priv); 1755 if (err) 1756 return err; 1757 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1758 1759 return 0; 1760 } 1761 1762 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1763 struct mv88e6xxx_vtu_entry *entry) 1764 { 1765 if (!chip->info->ops->vtu_loadpurge) 1766 return -EOPNOTSUPP; 1767 1768 return chip->info->ops->vtu_loadpurge(chip, entry); 1769 } 1770 1771 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1772 const struct mv88e6xxx_vtu_entry *entry, 1773 void *_fid_bitmap) 1774 { 1775 unsigned long *fid_bitmap = _fid_bitmap; 1776 1777 set_bit(entry->fid, fid_bitmap); 1778 return 0; 1779 } 1780 1781 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1782 { 1783 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1784 1785 /* Every FID has an associated VID, so walking the VTU 1786 * will discover the full set of FIDs in use. 1787 */ 1788 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1789 } 1790 1791 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1792 { 1793 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1794 int err; 1795 1796 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1797 if (err) 1798 return err; 1799 1800 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1801 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1802 return -ENOSPC; 1803 1804 /* Clear the database */ 1805 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1806 } 1807 1808 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1809 struct mv88e6xxx_stu_entry *entry) 1810 { 1811 if (!chip->info->ops->stu_loadpurge) 1812 return -EOPNOTSUPP; 1813 1814 return chip->info->ops->stu_loadpurge(chip, entry); 1815 } 1816 1817 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1818 { 1819 struct mv88e6xxx_stu_entry stu = { 1820 .valid = true, 1821 .sid = 0 1822 }; 1823 1824 if (!mv88e6xxx_has_stu(chip)) 1825 return 0; 1826 1827 /* Make sure that SID 0 is always valid. This is used by VTU 1828 * entries that do not make use of the STU, e.g. when creating 1829 * a VLAN upper on a port that is also part of a VLAN 1830 * filtering bridge. 1831 */ 1832 return mv88e6xxx_stu_loadpurge(chip, &stu); 1833 } 1834 1835 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1836 { 1837 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1838 struct mv88e6xxx_mst *mst; 1839 1840 __set_bit(0, busy); 1841 1842 list_for_each_entry(mst, &chip->msts, node) 1843 __set_bit(mst->stu.sid, busy); 1844 1845 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1846 1847 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1848 } 1849 1850 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1851 { 1852 struct mv88e6xxx_mst *mst, *tmp; 1853 int err; 1854 1855 if (!sid) 1856 return 0; 1857 1858 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1859 if (mst->stu.sid != sid) 1860 continue; 1861 1862 if (!refcount_dec_and_test(&mst->refcnt)) 1863 return 0; 1864 1865 mst->stu.valid = false; 1866 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1867 if (err) { 1868 refcount_set(&mst->refcnt, 1); 1869 return err; 1870 } 1871 1872 list_del(&mst->node); 1873 kfree(mst); 1874 return 0; 1875 } 1876 1877 return -ENOENT; 1878 } 1879 1880 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1881 u16 msti, u8 *sid) 1882 { 1883 struct mv88e6xxx_mst *mst; 1884 int err, i; 1885 1886 if (!mv88e6xxx_has_stu(chip)) { 1887 err = -EOPNOTSUPP; 1888 goto err; 1889 } 1890 1891 if (!msti) { 1892 *sid = 0; 1893 return 0; 1894 } 1895 1896 list_for_each_entry(mst, &chip->msts, node) { 1897 if (mst->br == br && mst->msti == msti) { 1898 refcount_inc(&mst->refcnt); 1899 *sid = mst->stu.sid; 1900 return 0; 1901 } 1902 } 1903 1904 err = mv88e6xxx_sid_get(chip, sid); 1905 if (err) 1906 goto err; 1907 1908 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1909 if (!mst) { 1910 err = -ENOMEM; 1911 goto err; 1912 } 1913 1914 INIT_LIST_HEAD(&mst->node); 1915 refcount_set(&mst->refcnt, 1); 1916 mst->br = br; 1917 mst->msti = msti; 1918 mst->stu.valid = true; 1919 mst->stu.sid = *sid; 1920 1921 /* The bridge starts out all ports in the disabled state. But 1922 * a STU state of disabled means to go by the port-global 1923 * state. So we set all user port's initial state to blocking, 1924 * to match the bridge's behavior. 1925 */ 1926 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1927 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1928 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1929 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1930 1931 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1932 if (err) 1933 goto err_free; 1934 1935 list_add_tail(&mst->node, &chip->msts); 1936 return 0; 1937 1938 err_free: 1939 kfree(mst); 1940 err: 1941 return err; 1942 } 1943 1944 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1945 const struct switchdev_mst_state *st) 1946 { 1947 struct dsa_port *dp = dsa_to_port(ds, port); 1948 struct mv88e6xxx_chip *chip = ds->priv; 1949 struct mv88e6xxx_mst *mst; 1950 u8 state; 1951 int err; 1952 1953 if (!mv88e6xxx_has_stu(chip)) 1954 return -EOPNOTSUPP; 1955 1956 switch (st->state) { 1957 case BR_STATE_DISABLED: 1958 case BR_STATE_BLOCKING: 1959 case BR_STATE_LISTENING: 1960 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1961 break; 1962 case BR_STATE_LEARNING: 1963 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1964 break; 1965 case BR_STATE_FORWARDING: 1966 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1967 break; 1968 default: 1969 return -EINVAL; 1970 } 1971 1972 list_for_each_entry(mst, &chip->msts, node) { 1973 if (mst->br == dsa_port_bridge_dev_get(dp) && 1974 mst->msti == st->msti) { 1975 if (mst->stu.state[port] == state) 1976 return 0; 1977 1978 mst->stu.state[port] = state; 1979 mv88e6xxx_reg_lock(chip); 1980 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1981 mv88e6xxx_reg_unlock(chip); 1982 return err; 1983 } 1984 } 1985 1986 return -ENOENT; 1987 } 1988 1989 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1990 u16 vid) 1991 { 1992 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1993 struct mv88e6xxx_chip *chip = ds->priv; 1994 struct mv88e6xxx_vtu_entry vlan; 1995 int err; 1996 1997 /* DSA and CPU ports have to be members of multiple vlans */ 1998 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1999 return 0; 2000 2001 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2002 if (err) 2003 return err; 2004 2005 if (!vlan.valid) 2006 return 0; 2007 2008 dsa_switch_for_each_user_port(other_dp, ds) { 2009 struct net_device *other_br; 2010 2011 if (vlan.member[other_dp->index] == 2012 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2013 continue; 2014 2015 if (dsa_port_bridge_same(dp, other_dp)) 2016 break; /* same bridge, check next VLAN */ 2017 2018 other_br = dsa_port_bridge_dev_get(other_dp); 2019 if (!other_br) 2020 continue; 2021 2022 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2023 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2024 return -EOPNOTSUPP; 2025 } 2026 2027 return 0; 2028 } 2029 2030 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2031 { 2032 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2033 struct net_device *br = dsa_port_bridge_dev_get(dp); 2034 struct mv88e6xxx_port *p = &chip->ports[port]; 2035 u16 pvid = MV88E6XXX_VID_STANDALONE; 2036 bool drop_untagged = false; 2037 int err; 2038 2039 if (br) { 2040 if (br_vlan_enabled(br)) { 2041 pvid = p->bridge_pvid.vid; 2042 drop_untagged = !p->bridge_pvid.valid; 2043 } else { 2044 pvid = MV88E6XXX_VID_BRIDGED; 2045 } 2046 } 2047 2048 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2049 if (err) 2050 return err; 2051 2052 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2053 } 2054 2055 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2056 bool vlan_filtering, 2057 struct netlink_ext_ack *extack) 2058 { 2059 struct mv88e6xxx_chip *chip = ds->priv; 2060 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2061 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2062 int err; 2063 2064 if (!mv88e6xxx_max_vid(chip)) 2065 return -EOPNOTSUPP; 2066 2067 mv88e6xxx_reg_lock(chip); 2068 2069 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2070 if (err) 2071 goto unlock; 2072 2073 err = mv88e6xxx_port_commit_pvid(chip, port); 2074 if (err) 2075 goto unlock; 2076 2077 unlock: 2078 mv88e6xxx_reg_unlock(chip); 2079 2080 return err; 2081 } 2082 2083 static int 2084 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2085 const struct switchdev_obj_port_vlan *vlan) 2086 { 2087 struct mv88e6xxx_chip *chip = ds->priv; 2088 int err; 2089 2090 if (!mv88e6xxx_max_vid(chip)) 2091 return -EOPNOTSUPP; 2092 2093 /* If the requested port doesn't belong to the same bridge as the VLAN 2094 * members, do not support it (yet) and fallback to software VLAN. 2095 */ 2096 mv88e6xxx_reg_lock(chip); 2097 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2098 mv88e6xxx_reg_unlock(chip); 2099 2100 return err; 2101 } 2102 2103 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2104 const unsigned char *addr, u16 vid, 2105 u8 state) 2106 { 2107 struct mv88e6xxx_atu_entry entry; 2108 struct mv88e6xxx_vtu_entry vlan; 2109 u16 fid; 2110 int err; 2111 2112 /* Ports have two private address databases: one for when the port is 2113 * standalone and one for when the port is under a bridge and the 2114 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2115 * address database to remain 100% empty, so we never load an ATU entry 2116 * into a standalone port's database. Therefore, translate the null 2117 * VLAN ID into the port's database used for VLAN-unaware bridging. 2118 */ 2119 if (vid == 0) { 2120 fid = MV88E6XXX_FID_BRIDGED; 2121 } else { 2122 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2123 if (err) 2124 return err; 2125 2126 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2127 if (!vlan.valid) 2128 return -EOPNOTSUPP; 2129 2130 fid = vlan.fid; 2131 } 2132 2133 entry.state = 0; 2134 ether_addr_copy(entry.mac, addr); 2135 eth_addr_dec(entry.mac); 2136 2137 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2138 if (err) 2139 return err; 2140 2141 /* Initialize a fresh ATU entry if it isn't found */ 2142 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2143 memset(&entry, 0, sizeof(entry)); 2144 ether_addr_copy(entry.mac, addr); 2145 } 2146 2147 /* Purge the ATU entry only if no port is using it anymore */ 2148 if (!state) { 2149 entry.portvec &= ~BIT(port); 2150 if (!entry.portvec) 2151 entry.state = 0; 2152 } else { 2153 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2154 entry.portvec = BIT(port); 2155 else 2156 entry.portvec |= BIT(port); 2157 2158 entry.state = state; 2159 } 2160 2161 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2162 } 2163 2164 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2165 const struct mv88e6xxx_policy *policy) 2166 { 2167 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2168 enum mv88e6xxx_policy_action action = policy->action; 2169 const u8 *addr = policy->addr; 2170 u16 vid = policy->vid; 2171 u8 state; 2172 int err; 2173 int id; 2174 2175 if (!chip->info->ops->port_set_policy) 2176 return -EOPNOTSUPP; 2177 2178 switch (mapping) { 2179 case MV88E6XXX_POLICY_MAPPING_DA: 2180 case MV88E6XXX_POLICY_MAPPING_SA: 2181 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2182 state = 0; /* Dissociate the port and address */ 2183 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2184 is_multicast_ether_addr(addr)) 2185 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2186 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2187 is_unicast_ether_addr(addr)) 2188 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2189 else 2190 return -EOPNOTSUPP; 2191 2192 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2193 state); 2194 if (err) 2195 return err; 2196 break; 2197 default: 2198 return -EOPNOTSUPP; 2199 } 2200 2201 /* Skip the port's policy clearing if the mapping is still in use */ 2202 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2203 idr_for_each_entry(&chip->policies, policy, id) 2204 if (policy->port == port && 2205 policy->mapping == mapping && 2206 policy->action != action) 2207 return 0; 2208 2209 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2210 } 2211 2212 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2213 struct ethtool_rx_flow_spec *fs) 2214 { 2215 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2216 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2217 enum mv88e6xxx_policy_mapping mapping; 2218 enum mv88e6xxx_policy_action action; 2219 struct mv88e6xxx_policy *policy; 2220 u16 vid = 0; 2221 u8 *addr; 2222 int err; 2223 int id; 2224 2225 if (fs->location != RX_CLS_LOC_ANY) 2226 return -EINVAL; 2227 2228 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2229 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2230 else 2231 return -EOPNOTSUPP; 2232 2233 switch (fs->flow_type & ~FLOW_EXT) { 2234 case ETHER_FLOW: 2235 if (!is_zero_ether_addr(mac_mask->h_dest) && 2236 is_zero_ether_addr(mac_mask->h_source)) { 2237 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2238 addr = mac_entry->h_dest; 2239 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2240 !is_zero_ether_addr(mac_mask->h_source)) { 2241 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2242 addr = mac_entry->h_source; 2243 } else { 2244 /* Cannot support DA and SA mapping in the same rule */ 2245 return -EOPNOTSUPP; 2246 } 2247 break; 2248 default: 2249 return -EOPNOTSUPP; 2250 } 2251 2252 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2253 if (fs->m_ext.vlan_tci != htons(0xffff)) 2254 return -EOPNOTSUPP; 2255 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2256 } 2257 2258 idr_for_each_entry(&chip->policies, policy, id) { 2259 if (policy->port == port && policy->mapping == mapping && 2260 policy->action == action && policy->vid == vid && 2261 ether_addr_equal(policy->addr, addr)) 2262 return -EEXIST; 2263 } 2264 2265 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2266 if (!policy) 2267 return -ENOMEM; 2268 2269 fs->location = 0; 2270 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2271 GFP_KERNEL); 2272 if (err) { 2273 devm_kfree(chip->dev, policy); 2274 return err; 2275 } 2276 2277 memcpy(&policy->fs, fs, sizeof(*fs)); 2278 ether_addr_copy(policy->addr, addr); 2279 policy->mapping = mapping; 2280 policy->action = action; 2281 policy->port = port; 2282 policy->vid = vid; 2283 2284 err = mv88e6xxx_policy_apply(chip, port, policy); 2285 if (err) { 2286 idr_remove(&chip->policies, fs->location); 2287 devm_kfree(chip->dev, policy); 2288 return err; 2289 } 2290 2291 return 0; 2292 } 2293 2294 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2295 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2296 { 2297 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2298 struct mv88e6xxx_chip *chip = ds->priv; 2299 struct mv88e6xxx_policy *policy; 2300 int err; 2301 int id; 2302 2303 mv88e6xxx_reg_lock(chip); 2304 2305 switch (rxnfc->cmd) { 2306 case ETHTOOL_GRXCLSRLCNT: 2307 rxnfc->data = 0; 2308 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2309 rxnfc->rule_cnt = 0; 2310 idr_for_each_entry(&chip->policies, policy, id) 2311 if (policy->port == port) 2312 rxnfc->rule_cnt++; 2313 err = 0; 2314 break; 2315 case ETHTOOL_GRXCLSRULE: 2316 err = -ENOENT; 2317 policy = idr_find(&chip->policies, fs->location); 2318 if (policy) { 2319 memcpy(fs, &policy->fs, sizeof(*fs)); 2320 err = 0; 2321 } 2322 break; 2323 case ETHTOOL_GRXCLSRLALL: 2324 rxnfc->data = 0; 2325 rxnfc->rule_cnt = 0; 2326 idr_for_each_entry(&chip->policies, policy, id) 2327 if (policy->port == port) 2328 rule_locs[rxnfc->rule_cnt++] = id; 2329 err = 0; 2330 break; 2331 default: 2332 err = -EOPNOTSUPP; 2333 break; 2334 } 2335 2336 mv88e6xxx_reg_unlock(chip); 2337 2338 return err; 2339 } 2340 2341 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2342 struct ethtool_rxnfc *rxnfc) 2343 { 2344 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2345 struct mv88e6xxx_chip *chip = ds->priv; 2346 struct mv88e6xxx_policy *policy; 2347 int err; 2348 2349 mv88e6xxx_reg_lock(chip); 2350 2351 switch (rxnfc->cmd) { 2352 case ETHTOOL_SRXCLSRLINS: 2353 err = mv88e6xxx_policy_insert(chip, port, fs); 2354 break; 2355 case ETHTOOL_SRXCLSRLDEL: 2356 err = -ENOENT; 2357 policy = idr_remove(&chip->policies, fs->location); 2358 if (policy) { 2359 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2360 err = mv88e6xxx_policy_apply(chip, port, policy); 2361 devm_kfree(chip->dev, policy); 2362 } 2363 break; 2364 default: 2365 err = -EOPNOTSUPP; 2366 break; 2367 } 2368 2369 mv88e6xxx_reg_unlock(chip); 2370 2371 return err; 2372 } 2373 2374 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2375 u16 vid) 2376 { 2377 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2378 u8 broadcast[ETH_ALEN]; 2379 2380 eth_broadcast_addr(broadcast); 2381 2382 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2383 } 2384 2385 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2386 { 2387 int port; 2388 int err; 2389 2390 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2391 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2392 struct net_device *brport; 2393 2394 if (dsa_is_unused_port(chip->ds, port)) 2395 continue; 2396 2397 brport = dsa_port_to_bridge_port(dp); 2398 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2399 /* Skip bridged user ports where broadcast 2400 * flooding is disabled. 2401 */ 2402 continue; 2403 2404 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2405 if (err) 2406 return err; 2407 } 2408 2409 return 0; 2410 } 2411 2412 struct mv88e6xxx_port_broadcast_sync_ctx { 2413 int port; 2414 bool flood; 2415 }; 2416 2417 static int 2418 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2419 const struct mv88e6xxx_vtu_entry *vlan, 2420 void *_ctx) 2421 { 2422 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2423 u8 broadcast[ETH_ALEN]; 2424 u8 state; 2425 2426 if (ctx->flood) 2427 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2428 else 2429 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2430 2431 eth_broadcast_addr(broadcast); 2432 2433 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2434 vlan->vid, state); 2435 } 2436 2437 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2438 bool flood) 2439 { 2440 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2441 .port = port, 2442 .flood = flood, 2443 }; 2444 struct mv88e6xxx_vtu_entry vid0 = { 2445 .vid = 0, 2446 }; 2447 int err; 2448 2449 /* Update the port's private database... */ 2450 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2451 if (err) 2452 return err; 2453 2454 /* ...and the database for all VLANs. */ 2455 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2456 &ctx); 2457 } 2458 2459 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2460 u16 vid, u8 member, bool warn) 2461 { 2462 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2463 struct mv88e6xxx_vtu_entry vlan; 2464 int i, err; 2465 2466 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2467 if (err) 2468 return err; 2469 2470 if (!vlan.valid) { 2471 memset(&vlan, 0, sizeof(vlan)); 2472 2473 if (vid == MV88E6XXX_VID_STANDALONE) 2474 vlan.policy = true; 2475 2476 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2477 if (err) 2478 return err; 2479 2480 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2481 if (i == port) 2482 vlan.member[i] = member; 2483 else 2484 vlan.member[i] = non_member; 2485 2486 vlan.vid = vid; 2487 vlan.valid = true; 2488 2489 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2490 if (err) 2491 return err; 2492 2493 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2494 if (err) 2495 return err; 2496 } else if (vlan.member[port] != member) { 2497 vlan.member[port] = member; 2498 2499 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2500 if (err) 2501 return err; 2502 } else if (warn) { 2503 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2504 port, vid); 2505 } 2506 2507 return 0; 2508 } 2509 2510 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2511 const struct switchdev_obj_port_vlan *vlan, 2512 struct netlink_ext_ack *extack) 2513 { 2514 struct mv88e6xxx_chip *chip = ds->priv; 2515 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2516 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2517 struct mv88e6xxx_port *p = &chip->ports[port]; 2518 bool warn; 2519 u8 member; 2520 int err; 2521 2522 if (!vlan->vid) 2523 return 0; 2524 2525 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2526 if (err) 2527 return err; 2528 2529 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2530 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2531 else if (untagged) 2532 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2533 else 2534 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2535 2536 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2537 * and then the CPU port. Do not warn for duplicates for the CPU port. 2538 */ 2539 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2540 2541 mv88e6xxx_reg_lock(chip); 2542 2543 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2544 if (err) { 2545 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2546 vlan->vid, untagged ? 'u' : 't'); 2547 goto out; 2548 } 2549 2550 if (pvid) { 2551 p->bridge_pvid.vid = vlan->vid; 2552 p->bridge_pvid.valid = true; 2553 2554 err = mv88e6xxx_port_commit_pvid(chip, port); 2555 if (err) 2556 goto out; 2557 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2558 /* The old pvid was reinstalled as a non-pvid VLAN */ 2559 p->bridge_pvid.valid = false; 2560 2561 err = mv88e6xxx_port_commit_pvid(chip, port); 2562 if (err) 2563 goto out; 2564 } 2565 2566 out: 2567 mv88e6xxx_reg_unlock(chip); 2568 2569 return err; 2570 } 2571 2572 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2573 int port, u16 vid) 2574 { 2575 struct mv88e6xxx_vtu_entry vlan; 2576 int i, err; 2577 2578 if (!vid) 2579 return 0; 2580 2581 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2582 if (err) 2583 return err; 2584 2585 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2586 * tell switchdev that this VLAN is likely handled in software. 2587 */ 2588 if (!vlan.valid || 2589 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2590 return -EOPNOTSUPP; 2591 2592 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2593 2594 /* keep the VLAN unless all ports are excluded */ 2595 vlan.valid = false; 2596 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2597 if (vlan.member[i] != 2598 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2599 vlan.valid = true; 2600 break; 2601 } 2602 } 2603 2604 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2605 if (err) 2606 return err; 2607 2608 if (!vlan.valid) { 2609 err = mv88e6xxx_mst_put(chip, vlan.sid); 2610 if (err) 2611 return err; 2612 } 2613 2614 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2615 } 2616 2617 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2618 const struct switchdev_obj_port_vlan *vlan) 2619 { 2620 struct mv88e6xxx_chip *chip = ds->priv; 2621 struct mv88e6xxx_port *p = &chip->ports[port]; 2622 int err = 0; 2623 u16 pvid; 2624 2625 if (!mv88e6xxx_max_vid(chip)) 2626 return -EOPNOTSUPP; 2627 2628 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2629 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2630 * switchdev workqueue to ensure that all FDB entries are deleted 2631 * before we remove the VLAN. 2632 */ 2633 dsa_flush_workqueue(); 2634 2635 mv88e6xxx_reg_lock(chip); 2636 2637 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2638 if (err) 2639 goto unlock; 2640 2641 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2642 if (err) 2643 goto unlock; 2644 2645 if (vlan->vid == pvid) { 2646 p->bridge_pvid.valid = false; 2647 2648 err = mv88e6xxx_port_commit_pvid(chip, port); 2649 if (err) 2650 goto unlock; 2651 } 2652 2653 unlock: 2654 mv88e6xxx_reg_unlock(chip); 2655 2656 return err; 2657 } 2658 2659 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2660 { 2661 struct mv88e6xxx_chip *chip = ds->priv; 2662 struct mv88e6xxx_vtu_entry vlan; 2663 int err; 2664 2665 mv88e6xxx_reg_lock(chip); 2666 2667 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2668 if (err) 2669 goto unlock; 2670 2671 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2672 2673 unlock: 2674 mv88e6xxx_reg_unlock(chip); 2675 2676 return err; 2677 } 2678 2679 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2680 struct dsa_bridge bridge, 2681 const struct switchdev_vlan_msti *msti) 2682 { 2683 struct mv88e6xxx_chip *chip = ds->priv; 2684 struct mv88e6xxx_vtu_entry vlan; 2685 u8 old_sid, new_sid; 2686 int err; 2687 2688 if (!mv88e6xxx_has_stu(chip)) 2689 return -EOPNOTSUPP; 2690 2691 mv88e6xxx_reg_lock(chip); 2692 2693 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2694 if (err) 2695 goto unlock; 2696 2697 if (!vlan.valid) { 2698 err = -EINVAL; 2699 goto unlock; 2700 } 2701 2702 old_sid = vlan.sid; 2703 2704 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2705 if (err) 2706 goto unlock; 2707 2708 if (new_sid != old_sid) { 2709 vlan.sid = new_sid; 2710 2711 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2712 if (err) { 2713 mv88e6xxx_mst_put(chip, new_sid); 2714 goto unlock; 2715 } 2716 } 2717 2718 err = mv88e6xxx_mst_put(chip, old_sid); 2719 2720 unlock: 2721 mv88e6xxx_reg_unlock(chip); 2722 return err; 2723 } 2724 2725 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2726 const unsigned char *addr, u16 vid, 2727 struct dsa_db db) 2728 { 2729 struct mv88e6xxx_chip *chip = ds->priv; 2730 int err; 2731 2732 mv88e6xxx_reg_lock(chip); 2733 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2734 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2735 mv88e6xxx_reg_unlock(chip); 2736 2737 return err; 2738 } 2739 2740 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2741 const unsigned char *addr, u16 vid, 2742 struct dsa_db db) 2743 { 2744 struct mv88e6xxx_chip *chip = ds->priv; 2745 int err; 2746 2747 mv88e6xxx_reg_lock(chip); 2748 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2749 mv88e6xxx_reg_unlock(chip); 2750 2751 return err; 2752 } 2753 2754 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2755 u16 fid, u16 vid, int port, 2756 dsa_fdb_dump_cb_t *cb, void *data) 2757 { 2758 struct mv88e6xxx_atu_entry addr; 2759 bool is_static; 2760 int err; 2761 2762 addr.state = 0; 2763 eth_broadcast_addr(addr.mac); 2764 2765 do { 2766 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2767 if (err) 2768 return err; 2769 2770 if (!addr.state) 2771 break; 2772 2773 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2774 continue; 2775 2776 if (!is_unicast_ether_addr(addr.mac)) 2777 continue; 2778 2779 is_static = (addr.state == 2780 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2781 err = cb(addr.mac, vid, is_static, data); 2782 if (err) 2783 return err; 2784 } while (!is_broadcast_ether_addr(addr.mac)); 2785 2786 return err; 2787 } 2788 2789 struct mv88e6xxx_port_db_dump_vlan_ctx { 2790 int port; 2791 dsa_fdb_dump_cb_t *cb; 2792 void *data; 2793 }; 2794 2795 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2796 const struct mv88e6xxx_vtu_entry *entry, 2797 void *_data) 2798 { 2799 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2800 2801 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2802 ctx->port, ctx->cb, ctx->data); 2803 } 2804 2805 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2806 dsa_fdb_dump_cb_t *cb, void *data) 2807 { 2808 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2809 .port = port, 2810 .cb = cb, 2811 .data = data, 2812 }; 2813 u16 fid; 2814 int err; 2815 2816 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2817 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2818 if (err) 2819 return err; 2820 2821 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2822 if (err) 2823 return err; 2824 2825 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2826 } 2827 2828 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2829 dsa_fdb_dump_cb_t *cb, void *data) 2830 { 2831 struct mv88e6xxx_chip *chip = ds->priv; 2832 int err; 2833 2834 mv88e6xxx_reg_lock(chip); 2835 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2836 mv88e6xxx_reg_unlock(chip); 2837 2838 return err; 2839 } 2840 2841 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2842 struct dsa_bridge bridge) 2843 { 2844 struct dsa_switch *ds = chip->ds; 2845 struct dsa_switch_tree *dst = ds->dst; 2846 struct dsa_port *dp; 2847 int err; 2848 2849 list_for_each_entry(dp, &dst->ports, list) { 2850 if (dsa_port_offloads_bridge(dp, &bridge)) { 2851 if (dp->ds == ds) { 2852 /* This is a local bridge group member, 2853 * remap its Port VLAN Map. 2854 */ 2855 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2856 if (err) 2857 return err; 2858 } else { 2859 /* This is an external bridge group member, 2860 * remap its cross-chip Port VLAN Table entry. 2861 */ 2862 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2863 dp->index); 2864 if (err) 2865 return err; 2866 } 2867 } 2868 } 2869 2870 return 0; 2871 } 2872 2873 /* Treat the software bridge as a virtual single-port switch behind the 2874 * CPU and map in the PVT. First dst->last_switch elements are taken by 2875 * physical switches, so start from beyond that range. 2876 */ 2877 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2878 unsigned int bridge_num) 2879 { 2880 u8 dev = bridge_num + ds->dst->last_switch; 2881 struct mv88e6xxx_chip *chip = ds->priv; 2882 2883 return mv88e6xxx_pvt_map(chip, dev, 0); 2884 } 2885 2886 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2887 struct dsa_bridge bridge, 2888 bool *tx_fwd_offload, 2889 struct netlink_ext_ack *extack) 2890 { 2891 struct mv88e6xxx_chip *chip = ds->priv; 2892 int err; 2893 2894 mv88e6xxx_reg_lock(chip); 2895 2896 err = mv88e6xxx_bridge_map(chip, bridge); 2897 if (err) 2898 goto unlock; 2899 2900 err = mv88e6xxx_port_set_map_da(chip, port, true); 2901 if (err) 2902 goto unlock; 2903 2904 err = mv88e6xxx_port_commit_pvid(chip, port); 2905 if (err) 2906 goto unlock; 2907 2908 if (mv88e6xxx_has_pvt(chip)) { 2909 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2910 if (err) 2911 goto unlock; 2912 2913 *tx_fwd_offload = true; 2914 } 2915 2916 unlock: 2917 mv88e6xxx_reg_unlock(chip); 2918 2919 return err; 2920 } 2921 2922 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2923 struct dsa_bridge bridge) 2924 { 2925 struct mv88e6xxx_chip *chip = ds->priv; 2926 int err; 2927 2928 mv88e6xxx_reg_lock(chip); 2929 2930 if (bridge.tx_fwd_offload && 2931 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2932 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2933 2934 if (mv88e6xxx_bridge_map(chip, bridge) || 2935 mv88e6xxx_port_vlan_map(chip, port)) 2936 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2937 2938 err = mv88e6xxx_port_set_map_da(chip, port, false); 2939 if (err) 2940 dev_err(ds->dev, 2941 "port %d failed to restore map-DA: %pe\n", 2942 port, ERR_PTR(err)); 2943 2944 err = mv88e6xxx_port_commit_pvid(chip, port); 2945 if (err) 2946 dev_err(ds->dev, 2947 "port %d failed to restore standalone pvid: %pe\n", 2948 port, ERR_PTR(err)); 2949 2950 mv88e6xxx_reg_unlock(chip); 2951 } 2952 2953 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2954 int tree_index, int sw_index, 2955 int port, struct dsa_bridge bridge, 2956 struct netlink_ext_ack *extack) 2957 { 2958 struct mv88e6xxx_chip *chip = ds->priv; 2959 int err; 2960 2961 if (tree_index != ds->dst->index) 2962 return 0; 2963 2964 mv88e6xxx_reg_lock(chip); 2965 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2966 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2967 mv88e6xxx_reg_unlock(chip); 2968 2969 return err; 2970 } 2971 2972 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2973 int tree_index, int sw_index, 2974 int port, struct dsa_bridge bridge) 2975 { 2976 struct mv88e6xxx_chip *chip = ds->priv; 2977 2978 if (tree_index != ds->dst->index) 2979 return; 2980 2981 mv88e6xxx_reg_lock(chip); 2982 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2983 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2984 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2985 mv88e6xxx_reg_unlock(chip); 2986 } 2987 2988 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2989 { 2990 if (chip->info->ops->reset) 2991 return chip->info->ops->reset(chip); 2992 2993 return 0; 2994 } 2995 2996 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2997 { 2998 struct gpio_desc *gpiod = chip->reset; 2999 3000 /* If there is a GPIO connected to the reset pin, toggle it */ 3001 if (gpiod) { 3002 gpiod_set_value_cansleep(gpiod, 1); 3003 usleep_range(10000, 20000); 3004 gpiod_set_value_cansleep(gpiod, 0); 3005 usleep_range(10000, 20000); 3006 3007 mv88e6xxx_g1_wait_eeprom_done(chip); 3008 } 3009 } 3010 3011 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3012 { 3013 int i, err; 3014 3015 /* Set all ports to the Disabled state */ 3016 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3017 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3018 if (err) 3019 return err; 3020 } 3021 3022 /* Wait for transmit queues to drain, 3023 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3024 */ 3025 usleep_range(2000, 4000); 3026 3027 return 0; 3028 } 3029 3030 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3031 { 3032 int err; 3033 3034 err = mv88e6xxx_disable_ports(chip); 3035 if (err) 3036 return err; 3037 3038 mv88e6xxx_hardware_reset(chip); 3039 3040 return mv88e6xxx_software_reset(chip); 3041 } 3042 3043 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3044 enum mv88e6xxx_frame_mode frame, 3045 enum mv88e6xxx_egress_mode egress, u16 etype) 3046 { 3047 int err; 3048 3049 if (!chip->info->ops->port_set_frame_mode) 3050 return -EOPNOTSUPP; 3051 3052 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3053 if (err) 3054 return err; 3055 3056 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3057 if (err) 3058 return err; 3059 3060 if (chip->info->ops->port_set_ether_type) 3061 return chip->info->ops->port_set_ether_type(chip, port, etype); 3062 3063 return 0; 3064 } 3065 3066 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3067 { 3068 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3069 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3070 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3071 } 3072 3073 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3074 { 3075 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3076 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3077 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3078 } 3079 3080 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3081 { 3082 return mv88e6xxx_set_port_mode(chip, port, 3083 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3084 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3085 ETH_P_EDSA); 3086 } 3087 3088 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3089 { 3090 if (dsa_is_dsa_port(chip->ds, port)) 3091 return mv88e6xxx_set_port_mode_dsa(chip, port); 3092 3093 if (dsa_is_user_port(chip->ds, port)) 3094 return mv88e6xxx_set_port_mode_normal(chip, port); 3095 3096 /* Setup CPU port mode depending on its supported tag format */ 3097 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3098 return mv88e6xxx_set_port_mode_dsa(chip, port); 3099 3100 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3101 return mv88e6xxx_set_port_mode_edsa(chip, port); 3102 3103 return -EINVAL; 3104 } 3105 3106 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3107 { 3108 bool message = dsa_is_dsa_port(chip->ds, port); 3109 3110 return mv88e6xxx_port_set_message_port(chip, port, message); 3111 } 3112 3113 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3114 { 3115 int err; 3116 3117 if (chip->info->ops->port_set_ucast_flood) { 3118 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3119 if (err) 3120 return err; 3121 } 3122 if (chip->info->ops->port_set_mcast_flood) { 3123 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3124 if (err) 3125 return err; 3126 } 3127 3128 return 0; 3129 } 3130 3131 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3132 { 3133 struct mv88e6xxx_port *mvp = dev_id; 3134 struct mv88e6xxx_chip *chip = mvp->chip; 3135 irqreturn_t ret = IRQ_NONE; 3136 int port = mvp->port; 3137 int lane; 3138 3139 mv88e6xxx_reg_lock(chip); 3140 lane = mv88e6xxx_serdes_get_lane(chip, port); 3141 if (lane >= 0) 3142 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3143 mv88e6xxx_reg_unlock(chip); 3144 3145 return ret; 3146 } 3147 3148 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3149 int lane) 3150 { 3151 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3152 unsigned int irq; 3153 int err; 3154 3155 /* Nothing to request if this SERDES port has no IRQ */ 3156 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3157 if (!irq) 3158 return 0; 3159 3160 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3161 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3162 3163 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3164 mv88e6xxx_reg_unlock(chip); 3165 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3166 IRQF_ONESHOT, dev_id->serdes_irq_name, 3167 dev_id); 3168 mv88e6xxx_reg_lock(chip); 3169 if (err) 3170 return err; 3171 3172 dev_id->serdes_irq = irq; 3173 3174 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3175 } 3176 3177 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3178 int lane) 3179 { 3180 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3181 unsigned int irq = dev_id->serdes_irq; 3182 int err; 3183 3184 /* Nothing to free if no IRQ has been requested */ 3185 if (!irq) 3186 return 0; 3187 3188 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3189 3190 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3191 mv88e6xxx_reg_unlock(chip); 3192 free_irq(irq, dev_id); 3193 mv88e6xxx_reg_lock(chip); 3194 3195 dev_id->serdes_irq = 0; 3196 3197 return err; 3198 } 3199 3200 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3201 bool on) 3202 { 3203 int lane; 3204 int err; 3205 3206 lane = mv88e6xxx_serdes_get_lane(chip, port); 3207 if (lane < 0) 3208 return 0; 3209 3210 if (on) { 3211 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3212 if (err) 3213 return err; 3214 3215 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3216 } else { 3217 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3218 if (err) 3219 return err; 3220 3221 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3222 } 3223 3224 return err; 3225 } 3226 3227 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3228 enum mv88e6xxx_egress_direction direction, 3229 int port) 3230 { 3231 int err; 3232 3233 if (!chip->info->ops->set_egress_port) 3234 return -EOPNOTSUPP; 3235 3236 err = chip->info->ops->set_egress_port(chip, direction, port); 3237 if (err) 3238 return err; 3239 3240 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3241 chip->ingress_dest_port = port; 3242 else 3243 chip->egress_dest_port = port; 3244 3245 return 0; 3246 } 3247 3248 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3249 { 3250 struct dsa_switch *ds = chip->ds; 3251 int upstream_port; 3252 int err; 3253 3254 upstream_port = dsa_upstream_port(ds, port); 3255 if (chip->info->ops->port_set_upstream_port) { 3256 err = chip->info->ops->port_set_upstream_port(chip, port, 3257 upstream_port); 3258 if (err) 3259 return err; 3260 } 3261 3262 if (port == upstream_port) { 3263 if (chip->info->ops->set_cpu_port) { 3264 err = chip->info->ops->set_cpu_port(chip, 3265 upstream_port); 3266 if (err) 3267 return err; 3268 } 3269 3270 err = mv88e6xxx_set_egress_port(chip, 3271 MV88E6XXX_EGRESS_DIR_INGRESS, 3272 upstream_port); 3273 if (err && err != -EOPNOTSUPP) 3274 return err; 3275 3276 err = mv88e6xxx_set_egress_port(chip, 3277 MV88E6XXX_EGRESS_DIR_EGRESS, 3278 upstream_port); 3279 if (err && err != -EOPNOTSUPP) 3280 return err; 3281 } 3282 3283 return 0; 3284 } 3285 3286 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3287 { 3288 struct device_node *phy_handle = NULL; 3289 struct dsa_switch *ds = chip->ds; 3290 phy_interface_t mode; 3291 struct dsa_port *dp; 3292 int tx_amp, speed; 3293 int err; 3294 u16 reg; 3295 3296 chip->ports[port].chip = chip; 3297 chip->ports[port].port = port; 3298 3299 dp = dsa_to_port(ds, port); 3300 3301 /* MAC Forcing register: don't force link, speed, duplex or flow control 3302 * state to any particular values on physical ports, but force the CPU 3303 * port and all DSA ports to their maximum bandwidth and full duplex. 3304 */ 3305 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3306 struct phylink_config pl_config = {}; 3307 unsigned long caps; 3308 3309 chip->info->ops->phylink_get_caps(chip, port, &pl_config); 3310 3311 caps = pl_config.mac_capabilities; 3312 3313 if (chip->info->ops->port_max_speed_mode) 3314 mode = chip->info->ops->port_max_speed_mode(port); 3315 else 3316 mode = PHY_INTERFACE_MODE_NA; 3317 3318 if (caps & MAC_10000FD) 3319 speed = SPEED_10000; 3320 else if (caps & MAC_5000FD) 3321 speed = SPEED_5000; 3322 else if (caps & MAC_2500FD) 3323 speed = SPEED_2500; 3324 else if (caps & MAC_1000) 3325 speed = SPEED_1000; 3326 else if (caps & MAC_100) 3327 speed = SPEED_100; 3328 else 3329 speed = SPEED_10; 3330 3331 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3332 speed, DUPLEX_FULL, 3333 PAUSE_OFF, mode); 3334 } else { 3335 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3336 SPEED_UNFORCED, DUPLEX_UNFORCED, 3337 PAUSE_ON, 3338 PHY_INTERFACE_MODE_NA); 3339 } 3340 if (err) 3341 return err; 3342 3343 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3344 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3345 * tunneling, determine priority by looking at 802.1p and IP 3346 * priority fields (IP prio has precedence), and set STP state 3347 * to Forwarding. 3348 * 3349 * If this is the CPU link, use DSA or EDSA tagging depending 3350 * on which tagging mode was configured. 3351 * 3352 * If this is a link to another switch, use DSA tagging mode. 3353 * 3354 * If this is the upstream port for this switch, enable 3355 * forwarding of unknown unicasts and multicasts. 3356 */ 3357 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3358 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3359 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3360 * by a USER port to the CPU port to allow snooping. 3361 */ 3362 if (dsa_is_user_port(ds, port)) 3363 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3364 3365 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3366 if (err) 3367 return err; 3368 3369 err = mv88e6xxx_setup_port_mode(chip, port); 3370 if (err) 3371 return err; 3372 3373 err = mv88e6xxx_setup_egress_floods(chip, port); 3374 if (err) 3375 return err; 3376 3377 /* Port Control 2: don't force a good FCS, set the MTU size to 3378 * 10222 bytes, disable 802.1q tags checking, don't discard 3379 * tagged or untagged frames on this port, skip destination 3380 * address lookup on user ports, disable ARP mirroring and don't 3381 * send a copy of all transmitted/received frames on this port 3382 * to the CPU. 3383 */ 3384 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3385 if (err) 3386 return err; 3387 3388 err = mv88e6xxx_setup_upstream_port(chip, port); 3389 if (err) 3390 return err; 3391 3392 /* On chips that support it, set all downstream DSA ports' 3393 * VLAN policy to TRAP. In combination with loading 3394 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3395 * provides a better isolation barrier between standalone 3396 * ports, as the ATU is bypassed on any intermediate switches 3397 * between the incoming port and the CPU. 3398 */ 3399 if (dsa_is_downstream_port(ds, port) && 3400 chip->info->ops->port_set_policy) { 3401 err = chip->info->ops->port_set_policy(chip, port, 3402 MV88E6XXX_POLICY_MAPPING_VTU, 3403 MV88E6XXX_POLICY_ACTION_TRAP); 3404 if (err) 3405 return err; 3406 } 3407 3408 /* User ports start out in standalone mode and 802.1Q is 3409 * therefore disabled. On DSA ports, all valid VIDs are always 3410 * loaded in the VTU - therefore, enable 802.1Q in order to take 3411 * advantage of VLAN policy on chips that supports it. 3412 */ 3413 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3414 dsa_is_user_port(ds, port) ? 3415 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3416 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3417 if (err) 3418 return err; 3419 3420 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3421 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3422 * the first free FID. This will be used as the private PVID for 3423 * unbridged ports. Shared (DSA and CPU) ports must also be 3424 * members of this VID, in order to trap all frames assigned to 3425 * it to the CPU. 3426 */ 3427 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3428 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3429 false); 3430 if (err) 3431 return err; 3432 3433 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3434 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3435 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3436 * as the private PVID on ports under a VLAN-unaware bridge. 3437 * Shared (DSA and CPU) ports must also be members of it, to translate 3438 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3439 * relying on their port default FID. 3440 */ 3441 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3442 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3443 false); 3444 if (err) 3445 return err; 3446 3447 if (chip->info->ops->port_set_jumbo_size) { 3448 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3449 if (err) 3450 return err; 3451 } 3452 3453 /* Port Association Vector: disable automatic address learning 3454 * on all user ports since they start out in standalone 3455 * mode. When joining a bridge, learning will be configured to 3456 * match the bridge port settings. Enable learning on all 3457 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3458 * learning process. 3459 * 3460 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3461 * and RefreshLocked. I.e. setup standard automatic learning. 3462 */ 3463 if (dsa_is_user_port(ds, port)) 3464 reg = 0; 3465 else 3466 reg = 1 << port; 3467 3468 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3469 reg); 3470 if (err) 3471 return err; 3472 3473 /* Egress rate control 2: disable egress rate control. */ 3474 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3475 0x0000); 3476 if (err) 3477 return err; 3478 3479 if (chip->info->ops->port_pause_limit) { 3480 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3481 if (err) 3482 return err; 3483 } 3484 3485 if (chip->info->ops->port_disable_learn_limit) { 3486 err = chip->info->ops->port_disable_learn_limit(chip, port); 3487 if (err) 3488 return err; 3489 } 3490 3491 if (chip->info->ops->port_disable_pri_override) { 3492 err = chip->info->ops->port_disable_pri_override(chip, port); 3493 if (err) 3494 return err; 3495 } 3496 3497 if (chip->info->ops->port_tag_remap) { 3498 err = chip->info->ops->port_tag_remap(chip, port); 3499 if (err) 3500 return err; 3501 } 3502 3503 if (chip->info->ops->port_egress_rate_limiting) { 3504 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3505 if (err) 3506 return err; 3507 } 3508 3509 if (chip->info->ops->port_setup_message_port) { 3510 err = chip->info->ops->port_setup_message_port(chip, port); 3511 if (err) 3512 return err; 3513 } 3514 3515 if (chip->info->ops->serdes_set_tx_amplitude) { 3516 if (dp) 3517 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3518 3519 if (phy_handle && !of_property_read_u32(phy_handle, 3520 "tx-p2p-microvolt", 3521 &tx_amp)) 3522 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3523 port, tx_amp); 3524 if (phy_handle) { 3525 of_node_put(phy_handle); 3526 if (err) 3527 return err; 3528 } 3529 } 3530 3531 /* Port based VLAN map: give each port the same default address 3532 * database, and allow bidirectional communication between the 3533 * CPU and DSA port(s), and the other ports. 3534 */ 3535 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3536 if (err) 3537 return err; 3538 3539 err = mv88e6xxx_port_vlan_map(chip, port); 3540 if (err) 3541 return err; 3542 3543 /* Default VLAN ID and priority: don't set a default VLAN 3544 * ID, and set the default packet priority to zero. 3545 */ 3546 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3547 } 3548 3549 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3550 { 3551 struct mv88e6xxx_chip *chip = ds->priv; 3552 3553 if (chip->info->ops->port_set_jumbo_size) 3554 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3555 else if (chip->info->ops->set_max_frame_size) 3556 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3557 return ETH_DATA_LEN; 3558 } 3559 3560 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3561 { 3562 struct mv88e6xxx_chip *chip = ds->priv; 3563 int ret = 0; 3564 3565 /* For families where we don't know how to alter the MTU, 3566 * just accept any value up to ETH_DATA_LEN 3567 */ 3568 if (!chip->info->ops->port_set_jumbo_size && 3569 !chip->info->ops->set_max_frame_size) { 3570 if (new_mtu > ETH_DATA_LEN) 3571 return -EINVAL; 3572 3573 return 0; 3574 } 3575 3576 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3577 new_mtu += EDSA_HLEN; 3578 3579 mv88e6xxx_reg_lock(chip); 3580 if (chip->info->ops->port_set_jumbo_size) 3581 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3582 else if (chip->info->ops->set_max_frame_size) 3583 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3584 mv88e6xxx_reg_unlock(chip); 3585 3586 return ret; 3587 } 3588 3589 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3590 struct phy_device *phydev) 3591 { 3592 struct mv88e6xxx_chip *chip = ds->priv; 3593 int err; 3594 3595 mv88e6xxx_reg_lock(chip); 3596 err = mv88e6xxx_serdes_power(chip, port, true); 3597 mv88e6xxx_reg_unlock(chip); 3598 3599 return err; 3600 } 3601 3602 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3603 { 3604 struct mv88e6xxx_chip *chip = ds->priv; 3605 3606 mv88e6xxx_reg_lock(chip); 3607 if (mv88e6xxx_serdes_power(chip, port, false)) 3608 dev_err(chip->dev, "failed to power off SERDES\n"); 3609 mv88e6xxx_reg_unlock(chip); 3610 } 3611 3612 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3613 unsigned int ageing_time) 3614 { 3615 struct mv88e6xxx_chip *chip = ds->priv; 3616 int err; 3617 3618 mv88e6xxx_reg_lock(chip); 3619 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3620 mv88e6xxx_reg_unlock(chip); 3621 3622 return err; 3623 } 3624 3625 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3626 { 3627 int err; 3628 3629 /* Initialize the statistics unit */ 3630 if (chip->info->ops->stats_set_histogram) { 3631 err = chip->info->ops->stats_set_histogram(chip); 3632 if (err) 3633 return err; 3634 } 3635 3636 return mv88e6xxx_g1_stats_clear(chip); 3637 } 3638 3639 /* Check if the errata has already been applied. */ 3640 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3641 { 3642 int port; 3643 int err; 3644 u16 val; 3645 3646 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3647 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3648 if (err) { 3649 dev_err(chip->dev, 3650 "Error reading hidden register: %d\n", err); 3651 return false; 3652 } 3653 if (val != 0x01c0) 3654 return false; 3655 } 3656 3657 return true; 3658 } 3659 3660 /* The 6390 copper ports have an errata which require poking magic 3661 * values into undocumented hidden registers and then performing a 3662 * software reset. 3663 */ 3664 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3665 { 3666 int port; 3667 int err; 3668 3669 if (mv88e6390_setup_errata_applied(chip)) 3670 return 0; 3671 3672 /* Set the ports into blocking mode */ 3673 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3674 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3675 if (err) 3676 return err; 3677 } 3678 3679 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3680 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3681 if (err) 3682 return err; 3683 } 3684 3685 return mv88e6xxx_software_reset(chip); 3686 } 3687 3688 /* prod_id for switch families which do not have a PHY model number */ 3689 static const u16 family_prod_id_table[] = { 3690 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3691 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3692 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3693 }; 3694 3695 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3696 { 3697 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3698 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3699 u16 prod_id; 3700 u16 val; 3701 int err; 3702 3703 if (!chip->info->ops->phy_read) 3704 return -EOPNOTSUPP; 3705 3706 mv88e6xxx_reg_lock(chip); 3707 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3708 mv88e6xxx_reg_unlock(chip); 3709 3710 /* Some internal PHYs don't have a model number. */ 3711 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3712 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3713 prod_id = family_prod_id_table[chip->info->family]; 3714 if (prod_id) 3715 val |= prod_id >> 4; 3716 } 3717 3718 return err ? err : val; 3719 } 3720 3721 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3722 int reg) 3723 { 3724 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3725 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3726 u16 val; 3727 int err; 3728 3729 if (!chip->info->ops->phy_read_c45) 3730 return -EOPNOTSUPP; 3731 3732 mv88e6xxx_reg_lock(chip); 3733 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3734 mv88e6xxx_reg_unlock(chip); 3735 3736 return err ? err : val; 3737 } 3738 3739 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3740 { 3741 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3742 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3743 int err; 3744 3745 if (!chip->info->ops->phy_write) 3746 return -EOPNOTSUPP; 3747 3748 mv88e6xxx_reg_lock(chip); 3749 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3750 mv88e6xxx_reg_unlock(chip); 3751 3752 return err; 3753 } 3754 3755 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3756 int reg, u16 val) 3757 { 3758 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3759 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3760 int err; 3761 3762 if (!chip->info->ops->phy_write_c45) 3763 return -EOPNOTSUPP; 3764 3765 mv88e6xxx_reg_lock(chip); 3766 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3767 mv88e6xxx_reg_unlock(chip); 3768 3769 return err; 3770 } 3771 3772 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3773 struct device_node *np, 3774 bool external) 3775 { 3776 static int index; 3777 struct mv88e6xxx_mdio_bus *mdio_bus; 3778 struct mii_bus *bus; 3779 int err; 3780 3781 if (external) { 3782 mv88e6xxx_reg_lock(chip); 3783 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3784 mv88e6xxx_reg_unlock(chip); 3785 3786 if (err) 3787 return err; 3788 } 3789 3790 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3791 if (!bus) 3792 return -ENOMEM; 3793 3794 mdio_bus = bus->priv; 3795 mdio_bus->bus = bus; 3796 mdio_bus->chip = chip; 3797 INIT_LIST_HEAD(&mdio_bus->list); 3798 mdio_bus->external = external; 3799 3800 if (np) { 3801 bus->name = np->full_name; 3802 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3803 } else { 3804 bus->name = "mv88e6xxx SMI"; 3805 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3806 } 3807 3808 bus->read = mv88e6xxx_mdio_read; 3809 bus->write = mv88e6xxx_mdio_write; 3810 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3811 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3812 bus->parent = chip->dev; 3813 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3814 mv88e6xxx_num_ports(chip) - 1, 3815 chip->info->phy_base_addr); 3816 3817 if (!external) { 3818 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3819 if (err) 3820 goto out; 3821 } 3822 3823 err = of_mdiobus_register(bus, np); 3824 if (err) { 3825 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3826 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3827 goto out; 3828 } 3829 3830 if (external) 3831 list_add_tail(&mdio_bus->list, &chip->mdios); 3832 else 3833 list_add(&mdio_bus->list, &chip->mdios); 3834 3835 return 0; 3836 3837 out: 3838 mdiobus_free(bus); 3839 return err; 3840 } 3841 3842 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3843 3844 { 3845 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3846 struct mii_bus *bus; 3847 3848 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3849 bus = mdio_bus->bus; 3850 3851 if (!mdio_bus->external) 3852 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3853 3854 mdiobus_unregister(bus); 3855 mdiobus_free(bus); 3856 } 3857 } 3858 3859 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3860 { 3861 struct device_node *np = chip->dev->of_node; 3862 struct device_node *child; 3863 int err; 3864 3865 /* Always register one mdio bus for the internal/default mdio 3866 * bus. This maybe represented in the device tree, but is 3867 * optional. 3868 */ 3869 child = of_get_child_by_name(np, "mdio"); 3870 err = mv88e6xxx_mdio_register(chip, child, false); 3871 of_node_put(child); 3872 if (err) 3873 return err; 3874 3875 /* Walk the device tree, and see if there are any other nodes 3876 * which say they are compatible with the external mdio 3877 * bus. 3878 */ 3879 for_each_available_child_of_node(np, child) { 3880 if (of_device_is_compatible( 3881 child, "marvell,mv88e6xxx-mdio-external")) { 3882 err = mv88e6xxx_mdio_register(chip, child, true); 3883 if (err) { 3884 mv88e6xxx_mdios_unregister(chip); 3885 of_node_put(child); 3886 return err; 3887 } 3888 } 3889 } 3890 3891 return 0; 3892 } 3893 3894 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3895 { 3896 struct mv88e6xxx_chip *chip = ds->priv; 3897 3898 mv88e6xxx_teardown_devlink_params(ds); 3899 dsa_devlink_resources_unregister(ds); 3900 mv88e6xxx_teardown_devlink_regions_global(ds); 3901 mv88e6xxx_mdios_unregister(chip); 3902 } 3903 3904 static int mv88e6xxx_setup(struct dsa_switch *ds) 3905 { 3906 struct mv88e6xxx_chip *chip = ds->priv; 3907 u8 cmode; 3908 int err; 3909 int i; 3910 3911 err = mv88e6xxx_mdios_register(chip); 3912 if (err) 3913 return err; 3914 3915 chip->ds = ds; 3916 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3917 3918 /* Since virtual bridges are mapped in the PVT, the number we support 3919 * depends on the physical switch topology. We need to let DSA figure 3920 * that out and therefore we cannot set this at dsa_register_switch() 3921 * time. 3922 */ 3923 if (mv88e6xxx_has_pvt(chip)) 3924 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3925 ds->dst->last_switch - 1; 3926 3927 mv88e6xxx_reg_lock(chip); 3928 3929 if (chip->info->ops->setup_errata) { 3930 err = chip->info->ops->setup_errata(chip); 3931 if (err) 3932 goto unlock; 3933 } 3934 3935 /* Cache the cmode of each port. */ 3936 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3937 if (chip->info->ops->port_get_cmode) { 3938 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3939 if (err) 3940 goto unlock; 3941 3942 chip->ports[i].cmode = cmode; 3943 } 3944 } 3945 3946 err = mv88e6xxx_vtu_setup(chip); 3947 if (err) 3948 goto unlock; 3949 3950 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3951 * VTU, thereby also flushing the STU). 3952 */ 3953 err = mv88e6xxx_stu_setup(chip); 3954 if (err) 3955 goto unlock; 3956 3957 /* Setup Switch Port Registers */ 3958 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3959 if (dsa_is_unused_port(ds, i)) 3960 continue; 3961 3962 /* Prevent the use of an invalid port. */ 3963 if (mv88e6xxx_is_invalid_port(chip, i)) { 3964 dev_err(chip->dev, "port %d is invalid\n", i); 3965 err = -EINVAL; 3966 goto unlock; 3967 } 3968 3969 err = mv88e6xxx_setup_port(chip, i); 3970 if (err) 3971 goto unlock; 3972 } 3973 3974 err = mv88e6xxx_irl_setup(chip); 3975 if (err) 3976 goto unlock; 3977 3978 err = mv88e6xxx_mac_setup(chip); 3979 if (err) 3980 goto unlock; 3981 3982 err = mv88e6xxx_phy_setup(chip); 3983 if (err) 3984 goto unlock; 3985 3986 err = mv88e6xxx_pvt_setup(chip); 3987 if (err) 3988 goto unlock; 3989 3990 err = mv88e6xxx_atu_setup(chip); 3991 if (err) 3992 goto unlock; 3993 3994 err = mv88e6xxx_broadcast_setup(chip, 0); 3995 if (err) 3996 goto unlock; 3997 3998 err = mv88e6xxx_pot_setup(chip); 3999 if (err) 4000 goto unlock; 4001 4002 err = mv88e6xxx_rmu_setup(chip); 4003 if (err) 4004 goto unlock; 4005 4006 err = mv88e6xxx_rsvd2cpu_setup(chip); 4007 if (err) 4008 goto unlock; 4009 4010 err = mv88e6xxx_trunk_setup(chip); 4011 if (err) 4012 goto unlock; 4013 4014 err = mv88e6xxx_devmap_setup(chip); 4015 if (err) 4016 goto unlock; 4017 4018 err = mv88e6xxx_pri_setup(chip); 4019 if (err) 4020 goto unlock; 4021 4022 /* Setup PTP Hardware Clock and timestamping */ 4023 if (chip->info->ptp_support) { 4024 err = mv88e6xxx_ptp_setup(chip); 4025 if (err) 4026 goto unlock; 4027 4028 err = mv88e6xxx_hwtstamp_setup(chip); 4029 if (err) 4030 goto unlock; 4031 } 4032 4033 err = mv88e6xxx_stats_setup(chip); 4034 if (err) 4035 goto unlock; 4036 4037 unlock: 4038 mv88e6xxx_reg_unlock(chip); 4039 4040 if (err) 4041 goto out_mdios; 4042 4043 /* Have to be called without holding the register lock, since 4044 * they take the devlink lock, and we later take the locks in 4045 * the reverse order when getting/setting parameters or 4046 * resource occupancy. 4047 */ 4048 err = mv88e6xxx_setup_devlink_resources(ds); 4049 if (err) 4050 goto out_mdios; 4051 4052 err = mv88e6xxx_setup_devlink_params(ds); 4053 if (err) 4054 goto out_resources; 4055 4056 err = mv88e6xxx_setup_devlink_regions_global(ds); 4057 if (err) 4058 goto out_params; 4059 4060 return 0; 4061 4062 out_params: 4063 mv88e6xxx_teardown_devlink_params(ds); 4064 out_resources: 4065 dsa_devlink_resources_unregister(ds); 4066 out_mdios: 4067 mv88e6xxx_mdios_unregister(chip); 4068 4069 return err; 4070 } 4071 4072 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4073 { 4074 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4075 } 4076 4077 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4078 { 4079 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4080 } 4081 4082 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4083 { 4084 struct mv88e6xxx_chip *chip = ds->priv; 4085 4086 return chip->eeprom_len; 4087 } 4088 4089 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4090 struct ethtool_eeprom *eeprom, u8 *data) 4091 { 4092 struct mv88e6xxx_chip *chip = ds->priv; 4093 int err; 4094 4095 if (!chip->info->ops->get_eeprom) 4096 return -EOPNOTSUPP; 4097 4098 mv88e6xxx_reg_lock(chip); 4099 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4100 mv88e6xxx_reg_unlock(chip); 4101 4102 if (err) 4103 return err; 4104 4105 eeprom->magic = 0xc3ec4951; 4106 4107 return 0; 4108 } 4109 4110 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4111 struct ethtool_eeprom *eeprom, u8 *data) 4112 { 4113 struct mv88e6xxx_chip *chip = ds->priv; 4114 int err; 4115 4116 if (!chip->info->ops->set_eeprom) 4117 return -EOPNOTSUPP; 4118 4119 if (eeprom->magic != 0xc3ec4951) 4120 return -EINVAL; 4121 4122 mv88e6xxx_reg_lock(chip); 4123 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4124 mv88e6xxx_reg_unlock(chip); 4125 4126 return err; 4127 } 4128 4129 static const struct mv88e6xxx_ops mv88e6085_ops = { 4130 /* MV88E6XXX_FAMILY_6097 */ 4131 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4132 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4133 .irl_init_all = mv88e6352_g2_irl_init_all, 4134 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4135 .phy_read = mv88e6185_phy_ppu_read, 4136 .phy_write = mv88e6185_phy_ppu_write, 4137 .port_set_link = mv88e6xxx_port_set_link, 4138 .port_sync_link = mv88e6xxx_port_sync_link, 4139 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4140 .port_tag_remap = mv88e6095_port_tag_remap, 4141 .port_set_policy = mv88e6352_port_set_policy, 4142 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4143 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4144 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4145 .port_set_ether_type = mv88e6351_port_set_ether_type, 4146 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4147 .port_pause_limit = mv88e6097_port_pause_limit, 4148 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4149 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4150 .port_get_cmode = mv88e6185_port_get_cmode, 4151 .port_setup_message_port = mv88e6xxx_setup_message_port, 4152 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4153 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4154 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4155 .stats_get_strings = mv88e6095_stats_get_strings, 4156 .stats_get_stats = mv88e6095_stats_get_stats, 4157 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4158 .set_egress_port = mv88e6095_g1_set_egress_port, 4159 .watchdog_ops = &mv88e6097_watchdog_ops, 4160 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4161 .pot_clear = mv88e6xxx_g2_pot_clear, 4162 .ppu_enable = mv88e6185_g1_ppu_enable, 4163 .ppu_disable = mv88e6185_g1_ppu_disable, 4164 .reset = mv88e6185_g1_reset, 4165 .rmu_disable = mv88e6085_g1_rmu_disable, 4166 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4167 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4168 .stu_getnext = mv88e6352_g1_stu_getnext, 4169 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4170 .phylink_get_caps = mv88e6185_phylink_get_caps, 4171 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4172 }; 4173 4174 static const struct mv88e6xxx_ops mv88e6095_ops = { 4175 /* MV88E6XXX_FAMILY_6095 */ 4176 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4177 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4178 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4179 .phy_read = mv88e6185_phy_ppu_read, 4180 .phy_write = mv88e6185_phy_ppu_write, 4181 .port_set_link = mv88e6xxx_port_set_link, 4182 .port_sync_link = mv88e6185_port_sync_link, 4183 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4184 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4185 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4186 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4187 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4188 .port_get_cmode = mv88e6185_port_get_cmode, 4189 .port_setup_message_port = mv88e6xxx_setup_message_port, 4190 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4191 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4192 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4193 .stats_get_strings = mv88e6095_stats_get_strings, 4194 .stats_get_stats = mv88e6095_stats_get_stats, 4195 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4196 .serdes_power = mv88e6185_serdes_power, 4197 .serdes_get_lane = mv88e6185_serdes_get_lane, 4198 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4199 .ppu_enable = mv88e6185_g1_ppu_enable, 4200 .ppu_disable = mv88e6185_g1_ppu_disable, 4201 .reset = mv88e6185_g1_reset, 4202 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4203 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4204 .phylink_get_caps = mv88e6095_phylink_get_caps, 4205 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4206 }; 4207 4208 static const struct mv88e6xxx_ops mv88e6097_ops = { 4209 /* MV88E6XXX_FAMILY_6097 */ 4210 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4211 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4212 .irl_init_all = mv88e6352_g2_irl_init_all, 4213 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4214 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4215 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4216 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4217 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4218 .port_set_link = mv88e6xxx_port_set_link, 4219 .port_sync_link = mv88e6185_port_sync_link, 4220 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4221 .port_tag_remap = mv88e6095_port_tag_remap, 4222 .port_set_policy = mv88e6352_port_set_policy, 4223 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4224 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4225 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4226 .port_set_ether_type = mv88e6351_port_set_ether_type, 4227 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4228 .port_pause_limit = mv88e6097_port_pause_limit, 4229 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4230 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4231 .port_get_cmode = mv88e6185_port_get_cmode, 4232 .port_setup_message_port = mv88e6xxx_setup_message_port, 4233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4234 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4235 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4236 .stats_get_strings = mv88e6095_stats_get_strings, 4237 .stats_get_stats = mv88e6095_stats_get_stats, 4238 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4239 .set_egress_port = mv88e6095_g1_set_egress_port, 4240 .watchdog_ops = &mv88e6097_watchdog_ops, 4241 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4242 .serdes_power = mv88e6185_serdes_power, 4243 .serdes_get_lane = mv88e6185_serdes_get_lane, 4244 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4245 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4246 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4247 .serdes_irq_status = mv88e6097_serdes_irq_status, 4248 .pot_clear = mv88e6xxx_g2_pot_clear, 4249 .reset = mv88e6352_g1_reset, 4250 .rmu_disable = mv88e6085_g1_rmu_disable, 4251 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4252 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4253 .phylink_get_caps = mv88e6095_phylink_get_caps, 4254 .stu_getnext = mv88e6352_g1_stu_getnext, 4255 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4256 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4257 }; 4258 4259 static const struct mv88e6xxx_ops mv88e6123_ops = { 4260 /* MV88E6XXX_FAMILY_6165 */ 4261 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4262 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4263 .irl_init_all = mv88e6352_g2_irl_init_all, 4264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4265 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4266 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4267 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4268 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4269 .port_set_link = mv88e6xxx_port_set_link, 4270 .port_sync_link = mv88e6xxx_port_sync_link, 4271 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4272 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4273 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4274 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4275 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4276 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4277 .port_get_cmode = mv88e6185_port_get_cmode, 4278 .port_setup_message_port = mv88e6xxx_setup_message_port, 4279 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4280 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4281 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4282 .stats_get_strings = mv88e6095_stats_get_strings, 4283 .stats_get_stats = mv88e6095_stats_get_stats, 4284 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4285 .set_egress_port = mv88e6095_g1_set_egress_port, 4286 .watchdog_ops = &mv88e6097_watchdog_ops, 4287 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4288 .pot_clear = mv88e6xxx_g2_pot_clear, 4289 .reset = mv88e6352_g1_reset, 4290 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4291 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4292 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4293 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4294 .stu_getnext = mv88e6352_g1_stu_getnext, 4295 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4296 .phylink_get_caps = mv88e6185_phylink_get_caps, 4297 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4298 }; 4299 4300 static const struct mv88e6xxx_ops mv88e6131_ops = { 4301 /* MV88E6XXX_FAMILY_6185 */ 4302 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4303 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4304 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4305 .phy_read = mv88e6185_phy_ppu_read, 4306 .phy_write = mv88e6185_phy_ppu_write, 4307 .port_set_link = mv88e6xxx_port_set_link, 4308 .port_sync_link = mv88e6xxx_port_sync_link, 4309 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4310 .port_tag_remap = mv88e6095_port_tag_remap, 4311 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4312 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4313 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4314 .port_set_ether_type = mv88e6351_port_set_ether_type, 4315 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4316 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4317 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4318 .port_pause_limit = mv88e6097_port_pause_limit, 4319 .port_set_pause = mv88e6185_port_set_pause, 4320 .port_get_cmode = mv88e6185_port_get_cmode, 4321 .port_setup_message_port = mv88e6xxx_setup_message_port, 4322 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4323 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4324 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4325 .stats_get_strings = mv88e6095_stats_get_strings, 4326 .stats_get_stats = mv88e6095_stats_get_stats, 4327 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4328 .set_egress_port = mv88e6095_g1_set_egress_port, 4329 .watchdog_ops = &mv88e6097_watchdog_ops, 4330 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4331 .ppu_enable = mv88e6185_g1_ppu_enable, 4332 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4333 .ppu_disable = mv88e6185_g1_ppu_disable, 4334 .reset = mv88e6185_g1_reset, 4335 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4336 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4337 .phylink_get_caps = mv88e6185_phylink_get_caps, 4338 }; 4339 4340 static const struct mv88e6xxx_ops mv88e6141_ops = { 4341 /* MV88E6XXX_FAMILY_6341 */ 4342 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4343 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4344 .irl_init_all = mv88e6352_g2_irl_init_all, 4345 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4346 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4347 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4348 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4349 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4350 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4351 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4352 .port_set_link = mv88e6xxx_port_set_link, 4353 .port_sync_link = mv88e6xxx_port_sync_link, 4354 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4355 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4356 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4357 .port_tag_remap = mv88e6095_port_tag_remap, 4358 .port_set_policy = mv88e6352_port_set_policy, 4359 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4360 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4361 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4362 .port_set_ether_type = mv88e6351_port_set_ether_type, 4363 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4364 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4365 .port_pause_limit = mv88e6097_port_pause_limit, 4366 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4367 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4368 .port_get_cmode = mv88e6352_port_get_cmode, 4369 .port_set_cmode = mv88e6341_port_set_cmode, 4370 .port_setup_message_port = mv88e6xxx_setup_message_port, 4371 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4372 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4373 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4374 .stats_get_strings = mv88e6320_stats_get_strings, 4375 .stats_get_stats = mv88e6390_stats_get_stats, 4376 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4377 .set_egress_port = mv88e6390_g1_set_egress_port, 4378 .watchdog_ops = &mv88e6390_watchdog_ops, 4379 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4380 .pot_clear = mv88e6xxx_g2_pot_clear, 4381 .reset = mv88e6352_g1_reset, 4382 .rmu_disable = mv88e6390_g1_rmu_disable, 4383 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4384 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4385 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4386 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4387 .stu_getnext = mv88e6352_g1_stu_getnext, 4388 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4389 .serdes_power = mv88e6390_serdes_power, 4390 .serdes_get_lane = mv88e6341_serdes_get_lane, 4391 /* Check status register pause & lpa register */ 4392 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4393 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4394 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4395 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4396 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4397 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4398 .serdes_irq_status = mv88e6390_serdes_irq_status, 4399 .gpio_ops = &mv88e6352_gpio_ops, 4400 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4401 .serdes_get_strings = mv88e6390_serdes_get_strings, 4402 .serdes_get_stats = mv88e6390_serdes_get_stats, 4403 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4404 .serdes_get_regs = mv88e6390_serdes_get_regs, 4405 .phylink_get_caps = mv88e6341_phylink_get_caps, 4406 }; 4407 4408 static const struct mv88e6xxx_ops mv88e6161_ops = { 4409 /* MV88E6XXX_FAMILY_6165 */ 4410 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4411 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4412 .irl_init_all = mv88e6352_g2_irl_init_all, 4413 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4414 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4415 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4416 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4417 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4418 .port_set_link = mv88e6xxx_port_set_link, 4419 .port_sync_link = mv88e6xxx_port_sync_link, 4420 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4421 .port_tag_remap = mv88e6095_port_tag_remap, 4422 .port_set_policy = mv88e6352_port_set_policy, 4423 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4424 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4425 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4426 .port_set_ether_type = mv88e6351_port_set_ether_type, 4427 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4428 .port_pause_limit = mv88e6097_port_pause_limit, 4429 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4430 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4431 .port_get_cmode = mv88e6185_port_get_cmode, 4432 .port_setup_message_port = mv88e6xxx_setup_message_port, 4433 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4434 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4435 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4436 .stats_get_strings = mv88e6095_stats_get_strings, 4437 .stats_get_stats = mv88e6095_stats_get_stats, 4438 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4439 .set_egress_port = mv88e6095_g1_set_egress_port, 4440 .watchdog_ops = &mv88e6097_watchdog_ops, 4441 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4442 .pot_clear = mv88e6xxx_g2_pot_clear, 4443 .reset = mv88e6352_g1_reset, 4444 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4445 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4446 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4447 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4448 .stu_getnext = mv88e6352_g1_stu_getnext, 4449 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4450 .avb_ops = &mv88e6165_avb_ops, 4451 .ptp_ops = &mv88e6165_ptp_ops, 4452 .phylink_get_caps = mv88e6185_phylink_get_caps, 4453 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4454 }; 4455 4456 static const struct mv88e6xxx_ops mv88e6165_ops = { 4457 /* MV88E6XXX_FAMILY_6165 */ 4458 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4459 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4460 .irl_init_all = mv88e6352_g2_irl_init_all, 4461 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4462 .phy_read = mv88e6165_phy_read, 4463 .phy_write = mv88e6165_phy_write, 4464 .port_set_link = mv88e6xxx_port_set_link, 4465 .port_sync_link = mv88e6xxx_port_sync_link, 4466 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4467 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4468 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4469 .port_get_cmode = mv88e6185_port_get_cmode, 4470 .port_setup_message_port = mv88e6xxx_setup_message_port, 4471 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4472 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4473 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4474 .stats_get_strings = mv88e6095_stats_get_strings, 4475 .stats_get_stats = mv88e6095_stats_get_stats, 4476 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4477 .set_egress_port = mv88e6095_g1_set_egress_port, 4478 .watchdog_ops = &mv88e6097_watchdog_ops, 4479 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4480 .pot_clear = mv88e6xxx_g2_pot_clear, 4481 .reset = mv88e6352_g1_reset, 4482 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4483 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4484 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4485 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4486 .stu_getnext = mv88e6352_g1_stu_getnext, 4487 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4488 .avb_ops = &mv88e6165_avb_ops, 4489 .ptp_ops = &mv88e6165_ptp_ops, 4490 .phylink_get_caps = mv88e6185_phylink_get_caps, 4491 }; 4492 4493 static const struct mv88e6xxx_ops mv88e6171_ops = { 4494 /* MV88E6XXX_FAMILY_6351 */ 4495 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4496 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4497 .irl_init_all = mv88e6352_g2_irl_init_all, 4498 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4499 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4500 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4501 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4502 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4503 .port_set_link = mv88e6xxx_port_set_link, 4504 .port_sync_link = mv88e6xxx_port_sync_link, 4505 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4506 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4507 .port_tag_remap = mv88e6095_port_tag_remap, 4508 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4509 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4510 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4511 .port_set_ether_type = mv88e6351_port_set_ether_type, 4512 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4513 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4514 .port_pause_limit = mv88e6097_port_pause_limit, 4515 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4516 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4517 .port_get_cmode = mv88e6352_port_get_cmode, 4518 .port_setup_message_port = mv88e6xxx_setup_message_port, 4519 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4520 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4521 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4522 .stats_get_strings = mv88e6095_stats_get_strings, 4523 .stats_get_stats = mv88e6095_stats_get_stats, 4524 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4525 .set_egress_port = mv88e6095_g1_set_egress_port, 4526 .watchdog_ops = &mv88e6097_watchdog_ops, 4527 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4528 .pot_clear = mv88e6xxx_g2_pot_clear, 4529 .reset = mv88e6352_g1_reset, 4530 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4531 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4532 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4533 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4534 .stu_getnext = mv88e6352_g1_stu_getnext, 4535 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4536 .phylink_get_caps = mv88e6185_phylink_get_caps, 4537 }; 4538 4539 static const struct mv88e6xxx_ops mv88e6172_ops = { 4540 /* MV88E6XXX_FAMILY_6352 */ 4541 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4542 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4543 .irl_init_all = mv88e6352_g2_irl_init_all, 4544 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4545 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4546 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4547 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4548 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4549 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4550 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4551 .port_set_link = mv88e6xxx_port_set_link, 4552 .port_sync_link = mv88e6xxx_port_sync_link, 4553 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4554 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4555 .port_tag_remap = mv88e6095_port_tag_remap, 4556 .port_set_policy = mv88e6352_port_set_policy, 4557 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4558 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4559 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4560 .port_set_ether_type = mv88e6351_port_set_ether_type, 4561 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4562 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4563 .port_pause_limit = mv88e6097_port_pause_limit, 4564 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4565 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4566 .port_get_cmode = mv88e6352_port_get_cmode, 4567 .port_setup_message_port = mv88e6xxx_setup_message_port, 4568 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4569 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4570 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4571 .stats_get_strings = mv88e6095_stats_get_strings, 4572 .stats_get_stats = mv88e6095_stats_get_stats, 4573 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4574 .set_egress_port = mv88e6095_g1_set_egress_port, 4575 .watchdog_ops = &mv88e6097_watchdog_ops, 4576 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4577 .pot_clear = mv88e6xxx_g2_pot_clear, 4578 .reset = mv88e6352_g1_reset, 4579 .rmu_disable = mv88e6352_g1_rmu_disable, 4580 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4581 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4582 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4583 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4584 .stu_getnext = mv88e6352_g1_stu_getnext, 4585 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4586 .serdes_get_lane = mv88e6352_serdes_get_lane, 4587 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4588 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4589 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4590 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4591 .serdes_power = mv88e6352_serdes_power, 4592 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4593 .serdes_get_regs = mv88e6352_serdes_get_regs, 4594 .gpio_ops = &mv88e6352_gpio_ops, 4595 .phylink_get_caps = mv88e6352_phylink_get_caps, 4596 }; 4597 4598 static const struct mv88e6xxx_ops mv88e6175_ops = { 4599 /* MV88E6XXX_FAMILY_6351 */ 4600 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4601 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4602 .irl_init_all = mv88e6352_g2_irl_init_all, 4603 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4604 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4605 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4606 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4607 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4608 .port_set_link = mv88e6xxx_port_set_link, 4609 .port_sync_link = mv88e6xxx_port_sync_link, 4610 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4611 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4612 .port_tag_remap = mv88e6095_port_tag_remap, 4613 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4614 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4615 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4616 .port_set_ether_type = mv88e6351_port_set_ether_type, 4617 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4618 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4619 .port_pause_limit = mv88e6097_port_pause_limit, 4620 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4621 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4622 .port_get_cmode = mv88e6352_port_get_cmode, 4623 .port_setup_message_port = mv88e6xxx_setup_message_port, 4624 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4625 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4626 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4627 .stats_get_strings = mv88e6095_stats_get_strings, 4628 .stats_get_stats = mv88e6095_stats_get_stats, 4629 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4630 .set_egress_port = mv88e6095_g1_set_egress_port, 4631 .watchdog_ops = &mv88e6097_watchdog_ops, 4632 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4633 .pot_clear = mv88e6xxx_g2_pot_clear, 4634 .reset = mv88e6352_g1_reset, 4635 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4636 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4637 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4638 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4639 .stu_getnext = mv88e6352_g1_stu_getnext, 4640 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4641 .phylink_get_caps = mv88e6185_phylink_get_caps, 4642 }; 4643 4644 static const struct mv88e6xxx_ops mv88e6176_ops = { 4645 /* MV88E6XXX_FAMILY_6352 */ 4646 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4647 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4648 .irl_init_all = mv88e6352_g2_irl_init_all, 4649 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4650 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4651 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4652 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4653 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4654 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4655 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4656 .port_set_link = mv88e6xxx_port_set_link, 4657 .port_sync_link = mv88e6xxx_port_sync_link, 4658 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4659 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4660 .port_tag_remap = mv88e6095_port_tag_remap, 4661 .port_set_policy = mv88e6352_port_set_policy, 4662 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4663 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4664 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4665 .port_set_ether_type = mv88e6351_port_set_ether_type, 4666 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4667 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4668 .port_pause_limit = mv88e6097_port_pause_limit, 4669 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4670 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4671 .port_get_cmode = mv88e6352_port_get_cmode, 4672 .port_setup_message_port = mv88e6xxx_setup_message_port, 4673 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4674 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4675 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4676 .stats_get_strings = mv88e6095_stats_get_strings, 4677 .stats_get_stats = mv88e6095_stats_get_stats, 4678 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4679 .set_egress_port = mv88e6095_g1_set_egress_port, 4680 .watchdog_ops = &mv88e6097_watchdog_ops, 4681 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4682 .pot_clear = mv88e6xxx_g2_pot_clear, 4683 .reset = mv88e6352_g1_reset, 4684 .rmu_disable = mv88e6352_g1_rmu_disable, 4685 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4686 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4687 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4688 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4689 .stu_getnext = mv88e6352_g1_stu_getnext, 4690 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4691 .serdes_get_lane = mv88e6352_serdes_get_lane, 4692 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4693 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4694 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4695 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4696 .serdes_power = mv88e6352_serdes_power, 4697 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4698 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4699 .serdes_irq_status = mv88e6352_serdes_irq_status, 4700 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4701 .serdes_get_regs = mv88e6352_serdes_get_regs, 4702 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4703 .gpio_ops = &mv88e6352_gpio_ops, 4704 .phylink_get_caps = mv88e6352_phylink_get_caps, 4705 }; 4706 4707 static const struct mv88e6xxx_ops mv88e6185_ops = { 4708 /* MV88E6XXX_FAMILY_6185 */ 4709 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4710 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4711 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4712 .phy_read = mv88e6185_phy_ppu_read, 4713 .phy_write = mv88e6185_phy_ppu_write, 4714 .port_set_link = mv88e6xxx_port_set_link, 4715 .port_sync_link = mv88e6185_port_sync_link, 4716 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4717 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4718 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4719 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4720 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4721 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4722 .port_set_pause = mv88e6185_port_set_pause, 4723 .port_get_cmode = mv88e6185_port_get_cmode, 4724 .port_setup_message_port = mv88e6xxx_setup_message_port, 4725 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4726 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4727 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4728 .stats_get_strings = mv88e6095_stats_get_strings, 4729 .stats_get_stats = mv88e6095_stats_get_stats, 4730 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4731 .set_egress_port = mv88e6095_g1_set_egress_port, 4732 .watchdog_ops = &mv88e6097_watchdog_ops, 4733 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4734 .serdes_power = mv88e6185_serdes_power, 4735 .serdes_get_lane = mv88e6185_serdes_get_lane, 4736 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4737 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4738 .ppu_enable = mv88e6185_g1_ppu_enable, 4739 .ppu_disable = mv88e6185_g1_ppu_disable, 4740 .reset = mv88e6185_g1_reset, 4741 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4742 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4743 .phylink_get_caps = mv88e6185_phylink_get_caps, 4744 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4745 }; 4746 4747 static const struct mv88e6xxx_ops mv88e6190_ops = { 4748 /* MV88E6XXX_FAMILY_6390 */ 4749 .setup_errata = mv88e6390_setup_errata, 4750 .irl_init_all = mv88e6390_g2_irl_init_all, 4751 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4752 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4753 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4754 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4755 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4756 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4757 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4758 .port_set_link = mv88e6xxx_port_set_link, 4759 .port_sync_link = mv88e6xxx_port_sync_link, 4760 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4761 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4762 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4763 .port_tag_remap = mv88e6390_port_tag_remap, 4764 .port_set_policy = mv88e6352_port_set_policy, 4765 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4766 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4767 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4768 .port_set_ether_type = mv88e6351_port_set_ether_type, 4769 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4770 .port_pause_limit = mv88e6390_port_pause_limit, 4771 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4772 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4773 .port_get_cmode = mv88e6352_port_get_cmode, 4774 .port_set_cmode = mv88e6390_port_set_cmode, 4775 .port_setup_message_port = mv88e6xxx_setup_message_port, 4776 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4777 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4778 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4779 .stats_get_strings = mv88e6320_stats_get_strings, 4780 .stats_get_stats = mv88e6390_stats_get_stats, 4781 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4782 .set_egress_port = mv88e6390_g1_set_egress_port, 4783 .watchdog_ops = &mv88e6390_watchdog_ops, 4784 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4785 .pot_clear = mv88e6xxx_g2_pot_clear, 4786 .reset = mv88e6352_g1_reset, 4787 .rmu_disable = mv88e6390_g1_rmu_disable, 4788 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4789 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4790 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4791 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4792 .stu_getnext = mv88e6390_g1_stu_getnext, 4793 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4794 .serdes_power = mv88e6390_serdes_power, 4795 .serdes_get_lane = mv88e6390_serdes_get_lane, 4796 /* Check status register pause & lpa register */ 4797 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4798 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4799 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4800 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4801 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4802 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4803 .serdes_irq_status = mv88e6390_serdes_irq_status, 4804 .serdes_get_strings = mv88e6390_serdes_get_strings, 4805 .serdes_get_stats = mv88e6390_serdes_get_stats, 4806 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4807 .serdes_get_regs = mv88e6390_serdes_get_regs, 4808 .gpio_ops = &mv88e6352_gpio_ops, 4809 .phylink_get_caps = mv88e6390_phylink_get_caps, 4810 }; 4811 4812 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4813 /* MV88E6XXX_FAMILY_6390 */ 4814 .setup_errata = mv88e6390_setup_errata, 4815 .irl_init_all = mv88e6390_g2_irl_init_all, 4816 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4817 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4818 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4819 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4820 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4821 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4822 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4823 .port_set_link = mv88e6xxx_port_set_link, 4824 .port_sync_link = mv88e6xxx_port_sync_link, 4825 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4826 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4827 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4828 .port_tag_remap = mv88e6390_port_tag_remap, 4829 .port_set_policy = mv88e6352_port_set_policy, 4830 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4831 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4832 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4833 .port_set_ether_type = mv88e6351_port_set_ether_type, 4834 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4835 .port_pause_limit = mv88e6390_port_pause_limit, 4836 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4837 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4838 .port_get_cmode = mv88e6352_port_get_cmode, 4839 .port_set_cmode = mv88e6390x_port_set_cmode, 4840 .port_setup_message_port = mv88e6xxx_setup_message_port, 4841 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4842 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4843 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4844 .stats_get_strings = mv88e6320_stats_get_strings, 4845 .stats_get_stats = mv88e6390_stats_get_stats, 4846 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4847 .set_egress_port = mv88e6390_g1_set_egress_port, 4848 .watchdog_ops = &mv88e6390_watchdog_ops, 4849 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4850 .pot_clear = mv88e6xxx_g2_pot_clear, 4851 .reset = mv88e6352_g1_reset, 4852 .rmu_disable = mv88e6390_g1_rmu_disable, 4853 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4854 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4855 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4856 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4857 .stu_getnext = mv88e6390_g1_stu_getnext, 4858 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4859 .serdes_power = mv88e6390_serdes_power, 4860 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4861 /* Check status register pause & lpa register */ 4862 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4863 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4864 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4865 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4866 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4867 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4868 .serdes_irq_status = mv88e6390_serdes_irq_status, 4869 .serdes_get_strings = mv88e6390_serdes_get_strings, 4870 .serdes_get_stats = mv88e6390_serdes_get_stats, 4871 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4872 .serdes_get_regs = mv88e6390_serdes_get_regs, 4873 .gpio_ops = &mv88e6352_gpio_ops, 4874 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4875 }; 4876 4877 static const struct mv88e6xxx_ops mv88e6191_ops = { 4878 /* MV88E6XXX_FAMILY_6390 */ 4879 .setup_errata = mv88e6390_setup_errata, 4880 .irl_init_all = mv88e6390_g2_irl_init_all, 4881 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4882 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4883 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4884 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4885 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4886 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4887 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4888 .port_set_link = mv88e6xxx_port_set_link, 4889 .port_sync_link = mv88e6xxx_port_sync_link, 4890 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4891 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4892 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4893 .port_tag_remap = mv88e6390_port_tag_remap, 4894 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4895 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4896 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4897 .port_set_ether_type = mv88e6351_port_set_ether_type, 4898 .port_pause_limit = mv88e6390_port_pause_limit, 4899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4901 .port_get_cmode = mv88e6352_port_get_cmode, 4902 .port_set_cmode = mv88e6390_port_set_cmode, 4903 .port_setup_message_port = mv88e6xxx_setup_message_port, 4904 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4905 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4906 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4907 .stats_get_strings = mv88e6320_stats_get_strings, 4908 .stats_get_stats = mv88e6390_stats_get_stats, 4909 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4910 .set_egress_port = mv88e6390_g1_set_egress_port, 4911 .watchdog_ops = &mv88e6390_watchdog_ops, 4912 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4913 .pot_clear = mv88e6xxx_g2_pot_clear, 4914 .reset = mv88e6352_g1_reset, 4915 .rmu_disable = mv88e6390_g1_rmu_disable, 4916 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4917 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4918 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4919 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4920 .stu_getnext = mv88e6390_g1_stu_getnext, 4921 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4922 .serdes_power = mv88e6390_serdes_power, 4923 .serdes_get_lane = mv88e6390_serdes_get_lane, 4924 /* Check status register pause & lpa register */ 4925 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4926 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4927 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4928 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4929 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4930 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4931 .serdes_irq_status = mv88e6390_serdes_irq_status, 4932 .serdes_get_strings = mv88e6390_serdes_get_strings, 4933 .serdes_get_stats = mv88e6390_serdes_get_stats, 4934 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4935 .serdes_get_regs = mv88e6390_serdes_get_regs, 4936 .avb_ops = &mv88e6390_avb_ops, 4937 .ptp_ops = &mv88e6352_ptp_ops, 4938 .phylink_get_caps = mv88e6390_phylink_get_caps, 4939 }; 4940 4941 static const struct mv88e6xxx_ops mv88e6240_ops = { 4942 /* MV88E6XXX_FAMILY_6352 */ 4943 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4944 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4945 .irl_init_all = mv88e6352_g2_irl_init_all, 4946 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4947 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4948 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4949 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4950 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4951 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4952 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4953 .port_set_link = mv88e6xxx_port_set_link, 4954 .port_sync_link = mv88e6xxx_port_sync_link, 4955 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4956 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4957 .port_tag_remap = mv88e6095_port_tag_remap, 4958 .port_set_policy = mv88e6352_port_set_policy, 4959 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4960 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4961 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4962 .port_set_ether_type = mv88e6351_port_set_ether_type, 4963 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4964 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4965 .port_pause_limit = mv88e6097_port_pause_limit, 4966 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4967 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4968 .port_get_cmode = mv88e6352_port_get_cmode, 4969 .port_setup_message_port = mv88e6xxx_setup_message_port, 4970 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4971 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4972 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4973 .stats_get_strings = mv88e6095_stats_get_strings, 4974 .stats_get_stats = mv88e6095_stats_get_stats, 4975 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4976 .set_egress_port = mv88e6095_g1_set_egress_port, 4977 .watchdog_ops = &mv88e6097_watchdog_ops, 4978 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4979 .pot_clear = mv88e6xxx_g2_pot_clear, 4980 .reset = mv88e6352_g1_reset, 4981 .rmu_disable = mv88e6352_g1_rmu_disable, 4982 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4983 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4984 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4985 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4986 .stu_getnext = mv88e6352_g1_stu_getnext, 4987 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4988 .serdes_get_lane = mv88e6352_serdes_get_lane, 4989 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4990 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4991 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4992 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4993 .serdes_power = mv88e6352_serdes_power, 4994 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4995 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4996 .serdes_irq_status = mv88e6352_serdes_irq_status, 4997 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4998 .serdes_get_regs = mv88e6352_serdes_get_regs, 4999 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5000 .gpio_ops = &mv88e6352_gpio_ops, 5001 .avb_ops = &mv88e6352_avb_ops, 5002 .ptp_ops = &mv88e6352_ptp_ops, 5003 .phylink_get_caps = mv88e6352_phylink_get_caps, 5004 }; 5005 5006 static const struct mv88e6xxx_ops mv88e6250_ops = { 5007 /* MV88E6XXX_FAMILY_6250 */ 5008 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5009 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5010 .irl_init_all = mv88e6352_g2_irl_init_all, 5011 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5012 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5013 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5014 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5015 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5016 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5017 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5018 .port_set_link = mv88e6xxx_port_set_link, 5019 .port_sync_link = mv88e6xxx_port_sync_link, 5020 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5021 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5022 .port_tag_remap = mv88e6095_port_tag_remap, 5023 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5024 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5025 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5026 .port_set_ether_type = mv88e6351_port_set_ether_type, 5027 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5028 .port_pause_limit = mv88e6097_port_pause_limit, 5029 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5030 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5031 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5032 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5033 .stats_get_strings = mv88e6250_stats_get_strings, 5034 .stats_get_stats = mv88e6250_stats_get_stats, 5035 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5036 .set_egress_port = mv88e6095_g1_set_egress_port, 5037 .watchdog_ops = &mv88e6250_watchdog_ops, 5038 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5039 .pot_clear = mv88e6xxx_g2_pot_clear, 5040 .reset = mv88e6250_g1_reset, 5041 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5042 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5043 .avb_ops = &mv88e6352_avb_ops, 5044 .ptp_ops = &mv88e6250_ptp_ops, 5045 .phylink_get_caps = mv88e6250_phylink_get_caps, 5046 }; 5047 5048 static const struct mv88e6xxx_ops mv88e6290_ops = { 5049 /* MV88E6XXX_FAMILY_6390 */ 5050 .setup_errata = mv88e6390_setup_errata, 5051 .irl_init_all = mv88e6390_g2_irl_init_all, 5052 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5053 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5054 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5055 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5056 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5057 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5058 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5059 .port_set_link = mv88e6xxx_port_set_link, 5060 .port_sync_link = mv88e6xxx_port_sync_link, 5061 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5062 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5063 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5064 .port_tag_remap = mv88e6390_port_tag_remap, 5065 .port_set_policy = mv88e6352_port_set_policy, 5066 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5067 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5068 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5069 .port_set_ether_type = mv88e6351_port_set_ether_type, 5070 .port_pause_limit = mv88e6390_port_pause_limit, 5071 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5072 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5073 .port_get_cmode = mv88e6352_port_get_cmode, 5074 .port_set_cmode = mv88e6390_port_set_cmode, 5075 .port_setup_message_port = mv88e6xxx_setup_message_port, 5076 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5077 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5078 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5079 .stats_get_strings = mv88e6320_stats_get_strings, 5080 .stats_get_stats = mv88e6390_stats_get_stats, 5081 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5082 .set_egress_port = mv88e6390_g1_set_egress_port, 5083 .watchdog_ops = &mv88e6390_watchdog_ops, 5084 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5085 .pot_clear = mv88e6xxx_g2_pot_clear, 5086 .reset = mv88e6352_g1_reset, 5087 .rmu_disable = mv88e6390_g1_rmu_disable, 5088 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5089 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5090 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5091 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5092 .stu_getnext = mv88e6390_g1_stu_getnext, 5093 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5094 .serdes_power = mv88e6390_serdes_power, 5095 .serdes_get_lane = mv88e6390_serdes_get_lane, 5096 /* Check status register pause & lpa register */ 5097 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5098 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5099 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5100 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5101 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5102 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5103 .serdes_irq_status = mv88e6390_serdes_irq_status, 5104 .serdes_get_strings = mv88e6390_serdes_get_strings, 5105 .serdes_get_stats = mv88e6390_serdes_get_stats, 5106 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5107 .serdes_get_regs = mv88e6390_serdes_get_regs, 5108 .gpio_ops = &mv88e6352_gpio_ops, 5109 .avb_ops = &mv88e6390_avb_ops, 5110 .ptp_ops = &mv88e6390_ptp_ops, 5111 .phylink_get_caps = mv88e6390_phylink_get_caps, 5112 }; 5113 5114 static const struct mv88e6xxx_ops mv88e6320_ops = { 5115 /* MV88E6XXX_FAMILY_6320 */ 5116 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5117 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5118 .irl_init_all = mv88e6352_g2_irl_init_all, 5119 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5120 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5121 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5122 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5123 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5124 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5125 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5126 .port_set_link = mv88e6xxx_port_set_link, 5127 .port_sync_link = mv88e6xxx_port_sync_link, 5128 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5129 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5130 .port_tag_remap = mv88e6095_port_tag_remap, 5131 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5132 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5133 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5134 .port_set_ether_type = mv88e6351_port_set_ether_type, 5135 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5136 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5137 .port_pause_limit = mv88e6097_port_pause_limit, 5138 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5139 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5140 .port_get_cmode = mv88e6352_port_get_cmode, 5141 .port_setup_message_port = mv88e6xxx_setup_message_port, 5142 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5143 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5144 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5145 .stats_get_strings = mv88e6320_stats_get_strings, 5146 .stats_get_stats = mv88e6320_stats_get_stats, 5147 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5148 .set_egress_port = mv88e6095_g1_set_egress_port, 5149 .watchdog_ops = &mv88e6390_watchdog_ops, 5150 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5151 .pot_clear = mv88e6xxx_g2_pot_clear, 5152 .reset = mv88e6352_g1_reset, 5153 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5154 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5155 .gpio_ops = &mv88e6352_gpio_ops, 5156 .avb_ops = &mv88e6352_avb_ops, 5157 .ptp_ops = &mv88e6352_ptp_ops, 5158 .phylink_get_caps = mv88e6185_phylink_get_caps, 5159 }; 5160 5161 static const struct mv88e6xxx_ops mv88e6321_ops = { 5162 /* MV88E6XXX_FAMILY_6320 */ 5163 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5164 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5165 .irl_init_all = mv88e6352_g2_irl_init_all, 5166 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5167 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5168 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5169 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5170 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5171 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5172 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5173 .port_set_link = mv88e6xxx_port_set_link, 5174 .port_sync_link = mv88e6xxx_port_sync_link, 5175 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5176 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5177 .port_tag_remap = mv88e6095_port_tag_remap, 5178 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5179 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5180 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5181 .port_set_ether_type = mv88e6351_port_set_ether_type, 5182 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5183 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5184 .port_pause_limit = mv88e6097_port_pause_limit, 5185 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5186 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5187 .port_get_cmode = mv88e6352_port_get_cmode, 5188 .port_setup_message_port = mv88e6xxx_setup_message_port, 5189 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5190 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5191 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5192 .stats_get_strings = mv88e6320_stats_get_strings, 5193 .stats_get_stats = mv88e6320_stats_get_stats, 5194 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5195 .set_egress_port = mv88e6095_g1_set_egress_port, 5196 .watchdog_ops = &mv88e6390_watchdog_ops, 5197 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5198 .reset = mv88e6352_g1_reset, 5199 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5200 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5201 .gpio_ops = &mv88e6352_gpio_ops, 5202 .avb_ops = &mv88e6352_avb_ops, 5203 .ptp_ops = &mv88e6352_ptp_ops, 5204 .phylink_get_caps = mv88e6185_phylink_get_caps, 5205 }; 5206 5207 static const struct mv88e6xxx_ops mv88e6341_ops = { 5208 /* MV88E6XXX_FAMILY_6341 */ 5209 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5210 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5211 .irl_init_all = mv88e6352_g2_irl_init_all, 5212 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5213 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5214 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5215 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5216 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5217 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5218 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5219 .port_set_link = mv88e6xxx_port_set_link, 5220 .port_sync_link = mv88e6xxx_port_sync_link, 5221 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5222 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5223 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5224 .port_tag_remap = mv88e6095_port_tag_remap, 5225 .port_set_policy = mv88e6352_port_set_policy, 5226 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5227 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5228 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5229 .port_set_ether_type = mv88e6351_port_set_ether_type, 5230 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5231 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5232 .port_pause_limit = mv88e6097_port_pause_limit, 5233 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5234 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5235 .port_get_cmode = mv88e6352_port_get_cmode, 5236 .port_set_cmode = mv88e6341_port_set_cmode, 5237 .port_setup_message_port = mv88e6xxx_setup_message_port, 5238 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5239 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5240 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5241 .stats_get_strings = mv88e6320_stats_get_strings, 5242 .stats_get_stats = mv88e6390_stats_get_stats, 5243 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5244 .set_egress_port = mv88e6390_g1_set_egress_port, 5245 .watchdog_ops = &mv88e6390_watchdog_ops, 5246 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5247 .pot_clear = mv88e6xxx_g2_pot_clear, 5248 .reset = mv88e6352_g1_reset, 5249 .rmu_disable = mv88e6390_g1_rmu_disable, 5250 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5251 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5252 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5253 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5254 .stu_getnext = mv88e6352_g1_stu_getnext, 5255 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5256 .serdes_power = mv88e6390_serdes_power, 5257 .serdes_get_lane = mv88e6341_serdes_get_lane, 5258 /* Check status register pause & lpa register */ 5259 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5260 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5261 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5262 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5263 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5264 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5265 .serdes_irq_status = mv88e6390_serdes_irq_status, 5266 .gpio_ops = &mv88e6352_gpio_ops, 5267 .avb_ops = &mv88e6390_avb_ops, 5268 .ptp_ops = &mv88e6352_ptp_ops, 5269 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5270 .serdes_get_strings = mv88e6390_serdes_get_strings, 5271 .serdes_get_stats = mv88e6390_serdes_get_stats, 5272 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5273 .serdes_get_regs = mv88e6390_serdes_get_regs, 5274 .phylink_get_caps = mv88e6341_phylink_get_caps, 5275 }; 5276 5277 static const struct mv88e6xxx_ops mv88e6350_ops = { 5278 /* MV88E6XXX_FAMILY_6351 */ 5279 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5280 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5281 .irl_init_all = mv88e6352_g2_irl_init_all, 5282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5283 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5284 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5285 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5286 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5287 .port_set_link = mv88e6xxx_port_set_link, 5288 .port_sync_link = mv88e6xxx_port_sync_link, 5289 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5290 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5291 .port_tag_remap = mv88e6095_port_tag_remap, 5292 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5293 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5294 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5295 .port_set_ether_type = mv88e6351_port_set_ether_type, 5296 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5297 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5298 .port_pause_limit = mv88e6097_port_pause_limit, 5299 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5300 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5301 .port_get_cmode = mv88e6352_port_get_cmode, 5302 .port_setup_message_port = mv88e6xxx_setup_message_port, 5303 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5304 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5305 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5306 .stats_get_strings = mv88e6095_stats_get_strings, 5307 .stats_get_stats = mv88e6095_stats_get_stats, 5308 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5309 .set_egress_port = mv88e6095_g1_set_egress_port, 5310 .watchdog_ops = &mv88e6097_watchdog_ops, 5311 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5312 .pot_clear = mv88e6xxx_g2_pot_clear, 5313 .reset = mv88e6352_g1_reset, 5314 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5315 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5316 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5317 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5318 .stu_getnext = mv88e6352_g1_stu_getnext, 5319 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5320 .phylink_get_caps = mv88e6185_phylink_get_caps, 5321 }; 5322 5323 static const struct mv88e6xxx_ops mv88e6351_ops = { 5324 /* MV88E6XXX_FAMILY_6351 */ 5325 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5326 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5327 .irl_init_all = mv88e6352_g2_irl_init_all, 5328 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5329 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5330 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5331 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5332 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5333 .port_set_link = mv88e6xxx_port_set_link, 5334 .port_sync_link = mv88e6xxx_port_sync_link, 5335 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5336 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5337 .port_tag_remap = mv88e6095_port_tag_remap, 5338 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5339 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5340 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5341 .port_set_ether_type = mv88e6351_port_set_ether_type, 5342 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5343 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5344 .port_pause_limit = mv88e6097_port_pause_limit, 5345 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5346 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5347 .port_get_cmode = mv88e6352_port_get_cmode, 5348 .port_setup_message_port = mv88e6xxx_setup_message_port, 5349 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5350 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5351 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5352 .stats_get_strings = mv88e6095_stats_get_strings, 5353 .stats_get_stats = mv88e6095_stats_get_stats, 5354 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5355 .set_egress_port = mv88e6095_g1_set_egress_port, 5356 .watchdog_ops = &mv88e6097_watchdog_ops, 5357 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5358 .pot_clear = mv88e6xxx_g2_pot_clear, 5359 .reset = mv88e6352_g1_reset, 5360 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5361 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5362 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5363 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5364 .stu_getnext = mv88e6352_g1_stu_getnext, 5365 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5366 .avb_ops = &mv88e6352_avb_ops, 5367 .ptp_ops = &mv88e6352_ptp_ops, 5368 .phylink_get_caps = mv88e6185_phylink_get_caps, 5369 }; 5370 5371 static const struct mv88e6xxx_ops mv88e6352_ops = { 5372 /* MV88E6XXX_FAMILY_6352 */ 5373 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5374 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5375 .irl_init_all = mv88e6352_g2_irl_init_all, 5376 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5377 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5378 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5379 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5380 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5381 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5382 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5383 .port_set_link = mv88e6xxx_port_set_link, 5384 .port_sync_link = mv88e6xxx_port_sync_link, 5385 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5386 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5387 .port_tag_remap = mv88e6095_port_tag_remap, 5388 .port_set_policy = mv88e6352_port_set_policy, 5389 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5390 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5391 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5392 .port_set_ether_type = mv88e6351_port_set_ether_type, 5393 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5394 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5395 .port_pause_limit = mv88e6097_port_pause_limit, 5396 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5397 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5398 .port_get_cmode = mv88e6352_port_get_cmode, 5399 .port_setup_message_port = mv88e6xxx_setup_message_port, 5400 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5401 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5402 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5403 .stats_get_strings = mv88e6095_stats_get_strings, 5404 .stats_get_stats = mv88e6095_stats_get_stats, 5405 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5406 .set_egress_port = mv88e6095_g1_set_egress_port, 5407 .watchdog_ops = &mv88e6097_watchdog_ops, 5408 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5409 .pot_clear = mv88e6xxx_g2_pot_clear, 5410 .reset = mv88e6352_g1_reset, 5411 .rmu_disable = mv88e6352_g1_rmu_disable, 5412 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5413 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5414 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5415 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5416 .stu_getnext = mv88e6352_g1_stu_getnext, 5417 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5418 .serdes_get_lane = mv88e6352_serdes_get_lane, 5419 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5420 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5421 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5422 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5423 .serdes_power = mv88e6352_serdes_power, 5424 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5425 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5426 .serdes_irq_status = mv88e6352_serdes_irq_status, 5427 .gpio_ops = &mv88e6352_gpio_ops, 5428 .avb_ops = &mv88e6352_avb_ops, 5429 .ptp_ops = &mv88e6352_ptp_ops, 5430 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5431 .serdes_get_strings = mv88e6352_serdes_get_strings, 5432 .serdes_get_stats = mv88e6352_serdes_get_stats, 5433 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5434 .serdes_get_regs = mv88e6352_serdes_get_regs, 5435 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5436 .phylink_get_caps = mv88e6352_phylink_get_caps, 5437 }; 5438 5439 static const struct mv88e6xxx_ops mv88e6390_ops = { 5440 /* MV88E6XXX_FAMILY_6390 */ 5441 .setup_errata = mv88e6390_setup_errata, 5442 .irl_init_all = mv88e6390_g2_irl_init_all, 5443 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5444 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5445 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5446 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5447 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5448 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5449 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5450 .port_set_link = mv88e6xxx_port_set_link, 5451 .port_sync_link = mv88e6xxx_port_sync_link, 5452 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5453 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5454 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5455 .port_tag_remap = mv88e6390_port_tag_remap, 5456 .port_set_policy = mv88e6352_port_set_policy, 5457 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5458 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5459 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5460 .port_set_ether_type = mv88e6351_port_set_ether_type, 5461 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5462 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5463 .port_pause_limit = mv88e6390_port_pause_limit, 5464 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5465 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5466 .port_get_cmode = mv88e6352_port_get_cmode, 5467 .port_set_cmode = mv88e6390_port_set_cmode, 5468 .port_setup_message_port = mv88e6xxx_setup_message_port, 5469 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5470 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5471 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5472 .stats_get_strings = mv88e6320_stats_get_strings, 5473 .stats_get_stats = mv88e6390_stats_get_stats, 5474 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5475 .set_egress_port = mv88e6390_g1_set_egress_port, 5476 .watchdog_ops = &mv88e6390_watchdog_ops, 5477 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5478 .pot_clear = mv88e6xxx_g2_pot_clear, 5479 .reset = mv88e6352_g1_reset, 5480 .rmu_disable = mv88e6390_g1_rmu_disable, 5481 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5482 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5483 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5484 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5485 .stu_getnext = mv88e6390_g1_stu_getnext, 5486 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5487 .serdes_power = mv88e6390_serdes_power, 5488 .serdes_get_lane = mv88e6390_serdes_get_lane, 5489 /* Check status register pause & lpa register */ 5490 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5491 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5492 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5493 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5494 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5495 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5496 .serdes_irq_status = mv88e6390_serdes_irq_status, 5497 .gpio_ops = &mv88e6352_gpio_ops, 5498 .avb_ops = &mv88e6390_avb_ops, 5499 .ptp_ops = &mv88e6390_ptp_ops, 5500 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5501 .serdes_get_strings = mv88e6390_serdes_get_strings, 5502 .serdes_get_stats = mv88e6390_serdes_get_stats, 5503 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5504 .serdes_get_regs = mv88e6390_serdes_get_regs, 5505 .phylink_get_caps = mv88e6390_phylink_get_caps, 5506 }; 5507 5508 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5509 /* MV88E6XXX_FAMILY_6390 */ 5510 .setup_errata = mv88e6390_setup_errata, 5511 .irl_init_all = mv88e6390_g2_irl_init_all, 5512 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5513 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5514 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5515 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5516 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5517 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5518 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5519 .port_set_link = mv88e6xxx_port_set_link, 5520 .port_sync_link = mv88e6xxx_port_sync_link, 5521 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5522 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5523 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5524 .port_tag_remap = mv88e6390_port_tag_remap, 5525 .port_set_policy = mv88e6352_port_set_policy, 5526 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5527 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5528 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5529 .port_set_ether_type = mv88e6351_port_set_ether_type, 5530 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5531 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5532 .port_pause_limit = mv88e6390_port_pause_limit, 5533 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5534 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5535 .port_get_cmode = mv88e6352_port_get_cmode, 5536 .port_set_cmode = mv88e6390x_port_set_cmode, 5537 .port_setup_message_port = mv88e6xxx_setup_message_port, 5538 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5539 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5540 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5541 .stats_get_strings = mv88e6320_stats_get_strings, 5542 .stats_get_stats = mv88e6390_stats_get_stats, 5543 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5544 .set_egress_port = mv88e6390_g1_set_egress_port, 5545 .watchdog_ops = &mv88e6390_watchdog_ops, 5546 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5547 .pot_clear = mv88e6xxx_g2_pot_clear, 5548 .reset = mv88e6352_g1_reset, 5549 .rmu_disable = mv88e6390_g1_rmu_disable, 5550 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5551 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5552 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5553 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5554 .stu_getnext = mv88e6390_g1_stu_getnext, 5555 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5556 .serdes_power = mv88e6390_serdes_power, 5557 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5558 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5559 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5560 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5561 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5562 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5563 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5564 .serdes_irq_status = mv88e6390_serdes_irq_status, 5565 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5566 .serdes_get_strings = mv88e6390_serdes_get_strings, 5567 .serdes_get_stats = mv88e6390_serdes_get_stats, 5568 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5569 .serdes_get_regs = mv88e6390_serdes_get_regs, 5570 .gpio_ops = &mv88e6352_gpio_ops, 5571 .avb_ops = &mv88e6390_avb_ops, 5572 .ptp_ops = &mv88e6390_ptp_ops, 5573 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5574 }; 5575 5576 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5577 /* MV88E6XXX_FAMILY_6393 */ 5578 .setup_errata = mv88e6393x_serdes_setup_errata, 5579 .irl_init_all = mv88e6390_g2_irl_init_all, 5580 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5581 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5582 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5583 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5584 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5585 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5586 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5587 .port_set_link = mv88e6xxx_port_set_link, 5588 .port_sync_link = mv88e6xxx_port_sync_link, 5589 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5590 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5591 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5592 .port_tag_remap = mv88e6390_port_tag_remap, 5593 .port_set_policy = mv88e6393x_port_set_policy, 5594 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5595 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5596 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5597 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5598 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5599 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5600 .port_pause_limit = mv88e6390_port_pause_limit, 5601 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5602 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5603 .port_get_cmode = mv88e6352_port_get_cmode, 5604 .port_set_cmode = mv88e6393x_port_set_cmode, 5605 .port_setup_message_port = mv88e6xxx_setup_message_port, 5606 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5607 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5608 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5609 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5610 .stats_get_strings = mv88e6320_stats_get_strings, 5611 .stats_get_stats = mv88e6390_stats_get_stats, 5612 /* .set_cpu_port is missing because this family does not support a global 5613 * CPU port, only per port CPU port which is set via 5614 * .port_set_upstream_port method. 5615 */ 5616 .set_egress_port = mv88e6393x_set_egress_port, 5617 .watchdog_ops = &mv88e6393x_watchdog_ops, 5618 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5619 .pot_clear = mv88e6xxx_g2_pot_clear, 5620 .reset = mv88e6352_g1_reset, 5621 .rmu_disable = mv88e6390_g1_rmu_disable, 5622 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5623 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5624 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5625 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5626 .stu_getnext = mv88e6390_g1_stu_getnext, 5627 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5628 .serdes_power = mv88e6393x_serdes_power, 5629 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5630 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5631 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5632 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5633 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5634 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5635 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5636 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5637 /* TODO: serdes stats */ 5638 .gpio_ops = &mv88e6352_gpio_ops, 5639 .avb_ops = &mv88e6390_avb_ops, 5640 .ptp_ops = &mv88e6352_ptp_ops, 5641 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5642 }; 5643 5644 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5645 [MV88E6085] = { 5646 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5647 .family = MV88E6XXX_FAMILY_6097, 5648 .name = "Marvell 88E6085", 5649 .num_databases = 4096, 5650 .num_macs = 8192, 5651 .num_ports = 10, 5652 .num_internal_phys = 5, 5653 .max_vid = 4095, 5654 .max_sid = 63, 5655 .port_base_addr = 0x10, 5656 .phy_base_addr = 0x0, 5657 .global1_addr = 0x1b, 5658 .global2_addr = 0x1c, 5659 .age_time_coeff = 15000, 5660 .g1_irqs = 8, 5661 .g2_irqs = 10, 5662 .atu_move_port_mask = 0xf, 5663 .pvt = true, 5664 .multi_chip = true, 5665 .ops = &mv88e6085_ops, 5666 }, 5667 5668 [MV88E6095] = { 5669 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5670 .family = MV88E6XXX_FAMILY_6095, 5671 .name = "Marvell 88E6095/88E6095F", 5672 .num_databases = 256, 5673 .num_macs = 8192, 5674 .num_ports = 11, 5675 .num_internal_phys = 0, 5676 .max_vid = 4095, 5677 .port_base_addr = 0x10, 5678 .phy_base_addr = 0x0, 5679 .global1_addr = 0x1b, 5680 .global2_addr = 0x1c, 5681 .age_time_coeff = 15000, 5682 .g1_irqs = 8, 5683 .atu_move_port_mask = 0xf, 5684 .multi_chip = true, 5685 .ops = &mv88e6095_ops, 5686 }, 5687 5688 [MV88E6097] = { 5689 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5690 .family = MV88E6XXX_FAMILY_6097, 5691 .name = "Marvell 88E6097/88E6097F", 5692 .num_databases = 4096, 5693 .num_macs = 8192, 5694 .num_ports = 11, 5695 .num_internal_phys = 8, 5696 .max_vid = 4095, 5697 .max_sid = 63, 5698 .port_base_addr = 0x10, 5699 .phy_base_addr = 0x0, 5700 .global1_addr = 0x1b, 5701 .global2_addr = 0x1c, 5702 .age_time_coeff = 15000, 5703 .g1_irqs = 8, 5704 .g2_irqs = 10, 5705 .atu_move_port_mask = 0xf, 5706 .pvt = true, 5707 .multi_chip = true, 5708 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5709 .ops = &mv88e6097_ops, 5710 }, 5711 5712 [MV88E6123] = { 5713 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5714 .family = MV88E6XXX_FAMILY_6165, 5715 .name = "Marvell 88E6123", 5716 .num_databases = 4096, 5717 .num_macs = 1024, 5718 .num_ports = 3, 5719 .num_internal_phys = 5, 5720 .max_vid = 4095, 5721 .max_sid = 63, 5722 .port_base_addr = 0x10, 5723 .phy_base_addr = 0x0, 5724 .global1_addr = 0x1b, 5725 .global2_addr = 0x1c, 5726 .age_time_coeff = 15000, 5727 .g1_irqs = 9, 5728 .g2_irqs = 10, 5729 .atu_move_port_mask = 0xf, 5730 .pvt = true, 5731 .multi_chip = true, 5732 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5733 .ops = &mv88e6123_ops, 5734 }, 5735 5736 [MV88E6131] = { 5737 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5738 .family = MV88E6XXX_FAMILY_6185, 5739 .name = "Marvell 88E6131", 5740 .num_databases = 256, 5741 .num_macs = 8192, 5742 .num_ports = 8, 5743 .num_internal_phys = 0, 5744 .max_vid = 4095, 5745 .port_base_addr = 0x10, 5746 .phy_base_addr = 0x0, 5747 .global1_addr = 0x1b, 5748 .global2_addr = 0x1c, 5749 .age_time_coeff = 15000, 5750 .g1_irqs = 9, 5751 .atu_move_port_mask = 0xf, 5752 .multi_chip = true, 5753 .ops = &mv88e6131_ops, 5754 }, 5755 5756 [MV88E6141] = { 5757 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5758 .family = MV88E6XXX_FAMILY_6341, 5759 .name = "Marvell 88E6141", 5760 .num_databases = 4096, 5761 .num_macs = 2048, 5762 .num_ports = 6, 5763 .num_internal_phys = 5, 5764 .num_gpio = 11, 5765 .max_vid = 4095, 5766 .max_sid = 63, 5767 .port_base_addr = 0x10, 5768 .phy_base_addr = 0x10, 5769 .global1_addr = 0x1b, 5770 .global2_addr = 0x1c, 5771 .age_time_coeff = 3750, 5772 .atu_move_port_mask = 0x1f, 5773 .g1_irqs = 9, 5774 .g2_irqs = 10, 5775 .pvt = true, 5776 .multi_chip = true, 5777 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5778 .ops = &mv88e6141_ops, 5779 }, 5780 5781 [MV88E6161] = { 5782 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5783 .family = MV88E6XXX_FAMILY_6165, 5784 .name = "Marvell 88E6161", 5785 .num_databases = 4096, 5786 .num_macs = 1024, 5787 .num_ports = 6, 5788 .num_internal_phys = 5, 5789 .max_vid = 4095, 5790 .max_sid = 63, 5791 .port_base_addr = 0x10, 5792 .phy_base_addr = 0x0, 5793 .global1_addr = 0x1b, 5794 .global2_addr = 0x1c, 5795 .age_time_coeff = 15000, 5796 .g1_irqs = 9, 5797 .g2_irqs = 10, 5798 .atu_move_port_mask = 0xf, 5799 .pvt = true, 5800 .multi_chip = true, 5801 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5802 .ptp_support = true, 5803 .ops = &mv88e6161_ops, 5804 }, 5805 5806 [MV88E6165] = { 5807 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5808 .family = MV88E6XXX_FAMILY_6165, 5809 .name = "Marvell 88E6165", 5810 .num_databases = 4096, 5811 .num_macs = 8192, 5812 .num_ports = 6, 5813 .num_internal_phys = 0, 5814 .max_vid = 4095, 5815 .max_sid = 63, 5816 .port_base_addr = 0x10, 5817 .phy_base_addr = 0x0, 5818 .global1_addr = 0x1b, 5819 .global2_addr = 0x1c, 5820 .age_time_coeff = 15000, 5821 .g1_irqs = 9, 5822 .g2_irqs = 10, 5823 .atu_move_port_mask = 0xf, 5824 .pvt = true, 5825 .multi_chip = true, 5826 .ptp_support = true, 5827 .ops = &mv88e6165_ops, 5828 }, 5829 5830 [MV88E6171] = { 5831 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5832 .family = MV88E6XXX_FAMILY_6351, 5833 .name = "Marvell 88E6171", 5834 .num_databases = 4096, 5835 .num_macs = 8192, 5836 .num_ports = 7, 5837 .num_internal_phys = 5, 5838 .max_vid = 4095, 5839 .max_sid = 63, 5840 .port_base_addr = 0x10, 5841 .phy_base_addr = 0x0, 5842 .global1_addr = 0x1b, 5843 .global2_addr = 0x1c, 5844 .age_time_coeff = 15000, 5845 .g1_irqs = 9, 5846 .g2_irqs = 10, 5847 .atu_move_port_mask = 0xf, 5848 .pvt = true, 5849 .multi_chip = true, 5850 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5851 .ops = &mv88e6171_ops, 5852 }, 5853 5854 [MV88E6172] = { 5855 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5856 .family = MV88E6XXX_FAMILY_6352, 5857 .name = "Marvell 88E6172", 5858 .num_databases = 4096, 5859 .num_macs = 8192, 5860 .num_ports = 7, 5861 .num_internal_phys = 5, 5862 .num_gpio = 15, 5863 .max_vid = 4095, 5864 .max_sid = 63, 5865 .port_base_addr = 0x10, 5866 .phy_base_addr = 0x0, 5867 .global1_addr = 0x1b, 5868 .global2_addr = 0x1c, 5869 .age_time_coeff = 15000, 5870 .g1_irqs = 9, 5871 .g2_irqs = 10, 5872 .atu_move_port_mask = 0xf, 5873 .pvt = true, 5874 .multi_chip = true, 5875 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5876 .ops = &mv88e6172_ops, 5877 }, 5878 5879 [MV88E6175] = { 5880 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5881 .family = MV88E6XXX_FAMILY_6351, 5882 .name = "Marvell 88E6175", 5883 .num_databases = 4096, 5884 .num_macs = 8192, 5885 .num_ports = 7, 5886 .num_internal_phys = 5, 5887 .max_vid = 4095, 5888 .max_sid = 63, 5889 .port_base_addr = 0x10, 5890 .phy_base_addr = 0x0, 5891 .global1_addr = 0x1b, 5892 .global2_addr = 0x1c, 5893 .age_time_coeff = 15000, 5894 .g1_irqs = 9, 5895 .g2_irqs = 10, 5896 .atu_move_port_mask = 0xf, 5897 .pvt = true, 5898 .multi_chip = true, 5899 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5900 .ops = &mv88e6175_ops, 5901 }, 5902 5903 [MV88E6176] = { 5904 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5905 .family = MV88E6XXX_FAMILY_6352, 5906 .name = "Marvell 88E6176", 5907 .num_databases = 4096, 5908 .num_macs = 8192, 5909 .num_ports = 7, 5910 .num_internal_phys = 5, 5911 .num_gpio = 15, 5912 .max_vid = 4095, 5913 .max_sid = 63, 5914 .port_base_addr = 0x10, 5915 .phy_base_addr = 0x0, 5916 .global1_addr = 0x1b, 5917 .global2_addr = 0x1c, 5918 .age_time_coeff = 15000, 5919 .g1_irqs = 9, 5920 .g2_irqs = 10, 5921 .atu_move_port_mask = 0xf, 5922 .pvt = true, 5923 .multi_chip = true, 5924 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5925 .ops = &mv88e6176_ops, 5926 }, 5927 5928 [MV88E6185] = { 5929 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5930 .family = MV88E6XXX_FAMILY_6185, 5931 .name = "Marvell 88E6185", 5932 .num_databases = 256, 5933 .num_macs = 8192, 5934 .num_ports = 10, 5935 .num_internal_phys = 0, 5936 .max_vid = 4095, 5937 .port_base_addr = 0x10, 5938 .phy_base_addr = 0x0, 5939 .global1_addr = 0x1b, 5940 .global2_addr = 0x1c, 5941 .age_time_coeff = 15000, 5942 .g1_irqs = 8, 5943 .atu_move_port_mask = 0xf, 5944 .multi_chip = true, 5945 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5946 .ops = &mv88e6185_ops, 5947 }, 5948 5949 [MV88E6190] = { 5950 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5951 .family = MV88E6XXX_FAMILY_6390, 5952 .name = "Marvell 88E6190", 5953 .num_databases = 4096, 5954 .num_macs = 16384, 5955 .num_ports = 11, /* 10 + Z80 */ 5956 .num_internal_phys = 9, 5957 .num_gpio = 16, 5958 .max_vid = 8191, 5959 .max_sid = 63, 5960 .port_base_addr = 0x0, 5961 .phy_base_addr = 0x0, 5962 .global1_addr = 0x1b, 5963 .global2_addr = 0x1c, 5964 .age_time_coeff = 3750, 5965 .g1_irqs = 9, 5966 .g2_irqs = 14, 5967 .pvt = true, 5968 .multi_chip = true, 5969 .atu_move_port_mask = 0x1f, 5970 .ops = &mv88e6190_ops, 5971 }, 5972 5973 [MV88E6190X] = { 5974 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5975 .family = MV88E6XXX_FAMILY_6390, 5976 .name = "Marvell 88E6190X", 5977 .num_databases = 4096, 5978 .num_macs = 16384, 5979 .num_ports = 11, /* 10 + Z80 */ 5980 .num_internal_phys = 9, 5981 .num_gpio = 16, 5982 .max_vid = 8191, 5983 .max_sid = 63, 5984 .port_base_addr = 0x0, 5985 .phy_base_addr = 0x0, 5986 .global1_addr = 0x1b, 5987 .global2_addr = 0x1c, 5988 .age_time_coeff = 3750, 5989 .g1_irqs = 9, 5990 .g2_irqs = 14, 5991 .atu_move_port_mask = 0x1f, 5992 .pvt = true, 5993 .multi_chip = true, 5994 .ops = &mv88e6190x_ops, 5995 }, 5996 5997 [MV88E6191] = { 5998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5999 .family = MV88E6XXX_FAMILY_6390, 6000 .name = "Marvell 88E6191", 6001 .num_databases = 4096, 6002 .num_macs = 16384, 6003 .num_ports = 11, /* 10 + Z80 */ 6004 .num_internal_phys = 9, 6005 .max_vid = 8191, 6006 .max_sid = 63, 6007 .port_base_addr = 0x0, 6008 .phy_base_addr = 0x0, 6009 .global1_addr = 0x1b, 6010 .global2_addr = 0x1c, 6011 .age_time_coeff = 3750, 6012 .g1_irqs = 9, 6013 .g2_irqs = 14, 6014 .atu_move_port_mask = 0x1f, 6015 .pvt = true, 6016 .multi_chip = true, 6017 .ptp_support = true, 6018 .ops = &mv88e6191_ops, 6019 }, 6020 6021 [MV88E6191X] = { 6022 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6023 .family = MV88E6XXX_FAMILY_6393, 6024 .name = "Marvell 88E6191X", 6025 .num_databases = 4096, 6026 .num_ports = 11, /* 10 + Z80 */ 6027 .num_internal_phys = 9, 6028 .max_vid = 8191, 6029 .max_sid = 63, 6030 .port_base_addr = 0x0, 6031 .phy_base_addr = 0x0, 6032 .global1_addr = 0x1b, 6033 .global2_addr = 0x1c, 6034 .age_time_coeff = 3750, 6035 .g1_irqs = 10, 6036 .g2_irqs = 14, 6037 .atu_move_port_mask = 0x1f, 6038 .pvt = true, 6039 .multi_chip = true, 6040 .ptp_support = true, 6041 .ops = &mv88e6393x_ops, 6042 }, 6043 6044 [MV88E6193X] = { 6045 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6046 .family = MV88E6XXX_FAMILY_6393, 6047 .name = "Marvell 88E6193X", 6048 .num_databases = 4096, 6049 .num_ports = 11, /* 10 + Z80 */ 6050 .num_internal_phys = 9, 6051 .max_vid = 8191, 6052 .max_sid = 63, 6053 .port_base_addr = 0x0, 6054 .phy_base_addr = 0x0, 6055 .global1_addr = 0x1b, 6056 .global2_addr = 0x1c, 6057 .age_time_coeff = 3750, 6058 .g1_irqs = 10, 6059 .g2_irqs = 14, 6060 .atu_move_port_mask = 0x1f, 6061 .pvt = true, 6062 .multi_chip = true, 6063 .ptp_support = true, 6064 .ops = &mv88e6393x_ops, 6065 }, 6066 6067 [MV88E6220] = { 6068 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6069 .family = MV88E6XXX_FAMILY_6250, 6070 .name = "Marvell 88E6220", 6071 .num_databases = 64, 6072 6073 /* Ports 2-4 are not routed to pins 6074 * => usable ports 0, 1, 5, 6 6075 */ 6076 .num_ports = 7, 6077 .num_internal_phys = 2, 6078 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6079 .max_vid = 4095, 6080 .port_base_addr = 0x08, 6081 .phy_base_addr = 0x00, 6082 .global1_addr = 0x0f, 6083 .global2_addr = 0x07, 6084 .age_time_coeff = 15000, 6085 .g1_irqs = 9, 6086 .g2_irqs = 10, 6087 .atu_move_port_mask = 0xf, 6088 .dual_chip = true, 6089 .ptp_support = true, 6090 .ops = &mv88e6250_ops, 6091 }, 6092 6093 [MV88E6240] = { 6094 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6095 .family = MV88E6XXX_FAMILY_6352, 6096 .name = "Marvell 88E6240", 6097 .num_databases = 4096, 6098 .num_macs = 8192, 6099 .num_ports = 7, 6100 .num_internal_phys = 5, 6101 .num_gpio = 15, 6102 .max_vid = 4095, 6103 .max_sid = 63, 6104 .port_base_addr = 0x10, 6105 .phy_base_addr = 0x0, 6106 .global1_addr = 0x1b, 6107 .global2_addr = 0x1c, 6108 .age_time_coeff = 15000, 6109 .g1_irqs = 9, 6110 .g2_irqs = 10, 6111 .atu_move_port_mask = 0xf, 6112 .pvt = true, 6113 .multi_chip = true, 6114 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6115 .ptp_support = true, 6116 .ops = &mv88e6240_ops, 6117 }, 6118 6119 [MV88E6250] = { 6120 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6121 .family = MV88E6XXX_FAMILY_6250, 6122 .name = "Marvell 88E6250", 6123 .num_databases = 64, 6124 .num_ports = 7, 6125 .num_internal_phys = 5, 6126 .max_vid = 4095, 6127 .port_base_addr = 0x08, 6128 .phy_base_addr = 0x00, 6129 .global1_addr = 0x0f, 6130 .global2_addr = 0x07, 6131 .age_time_coeff = 15000, 6132 .g1_irqs = 9, 6133 .g2_irqs = 10, 6134 .atu_move_port_mask = 0xf, 6135 .dual_chip = true, 6136 .ptp_support = true, 6137 .ops = &mv88e6250_ops, 6138 }, 6139 6140 [MV88E6290] = { 6141 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6142 .family = MV88E6XXX_FAMILY_6390, 6143 .name = "Marvell 88E6290", 6144 .num_databases = 4096, 6145 .num_ports = 11, /* 10 + Z80 */ 6146 .num_internal_phys = 9, 6147 .num_gpio = 16, 6148 .max_vid = 8191, 6149 .max_sid = 63, 6150 .port_base_addr = 0x0, 6151 .phy_base_addr = 0x0, 6152 .global1_addr = 0x1b, 6153 .global2_addr = 0x1c, 6154 .age_time_coeff = 3750, 6155 .g1_irqs = 9, 6156 .g2_irqs = 14, 6157 .atu_move_port_mask = 0x1f, 6158 .pvt = true, 6159 .multi_chip = true, 6160 .ptp_support = true, 6161 .ops = &mv88e6290_ops, 6162 }, 6163 6164 [MV88E6320] = { 6165 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6166 .family = MV88E6XXX_FAMILY_6320, 6167 .name = "Marvell 88E6320", 6168 .num_databases = 4096, 6169 .num_macs = 8192, 6170 .num_ports = 7, 6171 .num_internal_phys = 5, 6172 .num_gpio = 15, 6173 .max_vid = 4095, 6174 .port_base_addr = 0x10, 6175 .phy_base_addr = 0x0, 6176 .global1_addr = 0x1b, 6177 .global2_addr = 0x1c, 6178 .age_time_coeff = 15000, 6179 .g1_irqs = 8, 6180 .g2_irqs = 10, 6181 .atu_move_port_mask = 0xf, 6182 .pvt = true, 6183 .multi_chip = true, 6184 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6185 .ptp_support = true, 6186 .ops = &mv88e6320_ops, 6187 }, 6188 6189 [MV88E6321] = { 6190 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6191 .family = MV88E6XXX_FAMILY_6320, 6192 .name = "Marvell 88E6321", 6193 .num_databases = 4096, 6194 .num_macs = 8192, 6195 .num_ports = 7, 6196 .num_internal_phys = 5, 6197 .num_gpio = 15, 6198 .max_vid = 4095, 6199 .port_base_addr = 0x10, 6200 .phy_base_addr = 0x0, 6201 .global1_addr = 0x1b, 6202 .global2_addr = 0x1c, 6203 .age_time_coeff = 15000, 6204 .g1_irqs = 8, 6205 .g2_irqs = 10, 6206 .atu_move_port_mask = 0xf, 6207 .multi_chip = true, 6208 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6209 .ptp_support = true, 6210 .ops = &mv88e6321_ops, 6211 }, 6212 6213 [MV88E6341] = { 6214 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6215 .family = MV88E6XXX_FAMILY_6341, 6216 .name = "Marvell 88E6341", 6217 .num_databases = 4096, 6218 .num_macs = 2048, 6219 .num_internal_phys = 5, 6220 .num_ports = 6, 6221 .num_gpio = 11, 6222 .max_vid = 4095, 6223 .max_sid = 63, 6224 .port_base_addr = 0x10, 6225 .phy_base_addr = 0x10, 6226 .global1_addr = 0x1b, 6227 .global2_addr = 0x1c, 6228 .age_time_coeff = 3750, 6229 .atu_move_port_mask = 0x1f, 6230 .g1_irqs = 9, 6231 .g2_irqs = 10, 6232 .pvt = true, 6233 .multi_chip = true, 6234 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6235 .ptp_support = true, 6236 .ops = &mv88e6341_ops, 6237 }, 6238 6239 [MV88E6350] = { 6240 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6241 .family = MV88E6XXX_FAMILY_6351, 6242 .name = "Marvell 88E6350", 6243 .num_databases = 4096, 6244 .num_macs = 8192, 6245 .num_ports = 7, 6246 .num_internal_phys = 5, 6247 .max_vid = 4095, 6248 .max_sid = 63, 6249 .port_base_addr = 0x10, 6250 .phy_base_addr = 0x0, 6251 .global1_addr = 0x1b, 6252 .global2_addr = 0x1c, 6253 .age_time_coeff = 15000, 6254 .g1_irqs = 9, 6255 .g2_irqs = 10, 6256 .atu_move_port_mask = 0xf, 6257 .pvt = true, 6258 .multi_chip = true, 6259 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6260 .ops = &mv88e6350_ops, 6261 }, 6262 6263 [MV88E6351] = { 6264 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6265 .family = MV88E6XXX_FAMILY_6351, 6266 .name = "Marvell 88E6351", 6267 .num_databases = 4096, 6268 .num_macs = 8192, 6269 .num_ports = 7, 6270 .num_internal_phys = 5, 6271 .max_vid = 4095, 6272 .max_sid = 63, 6273 .port_base_addr = 0x10, 6274 .phy_base_addr = 0x0, 6275 .global1_addr = 0x1b, 6276 .global2_addr = 0x1c, 6277 .age_time_coeff = 15000, 6278 .g1_irqs = 9, 6279 .g2_irqs = 10, 6280 .atu_move_port_mask = 0xf, 6281 .pvt = true, 6282 .multi_chip = true, 6283 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6284 .ops = &mv88e6351_ops, 6285 }, 6286 6287 [MV88E6352] = { 6288 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6289 .family = MV88E6XXX_FAMILY_6352, 6290 .name = "Marvell 88E6352", 6291 .num_databases = 4096, 6292 .num_macs = 8192, 6293 .num_ports = 7, 6294 .num_internal_phys = 5, 6295 .num_gpio = 15, 6296 .max_vid = 4095, 6297 .max_sid = 63, 6298 .port_base_addr = 0x10, 6299 .phy_base_addr = 0x0, 6300 .global1_addr = 0x1b, 6301 .global2_addr = 0x1c, 6302 .age_time_coeff = 15000, 6303 .g1_irqs = 9, 6304 .g2_irqs = 10, 6305 .atu_move_port_mask = 0xf, 6306 .pvt = true, 6307 .multi_chip = true, 6308 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6309 .ptp_support = true, 6310 .ops = &mv88e6352_ops, 6311 }, 6312 [MV88E6390] = { 6313 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6314 .family = MV88E6XXX_FAMILY_6390, 6315 .name = "Marvell 88E6390", 6316 .num_databases = 4096, 6317 .num_macs = 16384, 6318 .num_ports = 11, /* 10 + Z80 */ 6319 .num_internal_phys = 9, 6320 .num_gpio = 16, 6321 .max_vid = 8191, 6322 .max_sid = 63, 6323 .port_base_addr = 0x0, 6324 .phy_base_addr = 0x0, 6325 .global1_addr = 0x1b, 6326 .global2_addr = 0x1c, 6327 .age_time_coeff = 3750, 6328 .g1_irqs = 9, 6329 .g2_irqs = 14, 6330 .atu_move_port_mask = 0x1f, 6331 .pvt = true, 6332 .multi_chip = true, 6333 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6334 .ptp_support = true, 6335 .ops = &mv88e6390_ops, 6336 }, 6337 [MV88E6390X] = { 6338 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6339 .family = MV88E6XXX_FAMILY_6390, 6340 .name = "Marvell 88E6390X", 6341 .num_databases = 4096, 6342 .num_macs = 16384, 6343 .num_ports = 11, /* 10 + Z80 */ 6344 .num_internal_phys = 9, 6345 .num_gpio = 16, 6346 .max_vid = 8191, 6347 .max_sid = 63, 6348 .port_base_addr = 0x0, 6349 .phy_base_addr = 0x0, 6350 .global1_addr = 0x1b, 6351 .global2_addr = 0x1c, 6352 .age_time_coeff = 3750, 6353 .g1_irqs = 9, 6354 .g2_irqs = 14, 6355 .atu_move_port_mask = 0x1f, 6356 .pvt = true, 6357 .multi_chip = true, 6358 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6359 .ptp_support = true, 6360 .ops = &mv88e6390x_ops, 6361 }, 6362 6363 [MV88E6393X] = { 6364 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6365 .family = MV88E6XXX_FAMILY_6393, 6366 .name = "Marvell 88E6393X", 6367 .num_databases = 4096, 6368 .num_ports = 11, /* 10 + Z80 */ 6369 .num_internal_phys = 9, 6370 .max_vid = 8191, 6371 .max_sid = 63, 6372 .port_base_addr = 0x0, 6373 .phy_base_addr = 0x0, 6374 .global1_addr = 0x1b, 6375 .global2_addr = 0x1c, 6376 .age_time_coeff = 3750, 6377 .g1_irqs = 10, 6378 .g2_irqs = 14, 6379 .atu_move_port_mask = 0x1f, 6380 .pvt = true, 6381 .multi_chip = true, 6382 .ptp_support = true, 6383 .ops = &mv88e6393x_ops, 6384 }, 6385 }; 6386 6387 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6388 { 6389 int i; 6390 6391 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6392 if (mv88e6xxx_table[i].prod_num == prod_num) 6393 return &mv88e6xxx_table[i]; 6394 6395 return NULL; 6396 } 6397 6398 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6399 { 6400 const struct mv88e6xxx_info *info; 6401 unsigned int prod_num, rev; 6402 u16 id; 6403 int err; 6404 6405 mv88e6xxx_reg_lock(chip); 6406 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6407 mv88e6xxx_reg_unlock(chip); 6408 if (err) 6409 return err; 6410 6411 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6412 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6413 6414 info = mv88e6xxx_lookup_info(prod_num); 6415 if (!info) 6416 return -ENODEV; 6417 6418 /* Update the compatible info with the probed one */ 6419 chip->info = info; 6420 6421 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6422 chip->info->prod_num, chip->info->name, rev); 6423 6424 return 0; 6425 } 6426 6427 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6428 struct mdio_device *mdiodev) 6429 { 6430 int err; 6431 6432 /* dual_chip takes precedence over single/multi-chip modes */ 6433 if (chip->info->dual_chip) 6434 return -EINVAL; 6435 6436 /* If the mdio addr is 16 indicating the first port address of a switch 6437 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6438 * configured in single chip addressing mode. Setup the smi access as 6439 * single chip addressing mode and attempt to detect the model of the 6440 * switch, if this fails the device is not configured in single chip 6441 * addressing mode. 6442 */ 6443 if (mdiodev->addr != 16) 6444 return -EINVAL; 6445 6446 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6447 if (err) 6448 return err; 6449 6450 return mv88e6xxx_detect(chip); 6451 } 6452 6453 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6454 { 6455 struct mv88e6xxx_chip *chip; 6456 6457 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6458 if (!chip) 6459 return NULL; 6460 6461 chip->dev = dev; 6462 6463 mutex_init(&chip->reg_lock); 6464 INIT_LIST_HEAD(&chip->mdios); 6465 idr_init(&chip->policies); 6466 INIT_LIST_HEAD(&chip->msts); 6467 6468 return chip; 6469 } 6470 6471 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6472 int port, 6473 enum dsa_tag_protocol m) 6474 { 6475 struct mv88e6xxx_chip *chip = ds->priv; 6476 6477 return chip->tag_protocol; 6478 } 6479 6480 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6481 enum dsa_tag_protocol proto) 6482 { 6483 struct mv88e6xxx_chip *chip = ds->priv; 6484 enum dsa_tag_protocol old_protocol; 6485 struct dsa_port *cpu_dp; 6486 int err; 6487 6488 switch (proto) { 6489 case DSA_TAG_PROTO_EDSA: 6490 switch (chip->info->edsa_support) { 6491 case MV88E6XXX_EDSA_UNSUPPORTED: 6492 return -EPROTONOSUPPORT; 6493 case MV88E6XXX_EDSA_UNDOCUMENTED: 6494 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6495 fallthrough; 6496 case MV88E6XXX_EDSA_SUPPORTED: 6497 break; 6498 } 6499 break; 6500 case DSA_TAG_PROTO_DSA: 6501 break; 6502 default: 6503 return -EPROTONOSUPPORT; 6504 } 6505 6506 old_protocol = chip->tag_protocol; 6507 chip->tag_protocol = proto; 6508 6509 mv88e6xxx_reg_lock(chip); 6510 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6511 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6512 if (err) { 6513 mv88e6xxx_reg_unlock(chip); 6514 goto unwind; 6515 } 6516 } 6517 mv88e6xxx_reg_unlock(chip); 6518 6519 return 0; 6520 6521 unwind: 6522 chip->tag_protocol = old_protocol; 6523 6524 mv88e6xxx_reg_lock(chip); 6525 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6526 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6527 mv88e6xxx_reg_unlock(chip); 6528 6529 return err; 6530 } 6531 6532 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6533 const struct switchdev_obj_port_mdb *mdb, 6534 struct dsa_db db) 6535 { 6536 struct mv88e6xxx_chip *chip = ds->priv; 6537 int err; 6538 6539 mv88e6xxx_reg_lock(chip); 6540 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6541 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6542 mv88e6xxx_reg_unlock(chip); 6543 6544 return err; 6545 } 6546 6547 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6548 const struct switchdev_obj_port_mdb *mdb, 6549 struct dsa_db db) 6550 { 6551 struct mv88e6xxx_chip *chip = ds->priv; 6552 int err; 6553 6554 mv88e6xxx_reg_lock(chip); 6555 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6556 mv88e6xxx_reg_unlock(chip); 6557 6558 return err; 6559 } 6560 6561 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6562 struct dsa_mall_mirror_tc_entry *mirror, 6563 bool ingress, 6564 struct netlink_ext_ack *extack) 6565 { 6566 enum mv88e6xxx_egress_direction direction = ingress ? 6567 MV88E6XXX_EGRESS_DIR_INGRESS : 6568 MV88E6XXX_EGRESS_DIR_EGRESS; 6569 struct mv88e6xxx_chip *chip = ds->priv; 6570 bool other_mirrors = false; 6571 int i; 6572 int err; 6573 6574 mutex_lock(&chip->reg_lock); 6575 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6576 mirror->to_local_port) { 6577 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6578 other_mirrors |= ingress ? 6579 chip->ports[i].mirror_ingress : 6580 chip->ports[i].mirror_egress; 6581 6582 /* Can't change egress port when other mirror is active */ 6583 if (other_mirrors) { 6584 err = -EBUSY; 6585 goto out; 6586 } 6587 6588 err = mv88e6xxx_set_egress_port(chip, direction, 6589 mirror->to_local_port); 6590 if (err) 6591 goto out; 6592 } 6593 6594 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6595 out: 6596 mutex_unlock(&chip->reg_lock); 6597 6598 return err; 6599 } 6600 6601 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6602 struct dsa_mall_mirror_tc_entry *mirror) 6603 { 6604 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6605 MV88E6XXX_EGRESS_DIR_INGRESS : 6606 MV88E6XXX_EGRESS_DIR_EGRESS; 6607 struct mv88e6xxx_chip *chip = ds->priv; 6608 bool other_mirrors = false; 6609 int i; 6610 6611 mutex_lock(&chip->reg_lock); 6612 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6613 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6614 6615 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6616 other_mirrors |= mirror->ingress ? 6617 chip->ports[i].mirror_ingress : 6618 chip->ports[i].mirror_egress; 6619 6620 /* Reset egress port when no other mirror is active */ 6621 if (!other_mirrors) { 6622 if (mv88e6xxx_set_egress_port(chip, direction, 6623 dsa_upstream_port(ds, port))) 6624 dev_err(ds->dev, "failed to set egress port\n"); 6625 } 6626 6627 mutex_unlock(&chip->reg_lock); 6628 } 6629 6630 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6631 struct switchdev_brport_flags flags, 6632 struct netlink_ext_ack *extack) 6633 { 6634 struct mv88e6xxx_chip *chip = ds->priv; 6635 const struct mv88e6xxx_ops *ops; 6636 6637 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6638 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6639 return -EINVAL; 6640 6641 ops = chip->info->ops; 6642 6643 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6644 return -EINVAL; 6645 6646 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6647 return -EINVAL; 6648 6649 return 0; 6650 } 6651 6652 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6653 struct switchdev_brport_flags flags, 6654 struct netlink_ext_ack *extack) 6655 { 6656 struct mv88e6xxx_chip *chip = ds->priv; 6657 int err = 0; 6658 6659 mv88e6xxx_reg_lock(chip); 6660 6661 if (flags.mask & BR_LEARNING) { 6662 bool learning = !!(flags.val & BR_LEARNING); 6663 u16 pav = learning ? (1 << port) : 0; 6664 6665 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6666 if (err) 6667 goto out; 6668 } 6669 6670 if (flags.mask & BR_FLOOD) { 6671 bool unicast = !!(flags.val & BR_FLOOD); 6672 6673 err = chip->info->ops->port_set_ucast_flood(chip, port, 6674 unicast); 6675 if (err) 6676 goto out; 6677 } 6678 6679 if (flags.mask & BR_MCAST_FLOOD) { 6680 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6681 6682 err = chip->info->ops->port_set_mcast_flood(chip, port, 6683 multicast); 6684 if (err) 6685 goto out; 6686 } 6687 6688 if (flags.mask & BR_BCAST_FLOOD) { 6689 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6690 6691 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6692 if (err) 6693 goto out; 6694 } 6695 6696 if (flags.mask & BR_PORT_MAB) { 6697 bool mab = !!(flags.val & BR_PORT_MAB); 6698 6699 mv88e6xxx_port_set_mab(chip, port, mab); 6700 } 6701 6702 if (flags.mask & BR_PORT_LOCKED) { 6703 bool locked = !!(flags.val & BR_PORT_LOCKED); 6704 6705 err = mv88e6xxx_port_set_lock(chip, port, locked); 6706 if (err) 6707 goto out; 6708 } 6709 out: 6710 mv88e6xxx_reg_unlock(chip); 6711 6712 return err; 6713 } 6714 6715 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6716 struct dsa_lag lag, 6717 struct netdev_lag_upper_info *info, 6718 struct netlink_ext_ack *extack) 6719 { 6720 struct mv88e6xxx_chip *chip = ds->priv; 6721 struct dsa_port *dp; 6722 int members = 0; 6723 6724 if (!mv88e6xxx_has_lag(chip)) { 6725 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6726 return false; 6727 } 6728 6729 if (!lag.id) 6730 return false; 6731 6732 dsa_lag_foreach_port(dp, ds->dst, &lag) 6733 /* Includes the port joining the LAG */ 6734 members++; 6735 6736 if (members > 8) { 6737 NL_SET_ERR_MSG_MOD(extack, 6738 "Cannot offload more than 8 LAG ports"); 6739 return false; 6740 } 6741 6742 /* We could potentially relax this to include active 6743 * backup in the future. 6744 */ 6745 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6746 NL_SET_ERR_MSG_MOD(extack, 6747 "Can only offload LAG using hash TX type"); 6748 return false; 6749 } 6750 6751 /* Ideally we would also validate that the hash type matches 6752 * the hardware. Alas, this is always set to unknown on team 6753 * interfaces. 6754 */ 6755 return true; 6756 } 6757 6758 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6759 { 6760 struct mv88e6xxx_chip *chip = ds->priv; 6761 struct dsa_port *dp; 6762 u16 map = 0; 6763 int id; 6764 6765 /* DSA LAG IDs are one-based, hardware is zero-based */ 6766 id = lag.id - 1; 6767 6768 /* Build the map of all ports to distribute flows destined for 6769 * this LAG. This can be either a local user port, or a DSA 6770 * port if the LAG port is on a remote chip. 6771 */ 6772 dsa_lag_foreach_port(dp, ds->dst, &lag) 6773 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6774 6775 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6776 } 6777 6778 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6779 /* Row number corresponds to the number of active members in a 6780 * LAG. Each column states which of the eight hash buckets are 6781 * mapped to the column:th port in the LAG. 6782 * 6783 * Example: In a LAG with three active ports, the second port 6784 * ([2][1]) would be selected for traffic mapped to buckets 6785 * 3,4,5 (0x38). 6786 */ 6787 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6788 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6789 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6790 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6791 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6792 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6793 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6794 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6795 }; 6796 6797 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6798 int num_tx, int nth) 6799 { 6800 u8 active = 0; 6801 int i; 6802 6803 num_tx = num_tx <= 8 ? num_tx : 8; 6804 if (nth < num_tx) 6805 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6806 6807 for (i = 0; i < 8; i++) { 6808 if (BIT(i) & active) 6809 mask[i] |= BIT(port); 6810 } 6811 } 6812 6813 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6814 { 6815 struct mv88e6xxx_chip *chip = ds->priv; 6816 unsigned int id, num_tx; 6817 struct dsa_port *dp; 6818 struct dsa_lag *lag; 6819 int i, err, nth; 6820 u16 mask[8]; 6821 u16 ivec; 6822 6823 /* Assume no port is a member of any LAG. */ 6824 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6825 6826 /* Disable all masks for ports that _are_ members of a LAG. */ 6827 dsa_switch_for_each_port(dp, ds) { 6828 if (!dp->lag) 6829 continue; 6830 6831 ivec &= ~BIT(dp->index); 6832 } 6833 6834 for (i = 0; i < 8; i++) 6835 mask[i] = ivec; 6836 6837 /* Enable the correct subset of masks for all LAG ports that 6838 * are in the Tx set. 6839 */ 6840 dsa_lags_foreach_id(id, ds->dst) { 6841 lag = dsa_lag_by_id(ds->dst, id); 6842 if (!lag) 6843 continue; 6844 6845 num_tx = 0; 6846 dsa_lag_foreach_port(dp, ds->dst, lag) { 6847 if (dp->lag_tx_enabled) 6848 num_tx++; 6849 } 6850 6851 if (!num_tx) 6852 continue; 6853 6854 nth = 0; 6855 dsa_lag_foreach_port(dp, ds->dst, lag) { 6856 if (!dp->lag_tx_enabled) 6857 continue; 6858 6859 if (dp->ds == ds) 6860 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6861 num_tx, nth); 6862 6863 nth++; 6864 } 6865 } 6866 6867 for (i = 0; i < 8; i++) { 6868 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6869 if (err) 6870 return err; 6871 } 6872 6873 return 0; 6874 } 6875 6876 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6877 struct dsa_lag lag) 6878 { 6879 int err; 6880 6881 err = mv88e6xxx_lag_sync_masks(ds); 6882 6883 if (!err) 6884 err = mv88e6xxx_lag_sync_map(ds, lag); 6885 6886 return err; 6887 } 6888 6889 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6890 { 6891 struct mv88e6xxx_chip *chip = ds->priv; 6892 int err; 6893 6894 mv88e6xxx_reg_lock(chip); 6895 err = mv88e6xxx_lag_sync_masks(ds); 6896 mv88e6xxx_reg_unlock(chip); 6897 return err; 6898 } 6899 6900 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6901 struct dsa_lag lag, 6902 struct netdev_lag_upper_info *info, 6903 struct netlink_ext_ack *extack) 6904 { 6905 struct mv88e6xxx_chip *chip = ds->priv; 6906 int err, id; 6907 6908 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6909 return -EOPNOTSUPP; 6910 6911 /* DSA LAG IDs are one-based */ 6912 id = lag.id - 1; 6913 6914 mv88e6xxx_reg_lock(chip); 6915 6916 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6917 if (err) 6918 goto err_unlock; 6919 6920 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6921 if (err) 6922 goto err_clear_trunk; 6923 6924 mv88e6xxx_reg_unlock(chip); 6925 return 0; 6926 6927 err_clear_trunk: 6928 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6929 err_unlock: 6930 mv88e6xxx_reg_unlock(chip); 6931 return err; 6932 } 6933 6934 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6935 struct dsa_lag lag) 6936 { 6937 struct mv88e6xxx_chip *chip = ds->priv; 6938 int err_sync, err_trunk; 6939 6940 mv88e6xxx_reg_lock(chip); 6941 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6942 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6943 mv88e6xxx_reg_unlock(chip); 6944 return err_sync ? : err_trunk; 6945 } 6946 6947 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6948 int port) 6949 { 6950 struct mv88e6xxx_chip *chip = ds->priv; 6951 int err; 6952 6953 mv88e6xxx_reg_lock(chip); 6954 err = mv88e6xxx_lag_sync_masks(ds); 6955 mv88e6xxx_reg_unlock(chip); 6956 return err; 6957 } 6958 6959 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6960 int port, struct dsa_lag lag, 6961 struct netdev_lag_upper_info *info, 6962 struct netlink_ext_ack *extack) 6963 { 6964 struct mv88e6xxx_chip *chip = ds->priv; 6965 int err; 6966 6967 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6968 return -EOPNOTSUPP; 6969 6970 mv88e6xxx_reg_lock(chip); 6971 6972 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6973 if (err) 6974 goto unlock; 6975 6976 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6977 6978 unlock: 6979 mv88e6xxx_reg_unlock(chip); 6980 return err; 6981 } 6982 6983 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6984 int port, struct dsa_lag lag) 6985 { 6986 struct mv88e6xxx_chip *chip = ds->priv; 6987 int err_sync, err_pvt; 6988 6989 mv88e6xxx_reg_lock(chip); 6990 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6991 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6992 mv88e6xxx_reg_unlock(chip); 6993 return err_sync ? : err_pvt; 6994 } 6995 6996 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6997 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6998 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6999 .setup = mv88e6xxx_setup, 7000 .teardown = mv88e6xxx_teardown, 7001 .port_setup = mv88e6xxx_port_setup, 7002 .port_teardown = mv88e6xxx_port_teardown, 7003 .phylink_get_caps = mv88e6xxx_get_caps, 7004 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 7005 .phylink_mac_config = mv88e6xxx_mac_config, 7006 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 7007 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 7008 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 7009 .get_strings = mv88e6xxx_get_strings, 7010 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7011 .get_sset_count = mv88e6xxx_get_sset_count, 7012 .port_enable = mv88e6xxx_port_enable, 7013 .port_disable = mv88e6xxx_port_disable, 7014 .port_max_mtu = mv88e6xxx_get_max_mtu, 7015 .port_change_mtu = mv88e6xxx_change_mtu, 7016 .get_mac_eee = mv88e6xxx_get_mac_eee, 7017 .set_mac_eee = mv88e6xxx_set_mac_eee, 7018 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7019 .get_eeprom = mv88e6xxx_get_eeprom, 7020 .set_eeprom = mv88e6xxx_set_eeprom, 7021 .get_regs_len = mv88e6xxx_get_regs_len, 7022 .get_regs = mv88e6xxx_get_regs, 7023 .get_rxnfc = mv88e6xxx_get_rxnfc, 7024 .set_rxnfc = mv88e6xxx_set_rxnfc, 7025 .set_ageing_time = mv88e6xxx_set_ageing_time, 7026 .port_bridge_join = mv88e6xxx_port_bridge_join, 7027 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7028 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7029 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7030 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7031 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7032 .port_fast_age = mv88e6xxx_port_fast_age, 7033 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7034 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7035 .port_vlan_add = mv88e6xxx_port_vlan_add, 7036 .port_vlan_del = mv88e6xxx_port_vlan_del, 7037 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7038 .port_fdb_add = mv88e6xxx_port_fdb_add, 7039 .port_fdb_del = mv88e6xxx_port_fdb_del, 7040 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7041 .port_mdb_add = mv88e6xxx_port_mdb_add, 7042 .port_mdb_del = mv88e6xxx_port_mdb_del, 7043 .port_mirror_add = mv88e6xxx_port_mirror_add, 7044 .port_mirror_del = mv88e6xxx_port_mirror_del, 7045 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7046 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7047 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7048 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7049 .port_txtstamp = mv88e6xxx_port_txtstamp, 7050 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7051 .get_ts_info = mv88e6xxx_get_ts_info, 7052 .devlink_param_get = mv88e6xxx_devlink_param_get, 7053 .devlink_param_set = mv88e6xxx_devlink_param_set, 7054 .devlink_info_get = mv88e6xxx_devlink_info_get, 7055 .port_lag_change = mv88e6xxx_port_lag_change, 7056 .port_lag_join = mv88e6xxx_port_lag_join, 7057 .port_lag_leave = mv88e6xxx_port_lag_leave, 7058 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7059 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7060 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7061 }; 7062 7063 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7064 { 7065 struct device *dev = chip->dev; 7066 struct dsa_switch *ds; 7067 7068 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7069 if (!ds) 7070 return -ENOMEM; 7071 7072 ds->dev = dev; 7073 ds->num_ports = mv88e6xxx_num_ports(chip); 7074 ds->priv = chip; 7075 ds->dev = dev; 7076 ds->ops = &mv88e6xxx_switch_ops; 7077 ds->ageing_time_min = chip->info->age_time_coeff; 7078 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7079 7080 /* Some chips support up to 32, but that requires enabling the 7081 * 5-bit port mode, which we do not support. 640k^W16 ought to 7082 * be enough for anyone. 7083 */ 7084 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7085 7086 dev_set_drvdata(dev, ds); 7087 7088 return dsa_register_switch(ds); 7089 } 7090 7091 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7092 { 7093 dsa_unregister_switch(chip->ds); 7094 } 7095 7096 static const void *pdata_device_get_match_data(struct device *dev) 7097 { 7098 const struct of_device_id *matches = dev->driver->of_match_table; 7099 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7100 7101 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7102 matches++) { 7103 if (!strcmp(pdata->compatible, matches->compatible)) 7104 return matches->data; 7105 } 7106 return NULL; 7107 } 7108 7109 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7110 * would be lost after a power cycle so prevent it to be suspended. 7111 */ 7112 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7113 { 7114 return -EOPNOTSUPP; 7115 } 7116 7117 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7118 { 7119 return 0; 7120 } 7121 7122 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7123 7124 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7125 { 7126 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7127 const struct mv88e6xxx_info *compat_info = NULL; 7128 struct device *dev = &mdiodev->dev; 7129 struct device_node *np = dev->of_node; 7130 struct mv88e6xxx_chip *chip; 7131 int port; 7132 int err; 7133 7134 if (!np && !pdata) 7135 return -EINVAL; 7136 7137 if (np) 7138 compat_info = of_device_get_match_data(dev); 7139 7140 if (pdata) { 7141 compat_info = pdata_device_get_match_data(dev); 7142 7143 if (!pdata->netdev) 7144 return -EINVAL; 7145 7146 for (port = 0; port < DSA_MAX_PORTS; port++) { 7147 if (!(pdata->enabled_ports & (1 << port))) 7148 continue; 7149 if (strcmp(pdata->cd.port_names[port], "cpu")) 7150 continue; 7151 pdata->cd.netdev[port] = &pdata->netdev->dev; 7152 break; 7153 } 7154 } 7155 7156 if (!compat_info) 7157 return -EINVAL; 7158 7159 chip = mv88e6xxx_alloc_chip(dev); 7160 if (!chip) { 7161 err = -ENOMEM; 7162 goto out; 7163 } 7164 7165 chip->info = compat_info; 7166 7167 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7168 if (IS_ERR(chip->reset)) { 7169 err = PTR_ERR(chip->reset); 7170 goto out; 7171 } 7172 if (chip->reset) 7173 usleep_range(10000, 20000); 7174 7175 /* Detect if the device is configured in single chip addressing mode, 7176 * otherwise continue with address specific smi init/detection. 7177 */ 7178 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7179 if (err) { 7180 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7181 if (err) 7182 goto out; 7183 7184 err = mv88e6xxx_detect(chip); 7185 if (err) 7186 goto out; 7187 } 7188 7189 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7190 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7191 else 7192 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7193 7194 mv88e6xxx_phy_init(chip); 7195 7196 if (chip->info->ops->get_eeprom) { 7197 if (np) 7198 of_property_read_u32(np, "eeprom-length", 7199 &chip->eeprom_len); 7200 else 7201 chip->eeprom_len = pdata->eeprom_len; 7202 } 7203 7204 mv88e6xxx_reg_lock(chip); 7205 err = mv88e6xxx_switch_reset(chip); 7206 mv88e6xxx_reg_unlock(chip); 7207 if (err) 7208 goto out; 7209 7210 if (np) { 7211 chip->irq = of_irq_get(np, 0); 7212 if (chip->irq == -EPROBE_DEFER) { 7213 err = chip->irq; 7214 goto out; 7215 } 7216 } 7217 7218 if (pdata) 7219 chip->irq = pdata->irq; 7220 7221 /* Has to be performed before the MDIO bus is created, because 7222 * the PHYs will link their interrupts to these interrupt 7223 * controllers 7224 */ 7225 mv88e6xxx_reg_lock(chip); 7226 if (chip->irq > 0) 7227 err = mv88e6xxx_g1_irq_setup(chip); 7228 else 7229 err = mv88e6xxx_irq_poll_setup(chip); 7230 mv88e6xxx_reg_unlock(chip); 7231 7232 if (err) 7233 goto out; 7234 7235 if (chip->info->g2_irqs > 0) { 7236 err = mv88e6xxx_g2_irq_setup(chip); 7237 if (err) 7238 goto out_g1_irq; 7239 } 7240 7241 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7242 if (err) 7243 goto out_g2_irq; 7244 7245 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7246 if (err) 7247 goto out_g1_atu_prob_irq; 7248 7249 err = mv88e6xxx_register_switch(chip); 7250 if (err) 7251 goto out_g1_vtu_prob_irq; 7252 7253 return 0; 7254 7255 out_g1_vtu_prob_irq: 7256 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7257 out_g1_atu_prob_irq: 7258 mv88e6xxx_g1_atu_prob_irq_free(chip); 7259 out_g2_irq: 7260 if (chip->info->g2_irqs > 0) 7261 mv88e6xxx_g2_irq_free(chip); 7262 out_g1_irq: 7263 if (chip->irq > 0) 7264 mv88e6xxx_g1_irq_free(chip); 7265 else 7266 mv88e6xxx_irq_poll_free(chip); 7267 out: 7268 if (pdata) 7269 dev_put(pdata->netdev); 7270 7271 return err; 7272 } 7273 7274 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7275 { 7276 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7277 struct mv88e6xxx_chip *chip; 7278 7279 if (!ds) 7280 return; 7281 7282 chip = ds->priv; 7283 7284 if (chip->info->ptp_support) { 7285 mv88e6xxx_hwtstamp_free(chip); 7286 mv88e6xxx_ptp_free(chip); 7287 } 7288 7289 mv88e6xxx_phy_destroy(chip); 7290 mv88e6xxx_unregister_switch(chip); 7291 7292 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7293 mv88e6xxx_g1_atu_prob_irq_free(chip); 7294 7295 if (chip->info->g2_irqs > 0) 7296 mv88e6xxx_g2_irq_free(chip); 7297 7298 if (chip->irq > 0) 7299 mv88e6xxx_g1_irq_free(chip); 7300 else 7301 mv88e6xxx_irq_poll_free(chip); 7302 } 7303 7304 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7305 { 7306 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7307 7308 if (!ds) 7309 return; 7310 7311 dsa_switch_shutdown(ds); 7312 7313 dev_set_drvdata(&mdiodev->dev, NULL); 7314 } 7315 7316 static const struct of_device_id mv88e6xxx_of_match[] = { 7317 { 7318 .compatible = "marvell,mv88e6085", 7319 .data = &mv88e6xxx_table[MV88E6085], 7320 }, 7321 { 7322 .compatible = "marvell,mv88e6190", 7323 .data = &mv88e6xxx_table[MV88E6190], 7324 }, 7325 { 7326 .compatible = "marvell,mv88e6250", 7327 .data = &mv88e6xxx_table[MV88E6250], 7328 }, 7329 { /* sentinel */ }, 7330 }; 7331 7332 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7333 7334 static struct mdio_driver mv88e6xxx_driver = { 7335 .probe = mv88e6xxx_probe, 7336 .remove = mv88e6xxx_remove, 7337 .shutdown = mv88e6xxx_shutdown, 7338 .mdiodrv.driver = { 7339 .name = "mv88e6085", 7340 .of_match_table = mv88e6xxx_of_match, 7341 .pm = &mv88e6xxx_pm_ops, 7342 }, 7343 }; 7344 7345 mdio_module_driver(mv88e6xxx_driver); 7346 7347 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7348 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7349 MODULE_LICENSE("GPL"); 7350