1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "serdes.h" 42 43 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 44 { 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 46 dev_err(chip->dev, "Switch registers lock not held!\n"); 47 dump_stack(); 48 } 49 } 50 51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 53 * 54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 55 * is the only device connected to the SMI master. In this mode it responds to 56 * all 32 possible SMI addresses, and thus maps directly the internal devices. 57 * 58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 59 * multiple devices to share the SMI interface. In this mode it responds to only 60 * 2 registers, used to indirectly access the internal SMI devices. 61 */ 62 63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 *val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->read(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 val) 74 { 75 if (!chip->smi_ops) 76 return -EOPNOTSUPP; 77 78 return chip->smi_ops->write(chip, addr, reg, val); 79 } 80 81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 82 int addr, int reg, u16 *val) 83 { 84 int ret; 85 86 ret = mdiobus_read_nested(chip->bus, addr, reg); 87 if (ret < 0) 88 return ret; 89 90 *val = ret & 0xffff; 91 92 return 0; 93 } 94 95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 96 int addr, int reg, u16 val) 97 { 98 int ret; 99 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 101 if (ret < 0) 102 return ret; 103 104 return 0; 105 } 106 107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 108 .read = mv88e6xxx_smi_single_chip_read, 109 .write = mv88e6xxx_smi_single_chip_write, 110 }; 111 112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 113 { 114 int ret; 115 int i; 116 117 for (i = 0; i < 16; i++) { 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 119 if (ret < 0) 120 return ret; 121 122 if ((ret & SMI_CMD_BUSY) == 0) 123 return 0; 124 } 125 126 return -ETIMEDOUT; 127 } 128 129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 130 int addr, int reg, u16 *val) 131 { 132 int ret; 133 134 /* Wait for the bus to become free. */ 135 ret = mv88e6xxx_smi_multi_chip_wait(chip); 136 if (ret < 0) 137 return ret; 138 139 /* Transmit the read command. */ 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 141 SMI_CMD_OP_22_READ | (addr << 5) | reg); 142 if (ret < 0) 143 return ret; 144 145 /* Wait for the read command to complete. */ 146 ret = mv88e6xxx_smi_multi_chip_wait(chip); 147 if (ret < 0) 148 return ret; 149 150 /* Read the data. */ 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 152 if (ret < 0) 153 return ret; 154 155 *val = ret & 0xffff; 156 157 return 0; 158 } 159 160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 161 int addr, int reg, u16 val) 162 { 163 int ret; 164 165 /* Wait for the bus to become free. */ 166 ret = mv88e6xxx_smi_multi_chip_wait(chip); 167 if (ret < 0) 168 return ret; 169 170 /* Transmit the data to write. */ 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 172 if (ret < 0) 173 return ret; 174 175 /* Transmit the write command. */ 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 178 if (ret < 0) 179 return ret; 180 181 /* Wait for the write command to complete. */ 182 ret = mv88e6xxx_smi_multi_chip_wait(chip); 183 if (ret < 0) 184 return ret; 185 186 return 0; 187 } 188 189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 190 .read = mv88e6xxx_smi_multi_chip_read, 191 .write = mv88e6xxx_smi_multi_chip_write, 192 }; 193 194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 195 { 196 int err; 197 198 assert_reg_lock(chip); 199 200 err = mv88e6xxx_smi_read(chip, addr, reg, val); 201 if (err) 202 return err; 203 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 205 addr, reg, *val); 206 207 return 0; 208 } 209 210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 211 { 212 int err; 213 214 assert_reg_lock(chip); 215 216 err = mv88e6xxx_smi_write(chip, addr, reg, val); 217 if (err) 218 return err; 219 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 221 addr, reg, val); 222 223 return 0; 224 } 225 226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 227 { 228 struct mv88e6xxx_mdio_bus *mdio_bus; 229 230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 231 list); 232 if (!mdio_bus) 233 return NULL; 234 235 return mdio_bus->bus; 236 } 237 238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 239 { 240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 241 unsigned int n = d->hwirq; 242 243 chip->g1_irq.masked |= (1 << n); 244 } 245 246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 247 { 248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 249 unsigned int n = d->hwirq; 250 251 chip->g1_irq.masked &= ~(1 << n); 252 } 253 254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 255 { 256 struct mv88e6xxx_chip *chip = dev_id; 257 unsigned int nhandled = 0; 258 unsigned int sub_irq; 259 unsigned int n; 260 u16 reg; 261 int err; 262 263 mutex_lock(&chip->reg_lock); 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 265 mutex_unlock(&chip->reg_lock); 266 267 if (err) 268 goto out; 269 270 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 271 if (reg & (1 << n)) { 272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 273 handle_nested_irq(sub_irq); 274 ++nhandled; 275 } 276 } 277 out: 278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 279 } 280 281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 282 { 283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 284 285 mutex_lock(&chip->reg_lock); 286 } 287 288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 289 { 290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 292 u16 reg; 293 int err; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 296 if (err) 297 goto out; 298 299 reg &= ~mask; 300 reg |= (~chip->g1_irq.masked & mask); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 303 if (err) 304 goto out; 305 306 out: 307 mutex_unlock(&chip->reg_lock); 308 } 309 310 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 311 .name = "mv88e6xxx-g1", 312 .irq_mask = mv88e6xxx_g1_irq_mask, 313 .irq_unmask = mv88e6xxx_g1_irq_unmask, 314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 316 }; 317 318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 319 unsigned int irq, 320 irq_hw_number_t hwirq) 321 { 322 struct mv88e6xxx_chip *chip = d->host_data; 323 324 irq_set_chip_data(irq, d->host_data); 325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 326 irq_set_noprobe(irq); 327 328 return 0; 329 } 330 331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 332 .map = mv88e6xxx_g1_irq_domain_map, 333 .xlate = irq_domain_xlate_twocell, 334 }; 335 336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 337 { 338 int irq, virq; 339 u16 mask; 340 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 342 mask |= GENMASK(chip->g1_irq.nirqs, 0); 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 344 345 free_irq(chip->irq, chip); 346 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 348 virq = irq_find_mapping(chip->g1_irq.domain, irq); 349 irq_dispose_mapping(virq); 350 } 351 352 irq_domain_remove(chip->g1_irq.domain); 353 } 354 355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 356 { 357 int err, irq, virq; 358 u16 reg, mask; 359 360 chip->g1_irq.nirqs = chip->info->g1_irqs; 361 chip->g1_irq.domain = irq_domain_add_simple( 362 NULL, chip->g1_irq.nirqs, 0, 363 &mv88e6xxx_g1_irq_domain_ops, chip); 364 if (!chip->g1_irq.domain) 365 return -ENOMEM; 366 367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 368 irq_create_mapping(chip->g1_irq.domain, irq); 369 370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 371 chip->g1_irq.masked = ~0; 372 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 374 if (err) 375 goto out_mapping; 376 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 378 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 380 if (err) 381 goto out_disable; 382 383 /* Reading the interrupt status clears (most of) them */ 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 385 if (err) 386 goto out_disable; 387 388 err = request_threaded_irq(chip->irq, NULL, 389 mv88e6xxx_g1_irq_thread_fn, 390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 391 dev_name(chip->dev), chip); 392 if (err) 393 goto out_disable; 394 395 return 0; 396 397 out_disable: 398 mask |= GENMASK(chip->g1_irq.nirqs, 0); 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 400 401 out_mapping: 402 for (irq = 0; irq < 16; irq++) { 403 virq = irq_find_mapping(chip->g1_irq.domain, irq); 404 irq_dispose_mapping(virq); 405 } 406 407 irq_domain_remove(chip->g1_irq.domain); 408 409 return err; 410 } 411 412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 413 { 414 int i; 415 416 for (i = 0; i < 16; i++) { 417 u16 val; 418 int err; 419 420 err = mv88e6xxx_read(chip, addr, reg, &val); 421 if (err) 422 return err; 423 424 if (!(val & mask)) 425 return 0; 426 427 usleep_range(1000, 2000); 428 } 429 430 dev_err(chip->dev, "Timeout while waiting for switch\n"); 431 return -ETIMEDOUT; 432 } 433 434 /* Indirect write to single pointer-data register with an Update bit */ 435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 436 { 437 u16 val; 438 int err; 439 440 /* Wait until the previous operation is completed */ 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 442 if (err) 443 return err; 444 445 /* Set the Update bit to trigger a write operation */ 446 val = BIT(15) | update; 447 448 return mv88e6xxx_write(chip, addr, reg, val); 449 } 450 451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 452 int link, int speed, int duplex, 453 phy_interface_t mode) 454 { 455 int err; 456 457 if (!chip->info->ops->port_set_link) 458 return 0; 459 460 /* Port's MAC control must not be changed unless the link is down */ 461 err = chip->info->ops->port_set_link(chip, port, 0); 462 if (err) 463 return err; 464 465 if (chip->info->ops->port_set_speed) { 466 err = chip->info->ops->port_set_speed(chip, port, speed); 467 if (err && err != -EOPNOTSUPP) 468 goto restore_link; 469 } 470 471 if (chip->info->ops->port_set_duplex) { 472 err = chip->info->ops->port_set_duplex(chip, port, duplex); 473 if (err && err != -EOPNOTSUPP) 474 goto restore_link; 475 } 476 477 if (chip->info->ops->port_set_rgmii_delay) { 478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 479 if (err && err != -EOPNOTSUPP) 480 goto restore_link; 481 } 482 483 if (chip->info->ops->port_set_cmode) { 484 err = chip->info->ops->port_set_cmode(chip, port, mode); 485 if (err && err != -EOPNOTSUPP) 486 goto restore_link; 487 } 488 489 err = 0; 490 restore_link: 491 if (chip->info->ops->port_set_link(chip, port, link)) 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 493 494 return err; 495 } 496 497 /* We expect the switch to perform auto negotiation if there is a real 498 * phy. However, in the case of a fixed link phy, we force the port 499 * settings from the fixed link settings. 500 */ 501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 502 struct phy_device *phydev) 503 { 504 struct mv88e6xxx_chip *chip = ds->priv; 505 int err; 506 507 if (!phy_is_pseudo_fixed_link(phydev)) 508 return; 509 510 mutex_lock(&chip->reg_lock); 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 512 phydev->duplex, phydev->interface); 513 mutex_unlock(&chip->reg_lock); 514 515 if (err && err != -EOPNOTSUPP) 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 517 } 518 519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 if (!chip->info->ops->stats_snapshot) 522 return -EOPNOTSUPP; 523 524 return chip->info->ops->stats_snapshot(chip, port); 525 } 526 527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 548 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 551 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 587 }; 588 589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 590 struct mv88e6xxx_hw_stat *s, 591 int port, u16 bank1_select, 592 u16 histogram) 593 { 594 u32 low; 595 u32 high = 0; 596 u16 reg = 0; 597 int err; 598 u64 value; 599 600 switch (s->type) { 601 case STATS_TYPE_PORT: 602 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 603 if (err) 604 return UINT64_MAX; 605 606 low = reg; 607 if (s->sizeof_stat == 4) { 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 609 if (err) 610 return UINT64_MAX; 611 high = reg; 612 } 613 break; 614 case STATS_TYPE_BANK1: 615 reg = bank1_select; 616 /* fall through */ 617 case STATS_TYPE_BANK0: 618 reg |= s->reg | histogram; 619 mv88e6xxx_g1_stats_read(chip, reg, &low); 620 if (s->sizeof_stat == 8) 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 622 break; 623 default: 624 return UINT64_MAX; 625 } 626 value = (((u64)high) << 16) | low; 627 return value; 628 } 629 630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 631 uint8_t *data, int types) 632 { 633 struct mv88e6xxx_hw_stat *stat; 634 int i, j; 635 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 637 stat = &mv88e6xxx_hw_stats[i]; 638 if (stat->type & types) { 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 640 ETH_GSTRING_LEN); 641 j++; 642 } 643 } 644 } 645 646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 647 uint8_t *data) 648 { 649 mv88e6xxx_stats_get_strings(chip, data, 650 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 651 } 652 653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 654 uint8_t *data) 655 { 656 mv88e6xxx_stats_get_strings(chip, data, 657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 658 } 659 660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 661 uint8_t *data) 662 { 663 struct mv88e6xxx_chip *chip = ds->priv; 664 665 if (chip->info->ops->stats_get_strings) 666 chip->info->ops->stats_get_strings(chip, data); 667 } 668 669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 670 int types) 671 { 672 struct mv88e6xxx_hw_stat *stat; 673 int i, j; 674 675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 676 stat = &mv88e6xxx_hw_stats[i]; 677 if (stat->type & types) 678 j++; 679 } 680 return j; 681 } 682 683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 684 { 685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 686 STATS_TYPE_PORT); 687 } 688 689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 692 STATS_TYPE_BANK1); 693 } 694 695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 696 { 697 struct mv88e6xxx_chip *chip = ds->priv; 698 699 if (chip->info->ops->stats_get_sset_count) 700 return chip->info->ops->stats_get_sset_count(chip); 701 702 return 0; 703 } 704 705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 706 uint64_t *data, int types, 707 u16 bank1_select, u16 histogram) 708 { 709 struct mv88e6xxx_hw_stat *stat; 710 int i, j; 711 712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 713 stat = &mv88e6xxx_hw_stats[i]; 714 if (stat->type & types) { 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 716 bank1_select, 717 histogram); 718 j++; 719 } 720 } 721 } 722 723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 724 uint64_t *data) 725 { 726 return mv88e6xxx_stats_get_stats(chip, port, data, 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 729 } 730 731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 732 uint64_t *data) 733 { 734 return mv88e6xxx_stats_get_stats(chip, port, data, 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 738 } 739 740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 741 uint64_t *data) 742 { 743 return mv88e6xxx_stats_get_stats(chip, port, data, 744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 746 0); 747 } 748 749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 750 uint64_t *data) 751 { 752 if (chip->info->ops->stats_get_stats) 753 chip->info->ops->stats_get_stats(chip, port, data); 754 } 755 756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 757 uint64_t *data) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 int ret; 761 762 mutex_lock(&chip->reg_lock); 763 764 ret = mv88e6xxx_stats_snapshot(chip, port); 765 if (ret < 0) { 766 mutex_unlock(&chip->reg_lock); 767 return; 768 } 769 770 mv88e6xxx_get_stats(chip, port, data); 771 772 mutex_unlock(&chip->reg_lock); 773 } 774 775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 776 { 777 if (chip->info->ops->stats_set_histogram) 778 return chip->info->ops->stats_set_histogram(chip); 779 780 return 0; 781 } 782 783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 784 { 785 return 32 * sizeof(u16); 786 } 787 788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 789 struct ethtool_regs *regs, void *_p) 790 { 791 struct mv88e6xxx_chip *chip = ds->priv; 792 int err; 793 u16 reg; 794 u16 *p = _p; 795 int i; 796 797 regs->version = 0; 798 799 memset(p, 0xff, 32 * sizeof(u16)); 800 801 mutex_lock(&chip->reg_lock); 802 803 for (i = 0; i < 32; i++) { 804 805 err = mv88e6xxx_port_read(chip, port, i, ®); 806 if (!err) 807 p[i] = reg; 808 } 809 810 mutex_unlock(&chip->reg_lock); 811 } 812 813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 814 struct ethtool_eee *e) 815 { 816 /* Nothing to do on the port's MAC */ 817 return 0; 818 } 819 820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 821 struct ethtool_eee *e) 822 { 823 /* Nothing to do on the port's MAC */ 824 return 0; 825 } 826 827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 828 { 829 struct dsa_switch *ds = NULL; 830 struct net_device *br; 831 u16 pvlan; 832 int i; 833 834 if (dev < DSA_MAX_SWITCHES) 835 ds = chip->ds->dst->ds[dev]; 836 837 /* Prevent frames from unknown switch or port */ 838 if (!ds || port >= ds->num_ports) 839 return 0; 840 841 /* Frames from DSA links and CPU ports can egress any local port */ 842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 843 return mv88e6xxx_port_mask(chip); 844 845 br = ds->ports[port].bridge_dev; 846 pvlan = 0; 847 848 /* Frames from user ports can egress any local DSA links and CPU ports, 849 * as well as any local member of their bridge group. 850 */ 851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 852 if (dsa_is_cpu_port(chip->ds, i) || 853 dsa_is_dsa_port(chip->ds, i) || 854 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 855 pvlan |= BIT(i); 856 857 return pvlan; 858 } 859 860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 861 { 862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 863 864 /* prevent frames from going back out of the port they came in on */ 865 output_ports &= ~BIT(port); 866 867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 868 } 869 870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 871 u8 state) 872 { 873 struct mv88e6xxx_chip *chip = ds->priv; 874 int err; 875 876 mutex_lock(&chip->reg_lock); 877 err = mv88e6xxx_port_set_state(chip, port, state); 878 mutex_unlock(&chip->reg_lock); 879 880 if (err) 881 dev_err(ds->dev, "p%d: failed to update state\n", port); 882 } 883 884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 885 { 886 if (chip->info->ops->pot_clear) 887 return chip->info->ops->pot_clear(chip); 888 889 return 0; 890 } 891 892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 893 { 894 if (chip->info->ops->mgmt_rsvd2cpu) 895 return chip->info->ops->mgmt_rsvd2cpu(chip); 896 897 return 0; 898 } 899 900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 901 { 902 int err; 903 904 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 905 if (err) 906 return err; 907 908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 909 if (err) 910 return err; 911 912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 913 } 914 915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 916 { 917 int port; 918 int err; 919 920 if (!chip->info->ops->irl_init_all) 921 return 0; 922 923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 924 /* Disable ingress rate limiting by resetting all per port 925 * ingress rate limit resources to their initial state. 926 */ 927 err = chip->info->ops->irl_init_all(chip, port); 928 if (err) 929 return err; 930 } 931 932 return 0; 933 } 934 935 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 936 { 937 if (chip->info->ops->set_switch_mac) { 938 u8 addr[ETH_ALEN]; 939 940 eth_random_addr(addr); 941 942 return chip->info->ops->set_switch_mac(chip, addr); 943 } 944 945 return 0; 946 } 947 948 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 949 { 950 u16 pvlan = 0; 951 952 if (!mv88e6xxx_has_pvt(chip)) 953 return -EOPNOTSUPP; 954 955 /* Skip the local source device, which uses in-chip port VLAN */ 956 if (dev != chip->ds->index) 957 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 958 959 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 960 } 961 962 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 963 { 964 int dev, port; 965 int err; 966 967 if (!mv88e6xxx_has_pvt(chip)) 968 return 0; 969 970 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 971 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 972 */ 973 err = mv88e6xxx_g2_misc_4_bit_port(chip); 974 if (err) 975 return err; 976 977 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 978 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 979 err = mv88e6xxx_pvt_map(chip, dev, port); 980 if (err) 981 return err; 982 } 983 } 984 985 return 0; 986 } 987 988 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 989 { 990 struct mv88e6xxx_chip *chip = ds->priv; 991 int err; 992 993 mutex_lock(&chip->reg_lock); 994 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 995 mutex_unlock(&chip->reg_lock); 996 997 if (err) 998 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 999 } 1000 1001 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1002 { 1003 if (!chip->info->max_vid) 1004 return 0; 1005 1006 return mv88e6xxx_g1_vtu_flush(chip); 1007 } 1008 1009 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1010 struct mv88e6xxx_vtu_entry *entry) 1011 { 1012 if (!chip->info->ops->vtu_getnext) 1013 return -EOPNOTSUPP; 1014 1015 return chip->info->ops->vtu_getnext(chip, entry); 1016 } 1017 1018 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1019 struct mv88e6xxx_vtu_entry *entry) 1020 { 1021 if (!chip->info->ops->vtu_loadpurge) 1022 return -EOPNOTSUPP; 1023 1024 return chip->info->ops->vtu_loadpurge(chip, entry); 1025 } 1026 1027 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1028 { 1029 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1030 struct mv88e6xxx_vtu_entry vlan = { 1031 .vid = chip->info->max_vid, 1032 }; 1033 int i, err; 1034 1035 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1036 1037 /* Set every FID bit used by the (un)bridged ports */ 1038 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1039 err = mv88e6xxx_port_get_fid(chip, i, fid); 1040 if (err) 1041 return err; 1042 1043 set_bit(*fid, fid_bitmap); 1044 } 1045 1046 /* Set every FID bit used by the VLAN entries */ 1047 do { 1048 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1049 if (err) 1050 return err; 1051 1052 if (!vlan.valid) 1053 break; 1054 1055 set_bit(vlan.fid, fid_bitmap); 1056 } while (vlan.vid < chip->info->max_vid); 1057 1058 /* The reset value 0x000 is used to indicate that multiple address 1059 * databases are not needed. Return the next positive available. 1060 */ 1061 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1062 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1063 return -ENOSPC; 1064 1065 /* Clear the database */ 1066 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1067 } 1068 1069 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1070 struct mv88e6xxx_vtu_entry *entry, bool new) 1071 { 1072 int err; 1073 1074 if (!vid) 1075 return -EINVAL; 1076 1077 entry->vid = vid - 1; 1078 entry->valid = false; 1079 1080 err = mv88e6xxx_vtu_getnext(chip, entry); 1081 if (err) 1082 return err; 1083 1084 if (entry->vid == vid && entry->valid) 1085 return 0; 1086 1087 if (new) { 1088 int i; 1089 1090 /* Initialize a fresh VLAN entry */ 1091 memset(entry, 0, sizeof(*entry)); 1092 entry->valid = true; 1093 entry->vid = vid; 1094 1095 /* Exclude all ports */ 1096 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1097 entry->member[i] = 1098 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1099 1100 return mv88e6xxx_atu_new(chip, &entry->fid); 1101 } 1102 1103 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1104 return -EOPNOTSUPP; 1105 } 1106 1107 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1108 u16 vid_begin, u16 vid_end) 1109 { 1110 struct mv88e6xxx_chip *chip = ds->priv; 1111 struct mv88e6xxx_vtu_entry vlan = { 1112 .vid = vid_begin - 1, 1113 }; 1114 int i, err; 1115 1116 /* DSA and CPU ports have to be members of multiple vlans */ 1117 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1118 return 0; 1119 1120 if (!vid_begin) 1121 return -EOPNOTSUPP; 1122 1123 mutex_lock(&chip->reg_lock); 1124 1125 do { 1126 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1127 if (err) 1128 goto unlock; 1129 1130 if (!vlan.valid) 1131 break; 1132 1133 if (vlan.vid > vid_end) 1134 break; 1135 1136 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1137 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1138 continue; 1139 1140 if (!ds->ports[i].slave) 1141 continue; 1142 1143 if (vlan.member[i] == 1144 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1145 continue; 1146 1147 if (dsa_to_port(ds, i)->bridge_dev == 1148 ds->ports[port].bridge_dev) 1149 break; /* same bridge, check next VLAN */ 1150 1151 if (!dsa_to_port(ds, i)->bridge_dev) 1152 continue; 1153 1154 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1155 port, vlan.vid, i, 1156 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1157 err = -EOPNOTSUPP; 1158 goto unlock; 1159 } 1160 } while (vlan.vid < vid_end); 1161 1162 unlock: 1163 mutex_unlock(&chip->reg_lock); 1164 1165 return err; 1166 } 1167 1168 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1169 bool vlan_filtering) 1170 { 1171 struct mv88e6xxx_chip *chip = ds->priv; 1172 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1173 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1174 int err; 1175 1176 if (!chip->info->max_vid) 1177 return -EOPNOTSUPP; 1178 1179 mutex_lock(&chip->reg_lock); 1180 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1181 mutex_unlock(&chip->reg_lock); 1182 1183 return err; 1184 } 1185 1186 static int 1187 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1188 const struct switchdev_obj_port_vlan *vlan, 1189 struct switchdev_trans *trans) 1190 { 1191 struct mv88e6xxx_chip *chip = ds->priv; 1192 int err; 1193 1194 if (!chip->info->max_vid) 1195 return -EOPNOTSUPP; 1196 1197 /* If the requested port doesn't belong to the same bridge as the VLAN 1198 * members, do not support it (yet) and fallback to software VLAN. 1199 */ 1200 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1201 vlan->vid_end); 1202 if (err) 1203 return err; 1204 1205 /* We don't need any dynamic resource from the kernel (yet), 1206 * so skip the prepare phase. 1207 */ 1208 return 0; 1209 } 1210 1211 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1212 const unsigned char *addr, u16 vid, 1213 u8 state) 1214 { 1215 struct mv88e6xxx_vtu_entry vlan; 1216 struct mv88e6xxx_atu_entry entry; 1217 int err; 1218 1219 /* Null VLAN ID corresponds to the port private database */ 1220 if (vid == 0) 1221 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1222 else 1223 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1224 if (err) 1225 return err; 1226 1227 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1228 ether_addr_copy(entry.mac, addr); 1229 eth_addr_dec(entry.mac); 1230 1231 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1232 if (err) 1233 return err; 1234 1235 /* Initialize a fresh ATU entry if it isn't found */ 1236 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1237 !ether_addr_equal(entry.mac, addr)) { 1238 memset(&entry, 0, sizeof(entry)); 1239 ether_addr_copy(entry.mac, addr); 1240 } 1241 1242 /* Purge the ATU entry only if no port is using it anymore */ 1243 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1244 entry.portvec &= ~BIT(port); 1245 if (!entry.portvec) 1246 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1247 } else { 1248 entry.portvec |= BIT(port); 1249 entry.state = state; 1250 } 1251 1252 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1253 } 1254 1255 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1256 u16 vid) 1257 { 1258 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1259 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1260 1261 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1262 } 1263 1264 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1265 { 1266 int port; 1267 int err; 1268 1269 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1270 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1271 if (err) 1272 return err; 1273 } 1274 1275 return 0; 1276 } 1277 1278 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1279 u16 vid, u8 member) 1280 { 1281 struct mv88e6xxx_vtu_entry vlan; 1282 int err; 1283 1284 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1285 if (err) 1286 return err; 1287 1288 vlan.member[port] = member; 1289 1290 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1291 if (err) 1292 return err; 1293 1294 return mv88e6xxx_broadcast_setup(chip, vid); 1295 } 1296 1297 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1298 const struct switchdev_obj_port_vlan *vlan, 1299 struct switchdev_trans *trans) 1300 { 1301 struct mv88e6xxx_chip *chip = ds->priv; 1302 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1303 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1304 u8 member; 1305 u16 vid; 1306 1307 if (!chip->info->max_vid) 1308 return; 1309 1310 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1311 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1312 else if (untagged) 1313 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1314 else 1315 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1316 1317 mutex_lock(&chip->reg_lock); 1318 1319 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1320 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1321 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1322 vid, untagged ? 'u' : 't'); 1323 1324 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1325 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1326 vlan->vid_end); 1327 1328 mutex_unlock(&chip->reg_lock); 1329 } 1330 1331 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1332 int port, u16 vid) 1333 { 1334 struct mv88e6xxx_vtu_entry vlan; 1335 int i, err; 1336 1337 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1338 if (err) 1339 return err; 1340 1341 /* Tell switchdev if this VLAN is handled in software */ 1342 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1343 return -EOPNOTSUPP; 1344 1345 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1346 1347 /* keep the VLAN unless all ports are excluded */ 1348 vlan.valid = false; 1349 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1350 if (vlan.member[i] != 1351 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1352 vlan.valid = true; 1353 break; 1354 } 1355 } 1356 1357 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1358 if (err) 1359 return err; 1360 1361 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1362 } 1363 1364 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1365 const struct switchdev_obj_port_vlan *vlan) 1366 { 1367 struct mv88e6xxx_chip *chip = ds->priv; 1368 u16 pvid, vid; 1369 int err = 0; 1370 1371 if (!chip->info->max_vid) 1372 return -EOPNOTSUPP; 1373 1374 mutex_lock(&chip->reg_lock); 1375 1376 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1377 if (err) 1378 goto unlock; 1379 1380 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1381 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1382 if (err) 1383 goto unlock; 1384 1385 if (vid == pvid) { 1386 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1387 if (err) 1388 goto unlock; 1389 } 1390 } 1391 1392 unlock: 1393 mutex_unlock(&chip->reg_lock); 1394 1395 return err; 1396 } 1397 1398 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1399 const unsigned char *addr, u16 vid) 1400 { 1401 struct mv88e6xxx_chip *chip = ds->priv; 1402 int err; 1403 1404 mutex_lock(&chip->reg_lock); 1405 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1406 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1407 mutex_unlock(&chip->reg_lock); 1408 1409 return err; 1410 } 1411 1412 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1413 const unsigned char *addr, u16 vid) 1414 { 1415 struct mv88e6xxx_chip *chip = ds->priv; 1416 int err; 1417 1418 mutex_lock(&chip->reg_lock); 1419 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1420 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1421 mutex_unlock(&chip->reg_lock); 1422 1423 return err; 1424 } 1425 1426 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1427 u16 fid, u16 vid, int port, 1428 dsa_fdb_dump_cb_t *cb, void *data) 1429 { 1430 struct mv88e6xxx_atu_entry addr; 1431 bool is_static; 1432 int err; 1433 1434 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1435 eth_broadcast_addr(addr.mac); 1436 1437 do { 1438 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1439 if (err) 1440 return err; 1441 1442 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1443 break; 1444 1445 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1446 continue; 1447 1448 if (!is_unicast_ether_addr(addr.mac)) 1449 continue; 1450 1451 is_static = (addr.state == 1452 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1453 err = cb(addr.mac, vid, is_static, data); 1454 if (err) 1455 return err; 1456 } while (!is_broadcast_ether_addr(addr.mac)); 1457 1458 return err; 1459 } 1460 1461 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1462 dsa_fdb_dump_cb_t *cb, void *data) 1463 { 1464 struct mv88e6xxx_vtu_entry vlan = { 1465 .vid = chip->info->max_vid, 1466 }; 1467 u16 fid; 1468 int err; 1469 1470 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1471 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1472 if (err) 1473 return err; 1474 1475 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1476 if (err) 1477 return err; 1478 1479 /* Dump VLANs' Filtering Information Databases */ 1480 do { 1481 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1482 if (err) 1483 return err; 1484 1485 if (!vlan.valid) 1486 break; 1487 1488 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1489 cb, data); 1490 if (err) 1491 return err; 1492 } while (vlan.vid < chip->info->max_vid); 1493 1494 return err; 1495 } 1496 1497 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1498 dsa_fdb_dump_cb_t *cb, void *data) 1499 { 1500 struct mv88e6xxx_chip *chip = ds->priv; 1501 int err; 1502 1503 mutex_lock(&chip->reg_lock); 1504 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1505 mutex_unlock(&chip->reg_lock); 1506 1507 return err; 1508 } 1509 1510 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1511 struct net_device *br) 1512 { 1513 struct dsa_switch *ds; 1514 int port; 1515 int dev; 1516 int err; 1517 1518 /* Remap the Port VLAN of each local bridge group member */ 1519 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1520 if (chip->ds->ports[port].bridge_dev == br) { 1521 err = mv88e6xxx_port_vlan_map(chip, port); 1522 if (err) 1523 return err; 1524 } 1525 } 1526 1527 if (!mv88e6xxx_has_pvt(chip)) 1528 return 0; 1529 1530 /* Remap the Port VLAN of each cross-chip bridge group member */ 1531 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1532 ds = chip->ds->dst->ds[dev]; 1533 if (!ds) 1534 break; 1535 1536 for (port = 0; port < ds->num_ports; ++port) { 1537 if (ds->ports[port].bridge_dev == br) { 1538 err = mv88e6xxx_pvt_map(chip, dev, port); 1539 if (err) 1540 return err; 1541 } 1542 } 1543 } 1544 1545 return 0; 1546 } 1547 1548 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1549 struct net_device *br) 1550 { 1551 struct mv88e6xxx_chip *chip = ds->priv; 1552 int err; 1553 1554 mutex_lock(&chip->reg_lock); 1555 err = mv88e6xxx_bridge_map(chip, br); 1556 mutex_unlock(&chip->reg_lock); 1557 1558 return err; 1559 } 1560 1561 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1562 struct net_device *br) 1563 { 1564 struct mv88e6xxx_chip *chip = ds->priv; 1565 1566 mutex_lock(&chip->reg_lock); 1567 if (mv88e6xxx_bridge_map(chip, br) || 1568 mv88e6xxx_port_vlan_map(chip, port)) 1569 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1570 mutex_unlock(&chip->reg_lock); 1571 } 1572 1573 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1574 int port, struct net_device *br) 1575 { 1576 struct mv88e6xxx_chip *chip = ds->priv; 1577 int err; 1578 1579 if (!mv88e6xxx_has_pvt(chip)) 1580 return 0; 1581 1582 mutex_lock(&chip->reg_lock); 1583 err = mv88e6xxx_pvt_map(chip, dev, port); 1584 mutex_unlock(&chip->reg_lock); 1585 1586 return err; 1587 } 1588 1589 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1590 int port, struct net_device *br) 1591 { 1592 struct mv88e6xxx_chip *chip = ds->priv; 1593 1594 if (!mv88e6xxx_has_pvt(chip)) 1595 return; 1596 1597 mutex_lock(&chip->reg_lock); 1598 if (mv88e6xxx_pvt_map(chip, dev, port)) 1599 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1600 mutex_unlock(&chip->reg_lock); 1601 } 1602 1603 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1604 { 1605 if (chip->info->ops->reset) 1606 return chip->info->ops->reset(chip); 1607 1608 return 0; 1609 } 1610 1611 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1612 { 1613 struct gpio_desc *gpiod = chip->reset; 1614 1615 /* If there is a GPIO connected to the reset pin, toggle it */ 1616 if (gpiod) { 1617 gpiod_set_value_cansleep(gpiod, 1); 1618 usleep_range(10000, 20000); 1619 gpiod_set_value_cansleep(gpiod, 0); 1620 usleep_range(10000, 20000); 1621 } 1622 } 1623 1624 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1625 { 1626 int i, err; 1627 1628 /* Set all ports to the Disabled state */ 1629 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1630 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1631 if (err) 1632 return err; 1633 } 1634 1635 /* Wait for transmit queues to drain, 1636 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1637 */ 1638 usleep_range(2000, 4000); 1639 1640 return 0; 1641 } 1642 1643 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1644 { 1645 int err; 1646 1647 err = mv88e6xxx_disable_ports(chip); 1648 if (err) 1649 return err; 1650 1651 mv88e6xxx_hardware_reset(chip); 1652 1653 return mv88e6xxx_software_reset(chip); 1654 } 1655 1656 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1657 enum mv88e6xxx_frame_mode frame, 1658 enum mv88e6xxx_egress_mode egress, u16 etype) 1659 { 1660 int err; 1661 1662 if (!chip->info->ops->port_set_frame_mode) 1663 return -EOPNOTSUPP; 1664 1665 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1666 if (err) 1667 return err; 1668 1669 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1670 if (err) 1671 return err; 1672 1673 if (chip->info->ops->port_set_ether_type) 1674 return chip->info->ops->port_set_ether_type(chip, port, etype); 1675 1676 return 0; 1677 } 1678 1679 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1680 { 1681 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1682 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1683 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1684 } 1685 1686 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1687 { 1688 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1689 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1690 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1691 } 1692 1693 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1694 { 1695 return mv88e6xxx_set_port_mode(chip, port, 1696 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1697 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1698 ETH_P_EDSA); 1699 } 1700 1701 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1702 { 1703 if (dsa_is_dsa_port(chip->ds, port)) 1704 return mv88e6xxx_set_port_mode_dsa(chip, port); 1705 1706 if (dsa_is_user_port(chip->ds, port)) 1707 return mv88e6xxx_set_port_mode_normal(chip, port); 1708 1709 /* Setup CPU port mode depending on its supported tag format */ 1710 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1711 return mv88e6xxx_set_port_mode_dsa(chip, port); 1712 1713 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1714 return mv88e6xxx_set_port_mode_edsa(chip, port); 1715 1716 return -EINVAL; 1717 } 1718 1719 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1720 { 1721 bool message = dsa_is_dsa_port(chip->ds, port); 1722 1723 return mv88e6xxx_port_set_message_port(chip, port, message); 1724 } 1725 1726 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1727 { 1728 bool flood = port == dsa_upstream_port(chip->ds); 1729 1730 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1731 if (chip->info->ops->port_set_egress_floods) 1732 return chip->info->ops->port_set_egress_floods(chip, port, 1733 flood, flood); 1734 1735 return 0; 1736 } 1737 1738 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1739 bool on) 1740 { 1741 if (chip->info->ops->serdes_power) 1742 return chip->info->ops->serdes_power(chip, port, on); 1743 1744 return 0; 1745 } 1746 1747 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1748 { 1749 struct dsa_switch *ds = chip->ds; 1750 int err; 1751 u16 reg; 1752 1753 /* MAC Forcing register: don't force link, speed, duplex or flow control 1754 * state to any particular values on physical ports, but force the CPU 1755 * port and all DSA ports to their maximum bandwidth and full duplex. 1756 */ 1757 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1758 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1759 SPEED_MAX, DUPLEX_FULL, 1760 PHY_INTERFACE_MODE_NA); 1761 else 1762 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1763 SPEED_UNFORCED, DUPLEX_UNFORCED, 1764 PHY_INTERFACE_MODE_NA); 1765 if (err) 1766 return err; 1767 1768 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1769 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1770 * tunneling, determine priority by looking at 802.1p and IP 1771 * priority fields (IP prio has precedence), and set STP state 1772 * to Forwarding. 1773 * 1774 * If this is the CPU link, use DSA or EDSA tagging depending 1775 * on which tagging mode was configured. 1776 * 1777 * If this is a link to another switch, use DSA tagging mode. 1778 * 1779 * If this is the upstream port for this switch, enable 1780 * forwarding of unknown unicasts and multicasts. 1781 */ 1782 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1783 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1784 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1785 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1786 if (err) 1787 return err; 1788 1789 err = mv88e6xxx_setup_port_mode(chip, port); 1790 if (err) 1791 return err; 1792 1793 err = mv88e6xxx_setup_egress_floods(chip, port); 1794 if (err) 1795 return err; 1796 1797 /* Enable the SERDES interface for DSA and CPU ports. Normal 1798 * ports SERDES are enabled when the port is enabled, thus 1799 * saving a bit of power. 1800 */ 1801 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1802 err = mv88e6xxx_serdes_power(chip, port, true); 1803 if (err) 1804 return err; 1805 } 1806 1807 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1808 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1809 * untagged frames on this port, do a destination address lookup on all 1810 * received packets as usual, disable ARP mirroring and don't send a 1811 * copy of all transmitted/received frames on this port to the CPU. 1812 */ 1813 err = mv88e6xxx_port_set_map_da(chip, port); 1814 if (err) 1815 return err; 1816 1817 reg = 0; 1818 if (chip->info->ops->port_set_upstream_port) { 1819 err = chip->info->ops->port_set_upstream_port( 1820 chip, port, dsa_upstream_port(ds)); 1821 if (err) 1822 return err; 1823 } 1824 1825 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1826 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1827 if (err) 1828 return err; 1829 1830 if (chip->info->ops->port_set_jumbo_size) { 1831 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1832 if (err) 1833 return err; 1834 } 1835 1836 /* Port Association Vector: when learning source addresses 1837 * of packets, add the address to the address database using 1838 * a port bitmap that has only the bit for this port set and 1839 * the other bits clear. 1840 */ 1841 reg = 1 << port; 1842 /* Disable learning for CPU port */ 1843 if (dsa_is_cpu_port(ds, port)) 1844 reg = 0; 1845 1846 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1847 reg); 1848 if (err) 1849 return err; 1850 1851 /* Egress rate control 2: disable egress rate control. */ 1852 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1853 0x0000); 1854 if (err) 1855 return err; 1856 1857 if (chip->info->ops->port_pause_limit) { 1858 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1859 if (err) 1860 return err; 1861 } 1862 1863 if (chip->info->ops->port_disable_learn_limit) { 1864 err = chip->info->ops->port_disable_learn_limit(chip, port); 1865 if (err) 1866 return err; 1867 } 1868 1869 if (chip->info->ops->port_disable_pri_override) { 1870 err = chip->info->ops->port_disable_pri_override(chip, port); 1871 if (err) 1872 return err; 1873 } 1874 1875 if (chip->info->ops->port_tag_remap) { 1876 err = chip->info->ops->port_tag_remap(chip, port); 1877 if (err) 1878 return err; 1879 } 1880 1881 if (chip->info->ops->port_egress_rate_limiting) { 1882 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1883 if (err) 1884 return err; 1885 } 1886 1887 err = mv88e6xxx_setup_message_port(chip, port); 1888 if (err) 1889 return err; 1890 1891 /* Port based VLAN map: give each port the same default address 1892 * database, and allow bidirectional communication between the 1893 * CPU and DSA port(s), and the other ports. 1894 */ 1895 err = mv88e6xxx_port_set_fid(chip, port, 0); 1896 if (err) 1897 return err; 1898 1899 err = mv88e6xxx_port_vlan_map(chip, port); 1900 if (err) 1901 return err; 1902 1903 /* Default VLAN ID and priority: don't set a default VLAN 1904 * ID, and set the default packet priority to zero. 1905 */ 1906 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 1907 } 1908 1909 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 1910 struct phy_device *phydev) 1911 { 1912 struct mv88e6xxx_chip *chip = ds->priv; 1913 int err; 1914 1915 mutex_lock(&chip->reg_lock); 1916 err = mv88e6xxx_serdes_power(chip, port, true); 1917 mutex_unlock(&chip->reg_lock); 1918 1919 return err; 1920 } 1921 1922 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 1923 struct phy_device *phydev) 1924 { 1925 struct mv88e6xxx_chip *chip = ds->priv; 1926 1927 mutex_lock(&chip->reg_lock); 1928 if (mv88e6xxx_serdes_power(chip, port, false)) 1929 dev_err(chip->dev, "failed to power off SERDES\n"); 1930 mutex_unlock(&chip->reg_lock); 1931 } 1932 1933 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 1934 unsigned int ageing_time) 1935 { 1936 struct mv88e6xxx_chip *chip = ds->priv; 1937 int err; 1938 1939 mutex_lock(&chip->reg_lock); 1940 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 1941 mutex_unlock(&chip->reg_lock); 1942 1943 return err; 1944 } 1945 1946 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 1947 { 1948 struct dsa_switch *ds = chip->ds; 1949 u32 upstream_port = dsa_upstream_port(ds); 1950 int err; 1951 1952 if (chip->info->ops->set_cpu_port) { 1953 err = chip->info->ops->set_cpu_port(chip, upstream_port); 1954 if (err) 1955 return err; 1956 } 1957 1958 if (chip->info->ops->set_egress_port) { 1959 err = chip->info->ops->set_egress_port(chip, upstream_port); 1960 if (err) 1961 return err; 1962 } 1963 1964 /* Disable remote management, and set the switch's DSA device number. */ 1965 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 1966 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 1967 (ds->index & 0x1f)); 1968 if (err) 1969 return err; 1970 1971 /* Configure the IP ToS mapping registers. */ 1972 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 1973 if (err) 1974 return err; 1975 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 1976 if (err) 1977 return err; 1978 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 1979 if (err) 1980 return err; 1981 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 1982 if (err) 1983 return err; 1984 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 1985 if (err) 1986 return err; 1987 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 1988 if (err) 1989 return err; 1990 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 1991 if (err) 1992 return err; 1993 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 1994 if (err) 1995 return err; 1996 1997 /* Configure the IEEE 802.1p priority mapping register. */ 1998 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 1999 if (err) 2000 return err; 2001 2002 /* Initialize the statistics unit */ 2003 err = mv88e6xxx_stats_set_histogram(chip); 2004 if (err) 2005 return err; 2006 2007 return mv88e6xxx_g1_stats_clear(chip); 2008 } 2009 2010 static int mv88e6xxx_setup(struct dsa_switch *ds) 2011 { 2012 struct mv88e6xxx_chip *chip = ds->priv; 2013 int err; 2014 int i; 2015 2016 chip->ds = ds; 2017 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2018 2019 mutex_lock(&chip->reg_lock); 2020 2021 /* Setup Switch Port Registers */ 2022 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2023 if (dsa_is_unused_port(ds, i)) 2024 continue; 2025 2026 err = mv88e6xxx_setup_port(chip, i); 2027 if (err) 2028 goto unlock; 2029 } 2030 2031 /* Setup Switch Global 1 Registers */ 2032 err = mv88e6xxx_g1_setup(chip); 2033 if (err) 2034 goto unlock; 2035 2036 /* Setup Switch Global 2 Registers */ 2037 if (chip->info->global2_addr) { 2038 err = mv88e6xxx_g2_setup(chip); 2039 if (err) 2040 goto unlock; 2041 } 2042 2043 err = mv88e6xxx_irl_setup(chip); 2044 if (err) 2045 goto unlock; 2046 2047 err = mv88e6xxx_mac_setup(chip); 2048 if (err) 2049 goto unlock; 2050 2051 err = mv88e6xxx_phy_setup(chip); 2052 if (err) 2053 goto unlock; 2054 2055 err = mv88e6xxx_vtu_setup(chip); 2056 if (err) 2057 goto unlock; 2058 2059 err = mv88e6xxx_pvt_setup(chip); 2060 if (err) 2061 goto unlock; 2062 2063 err = mv88e6xxx_atu_setup(chip); 2064 if (err) 2065 goto unlock; 2066 2067 err = mv88e6xxx_broadcast_setup(chip, 0); 2068 if (err) 2069 goto unlock; 2070 2071 err = mv88e6xxx_pot_setup(chip); 2072 if (err) 2073 goto unlock; 2074 2075 err = mv88e6xxx_rsvd2cpu_setup(chip); 2076 if (err) 2077 goto unlock; 2078 2079 unlock: 2080 mutex_unlock(&chip->reg_lock); 2081 2082 return err; 2083 } 2084 2085 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2086 { 2087 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2088 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2089 u16 val; 2090 int err; 2091 2092 if (!chip->info->ops->phy_read) 2093 return -EOPNOTSUPP; 2094 2095 mutex_lock(&chip->reg_lock); 2096 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2097 mutex_unlock(&chip->reg_lock); 2098 2099 if (reg == MII_PHYSID2) { 2100 /* Some internal PHYS don't have a model number. Use 2101 * the mv88e6390 family model number instead. 2102 */ 2103 if (!(val & 0x3f0)) 2104 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2105 } 2106 2107 return err ? err : val; 2108 } 2109 2110 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2111 { 2112 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2113 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2114 int err; 2115 2116 if (!chip->info->ops->phy_write) 2117 return -EOPNOTSUPP; 2118 2119 mutex_lock(&chip->reg_lock); 2120 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2121 mutex_unlock(&chip->reg_lock); 2122 2123 return err; 2124 } 2125 2126 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2127 struct device_node *np, 2128 bool external) 2129 { 2130 static int index; 2131 struct mv88e6xxx_mdio_bus *mdio_bus; 2132 struct mii_bus *bus; 2133 int err; 2134 2135 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2136 if (!bus) 2137 return -ENOMEM; 2138 2139 mdio_bus = bus->priv; 2140 mdio_bus->bus = bus; 2141 mdio_bus->chip = chip; 2142 INIT_LIST_HEAD(&mdio_bus->list); 2143 mdio_bus->external = external; 2144 2145 if (np) { 2146 bus->name = np->full_name; 2147 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2148 } else { 2149 bus->name = "mv88e6xxx SMI"; 2150 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2151 } 2152 2153 bus->read = mv88e6xxx_mdio_read; 2154 bus->write = mv88e6xxx_mdio_write; 2155 bus->parent = chip->dev; 2156 2157 if (np) 2158 err = of_mdiobus_register(bus, np); 2159 else 2160 err = mdiobus_register(bus); 2161 if (err) { 2162 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2163 return err; 2164 } 2165 2166 if (external) 2167 list_add_tail(&mdio_bus->list, &chip->mdios); 2168 else 2169 list_add(&mdio_bus->list, &chip->mdios); 2170 2171 return 0; 2172 } 2173 2174 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2175 { .compatible = "marvell,mv88e6xxx-mdio-external", 2176 .data = (void *)true }, 2177 { }, 2178 }; 2179 2180 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2181 struct device_node *np) 2182 { 2183 const struct of_device_id *match; 2184 struct device_node *child; 2185 int err; 2186 2187 /* Always register one mdio bus for the internal/default mdio 2188 * bus. This maybe represented in the device tree, but is 2189 * optional. 2190 */ 2191 child = of_get_child_by_name(np, "mdio"); 2192 err = mv88e6xxx_mdio_register(chip, child, false); 2193 if (err) 2194 return err; 2195 2196 /* Walk the device tree, and see if there are any other nodes 2197 * which say they are compatible with the external mdio 2198 * bus. 2199 */ 2200 for_each_available_child_of_node(np, child) { 2201 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2202 if (match) { 2203 err = mv88e6xxx_mdio_register(chip, child, true); 2204 if (err) 2205 return err; 2206 } 2207 } 2208 2209 return 0; 2210 } 2211 2212 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2213 2214 { 2215 struct mv88e6xxx_mdio_bus *mdio_bus; 2216 struct mii_bus *bus; 2217 2218 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2219 bus = mdio_bus->bus; 2220 2221 mdiobus_unregister(bus); 2222 } 2223 } 2224 2225 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2226 { 2227 struct mv88e6xxx_chip *chip = ds->priv; 2228 2229 return chip->eeprom_len; 2230 } 2231 2232 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2233 struct ethtool_eeprom *eeprom, u8 *data) 2234 { 2235 struct mv88e6xxx_chip *chip = ds->priv; 2236 int err; 2237 2238 if (!chip->info->ops->get_eeprom) 2239 return -EOPNOTSUPP; 2240 2241 mutex_lock(&chip->reg_lock); 2242 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2243 mutex_unlock(&chip->reg_lock); 2244 2245 if (err) 2246 return err; 2247 2248 eeprom->magic = 0xc3ec4951; 2249 2250 return 0; 2251 } 2252 2253 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2254 struct ethtool_eeprom *eeprom, u8 *data) 2255 { 2256 struct mv88e6xxx_chip *chip = ds->priv; 2257 int err; 2258 2259 if (!chip->info->ops->set_eeprom) 2260 return -EOPNOTSUPP; 2261 2262 if (eeprom->magic != 0xc3ec4951) 2263 return -EINVAL; 2264 2265 mutex_lock(&chip->reg_lock); 2266 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2267 mutex_unlock(&chip->reg_lock); 2268 2269 return err; 2270 } 2271 2272 static const struct mv88e6xxx_ops mv88e6085_ops = { 2273 /* MV88E6XXX_FAMILY_6097 */ 2274 .irl_init_all = mv88e6352_g2_irl_init_all, 2275 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2276 .phy_read = mv88e6185_phy_ppu_read, 2277 .phy_write = mv88e6185_phy_ppu_write, 2278 .port_set_link = mv88e6xxx_port_set_link, 2279 .port_set_duplex = mv88e6xxx_port_set_duplex, 2280 .port_set_speed = mv88e6185_port_set_speed, 2281 .port_tag_remap = mv88e6095_port_tag_remap, 2282 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2283 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2284 .port_set_ether_type = mv88e6351_port_set_ether_type, 2285 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2286 .port_pause_limit = mv88e6097_port_pause_limit, 2287 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2288 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2289 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2290 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2291 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2292 .stats_get_strings = mv88e6095_stats_get_strings, 2293 .stats_get_stats = mv88e6095_stats_get_stats, 2294 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2295 .set_egress_port = mv88e6095_g1_set_egress_port, 2296 .watchdog_ops = &mv88e6097_watchdog_ops, 2297 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2298 .pot_clear = mv88e6xxx_g2_pot_clear, 2299 .ppu_enable = mv88e6185_g1_ppu_enable, 2300 .ppu_disable = mv88e6185_g1_ppu_disable, 2301 .reset = mv88e6185_g1_reset, 2302 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2303 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2304 }; 2305 2306 static const struct mv88e6xxx_ops mv88e6095_ops = { 2307 /* MV88E6XXX_FAMILY_6095 */ 2308 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2309 .phy_read = mv88e6185_phy_ppu_read, 2310 .phy_write = mv88e6185_phy_ppu_write, 2311 .port_set_link = mv88e6xxx_port_set_link, 2312 .port_set_duplex = mv88e6xxx_port_set_duplex, 2313 .port_set_speed = mv88e6185_port_set_speed, 2314 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2315 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2316 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2317 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2318 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2319 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2320 .stats_get_strings = mv88e6095_stats_get_strings, 2321 .stats_get_stats = mv88e6095_stats_get_stats, 2322 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2323 .ppu_enable = mv88e6185_g1_ppu_enable, 2324 .ppu_disable = mv88e6185_g1_ppu_disable, 2325 .reset = mv88e6185_g1_reset, 2326 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2327 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2328 }; 2329 2330 static const struct mv88e6xxx_ops mv88e6097_ops = { 2331 /* MV88E6XXX_FAMILY_6097 */ 2332 .irl_init_all = mv88e6352_g2_irl_init_all, 2333 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2334 .phy_read = mv88e6xxx_g2_smi_phy_read, 2335 .phy_write = mv88e6xxx_g2_smi_phy_write, 2336 .port_set_link = mv88e6xxx_port_set_link, 2337 .port_set_duplex = mv88e6xxx_port_set_duplex, 2338 .port_set_speed = mv88e6185_port_set_speed, 2339 .port_tag_remap = mv88e6095_port_tag_remap, 2340 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2341 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2342 .port_set_ether_type = mv88e6351_port_set_ether_type, 2343 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2344 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2345 .port_pause_limit = mv88e6097_port_pause_limit, 2346 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2347 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2348 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2349 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2350 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2351 .stats_get_strings = mv88e6095_stats_get_strings, 2352 .stats_get_stats = mv88e6095_stats_get_stats, 2353 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2354 .set_egress_port = mv88e6095_g1_set_egress_port, 2355 .watchdog_ops = &mv88e6097_watchdog_ops, 2356 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2357 .pot_clear = mv88e6xxx_g2_pot_clear, 2358 .reset = mv88e6352_g1_reset, 2359 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2360 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2361 }; 2362 2363 static const struct mv88e6xxx_ops mv88e6123_ops = { 2364 /* MV88E6XXX_FAMILY_6165 */ 2365 .irl_init_all = mv88e6352_g2_irl_init_all, 2366 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2367 .phy_read = mv88e6xxx_g2_smi_phy_read, 2368 .phy_write = mv88e6xxx_g2_smi_phy_write, 2369 .port_set_link = mv88e6xxx_port_set_link, 2370 .port_set_duplex = mv88e6xxx_port_set_duplex, 2371 .port_set_speed = mv88e6185_port_set_speed, 2372 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2373 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2374 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2375 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2376 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2377 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2378 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2379 .stats_get_strings = mv88e6095_stats_get_strings, 2380 .stats_get_stats = mv88e6095_stats_get_stats, 2381 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2382 .set_egress_port = mv88e6095_g1_set_egress_port, 2383 .watchdog_ops = &mv88e6097_watchdog_ops, 2384 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2385 .pot_clear = mv88e6xxx_g2_pot_clear, 2386 .reset = mv88e6352_g1_reset, 2387 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2388 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2389 }; 2390 2391 static const struct mv88e6xxx_ops mv88e6131_ops = { 2392 /* MV88E6XXX_FAMILY_6185 */ 2393 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2394 .phy_read = mv88e6185_phy_ppu_read, 2395 .phy_write = mv88e6185_phy_ppu_write, 2396 .port_set_link = mv88e6xxx_port_set_link, 2397 .port_set_duplex = mv88e6xxx_port_set_duplex, 2398 .port_set_speed = mv88e6185_port_set_speed, 2399 .port_tag_remap = mv88e6095_port_tag_remap, 2400 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2401 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2402 .port_set_ether_type = mv88e6351_port_set_ether_type, 2403 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2404 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2405 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2406 .port_pause_limit = mv88e6097_port_pause_limit, 2407 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2408 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2409 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2410 .stats_get_strings = mv88e6095_stats_get_strings, 2411 .stats_get_stats = mv88e6095_stats_get_stats, 2412 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2413 .set_egress_port = mv88e6095_g1_set_egress_port, 2414 .watchdog_ops = &mv88e6097_watchdog_ops, 2415 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2416 .ppu_enable = mv88e6185_g1_ppu_enable, 2417 .ppu_disable = mv88e6185_g1_ppu_disable, 2418 .reset = mv88e6185_g1_reset, 2419 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2420 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2421 }; 2422 2423 static const struct mv88e6xxx_ops mv88e6141_ops = { 2424 /* MV88E6XXX_FAMILY_6341 */ 2425 .irl_init_all = mv88e6352_g2_irl_init_all, 2426 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2427 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2428 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2429 .phy_read = mv88e6xxx_g2_smi_phy_read, 2430 .phy_write = mv88e6xxx_g2_smi_phy_write, 2431 .port_set_link = mv88e6xxx_port_set_link, 2432 .port_set_duplex = mv88e6xxx_port_set_duplex, 2433 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2434 .port_set_speed = mv88e6390_port_set_speed, 2435 .port_tag_remap = mv88e6095_port_tag_remap, 2436 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2437 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2438 .port_set_ether_type = mv88e6351_port_set_ether_type, 2439 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2440 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2441 .port_pause_limit = mv88e6097_port_pause_limit, 2442 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2443 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2444 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2445 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2446 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2447 .stats_get_strings = mv88e6320_stats_get_strings, 2448 .stats_get_stats = mv88e6390_stats_get_stats, 2449 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2450 .set_egress_port = mv88e6390_g1_set_egress_port, 2451 .watchdog_ops = &mv88e6390_watchdog_ops, 2452 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2453 .pot_clear = mv88e6xxx_g2_pot_clear, 2454 .reset = mv88e6352_g1_reset, 2455 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2456 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2457 }; 2458 2459 static const struct mv88e6xxx_ops mv88e6161_ops = { 2460 /* MV88E6XXX_FAMILY_6165 */ 2461 .irl_init_all = mv88e6352_g2_irl_init_all, 2462 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2463 .phy_read = mv88e6xxx_g2_smi_phy_read, 2464 .phy_write = mv88e6xxx_g2_smi_phy_write, 2465 .port_set_link = mv88e6xxx_port_set_link, 2466 .port_set_duplex = mv88e6xxx_port_set_duplex, 2467 .port_set_speed = mv88e6185_port_set_speed, 2468 .port_tag_remap = mv88e6095_port_tag_remap, 2469 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2470 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2471 .port_set_ether_type = mv88e6351_port_set_ether_type, 2472 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2473 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2474 .port_pause_limit = mv88e6097_port_pause_limit, 2475 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2476 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2477 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2478 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2479 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2480 .stats_get_strings = mv88e6095_stats_get_strings, 2481 .stats_get_stats = mv88e6095_stats_get_stats, 2482 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2483 .set_egress_port = mv88e6095_g1_set_egress_port, 2484 .watchdog_ops = &mv88e6097_watchdog_ops, 2485 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2486 .pot_clear = mv88e6xxx_g2_pot_clear, 2487 .reset = mv88e6352_g1_reset, 2488 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2489 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2490 }; 2491 2492 static const struct mv88e6xxx_ops mv88e6165_ops = { 2493 /* MV88E6XXX_FAMILY_6165 */ 2494 .irl_init_all = mv88e6352_g2_irl_init_all, 2495 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2496 .phy_read = mv88e6165_phy_read, 2497 .phy_write = mv88e6165_phy_write, 2498 .port_set_link = mv88e6xxx_port_set_link, 2499 .port_set_duplex = mv88e6xxx_port_set_duplex, 2500 .port_set_speed = mv88e6185_port_set_speed, 2501 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2502 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2503 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2504 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2505 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2506 .stats_get_strings = mv88e6095_stats_get_strings, 2507 .stats_get_stats = mv88e6095_stats_get_stats, 2508 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2509 .set_egress_port = mv88e6095_g1_set_egress_port, 2510 .watchdog_ops = &mv88e6097_watchdog_ops, 2511 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2512 .pot_clear = mv88e6xxx_g2_pot_clear, 2513 .reset = mv88e6352_g1_reset, 2514 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2515 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2516 }; 2517 2518 static const struct mv88e6xxx_ops mv88e6171_ops = { 2519 /* MV88E6XXX_FAMILY_6351 */ 2520 .irl_init_all = mv88e6352_g2_irl_init_all, 2521 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2522 .phy_read = mv88e6xxx_g2_smi_phy_read, 2523 .phy_write = mv88e6xxx_g2_smi_phy_write, 2524 .port_set_link = mv88e6xxx_port_set_link, 2525 .port_set_duplex = mv88e6xxx_port_set_duplex, 2526 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2527 .port_set_speed = mv88e6185_port_set_speed, 2528 .port_tag_remap = mv88e6095_port_tag_remap, 2529 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2530 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2531 .port_set_ether_type = mv88e6351_port_set_ether_type, 2532 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2533 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2534 .port_pause_limit = mv88e6097_port_pause_limit, 2535 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2536 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2537 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2538 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2539 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2540 .stats_get_strings = mv88e6095_stats_get_strings, 2541 .stats_get_stats = mv88e6095_stats_get_stats, 2542 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2543 .set_egress_port = mv88e6095_g1_set_egress_port, 2544 .watchdog_ops = &mv88e6097_watchdog_ops, 2545 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2546 .pot_clear = mv88e6xxx_g2_pot_clear, 2547 .reset = mv88e6352_g1_reset, 2548 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2549 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2550 }; 2551 2552 static const struct mv88e6xxx_ops mv88e6172_ops = { 2553 /* MV88E6XXX_FAMILY_6352 */ 2554 .irl_init_all = mv88e6352_g2_irl_init_all, 2555 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2556 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2557 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2558 .phy_read = mv88e6xxx_g2_smi_phy_read, 2559 .phy_write = mv88e6xxx_g2_smi_phy_write, 2560 .port_set_link = mv88e6xxx_port_set_link, 2561 .port_set_duplex = mv88e6xxx_port_set_duplex, 2562 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2563 .port_set_speed = mv88e6352_port_set_speed, 2564 .port_tag_remap = mv88e6095_port_tag_remap, 2565 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2566 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2567 .port_set_ether_type = mv88e6351_port_set_ether_type, 2568 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2569 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2570 .port_pause_limit = mv88e6097_port_pause_limit, 2571 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2572 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2573 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2574 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2575 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2576 .stats_get_strings = mv88e6095_stats_get_strings, 2577 .stats_get_stats = mv88e6095_stats_get_stats, 2578 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2579 .set_egress_port = mv88e6095_g1_set_egress_port, 2580 .watchdog_ops = &mv88e6097_watchdog_ops, 2581 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2582 .pot_clear = mv88e6xxx_g2_pot_clear, 2583 .reset = mv88e6352_g1_reset, 2584 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2585 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2586 .serdes_power = mv88e6352_serdes_power, 2587 }; 2588 2589 static const struct mv88e6xxx_ops mv88e6175_ops = { 2590 /* MV88E6XXX_FAMILY_6351 */ 2591 .irl_init_all = mv88e6352_g2_irl_init_all, 2592 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2593 .phy_read = mv88e6xxx_g2_smi_phy_read, 2594 .phy_write = mv88e6xxx_g2_smi_phy_write, 2595 .port_set_link = mv88e6xxx_port_set_link, 2596 .port_set_duplex = mv88e6xxx_port_set_duplex, 2597 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2598 .port_set_speed = mv88e6185_port_set_speed, 2599 .port_tag_remap = mv88e6095_port_tag_remap, 2600 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2601 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2602 .port_set_ether_type = mv88e6351_port_set_ether_type, 2603 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2604 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2605 .port_pause_limit = mv88e6097_port_pause_limit, 2606 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2607 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2608 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2609 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2610 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2611 .stats_get_strings = mv88e6095_stats_get_strings, 2612 .stats_get_stats = mv88e6095_stats_get_stats, 2613 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2614 .set_egress_port = mv88e6095_g1_set_egress_port, 2615 .watchdog_ops = &mv88e6097_watchdog_ops, 2616 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2617 .pot_clear = mv88e6xxx_g2_pot_clear, 2618 .reset = mv88e6352_g1_reset, 2619 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2620 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2621 }; 2622 2623 static const struct mv88e6xxx_ops mv88e6176_ops = { 2624 /* MV88E6XXX_FAMILY_6352 */ 2625 .irl_init_all = mv88e6352_g2_irl_init_all, 2626 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2627 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2628 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2629 .phy_read = mv88e6xxx_g2_smi_phy_read, 2630 .phy_write = mv88e6xxx_g2_smi_phy_write, 2631 .port_set_link = mv88e6xxx_port_set_link, 2632 .port_set_duplex = mv88e6xxx_port_set_duplex, 2633 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2634 .port_set_speed = mv88e6352_port_set_speed, 2635 .port_tag_remap = mv88e6095_port_tag_remap, 2636 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2637 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2638 .port_set_ether_type = mv88e6351_port_set_ether_type, 2639 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2640 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2641 .port_pause_limit = mv88e6097_port_pause_limit, 2642 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2643 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2644 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2645 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2646 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2647 .stats_get_strings = mv88e6095_stats_get_strings, 2648 .stats_get_stats = mv88e6095_stats_get_stats, 2649 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2650 .set_egress_port = mv88e6095_g1_set_egress_port, 2651 .watchdog_ops = &mv88e6097_watchdog_ops, 2652 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2653 .pot_clear = mv88e6xxx_g2_pot_clear, 2654 .reset = mv88e6352_g1_reset, 2655 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2656 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2657 .serdes_power = mv88e6352_serdes_power, 2658 }; 2659 2660 static const struct mv88e6xxx_ops mv88e6185_ops = { 2661 /* MV88E6XXX_FAMILY_6185 */ 2662 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2663 .phy_read = mv88e6185_phy_ppu_read, 2664 .phy_write = mv88e6185_phy_ppu_write, 2665 .port_set_link = mv88e6xxx_port_set_link, 2666 .port_set_duplex = mv88e6xxx_port_set_duplex, 2667 .port_set_speed = mv88e6185_port_set_speed, 2668 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2669 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2670 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2671 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2672 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2673 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2674 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2675 .stats_get_strings = mv88e6095_stats_get_strings, 2676 .stats_get_stats = mv88e6095_stats_get_stats, 2677 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2678 .set_egress_port = mv88e6095_g1_set_egress_port, 2679 .watchdog_ops = &mv88e6097_watchdog_ops, 2680 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2681 .ppu_enable = mv88e6185_g1_ppu_enable, 2682 .ppu_disable = mv88e6185_g1_ppu_disable, 2683 .reset = mv88e6185_g1_reset, 2684 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2685 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2686 }; 2687 2688 static const struct mv88e6xxx_ops mv88e6190_ops = { 2689 /* MV88E6XXX_FAMILY_6390 */ 2690 .irl_init_all = mv88e6390_g2_irl_init_all, 2691 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2692 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2693 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2694 .phy_read = mv88e6xxx_g2_smi_phy_read, 2695 .phy_write = mv88e6xxx_g2_smi_phy_write, 2696 .port_set_link = mv88e6xxx_port_set_link, 2697 .port_set_duplex = mv88e6xxx_port_set_duplex, 2698 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2699 .port_set_speed = mv88e6390_port_set_speed, 2700 .port_tag_remap = mv88e6390_port_tag_remap, 2701 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2702 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2703 .port_set_ether_type = mv88e6351_port_set_ether_type, 2704 .port_pause_limit = mv88e6390_port_pause_limit, 2705 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2706 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2707 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2708 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2709 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2710 .stats_get_strings = mv88e6320_stats_get_strings, 2711 .stats_get_stats = mv88e6390_stats_get_stats, 2712 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2713 .set_egress_port = mv88e6390_g1_set_egress_port, 2714 .watchdog_ops = &mv88e6390_watchdog_ops, 2715 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2716 .pot_clear = mv88e6xxx_g2_pot_clear, 2717 .reset = mv88e6352_g1_reset, 2718 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2719 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2720 .serdes_power = mv88e6390_serdes_power, 2721 }; 2722 2723 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2724 /* MV88E6XXX_FAMILY_6390 */ 2725 .irl_init_all = mv88e6390_g2_irl_init_all, 2726 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2727 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2728 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2729 .phy_read = mv88e6xxx_g2_smi_phy_read, 2730 .phy_write = mv88e6xxx_g2_smi_phy_write, 2731 .port_set_link = mv88e6xxx_port_set_link, 2732 .port_set_duplex = mv88e6xxx_port_set_duplex, 2733 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2734 .port_set_speed = mv88e6390x_port_set_speed, 2735 .port_tag_remap = mv88e6390_port_tag_remap, 2736 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2737 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2738 .port_set_ether_type = mv88e6351_port_set_ether_type, 2739 .port_pause_limit = mv88e6390_port_pause_limit, 2740 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2741 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2742 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2743 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2744 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2745 .stats_get_strings = mv88e6320_stats_get_strings, 2746 .stats_get_stats = mv88e6390_stats_get_stats, 2747 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2748 .set_egress_port = mv88e6390_g1_set_egress_port, 2749 .watchdog_ops = &mv88e6390_watchdog_ops, 2750 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2751 .pot_clear = mv88e6xxx_g2_pot_clear, 2752 .reset = mv88e6352_g1_reset, 2753 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2754 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2755 .serdes_power = mv88e6390_serdes_power, 2756 }; 2757 2758 static const struct mv88e6xxx_ops mv88e6191_ops = { 2759 /* MV88E6XXX_FAMILY_6390 */ 2760 .irl_init_all = mv88e6390_g2_irl_init_all, 2761 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2762 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2763 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2764 .phy_read = mv88e6xxx_g2_smi_phy_read, 2765 .phy_write = mv88e6xxx_g2_smi_phy_write, 2766 .port_set_link = mv88e6xxx_port_set_link, 2767 .port_set_duplex = mv88e6xxx_port_set_duplex, 2768 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2769 .port_set_speed = mv88e6390_port_set_speed, 2770 .port_tag_remap = mv88e6390_port_tag_remap, 2771 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2772 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2773 .port_set_ether_type = mv88e6351_port_set_ether_type, 2774 .port_pause_limit = mv88e6390_port_pause_limit, 2775 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2776 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2777 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2778 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2779 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2780 .stats_get_strings = mv88e6320_stats_get_strings, 2781 .stats_get_stats = mv88e6390_stats_get_stats, 2782 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2783 .set_egress_port = mv88e6390_g1_set_egress_port, 2784 .watchdog_ops = &mv88e6390_watchdog_ops, 2785 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2786 .pot_clear = mv88e6xxx_g2_pot_clear, 2787 .reset = mv88e6352_g1_reset, 2788 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2789 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2790 .serdes_power = mv88e6390_serdes_power, 2791 }; 2792 2793 static const struct mv88e6xxx_ops mv88e6240_ops = { 2794 /* MV88E6XXX_FAMILY_6352 */ 2795 .irl_init_all = mv88e6352_g2_irl_init_all, 2796 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2797 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2798 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2799 .phy_read = mv88e6xxx_g2_smi_phy_read, 2800 .phy_write = mv88e6xxx_g2_smi_phy_write, 2801 .port_set_link = mv88e6xxx_port_set_link, 2802 .port_set_duplex = mv88e6xxx_port_set_duplex, 2803 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2804 .port_set_speed = mv88e6352_port_set_speed, 2805 .port_tag_remap = mv88e6095_port_tag_remap, 2806 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2807 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2808 .port_set_ether_type = mv88e6351_port_set_ether_type, 2809 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2810 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2811 .port_pause_limit = mv88e6097_port_pause_limit, 2812 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2813 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2814 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2815 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2816 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2817 .stats_get_strings = mv88e6095_stats_get_strings, 2818 .stats_get_stats = mv88e6095_stats_get_stats, 2819 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2820 .set_egress_port = mv88e6095_g1_set_egress_port, 2821 .watchdog_ops = &mv88e6097_watchdog_ops, 2822 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2823 .pot_clear = mv88e6xxx_g2_pot_clear, 2824 .reset = mv88e6352_g1_reset, 2825 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2826 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2827 .serdes_power = mv88e6352_serdes_power, 2828 }; 2829 2830 static const struct mv88e6xxx_ops mv88e6290_ops = { 2831 /* MV88E6XXX_FAMILY_6390 */ 2832 .irl_init_all = mv88e6390_g2_irl_init_all, 2833 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2834 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2835 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2836 .phy_read = mv88e6xxx_g2_smi_phy_read, 2837 .phy_write = mv88e6xxx_g2_smi_phy_write, 2838 .port_set_link = mv88e6xxx_port_set_link, 2839 .port_set_duplex = mv88e6xxx_port_set_duplex, 2840 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2841 .port_set_speed = mv88e6390_port_set_speed, 2842 .port_tag_remap = mv88e6390_port_tag_remap, 2843 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2844 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2845 .port_set_ether_type = mv88e6351_port_set_ether_type, 2846 .port_pause_limit = mv88e6390_port_pause_limit, 2847 .port_set_cmode = mv88e6390x_port_set_cmode, 2848 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2849 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2850 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2851 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2852 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2853 .stats_get_strings = mv88e6320_stats_get_strings, 2854 .stats_get_stats = mv88e6390_stats_get_stats, 2855 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2856 .set_egress_port = mv88e6390_g1_set_egress_port, 2857 .watchdog_ops = &mv88e6390_watchdog_ops, 2858 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2859 .pot_clear = mv88e6xxx_g2_pot_clear, 2860 .reset = mv88e6352_g1_reset, 2861 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2862 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2863 .serdes_power = mv88e6390_serdes_power, 2864 }; 2865 2866 static const struct mv88e6xxx_ops mv88e6320_ops = { 2867 /* MV88E6XXX_FAMILY_6320 */ 2868 .irl_init_all = mv88e6352_g2_irl_init_all, 2869 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2870 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2871 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2872 .phy_read = mv88e6xxx_g2_smi_phy_read, 2873 .phy_write = mv88e6xxx_g2_smi_phy_write, 2874 .port_set_link = mv88e6xxx_port_set_link, 2875 .port_set_duplex = mv88e6xxx_port_set_duplex, 2876 .port_set_speed = mv88e6185_port_set_speed, 2877 .port_tag_remap = mv88e6095_port_tag_remap, 2878 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2879 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2880 .port_set_ether_type = mv88e6351_port_set_ether_type, 2881 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2882 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2883 .port_pause_limit = mv88e6097_port_pause_limit, 2884 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2885 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2886 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2887 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2888 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2889 .stats_get_strings = mv88e6320_stats_get_strings, 2890 .stats_get_stats = mv88e6320_stats_get_stats, 2891 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2892 .set_egress_port = mv88e6095_g1_set_egress_port, 2893 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2894 .pot_clear = mv88e6xxx_g2_pot_clear, 2895 .reset = mv88e6352_g1_reset, 2896 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2897 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2898 }; 2899 2900 static const struct mv88e6xxx_ops mv88e6321_ops = { 2901 /* MV88E6XXX_FAMILY_6320 */ 2902 .irl_init_all = mv88e6352_g2_irl_init_all, 2903 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2904 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2905 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2906 .phy_read = mv88e6xxx_g2_smi_phy_read, 2907 .phy_write = mv88e6xxx_g2_smi_phy_write, 2908 .port_set_link = mv88e6xxx_port_set_link, 2909 .port_set_duplex = mv88e6xxx_port_set_duplex, 2910 .port_set_speed = mv88e6185_port_set_speed, 2911 .port_tag_remap = mv88e6095_port_tag_remap, 2912 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2913 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2914 .port_set_ether_type = mv88e6351_port_set_ether_type, 2915 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2916 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2917 .port_pause_limit = mv88e6097_port_pause_limit, 2918 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2919 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2920 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2921 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2922 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2923 .stats_get_strings = mv88e6320_stats_get_strings, 2924 .stats_get_stats = mv88e6320_stats_get_stats, 2925 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2926 .set_egress_port = mv88e6095_g1_set_egress_port, 2927 .reset = mv88e6352_g1_reset, 2928 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2929 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2930 }; 2931 2932 static const struct mv88e6xxx_ops mv88e6341_ops = { 2933 /* MV88E6XXX_FAMILY_6341 */ 2934 .irl_init_all = mv88e6352_g2_irl_init_all, 2935 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2936 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2937 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2938 .phy_read = mv88e6xxx_g2_smi_phy_read, 2939 .phy_write = mv88e6xxx_g2_smi_phy_write, 2940 .port_set_link = mv88e6xxx_port_set_link, 2941 .port_set_duplex = mv88e6xxx_port_set_duplex, 2942 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2943 .port_set_speed = mv88e6390_port_set_speed, 2944 .port_tag_remap = mv88e6095_port_tag_remap, 2945 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2946 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2947 .port_set_ether_type = mv88e6351_port_set_ether_type, 2948 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2949 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2950 .port_pause_limit = mv88e6097_port_pause_limit, 2951 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2952 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2953 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2954 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2955 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2956 .stats_get_strings = mv88e6320_stats_get_strings, 2957 .stats_get_stats = mv88e6390_stats_get_stats, 2958 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2959 .set_egress_port = mv88e6390_g1_set_egress_port, 2960 .watchdog_ops = &mv88e6390_watchdog_ops, 2961 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2962 .pot_clear = mv88e6xxx_g2_pot_clear, 2963 .reset = mv88e6352_g1_reset, 2964 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2965 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2966 }; 2967 2968 static const struct mv88e6xxx_ops mv88e6350_ops = { 2969 /* MV88E6XXX_FAMILY_6351 */ 2970 .irl_init_all = mv88e6352_g2_irl_init_all, 2971 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2972 .phy_read = mv88e6xxx_g2_smi_phy_read, 2973 .phy_write = mv88e6xxx_g2_smi_phy_write, 2974 .port_set_link = mv88e6xxx_port_set_link, 2975 .port_set_duplex = mv88e6xxx_port_set_duplex, 2976 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2977 .port_set_speed = mv88e6185_port_set_speed, 2978 .port_tag_remap = mv88e6095_port_tag_remap, 2979 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2980 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2981 .port_set_ether_type = mv88e6351_port_set_ether_type, 2982 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2983 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2984 .port_pause_limit = mv88e6097_port_pause_limit, 2985 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2986 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2987 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2988 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2989 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2990 .stats_get_strings = mv88e6095_stats_get_strings, 2991 .stats_get_stats = mv88e6095_stats_get_stats, 2992 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2993 .set_egress_port = mv88e6095_g1_set_egress_port, 2994 .watchdog_ops = &mv88e6097_watchdog_ops, 2995 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2996 .pot_clear = mv88e6xxx_g2_pot_clear, 2997 .reset = mv88e6352_g1_reset, 2998 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2999 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3000 }; 3001 3002 static const struct mv88e6xxx_ops mv88e6351_ops = { 3003 /* MV88E6XXX_FAMILY_6351 */ 3004 .irl_init_all = mv88e6352_g2_irl_init_all, 3005 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3006 .phy_read = mv88e6xxx_g2_smi_phy_read, 3007 .phy_write = mv88e6xxx_g2_smi_phy_write, 3008 .port_set_link = mv88e6xxx_port_set_link, 3009 .port_set_duplex = mv88e6xxx_port_set_duplex, 3010 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3011 .port_set_speed = mv88e6185_port_set_speed, 3012 .port_tag_remap = mv88e6095_port_tag_remap, 3013 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3014 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3015 .port_set_ether_type = mv88e6351_port_set_ether_type, 3016 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3017 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3018 .port_pause_limit = mv88e6097_port_pause_limit, 3019 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3020 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3021 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3022 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3023 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3024 .stats_get_strings = mv88e6095_stats_get_strings, 3025 .stats_get_stats = mv88e6095_stats_get_stats, 3026 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3027 .set_egress_port = mv88e6095_g1_set_egress_port, 3028 .watchdog_ops = &mv88e6097_watchdog_ops, 3029 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3030 .pot_clear = mv88e6xxx_g2_pot_clear, 3031 .reset = mv88e6352_g1_reset, 3032 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3033 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3034 }; 3035 3036 static const struct mv88e6xxx_ops mv88e6352_ops = { 3037 /* MV88E6XXX_FAMILY_6352 */ 3038 .irl_init_all = mv88e6352_g2_irl_init_all, 3039 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3040 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3042 .phy_read = mv88e6xxx_g2_smi_phy_read, 3043 .phy_write = mv88e6xxx_g2_smi_phy_write, 3044 .port_set_link = mv88e6xxx_port_set_link, 3045 .port_set_duplex = mv88e6xxx_port_set_duplex, 3046 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3047 .port_set_speed = mv88e6352_port_set_speed, 3048 .port_tag_remap = mv88e6095_port_tag_remap, 3049 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3050 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3051 .port_set_ether_type = mv88e6351_port_set_ether_type, 3052 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3053 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3054 .port_pause_limit = mv88e6097_port_pause_limit, 3055 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3056 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3057 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3058 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3059 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3060 .stats_get_strings = mv88e6095_stats_get_strings, 3061 .stats_get_stats = mv88e6095_stats_get_stats, 3062 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3063 .set_egress_port = mv88e6095_g1_set_egress_port, 3064 .watchdog_ops = &mv88e6097_watchdog_ops, 3065 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3066 .pot_clear = mv88e6xxx_g2_pot_clear, 3067 .reset = mv88e6352_g1_reset, 3068 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3069 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3070 .serdes_power = mv88e6352_serdes_power, 3071 }; 3072 3073 static const struct mv88e6xxx_ops mv88e6390_ops = { 3074 /* MV88E6XXX_FAMILY_6390 */ 3075 .irl_init_all = mv88e6390_g2_irl_init_all, 3076 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3077 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3078 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3079 .phy_read = mv88e6xxx_g2_smi_phy_read, 3080 .phy_write = mv88e6xxx_g2_smi_phy_write, 3081 .port_set_link = mv88e6xxx_port_set_link, 3082 .port_set_duplex = mv88e6xxx_port_set_duplex, 3083 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3084 .port_set_speed = mv88e6390_port_set_speed, 3085 .port_tag_remap = mv88e6390_port_tag_remap, 3086 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3087 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3088 .port_set_ether_type = mv88e6351_port_set_ether_type, 3089 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3090 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3091 .port_pause_limit = mv88e6390_port_pause_limit, 3092 .port_set_cmode = mv88e6390x_port_set_cmode, 3093 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3094 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3095 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3096 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3097 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3098 .stats_get_strings = mv88e6320_stats_get_strings, 3099 .stats_get_stats = mv88e6390_stats_get_stats, 3100 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3101 .set_egress_port = mv88e6390_g1_set_egress_port, 3102 .watchdog_ops = &mv88e6390_watchdog_ops, 3103 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3104 .pot_clear = mv88e6xxx_g2_pot_clear, 3105 .reset = mv88e6352_g1_reset, 3106 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3107 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3108 .serdes_power = mv88e6390_serdes_power, 3109 }; 3110 3111 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3112 /* MV88E6XXX_FAMILY_6390 */ 3113 .irl_init_all = mv88e6390_g2_irl_init_all, 3114 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3115 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3116 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3117 .phy_read = mv88e6xxx_g2_smi_phy_read, 3118 .phy_write = mv88e6xxx_g2_smi_phy_write, 3119 .port_set_link = mv88e6xxx_port_set_link, 3120 .port_set_duplex = mv88e6xxx_port_set_duplex, 3121 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3122 .port_set_speed = mv88e6390x_port_set_speed, 3123 .port_tag_remap = mv88e6390_port_tag_remap, 3124 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3125 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3126 .port_set_ether_type = mv88e6351_port_set_ether_type, 3127 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3128 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3129 .port_pause_limit = mv88e6390_port_pause_limit, 3130 .port_set_cmode = mv88e6390x_port_set_cmode, 3131 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3132 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3133 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3134 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3135 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3136 .stats_get_strings = mv88e6320_stats_get_strings, 3137 .stats_get_stats = mv88e6390_stats_get_stats, 3138 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3139 .set_egress_port = mv88e6390_g1_set_egress_port, 3140 .watchdog_ops = &mv88e6390_watchdog_ops, 3141 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3142 .pot_clear = mv88e6xxx_g2_pot_clear, 3143 .reset = mv88e6352_g1_reset, 3144 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3145 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3146 .serdes_power = mv88e6390_serdes_power, 3147 }; 3148 3149 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3150 [MV88E6085] = { 3151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3152 .family = MV88E6XXX_FAMILY_6097, 3153 .name = "Marvell 88E6085", 3154 .num_databases = 4096, 3155 .num_ports = 10, 3156 .max_vid = 4095, 3157 .port_base_addr = 0x10, 3158 .global1_addr = 0x1b, 3159 .global2_addr = 0x1c, 3160 .age_time_coeff = 15000, 3161 .g1_irqs = 8, 3162 .g2_irqs = 10, 3163 .atu_move_port_mask = 0xf, 3164 .pvt = true, 3165 .multi_chip = true, 3166 .tag_protocol = DSA_TAG_PROTO_DSA, 3167 .ops = &mv88e6085_ops, 3168 }, 3169 3170 [MV88E6095] = { 3171 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3172 .family = MV88E6XXX_FAMILY_6095, 3173 .name = "Marvell 88E6095/88E6095F", 3174 .num_databases = 256, 3175 .num_ports = 11, 3176 .max_vid = 4095, 3177 .port_base_addr = 0x10, 3178 .global1_addr = 0x1b, 3179 .global2_addr = 0x1c, 3180 .age_time_coeff = 15000, 3181 .g1_irqs = 8, 3182 .atu_move_port_mask = 0xf, 3183 .multi_chip = true, 3184 .tag_protocol = DSA_TAG_PROTO_DSA, 3185 .ops = &mv88e6095_ops, 3186 }, 3187 3188 [MV88E6097] = { 3189 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3190 .family = MV88E6XXX_FAMILY_6097, 3191 .name = "Marvell 88E6097/88E6097F", 3192 .num_databases = 4096, 3193 .num_ports = 11, 3194 .max_vid = 4095, 3195 .port_base_addr = 0x10, 3196 .global1_addr = 0x1b, 3197 .global2_addr = 0x1c, 3198 .age_time_coeff = 15000, 3199 .g1_irqs = 8, 3200 .g2_irqs = 10, 3201 .atu_move_port_mask = 0xf, 3202 .pvt = true, 3203 .multi_chip = true, 3204 .tag_protocol = DSA_TAG_PROTO_EDSA, 3205 .ops = &mv88e6097_ops, 3206 }, 3207 3208 [MV88E6123] = { 3209 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3210 .family = MV88E6XXX_FAMILY_6165, 3211 .name = "Marvell 88E6123", 3212 .num_databases = 4096, 3213 .num_ports = 3, 3214 .max_vid = 4095, 3215 .port_base_addr = 0x10, 3216 .global1_addr = 0x1b, 3217 .global2_addr = 0x1c, 3218 .age_time_coeff = 15000, 3219 .g1_irqs = 9, 3220 .g2_irqs = 10, 3221 .atu_move_port_mask = 0xf, 3222 .pvt = true, 3223 .multi_chip = true, 3224 .tag_protocol = DSA_TAG_PROTO_EDSA, 3225 .ops = &mv88e6123_ops, 3226 }, 3227 3228 [MV88E6131] = { 3229 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3230 .family = MV88E6XXX_FAMILY_6185, 3231 .name = "Marvell 88E6131", 3232 .num_databases = 256, 3233 .num_ports = 8, 3234 .max_vid = 4095, 3235 .port_base_addr = 0x10, 3236 .global1_addr = 0x1b, 3237 .global2_addr = 0x1c, 3238 .age_time_coeff = 15000, 3239 .g1_irqs = 9, 3240 .atu_move_port_mask = 0xf, 3241 .multi_chip = true, 3242 .tag_protocol = DSA_TAG_PROTO_DSA, 3243 .ops = &mv88e6131_ops, 3244 }, 3245 3246 [MV88E6141] = { 3247 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3248 .family = MV88E6XXX_FAMILY_6341, 3249 .name = "Marvell 88E6341", 3250 .num_databases = 4096, 3251 .num_ports = 6, 3252 .max_vid = 4095, 3253 .port_base_addr = 0x10, 3254 .global1_addr = 0x1b, 3255 .global2_addr = 0x1c, 3256 .age_time_coeff = 3750, 3257 .atu_move_port_mask = 0x1f, 3258 .g2_irqs = 10, 3259 .pvt = true, 3260 .multi_chip = true, 3261 .tag_protocol = DSA_TAG_PROTO_EDSA, 3262 .ops = &mv88e6141_ops, 3263 }, 3264 3265 [MV88E6161] = { 3266 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3267 .family = MV88E6XXX_FAMILY_6165, 3268 .name = "Marvell 88E6161", 3269 .num_databases = 4096, 3270 .num_ports = 6, 3271 .max_vid = 4095, 3272 .port_base_addr = 0x10, 3273 .global1_addr = 0x1b, 3274 .global2_addr = 0x1c, 3275 .age_time_coeff = 15000, 3276 .g1_irqs = 9, 3277 .g2_irqs = 10, 3278 .atu_move_port_mask = 0xf, 3279 .pvt = true, 3280 .multi_chip = true, 3281 .tag_protocol = DSA_TAG_PROTO_EDSA, 3282 .ops = &mv88e6161_ops, 3283 }, 3284 3285 [MV88E6165] = { 3286 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3287 .family = MV88E6XXX_FAMILY_6165, 3288 .name = "Marvell 88E6165", 3289 .num_databases = 4096, 3290 .num_ports = 6, 3291 .max_vid = 4095, 3292 .port_base_addr = 0x10, 3293 .global1_addr = 0x1b, 3294 .global2_addr = 0x1c, 3295 .age_time_coeff = 15000, 3296 .g1_irqs = 9, 3297 .g2_irqs = 10, 3298 .atu_move_port_mask = 0xf, 3299 .pvt = true, 3300 .multi_chip = true, 3301 .tag_protocol = DSA_TAG_PROTO_DSA, 3302 .ops = &mv88e6165_ops, 3303 }, 3304 3305 [MV88E6171] = { 3306 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3307 .family = MV88E6XXX_FAMILY_6351, 3308 .name = "Marvell 88E6171", 3309 .num_databases = 4096, 3310 .num_ports = 7, 3311 .max_vid = 4095, 3312 .port_base_addr = 0x10, 3313 .global1_addr = 0x1b, 3314 .global2_addr = 0x1c, 3315 .age_time_coeff = 15000, 3316 .g1_irqs = 9, 3317 .g2_irqs = 10, 3318 .atu_move_port_mask = 0xf, 3319 .pvt = true, 3320 .multi_chip = true, 3321 .tag_protocol = DSA_TAG_PROTO_EDSA, 3322 .ops = &mv88e6171_ops, 3323 }, 3324 3325 [MV88E6172] = { 3326 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3327 .family = MV88E6XXX_FAMILY_6352, 3328 .name = "Marvell 88E6172", 3329 .num_databases = 4096, 3330 .num_ports = 7, 3331 .max_vid = 4095, 3332 .port_base_addr = 0x10, 3333 .global1_addr = 0x1b, 3334 .global2_addr = 0x1c, 3335 .age_time_coeff = 15000, 3336 .g1_irqs = 9, 3337 .g2_irqs = 10, 3338 .atu_move_port_mask = 0xf, 3339 .pvt = true, 3340 .multi_chip = true, 3341 .tag_protocol = DSA_TAG_PROTO_EDSA, 3342 .ops = &mv88e6172_ops, 3343 }, 3344 3345 [MV88E6175] = { 3346 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3347 .family = MV88E6XXX_FAMILY_6351, 3348 .name = "Marvell 88E6175", 3349 .num_databases = 4096, 3350 .num_ports = 7, 3351 .max_vid = 4095, 3352 .port_base_addr = 0x10, 3353 .global1_addr = 0x1b, 3354 .global2_addr = 0x1c, 3355 .age_time_coeff = 15000, 3356 .g1_irqs = 9, 3357 .g2_irqs = 10, 3358 .atu_move_port_mask = 0xf, 3359 .pvt = true, 3360 .multi_chip = true, 3361 .tag_protocol = DSA_TAG_PROTO_EDSA, 3362 .ops = &mv88e6175_ops, 3363 }, 3364 3365 [MV88E6176] = { 3366 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3367 .family = MV88E6XXX_FAMILY_6352, 3368 .name = "Marvell 88E6176", 3369 .num_databases = 4096, 3370 .num_ports = 7, 3371 .max_vid = 4095, 3372 .port_base_addr = 0x10, 3373 .global1_addr = 0x1b, 3374 .global2_addr = 0x1c, 3375 .age_time_coeff = 15000, 3376 .g1_irqs = 9, 3377 .g2_irqs = 10, 3378 .atu_move_port_mask = 0xf, 3379 .pvt = true, 3380 .multi_chip = true, 3381 .tag_protocol = DSA_TAG_PROTO_EDSA, 3382 .ops = &mv88e6176_ops, 3383 }, 3384 3385 [MV88E6185] = { 3386 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3387 .family = MV88E6XXX_FAMILY_6185, 3388 .name = "Marvell 88E6185", 3389 .num_databases = 256, 3390 .num_ports = 10, 3391 .max_vid = 4095, 3392 .port_base_addr = 0x10, 3393 .global1_addr = 0x1b, 3394 .global2_addr = 0x1c, 3395 .age_time_coeff = 15000, 3396 .g1_irqs = 8, 3397 .atu_move_port_mask = 0xf, 3398 .multi_chip = true, 3399 .tag_protocol = DSA_TAG_PROTO_EDSA, 3400 .ops = &mv88e6185_ops, 3401 }, 3402 3403 [MV88E6190] = { 3404 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3405 .family = MV88E6XXX_FAMILY_6390, 3406 .name = "Marvell 88E6190", 3407 .num_databases = 4096, 3408 .num_ports = 11, /* 10 + Z80 */ 3409 .max_vid = 8191, 3410 .port_base_addr = 0x0, 3411 .global1_addr = 0x1b, 3412 .global2_addr = 0x1c, 3413 .tag_protocol = DSA_TAG_PROTO_DSA, 3414 .age_time_coeff = 3750, 3415 .g1_irqs = 9, 3416 .g2_irqs = 14, 3417 .pvt = true, 3418 .multi_chip = true, 3419 .atu_move_port_mask = 0x1f, 3420 .ops = &mv88e6190_ops, 3421 }, 3422 3423 [MV88E6190X] = { 3424 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3425 .family = MV88E6XXX_FAMILY_6390, 3426 .name = "Marvell 88E6190X", 3427 .num_databases = 4096, 3428 .num_ports = 11, /* 10 + Z80 */ 3429 .max_vid = 8191, 3430 .port_base_addr = 0x0, 3431 .global1_addr = 0x1b, 3432 .global2_addr = 0x1c, 3433 .age_time_coeff = 3750, 3434 .g1_irqs = 9, 3435 .g2_irqs = 14, 3436 .atu_move_port_mask = 0x1f, 3437 .pvt = true, 3438 .multi_chip = true, 3439 .tag_protocol = DSA_TAG_PROTO_DSA, 3440 .ops = &mv88e6190x_ops, 3441 }, 3442 3443 [MV88E6191] = { 3444 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3445 .family = MV88E6XXX_FAMILY_6390, 3446 .name = "Marvell 88E6191", 3447 .num_databases = 4096, 3448 .num_ports = 11, /* 10 + Z80 */ 3449 .max_vid = 8191, 3450 .port_base_addr = 0x0, 3451 .global1_addr = 0x1b, 3452 .global2_addr = 0x1c, 3453 .age_time_coeff = 3750, 3454 .g1_irqs = 9, 3455 .g2_irqs = 14, 3456 .atu_move_port_mask = 0x1f, 3457 .pvt = true, 3458 .multi_chip = true, 3459 .tag_protocol = DSA_TAG_PROTO_DSA, 3460 .ops = &mv88e6191_ops, 3461 }, 3462 3463 [MV88E6240] = { 3464 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3465 .family = MV88E6XXX_FAMILY_6352, 3466 .name = "Marvell 88E6240", 3467 .num_databases = 4096, 3468 .num_ports = 7, 3469 .max_vid = 4095, 3470 .port_base_addr = 0x10, 3471 .global1_addr = 0x1b, 3472 .global2_addr = 0x1c, 3473 .age_time_coeff = 15000, 3474 .g1_irqs = 9, 3475 .g2_irqs = 10, 3476 .atu_move_port_mask = 0xf, 3477 .pvt = true, 3478 .multi_chip = true, 3479 .tag_protocol = DSA_TAG_PROTO_EDSA, 3480 .ops = &mv88e6240_ops, 3481 }, 3482 3483 [MV88E6290] = { 3484 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3485 .family = MV88E6XXX_FAMILY_6390, 3486 .name = "Marvell 88E6290", 3487 .num_databases = 4096, 3488 .num_ports = 11, /* 10 + Z80 */ 3489 .max_vid = 8191, 3490 .port_base_addr = 0x0, 3491 .global1_addr = 0x1b, 3492 .global2_addr = 0x1c, 3493 .age_time_coeff = 3750, 3494 .g1_irqs = 9, 3495 .g2_irqs = 14, 3496 .atu_move_port_mask = 0x1f, 3497 .pvt = true, 3498 .multi_chip = true, 3499 .tag_protocol = DSA_TAG_PROTO_DSA, 3500 .ops = &mv88e6290_ops, 3501 }, 3502 3503 [MV88E6320] = { 3504 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3505 .family = MV88E6XXX_FAMILY_6320, 3506 .name = "Marvell 88E6320", 3507 .num_databases = 4096, 3508 .num_ports = 7, 3509 .max_vid = 4095, 3510 .port_base_addr = 0x10, 3511 .global1_addr = 0x1b, 3512 .global2_addr = 0x1c, 3513 .age_time_coeff = 15000, 3514 .g1_irqs = 8, 3515 .atu_move_port_mask = 0xf, 3516 .pvt = true, 3517 .multi_chip = true, 3518 .tag_protocol = DSA_TAG_PROTO_EDSA, 3519 .ops = &mv88e6320_ops, 3520 }, 3521 3522 [MV88E6321] = { 3523 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3524 .family = MV88E6XXX_FAMILY_6320, 3525 .name = "Marvell 88E6321", 3526 .num_databases = 4096, 3527 .num_ports = 7, 3528 .max_vid = 4095, 3529 .port_base_addr = 0x10, 3530 .global1_addr = 0x1b, 3531 .global2_addr = 0x1c, 3532 .age_time_coeff = 15000, 3533 .g1_irqs = 8, 3534 .atu_move_port_mask = 0xf, 3535 .multi_chip = true, 3536 .tag_protocol = DSA_TAG_PROTO_EDSA, 3537 .ops = &mv88e6321_ops, 3538 }, 3539 3540 [MV88E6341] = { 3541 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3542 .family = MV88E6XXX_FAMILY_6341, 3543 .name = "Marvell 88E6341", 3544 .num_databases = 4096, 3545 .num_ports = 6, 3546 .max_vid = 4095, 3547 .port_base_addr = 0x10, 3548 .global1_addr = 0x1b, 3549 .global2_addr = 0x1c, 3550 .age_time_coeff = 3750, 3551 .atu_move_port_mask = 0x1f, 3552 .g2_irqs = 10, 3553 .pvt = true, 3554 .multi_chip = true, 3555 .tag_protocol = DSA_TAG_PROTO_EDSA, 3556 .ops = &mv88e6341_ops, 3557 }, 3558 3559 [MV88E6350] = { 3560 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3561 .family = MV88E6XXX_FAMILY_6351, 3562 .name = "Marvell 88E6350", 3563 .num_databases = 4096, 3564 .num_ports = 7, 3565 .max_vid = 4095, 3566 .port_base_addr = 0x10, 3567 .global1_addr = 0x1b, 3568 .global2_addr = 0x1c, 3569 .age_time_coeff = 15000, 3570 .g1_irqs = 9, 3571 .g2_irqs = 10, 3572 .atu_move_port_mask = 0xf, 3573 .pvt = true, 3574 .multi_chip = true, 3575 .tag_protocol = DSA_TAG_PROTO_EDSA, 3576 .ops = &mv88e6350_ops, 3577 }, 3578 3579 [MV88E6351] = { 3580 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3581 .family = MV88E6XXX_FAMILY_6351, 3582 .name = "Marvell 88E6351", 3583 .num_databases = 4096, 3584 .num_ports = 7, 3585 .max_vid = 4095, 3586 .port_base_addr = 0x10, 3587 .global1_addr = 0x1b, 3588 .global2_addr = 0x1c, 3589 .age_time_coeff = 15000, 3590 .g1_irqs = 9, 3591 .g2_irqs = 10, 3592 .atu_move_port_mask = 0xf, 3593 .pvt = true, 3594 .multi_chip = true, 3595 .tag_protocol = DSA_TAG_PROTO_EDSA, 3596 .ops = &mv88e6351_ops, 3597 }, 3598 3599 [MV88E6352] = { 3600 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3601 .family = MV88E6XXX_FAMILY_6352, 3602 .name = "Marvell 88E6352", 3603 .num_databases = 4096, 3604 .num_ports = 7, 3605 .max_vid = 4095, 3606 .port_base_addr = 0x10, 3607 .global1_addr = 0x1b, 3608 .global2_addr = 0x1c, 3609 .age_time_coeff = 15000, 3610 .g1_irqs = 9, 3611 .g2_irqs = 10, 3612 .atu_move_port_mask = 0xf, 3613 .pvt = true, 3614 .multi_chip = true, 3615 .tag_protocol = DSA_TAG_PROTO_EDSA, 3616 .ops = &mv88e6352_ops, 3617 }, 3618 [MV88E6390] = { 3619 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3620 .family = MV88E6XXX_FAMILY_6390, 3621 .name = "Marvell 88E6390", 3622 .num_databases = 4096, 3623 .num_ports = 11, /* 10 + Z80 */ 3624 .max_vid = 8191, 3625 .port_base_addr = 0x0, 3626 .global1_addr = 0x1b, 3627 .global2_addr = 0x1c, 3628 .age_time_coeff = 3750, 3629 .g1_irqs = 9, 3630 .g2_irqs = 14, 3631 .atu_move_port_mask = 0x1f, 3632 .pvt = true, 3633 .multi_chip = true, 3634 .tag_protocol = DSA_TAG_PROTO_DSA, 3635 .ops = &mv88e6390_ops, 3636 }, 3637 [MV88E6390X] = { 3638 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3639 .family = MV88E6XXX_FAMILY_6390, 3640 .name = "Marvell 88E6390X", 3641 .num_databases = 4096, 3642 .num_ports = 11, /* 10 + Z80 */ 3643 .max_vid = 8191, 3644 .port_base_addr = 0x0, 3645 .global1_addr = 0x1b, 3646 .global2_addr = 0x1c, 3647 .age_time_coeff = 3750, 3648 .g1_irqs = 9, 3649 .g2_irqs = 14, 3650 .atu_move_port_mask = 0x1f, 3651 .pvt = true, 3652 .multi_chip = true, 3653 .tag_protocol = DSA_TAG_PROTO_DSA, 3654 .ops = &mv88e6390x_ops, 3655 }, 3656 }; 3657 3658 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3659 { 3660 int i; 3661 3662 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3663 if (mv88e6xxx_table[i].prod_num == prod_num) 3664 return &mv88e6xxx_table[i]; 3665 3666 return NULL; 3667 } 3668 3669 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3670 { 3671 const struct mv88e6xxx_info *info; 3672 unsigned int prod_num, rev; 3673 u16 id; 3674 int err; 3675 3676 mutex_lock(&chip->reg_lock); 3677 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3678 mutex_unlock(&chip->reg_lock); 3679 if (err) 3680 return err; 3681 3682 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3683 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3684 3685 info = mv88e6xxx_lookup_info(prod_num); 3686 if (!info) 3687 return -ENODEV; 3688 3689 /* Update the compatible info with the probed one */ 3690 chip->info = info; 3691 3692 err = mv88e6xxx_g2_require(chip); 3693 if (err) 3694 return err; 3695 3696 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3697 chip->info->prod_num, chip->info->name, rev); 3698 3699 return 0; 3700 } 3701 3702 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3703 { 3704 struct mv88e6xxx_chip *chip; 3705 3706 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3707 if (!chip) 3708 return NULL; 3709 3710 chip->dev = dev; 3711 3712 mutex_init(&chip->reg_lock); 3713 INIT_LIST_HEAD(&chip->mdios); 3714 3715 return chip; 3716 } 3717 3718 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3719 struct mii_bus *bus, int sw_addr) 3720 { 3721 if (sw_addr == 0) 3722 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3723 else if (chip->info->multi_chip) 3724 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3725 else 3726 return -EINVAL; 3727 3728 chip->bus = bus; 3729 chip->sw_addr = sw_addr; 3730 3731 return 0; 3732 } 3733 3734 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 3735 int port) 3736 { 3737 struct mv88e6xxx_chip *chip = ds->priv; 3738 3739 return chip->info->tag_protocol; 3740 } 3741 3742 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3743 struct device *host_dev, int sw_addr, 3744 void **priv) 3745 { 3746 struct mv88e6xxx_chip *chip; 3747 struct mii_bus *bus; 3748 int err; 3749 3750 bus = dsa_host_dev_to_mii_bus(host_dev); 3751 if (!bus) 3752 return NULL; 3753 3754 chip = mv88e6xxx_alloc_chip(dsa_dev); 3755 if (!chip) 3756 return NULL; 3757 3758 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3759 chip->info = &mv88e6xxx_table[MV88E6085]; 3760 3761 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3762 if (err) 3763 goto free; 3764 3765 err = mv88e6xxx_detect(chip); 3766 if (err) 3767 goto free; 3768 3769 mutex_lock(&chip->reg_lock); 3770 err = mv88e6xxx_switch_reset(chip); 3771 mutex_unlock(&chip->reg_lock); 3772 if (err) 3773 goto free; 3774 3775 mv88e6xxx_phy_init(chip); 3776 3777 err = mv88e6xxx_mdios_register(chip, NULL); 3778 if (err) 3779 goto free; 3780 3781 *priv = chip; 3782 3783 return chip->info->name; 3784 free: 3785 devm_kfree(dsa_dev, chip); 3786 3787 return NULL; 3788 } 3789 3790 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3791 const struct switchdev_obj_port_mdb *mdb, 3792 struct switchdev_trans *trans) 3793 { 3794 /* We don't need any dynamic resource from the kernel (yet), 3795 * so skip the prepare phase. 3796 */ 3797 3798 return 0; 3799 } 3800 3801 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3802 const struct switchdev_obj_port_mdb *mdb, 3803 struct switchdev_trans *trans) 3804 { 3805 struct mv88e6xxx_chip *chip = ds->priv; 3806 3807 mutex_lock(&chip->reg_lock); 3808 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3809 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3810 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3811 port); 3812 mutex_unlock(&chip->reg_lock); 3813 } 3814 3815 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3816 const struct switchdev_obj_port_mdb *mdb) 3817 { 3818 struct mv88e6xxx_chip *chip = ds->priv; 3819 int err; 3820 3821 mutex_lock(&chip->reg_lock); 3822 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3823 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3824 mutex_unlock(&chip->reg_lock); 3825 3826 return err; 3827 } 3828 3829 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3830 .probe = mv88e6xxx_drv_probe, 3831 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3832 .setup = mv88e6xxx_setup, 3833 .adjust_link = mv88e6xxx_adjust_link, 3834 .get_strings = mv88e6xxx_get_strings, 3835 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3836 .get_sset_count = mv88e6xxx_get_sset_count, 3837 .port_enable = mv88e6xxx_port_enable, 3838 .port_disable = mv88e6xxx_port_disable, 3839 .get_mac_eee = mv88e6xxx_get_mac_eee, 3840 .set_mac_eee = mv88e6xxx_set_mac_eee, 3841 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3842 .get_eeprom = mv88e6xxx_get_eeprom, 3843 .set_eeprom = mv88e6xxx_set_eeprom, 3844 .get_regs_len = mv88e6xxx_get_regs_len, 3845 .get_regs = mv88e6xxx_get_regs, 3846 .set_ageing_time = mv88e6xxx_set_ageing_time, 3847 .port_bridge_join = mv88e6xxx_port_bridge_join, 3848 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3849 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3850 .port_fast_age = mv88e6xxx_port_fast_age, 3851 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3852 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3853 .port_vlan_add = mv88e6xxx_port_vlan_add, 3854 .port_vlan_del = mv88e6xxx_port_vlan_del, 3855 .port_fdb_add = mv88e6xxx_port_fdb_add, 3856 .port_fdb_del = mv88e6xxx_port_fdb_del, 3857 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3858 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3859 .port_mdb_add = mv88e6xxx_port_mdb_add, 3860 .port_mdb_del = mv88e6xxx_port_mdb_del, 3861 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 3862 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 3863 }; 3864 3865 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 3866 .ops = &mv88e6xxx_switch_ops, 3867 }; 3868 3869 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 3870 { 3871 struct device *dev = chip->dev; 3872 struct dsa_switch *ds; 3873 3874 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 3875 if (!ds) 3876 return -ENOMEM; 3877 3878 ds->priv = chip; 3879 ds->ops = &mv88e6xxx_switch_ops; 3880 ds->ageing_time_min = chip->info->age_time_coeff; 3881 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 3882 3883 dev_set_drvdata(dev, ds); 3884 3885 return dsa_register_switch(ds); 3886 } 3887 3888 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3889 { 3890 dsa_unregister_switch(chip->ds); 3891 } 3892 3893 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3894 { 3895 struct device *dev = &mdiodev->dev; 3896 struct device_node *np = dev->of_node; 3897 const struct mv88e6xxx_info *compat_info; 3898 struct mv88e6xxx_chip *chip; 3899 u32 eeprom_len; 3900 int err; 3901 3902 compat_info = of_device_get_match_data(dev); 3903 if (!compat_info) 3904 return -EINVAL; 3905 3906 chip = mv88e6xxx_alloc_chip(dev); 3907 if (!chip) 3908 return -ENOMEM; 3909 3910 chip->info = compat_info; 3911 3912 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3913 if (err) 3914 return err; 3915 3916 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 3917 if (IS_ERR(chip->reset)) 3918 return PTR_ERR(chip->reset); 3919 3920 err = mv88e6xxx_detect(chip); 3921 if (err) 3922 return err; 3923 3924 mv88e6xxx_phy_init(chip); 3925 3926 if (chip->info->ops->get_eeprom && 3927 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3928 chip->eeprom_len = eeprom_len; 3929 3930 mutex_lock(&chip->reg_lock); 3931 err = mv88e6xxx_switch_reset(chip); 3932 mutex_unlock(&chip->reg_lock); 3933 if (err) 3934 goto out; 3935 3936 chip->irq = of_irq_get(np, 0); 3937 if (chip->irq == -EPROBE_DEFER) { 3938 err = chip->irq; 3939 goto out; 3940 } 3941 3942 if (chip->irq > 0) { 3943 /* Has to be performed before the MDIO bus is created, 3944 * because the PHYs will link there interrupts to these 3945 * interrupt controllers 3946 */ 3947 mutex_lock(&chip->reg_lock); 3948 err = mv88e6xxx_g1_irq_setup(chip); 3949 mutex_unlock(&chip->reg_lock); 3950 3951 if (err) 3952 goto out; 3953 3954 if (chip->info->g2_irqs > 0) { 3955 err = mv88e6xxx_g2_irq_setup(chip); 3956 if (err) 3957 goto out_g1_irq; 3958 } 3959 } 3960 3961 err = mv88e6xxx_mdios_register(chip, np); 3962 if (err) 3963 goto out_g2_irq; 3964 3965 err = mv88e6xxx_register_switch(chip); 3966 if (err) 3967 goto out_mdio; 3968 3969 return 0; 3970 3971 out_mdio: 3972 mv88e6xxx_mdios_unregister(chip); 3973 out_g2_irq: 3974 if (chip->info->g2_irqs > 0 && chip->irq > 0) 3975 mv88e6xxx_g2_irq_free(chip); 3976 out_g1_irq: 3977 if (chip->irq > 0) { 3978 mutex_lock(&chip->reg_lock); 3979 mv88e6xxx_g1_irq_free(chip); 3980 mutex_unlock(&chip->reg_lock); 3981 } 3982 out: 3983 return err; 3984 } 3985 3986 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 3987 { 3988 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 3989 struct mv88e6xxx_chip *chip = ds->priv; 3990 3991 mv88e6xxx_phy_destroy(chip); 3992 mv88e6xxx_unregister_switch(chip); 3993 mv88e6xxx_mdios_unregister(chip); 3994 3995 if (chip->irq > 0) { 3996 if (chip->info->g2_irqs > 0) 3997 mv88e6xxx_g2_irq_free(chip); 3998 mutex_lock(&chip->reg_lock); 3999 mv88e6xxx_g1_irq_free(chip); 4000 mutex_unlock(&chip->reg_lock); 4001 } 4002 } 4003 4004 static const struct of_device_id mv88e6xxx_of_match[] = { 4005 { 4006 .compatible = "marvell,mv88e6085", 4007 .data = &mv88e6xxx_table[MV88E6085], 4008 }, 4009 { 4010 .compatible = "marvell,mv88e6190", 4011 .data = &mv88e6xxx_table[MV88E6190], 4012 }, 4013 { /* sentinel */ }, 4014 }; 4015 4016 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4017 4018 static struct mdio_driver mv88e6xxx_driver = { 4019 .probe = mv88e6xxx_probe, 4020 .remove = mv88e6xxx_remove, 4021 .mdiodrv.driver = { 4022 .name = "mv88e6085", 4023 .of_match_table = mv88e6xxx_of_match, 4024 }, 4025 }; 4026 4027 static int __init mv88e6xxx_init(void) 4028 { 4029 register_switch_driver(&mv88e6xxx_switch_drv); 4030 return mdio_driver_register(&mv88e6xxx_driver); 4031 } 4032 module_init(mv88e6xxx_init); 4033 4034 static void __exit mv88e6xxx_cleanup(void) 4035 { 4036 mdio_driver_unregister(&mv88e6xxx_driver); 4037 unregister_switch_driver(&mv88e6xxx_switch_drv); 4038 } 4039 module_exit(mv88e6xxx_cleanup); 4040 4041 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4042 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4043 MODULE_LICENSE("GPL"); 4044