1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 /* The 88e6250 family does not have the PHY detect bit. Instead, 475 * report whether the port is internal. 476 */ 477 if (chip->info->family == MV88E6XXX_FAMILY_6250) 478 return port < chip->info->num_internal_phys; 479 480 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 481 if (err) { 482 dev_err(chip->dev, 483 "p%d: %s: failed to read port status\n", 484 port, __func__); 485 return err; 486 } 487 488 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 489 } 490 491 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 492 struct phylink_link_state *state) 493 { 494 struct mv88e6xxx_chip *chip = ds->priv; 495 int lane; 496 int err; 497 498 mv88e6xxx_reg_lock(chip); 499 lane = mv88e6xxx_serdes_get_lane(chip, port); 500 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 501 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 502 state); 503 else 504 err = -EOPNOTSUPP; 505 mv88e6xxx_reg_unlock(chip); 506 507 return err; 508 } 509 510 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 511 unsigned int mode, 512 phy_interface_t interface, 513 const unsigned long *advertise) 514 { 515 const struct mv88e6xxx_ops *ops = chip->info->ops; 516 int lane; 517 518 if (ops->serdes_pcs_config) { 519 lane = mv88e6xxx_serdes_get_lane(chip, port); 520 if (lane >= 0) 521 return ops->serdes_pcs_config(chip, port, lane, mode, 522 interface, advertise); 523 } 524 525 return 0; 526 } 527 528 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 529 { 530 struct mv88e6xxx_chip *chip = ds->priv; 531 const struct mv88e6xxx_ops *ops; 532 int err = 0; 533 int lane; 534 535 ops = chip->info->ops; 536 537 if (ops->serdes_pcs_an_restart) { 538 mv88e6xxx_reg_lock(chip); 539 lane = mv88e6xxx_serdes_get_lane(chip, port); 540 if (lane >= 0) 541 err = ops->serdes_pcs_an_restart(chip, port, lane); 542 mv88e6xxx_reg_unlock(chip); 543 544 if (err) 545 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 546 } 547 } 548 549 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 550 unsigned int mode, 551 int speed, int duplex) 552 { 553 const struct mv88e6xxx_ops *ops = chip->info->ops; 554 int lane; 555 556 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 557 lane = mv88e6xxx_serdes_get_lane(chip, port); 558 if (lane >= 0) 559 return ops->serdes_pcs_link_up(chip, port, lane, 560 speed, duplex); 561 } 562 563 return 0; 564 } 565 566 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 567 unsigned long *mask, 568 struct phylink_link_state *state) 569 { 570 if (!phy_interface_mode_is_8023z(state->interface)) { 571 /* 10M and 100M are only supported in non-802.3z mode */ 572 phylink_set(mask, 10baseT_Half); 573 phylink_set(mask, 10baseT_Full); 574 phylink_set(mask, 100baseT_Half); 575 phylink_set(mask, 100baseT_Full); 576 } 577 } 578 579 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 580 unsigned long *mask, 581 struct phylink_link_state *state) 582 { 583 /* FIXME: if the port is in 1000Base-X mode, then it only supports 584 * 1000M FD speeds. In this case, CMODE will indicate 5. 585 */ 586 phylink_set(mask, 1000baseT_Full); 587 phylink_set(mask, 1000baseX_Full); 588 589 mv88e6065_phylink_validate(chip, port, mask, state); 590 } 591 592 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 593 unsigned long *mask, 594 struct phylink_link_state *state) 595 { 596 if (port >= 5) 597 phylink_set(mask, 2500baseX_Full); 598 599 /* No ethtool bits for 200Mbps */ 600 phylink_set(mask, 1000baseT_Full); 601 phylink_set(mask, 1000baseX_Full); 602 603 mv88e6065_phylink_validate(chip, port, mask, state); 604 } 605 606 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 607 unsigned long *mask, 608 struct phylink_link_state *state) 609 { 610 /* No ethtool bits for 200Mbps */ 611 phylink_set(mask, 1000baseT_Full); 612 phylink_set(mask, 1000baseX_Full); 613 614 mv88e6065_phylink_validate(chip, port, mask, state); 615 } 616 617 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 618 unsigned long *mask, 619 struct phylink_link_state *state) 620 { 621 if (port >= 9) { 622 phylink_set(mask, 2500baseX_Full); 623 phylink_set(mask, 2500baseT_Full); 624 } 625 626 /* No ethtool bits for 200Mbps */ 627 phylink_set(mask, 1000baseT_Full); 628 phylink_set(mask, 1000baseX_Full); 629 630 mv88e6065_phylink_validate(chip, port, mask, state); 631 } 632 633 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 634 unsigned long *mask, 635 struct phylink_link_state *state) 636 { 637 if (port >= 9) { 638 phylink_set(mask, 10000baseT_Full); 639 phylink_set(mask, 10000baseKR_Full); 640 } 641 642 mv88e6390_phylink_validate(chip, port, mask, state); 643 } 644 645 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 646 unsigned long *mask, 647 struct phylink_link_state *state) 648 { 649 bool is_6191x = 650 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 651 652 if (((port == 0 || port == 9) && !is_6191x) || port == 10) { 653 phylink_set(mask, 10000baseT_Full); 654 phylink_set(mask, 10000baseKR_Full); 655 phylink_set(mask, 10000baseCR_Full); 656 phylink_set(mask, 10000baseSR_Full); 657 phylink_set(mask, 10000baseLR_Full); 658 phylink_set(mask, 10000baseLRM_Full); 659 phylink_set(mask, 10000baseER_Full); 660 phylink_set(mask, 5000baseT_Full); 661 phylink_set(mask, 2500baseX_Full); 662 phylink_set(mask, 2500baseT_Full); 663 } 664 665 phylink_set(mask, 1000baseT_Full); 666 phylink_set(mask, 1000baseX_Full); 667 668 mv88e6065_phylink_validate(chip, port, mask, state); 669 } 670 671 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 672 unsigned long *supported, 673 struct phylink_link_state *state) 674 { 675 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 676 struct mv88e6xxx_chip *chip = ds->priv; 677 678 /* Allow all the expected bits */ 679 phylink_set(mask, Autoneg); 680 phylink_set(mask, Pause); 681 phylink_set_port_modes(mask); 682 683 if (chip->info->ops->phylink_validate) 684 chip->info->ops->phylink_validate(chip, port, mask, state); 685 686 linkmode_and(supported, supported, mask); 687 linkmode_and(state->advertising, state->advertising, mask); 688 689 /* We can only operate at 2500BaseX or 1000BaseX. If requested 690 * to advertise both, only report advertising at 2500BaseX. 691 */ 692 phylink_helper_basex_speed(state); 693 } 694 695 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 696 unsigned int mode, 697 const struct phylink_link_state *state) 698 { 699 struct mv88e6xxx_chip *chip = ds->priv; 700 struct mv88e6xxx_port *p; 701 int err = 0; 702 703 p = &chip->ports[port]; 704 705 mv88e6xxx_reg_lock(chip); 706 707 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 708 /* In inband mode, the link may come up at any time while the 709 * link is not forced down. Force the link down while we 710 * reconfigure the interface mode. 711 */ 712 if (mode == MLO_AN_INBAND && 713 p->interface != state->interface && 714 chip->info->ops->port_set_link) 715 chip->info->ops->port_set_link(chip, port, 716 LINK_FORCED_DOWN); 717 718 err = mv88e6xxx_port_config_interface(chip, port, 719 state->interface); 720 if (err && err != -EOPNOTSUPP) 721 goto err_unlock; 722 723 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 724 state->interface, 725 state->advertising); 726 /* FIXME: we should restart negotiation if something changed - 727 * which is something we get if we convert to using phylinks 728 * PCS operations. 729 */ 730 if (err > 0) 731 err = 0; 732 } 733 734 /* Undo the forced down state above after completing configuration 735 * irrespective of its state on entry, which allows the link to come 736 * up in the in-band case where there is no separate SERDES. Also 737 * ensure that the link can come up if the PPU is in use and we are 738 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 739 */ 740 if (chip->info->ops->port_set_link && 741 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 742 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 743 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 744 745 p->interface = state->interface; 746 747 err_unlock: 748 mv88e6xxx_reg_unlock(chip); 749 750 if (err && err != -EOPNOTSUPP) 751 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 752 } 753 754 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 755 unsigned int mode, 756 phy_interface_t interface) 757 { 758 struct mv88e6xxx_chip *chip = ds->priv; 759 const struct mv88e6xxx_ops *ops; 760 int err = 0; 761 762 ops = chip->info->ops; 763 764 mv88e6xxx_reg_lock(chip); 765 /* Force the link down if we know the port may not be automatically 766 * updated by the switch or if we are using fixed-link mode. 767 */ 768 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 769 mode == MLO_AN_FIXED) && ops->port_sync_link) 770 err = ops->port_sync_link(chip, port, mode, false); 771 772 if (!err && ops->port_set_speed_duplex) 773 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 774 DUPLEX_UNFORCED); 775 mv88e6xxx_reg_unlock(chip); 776 777 if (err) 778 dev_err(chip->dev, 779 "p%d: failed to force MAC link down\n", port); 780 } 781 782 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 783 unsigned int mode, phy_interface_t interface, 784 struct phy_device *phydev, 785 int speed, int duplex, 786 bool tx_pause, bool rx_pause) 787 { 788 struct mv88e6xxx_chip *chip = ds->priv; 789 const struct mv88e6xxx_ops *ops; 790 int err = 0; 791 792 ops = chip->info->ops; 793 794 mv88e6xxx_reg_lock(chip); 795 /* Configure and force the link up if we know that the port may not 796 * automatically updated by the switch or if we are using fixed-link 797 * mode. 798 */ 799 if (!mv88e6xxx_port_ppu_updates(chip, port) || 800 mode == MLO_AN_FIXED) { 801 /* FIXME: for an automedia port, should we force the link 802 * down here - what if the link comes up due to "other" media 803 * while we're bringing the port up, how is the exclusivity 804 * handled in the Marvell hardware? E.g. port 2 on 88E6390 805 * shared between internal PHY and Serdes. 806 */ 807 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 808 duplex); 809 if (err) 810 goto error; 811 812 if (ops->port_set_speed_duplex) { 813 err = ops->port_set_speed_duplex(chip, port, 814 speed, duplex); 815 if (err && err != -EOPNOTSUPP) 816 goto error; 817 } 818 819 if (ops->port_sync_link) 820 err = ops->port_sync_link(chip, port, mode, true); 821 } 822 error: 823 mv88e6xxx_reg_unlock(chip); 824 825 if (err && err != -EOPNOTSUPP) 826 dev_err(ds->dev, 827 "p%d: failed to configure MAC link up\n", port); 828 } 829 830 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 831 { 832 if (!chip->info->ops->stats_snapshot) 833 return -EOPNOTSUPP; 834 835 return chip->info->ops->stats_snapshot(chip, port); 836 } 837 838 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 839 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 840 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 841 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 842 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 843 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 844 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 845 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 846 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 847 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 848 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 849 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 850 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 851 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 852 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 853 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 854 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 855 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 856 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 857 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 858 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 859 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 860 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 861 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 862 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 863 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 864 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 865 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 866 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 867 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 868 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 869 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 870 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 871 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 872 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 873 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 874 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 875 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 876 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 877 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 878 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 879 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 880 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 881 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 882 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 883 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 884 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 885 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 886 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 887 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 888 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 889 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 890 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 891 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 892 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 893 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 894 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 895 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 896 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 897 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 898 }; 899 900 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 901 struct mv88e6xxx_hw_stat *s, 902 int port, u16 bank1_select, 903 u16 histogram) 904 { 905 u32 low; 906 u32 high = 0; 907 u16 reg = 0; 908 int err; 909 u64 value; 910 911 switch (s->type) { 912 case STATS_TYPE_PORT: 913 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 914 if (err) 915 return U64_MAX; 916 917 low = reg; 918 if (s->size == 4) { 919 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 920 if (err) 921 return U64_MAX; 922 low |= ((u32)reg) << 16; 923 } 924 break; 925 case STATS_TYPE_BANK1: 926 reg = bank1_select; 927 fallthrough; 928 case STATS_TYPE_BANK0: 929 reg |= s->reg | histogram; 930 mv88e6xxx_g1_stats_read(chip, reg, &low); 931 if (s->size == 8) 932 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 933 break; 934 default: 935 return U64_MAX; 936 } 937 value = (((u64)high) << 32) | low; 938 return value; 939 } 940 941 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 942 uint8_t *data, int types) 943 { 944 struct mv88e6xxx_hw_stat *stat; 945 int i, j; 946 947 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 948 stat = &mv88e6xxx_hw_stats[i]; 949 if (stat->type & types) { 950 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 951 ETH_GSTRING_LEN); 952 j++; 953 } 954 } 955 956 return j; 957 } 958 959 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 960 uint8_t *data) 961 { 962 return mv88e6xxx_stats_get_strings(chip, data, 963 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 964 } 965 966 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 967 uint8_t *data) 968 { 969 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 970 } 971 972 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 973 uint8_t *data) 974 { 975 return mv88e6xxx_stats_get_strings(chip, data, 976 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 977 } 978 979 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 980 "atu_member_violation", 981 "atu_miss_violation", 982 "atu_full_violation", 983 "vtu_member_violation", 984 "vtu_miss_violation", 985 }; 986 987 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 988 { 989 unsigned int i; 990 991 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 992 strlcpy(data + i * ETH_GSTRING_LEN, 993 mv88e6xxx_atu_vtu_stats_strings[i], 994 ETH_GSTRING_LEN); 995 } 996 997 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 998 u32 stringset, uint8_t *data) 999 { 1000 struct mv88e6xxx_chip *chip = ds->priv; 1001 int count = 0; 1002 1003 if (stringset != ETH_SS_STATS) 1004 return; 1005 1006 mv88e6xxx_reg_lock(chip); 1007 1008 if (chip->info->ops->stats_get_strings) 1009 count = chip->info->ops->stats_get_strings(chip, data); 1010 1011 if (chip->info->ops->serdes_get_strings) { 1012 data += count * ETH_GSTRING_LEN; 1013 count = chip->info->ops->serdes_get_strings(chip, port, data); 1014 } 1015 1016 data += count * ETH_GSTRING_LEN; 1017 mv88e6xxx_atu_vtu_get_strings(data); 1018 1019 mv88e6xxx_reg_unlock(chip); 1020 } 1021 1022 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1023 int types) 1024 { 1025 struct mv88e6xxx_hw_stat *stat; 1026 int i, j; 1027 1028 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1029 stat = &mv88e6xxx_hw_stats[i]; 1030 if (stat->type & types) 1031 j++; 1032 } 1033 return j; 1034 } 1035 1036 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1037 { 1038 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1039 STATS_TYPE_PORT); 1040 } 1041 1042 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1043 { 1044 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1045 } 1046 1047 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1048 { 1049 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1050 STATS_TYPE_BANK1); 1051 } 1052 1053 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1054 { 1055 struct mv88e6xxx_chip *chip = ds->priv; 1056 int serdes_count = 0; 1057 int count = 0; 1058 1059 if (sset != ETH_SS_STATS) 1060 return 0; 1061 1062 mv88e6xxx_reg_lock(chip); 1063 if (chip->info->ops->stats_get_sset_count) 1064 count = chip->info->ops->stats_get_sset_count(chip); 1065 if (count < 0) 1066 goto out; 1067 1068 if (chip->info->ops->serdes_get_sset_count) 1069 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1070 port); 1071 if (serdes_count < 0) { 1072 count = serdes_count; 1073 goto out; 1074 } 1075 count += serdes_count; 1076 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1077 1078 out: 1079 mv88e6xxx_reg_unlock(chip); 1080 1081 return count; 1082 } 1083 1084 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1085 uint64_t *data, int types, 1086 u16 bank1_select, u16 histogram) 1087 { 1088 struct mv88e6xxx_hw_stat *stat; 1089 int i, j; 1090 1091 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1092 stat = &mv88e6xxx_hw_stats[i]; 1093 if (stat->type & types) { 1094 mv88e6xxx_reg_lock(chip); 1095 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1096 bank1_select, 1097 histogram); 1098 mv88e6xxx_reg_unlock(chip); 1099 1100 j++; 1101 } 1102 } 1103 return j; 1104 } 1105 1106 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1107 uint64_t *data) 1108 { 1109 return mv88e6xxx_stats_get_stats(chip, port, data, 1110 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1111 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1112 } 1113 1114 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1115 uint64_t *data) 1116 { 1117 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1118 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1119 } 1120 1121 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1122 uint64_t *data) 1123 { 1124 return mv88e6xxx_stats_get_stats(chip, port, data, 1125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1126 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1127 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1128 } 1129 1130 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1131 uint64_t *data) 1132 { 1133 return mv88e6xxx_stats_get_stats(chip, port, data, 1134 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1135 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1136 0); 1137 } 1138 1139 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1140 uint64_t *data) 1141 { 1142 *data++ = chip->ports[port].atu_member_violation; 1143 *data++ = chip->ports[port].atu_miss_violation; 1144 *data++ = chip->ports[port].atu_full_violation; 1145 *data++ = chip->ports[port].vtu_member_violation; 1146 *data++ = chip->ports[port].vtu_miss_violation; 1147 } 1148 1149 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1150 uint64_t *data) 1151 { 1152 int count = 0; 1153 1154 if (chip->info->ops->stats_get_stats) 1155 count = chip->info->ops->stats_get_stats(chip, port, data); 1156 1157 mv88e6xxx_reg_lock(chip); 1158 if (chip->info->ops->serdes_get_stats) { 1159 data += count; 1160 count = chip->info->ops->serdes_get_stats(chip, port, data); 1161 } 1162 data += count; 1163 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1164 mv88e6xxx_reg_unlock(chip); 1165 } 1166 1167 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1168 uint64_t *data) 1169 { 1170 struct mv88e6xxx_chip *chip = ds->priv; 1171 int ret; 1172 1173 mv88e6xxx_reg_lock(chip); 1174 1175 ret = mv88e6xxx_stats_snapshot(chip, port); 1176 mv88e6xxx_reg_unlock(chip); 1177 1178 if (ret < 0) 1179 return; 1180 1181 mv88e6xxx_get_stats(chip, port, data); 1182 1183 } 1184 1185 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1186 { 1187 struct mv88e6xxx_chip *chip = ds->priv; 1188 int len; 1189 1190 len = 32 * sizeof(u16); 1191 if (chip->info->ops->serdes_get_regs_len) 1192 len += chip->info->ops->serdes_get_regs_len(chip, port); 1193 1194 return len; 1195 } 1196 1197 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1198 struct ethtool_regs *regs, void *_p) 1199 { 1200 struct mv88e6xxx_chip *chip = ds->priv; 1201 int err; 1202 u16 reg; 1203 u16 *p = _p; 1204 int i; 1205 1206 regs->version = chip->info->prod_num; 1207 1208 memset(p, 0xff, 32 * sizeof(u16)); 1209 1210 mv88e6xxx_reg_lock(chip); 1211 1212 for (i = 0; i < 32; i++) { 1213 1214 err = mv88e6xxx_port_read(chip, port, i, ®); 1215 if (!err) 1216 p[i] = reg; 1217 } 1218 1219 if (chip->info->ops->serdes_get_regs) 1220 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1221 1222 mv88e6xxx_reg_unlock(chip); 1223 } 1224 1225 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1226 struct ethtool_eee *e) 1227 { 1228 /* Nothing to do on the port's MAC */ 1229 return 0; 1230 } 1231 1232 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1233 struct ethtool_eee *e) 1234 { 1235 /* Nothing to do on the port's MAC */ 1236 return 0; 1237 } 1238 1239 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1240 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1241 { 1242 struct dsa_switch *ds = chip->ds; 1243 struct dsa_switch_tree *dst = ds->dst; 1244 struct dsa_port *dp, *other_dp; 1245 bool found = false; 1246 u16 pvlan; 1247 1248 /* dev is a physical switch */ 1249 if (dev <= dst->last_switch) { 1250 list_for_each_entry(dp, &dst->ports, list) { 1251 if (dp->ds->index == dev && dp->index == port) { 1252 /* dp might be a DSA link or a user port, so it 1253 * might or might not have a bridge. 1254 * Use the "found" variable for both cases. 1255 */ 1256 found = true; 1257 break; 1258 } 1259 } 1260 /* dev is a virtual bridge */ 1261 } else { 1262 list_for_each_entry(dp, &dst->ports, list) { 1263 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1264 1265 if (!bridge_num) 1266 continue; 1267 1268 if (bridge_num + dst->last_switch != dev) 1269 continue; 1270 1271 found = true; 1272 break; 1273 } 1274 } 1275 1276 /* Prevent frames from unknown switch or virtual bridge */ 1277 if (!found) 1278 return 0; 1279 1280 /* Frames from DSA links and CPU ports can egress any local port */ 1281 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1282 return mv88e6xxx_port_mask(chip); 1283 1284 pvlan = 0; 1285 1286 /* Frames from user ports can egress any local DSA links and CPU ports, 1287 * as well as any local member of their bridge group. 1288 */ 1289 dsa_switch_for_each_port(other_dp, ds) 1290 if (other_dp->type == DSA_PORT_TYPE_CPU || 1291 other_dp->type == DSA_PORT_TYPE_DSA || 1292 dsa_port_bridge_same(dp, other_dp)) 1293 pvlan |= BIT(other_dp->index); 1294 1295 return pvlan; 1296 } 1297 1298 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1299 { 1300 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1301 1302 /* prevent frames from going back out of the port they came in on */ 1303 output_ports &= ~BIT(port); 1304 1305 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1306 } 1307 1308 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1309 u8 state) 1310 { 1311 struct mv88e6xxx_chip *chip = ds->priv; 1312 int err; 1313 1314 mv88e6xxx_reg_lock(chip); 1315 err = mv88e6xxx_port_set_state(chip, port, state); 1316 mv88e6xxx_reg_unlock(chip); 1317 1318 if (err) 1319 dev_err(ds->dev, "p%d: failed to update state\n", port); 1320 } 1321 1322 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1323 { 1324 int err; 1325 1326 if (chip->info->ops->ieee_pri_map) { 1327 err = chip->info->ops->ieee_pri_map(chip); 1328 if (err) 1329 return err; 1330 } 1331 1332 if (chip->info->ops->ip_pri_map) { 1333 err = chip->info->ops->ip_pri_map(chip); 1334 if (err) 1335 return err; 1336 } 1337 1338 return 0; 1339 } 1340 1341 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1342 { 1343 struct dsa_switch *ds = chip->ds; 1344 int target, port; 1345 int err; 1346 1347 if (!chip->info->global2_addr) 1348 return 0; 1349 1350 /* Initialize the routing port to the 32 possible target devices */ 1351 for (target = 0; target < 32; target++) { 1352 port = dsa_routing_port(ds, target); 1353 if (port == ds->num_ports) 1354 port = 0x1f; 1355 1356 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1357 if (err) 1358 return err; 1359 } 1360 1361 if (chip->info->ops->set_cascade_port) { 1362 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1363 err = chip->info->ops->set_cascade_port(chip, port); 1364 if (err) 1365 return err; 1366 } 1367 1368 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1369 if (err) 1370 return err; 1371 1372 return 0; 1373 } 1374 1375 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1376 { 1377 /* Clear all trunk masks and mapping */ 1378 if (chip->info->global2_addr) 1379 return mv88e6xxx_g2_trunk_clear(chip); 1380 1381 return 0; 1382 } 1383 1384 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1385 { 1386 if (chip->info->ops->rmu_disable) 1387 return chip->info->ops->rmu_disable(chip); 1388 1389 return 0; 1390 } 1391 1392 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1393 { 1394 if (chip->info->ops->pot_clear) 1395 return chip->info->ops->pot_clear(chip); 1396 1397 return 0; 1398 } 1399 1400 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1401 { 1402 if (chip->info->ops->mgmt_rsvd2cpu) 1403 return chip->info->ops->mgmt_rsvd2cpu(chip); 1404 1405 return 0; 1406 } 1407 1408 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1409 { 1410 int err; 1411 1412 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1413 if (err) 1414 return err; 1415 1416 /* The chips that have a "learn2all" bit in Global1, ATU 1417 * Control are precisely those whose port registers have a 1418 * Message Port bit in Port Control 1 and hence implement 1419 * ->port_setup_message_port. 1420 */ 1421 if (chip->info->ops->port_setup_message_port) { 1422 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1423 if (err) 1424 return err; 1425 } 1426 1427 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1428 } 1429 1430 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1431 { 1432 int port; 1433 int err; 1434 1435 if (!chip->info->ops->irl_init_all) 1436 return 0; 1437 1438 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1439 /* Disable ingress rate limiting by resetting all per port 1440 * ingress rate limit resources to their initial state. 1441 */ 1442 err = chip->info->ops->irl_init_all(chip, port); 1443 if (err) 1444 return err; 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1451 { 1452 if (chip->info->ops->set_switch_mac) { 1453 u8 addr[ETH_ALEN]; 1454 1455 eth_random_addr(addr); 1456 1457 return chip->info->ops->set_switch_mac(chip, addr); 1458 } 1459 1460 return 0; 1461 } 1462 1463 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1464 { 1465 struct dsa_switch_tree *dst = chip->ds->dst; 1466 struct dsa_switch *ds; 1467 struct dsa_port *dp; 1468 u16 pvlan = 0; 1469 1470 if (!mv88e6xxx_has_pvt(chip)) 1471 return 0; 1472 1473 /* Skip the local source device, which uses in-chip port VLAN */ 1474 if (dev != chip->ds->index) { 1475 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1476 1477 ds = dsa_switch_find(dst->index, dev); 1478 dp = ds ? dsa_to_port(ds, port) : NULL; 1479 if (dp && dp->lag_dev) { 1480 /* As the PVT is used to limit flooding of 1481 * FORWARD frames, which use the LAG ID as the 1482 * source port, we must translate dev/port to 1483 * the special "LAG device" in the PVT, using 1484 * the LAG ID as the port number. 1485 */ 1486 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1487 port = dsa_lag_id(dst, dp->lag_dev); 1488 } 1489 } 1490 1491 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1492 } 1493 1494 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1495 { 1496 int dev, port; 1497 int err; 1498 1499 if (!mv88e6xxx_has_pvt(chip)) 1500 return 0; 1501 1502 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1503 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1504 */ 1505 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1506 if (err) 1507 return err; 1508 1509 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1510 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1511 err = mv88e6xxx_pvt_map(chip, dev, port); 1512 if (err) 1513 return err; 1514 } 1515 } 1516 1517 return 0; 1518 } 1519 1520 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1521 { 1522 struct mv88e6xxx_chip *chip = ds->priv; 1523 int err; 1524 1525 if (dsa_to_port(ds, port)->lag_dev) 1526 /* Hardware is incapable of fast-aging a LAG through a 1527 * regular ATU move operation. Until we have something 1528 * more fancy in place this is a no-op. 1529 */ 1530 return; 1531 1532 mv88e6xxx_reg_lock(chip); 1533 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1534 mv88e6xxx_reg_unlock(chip); 1535 1536 if (err) 1537 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1538 } 1539 1540 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1541 { 1542 if (!mv88e6xxx_max_vid(chip)) 1543 return 0; 1544 1545 return mv88e6xxx_g1_vtu_flush(chip); 1546 } 1547 1548 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1549 struct mv88e6xxx_vtu_entry *entry) 1550 { 1551 int err; 1552 1553 if (!chip->info->ops->vtu_getnext) 1554 return -EOPNOTSUPP; 1555 1556 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1557 entry->valid = false; 1558 1559 err = chip->info->ops->vtu_getnext(chip, entry); 1560 1561 if (entry->vid != vid) 1562 entry->valid = false; 1563 1564 return err; 1565 } 1566 1567 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1568 int (*cb)(struct mv88e6xxx_chip *chip, 1569 const struct mv88e6xxx_vtu_entry *entry, 1570 void *priv), 1571 void *priv) 1572 { 1573 struct mv88e6xxx_vtu_entry entry = { 1574 .vid = mv88e6xxx_max_vid(chip), 1575 .valid = false, 1576 }; 1577 int err; 1578 1579 if (!chip->info->ops->vtu_getnext) 1580 return -EOPNOTSUPP; 1581 1582 do { 1583 err = chip->info->ops->vtu_getnext(chip, &entry); 1584 if (err) 1585 return err; 1586 1587 if (!entry.valid) 1588 break; 1589 1590 err = cb(chip, &entry, priv); 1591 if (err) 1592 return err; 1593 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1594 1595 return 0; 1596 } 1597 1598 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1599 struct mv88e6xxx_vtu_entry *entry) 1600 { 1601 if (!chip->info->ops->vtu_loadpurge) 1602 return -EOPNOTSUPP; 1603 1604 return chip->info->ops->vtu_loadpurge(chip, entry); 1605 } 1606 1607 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1608 const struct mv88e6xxx_vtu_entry *entry, 1609 void *_fid_bitmap) 1610 { 1611 unsigned long *fid_bitmap = _fid_bitmap; 1612 1613 set_bit(entry->fid, fid_bitmap); 1614 return 0; 1615 } 1616 1617 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1618 { 1619 int i, err; 1620 u16 fid; 1621 1622 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1623 1624 /* Set every FID bit used by the (un)bridged ports */ 1625 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1626 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1627 if (err) 1628 return err; 1629 1630 set_bit(fid, fid_bitmap); 1631 } 1632 1633 /* Set every FID bit used by the VLAN entries */ 1634 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1635 } 1636 1637 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1638 { 1639 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1640 int err; 1641 1642 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1643 if (err) 1644 return err; 1645 1646 /* The reset value 0x000 is used to indicate that multiple address 1647 * databases are not needed. Return the next positive available. 1648 */ 1649 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1650 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1651 return -ENOSPC; 1652 1653 /* Clear the database */ 1654 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1655 } 1656 1657 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1658 u16 vid) 1659 { 1660 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1661 struct mv88e6xxx_chip *chip = ds->priv; 1662 struct mv88e6xxx_vtu_entry vlan; 1663 int err; 1664 1665 /* DSA and CPU ports have to be members of multiple vlans */ 1666 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1667 return 0; 1668 1669 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1670 if (err) 1671 return err; 1672 1673 if (!vlan.valid) 1674 return 0; 1675 1676 dsa_switch_for_each_user_port(other_dp, ds) { 1677 struct net_device *other_br; 1678 1679 if (vlan.member[other_dp->index] == 1680 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1681 continue; 1682 1683 if (dsa_port_bridge_same(dp, other_dp)) 1684 break; /* same bridge, check next VLAN */ 1685 1686 other_br = dsa_port_bridge_dev_get(other_dp); 1687 if (!other_br) 1688 continue; 1689 1690 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1691 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1692 return -EOPNOTSUPP; 1693 } 1694 1695 return 0; 1696 } 1697 1698 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1699 { 1700 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1701 struct net_device *br = dsa_port_bridge_dev_get(dp); 1702 struct mv88e6xxx_port *p = &chip->ports[port]; 1703 u16 pvid = MV88E6XXX_VID_STANDALONE; 1704 bool drop_untagged = false; 1705 int err; 1706 1707 if (br) { 1708 if (br_vlan_enabled(br)) { 1709 pvid = p->bridge_pvid.vid; 1710 drop_untagged = !p->bridge_pvid.valid; 1711 } else { 1712 pvid = MV88E6XXX_VID_BRIDGED; 1713 } 1714 } 1715 1716 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1717 if (err) 1718 return err; 1719 1720 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1721 } 1722 1723 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1724 bool vlan_filtering, 1725 struct netlink_ext_ack *extack) 1726 { 1727 struct mv88e6xxx_chip *chip = ds->priv; 1728 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1729 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1730 int err; 1731 1732 if (!mv88e6xxx_max_vid(chip)) 1733 return -EOPNOTSUPP; 1734 1735 mv88e6xxx_reg_lock(chip); 1736 1737 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1738 if (err) 1739 goto unlock; 1740 1741 err = mv88e6xxx_port_commit_pvid(chip, port); 1742 if (err) 1743 goto unlock; 1744 1745 unlock: 1746 mv88e6xxx_reg_unlock(chip); 1747 1748 return err; 1749 } 1750 1751 static int 1752 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1753 const struct switchdev_obj_port_vlan *vlan) 1754 { 1755 struct mv88e6xxx_chip *chip = ds->priv; 1756 int err; 1757 1758 if (!mv88e6xxx_max_vid(chip)) 1759 return -EOPNOTSUPP; 1760 1761 /* If the requested port doesn't belong to the same bridge as the VLAN 1762 * members, do not support it (yet) and fallback to software VLAN. 1763 */ 1764 mv88e6xxx_reg_lock(chip); 1765 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1766 mv88e6xxx_reg_unlock(chip); 1767 1768 return err; 1769 } 1770 1771 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1772 const unsigned char *addr, u16 vid, 1773 u8 state) 1774 { 1775 struct mv88e6xxx_atu_entry entry; 1776 struct mv88e6xxx_vtu_entry vlan; 1777 u16 fid; 1778 int err; 1779 1780 /* Ports have two private address databases: one for when the port is 1781 * standalone and one for when the port is under a bridge and the 1782 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1783 * address database to remain 100% empty, so we never load an ATU entry 1784 * into a standalone port's database. Therefore, translate the null 1785 * VLAN ID into the port's database used for VLAN-unaware bridging. 1786 */ 1787 if (vid == 0) { 1788 fid = MV88E6XXX_FID_BRIDGED; 1789 } else { 1790 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1791 if (err) 1792 return err; 1793 1794 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1795 if (!vlan.valid) 1796 return -EOPNOTSUPP; 1797 1798 fid = vlan.fid; 1799 } 1800 1801 entry.state = 0; 1802 ether_addr_copy(entry.mac, addr); 1803 eth_addr_dec(entry.mac); 1804 1805 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1806 if (err) 1807 return err; 1808 1809 /* Initialize a fresh ATU entry if it isn't found */ 1810 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1811 memset(&entry, 0, sizeof(entry)); 1812 ether_addr_copy(entry.mac, addr); 1813 } 1814 1815 /* Purge the ATU entry only if no port is using it anymore */ 1816 if (!state) { 1817 entry.portvec &= ~BIT(port); 1818 if (!entry.portvec) 1819 entry.state = 0; 1820 } else { 1821 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1822 entry.portvec = BIT(port); 1823 else 1824 entry.portvec |= BIT(port); 1825 1826 entry.state = state; 1827 } 1828 1829 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1830 } 1831 1832 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1833 const struct mv88e6xxx_policy *policy) 1834 { 1835 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1836 enum mv88e6xxx_policy_action action = policy->action; 1837 const u8 *addr = policy->addr; 1838 u16 vid = policy->vid; 1839 u8 state; 1840 int err; 1841 int id; 1842 1843 if (!chip->info->ops->port_set_policy) 1844 return -EOPNOTSUPP; 1845 1846 switch (mapping) { 1847 case MV88E6XXX_POLICY_MAPPING_DA: 1848 case MV88E6XXX_POLICY_MAPPING_SA: 1849 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1850 state = 0; /* Dissociate the port and address */ 1851 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1852 is_multicast_ether_addr(addr)) 1853 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1854 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1855 is_unicast_ether_addr(addr)) 1856 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1857 else 1858 return -EOPNOTSUPP; 1859 1860 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1861 state); 1862 if (err) 1863 return err; 1864 break; 1865 default: 1866 return -EOPNOTSUPP; 1867 } 1868 1869 /* Skip the port's policy clearing if the mapping is still in use */ 1870 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1871 idr_for_each_entry(&chip->policies, policy, id) 1872 if (policy->port == port && 1873 policy->mapping == mapping && 1874 policy->action != action) 1875 return 0; 1876 1877 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1878 } 1879 1880 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1881 struct ethtool_rx_flow_spec *fs) 1882 { 1883 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1884 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1885 enum mv88e6xxx_policy_mapping mapping; 1886 enum mv88e6xxx_policy_action action; 1887 struct mv88e6xxx_policy *policy; 1888 u16 vid = 0; 1889 u8 *addr; 1890 int err; 1891 int id; 1892 1893 if (fs->location != RX_CLS_LOC_ANY) 1894 return -EINVAL; 1895 1896 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1897 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1898 else 1899 return -EOPNOTSUPP; 1900 1901 switch (fs->flow_type & ~FLOW_EXT) { 1902 case ETHER_FLOW: 1903 if (!is_zero_ether_addr(mac_mask->h_dest) && 1904 is_zero_ether_addr(mac_mask->h_source)) { 1905 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1906 addr = mac_entry->h_dest; 1907 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1908 !is_zero_ether_addr(mac_mask->h_source)) { 1909 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1910 addr = mac_entry->h_source; 1911 } else { 1912 /* Cannot support DA and SA mapping in the same rule */ 1913 return -EOPNOTSUPP; 1914 } 1915 break; 1916 default: 1917 return -EOPNOTSUPP; 1918 } 1919 1920 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1921 if (fs->m_ext.vlan_tci != htons(0xffff)) 1922 return -EOPNOTSUPP; 1923 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1924 } 1925 1926 idr_for_each_entry(&chip->policies, policy, id) { 1927 if (policy->port == port && policy->mapping == mapping && 1928 policy->action == action && policy->vid == vid && 1929 ether_addr_equal(policy->addr, addr)) 1930 return -EEXIST; 1931 } 1932 1933 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1934 if (!policy) 1935 return -ENOMEM; 1936 1937 fs->location = 0; 1938 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1939 GFP_KERNEL); 1940 if (err) { 1941 devm_kfree(chip->dev, policy); 1942 return err; 1943 } 1944 1945 memcpy(&policy->fs, fs, sizeof(*fs)); 1946 ether_addr_copy(policy->addr, addr); 1947 policy->mapping = mapping; 1948 policy->action = action; 1949 policy->port = port; 1950 policy->vid = vid; 1951 1952 err = mv88e6xxx_policy_apply(chip, port, policy); 1953 if (err) { 1954 idr_remove(&chip->policies, fs->location); 1955 devm_kfree(chip->dev, policy); 1956 return err; 1957 } 1958 1959 return 0; 1960 } 1961 1962 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1963 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1964 { 1965 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1966 struct mv88e6xxx_chip *chip = ds->priv; 1967 struct mv88e6xxx_policy *policy; 1968 int err; 1969 int id; 1970 1971 mv88e6xxx_reg_lock(chip); 1972 1973 switch (rxnfc->cmd) { 1974 case ETHTOOL_GRXCLSRLCNT: 1975 rxnfc->data = 0; 1976 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1977 rxnfc->rule_cnt = 0; 1978 idr_for_each_entry(&chip->policies, policy, id) 1979 if (policy->port == port) 1980 rxnfc->rule_cnt++; 1981 err = 0; 1982 break; 1983 case ETHTOOL_GRXCLSRULE: 1984 err = -ENOENT; 1985 policy = idr_find(&chip->policies, fs->location); 1986 if (policy) { 1987 memcpy(fs, &policy->fs, sizeof(*fs)); 1988 err = 0; 1989 } 1990 break; 1991 case ETHTOOL_GRXCLSRLALL: 1992 rxnfc->data = 0; 1993 rxnfc->rule_cnt = 0; 1994 idr_for_each_entry(&chip->policies, policy, id) 1995 if (policy->port == port) 1996 rule_locs[rxnfc->rule_cnt++] = id; 1997 err = 0; 1998 break; 1999 default: 2000 err = -EOPNOTSUPP; 2001 break; 2002 } 2003 2004 mv88e6xxx_reg_unlock(chip); 2005 2006 return err; 2007 } 2008 2009 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2010 struct ethtool_rxnfc *rxnfc) 2011 { 2012 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2013 struct mv88e6xxx_chip *chip = ds->priv; 2014 struct mv88e6xxx_policy *policy; 2015 int err; 2016 2017 mv88e6xxx_reg_lock(chip); 2018 2019 switch (rxnfc->cmd) { 2020 case ETHTOOL_SRXCLSRLINS: 2021 err = mv88e6xxx_policy_insert(chip, port, fs); 2022 break; 2023 case ETHTOOL_SRXCLSRLDEL: 2024 err = -ENOENT; 2025 policy = idr_remove(&chip->policies, fs->location); 2026 if (policy) { 2027 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2028 err = mv88e6xxx_policy_apply(chip, port, policy); 2029 devm_kfree(chip->dev, policy); 2030 } 2031 break; 2032 default: 2033 err = -EOPNOTSUPP; 2034 break; 2035 } 2036 2037 mv88e6xxx_reg_unlock(chip); 2038 2039 return err; 2040 } 2041 2042 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2043 u16 vid) 2044 { 2045 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2046 u8 broadcast[ETH_ALEN]; 2047 2048 eth_broadcast_addr(broadcast); 2049 2050 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2051 } 2052 2053 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2054 { 2055 int port; 2056 int err; 2057 2058 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2059 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2060 struct net_device *brport; 2061 2062 if (dsa_is_unused_port(chip->ds, port)) 2063 continue; 2064 2065 brport = dsa_port_to_bridge_port(dp); 2066 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2067 /* Skip bridged user ports where broadcast 2068 * flooding is disabled. 2069 */ 2070 continue; 2071 2072 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2073 if (err) 2074 return err; 2075 } 2076 2077 return 0; 2078 } 2079 2080 struct mv88e6xxx_port_broadcast_sync_ctx { 2081 int port; 2082 bool flood; 2083 }; 2084 2085 static int 2086 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2087 const struct mv88e6xxx_vtu_entry *vlan, 2088 void *_ctx) 2089 { 2090 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2091 u8 broadcast[ETH_ALEN]; 2092 u8 state; 2093 2094 if (ctx->flood) 2095 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2096 else 2097 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2098 2099 eth_broadcast_addr(broadcast); 2100 2101 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2102 vlan->vid, state); 2103 } 2104 2105 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2106 bool flood) 2107 { 2108 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2109 .port = port, 2110 .flood = flood, 2111 }; 2112 struct mv88e6xxx_vtu_entry vid0 = { 2113 .vid = 0, 2114 }; 2115 int err; 2116 2117 /* Update the port's private database... */ 2118 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2119 if (err) 2120 return err; 2121 2122 /* ...and the database for all VLANs. */ 2123 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2124 &ctx); 2125 } 2126 2127 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2128 u16 vid, u8 member, bool warn) 2129 { 2130 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2131 struct mv88e6xxx_vtu_entry vlan; 2132 int i, err; 2133 2134 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2135 if (err) 2136 return err; 2137 2138 if (!vlan.valid) { 2139 memset(&vlan, 0, sizeof(vlan)); 2140 2141 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2142 if (err) 2143 return err; 2144 2145 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2146 if (i == port) 2147 vlan.member[i] = member; 2148 else 2149 vlan.member[i] = non_member; 2150 2151 vlan.vid = vid; 2152 vlan.valid = true; 2153 2154 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2155 if (err) 2156 return err; 2157 2158 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2159 if (err) 2160 return err; 2161 } else if (vlan.member[port] != member) { 2162 vlan.member[port] = member; 2163 2164 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2165 if (err) 2166 return err; 2167 } else if (warn) { 2168 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2169 port, vid); 2170 } 2171 2172 return 0; 2173 } 2174 2175 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2176 const struct switchdev_obj_port_vlan *vlan, 2177 struct netlink_ext_ack *extack) 2178 { 2179 struct mv88e6xxx_chip *chip = ds->priv; 2180 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2181 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2182 struct mv88e6xxx_port *p = &chip->ports[port]; 2183 bool warn; 2184 u8 member; 2185 int err; 2186 2187 if (!vlan->vid) 2188 return 0; 2189 2190 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2191 if (err) 2192 return err; 2193 2194 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2195 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2196 else if (untagged) 2197 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2198 else 2199 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2200 2201 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2202 * and then the CPU port. Do not warn for duplicates for the CPU port. 2203 */ 2204 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2205 2206 mv88e6xxx_reg_lock(chip); 2207 2208 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2209 if (err) { 2210 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2211 vlan->vid, untagged ? 'u' : 't'); 2212 goto out; 2213 } 2214 2215 if (pvid) { 2216 p->bridge_pvid.vid = vlan->vid; 2217 p->bridge_pvid.valid = true; 2218 2219 err = mv88e6xxx_port_commit_pvid(chip, port); 2220 if (err) 2221 goto out; 2222 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2223 /* The old pvid was reinstalled as a non-pvid VLAN */ 2224 p->bridge_pvid.valid = false; 2225 2226 err = mv88e6xxx_port_commit_pvid(chip, port); 2227 if (err) 2228 goto out; 2229 } 2230 2231 out: 2232 mv88e6xxx_reg_unlock(chip); 2233 2234 return err; 2235 } 2236 2237 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2238 int port, u16 vid) 2239 { 2240 struct mv88e6xxx_vtu_entry vlan; 2241 int i, err; 2242 2243 if (!vid) 2244 return 0; 2245 2246 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2247 if (err) 2248 return err; 2249 2250 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2251 * tell switchdev that this VLAN is likely handled in software. 2252 */ 2253 if (!vlan.valid || 2254 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2255 return -EOPNOTSUPP; 2256 2257 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2258 2259 /* keep the VLAN unless all ports are excluded */ 2260 vlan.valid = false; 2261 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2262 if (vlan.member[i] != 2263 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2264 vlan.valid = true; 2265 break; 2266 } 2267 } 2268 2269 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2270 if (err) 2271 return err; 2272 2273 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2274 } 2275 2276 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2277 const struct switchdev_obj_port_vlan *vlan) 2278 { 2279 struct mv88e6xxx_chip *chip = ds->priv; 2280 struct mv88e6xxx_port *p = &chip->ports[port]; 2281 int err = 0; 2282 u16 pvid; 2283 2284 if (!mv88e6xxx_max_vid(chip)) 2285 return -EOPNOTSUPP; 2286 2287 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2288 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2289 * switchdev workqueue to ensure that all FDB entries are deleted 2290 * before we remove the VLAN. 2291 */ 2292 dsa_flush_workqueue(); 2293 2294 mv88e6xxx_reg_lock(chip); 2295 2296 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2297 if (err) 2298 goto unlock; 2299 2300 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2301 if (err) 2302 goto unlock; 2303 2304 if (vlan->vid == pvid) { 2305 p->bridge_pvid.valid = false; 2306 2307 err = mv88e6xxx_port_commit_pvid(chip, port); 2308 if (err) 2309 goto unlock; 2310 } 2311 2312 unlock: 2313 mv88e6xxx_reg_unlock(chip); 2314 2315 return err; 2316 } 2317 2318 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2319 const unsigned char *addr, u16 vid) 2320 { 2321 struct mv88e6xxx_chip *chip = ds->priv; 2322 int err; 2323 2324 mv88e6xxx_reg_lock(chip); 2325 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2326 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2327 mv88e6xxx_reg_unlock(chip); 2328 2329 return err; 2330 } 2331 2332 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2333 const unsigned char *addr, u16 vid) 2334 { 2335 struct mv88e6xxx_chip *chip = ds->priv; 2336 int err; 2337 2338 mv88e6xxx_reg_lock(chip); 2339 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2340 mv88e6xxx_reg_unlock(chip); 2341 2342 return err; 2343 } 2344 2345 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2346 u16 fid, u16 vid, int port, 2347 dsa_fdb_dump_cb_t *cb, void *data) 2348 { 2349 struct mv88e6xxx_atu_entry addr; 2350 bool is_static; 2351 int err; 2352 2353 addr.state = 0; 2354 eth_broadcast_addr(addr.mac); 2355 2356 do { 2357 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2358 if (err) 2359 return err; 2360 2361 if (!addr.state) 2362 break; 2363 2364 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2365 continue; 2366 2367 if (!is_unicast_ether_addr(addr.mac)) 2368 continue; 2369 2370 is_static = (addr.state == 2371 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2372 err = cb(addr.mac, vid, is_static, data); 2373 if (err) 2374 return err; 2375 } while (!is_broadcast_ether_addr(addr.mac)); 2376 2377 return err; 2378 } 2379 2380 struct mv88e6xxx_port_db_dump_vlan_ctx { 2381 int port; 2382 dsa_fdb_dump_cb_t *cb; 2383 void *data; 2384 }; 2385 2386 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2387 const struct mv88e6xxx_vtu_entry *entry, 2388 void *_data) 2389 { 2390 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2391 2392 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2393 ctx->port, ctx->cb, ctx->data); 2394 } 2395 2396 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2397 dsa_fdb_dump_cb_t *cb, void *data) 2398 { 2399 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2400 .port = port, 2401 .cb = cb, 2402 .data = data, 2403 }; 2404 u16 fid; 2405 int err; 2406 2407 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2408 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2409 if (err) 2410 return err; 2411 2412 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2413 if (err) 2414 return err; 2415 2416 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2417 } 2418 2419 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2420 dsa_fdb_dump_cb_t *cb, void *data) 2421 { 2422 struct mv88e6xxx_chip *chip = ds->priv; 2423 int err; 2424 2425 mv88e6xxx_reg_lock(chip); 2426 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2427 mv88e6xxx_reg_unlock(chip); 2428 2429 return err; 2430 } 2431 2432 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2433 struct dsa_bridge bridge) 2434 { 2435 struct dsa_switch *ds = chip->ds; 2436 struct dsa_switch_tree *dst = ds->dst; 2437 struct dsa_port *dp; 2438 int err; 2439 2440 list_for_each_entry(dp, &dst->ports, list) { 2441 if (dsa_port_offloads_bridge(dp, &bridge)) { 2442 if (dp->ds == ds) { 2443 /* This is a local bridge group member, 2444 * remap its Port VLAN Map. 2445 */ 2446 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2447 if (err) 2448 return err; 2449 } else { 2450 /* This is an external bridge group member, 2451 * remap its cross-chip Port VLAN Table entry. 2452 */ 2453 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2454 dp->index); 2455 if (err) 2456 return err; 2457 } 2458 } 2459 } 2460 2461 return 0; 2462 } 2463 2464 /* Treat the software bridge as a virtual single-port switch behind the 2465 * CPU and map in the PVT. First dst->last_switch elements are taken by 2466 * physical switches, so start from beyond that range. 2467 */ 2468 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2469 unsigned int bridge_num) 2470 { 2471 u8 dev = bridge_num + ds->dst->last_switch; 2472 struct mv88e6xxx_chip *chip = ds->priv; 2473 2474 return mv88e6xxx_pvt_map(chip, dev, 0); 2475 } 2476 2477 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2478 struct dsa_bridge bridge, 2479 bool *tx_fwd_offload) 2480 { 2481 struct mv88e6xxx_chip *chip = ds->priv; 2482 int err; 2483 2484 mv88e6xxx_reg_lock(chip); 2485 2486 err = mv88e6xxx_bridge_map(chip, bridge); 2487 if (err) 2488 goto unlock; 2489 2490 err = mv88e6xxx_port_commit_pvid(chip, port); 2491 if (err) 2492 goto unlock; 2493 2494 if (mv88e6xxx_has_pvt(chip)) { 2495 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2496 if (err) 2497 goto unlock; 2498 2499 *tx_fwd_offload = true; 2500 } 2501 2502 unlock: 2503 mv88e6xxx_reg_unlock(chip); 2504 2505 return err; 2506 } 2507 2508 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2509 struct dsa_bridge bridge) 2510 { 2511 struct mv88e6xxx_chip *chip = ds->priv; 2512 int err; 2513 2514 mv88e6xxx_reg_lock(chip); 2515 2516 if (bridge.tx_fwd_offload && 2517 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2518 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2519 2520 if (mv88e6xxx_bridge_map(chip, bridge) || 2521 mv88e6xxx_port_vlan_map(chip, port)) 2522 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2523 2524 err = mv88e6xxx_port_commit_pvid(chip, port); 2525 if (err) 2526 dev_err(ds->dev, 2527 "port %d failed to restore standalone pvid: %pe\n", 2528 port, ERR_PTR(err)); 2529 2530 mv88e6xxx_reg_unlock(chip); 2531 } 2532 2533 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2534 int tree_index, int sw_index, 2535 int port, struct dsa_bridge bridge) 2536 { 2537 struct mv88e6xxx_chip *chip = ds->priv; 2538 int err; 2539 2540 if (tree_index != ds->dst->index) 2541 return 0; 2542 2543 mv88e6xxx_reg_lock(chip); 2544 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2545 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2546 mv88e6xxx_reg_unlock(chip); 2547 2548 return err; 2549 } 2550 2551 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2552 int tree_index, int sw_index, 2553 int port, struct dsa_bridge bridge) 2554 { 2555 struct mv88e6xxx_chip *chip = ds->priv; 2556 2557 if (tree_index != ds->dst->index) 2558 return; 2559 2560 mv88e6xxx_reg_lock(chip); 2561 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2562 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2563 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2564 mv88e6xxx_reg_unlock(chip); 2565 } 2566 2567 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2568 { 2569 if (chip->info->ops->reset) 2570 return chip->info->ops->reset(chip); 2571 2572 return 0; 2573 } 2574 2575 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2576 { 2577 struct gpio_desc *gpiod = chip->reset; 2578 2579 /* If there is a GPIO connected to the reset pin, toggle it */ 2580 if (gpiod) { 2581 gpiod_set_value_cansleep(gpiod, 1); 2582 usleep_range(10000, 20000); 2583 gpiod_set_value_cansleep(gpiod, 0); 2584 usleep_range(10000, 20000); 2585 2586 mv88e6xxx_g1_wait_eeprom_done(chip); 2587 } 2588 } 2589 2590 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2591 { 2592 int i, err; 2593 2594 /* Set all ports to the Disabled state */ 2595 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2596 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2597 if (err) 2598 return err; 2599 } 2600 2601 /* Wait for transmit queues to drain, 2602 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2603 */ 2604 usleep_range(2000, 4000); 2605 2606 return 0; 2607 } 2608 2609 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2610 { 2611 int err; 2612 2613 err = mv88e6xxx_disable_ports(chip); 2614 if (err) 2615 return err; 2616 2617 mv88e6xxx_hardware_reset(chip); 2618 2619 return mv88e6xxx_software_reset(chip); 2620 } 2621 2622 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2623 enum mv88e6xxx_frame_mode frame, 2624 enum mv88e6xxx_egress_mode egress, u16 etype) 2625 { 2626 int err; 2627 2628 if (!chip->info->ops->port_set_frame_mode) 2629 return -EOPNOTSUPP; 2630 2631 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2632 if (err) 2633 return err; 2634 2635 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2636 if (err) 2637 return err; 2638 2639 if (chip->info->ops->port_set_ether_type) 2640 return chip->info->ops->port_set_ether_type(chip, port, etype); 2641 2642 return 0; 2643 } 2644 2645 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2646 { 2647 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2648 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2649 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2650 } 2651 2652 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2653 { 2654 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2655 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2656 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2657 } 2658 2659 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2660 { 2661 return mv88e6xxx_set_port_mode(chip, port, 2662 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2663 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2664 ETH_P_EDSA); 2665 } 2666 2667 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2668 { 2669 if (dsa_is_dsa_port(chip->ds, port)) 2670 return mv88e6xxx_set_port_mode_dsa(chip, port); 2671 2672 if (dsa_is_user_port(chip->ds, port)) 2673 return mv88e6xxx_set_port_mode_normal(chip, port); 2674 2675 /* Setup CPU port mode depending on its supported tag format */ 2676 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2677 return mv88e6xxx_set_port_mode_dsa(chip, port); 2678 2679 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2680 return mv88e6xxx_set_port_mode_edsa(chip, port); 2681 2682 return -EINVAL; 2683 } 2684 2685 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2686 { 2687 bool message = dsa_is_dsa_port(chip->ds, port); 2688 2689 return mv88e6xxx_port_set_message_port(chip, port, message); 2690 } 2691 2692 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2693 { 2694 int err; 2695 2696 if (chip->info->ops->port_set_ucast_flood) { 2697 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2698 if (err) 2699 return err; 2700 } 2701 if (chip->info->ops->port_set_mcast_flood) { 2702 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2703 if (err) 2704 return err; 2705 } 2706 2707 return 0; 2708 } 2709 2710 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2711 { 2712 struct mv88e6xxx_port *mvp = dev_id; 2713 struct mv88e6xxx_chip *chip = mvp->chip; 2714 irqreturn_t ret = IRQ_NONE; 2715 int port = mvp->port; 2716 int lane; 2717 2718 mv88e6xxx_reg_lock(chip); 2719 lane = mv88e6xxx_serdes_get_lane(chip, port); 2720 if (lane >= 0) 2721 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2722 mv88e6xxx_reg_unlock(chip); 2723 2724 return ret; 2725 } 2726 2727 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2728 int lane) 2729 { 2730 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2731 unsigned int irq; 2732 int err; 2733 2734 /* Nothing to request if this SERDES port has no IRQ */ 2735 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2736 if (!irq) 2737 return 0; 2738 2739 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2740 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2741 2742 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2743 mv88e6xxx_reg_unlock(chip); 2744 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2745 IRQF_ONESHOT, dev_id->serdes_irq_name, 2746 dev_id); 2747 mv88e6xxx_reg_lock(chip); 2748 if (err) 2749 return err; 2750 2751 dev_id->serdes_irq = irq; 2752 2753 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2754 } 2755 2756 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2757 int lane) 2758 { 2759 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2760 unsigned int irq = dev_id->serdes_irq; 2761 int err; 2762 2763 /* Nothing to free if no IRQ has been requested */ 2764 if (!irq) 2765 return 0; 2766 2767 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2768 2769 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2770 mv88e6xxx_reg_unlock(chip); 2771 free_irq(irq, dev_id); 2772 mv88e6xxx_reg_lock(chip); 2773 2774 dev_id->serdes_irq = 0; 2775 2776 return err; 2777 } 2778 2779 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2780 bool on) 2781 { 2782 int lane; 2783 int err; 2784 2785 lane = mv88e6xxx_serdes_get_lane(chip, port); 2786 if (lane < 0) 2787 return 0; 2788 2789 if (on) { 2790 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2791 if (err) 2792 return err; 2793 2794 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2795 } else { 2796 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2797 if (err) 2798 return err; 2799 2800 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2801 } 2802 2803 return err; 2804 } 2805 2806 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2807 enum mv88e6xxx_egress_direction direction, 2808 int port) 2809 { 2810 int err; 2811 2812 if (!chip->info->ops->set_egress_port) 2813 return -EOPNOTSUPP; 2814 2815 err = chip->info->ops->set_egress_port(chip, direction, port); 2816 if (err) 2817 return err; 2818 2819 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2820 chip->ingress_dest_port = port; 2821 else 2822 chip->egress_dest_port = port; 2823 2824 return 0; 2825 } 2826 2827 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2828 { 2829 struct dsa_switch *ds = chip->ds; 2830 int upstream_port; 2831 int err; 2832 2833 upstream_port = dsa_upstream_port(ds, port); 2834 if (chip->info->ops->port_set_upstream_port) { 2835 err = chip->info->ops->port_set_upstream_port(chip, port, 2836 upstream_port); 2837 if (err) 2838 return err; 2839 } 2840 2841 if (port == upstream_port) { 2842 if (chip->info->ops->set_cpu_port) { 2843 err = chip->info->ops->set_cpu_port(chip, 2844 upstream_port); 2845 if (err) 2846 return err; 2847 } 2848 2849 err = mv88e6xxx_set_egress_port(chip, 2850 MV88E6XXX_EGRESS_DIR_INGRESS, 2851 upstream_port); 2852 if (err && err != -EOPNOTSUPP) 2853 return err; 2854 2855 err = mv88e6xxx_set_egress_port(chip, 2856 MV88E6XXX_EGRESS_DIR_EGRESS, 2857 upstream_port); 2858 if (err && err != -EOPNOTSUPP) 2859 return err; 2860 } 2861 2862 return 0; 2863 } 2864 2865 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2866 { 2867 struct dsa_switch *ds = chip->ds; 2868 int err; 2869 u16 reg; 2870 2871 chip->ports[port].chip = chip; 2872 chip->ports[port].port = port; 2873 2874 /* MAC Forcing register: don't force link, speed, duplex or flow control 2875 * state to any particular values on physical ports, but force the CPU 2876 * port and all DSA ports to their maximum bandwidth and full duplex. 2877 */ 2878 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2879 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2880 SPEED_MAX, DUPLEX_FULL, 2881 PAUSE_OFF, 2882 PHY_INTERFACE_MODE_NA); 2883 else 2884 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2885 SPEED_UNFORCED, DUPLEX_UNFORCED, 2886 PAUSE_ON, 2887 PHY_INTERFACE_MODE_NA); 2888 if (err) 2889 return err; 2890 2891 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2892 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2893 * tunneling, determine priority by looking at 802.1p and IP 2894 * priority fields (IP prio has precedence), and set STP state 2895 * to Forwarding. 2896 * 2897 * If this is the CPU link, use DSA or EDSA tagging depending 2898 * on which tagging mode was configured. 2899 * 2900 * If this is a link to another switch, use DSA tagging mode. 2901 * 2902 * If this is the upstream port for this switch, enable 2903 * forwarding of unknown unicasts and multicasts. 2904 */ 2905 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2906 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2907 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2908 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2909 if (err) 2910 return err; 2911 2912 err = mv88e6xxx_setup_port_mode(chip, port); 2913 if (err) 2914 return err; 2915 2916 err = mv88e6xxx_setup_egress_floods(chip, port); 2917 if (err) 2918 return err; 2919 2920 /* Port Control 2: don't force a good FCS, set the MTU size to 2921 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2922 * untagged frames on this port, do a destination address lookup on all 2923 * received packets as usual, disable ARP mirroring and don't send a 2924 * copy of all transmitted/received frames on this port to the CPU. 2925 */ 2926 err = mv88e6xxx_port_set_map_da(chip, port); 2927 if (err) 2928 return err; 2929 2930 err = mv88e6xxx_setup_upstream_port(chip, port); 2931 if (err) 2932 return err; 2933 2934 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2935 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2936 if (err) 2937 return err; 2938 2939 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2940 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2941 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2942 * as the private PVID on ports under a VLAN-unaware bridge. 2943 * Shared (DSA and CPU) ports must also be members of it, to translate 2944 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2945 * relying on their port default FID. 2946 */ 2947 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2948 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2949 false); 2950 if (err) 2951 return err; 2952 2953 if (chip->info->ops->port_set_jumbo_size) { 2954 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2955 if (err) 2956 return err; 2957 } 2958 2959 /* Port Association Vector: disable automatic address learning 2960 * on all user ports since they start out in standalone 2961 * mode. When joining a bridge, learning will be configured to 2962 * match the bridge port settings. Enable learning on all 2963 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2964 * learning process. 2965 * 2966 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2967 * and RefreshLocked. I.e. setup standard automatic learning. 2968 */ 2969 if (dsa_is_user_port(ds, port)) 2970 reg = 0; 2971 else 2972 reg = 1 << port; 2973 2974 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2975 reg); 2976 if (err) 2977 return err; 2978 2979 /* Egress rate control 2: disable egress rate control. */ 2980 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2981 0x0000); 2982 if (err) 2983 return err; 2984 2985 if (chip->info->ops->port_pause_limit) { 2986 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2987 if (err) 2988 return err; 2989 } 2990 2991 if (chip->info->ops->port_disable_learn_limit) { 2992 err = chip->info->ops->port_disable_learn_limit(chip, port); 2993 if (err) 2994 return err; 2995 } 2996 2997 if (chip->info->ops->port_disable_pri_override) { 2998 err = chip->info->ops->port_disable_pri_override(chip, port); 2999 if (err) 3000 return err; 3001 } 3002 3003 if (chip->info->ops->port_tag_remap) { 3004 err = chip->info->ops->port_tag_remap(chip, port); 3005 if (err) 3006 return err; 3007 } 3008 3009 if (chip->info->ops->port_egress_rate_limiting) { 3010 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3011 if (err) 3012 return err; 3013 } 3014 3015 if (chip->info->ops->port_setup_message_port) { 3016 err = chip->info->ops->port_setup_message_port(chip, port); 3017 if (err) 3018 return err; 3019 } 3020 3021 /* Port based VLAN map: give each port the same default address 3022 * database, and allow bidirectional communication between the 3023 * CPU and DSA port(s), and the other ports. 3024 */ 3025 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3026 if (err) 3027 return err; 3028 3029 err = mv88e6xxx_port_vlan_map(chip, port); 3030 if (err) 3031 return err; 3032 3033 /* Default VLAN ID and priority: don't set a default VLAN 3034 * ID, and set the default packet priority to zero. 3035 */ 3036 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3037 } 3038 3039 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3040 { 3041 struct mv88e6xxx_chip *chip = ds->priv; 3042 3043 if (chip->info->ops->port_set_jumbo_size) 3044 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3045 else if (chip->info->ops->set_max_frame_size) 3046 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3047 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3048 } 3049 3050 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3051 { 3052 struct mv88e6xxx_chip *chip = ds->priv; 3053 int ret = 0; 3054 3055 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3056 new_mtu += EDSA_HLEN; 3057 3058 mv88e6xxx_reg_lock(chip); 3059 if (chip->info->ops->port_set_jumbo_size) 3060 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3061 else if (chip->info->ops->set_max_frame_size) 3062 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3063 else 3064 if (new_mtu > 1522) 3065 ret = -EINVAL; 3066 mv88e6xxx_reg_unlock(chip); 3067 3068 return ret; 3069 } 3070 3071 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3072 struct phy_device *phydev) 3073 { 3074 struct mv88e6xxx_chip *chip = ds->priv; 3075 int err; 3076 3077 mv88e6xxx_reg_lock(chip); 3078 err = mv88e6xxx_serdes_power(chip, port, true); 3079 mv88e6xxx_reg_unlock(chip); 3080 3081 return err; 3082 } 3083 3084 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3085 { 3086 struct mv88e6xxx_chip *chip = ds->priv; 3087 3088 mv88e6xxx_reg_lock(chip); 3089 if (mv88e6xxx_serdes_power(chip, port, false)) 3090 dev_err(chip->dev, "failed to power off SERDES\n"); 3091 mv88e6xxx_reg_unlock(chip); 3092 } 3093 3094 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3095 unsigned int ageing_time) 3096 { 3097 struct mv88e6xxx_chip *chip = ds->priv; 3098 int err; 3099 3100 mv88e6xxx_reg_lock(chip); 3101 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3102 mv88e6xxx_reg_unlock(chip); 3103 3104 return err; 3105 } 3106 3107 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3108 { 3109 int err; 3110 3111 /* Initialize the statistics unit */ 3112 if (chip->info->ops->stats_set_histogram) { 3113 err = chip->info->ops->stats_set_histogram(chip); 3114 if (err) 3115 return err; 3116 } 3117 3118 return mv88e6xxx_g1_stats_clear(chip); 3119 } 3120 3121 /* Check if the errata has already been applied. */ 3122 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3123 { 3124 int port; 3125 int err; 3126 u16 val; 3127 3128 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3129 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3130 if (err) { 3131 dev_err(chip->dev, 3132 "Error reading hidden register: %d\n", err); 3133 return false; 3134 } 3135 if (val != 0x01c0) 3136 return false; 3137 } 3138 3139 return true; 3140 } 3141 3142 /* The 6390 copper ports have an errata which require poking magic 3143 * values into undocumented hidden registers and then performing a 3144 * software reset. 3145 */ 3146 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3147 { 3148 int port; 3149 int err; 3150 3151 if (mv88e6390_setup_errata_applied(chip)) 3152 return 0; 3153 3154 /* Set the ports into blocking mode */ 3155 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3156 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3157 if (err) 3158 return err; 3159 } 3160 3161 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3162 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3163 if (err) 3164 return err; 3165 } 3166 3167 return mv88e6xxx_software_reset(chip); 3168 } 3169 3170 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3171 { 3172 mv88e6xxx_teardown_devlink_params(ds); 3173 dsa_devlink_resources_unregister(ds); 3174 mv88e6xxx_teardown_devlink_regions_global(ds); 3175 } 3176 3177 static int mv88e6xxx_setup(struct dsa_switch *ds) 3178 { 3179 struct mv88e6xxx_chip *chip = ds->priv; 3180 u8 cmode; 3181 int err; 3182 int i; 3183 3184 chip->ds = ds; 3185 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3186 3187 /* Since virtual bridges are mapped in the PVT, the number we support 3188 * depends on the physical switch topology. We need to let DSA figure 3189 * that out and therefore we cannot set this at dsa_register_switch() 3190 * time. 3191 */ 3192 if (mv88e6xxx_has_pvt(chip)) 3193 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3194 ds->dst->last_switch - 1; 3195 3196 mv88e6xxx_reg_lock(chip); 3197 3198 if (chip->info->ops->setup_errata) { 3199 err = chip->info->ops->setup_errata(chip); 3200 if (err) 3201 goto unlock; 3202 } 3203 3204 /* Cache the cmode of each port. */ 3205 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3206 if (chip->info->ops->port_get_cmode) { 3207 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3208 if (err) 3209 goto unlock; 3210 3211 chip->ports[i].cmode = cmode; 3212 } 3213 } 3214 3215 err = mv88e6xxx_vtu_setup(chip); 3216 if (err) 3217 goto unlock; 3218 3219 /* Setup Switch Port Registers */ 3220 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3221 if (dsa_is_unused_port(ds, i)) 3222 continue; 3223 3224 /* Prevent the use of an invalid port. */ 3225 if (mv88e6xxx_is_invalid_port(chip, i)) { 3226 dev_err(chip->dev, "port %d is invalid\n", i); 3227 err = -EINVAL; 3228 goto unlock; 3229 } 3230 3231 err = mv88e6xxx_setup_port(chip, i); 3232 if (err) 3233 goto unlock; 3234 } 3235 3236 err = mv88e6xxx_irl_setup(chip); 3237 if (err) 3238 goto unlock; 3239 3240 err = mv88e6xxx_mac_setup(chip); 3241 if (err) 3242 goto unlock; 3243 3244 err = mv88e6xxx_phy_setup(chip); 3245 if (err) 3246 goto unlock; 3247 3248 err = mv88e6xxx_pvt_setup(chip); 3249 if (err) 3250 goto unlock; 3251 3252 err = mv88e6xxx_atu_setup(chip); 3253 if (err) 3254 goto unlock; 3255 3256 err = mv88e6xxx_broadcast_setup(chip, 0); 3257 if (err) 3258 goto unlock; 3259 3260 err = mv88e6xxx_pot_setup(chip); 3261 if (err) 3262 goto unlock; 3263 3264 err = mv88e6xxx_rmu_setup(chip); 3265 if (err) 3266 goto unlock; 3267 3268 err = mv88e6xxx_rsvd2cpu_setup(chip); 3269 if (err) 3270 goto unlock; 3271 3272 err = mv88e6xxx_trunk_setup(chip); 3273 if (err) 3274 goto unlock; 3275 3276 err = mv88e6xxx_devmap_setup(chip); 3277 if (err) 3278 goto unlock; 3279 3280 err = mv88e6xxx_pri_setup(chip); 3281 if (err) 3282 goto unlock; 3283 3284 /* Setup PTP Hardware Clock and timestamping */ 3285 if (chip->info->ptp_support) { 3286 err = mv88e6xxx_ptp_setup(chip); 3287 if (err) 3288 goto unlock; 3289 3290 err = mv88e6xxx_hwtstamp_setup(chip); 3291 if (err) 3292 goto unlock; 3293 } 3294 3295 err = mv88e6xxx_stats_setup(chip); 3296 if (err) 3297 goto unlock; 3298 3299 unlock: 3300 mv88e6xxx_reg_unlock(chip); 3301 3302 if (err) 3303 return err; 3304 3305 /* Have to be called without holding the register lock, since 3306 * they take the devlink lock, and we later take the locks in 3307 * the reverse order when getting/setting parameters or 3308 * resource occupancy. 3309 */ 3310 err = mv88e6xxx_setup_devlink_resources(ds); 3311 if (err) 3312 return err; 3313 3314 err = mv88e6xxx_setup_devlink_params(ds); 3315 if (err) 3316 goto out_resources; 3317 3318 err = mv88e6xxx_setup_devlink_regions_global(ds); 3319 if (err) 3320 goto out_params; 3321 3322 return 0; 3323 3324 out_params: 3325 mv88e6xxx_teardown_devlink_params(ds); 3326 out_resources: 3327 dsa_devlink_resources_unregister(ds); 3328 3329 return err; 3330 } 3331 3332 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3333 { 3334 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3335 } 3336 3337 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3338 { 3339 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3340 } 3341 3342 /* prod_id for switch families which do not have a PHY model number */ 3343 static const u16 family_prod_id_table[] = { 3344 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3345 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3346 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3347 }; 3348 3349 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3350 { 3351 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3352 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3353 u16 prod_id; 3354 u16 val; 3355 int err; 3356 3357 if (!chip->info->ops->phy_read) 3358 return -EOPNOTSUPP; 3359 3360 mv88e6xxx_reg_lock(chip); 3361 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3362 mv88e6xxx_reg_unlock(chip); 3363 3364 /* Some internal PHYs don't have a model number. */ 3365 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3366 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3367 prod_id = family_prod_id_table[chip->info->family]; 3368 if (prod_id) 3369 val |= prod_id >> 4; 3370 } 3371 3372 return err ? err : val; 3373 } 3374 3375 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3376 { 3377 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3378 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3379 int err; 3380 3381 if (!chip->info->ops->phy_write) 3382 return -EOPNOTSUPP; 3383 3384 mv88e6xxx_reg_lock(chip); 3385 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3386 mv88e6xxx_reg_unlock(chip); 3387 3388 return err; 3389 } 3390 3391 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3392 struct device_node *np, 3393 bool external) 3394 { 3395 static int index; 3396 struct mv88e6xxx_mdio_bus *mdio_bus; 3397 struct mii_bus *bus; 3398 int err; 3399 3400 if (external) { 3401 mv88e6xxx_reg_lock(chip); 3402 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3403 mv88e6xxx_reg_unlock(chip); 3404 3405 if (err) 3406 return err; 3407 } 3408 3409 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3410 if (!bus) 3411 return -ENOMEM; 3412 3413 mdio_bus = bus->priv; 3414 mdio_bus->bus = bus; 3415 mdio_bus->chip = chip; 3416 INIT_LIST_HEAD(&mdio_bus->list); 3417 mdio_bus->external = external; 3418 3419 if (np) { 3420 bus->name = np->full_name; 3421 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3422 } else { 3423 bus->name = "mv88e6xxx SMI"; 3424 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3425 } 3426 3427 bus->read = mv88e6xxx_mdio_read; 3428 bus->write = mv88e6xxx_mdio_write; 3429 bus->parent = chip->dev; 3430 3431 if (!external) { 3432 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3433 if (err) 3434 goto out; 3435 } 3436 3437 err = of_mdiobus_register(bus, np); 3438 if (err) { 3439 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3440 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3441 goto out; 3442 } 3443 3444 if (external) 3445 list_add_tail(&mdio_bus->list, &chip->mdios); 3446 else 3447 list_add(&mdio_bus->list, &chip->mdios); 3448 3449 return 0; 3450 3451 out: 3452 mdiobus_free(bus); 3453 return err; 3454 } 3455 3456 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3457 3458 { 3459 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3460 struct mii_bus *bus; 3461 3462 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3463 bus = mdio_bus->bus; 3464 3465 if (!mdio_bus->external) 3466 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3467 3468 mdiobus_unregister(bus); 3469 mdiobus_free(bus); 3470 } 3471 } 3472 3473 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3474 struct device_node *np) 3475 { 3476 struct device_node *child; 3477 int err; 3478 3479 /* Always register one mdio bus for the internal/default mdio 3480 * bus. This maybe represented in the device tree, but is 3481 * optional. 3482 */ 3483 child = of_get_child_by_name(np, "mdio"); 3484 err = mv88e6xxx_mdio_register(chip, child, false); 3485 if (err) 3486 return err; 3487 3488 /* Walk the device tree, and see if there are any other nodes 3489 * which say they are compatible with the external mdio 3490 * bus. 3491 */ 3492 for_each_available_child_of_node(np, child) { 3493 if (of_device_is_compatible( 3494 child, "marvell,mv88e6xxx-mdio-external")) { 3495 err = mv88e6xxx_mdio_register(chip, child, true); 3496 if (err) { 3497 mv88e6xxx_mdios_unregister(chip); 3498 of_node_put(child); 3499 return err; 3500 } 3501 } 3502 } 3503 3504 return 0; 3505 } 3506 3507 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3508 { 3509 struct mv88e6xxx_chip *chip = ds->priv; 3510 3511 return chip->eeprom_len; 3512 } 3513 3514 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3515 struct ethtool_eeprom *eeprom, u8 *data) 3516 { 3517 struct mv88e6xxx_chip *chip = ds->priv; 3518 int err; 3519 3520 if (!chip->info->ops->get_eeprom) 3521 return -EOPNOTSUPP; 3522 3523 mv88e6xxx_reg_lock(chip); 3524 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3525 mv88e6xxx_reg_unlock(chip); 3526 3527 if (err) 3528 return err; 3529 3530 eeprom->magic = 0xc3ec4951; 3531 3532 return 0; 3533 } 3534 3535 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3536 struct ethtool_eeprom *eeprom, u8 *data) 3537 { 3538 struct mv88e6xxx_chip *chip = ds->priv; 3539 int err; 3540 3541 if (!chip->info->ops->set_eeprom) 3542 return -EOPNOTSUPP; 3543 3544 if (eeprom->magic != 0xc3ec4951) 3545 return -EINVAL; 3546 3547 mv88e6xxx_reg_lock(chip); 3548 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3549 mv88e6xxx_reg_unlock(chip); 3550 3551 return err; 3552 } 3553 3554 static const struct mv88e6xxx_ops mv88e6085_ops = { 3555 /* MV88E6XXX_FAMILY_6097 */ 3556 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3557 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3558 .irl_init_all = mv88e6352_g2_irl_init_all, 3559 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3560 .phy_read = mv88e6185_phy_ppu_read, 3561 .phy_write = mv88e6185_phy_ppu_write, 3562 .port_set_link = mv88e6xxx_port_set_link, 3563 .port_sync_link = mv88e6xxx_port_sync_link, 3564 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3565 .port_tag_remap = mv88e6095_port_tag_remap, 3566 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3567 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3568 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3569 .port_set_ether_type = mv88e6351_port_set_ether_type, 3570 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3571 .port_pause_limit = mv88e6097_port_pause_limit, 3572 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3573 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3574 .port_get_cmode = mv88e6185_port_get_cmode, 3575 .port_setup_message_port = mv88e6xxx_setup_message_port, 3576 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3577 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3578 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3579 .stats_get_strings = mv88e6095_stats_get_strings, 3580 .stats_get_stats = mv88e6095_stats_get_stats, 3581 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3582 .set_egress_port = mv88e6095_g1_set_egress_port, 3583 .watchdog_ops = &mv88e6097_watchdog_ops, 3584 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3585 .pot_clear = mv88e6xxx_g2_pot_clear, 3586 .ppu_enable = mv88e6185_g1_ppu_enable, 3587 .ppu_disable = mv88e6185_g1_ppu_disable, 3588 .reset = mv88e6185_g1_reset, 3589 .rmu_disable = mv88e6085_g1_rmu_disable, 3590 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3591 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3592 .phylink_validate = mv88e6185_phylink_validate, 3593 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3594 }; 3595 3596 static const struct mv88e6xxx_ops mv88e6095_ops = { 3597 /* MV88E6XXX_FAMILY_6095 */ 3598 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3599 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3600 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3601 .phy_read = mv88e6185_phy_ppu_read, 3602 .phy_write = mv88e6185_phy_ppu_write, 3603 .port_set_link = mv88e6xxx_port_set_link, 3604 .port_sync_link = mv88e6185_port_sync_link, 3605 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3606 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3607 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3608 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3609 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3610 .port_get_cmode = mv88e6185_port_get_cmode, 3611 .port_setup_message_port = mv88e6xxx_setup_message_port, 3612 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3613 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3614 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3615 .stats_get_strings = mv88e6095_stats_get_strings, 3616 .stats_get_stats = mv88e6095_stats_get_stats, 3617 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3618 .serdes_power = mv88e6185_serdes_power, 3619 .serdes_get_lane = mv88e6185_serdes_get_lane, 3620 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3621 .ppu_enable = mv88e6185_g1_ppu_enable, 3622 .ppu_disable = mv88e6185_g1_ppu_disable, 3623 .reset = mv88e6185_g1_reset, 3624 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3625 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3626 .phylink_validate = mv88e6185_phylink_validate, 3627 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3628 }; 3629 3630 static const struct mv88e6xxx_ops mv88e6097_ops = { 3631 /* MV88E6XXX_FAMILY_6097 */ 3632 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3633 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3634 .irl_init_all = mv88e6352_g2_irl_init_all, 3635 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3636 .phy_read = mv88e6xxx_g2_smi_phy_read, 3637 .phy_write = mv88e6xxx_g2_smi_phy_write, 3638 .port_set_link = mv88e6xxx_port_set_link, 3639 .port_sync_link = mv88e6185_port_sync_link, 3640 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3641 .port_tag_remap = mv88e6095_port_tag_remap, 3642 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3643 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3644 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3645 .port_set_ether_type = mv88e6351_port_set_ether_type, 3646 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3647 .port_pause_limit = mv88e6097_port_pause_limit, 3648 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3649 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3650 .port_get_cmode = mv88e6185_port_get_cmode, 3651 .port_setup_message_port = mv88e6xxx_setup_message_port, 3652 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3653 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3654 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3655 .stats_get_strings = mv88e6095_stats_get_strings, 3656 .stats_get_stats = mv88e6095_stats_get_stats, 3657 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3658 .set_egress_port = mv88e6095_g1_set_egress_port, 3659 .watchdog_ops = &mv88e6097_watchdog_ops, 3660 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3661 .serdes_power = mv88e6185_serdes_power, 3662 .serdes_get_lane = mv88e6185_serdes_get_lane, 3663 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3664 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3665 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3666 .serdes_irq_status = mv88e6097_serdes_irq_status, 3667 .pot_clear = mv88e6xxx_g2_pot_clear, 3668 .reset = mv88e6352_g1_reset, 3669 .rmu_disable = mv88e6085_g1_rmu_disable, 3670 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3671 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3672 .phylink_validate = mv88e6185_phylink_validate, 3673 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3674 }; 3675 3676 static const struct mv88e6xxx_ops mv88e6123_ops = { 3677 /* MV88E6XXX_FAMILY_6165 */ 3678 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3679 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3680 .irl_init_all = mv88e6352_g2_irl_init_all, 3681 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3682 .phy_read = mv88e6xxx_g2_smi_phy_read, 3683 .phy_write = mv88e6xxx_g2_smi_phy_write, 3684 .port_set_link = mv88e6xxx_port_set_link, 3685 .port_sync_link = mv88e6xxx_port_sync_link, 3686 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3687 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3688 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3689 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3690 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3691 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3692 .port_get_cmode = mv88e6185_port_get_cmode, 3693 .port_setup_message_port = mv88e6xxx_setup_message_port, 3694 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3695 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3696 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3697 .stats_get_strings = mv88e6095_stats_get_strings, 3698 .stats_get_stats = mv88e6095_stats_get_stats, 3699 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3700 .set_egress_port = mv88e6095_g1_set_egress_port, 3701 .watchdog_ops = &mv88e6097_watchdog_ops, 3702 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3703 .pot_clear = mv88e6xxx_g2_pot_clear, 3704 .reset = mv88e6352_g1_reset, 3705 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3706 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3707 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3708 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3709 .phylink_validate = mv88e6185_phylink_validate, 3710 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3711 }; 3712 3713 static const struct mv88e6xxx_ops mv88e6131_ops = { 3714 /* MV88E6XXX_FAMILY_6185 */ 3715 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3716 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3717 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3718 .phy_read = mv88e6185_phy_ppu_read, 3719 .phy_write = mv88e6185_phy_ppu_write, 3720 .port_set_link = mv88e6xxx_port_set_link, 3721 .port_sync_link = mv88e6xxx_port_sync_link, 3722 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3723 .port_tag_remap = mv88e6095_port_tag_remap, 3724 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3725 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3726 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3727 .port_set_ether_type = mv88e6351_port_set_ether_type, 3728 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3729 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3730 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3731 .port_pause_limit = mv88e6097_port_pause_limit, 3732 .port_set_pause = mv88e6185_port_set_pause, 3733 .port_get_cmode = mv88e6185_port_get_cmode, 3734 .port_setup_message_port = mv88e6xxx_setup_message_port, 3735 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3736 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3737 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3738 .stats_get_strings = mv88e6095_stats_get_strings, 3739 .stats_get_stats = mv88e6095_stats_get_stats, 3740 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3741 .set_egress_port = mv88e6095_g1_set_egress_port, 3742 .watchdog_ops = &mv88e6097_watchdog_ops, 3743 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3744 .ppu_enable = mv88e6185_g1_ppu_enable, 3745 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3746 .ppu_disable = mv88e6185_g1_ppu_disable, 3747 .reset = mv88e6185_g1_reset, 3748 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3749 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3750 .phylink_validate = mv88e6185_phylink_validate, 3751 }; 3752 3753 static const struct mv88e6xxx_ops mv88e6141_ops = { 3754 /* MV88E6XXX_FAMILY_6341 */ 3755 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3756 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3757 .irl_init_all = mv88e6352_g2_irl_init_all, 3758 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3759 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3760 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3761 .phy_read = mv88e6xxx_g2_smi_phy_read, 3762 .phy_write = mv88e6xxx_g2_smi_phy_write, 3763 .port_set_link = mv88e6xxx_port_set_link, 3764 .port_sync_link = mv88e6xxx_port_sync_link, 3765 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3766 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3767 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3768 .port_tag_remap = mv88e6095_port_tag_remap, 3769 .port_set_policy = mv88e6352_port_set_policy, 3770 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3771 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3772 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3773 .port_set_ether_type = mv88e6351_port_set_ether_type, 3774 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3775 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3776 .port_pause_limit = mv88e6097_port_pause_limit, 3777 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3778 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3779 .port_get_cmode = mv88e6352_port_get_cmode, 3780 .port_set_cmode = mv88e6341_port_set_cmode, 3781 .port_setup_message_port = mv88e6xxx_setup_message_port, 3782 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3783 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3784 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3785 .stats_get_strings = mv88e6320_stats_get_strings, 3786 .stats_get_stats = mv88e6390_stats_get_stats, 3787 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3788 .set_egress_port = mv88e6390_g1_set_egress_port, 3789 .watchdog_ops = &mv88e6390_watchdog_ops, 3790 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3791 .pot_clear = mv88e6xxx_g2_pot_clear, 3792 .reset = mv88e6352_g1_reset, 3793 .rmu_disable = mv88e6390_g1_rmu_disable, 3794 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3795 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3796 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3797 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3798 .serdes_power = mv88e6390_serdes_power, 3799 .serdes_get_lane = mv88e6341_serdes_get_lane, 3800 /* Check status register pause & lpa register */ 3801 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3802 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3803 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3804 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3805 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3806 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3807 .serdes_irq_status = mv88e6390_serdes_irq_status, 3808 .gpio_ops = &mv88e6352_gpio_ops, 3809 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3810 .serdes_get_strings = mv88e6390_serdes_get_strings, 3811 .serdes_get_stats = mv88e6390_serdes_get_stats, 3812 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3813 .serdes_get_regs = mv88e6390_serdes_get_regs, 3814 .phylink_validate = mv88e6341_phylink_validate, 3815 }; 3816 3817 static const struct mv88e6xxx_ops mv88e6161_ops = { 3818 /* MV88E6XXX_FAMILY_6165 */ 3819 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3820 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3821 .irl_init_all = mv88e6352_g2_irl_init_all, 3822 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3823 .phy_read = mv88e6xxx_g2_smi_phy_read, 3824 .phy_write = mv88e6xxx_g2_smi_phy_write, 3825 .port_set_link = mv88e6xxx_port_set_link, 3826 .port_sync_link = mv88e6xxx_port_sync_link, 3827 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3828 .port_tag_remap = mv88e6095_port_tag_remap, 3829 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3830 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3831 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3832 .port_set_ether_type = mv88e6351_port_set_ether_type, 3833 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3834 .port_pause_limit = mv88e6097_port_pause_limit, 3835 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3836 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3837 .port_get_cmode = mv88e6185_port_get_cmode, 3838 .port_setup_message_port = mv88e6xxx_setup_message_port, 3839 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3840 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3841 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3842 .stats_get_strings = mv88e6095_stats_get_strings, 3843 .stats_get_stats = mv88e6095_stats_get_stats, 3844 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3845 .set_egress_port = mv88e6095_g1_set_egress_port, 3846 .watchdog_ops = &mv88e6097_watchdog_ops, 3847 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3848 .pot_clear = mv88e6xxx_g2_pot_clear, 3849 .reset = mv88e6352_g1_reset, 3850 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3851 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3852 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3853 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3854 .avb_ops = &mv88e6165_avb_ops, 3855 .ptp_ops = &mv88e6165_ptp_ops, 3856 .phylink_validate = mv88e6185_phylink_validate, 3857 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3858 }; 3859 3860 static const struct mv88e6xxx_ops mv88e6165_ops = { 3861 /* MV88E6XXX_FAMILY_6165 */ 3862 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3863 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3864 .irl_init_all = mv88e6352_g2_irl_init_all, 3865 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3866 .phy_read = mv88e6165_phy_read, 3867 .phy_write = mv88e6165_phy_write, 3868 .port_set_link = mv88e6xxx_port_set_link, 3869 .port_sync_link = mv88e6xxx_port_sync_link, 3870 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3871 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3872 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3873 .port_get_cmode = mv88e6185_port_get_cmode, 3874 .port_setup_message_port = mv88e6xxx_setup_message_port, 3875 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3876 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3877 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3878 .stats_get_strings = mv88e6095_stats_get_strings, 3879 .stats_get_stats = mv88e6095_stats_get_stats, 3880 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3881 .set_egress_port = mv88e6095_g1_set_egress_port, 3882 .watchdog_ops = &mv88e6097_watchdog_ops, 3883 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3884 .pot_clear = mv88e6xxx_g2_pot_clear, 3885 .reset = mv88e6352_g1_reset, 3886 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3887 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3888 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3889 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3890 .avb_ops = &mv88e6165_avb_ops, 3891 .ptp_ops = &mv88e6165_ptp_ops, 3892 .phylink_validate = mv88e6185_phylink_validate, 3893 }; 3894 3895 static const struct mv88e6xxx_ops mv88e6171_ops = { 3896 /* MV88E6XXX_FAMILY_6351 */ 3897 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3898 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3899 .irl_init_all = mv88e6352_g2_irl_init_all, 3900 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3901 .phy_read = mv88e6xxx_g2_smi_phy_read, 3902 .phy_write = mv88e6xxx_g2_smi_phy_write, 3903 .port_set_link = mv88e6xxx_port_set_link, 3904 .port_sync_link = mv88e6xxx_port_sync_link, 3905 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3906 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3907 .port_tag_remap = mv88e6095_port_tag_remap, 3908 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3909 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3910 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3911 .port_set_ether_type = mv88e6351_port_set_ether_type, 3912 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3913 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3914 .port_pause_limit = mv88e6097_port_pause_limit, 3915 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3916 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3917 .port_get_cmode = mv88e6352_port_get_cmode, 3918 .port_setup_message_port = mv88e6xxx_setup_message_port, 3919 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3920 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3921 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3922 .stats_get_strings = mv88e6095_stats_get_strings, 3923 .stats_get_stats = mv88e6095_stats_get_stats, 3924 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3925 .set_egress_port = mv88e6095_g1_set_egress_port, 3926 .watchdog_ops = &mv88e6097_watchdog_ops, 3927 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3928 .pot_clear = mv88e6xxx_g2_pot_clear, 3929 .reset = mv88e6352_g1_reset, 3930 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3931 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3932 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3933 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3934 .phylink_validate = mv88e6185_phylink_validate, 3935 }; 3936 3937 static const struct mv88e6xxx_ops mv88e6172_ops = { 3938 /* MV88E6XXX_FAMILY_6352 */ 3939 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3940 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3941 .irl_init_all = mv88e6352_g2_irl_init_all, 3942 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3943 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3944 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3945 .phy_read = mv88e6xxx_g2_smi_phy_read, 3946 .phy_write = mv88e6xxx_g2_smi_phy_write, 3947 .port_set_link = mv88e6xxx_port_set_link, 3948 .port_sync_link = mv88e6xxx_port_sync_link, 3949 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3950 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3951 .port_tag_remap = mv88e6095_port_tag_remap, 3952 .port_set_policy = mv88e6352_port_set_policy, 3953 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3954 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3955 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3956 .port_set_ether_type = mv88e6351_port_set_ether_type, 3957 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3958 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3959 .port_pause_limit = mv88e6097_port_pause_limit, 3960 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3961 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3962 .port_get_cmode = mv88e6352_port_get_cmode, 3963 .port_setup_message_port = mv88e6xxx_setup_message_port, 3964 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3965 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3966 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3967 .stats_get_strings = mv88e6095_stats_get_strings, 3968 .stats_get_stats = mv88e6095_stats_get_stats, 3969 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3970 .set_egress_port = mv88e6095_g1_set_egress_port, 3971 .watchdog_ops = &mv88e6097_watchdog_ops, 3972 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3973 .pot_clear = mv88e6xxx_g2_pot_clear, 3974 .reset = mv88e6352_g1_reset, 3975 .rmu_disable = mv88e6352_g1_rmu_disable, 3976 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3977 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3978 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3979 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3980 .serdes_get_lane = mv88e6352_serdes_get_lane, 3981 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3982 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3983 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3984 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3985 .serdes_power = mv88e6352_serdes_power, 3986 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3987 .serdes_get_regs = mv88e6352_serdes_get_regs, 3988 .gpio_ops = &mv88e6352_gpio_ops, 3989 .phylink_validate = mv88e6352_phylink_validate, 3990 }; 3991 3992 static const struct mv88e6xxx_ops mv88e6175_ops = { 3993 /* MV88E6XXX_FAMILY_6351 */ 3994 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3995 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3996 .irl_init_all = mv88e6352_g2_irl_init_all, 3997 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3998 .phy_read = mv88e6xxx_g2_smi_phy_read, 3999 .phy_write = mv88e6xxx_g2_smi_phy_write, 4000 .port_set_link = mv88e6xxx_port_set_link, 4001 .port_sync_link = mv88e6xxx_port_sync_link, 4002 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4003 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4004 .port_tag_remap = mv88e6095_port_tag_remap, 4005 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4006 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4007 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4008 .port_set_ether_type = mv88e6351_port_set_ether_type, 4009 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4010 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4011 .port_pause_limit = mv88e6097_port_pause_limit, 4012 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4013 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4014 .port_get_cmode = mv88e6352_port_get_cmode, 4015 .port_setup_message_port = mv88e6xxx_setup_message_port, 4016 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4017 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4018 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4019 .stats_get_strings = mv88e6095_stats_get_strings, 4020 .stats_get_stats = mv88e6095_stats_get_stats, 4021 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4022 .set_egress_port = mv88e6095_g1_set_egress_port, 4023 .watchdog_ops = &mv88e6097_watchdog_ops, 4024 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4025 .pot_clear = mv88e6xxx_g2_pot_clear, 4026 .reset = mv88e6352_g1_reset, 4027 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4028 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4029 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4030 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4031 .phylink_validate = mv88e6185_phylink_validate, 4032 }; 4033 4034 static const struct mv88e6xxx_ops mv88e6176_ops = { 4035 /* MV88E6XXX_FAMILY_6352 */ 4036 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4037 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4038 .irl_init_all = mv88e6352_g2_irl_init_all, 4039 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4040 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4042 .phy_read = mv88e6xxx_g2_smi_phy_read, 4043 .phy_write = mv88e6xxx_g2_smi_phy_write, 4044 .port_set_link = mv88e6xxx_port_set_link, 4045 .port_sync_link = mv88e6xxx_port_sync_link, 4046 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4047 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4048 .port_tag_remap = mv88e6095_port_tag_remap, 4049 .port_set_policy = mv88e6352_port_set_policy, 4050 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4051 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4052 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4053 .port_set_ether_type = mv88e6351_port_set_ether_type, 4054 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4055 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4056 .port_pause_limit = mv88e6097_port_pause_limit, 4057 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4058 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4059 .port_get_cmode = mv88e6352_port_get_cmode, 4060 .port_setup_message_port = mv88e6xxx_setup_message_port, 4061 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4062 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4063 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4064 .stats_get_strings = mv88e6095_stats_get_strings, 4065 .stats_get_stats = mv88e6095_stats_get_stats, 4066 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4067 .set_egress_port = mv88e6095_g1_set_egress_port, 4068 .watchdog_ops = &mv88e6097_watchdog_ops, 4069 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4070 .pot_clear = mv88e6xxx_g2_pot_clear, 4071 .reset = mv88e6352_g1_reset, 4072 .rmu_disable = mv88e6352_g1_rmu_disable, 4073 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4074 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4075 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4076 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4077 .serdes_get_lane = mv88e6352_serdes_get_lane, 4078 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4079 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4080 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4081 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4082 .serdes_power = mv88e6352_serdes_power, 4083 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4084 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4085 .serdes_irq_status = mv88e6352_serdes_irq_status, 4086 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4087 .serdes_get_regs = mv88e6352_serdes_get_regs, 4088 .gpio_ops = &mv88e6352_gpio_ops, 4089 .phylink_validate = mv88e6352_phylink_validate, 4090 }; 4091 4092 static const struct mv88e6xxx_ops mv88e6185_ops = { 4093 /* MV88E6XXX_FAMILY_6185 */ 4094 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4095 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4096 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4097 .phy_read = mv88e6185_phy_ppu_read, 4098 .phy_write = mv88e6185_phy_ppu_write, 4099 .port_set_link = mv88e6xxx_port_set_link, 4100 .port_sync_link = mv88e6185_port_sync_link, 4101 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4102 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4103 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4104 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4105 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4106 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4107 .port_set_pause = mv88e6185_port_set_pause, 4108 .port_get_cmode = mv88e6185_port_get_cmode, 4109 .port_setup_message_port = mv88e6xxx_setup_message_port, 4110 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4111 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4112 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4113 .stats_get_strings = mv88e6095_stats_get_strings, 4114 .stats_get_stats = mv88e6095_stats_get_stats, 4115 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4116 .set_egress_port = mv88e6095_g1_set_egress_port, 4117 .watchdog_ops = &mv88e6097_watchdog_ops, 4118 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4119 .serdes_power = mv88e6185_serdes_power, 4120 .serdes_get_lane = mv88e6185_serdes_get_lane, 4121 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4122 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4123 .ppu_enable = mv88e6185_g1_ppu_enable, 4124 .ppu_disable = mv88e6185_g1_ppu_disable, 4125 .reset = mv88e6185_g1_reset, 4126 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4127 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4128 .phylink_validate = mv88e6185_phylink_validate, 4129 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4130 }; 4131 4132 static const struct mv88e6xxx_ops mv88e6190_ops = { 4133 /* MV88E6XXX_FAMILY_6390 */ 4134 .setup_errata = mv88e6390_setup_errata, 4135 .irl_init_all = mv88e6390_g2_irl_init_all, 4136 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4137 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4138 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4139 .phy_read = mv88e6xxx_g2_smi_phy_read, 4140 .phy_write = mv88e6xxx_g2_smi_phy_write, 4141 .port_set_link = mv88e6xxx_port_set_link, 4142 .port_sync_link = mv88e6xxx_port_sync_link, 4143 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4144 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4145 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4146 .port_tag_remap = mv88e6390_port_tag_remap, 4147 .port_set_policy = mv88e6352_port_set_policy, 4148 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4149 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4150 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4151 .port_set_ether_type = mv88e6351_port_set_ether_type, 4152 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4153 .port_pause_limit = mv88e6390_port_pause_limit, 4154 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4155 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4156 .port_get_cmode = mv88e6352_port_get_cmode, 4157 .port_set_cmode = mv88e6390_port_set_cmode, 4158 .port_setup_message_port = mv88e6xxx_setup_message_port, 4159 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4160 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4161 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4162 .stats_get_strings = mv88e6320_stats_get_strings, 4163 .stats_get_stats = mv88e6390_stats_get_stats, 4164 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4165 .set_egress_port = mv88e6390_g1_set_egress_port, 4166 .watchdog_ops = &mv88e6390_watchdog_ops, 4167 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4168 .pot_clear = mv88e6xxx_g2_pot_clear, 4169 .reset = mv88e6352_g1_reset, 4170 .rmu_disable = mv88e6390_g1_rmu_disable, 4171 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4172 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4173 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4174 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4175 .serdes_power = mv88e6390_serdes_power, 4176 .serdes_get_lane = mv88e6390_serdes_get_lane, 4177 /* Check status register pause & lpa register */ 4178 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4179 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4180 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4181 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4182 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4183 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4184 .serdes_irq_status = mv88e6390_serdes_irq_status, 4185 .serdes_get_strings = mv88e6390_serdes_get_strings, 4186 .serdes_get_stats = mv88e6390_serdes_get_stats, 4187 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4188 .serdes_get_regs = mv88e6390_serdes_get_regs, 4189 .gpio_ops = &mv88e6352_gpio_ops, 4190 .phylink_validate = mv88e6390_phylink_validate, 4191 }; 4192 4193 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4194 /* MV88E6XXX_FAMILY_6390 */ 4195 .setup_errata = mv88e6390_setup_errata, 4196 .irl_init_all = mv88e6390_g2_irl_init_all, 4197 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4198 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4199 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4200 .phy_read = mv88e6xxx_g2_smi_phy_read, 4201 .phy_write = mv88e6xxx_g2_smi_phy_write, 4202 .port_set_link = mv88e6xxx_port_set_link, 4203 .port_sync_link = mv88e6xxx_port_sync_link, 4204 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4205 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4206 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4207 .port_tag_remap = mv88e6390_port_tag_remap, 4208 .port_set_policy = mv88e6352_port_set_policy, 4209 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4210 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4211 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4212 .port_set_ether_type = mv88e6351_port_set_ether_type, 4213 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4214 .port_pause_limit = mv88e6390_port_pause_limit, 4215 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4216 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4217 .port_get_cmode = mv88e6352_port_get_cmode, 4218 .port_set_cmode = mv88e6390x_port_set_cmode, 4219 .port_setup_message_port = mv88e6xxx_setup_message_port, 4220 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4221 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4222 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4223 .stats_get_strings = mv88e6320_stats_get_strings, 4224 .stats_get_stats = mv88e6390_stats_get_stats, 4225 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4226 .set_egress_port = mv88e6390_g1_set_egress_port, 4227 .watchdog_ops = &mv88e6390_watchdog_ops, 4228 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4229 .pot_clear = mv88e6xxx_g2_pot_clear, 4230 .reset = mv88e6352_g1_reset, 4231 .rmu_disable = mv88e6390_g1_rmu_disable, 4232 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4233 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4234 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4235 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4236 .serdes_power = mv88e6390_serdes_power, 4237 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4238 /* Check status register pause & lpa register */ 4239 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4240 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4241 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4242 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4243 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4244 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4245 .serdes_irq_status = mv88e6390_serdes_irq_status, 4246 .serdes_get_strings = mv88e6390_serdes_get_strings, 4247 .serdes_get_stats = mv88e6390_serdes_get_stats, 4248 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4249 .serdes_get_regs = mv88e6390_serdes_get_regs, 4250 .gpio_ops = &mv88e6352_gpio_ops, 4251 .phylink_validate = mv88e6390x_phylink_validate, 4252 }; 4253 4254 static const struct mv88e6xxx_ops mv88e6191_ops = { 4255 /* MV88E6XXX_FAMILY_6390 */ 4256 .setup_errata = mv88e6390_setup_errata, 4257 .irl_init_all = mv88e6390_g2_irl_init_all, 4258 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4259 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4260 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4261 .phy_read = mv88e6xxx_g2_smi_phy_read, 4262 .phy_write = mv88e6xxx_g2_smi_phy_write, 4263 .port_set_link = mv88e6xxx_port_set_link, 4264 .port_sync_link = mv88e6xxx_port_sync_link, 4265 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4266 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4267 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4268 .port_tag_remap = mv88e6390_port_tag_remap, 4269 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4270 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4271 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4272 .port_set_ether_type = mv88e6351_port_set_ether_type, 4273 .port_pause_limit = mv88e6390_port_pause_limit, 4274 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4275 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4276 .port_get_cmode = mv88e6352_port_get_cmode, 4277 .port_set_cmode = mv88e6390_port_set_cmode, 4278 .port_setup_message_port = mv88e6xxx_setup_message_port, 4279 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4280 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4281 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4282 .stats_get_strings = mv88e6320_stats_get_strings, 4283 .stats_get_stats = mv88e6390_stats_get_stats, 4284 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4285 .set_egress_port = mv88e6390_g1_set_egress_port, 4286 .watchdog_ops = &mv88e6390_watchdog_ops, 4287 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4288 .pot_clear = mv88e6xxx_g2_pot_clear, 4289 .reset = mv88e6352_g1_reset, 4290 .rmu_disable = mv88e6390_g1_rmu_disable, 4291 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4292 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4293 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4294 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4295 .serdes_power = mv88e6390_serdes_power, 4296 .serdes_get_lane = mv88e6390_serdes_get_lane, 4297 /* Check status register pause & lpa register */ 4298 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4299 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4300 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4301 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4302 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4303 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4304 .serdes_irq_status = mv88e6390_serdes_irq_status, 4305 .serdes_get_strings = mv88e6390_serdes_get_strings, 4306 .serdes_get_stats = mv88e6390_serdes_get_stats, 4307 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4308 .serdes_get_regs = mv88e6390_serdes_get_regs, 4309 .avb_ops = &mv88e6390_avb_ops, 4310 .ptp_ops = &mv88e6352_ptp_ops, 4311 .phylink_validate = mv88e6390_phylink_validate, 4312 }; 4313 4314 static const struct mv88e6xxx_ops mv88e6240_ops = { 4315 /* MV88E6XXX_FAMILY_6352 */ 4316 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4317 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4318 .irl_init_all = mv88e6352_g2_irl_init_all, 4319 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4320 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4321 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4322 .phy_read = mv88e6xxx_g2_smi_phy_read, 4323 .phy_write = mv88e6xxx_g2_smi_phy_write, 4324 .port_set_link = mv88e6xxx_port_set_link, 4325 .port_sync_link = mv88e6xxx_port_sync_link, 4326 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4327 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4328 .port_tag_remap = mv88e6095_port_tag_remap, 4329 .port_set_policy = mv88e6352_port_set_policy, 4330 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4331 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4332 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4333 .port_set_ether_type = mv88e6351_port_set_ether_type, 4334 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4335 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4336 .port_pause_limit = mv88e6097_port_pause_limit, 4337 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4338 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4339 .port_get_cmode = mv88e6352_port_get_cmode, 4340 .port_setup_message_port = mv88e6xxx_setup_message_port, 4341 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4342 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4343 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4344 .stats_get_strings = mv88e6095_stats_get_strings, 4345 .stats_get_stats = mv88e6095_stats_get_stats, 4346 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4347 .set_egress_port = mv88e6095_g1_set_egress_port, 4348 .watchdog_ops = &mv88e6097_watchdog_ops, 4349 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4350 .pot_clear = mv88e6xxx_g2_pot_clear, 4351 .reset = mv88e6352_g1_reset, 4352 .rmu_disable = mv88e6352_g1_rmu_disable, 4353 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4354 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4355 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4356 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4357 .serdes_get_lane = mv88e6352_serdes_get_lane, 4358 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4359 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4360 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4361 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4362 .serdes_power = mv88e6352_serdes_power, 4363 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4364 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4365 .serdes_irq_status = mv88e6352_serdes_irq_status, 4366 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4367 .serdes_get_regs = mv88e6352_serdes_get_regs, 4368 .gpio_ops = &mv88e6352_gpio_ops, 4369 .avb_ops = &mv88e6352_avb_ops, 4370 .ptp_ops = &mv88e6352_ptp_ops, 4371 .phylink_validate = mv88e6352_phylink_validate, 4372 }; 4373 4374 static const struct mv88e6xxx_ops mv88e6250_ops = { 4375 /* MV88E6XXX_FAMILY_6250 */ 4376 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4377 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4378 .irl_init_all = mv88e6352_g2_irl_init_all, 4379 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4380 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4381 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4382 .phy_read = mv88e6xxx_g2_smi_phy_read, 4383 .phy_write = mv88e6xxx_g2_smi_phy_write, 4384 .port_set_link = mv88e6xxx_port_set_link, 4385 .port_sync_link = mv88e6xxx_port_sync_link, 4386 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4387 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4388 .port_tag_remap = mv88e6095_port_tag_remap, 4389 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4390 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4391 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4392 .port_set_ether_type = mv88e6351_port_set_ether_type, 4393 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4394 .port_pause_limit = mv88e6097_port_pause_limit, 4395 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4396 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4397 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4398 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4399 .stats_get_strings = mv88e6250_stats_get_strings, 4400 .stats_get_stats = mv88e6250_stats_get_stats, 4401 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4402 .set_egress_port = mv88e6095_g1_set_egress_port, 4403 .watchdog_ops = &mv88e6250_watchdog_ops, 4404 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4405 .pot_clear = mv88e6xxx_g2_pot_clear, 4406 .reset = mv88e6250_g1_reset, 4407 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4408 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4409 .avb_ops = &mv88e6352_avb_ops, 4410 .ptp_ops = &mv88e6250_ptp_ops, 4411 .phylink_validate = mv88e6065_phylink_validate, 4412 }; 4413 4414 static const struct mv88e6xxx_ops mv88e6290_ops = { 4415 /* MV88E6XXX_FAMILY_6390 */ 4416 .setup_errata = mv88e6390_setup_errata, 4417 .irl_init_all = mv88e6390_g2_irl_init_all, 4418 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4419 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4420 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4421 .phy_read = mv88e6xxx_g2_smi_phy_read, 4422 .phy_write = mv88e6xxx_g2_smi_phy_write, 4423 .port_set_link = mv88e6xxx_port_set_link, 4424 .port_sync_link = mv88e6xxx_port_sync_link, 4425 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4426 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4427 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4428 .port_tag_remap = mv88e6390_port_tag_remap, 4429 .port_set_policy = mv88e6352_port_set_policy, 4430 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4431 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4432 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4433 .port_set_ether_type = mv88e6351_port_set_ether_type, 4434 .port_pause_limit = mv88e6390_port_pause_limit, 4435 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4436 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4437 .port_get_cmode = mv88e6352_port_get_cmode, 4438 .port_set_cmode = mv88e6390_port_set_cmode, 4439 .port_setup_message_port = mv88e6xxx_setup_message_port, 4440 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4441 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4442 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4443 .stats_get_strings = mv88e6320_stats_get_strings, 4444 .stats_get_stats = mv88e6390_stats_get_stats, 4445 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4446 .set_egress_port = mv88e6390_g1_set_egress_port, 4447 .watchdog_ops = &mv88e6390_watchdog_ops, 4448 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4449 .pot_clear = mv88e6xxx_g2_pot_clear, 4450 .reset = mv88e6352_g1_reset, 4451 .rmu_disable = mv88e6390_g1_rmu_disable, 4452 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4453 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4454 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4455 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4456 .serdes_power = mv88e6390_serdes_power, 4457 .serdes_get_lane = mv88e6390_serdes_get_lane, 4458 /* Check status register pause & lpa register */ 4459 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4460 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4461 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4462 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4463 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4464 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4465 .serdes_irq_status = mv88e6390_serdes_irq_status, 4466 .serdes_get_strings = mv88e6390_serdes_get_strings, 4467 .serdes_get_stats = mv88e6390_serdes_get_stats, 4468 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4469 .serdes_get_regs = mv88e6390_serdes_get_regs, 4470 .gpio_ops = &mv88e6352_gpio_ops, 4471 .avb_ops = &mv88e6390_avb_ops, 4472 .ptp_ops = &mv88e6352_ptp_ops, 4473 .phylink_validate = mv88e6390_phylink_validate, 4474 }; 4475 4476 static const struct mv88e6xxx_ops mv88e6320_ops = { 4477 /* MV88E6XXX_FAMILY_6320 */ 4478 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4479 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4480 .irl_init_all = mv88e6352_g2_irl_init_all, 4481 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4482 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4483 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4484 .phy_read = mv88e6xxx_g2_smi_phy_read, 4485 .phy_write = mv88e6xxx_g2_smi_phy_write, 4486 .port_set_link = mv88e6xxx_port_set_link, 4487 .port_sync_link = mv88e6xxx_port_sync_link, 4488 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4489 .port_tag_remap = mv88e6095_port_tag_remap, 4490 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4491 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4492 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4493 .port_set_ether_type = mv88e6351_port_set_ether_type, 4494 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4495 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4496 .port_pause_limit = mv88e6097_port_pause_limit, 4497 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4498 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4499 .port_get_cmode = mv88e6352_port_get_cmode, 4500 .port_setup_message_port = mv88e6xxx_setup_message_port, 4501 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4502 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4503 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4504 .stats_get_strings = mv88e6320_stats_get_strings, 4505 .stats_get_stats = mv88e6320_stats_get_stats, 4506 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4507 .set_egress_port = mv88e6095_g1_set_egress_port, 4508 .watchdog_ops = &mv88e6390_watchdog_ops, 4509 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4510 .pot_clear = mv88e6xxx_g2_pot_clear, 4511 .reset = mv88e6352_g1_reset, 4512 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4513 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4514 .gpio_ops = &mv88e6352_gpio_ops, 4515 .avb_ops = &mv88e6352_avb_ops, 4516 .ptp_ops = &mv88e6352_ptp_ops, 4517 .phylink_validate = mv88e6185_phylink_validate, 4518 }; 4519 4520 static const struct mv88e6xxx_ops mv88e6321_ops = { 4521 /* MV88E6XXX_FAMILY_6320 */ 4522 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4523 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4524 .irl_init_all = mv88e6352_g2_irl_init_all, 4525 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4526 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4527 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4528 .phy_read = mv88e6xxx_g2_smi_phy_read, 4529 .phy_write = mv88e6xxx_g2_smi_phy_write, 4530 .port_set_link = mv88e6xxx_port_set_link, 4531 .port_sync_link = mv88e6xxx_port_sync_link, 4532 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4533 .port_tag_remap = mv88e6095_port_tag_remap, 4534 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4535 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4536 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4537 .port_set_ether_type = mv88e6351_port_set_ether_type, 4538 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4539 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4540 .port_pause_limit = mv88e6097_port_pause_limit, 4541 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4542 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4543 .port_get_cmode = mv88e6352_port_get_cmode, 4544 .port_setup_message_port = mv88e6xxx_setup_message_port, 4545 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4546 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4547 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4548 .stats_get_strings = mv88e6320_stats_get_strings, 4549 .stats_get_stats = mv88e6320_stats_get_stats, 4550 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4551 .set_egress_port = mv88e6095_g1_set_egress_port, 4552 .watchdog_ops = &mv88e6390_watchdog_ops, 4553 .reset = mv88e6352_g1_reset, 4554 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4555 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4556 .gpio_ops = &mv88e6352_gpio_ops, 4557 .avb_ops = &mv88e6352_avb_ops, 4558 .ptp_ops = &mv88e6352_ptp_ops, 4559 .phylink_validate = mv88e6185_phylink_validate, 4560 }; 4561 4562 static const struct mv88e6xxx_ops mv88e6341_ops = { 4563 /* MV88E6XXX_FAMILY_6341 */ 4564 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4565 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4566 .irl_init_all = mv88e6352_g2_irl_init_all, 4567 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4568 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4569 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4570 .phy_read = mv88e6xxx_g2_smi_phy_read, 4571 .phy_write = mv88e6xxx_g2_smi_phy_write, 4572 .port_set_link = mv88e6xxx_port_set_link, 4573 .port_sync_link = mv88e6xxx_port_sync_link, 4574 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4575 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4576 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4577 .port_tag_remap = mv88e6095_port_tag_remap, 4578 .port_set_policy = mv88e6352_port_set_policy, 4579 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4580 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4581 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4582 .port_set_ether_type = mv88e6351_port_set_ether_type, 4583 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4584 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4585 .port_pause_limit = mv88e6097_port_pause_limit, 4586 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4587 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4588 .port_get_cmode = mv88e6352_port_get_cmode, 4589 .port_set_cmode = mv88e6341_port_set_cmode, 4590 .port_setup_message_port = mv88e6xxx_setup_message_port, 4591 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4592 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4593 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4594 .stats_get_strings = mv88e6320_stats_get_strings, 4595 .stats_get_stats = mv88e6390_stats_get_stats, 4596 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4597 .set_egress_port = mv88e6390_g1_set_egress_port, 4598 .watchdog_ops = &mv88e6390_watchdog_ops, 4599 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4600 .pot_clear = mv88e6xxx_g2_pot_clear, 4601 .reset = mv88e6352_g1_reset, 4602 .rmu_disable = mv88e6390_g1_rmu_disable, 4603 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4604 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4605 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4606 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4607 .serdes_power = mv88e6390_serdes_power, 4608 .serdes_get_lane = mv88e6341_serdes_get_lane, 4609 /* Check status register pause & lpa register */ 4610 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4611 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4612 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4613 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4614 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4615 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4616 .serdes_irq_status = mv88e6390_serdes_irq_status, 4617 .gpio_ops = &mv88e6352_gpio_ops, 4618 .avb_ops = &mv88e6390_avb_ops, 4619 .ptp_ops = &mv88e6352_ptp_ops, 4620 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4621 .serdes_get_strings = mv88e6390_serdes_get_strings, 4622 .serdes_get_stats = mv88e6390_serdes_get_stats, 4623 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4624 .serdes_get_regs = mv88e6390_serdes_get_regs, 4625 .phylink_validate = mv88e6341_phylink_validate, 4626 }; 4627 4628 static const struct mv88e6xxx_ops mv88e6350_ops = { 4629 /* MV88E6XXX_FAMILY_6351 */ 4630 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4631 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4632 .irl_init_all = mv88e6352_g2_irl_init_all, 4633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4634 .phy_read = mv88e6xxx_g2_smi_phy_read, 4635 .phy_write = mv88e6xxx_g2_smi_phy_write, 4636 .port_set_link = mv88e6xxx_port_set_link, 4637 .port_sync_link = mv88e6xxx_port_sync_link, 4638 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4639 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4640 .port_tag_remap = mv88e6095_port_tag_remap, 4641 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4642 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4643 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4644 .port_set_ether_type = mv88e6351_port_set_ether_type, 4645 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4646 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4647 .port_pause_limit = mv88e6097_port_pause_limit, 4648 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4649 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4650 .port_get_cmode = mv88e6352_port_get_cmode, 4651 .port_setup_message_port = mv88e6xxx_setup_message_port, 4652 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4653 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4654 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4655 .stats_get_strings = mv88e6095_stats_get_strings, 4656 .stats_get_stats = mv88e6095_stats_get_stats, 4657 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4658 .set_egress_port = mv88e6095_g1_set_egress_port, 4659 .watchdog_ops = &mv88e6097_watchdog_ops, 4660 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4661 .pot_clear = mv88e6xxx_g2_pot_clear, 4662 .reset = mv88e6352_g1_reset, 4663 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4664 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4665 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4666 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4667 .phylink_validate = mv88e6185_phylink_validate, 4668 }; 4669 4670 static const struct mv88e6xxx_ops mv88e6351_ops = { 4671 /* MV88E6XXX_FAMILY_6351 */ 4672 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4673 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4674 .irl_init_all = mv88e6352_g2_irl_init_all, 4675 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4676 .phy_read = mv88e6xxx_g2_smi_phy_read, 4677 .phy_write = mv88e6xxx_g2_smi_phy_write, 4678 .port_set_link = mv88e6xxx_port_set_link, 4679 .port_sync_link = mv88e6xxx_port_sync_link, 4680 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4681 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4682 .port_tag_remap = mv88e6095_port_tag_remap, 4683 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4684 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4685 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4686 .port_set_ether_type = mv88e6351_port_set_ether_type, 4687 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4688 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4689 .port_pause_limit = mv88e6097_port_pause_limit, 4690 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4691 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4692 .port_get_cmode = mv88e6352_port_get_cmode, 4693 .port_setup_message_port = mv88e6xxx_setup_message_port, 4694 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4695 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4696 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4697 .stats_get_strings = mv88e6095_stats_get_strings, 4698 .stats_get_stats = mv88e6095_stats_get_stats, 4699 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4700 .set_egress_port = mv88e6095_g1_set_egress_port, 4701 .watchdog_ops = &mv88e6097_watchdog_ops, 4702 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4703 .pot_clear = mv88e6xxx_g2_pot_clear, 4704 .reset = mv88e6352_g1_reset, 4705 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4706 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4707 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4708 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4709 .avb_ops = &mv88e6352_avb_ops, 4710 .ptp_ops = &mv88e6352_ptp_ops, 4711 .phylink_validate = mv88e6185_phylink_validate, 4712 }; 4713 4714 static const struct mv88e6xxx_ops mv88e6352_ops = { 4715 /* MV88E6XXX_FAMILY_6352 */ 4716 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4717 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4718 .irl_init_all = mv88e6352_g2_irl_init_all, 4719 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4720 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4721 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4722 .phy_read = mv88e6xxx_g2_smi_phy_read, 4723 .phy_write = mv88e6xxx_g2_smi_phy_write, 4724 .port_set_link = mv88e6xxx_port_set_link, 4725 .port_sync_link = mv88e6xxx_port_sync_link, 4726 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4727 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4728 .port_tag_remap = mv88e6095_port_tag_remap, 4729 .port_set_policy = mv88e6352_port_set_policy, 4730 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4731 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4732 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4733 .port_set_ether_type = mv88e6351_port_set_ether_type, 4734 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4735 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4736 .port_pause_limit = mv88e6097_port_pause_limit, 4737 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4738 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4739 .port_get_cmode = mv88e6352_port_get_cmode, 4740 .port_setup_message_port = mv88e6xxx_setup_message_port, 4741 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4742 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4743 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4744 .stats_get_strings = mv88e6095_stats_get_strings, 4745 .stats_get_stats = mv88e6095_stats_get_stats, 4746 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4747 .set_egress_port = mv88e6095_g1_set_egress_port, 4748 .watchdog_ops = &mv88e6097_watchdog_ops, 4749 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4750 .pot_clear = mv88e6xxx_g2_pot_clear, 4751 .reset = mv88e6352_g1_reset, 4752 .rmu_disable = mv88e6352_g1_rmu_disable, 4753 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4754 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4755 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4756 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4757 .serdes_get_lane = mv88e6352_serdes_get_lane, 4758 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4759 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4760 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4761 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4762 .serdes_power = mv88e6352_serdes_power, 4763 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4764 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4765 .serdes_irq_status = mv88e6352_serdes_irq_status, 4766 .gpio_ops = &mv88e6352_gpio_ops, 4767 .avb_ops = &mv88e6352_avb_ops, 4768 .ptp_ops = &mv88e6352_ptp_ops, 4769 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4770 .serdes_get_strings = mv88e6352_serdes_get_strings, 4771 .serdes_get_stats = mv88e6352_serdes_get_stats, 4772 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4773 .serdes_get_regs = mv88e6352_serdes_get_regs, 4774 .phylink_validate = mv88e6352_phylink_validate, 4775 }; 4776 4777 static const struct mv88e6xxx_ops mv88e6390_ops = { 4778 /* MV88E6XXX_FAMILY_6390 */ 4779 .setup_errata = mv88e6390_setup_errata, 4780 .irl_init_all = mv88e6390_g2_irl_init_all, 4781 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4782 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4783 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4784 .phy_read = mv88e6xxx_g2_smi_phy_read, 4785 .phy_write = mv88e6xxx_g2_smi_phy_write, 4786 .port_set_link = mv88e6xxx_port_set_link, 4787 .port_sync_link = mv88e6xxx_port_sync_link, 4788 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4789 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4790 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4791 .port_tag_remap = mv88e6390_port_tag_remap, 4792 .port_set_policy = mv88e6352_port_set_policy, 4793 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4794 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4795 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4796 .port_set_ether_type = mv88e6351_port_set_ether_type, 4797 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4798 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4799 .port_pause_limit = mv88e6390_port_pause_limit, 4800 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4801 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4802 .port_get_cmode = mv88e6352_port_get_cmode, 4803 .port_set_cmode = mv88e6390_port_set_cmode, 4804 .port_setup_message_port = mv88e6xxx_setup_message_port, 4805 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4806 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4807 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4808 .stats_get_strings = mv88e6320_stats_get_strings, 4809 .stats_get_stats = mv88e6390_stats_get_stats, 4810 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4811 .set_egress_port = mv88e6390_g1_set_egress_port, 4812 .watchdog_ops = &mv88e6390_watchdog_ops, 4813 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4814 .pot_clear = mv88e6xxx_g2_pot_clear, 4815 .reset = mv88e6352_g1_reset, 4816 .rmu_disable = mv88e6390_g1_rmu_disable, 4817 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4818 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4819 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4820 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4821 .serdes_power = mv88e6390_serdes_power, 4822 .serdes_get_lane = mv88e6390_serdes_get_lane, 4823 /* Check status register pause & lpa register */ 4824 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4825 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4826 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4827 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4828 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4829 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4830 .serdes_irq_status = mv88e6390_serdes_irq_status, 4831 .gpio_ops = &mv88e6352_gpio_ops, 4832 .avb_ops = &mv88e6390_avb_ops, 4833 .ptp_ops = &mv88e6352_ptp_ops, 4834 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4835 .serdes_get_strings = mv88e6390_serdes_get_strings, 4836 .serdes_get_stats = mv88e6390_serdes_get_stats, 4837 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4838 .serdes_get_regs = mv88e6390_serdes_get_regs, 4839 .phylink_validate = mv88e6390_phylink_validate, 4840 }; 4841 4842 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4843 /* MV88E6XXX_FAMILY_6390 */ 4844 .setup_errata = mv88e6390_setup_errata, 4845 .irl_init_all = mv88e6390_g2_irl_init_all, 4846 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4847 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4848 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4849 .phy_read = mv88e6xxx_g2_smi_phy_read, 4850 .phy_write = mv88e6xxx_g2_smi_phy_write, 4851 .port_set_link = mv88e6xxx_port_set_link, 4852 .port_sync_link = mv88e6xxx_port_sync_link, 4853 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4854 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4855 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4856 .port_tag_remap = mv88e6390_port_tag_remap, 4857 .port_set_policy = mv88e6352_port_set_policy, 4858 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4859 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4860 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4861 .port_set_ether_type = mv88e6351_port_set_ether_type, 4862 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4863 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4864 .port_pause_limit = mv88e6390_port_pause_limit, 4865 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4866 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4867 .port_get_cmode = mv88e6352_port_get_cmode, 4868 .port_set_cmode = mv88e6390x_port_set_cmode, 4869 .port_setup_message_port = mv88e6xxx_setup_message_port, 4870 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4871 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4872 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4873 .stats_get_strings = mv88e6320_stats_get_strings, 4874 .stats_get_stats = mv88e6390_stats_get_stats, 4875 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4876 .set_egress_port = mv88e6390_g1_set_egress_port, 4877 .watchdog_ops = &mv88e6390_watchdog_ops, 4878 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4879 .pot_clear = mv88e6xxx_g2_pot_clear, 4880 .reset = mv88e6352_g1_reset, 4881 .rmu_disable = mv88e6390_g1_rmu_disable, 4882 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4883 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4884 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4885 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4886 .serdes_power = mv88e6390_serdes_power, 4887 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4888 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4889 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4890 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4891 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4892 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4893 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4894 .serdes_irq_status = mv88e6390_serdes_irq_status, 4895 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4896 .serdes_get_strings = mv88e6390_serdes_get_strings, 4897 .serdes_get_stats = mv88e6390_serdes_get_stats, 4898 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4899 .serdes_get_regs = mv88e6390_serdes_get_regs, 4900 .gpio_ops = &mv88e6352_gpio_ops, 4901 .avb_ops = &mv88e6390_avb_ops, 4902 .ptp_ops = &mv88e6352_ptp_ops, 4903 .phylink_validate = mv88e6390x_phylink_validate, 4904 }; 4905 4906 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4907 /* MV88E6XXX_FAMILY_6393 */ 4908 .setup_errata = mv88e6393x_serdes_setup_errata, 4909 .irl_init_all = mv88e6390_g2_irl_init_all, 4910 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4911 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4912 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4913 .phy_read = mv88e6xxx_g2_smi_phy_read, 4914 .phy_write = mv88e6xxx_g2_smi_phy_write, 4915 .port_set_link = mv88e6xxx_port_set_link, 4916 .port_sync_link = mv88e6xxx_port_sync_link, 4917 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4918 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4919 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4920 .port_tag_remap = mv88e6390_port_tag_remap, 4921 .port_set_policy = mv88e6393x_port_set_policy, 4922 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4923 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4924 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4925 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4926 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4927 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4928 .port_pause_limit = mv88e6390_port_pause_limit, 4929 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4930 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4931 .port_get_cmode = mv88e6352_port_get_cmode, 4932 .port_set_cmode = mv88e6393x_port_set_cmode, 4933 .port_setup_message_port = mv88e6xxx_setup_message_port, 4934 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4935 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4936 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4937 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4938 .stats_get_strings = mv88e6320_stats_get_strings, 4939 .stats_get_stats = mv88e6390_stats_get_stats, 4940 /* .set_cpu_port is missing because this family does not support a global 4941 * CPU port, only per port CPU port which is set via 4942 * .port_set_upstream_port method. 4943 */ 4944 .set_egress_port = mv88e6393x_set_egress_port, 4945 .watchdog_ops = &mv88e6390_watchdog_ops, 4946 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4947 .pot_clear = mv88e6xxx_g2_pot_clear, 4948 .reset = mv88e6352_g1_reset, 4949 .rmu_disable = mv88e6390_g1_rmu_disable, 4950 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4951 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4952 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4953 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4954 .serdes_power = mv88e6393x_serdes_power, 4955 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4956 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4957 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4958 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4959 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4960 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4961 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4962 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4963 /* TODO: serdes stats */ 4964 .gpio_ops = &mv88e6352_gpio_ops, 4965 .avb_ops = &mv88e6390_avb_ops, 4966 .ptp_ops = &mv88e6352_ptp_ops, 4967 .phylink_validate = mv88e6393x_phylink_validate, 4968 }; 4969 4970 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4971 [MV88E6085] = { 4972 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4973 .family = MV88E6XXX_FAMILY_6097, 4974 .name = "Marvell 88E6085", 4975 .num_databases = 4096, 4976 .num_macs = 8192, 4977 .num_ports = 10, 4978 .num_internal_phys = 5, 4979 .max_vid = 4095, 4980 .port_base_addr = 0x10, 4981 .phy_base_addr = 0x0, 4982 .global1_addr = 0x1b, 4983 .global2_addr = 0x1c, 4984 .age_time_coeff = 15000, 4985 .g1_irqs = 8, 4986 .g2_irqs = 10, 4987 .atu_move_port_mask = 0xf, 4988 .pvt = true, 4989 .multi_chip = true, 4990 .ops = &mv88e6085_ops, 4991 }, 4992 4993 [MV88E6095] = { 4994 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4995 .family = MV88E6XXX_FAMILY_6095, 4996 .name = "Marvell 88E6095/88E6095F", 4997 .num_databases = 256, 4998 .num_macs = 8192, 4999 .num_ports = 11, 5000 .num_internal_phys = 0, 5001 .max_vid = 4095, 5002 .port_base_addr = 0x10, 5003 .phy_base_addr = 0x0, 5004 .global1_addr = 0x1b, 5005 .global2_addr = 0x1c, 5006 .age_time_coeff = 15000, 5007 .g1_irqs = 8, 5008 .atu_move_port_mask = 0xf, 5009 .multi_chip = true, 5010 .ops = &mv88e6095_ops, 5011 }, 5012 5013 [MV88E6097] = { 5014 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5015 .family = MV88E6XXX_FAMILY_6097, 5016 .name = "Marvell 88E6097/88E6097F", 5017 .num_databases = 4096, 5018 .num_macs = 8192, 5019 .num_ports = 11, 5020 .num_internal_phys = 8, 5021 .max_vid = 4095, 5022 .port_base_addr = 0x10, 5023 .phy_base_addr = 0x0, 5024 .global1_addr = 0x1b, 5025 .global2_addr = 0x1c, 5026 .age_time_coeff = 15000, 5027 .g1_irqs = 8, 5028 .g2_irqs = 10, 5029 .atu_move_port_mask = 0xf, 5030 .pvt = true, 5031 .multi_chip = true, 5032 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5033 .ops = &mv88e6097_ops, 5034 }, 5035 5036 [MV88E6123] = { 5037 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5038 .family = MV88E6XXX_FAMILY_6165, 5039 .name = "Marvell 88E6123", 5040 .num_databases = 4096, 5041 .num_macs = 1024, 5042 .num_ports = 3, 5043 .num_internal_phys = 5, 5044 .max_vid = 4095, 5045 .port_base_addr = 0x10, 5046 .phy_base_addr = 0x0, 5047 .global1_addr = 0x1b, 5048 .global2_addr = 0x1c, 5049 .age_time_coeff = 15000, 5050 .g1_irqs = 9, 5051 .g2_irqs = 10, 5052 .atu_move_port_mask = 0xf, 5053 .pvt = true, 5054 .multi_chip = true, 5055 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5056 .ops = &mv88e6123_ops, 5057 }, 5058 5059 [MV88E6131] = { 5060 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5061 .family = MV88E6XXX_FAMILY_6185, 5062 .name = "Marvell 88E6131", 5063 .num_databases = 256, 5064 .num_macs = 8192, 5065 .num_ports = 8, 5066 .num_internal_phys = 0, 5067 .max_vid = 4095, 5068 .port_base_addr = 0x10, 5069 .phy_base_addr = 0x0, 5070 .global1_addr = 0x1b, 5071 .global2_addr = 0x1c, 5072 .age_time_coeff = 15000, 5073 .g1_irqs = 9, 5074 .atu_move_port_mask = 0xf, 5075 .multi_chip = true, 5076 .ops = &mv88e6131_ops, 5077 }, 5078 5079 [MV88E6141] = { 5080 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5081 .family = MV88E6XXX_FAMILY_6341, 5082 .name = "Marvell 88E6141", 5083 .num_databases = 4096, 5084 .num_macs = 2048, 5085 .num_ports = 6, 5086 .num_internal_phys = 5, 5087 .num_gpio = 11, 5088 .max_vid = 4095, 5089 .port_base_addr = 0x10, 5090 .phy_base_addr = 0x10, 5091 .global1_addr = 0x1b, 5092 .global2_addr = 0x1c, 5093 .age_time_coeff = 3750, 5094 .atu_move_port_mask = 0x1f, 5095 .g1_irqs = 9, 5096 .g2_irqs = 10, 5097 .pvt = true, 5098 .multi_chip = true, 5099 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5100 .ops = &mv88e6141_ops, 5101 }, 5102 5103 [MV88E6161] = { 5104 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5105 .family = MV88E6XXX_FAMILY_6165, 5106 .name = "Marvell 88E6161", 5107 .num_databases = 4096, 5108 .num_macs = 1024, 5109 .num_ports = 6, 5110 .num_internal_phys = 5, 5111 .max_vid = 4095, 5112 .port_base_addr = 0x10, 5113 .phy_base_addr = 0x0, 5114 .global1_addr = 0x1b, 5115 .global2_addr = 0x1c, 5116 .age_time_coeff = 15000, 5117 .g1_irqs = 9, 5118 .g2_irqs = 10, 5119 .atu_move_port_mask = 0xf, 5120 .pvt = true, 5121 .multi_chip = true, 5122 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5123 .ptp_support = true, 5124 .ops = &mv88e6161_ops, 5125 }, 5126 5127 [MV88E6165] = { 5128 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5129 .family = MV88E6XXX_FAMILY_6165, 5130 .name = "Marvell 88E6165", 5131 .num_databases = 4096, 5132 .num_macs = 8192, 5133 .num_ports = 6, 5134 .num_internal_phys = 0, 5135 .max_vid = 4095, 5136 .port_base_addr = 0x10, 5137 .phy_base_addr = 0x0, 5138 .global1_addr = 0x1b, 5139 .global2_addr = 0x1c, 5140 .age_time_coeff = 15000, 5141 .g1_irqs = 9, 5142 .g2_irqs = 10, 5143 .atu_move_port_mask = 0xf, 5144 .pvt = true, 5145 .multi_chip = true, 5146 .ptp_support = true, 5147 .ops = &mv88e6165_ops, 5148 }, 5149 5150 [MV88E6171] = { 5151 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5152 .family = MV88E6XXX_FAMILY_6351, 5153 .name = "Marvell 88E6171", 5154 .num_databases = 4096, 5155 .num_macs = 8192, 5156 .num_ports = 7, 5157 .num_internal_phys = 5, 5158 .max_vid = 4095, 5159 .port_base_addr = 0x10, 5160 .phy_base_addr = 0x0, 5161 .global1_addr = 0x1b, 5162 .global2_addr = 0x1c, 5163 .age_time_coeff = 15000, 5164 .g1_irqs = 9, 5165 .g2_irqs = 10, 5166 .atu_move_port_mask = 0xf, 5167 .pvt = true, 5168 .multi_chip = true, 5169 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5170 .ops = &mv88e6171_ops, 5171 }, 5172 5173 [MV88E6172] = { 5174 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5175 .family = MV88E6XXX_FAMILY_6352, 5176 .name = "Marvell 88E6172", 5177 .num_databases = 4096, 5178 .num_macs = 8192, 5179 .num_ports = 7, 5180 .num_internal_phys = 5, 5181 .num_gpio = 15, 5182 .max_vid = 4095, 5183 .port_base_addr = 0x10, 5184 .phy_base_addr = 0x0, 5185 .global1_addr = 0x1b, 5186 .global2_addr = 0x1c, 5187 .age_time_coeff = 15000, 5188 .g1_irqs = 9, 5189 .g2_irqs = 10, 5190 .atu_move_port_mask = 0xf, 5191 .pvt = true, 5192 .multi_chip = true, 5193 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5194 .ops = &mv88e6172_ops, 5195 }, 5196 5197 [MV88E6175] = { 5198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5199 .family = MV88E6XXX_FAMILY_6351, 5200 .name = "Marvell 88E6175", 5201 .num_databases = 4096, 5202 .num_macs = 8192, 5203 .num_ports = 7, 5204 .num_internal_phys = 5, 5205 .max_vid = 4095, 5206 .port_base_addr = 0x10, 5207 .phy_base_addr = 0x0, 5208 .global1_addr = 0x1b, 5209 .global2_addr = 0x1c, 5210 .age_time_coeff = 15000, 5211 .g1_irqs = 9, 5212 .g2_irqs = 10, 5213 .atu_move_port_mask = 0xf, 5214 .pvt = true, 5215 .multi_chip = true, 5216 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5217 .ops = &mv88e6175_ops, 5218 }, 5219 5220 [MV88E6176] = { 5221 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5222 .family = MV88E6XXX_FAMILY_6352, 5223 .name = "Marvell 88E6176", 5224 .num_databases = 4096, 5225 .num_macs = 8192, 5226 .num_ports = 7, 5227 .num_internal_phys = 5, 5228 .num_gpio = 15, 5229 .max_vid = 4095, 5230 .port_base_addr = 0x10, 5231 .phy_base_addr = 0x0, 5232 .global1_addr = 0x1b, 5233 .global2_addr = 0x1c, 5234 .age_time_coeff = 15000, 5235 .g1_irqs = 9, 5236 .g2_irqs = 10, 5237 .atu_move_port_mask = 0xf, 5238 .pvt = true, 5239 .multi_chip = true, 5240 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5241 .ops = &mv88e6176_ops, 5242 }, 5243 5244 [MV88E6185] = { 5245 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5246 .family = MV88E6XXX_FAMILY_6185, 5247 .name = "Marvell 88E6185", 5248 .num_databases = 256, 5249 .num_macs = 8192, 5250 .num_ports = 10, 5251 .num_internal_phys = 0, 5252 .max_vid = 4095, 5253 .port_base_addr = 0x10, 5254 .phy_base_addr = 0x0, 5255 .global1_addr = 0x1b, 5256 .global2_addr = 0x1c, 5257 .age_time_coeff = 15000, 5258 .g1_irqs = 8, 5259 .atu_move_port_mask = 0xf, 5260 .multi_chip = true, 5261 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5262 .ops = &mv88e6185_ops, 5263 }, 5264 5265 [MV88E6190] = { 5266 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5267 .family = MV88E6XXX_FAMILY_6390, 5268 .name = "Marvell 88E6190", 5269 .num_databases = 4096, 5270 .num_macs = 16384, 5271 .num_ports = 11, /* 10 + Z80 */ 5272 .num_internal_phys = 9, 5273 .num_gpio = 16, 5274 .max_vid = 8191, 5275 .port_base_addr = 0x0, 5276 .phy_base_addr = 0x0, 5277 .global1_addr = 0x1b, 5278 .global2_addr = 0x1c, 5279 .age_time_coeff = 3750, 5280 .g1_irqs = 9, 5281 .g2_irqs = 14, 5282 .pvt = true, 5283 .multi_chip = true, 5284 .atu_move_port_mask = 0x1f, 5285 .ops = &mv88e6190_ops, 5286 }, 5287 5288 [MV88E6190X] = { 5289 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5290 .family = MV88E6XXX_FAMILY_6390, 5291 .name = "Marvell 88E6190X", 5292 .num_databases = 4096, 5293 .num_macs = 16384, 5294 .num_ports = 11, /* 10 + Z80 */ 5295 .num_internal_phys = 9, 5296 .num_gpio = 16, 5297 .max_vid = 8191, 5298 .port_base_addr = 0x0, 5299 .phy_base_addr = 0x0, 5300 .global1_addr = 0x1b, 5301 .global2_addr = 0x1c, 5302 .age_time_coeff = 3750, 5303 .g1_irqs = 9, 5304 .g2_irqs = 14, 5305 .atu_move_port_mask = 0x1f, 5306 .pvt = true, 5307 .multi_chip = true, 5308 .ops = &mv88e6190x_ops, 5309 }, 5310 5311 [MV88E6191] = { 5312 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5313 .family = MV88E6XXX_FAMILY_6390, 5314 .name = "Marvell 88E6191", 5315 .num_databases = 4096, 5316 .num_macs = 16384, 5317 .num_ports = 11, /* 10 + Z80 */ 5318 .num_internal_phys = 9, 5319 .max_vid = 8191, 5320 .port_base_addr = 0x0, 5321 .phy_base_addr = 0x0, 5322 .global1_addr = 0x1b, 5323 .global2_addr = 0x1c, 5324 .age_time_coeff = 3750, 5325 .g1_irqs = 9, 5326 .g2_irqs = 14, 5327 .atu_move_port_mask = 0x1f, 5328 .pvt = true, 5329 .multi_chip = true, 5330 .ptp_support = true, 5331 .ops = &mv88e6191_ops, 5332 }, 5333 5334 [MV88E6191X] = { 5335 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5336 .family = MV88E6XXX_FAMILY_6393, 5337 .name = "Marvell 88E6191X", 5338 .num_databases = 4096, 5339 .num_ports = 11, /* 10 + Z80 */ 5340 .num_internal_phys = 9, 5341 .max_vid = 8191, 5342 .port_base_addr = 0x0, 5343 .phy_base_addr = 0x0, 5344 .global1_addr = 0x1b, 5345 .global2_addr = 0x1c, 5346 .age_time_coeff = 3750, 5347 .g1_irqs = 10, 5348 .g2_irqs = 14, 5349 .atu_move_port_mask = 0x1f, 5350 .pvt = true, 5351 .multi_chip = true, 5352 .ptp_support = true, 5353 .ops = &mv88e6393x_ops, 5354 }, 5355 5356 [MV88E6193X] = { 5357 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5358 .family = MV88E6XXX_FAMILY_6393, 5359 .name = "Marvell 88E6193X", 5360 .num_databases = 4096, 5361 .num_ports = 11, /* 10 + Z80 */ 5362 .num_internal_phys = 9, 5363 .max_vid = 8191, 5364 .port_base_addr = 0x0, 5365 .phy_base_addr = 0x0, 5366 .global1_addr = 0x1b, 5367 .global2_addr = 0x1c, 5368 .age_time_coeff = 3750, 5369 .g1_irqs = 10, 5370 .g2_irqs = 14, 5371 .atu_move_port_mask = 0x1f, 5372 .pvt = true, 5373 .multi_chip = true, 5374 .ptp_support = true, 5375 .ops = &mv88e6393x_ops, 5376 }, 5377 5378 [MV88E6220] = { 5379 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5380 .family = MV88E6XXX_FAMILY_6250, 5381 .name = "Marvell 88E6220", 5382 .num_databases = 64, 5383 5384 /* Ports 2-4 are not routed to pins 5385 * => usable ports 0, 1, 5, 6 5386 */ 5387 .num_ports = 7, 5388 .num_internal_phys = 2, 5389 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5390 .max_vid = 4095, 5391 .port_base_addr = 0x08, 5392 .phy_base_addr = 0x00, 5393 .global1_addr = 0x0f, 5394 .global2_addr = 0x07, 5395 .age_time_coeff = 15000, 5396 .g1_irqs = 9, 5397 .g2_irqs = 10, 5398 .atu_move_port_mask = 0xf, 5399 .dual_chip = true, 5400 .ptp_support = true, 5401 .ops = &mv88e6250_ops, 5402 }, 5403 5404 [MV88E6240] = { 5405 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5406 .family = MV88E6XXX_FAMILY_6352, 5407 .name = "Marvell 88E6240", 5408 .num_databases = 4096, 5409 .num_macs = 8192, 5410 .num_ports = 7, 5411 .num_internal_phys = 5, 5412 .num_gpio = 15, 5413 .max_vid = 4095, 5414 .port_base_addr = 0x10, 5415 .phy_base_addr = 0x0, 5416 .global1_addr = 0x1b, 5417 .global2_addr = 0x1c, 5418 .age_time_coeff = 15000, 5419 .g1_irqs = 9, 5420 .g2_irqs = 10, 5421 .atu_move_port_mask = 0xf, 5422 .pvt = true, 5423 .multi_chip = true, 5424 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5425 .ptp_support = true, 5426 .ops = &mv88e6240_ops, 5427 }, 5428 5429 [MV88E6250] = { 5430 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5431 .family = MV88E6XXX_FAMILY_6250, 5432 .name = "Marvell 88E6250", 5433 .num_databases = 64, 5434 .num_ports = 7, 5435 .num_internal_phys = 5, 5436 .max_vid = 4095, 5437 .port_base_addr = 0x08, 5438 .phy_base_addr = 0x00, 5439 .global1_addr = 0x0f, 5440 .global2_addr = 0x07, 5441 .age_time_coeff = 15000, 5442 .g1_irqs = 9, 5443 .g2_irqs = 10, 5444 .atu_move_port_mask = 0xf, 5445 .dual_chip = true, 5446 .ptp_support = true, 5447 .ops = &mv88e6250_ops, 5448 }, 5449 5450 [MV88E6290] = { 5451 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5452 .family = MV88E6XXX_FAMILY_6390, 5453 .name = "Marvell 88E6290", 5454 .num_databases = 4096, 5455 .num_ports = 11, /* 10 + Z80 */ 5456 .num_internal_phys = 9, 5457 .num_gpio = 16, 5458 .max_vid = 8191, 5459 .port_base_addr = 0x0, 5460 .phy_base_addr = 0x0, 5461 .global1_addr = 0x1b, 5462 .global2_addr = 0x1c, 5463 .age_time_coeff = 3750, 5464 .g1_irqs = 9, 5465 .g2_irqs = 14, 5466 .atu_move_port_mask = 0x1f, 5467 .pvt = true, 5468 .multi_chip = true, 5469 .ptp_support = true, 5470 .ops = &mv88e6290_ops, 5471 }, 5472 5473 [MV88E6320] = { 5474 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5475 .family = MV88E6XXX_FAMILY_6320, 5476 .name = "Marvell 88E6320", 5477 .num_databases = 4096, 5478 .num_macs = 8192, 5479 .num_ports = 7, 5480 .num_internal_phys = 5, 5481 .num_gpio = 15, 5482 .max_vid = 4095, 5483 .port_base_addr = 0x10, 5484 .phy_base_addr = 0x0, 5485 .global1_addr = 0x1b, 5486 .global2_addr = 0x1c, 5487 .age_time_coeff = 15000, 5488 .g1_irqs = 8, 5489 .g2_irqs = 10, 5490 .atu_move_port_mask = 0xf, 5491 .pvt = true, 5492 .multi_chip = true, 5493 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5494 .ptp_support = true, 5495 .ops = &mv88e6320_ops, 5496 }, 5497 5498 [MV88E6321] = { 5499 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5500 .family = MV88E6XXX_FAMILY_6320, 5501 .name = "Marvell 88E6321", 5502 .num_databases = 4096, 5503 .num_macs = 8192, 5504 .num_ports = 7, 5505 .num_internal_phys = 5, 5506 .num_gpio = 15, 5507 .max_vid = 4095, 5508 .port_base_addr = 0x10, 5509 .phy_base_addr = 0x0, 5510 .global1_addr = 0x1b, 5511 .global2_addr = 0x1c, 5512 .age_time_coeff = 15000, 5513 .g1_irqs = 8, 5514 .g2_irqs = 10, 5515 .atu_move_port_mask = 0xf, 5516 .multi_chip = true, 5517 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5518 .ptp_support = true, 5519 .ops = &mv88e6321_ops, 5520 }, 5521 5522 [MV88E6341] = { 5523 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5524 .family = MV88E6XXX_FAMILY_6341, 5525 .name = "Marvell 88E6341", 5526 .num_databases = 4096, 5527 .num_macs = 2048, 5528 .num_internal_phys = 5, 5529 .num_ports = 6, 5530 .num_gpio = 11, 5531 .max_vid = 4095, 5532 .port_base_addr = 0x10, 5533 .phy_base_addr = 0x10, 5534 .global1_addr = 0x1b, 5535 .global2_addr = 0x1c, 5536 .age_time_coeff = 3750, 5537 .atu_move_port_mask = 0x1f, 5538 .g1_irqs = 9, 5539 .g2_irqs = 10, 5540 .pvt = true, 5541 .multi_chip = true, 5542 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5543 .ptp_support = true, 5544 .ops = &mv88e6341_ops, 5545 }, 5546 5547 [MV88E6350] = { 5548 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5549 .family = MV88E6XXX_FAMILY_6351, 5550 .name = "Marvell 88E6350", 5551 .num_databases = 4096, 5552 .num_macs = 8192, 5553 .num_ports = 7, 5554 .num_internal_phys = 5, 5555 .max_vid = 4095, 5556 .port_base_addr = 0x10, 5557 .phy_base_addr = 0x0, 5558 .global1_addr = 0x1b, 5559 .global2_addr = 0x1c, 5560 .age_time_coeff = 15000, 5561 .g1_irqs = 9, 5562 .g2_irqs = 10, 5563 .atu_move_port_mask = 0xf, 5564 .pvt = true, 5565 .multi_chip = true, 5566 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5567 .ops = &mv88e6350_ops, 5568 }, 5569 5570 [MV88E6351] = { 5571 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5572 .family = MV88E6XXX_FAMILY_6351, 5573 .name = "Marvell 88E6351", 5574 .num_databases = 4096, 5575 .num_macs = 8192, 5576 .num_ports = 7, 5577 .num_internal_phys = 5, 5578 .max_vid = 4095, 5579 .port_base_addr = 0x10, 5580 .phy_base_addr = 0x0, 5581 .global1_addr = 0x1b, 5582 .global2_addr = 0x1c, 5583 .age_time_coeff = 15000, 5584 .g1_irqs = 9, 5585 .g2_irqs = 10, 5586 .atu_move_port_mask = 0xf, 5587 .pvt = true, 5588 .multi_chip = true, 5589 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5590 .ops = &mv88e6351_ops, 5591 }, 5592 5593 [MV88E6352] = { 5594 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5595 .family = MV88E6XXX_FAMILY_6352, 5596 .name = "Marvell 88E6352", 5597 .num_databases = 4096, 5598 .num_macs = 8192, 5599 .num_ports = 7, 5600 .num_internal_phys = 5, 5601 .num_gpio = 15, 5602 .max_vid = 4095, 5603 .port_base_addr = 0x10, 5604 .phy_base_addr = 0x0, 5605 .global1_addr = 0x1b, 5606 .global2_addr = 0x1c, 5607 .age_time_coeff = 15000, 5608 .g1_irqs = 9, 5609 .g2_irqs = 10, 5610 .atu_move_port_mask = 0xf, 5611 .pvt = true, 5612 .multi_chip = true, 5613 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5614 .ptp_support = true, 5615 .ops = &mv88e6352_ops, 5616 }, 5617 [MV88E6390] = { 5618 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5619 .family = MV88E6XXX_FAMILY_6390, 5620 .name = "Marvell 88E6390", 5621 .num_databases = 4096, 5622 .num_macs = 16384, 5623 .num_ports = 11, /* 10 + Z80 */ 5624 .num_internal_phys = 9, 5625 .num_gpio = 16, 5626 .max_vid = 8191, 5627 .port_base_addr = 0x0, 5628 .phy_base_addr = 0x0, 5629 .global1_addr = 0x1b, 5630 .global2_addr = 0x1c, 5631 .age_time_coeff = 3750, 5632 .g1_irqs = 9, 5633 .g2_irqs = 14, 5634 .atu_move_port_mask = 0x1f, 5635 .pvt = true, 5636 .multi_chip = true, 5637 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5638 .ptp_support = true, 5639 .ops = &mv88e6390_ops, 5640 }, 5641 [MV88E6390X] = { 5642 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5643 .family = MV88E6XXX_FAMILY_6390, 5644 .name = "Marvell 88E6390X", 5645 .num_databases = 4096, 5646 .num_macs = 16384, 5647 .num_ports = 11, /* 10 + Z80 */ 5648 .num_internal_phys = 9, 5649 .num_gpio = 16, 5650 .max_vid = 8191, 5651 .port_base_addr = 0x0, 5652 .phy_base_addr = 0x0, 5653 .global1_addr = 0x1b, 5654 .global2_addr = 0x1c, 5655 .age_time_coeff = 3750, 5656 .g1_irqs = 9, 5657 .g2_irqs = 14, 5658 .atu_move_port_mask = 0x1f, 5659 .pvt = true, 5660 .multi_chip = true, 5661 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5662 .ptp_support = true, 5663 .ops = &mv88e6390x_ops, 5664 }, 5665 5666 [MV88E6393X] = { 5667 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5668 .family = MV88E6XXX_FAMILY_6393, 5669 .name = "Marvell 88E6393X", 5670 .num_databases = 4096, 5671 .num_ports = 11, /* 10 + Z80 */ 5672 .num_internal_phys = 9, 5673 .max_vid = 8191, 5674 .port_base_addr = 0x0, 5675 .phy_base_addr = 0x0, 5676 .global1_addr = 0x1b, 5677 .global2_addr = 0x1c, 5678 .age_time_coeff = 3750, 5679 .g1_irqs = 10, 5680 .g2_irqs = 14, 5681 .atu_move_port_mask = 0x1f, 5682 .pvt = true, 5683 .multi_chip = true, 5684 .ptp_support = true, 5685 .ops = &mv88e6393x_ops, 5686 }, 5687 }; 5688 5689 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5690 { 5691 int i; 5692 5693 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5694 if (mv88e6xxx_table[i].prod_num == prod_num) 5695 return &mv88e6xxx_table[i]; 5696 5697 return NULL; 5698 } 5699 5700 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5701 { 5702 const struct mv88e6xxx_info *info; 5703 unsigned int prod_num, rev; 5704 u16 id; 5705 int err; 5706 5707 mv88e6xxx_reg_lock(chip); 5708 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5709 mv88e6xxx_reg_unlock(chip); 5710 if (err) 5711 return err; 5712 5713 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5714 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5715 5716 info = mv88e6xxx_lookup_info(prod_num); 5717 if (!info) 5718 return -ENODEV; 5719 5720 /* Update the compatible info with the probed one */ 5721 chip->info = info; 5722 5723 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5724 chip->info->prod_num, chip->info->name, rev); 5725 5726 return 0; 5727 } 5728 5729 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5730 { 5731 struct mv88e6xxx_chip *chip; 5732 5733 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5734 if (!chip) 5735 return NULL; 5736 5737 chip->dev = dev; 5738 5739 mutex_init(&chip->reg_lock); 5740 INIT_LIST_HEAD(&chip->mdios); 5741 idr_init(&chip->policies); 5742 5743 return chip; 5744 } 5745 5746 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5747 int port, 5748 enum dsa_tag_protocol m) 5749 { 5750 struct mv88e6xxx_chip *chip = ds->priv; 5751 5752 return chip->tag_protocol; 5753 } 5754 5755 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5756 enum dsa_tag_protocol proto) 5757 { 5758 struct mv88e6xxx_chip *chip = ds->priv; 5759 enum dsa_tag_protocol old_protocol; 5760 int err; 5761 5762 switch (proto) { 5763 case DSA_TAG_PROTO_EDSA: 5764 switch (chip->info->edsa_support) { 5765 case MV88E6XXX_EDSA_UNSUPPORTED: 5766 return -EPROTONOSUPPORT; 5767 case MV88E6XXX_EDSA_UNDOCUMENTED: 5768 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5769 fallthrough; 5770 case MV88E6XXX_EDSA_SUPPORTED: 5771 break; 5772 } 5773 break; 5774 case DSA_TAG_PROTO_DSA: 5775 break; 5776 default: 5777 return -EPROTONOSUPPORT; 5778 } 5779 5780 old_protocol = chip->tag_protocol; 5781 chip->tag_protocol = proto; 5782 5783 mv88e6xxx_reg_lock(chip); 5784 err = mv88e6xxx_setup_port_mode(chip, port); 5785 mv88e6xxx_reg_unlock(chip); 5786 5787 if (err) 5788 chip->tag_protocol = old_protocol; 5789 5790 return err; 5791 } 5792 5793 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5794 const struct switchdev_obj_port_mdb *mdb) 5795 { 5796 struct mv88e6xxx_chip *chip = ds->priv; 5797 int err; 5798 5799 mv88e6xxx_reg_lock(chip); 5800 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5801 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5802 mv88e6xxx_reg_unlock(chip); 5803 5804 return err; 5805 } 5806 5807 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5808 const struct switchdev_obj_port_mdb *mdb) 5809 { 5810 struct mv88e6xxx_chip *chip = ds->priv; 5811 int err; 5812 5813 mv88e6xxx_reg_lock(chip); 5814 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5815 mv88e6xxx_reg_unlock(chip); 5816 5817 return err; 5818 } 5819 5820 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5821 struct dsa_mall_mirror_tc_entry *mirror, 5822 bool ingress) 5823 { 5824 enum mv88e6xxx_egress_direction direction = ingress ? 5825 MV88E6XXX_EGRESS_DIR_INGRESS : 5826 MV88E6XXX_EGRESS_DIR_EGRESS; 5827 struct mv88e6xxx_chip *chip = ds->priv; 5828 bool other_mirrors = false; 5829 int i; 5830 int err; 5831 5832 mutex_lock(&chip->reg_lock); 5833 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5834 mirror->to_local_port) { 5835 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5836 other_mirrors |= ingress ? 5837 chip->ports[i].mirror_ingress : 5838 chip->ports[i].mirror_egress; 5839 5840 /* Can't change egress port when other mirror is active */ 5841 if (other_mirrors) { 5842 err = -EBUSY; 5843 goto out; 5844 } 5845 5846 err = mv88e6xxx_set_egress_port(chip, direction, 5847 mirror->to_local_port); 5848 if (err) 5849 goto out; 5850 } 5851 5852 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5853 out: 5854 mutex_unlock(&chip->reg_lock); 5855 5856 return err; 5857 } 5858 5859 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5860 struct dsa_mall_mirror_tc_entry *mirror) 5861 { 5862 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5863 MV88E6XXX_EGRESS_DIR_INGRESS : 5864 MV88E6XXX_EGRESS_DIR_EGRESS; 5865 struct mv88e6xxx_chip *chip = ds->priv; 5866 bool other_mirrors = false; 5867 int i; 5868 5869 mutex_lock(&chip->reg_lock); 5870 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5871 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5872 5873 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5874 other_mirrors |= mirror->ingress ? 5875 chip->ports[i].mirror_ingress : 5876 chip->ports[i].mirror_egress; 5877 5878 /* Reset egress port when no other mirror is active */ 5879 if (!other_mirrors) { 5880 if (mv88e6xxx_set_egress_port(chip, direction, 5881 dsa_upstream_port(ds, port))) 5882 dev_err(ds->dev, "failed to set egress port\n"); 5883 } 5884 5885 mutex_unlock(&chip->reg_lock); 5886 } 5887 5888 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5889 struct switchdev_brport_flags flags, 5890 struct netlink_ext_ack *extack) 5891 { 5892 struct mv88e6xxx_chip *chip = ds->priv; 5893 const struct mv88e6xxx_ops *ops; 5894 5895 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5896 BR_BCAST_FLOOD)) 5897 return -EINVAL; 5898 5899 ops = chip->info->ops; 5900 5901 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5902 return -EINVAL; 5903 5904 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5905 return -EINVAL; 5906 5907 return 0; 5908 } 5909 5910 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5911 struct switchdev_brport_flags flags, 5912 struct netlink_ext_ack *extack) 5913 { 5914 struct mv88e6xxx_chip *chip = ds->priv; 5915 int err = -EOPNOTSUPP; 5916 5917 mv88e6xxx_reg_lock(chip); 5918 5919 if (flags.mask & BR_LEARNING) { 5920 bool learning = !!(flags.val & BR_LEARNING); 5921 u16 pav = learning ? (1 << port) : 0; 5922 5923 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5924 if (err) 5925 goto out; 5926 } 5927 5928 if (flags.mask & BR_FLOOD) { 5929 bool unicast = !!(flags.val & BR_FLOOD); 5930 5931 err = chip->info->ops->port_set_ucast_flood(chip, port, 5932 unicast); 5933 if (err) 5934 goto out; 5935 } 5936 5937 if (flags.mask & BR_MCAST_FLOOD) { 5938 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5939 5940 err = chip->info->ops->port_set_mcast_flood(chip, port, 5941 multicast); 5942 if (err) 5943 goto out; 5944 } 5945 5946 if (flags.mask & BR_BCAST_FLOOD) { 5947 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5948 5949 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5950 if (err) 5951 goto out; 5952 } 5953 5954 out: 5955 mv88e6xxx_reg_unlock(chip); 5956 5957 return err; 5958 } 5959 5960 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5961 struct net_device *lag, 5962 struct netdev_lag_upper_info *info) 5963 { 5964 struct mv88e6xxx_chip *chip = ds->priv; 5965 struct dsa_port *dp; 5966 int id, members = 0; 5967 5968 if (!mv88e6xxx_has_lag(chip)) 5969 return false; 5970 5971 id = dsa_lag_id(ds->dst, lag); 5972 if (id < 0 || id >= ds->num_lag_ids) 5973 return false; 5974 5975 dsa_lag_foreach_port(dp, ds->dst, lag) 5976 /* Includes the port joining the LAG */ 5977 members++; 5978 5979 if (members > 8) 5980 return false; 5981 5982 /* We could potentially relax this to include active 5983 * backup in the future. 5984 */ 5985 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5986 return false; 5987 5988 /* Ideally we would also validate that the hash type matches 5989 * the hardware. Alas, this is always set to unknown on team 5990 * interfaces. 5991 */ 5992 return true; 5993 } 5994 5995 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 5996 { 5997 struct mv88e6xxx_chip *chip = ds->priv; 5998 struct dsa_port *dp; 5999 u16 map = 0; 6000 int id; 6001 6002 id = dsa_lag_id(ds->dst, lag); 6003 6004 /* Build the map of all ports to distribute flows destined for 6005 * this LAG. This can be either a local user port, or a DSA 6006 * port if the LAG port is on a remote chip. 6007 */ 6008 dsa_lag_foreach_port(dp, ds->dst, lag) 6009 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6010 6011 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6012 } 6013 6014 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6015 /* Row number corresponds to the number of active members in a 6016 * LAG. Each column states which of the eight hash buckets are 6017 * mapped to the column:th port in the LAG. 6018 * 6019 * Example: In a LAG with three active ports, the second port 6020 * ([2][1]) would be selected for traffic mapped to buckets 6021 * 3,4,5 (0x38). 6022 */ 6023 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6024 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6025 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6026 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6027 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6028 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6029 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6030 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6031 }; 6032 6033 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6034 int num_tx, int nth) 6035 { 6036 u8 active = 0; 6037 int i; 6038 6039 num_tx = num_tx <= 8 ? num_tx : 8; 6040 if (nth < num_tx) 6041 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6042 6043 for (i = 0; i < 8; i++) { 6044 if (BIT(i) & active) 6045 mask[i] |= BIT(port); 6046 } 6047 } 6048 6049 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6050 { 6051 struct mv88e6xxx_chip *chip = ds->priv; 6052 unsigned int id, num_tx; 6053 struct net_device *lag; 6054 struct dsa_port *dp; 6055 int i, err, nth; 6056 u16 mask[8]; 6057 u16 ivec; 6058 6059 /* Assume no port is a member of any LAG. */ 6060 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6061 6062 /* Disable all masks for ports that _are_ members of a LAG. */ 6063 list_for_each_entry(dp, &ds->dst->ports, list) { 6064 if (!dp->lag_dev || dp->ds != ds) 6065 continue; 6066 6067 ivec &= ~BIT(dp->index); 6068 } 6069 6070 for (i = 0; i < 8; i++) 6071 mask[i] = ivec; 6072 6073 /* Enable the correct subset of masks for all LAG ports that 6074 * are in the Tx set. 6075 */ 6076 dsa_lags_foreach_id(id, ds->dst) { 6077 lag = dsa_lag_dev(ds->dst, id); 6078 if (!lag) 6079 continue; 6080 6081 num_tx = 0; 6082 dsa_lag_foreach_port(dp, ds->dst, lag) { 6083 if (dp->lag_tx_enabled) 6084 num_tx++; 6085 } 6086 6087 if (!num_tx) 6088 continue; 6089 6090 nth = 0; 6091 dsa_lag_foreach_port(dp, ds->dst, lag) { 6092 if (!dp->lag_tx_enabled) 6093 continue; 6094 6095 if (dp->ds == ds) 6096 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6097 num_tx, nth); 6098 6099 nth++; 6100 } 6101 } 6102 6103 for (i = 0; i < 8; i++) { 6104 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6105 if (err) 6106 return err; 6107 } 6108 6109 return 0; 6110 } 6111 6112 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6113 struct net_device *lag) 6114 { 6115 int err; 6116 6117 err = mv88e6xxx_lag_sync_masks(ds); 6118 6119 if (!err) 6120 err = mv88e6xxx_lag_sync_map(ds, lag); 6121 6122 return err; 6123 } 6124 6125 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6126 { 6127 struct mv88e6xxx_chip *chip = ds->priv; 6128 int err; 6129 6130 mv88e6xxx_reg_lock(chip); 6131 err = mv88e6xxx_lag_sync_masks(ds); 6132 mv88e6xxx_reg_unlock(chip); 6133 return err; 6134 } 6135 6136 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6137 struct net_device *lag, 6138 struct netdev_lag_upper_info *info) 6139 { 6140 struct mv88e6xxx_chip *chip = ds->priv; 6141 int err, id; 6142 6143 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6144 return -EOPNOTSUPP; 6145 6146 id = dsa_lag_id(ds->dst, lag); 6147 6148 mv88e6xxx_reg_lock(chip); 6149 6150 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6151 if (err) 6152 goto err_unlock; 6153 6154 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6155 if (err) 6156 goto err_clear_trunk; 6157 6158 mv88e6xxx_reg_unlock(chip); 6159 return 0; 6160 6161 err_clear_trunk: 6162 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6163 err_unlock: 6164 mv88e6xxx_reg_unlock(chip); 6165 return err; 6166 } 6167 6168 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6169 struct net_device *lag) 6170 { 6171 struct mv88e6xxx_chip *chip = ds->priv; 6172 int err_sync, err_trunk; 6173 6174 mv88e6xxx_reg_lock(chip); 6175 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6176 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6177 mv88e6xxx_reg_unlock(chip); 6178 return err_sync ? : err_trunk; 6179 } 6180 6181 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6182 int port) 6183 { 6184 struct mv88e6xxx_chip *chip = ds->priv; 6185 int err; 6186 6187 mv88e6xxx_reg_lock(chip); 6188 err = mv88e6xxx_lag_sync_masks(ds); 6189 mv88e6xxx_reg_unlock(chip); 6190 return err; 6191 } 6192 6193 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6194 int port, struct net_device *lag, 6195 struct netdev_lag_upper_info *info) 6196 { 6197 struct mv88e6xxx_chip *chip = ds->priv; 6198 int err; 6199 6200 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6201 return -EOPNOTSUPP; 6202 6203 mv88e6xxx_reg_lock(chip); 6204 6205 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6206 if (err) 6207 goto unlock; 6208 6209 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6210 6211 unlock: 6212 mv88e6xxx_reg_unlock(chip); 6213 return err; 6214 } 6215 6216 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6217 int port, struct net_device *lag) 6218 { 6219 struct mv88e6xxx_chip *chip = ds->priv; 6220 int err_sync, err_pvt; 6221 6222 mv88e6xxx_reg_lock(chip); 6223 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6224 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6225 mv88e6xxx_reg_unlock(chip); 6226 return err_sync ? : err_pvt; 6227 } 6228 6229 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6230 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6231 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6232 .setup = mv88e6xxx_setup, 6233 .teardown = mv88e6xxx_teardown, 6234 .port_setup = mv88e6xxx_port_setup, 6235 .port_teardown = mv88e6xxx_port_teardown, 6236 .phylink_validate = mv88e6xxx_validate, 6237 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6238 .phylink_mac_config = mv88e6xxx_mac_config, 6239 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6240 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6241 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6242 .get_strings = mv88e6xxx_get_strings, 6243 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6244 .get_sset_count = mv88e6xxx_get_sset_count, 6245 .port_enable = mv88e6xxx_port_enable, 6246 .port_disable = mv88e6xxx_port_disable, 6247 .port_max_mtu = mv88e6xxx_get_max_mtu, 6248 .port_change_mtu = mv88e6xxx_change_mtu, 6249 .get_mac_eee = mv88e6xxx_get_mac_eee, 6250 .set_mac_eee = mv88e6xxx_set_mac_eee, 6251 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6252 .get_eeprom = mv88e6xxx_get_eeprom, 6253 .set_eeprom = mv88e6xxx_set_eeprom, 6254 .get_regs_len = mv88e6xxx_get_regs_len, 6255 .get_regs = mv88e6xxx_get_regs, 6256 .get_rxnfc = mv88e6xxx_get_rxnfc, 6257 .set_rxnfc = mv88e6xxx_set_rxnfc, 6258 .set_ageing_time = mv88e6xxx_set_ageing_time, 6259 .port_bridge_join = mv88e6xxx_port_bridge_join, 6260 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6261 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6262 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6263 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6264 .port_fast_age = mv88e6xxx_port_fast_age, 6265 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6266 .port_vlan_add = mv88e6xxx_port_vlan_add, 6267 .port_vlan_del = mv88e6xxx_port_vlan_del, 6268 .port_fdb_add = mv88e6xxx_port_fdb_add, 6269 .port_fdb_del = mv88e6xxx_port_fdb_del, 6270 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6271 .port_mdb_add = mv88e6xxx_port_mdb_add, 6272 .port_mdb_del = mv88e6xxx_port_mdb_del, 6273 .port_mirror_add = mv88e6xxx_port_mirror_add, 6274 .port_mirror_del = mv88e6xxx_port_mirror_del, 6275 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6276 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6277 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6278 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6279 .port_txtstamp = mv88e6xxx_port_txtstamp, 6280 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6281 .get_ts_info = mv88e6xxx_get_ts_info, 6282 .devlink_param_get = mv88e6xxx_devlink_param_get, 6283 .devlink_param_set = mv88e6xxx_devlink_param_set, 6284 .devlink_info_get = mv88e6xxx_devlink_info_get, 6285 .port_lag_change = mv88e6xxx_port_lag_change, 6286 .port_lag_join = mv88e6xxx_port_lag_join, 6287 .port_lag_leave = mv88e6xxx_port_lag_leave, 6288 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6289 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6290 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6291 }; 6292 6293 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6294 { 6295 struct device *dev = chip->dev; 6296 struct dsa_switch *ds; 6297 6298 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6299 if (!ds) 6300 return -ENOMEM; 6301 6302 ds->dev = dev; 6303 ds->num_ports = mv88e6xxx_num_ports(chip); 6304 ds->priv = chip; 6305 ds->dev = dev; 6306 ds->ops = &mv88e6xxx_switch_ops; 6307 ds->ageing_time_min = chip->info->age_time_coeff; 6308 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6309 6310 /* Some chips support up to 32, but that requires enabling the 6311 * 5-bit port mode, which we do not support. 640k^W16 ought to 6312 * be enough for anyone. 6313 */ 6314 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6315 6316 dev_set_drvdata(dev, ds); 6317 6318 return dsa_register_switch(ds); 6319 } 6320 6321 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6322 { 6323 dsa_unregister_switch(chip->ds); 6324 } 6325 6326 static const void *pdata_device_get_match_data(struct device *dev) 6327 { 6328 const struct of_device_id *matches = dev->driver->of_match_table; 6329 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6330 6331 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6332 matches++) { 6333 if (!strcmp(pdata->compatible, matches->compatible)) 6334 return matches->data; 6335 } 6336 return NULL; 6337 } 6338 6339 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6340 * would be lost after a power cycle so prevent it to be suspended. 6341 */ 6342 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6343 { 6344 return -EOPNOTSUPP; 6345 } 6346 6347 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6348 { 6349 return 0; 6350 } 6351 6352 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6353 6354 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6355 { 6356 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6357 const struct mv88e6xxx_info *compat_info = NULL; 6358 struct device *dev = &mdiodev->dev; 6359 struct device_node *np = dev->of_node; 6360 struct mv88e6xxx_chip *chip; 6361 int port; 6362 int err; 6363 6364 if (!np && !pdata) 6365 return -EINVAL; 6366 6367 if (np) 6368 compat_info = of_device_get_match_data(dev); 6369 6370 if (pdata) { 6371 compat_info = pdata_device_get_match_data(dev); 6372 6373 if (!pdata->netdev) 6374 return -EINVAL; 6375 6376 for (port = 0; port < DSA_MAX_PORTS; port++) { 6377 if (!(pdata->enabled_ports & (1 << port))) 6378 continue; 6379 if (strcmp(pdata->cd.port_names[port], "cpu")) 6380 continue; 6381 pdata->cd.netdev[port] = &pdata->netdev->dev; 6382 break; 6383 } 6384 } 6385 6386 if (!compat_info) 6387 return -EINVAL; 6388 6389 chip = mv88e6xxx_alloc_chip(dev); 6390 if (!chip) { 6391 err = -ENOMEM; 6392 goto out; 6393 } 6394 6395 chip->info = compat_info; 6396 6397 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6398 if (err) 6399 goto out; 6400 6401 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6402 if (IS_ERR(chip->reset)) { 6403 err = PTR_ERR(chip->reset); 6404 goto out; 6405 } 6406 if (chip->reset) 6407 usleep_range(1000, 2000); 6408 6409 err = mv88e6xxx_detect(chip); 6410 if (err) 6411 goto out; 6412 6413 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6414 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6415 else 6416 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6417 6418 mv88e6xxx_phy_init(chip); 6419 6420 if (chip->info->ops->get_eeprom) { 6421 if (np) 6422 of_property_read_u32(np, "eeprom-length", 6423 &chip->eeprom_len); 6424 else 6425 chip->eeprom_len = pdata->eeprom_len; 6426 } 6427 6428 mv88e6xxx_reg_lock(chip); 6429 err = mv88e6xxx_switch_reset(chip); 6430 mv88e6xxx_reg_unlock(chip); 6431 if (err) 6432 goto out; 6433 6434 if (np) { 6435 chip->irq = of_irq_get(np, 0); 6436 if (chip->irq == -EPROBE_DEFER) { 6437 err = chip->irq; 6438 goto out; 6439 } 6440 } 6441 6442 if (pdata) 6443 chip->irq = pdata->irq; 6444 6445 /* Has to be performed before the MDIO bus is created, because 6446 * the PHYs will link their interrupts to these interrupt 6447 * controllers 6448 */ 6449 mv88e6xxx_reg_lock(chip); 6450 if (chip->irq > 0) 6451 err = mv88e6xxx_g1_irq_setup(chip); 6452 else 6453 err = mv88e6xxx_irq_poll_setup(chip); 6454 mv88e6xxx_reg_unlock(chip); 6455 6456 if (err) 6457 goto out; 6458 6459 if (chip->info->g2_irqs > 0) { 6460 err = mv88e6xxx_g2_irq_setup(chip); 6461 if (err) 6462 goto out_g1_irq; 6463 } 6464 6465 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6466 if (err) 6467 goto out_g2_irq; 6468 6469 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6470 if (err) 6471 goto out_g1_atu_prob_irq; 6472 6473 err = mv88e6xxx_mdios_register(chip, np); 6474 if (err) 6475 goto out_g1_vtu_prob_irq; 6476 6477 err = mv88e6xxx_register_switch(chip); 6478 if (err) 6479 goto out_mdio; 6480 6481 return 0; 6482 6483 out_mdio: 6484 mv88e6xxx_mdios_unregister(chip); 6485 out_g1_vtu_prob_irq: 6486 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6487 out_g1_atu_prob_irq: 6488 mv88e6xxx_g1_atu_prob_irq_free(chip); 6489 out_g2_irq: 6490 if (chip->info->g2_irqs > 0) 6491 mv88e6xxx_g2_irq_free(chip); 6492 out_g1_irq: 6493 if (chip->irq > 0) 6494 mv88e6xxx_g1_irq_free(chip); 6495 else 6496 mv88e6xxx_irq_poll_free(chip); 6497 out: 6498 if (pdata) 6499 dev_put(pdata->netdev); 6500 6501 return err; 6502 } 6503 6504 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6505 { 6506 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6507 struct mv88e6xxx_chip *chip; 6508 6509 if (!ds) 6510 return; 6511 6512 chip = ds->priv; 6513 6514 if (chip->info->ptp_support) { 6515 mv88e6xxx_hwtstamp_free(chip); 6516 mv88e6xxx_ptp_free(chip); 6517 } 6518 6519 mv88e6xxx_phy_destroy(chip); 6520 mv88e6xxx_unregister_switch(chip); 6521 mv88e6xxx_mdios_unregister(chip); 6522 6523 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6524 mv88e6xxx_g1_atu_prob_irq_free(chip); 6525 6526 if (chip->info->g2_irqs > 0) 6527 mv88e6xxx_g2_irq_free(chip); 6528 6529 if (chip->irq > 0) 6530 mv88e6xxx_g1_irq_free(chip); 6531 else 6532 mv88e6xxx_irq_poll_free(chip); 6533 6534 dev_set_drvdata(&mdiodev->dev, NULL); 6535 } 6536 6537 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6538 { 6539 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6540 6541 if (!ds) 6542 return; 6543 6544 dsa_switch_shutdown(ds); 6545 6546 dev_set_drvdata(&mdiodev->dev, NULL); 6547 } 6548 6549 static const struct of_device_id mv88e6xxx_of_match[] = { 6550 { 6551 .compatible = "marvell,mv88e6085", 6552 .data = &mv88e6xxx_table[MV88E6085], 6553 }, 6554 { 6555 .compatible = "marvell,mv88e6190", 6556 .data = &mv88e6xxx_table[MV88E6190], 6557 }, 6558 { 6559 .compatible = "marvell,mv88e6250", 6560 .data = &mv88e6xxx_table[MV88E6250], 6561 }, 6562 { /* sentinel */ }, 6563 }; 6564 6565 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6566 6567 static struct mdio_driver mv88e6xxx_driver = { 6568 .probe = mv88e6xxx_probe, 6569 .remove = mv88e6xxx_remove, 6570 .shutdown = mv88e6xxx_shutdown, 6571 .mdiodrv.driver = { 6572 .name = "mv88e6085", 6573 .of_match_table = mv88e6xxx_of_match, 6574 .pm = &mv88e6xxx_pm_ops, 6575 }, 6576 }; 6577 6578 mdio_module_driver(mv88e6xxx_driver); 6579 6580 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6581 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6582 MODULE_LICENSE("GPL"); 6583