1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 snprintf(chip->irq_name, sizeof(chip->irq_name), 344 "mv88e6xxx-%s", dev_name(chip->dev)); 345 346 mv88e6xxx_reg_unlock(chip); 347 err = request_threaded_irq(chip->irq, NULL, 348 mv88e6xxx_g1_irq_thread_fn, 349 IRQF_ONESHOT | IRQF_SHARED, 350 chip->irq_name, chip); 351 mv88e6xxx_reg_lock(chip); 352 if (err) 353 mv88e6xxx_g1_irq_free_common(chip); 354 355 return err; 356 } 357 358 static void mv88e6xxx_irq_poll(struct kthread_work *work) 359 { 360 struct mv88e6xxx_chip *chip = container_of(work, 361 struct mv88e6xxx_chip, 362 irq_poll_work.work); 363 mv88e6xxx_g1_irq_thread_work(chip); 364 365 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 366 msecs_to_jiffies(100)); 367 } 368 369 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 370 { 371 int err; 372 373 err = mv88e6xxx_g1_irq_setup_common(chip); 374 if (err) 375 return err; 376 377 kthread_init_delayed_work(&chip->irq_poll_work, 378 mv88e6xxx_irq_poll); 379 380 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 381 if (IS_ERR(chip->kworker)) 382 return PTR_ERR(chip->kworker); 383 384 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 385 msecs_to_jiffies(100)); 386 387 return 0; 388 } 389 390 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 391 { 392 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 393 kthread_destroy_worker(chip->kworker); 394 395 mv88e6xxx_reg_lock(chip); 396 mv88e6xxx_g1_irq_free_common(chip); 397 mv88e6xxx_reg_unlock(chip); 398 } 399 400 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 401 int port, phy_interface_t interface) 402 { 403 int err; 404 405 if (chip->info->ops->port_set_rgmii_delay) { 406 err = chip->info->ops->port_set_rgmii_delay(chip, port, 407 interface); 408 if (err && err != -EOPNOTSUPP) 409 return err; 410 } 411 412 if (chip->info->ops->port_set_cmode) { 413 err = chip->info->ops->port_set_cmode(chip, port, 414 interface); 415 if (err && err != -EOPNOTSUPP) 416 return err; 417 } 418 419 return 0; 420 } 421 422 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 423 int link, int speed, int duplex, int pause, 424 phy_interface_t mode) 425 { 426 int err; 427 428 if (!chip->info->ops->port_set_link) 429 return 0; 430 431 /* Port's MAC control must not be changed unless the link is down */ 432 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 433 if (err) 434 return err; 435 436 if (chip->info->ops->port_set_speed_duplex) { 437 err = chip->info->ops->port_set_speed_duplex(chip, port, 438 speed, duplex); 439 if (err && err != -EOPNOTSUPP) 440 goto restore_link; 441 } 442 443 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 444 mode = chip->info->ops->port_max_speed_mode(port); 445 446 if (chip->info->ops->port_set_pause) { 447 err = chip->info->ops->port_set_pause(chip, port, pause); 448 if (err) 449 goto restore_link; 450 } 451 452 err = mv88e6xxx_port_config_interface(chip, port, mode); 453 restore_link: 454 if (chip->info->ops->port_set_link(chip, port, link)) 455 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 456 457 return err; 458 } 459 460 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 461 { 462 struct mv88e6xxx_chip *chip = ds->priv; 463 464 return port < chip->info->num_internal_phys; 465 } 466 467 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 468 { 469 u16 reg; 470 int err; 471 472 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 473 if (err) { 474 dev_err(chip->dev, 475 "p%d: %s: failed to read port status\n", 476 port, __func__); 477 return err; 478 } 479 480 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 481 } 482 483 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 484 struct phylink_link_state *state) 485 { 486 struct mv88e6xxx_chip *chip = ds->priv; 487 u8 lane; 488 int err; 489 490 mv88e6xxx_reg_lock(chip); 491 lane = mv88e6xxx_serdes_get_lane(chip, port); 492 if (lane && chip->info->ops->serdes_pcs_get_state) 493 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 494 state); 495 else 496 err = -EOPNOTSUPP; 497 mv88e6xxx_reg_unlock(chip); 498 499 return err; 500 } 501 502 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 503 unsigned int mode, 504 phy_interface_t interface, 505 const unsigned long *advertise) 506 { 507 const struct mv88e6xxx_ops *ops = chip->info->ops; 508 u8 lane; 509 510 if (ops->serdes_pcs_config) { 511 lane = mv88e6xxx_serdes_get_lane(chip, port); 512 if (lane) 513 return ops->serdes_pcs_config(chip, port, lane, mode, 514 interface, advertise); 515 } 516 517 return 0; 518 } 519 520 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 521 { 522 struct mv88e6xxx_chip *chip = ds->priv; 523 const struct mv88e6xxx_ops *ops; 524 int err = 0; 525 u8 lane; 526 527 ops = chip->info->ops; 528 529 if (ops->serdes_pcs_an_restart) { 530 mv88e6xxx_reg_lock(chip); 531 lane = mv88e6xxx_serdes_get_lane(chip, port); 532 if (lane) 533 err = ops->serdes_pcs_an_restart(chip, port, lane); 534 mv88e6xxx_reg_unlock(chip); 535 536 if (err) 537 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 538 } 539 } 540 541 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 542 unsigned int mode, 543 int speed, int duplex) 544 { 545 const struct mv88e6xxx_ops *ops = chip->info->ops; 546 u8 lane; 547 548 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 549 lane = mv88e6xxx_serdes_get_lane(chip, port); 550 if (lane) 551 return ops->serdes_pcs_link_up(chip, port, lane, 552 speed, duplex); 553 } 554 555 return 0; 556 } 557 558 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 559 unsigned long *mask, 560 struct phylink_link_state *state) 561 { 562 if (!phy_interface_mode_is_8023z(state->interface)) { 563 /* 10M and 100M are only supported in non-802.3z mode */ 564 phylink_set(mask, 10baseT_Half); 565 phylink_set(mask, 10baseT_Full); 566 phylink_set(mask, 100baseT_Half); 567 phylink_set(mask, 100baseT_Full); 568 } 569 } 570 571 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 572 unsigned long *mask, 573 struct phylink_link_state *state) 574 { 575 /* FIXME: if the port is in 1000Base-X mode, then it only supports 576 * 1000M FD speeds. In this case, CMODE will indicate 5. 577 */ 578 phylink_set(mask, 1000baseT_Full); 579 phylink_set(mask, 1000baseX_Full); 580 581 mv88e6065_phylink_validate(chip, port, mask, state); 582 } 583 584 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 585 unsigned long *mask, 586 struct phylink_link_state *state) 587 { 588 if (port >= 5) 589 phylink_set(mask, 2500baseX_Full); 590 591 /* No ethtool bits for 200Mbps */ 592 phylink_set(mask, 1000baseT_Full); 593 phylink_set(mask, 1000baseX_Full); 594 595 mv88e6065_phylink_validate(chip, port, mask, state); 596 } 597 598 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 599 unsigned long *mask, 600 struct phylink_link_state *state) 601 { 602 /* No ethtool bits for 200Mbps */ 603 phylink_set(mask, 1000baseT_Full); 604 phylink_set(mask, 1000baseX_Full); 605 606 mv88e6065_phylink_validate(chip, port, mask, state); 607 } 608 609 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 610 unsigned long *mask, 611 struct phylink_link_state *state) 612 { 613 if (port >= 9) { 614 phylink_set(mask, 2500baseX_Full); 615 phylink_set(mask, 2500baseT_Full); 616 } 617 618 /* No ethtool bits for 200Mbps */ 619 phylink_set(mask, 1000baseT_Full); 620 phylink_set(mask, 1000baseX_Full); 621 622 mv88e6065_phylink_validate(chip, port, mask, state); 623 } 624 625 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 626 unsigned long *mask, 627 struct phylink_link_state *state) 628 { 629 if (port >= 9) { 630 phylink_set(mask, 10000baseT_Full); 631 phylink_set(mask, 10000baseKR_Full); 632 } 633 634 mv88e6390_phylink_validate(chip, port, mask, state); 635 } 636 637 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 638 unsigned long *supported, 639 struct phylink_link_state *state) 640 { 641 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 642 struct mv88e6xxx_chip *chip = ds->priv; 643 644 /* Allow all the expected bits */ 645 phylink_set(mask, Autoneg); 646 phylink_set(mask, Pause); 647 phylink_set_port_modes(mask); 648 649 if (chip->info->ops->phylink_validate) 650 chip->info->ops->phylink_validate(chip, port, mask, state); 651 652 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 653 bitmap_and(state->advertising, state->advertising, mask, 654 __ETHTOOL_LINK_MODE_MASK_NBITS); 655 656 /* We can only operate at 2500BaseX or 1000BaseX. If requested 657 * to advertise both, only report advertising at 2500BaseX. 658 */ 659 phylink_helper_basex_speed(state); 660 } 661 662 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 663 unsigned int mode, 664 const struct phylink_link_state *state) 665 { 666 struct mv88e6xxx_chip *chip = ds->priv; 667 int err; 668 669 /* FIXME: is this the correct test? If we're in fixed mode on an 670 * internal port, why should we process this any different from 671 * PHY mode? On the other hand, the port may be automedia between 672 * an internal PHY and the serdes... 673 */ 674 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 675 return; 676 677 mv88e6xxx_reg_lock(chip); 678 /* FIXME: should we force the link down here - but if we do, how 679 * do we restore the link force/unforce state? The driver layering 680 * gets in the way. 681 */ 682 err = mv88e6xxx_port_config_interface(chip, port, state->interface); 683 if (err && err != -EOPNOTSUPP) 684 goto err_unlock; 685 686 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, state->interface, 687 state->advertising); 688 /* FIXME: we should restart negotiation if something changed - which 689 * is something we get if we convert to using phylinks PCS operations. 690 */ 691 if (err > 0) 692 err = 0; 693 694 err_unlock: 695 mv88e6xxx_reg_unlock(chip); 696 697 if (err && err != -EOPNOTSUPP) 698 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 699 } 700 701 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 702 unsigned int mode, 703 phy_interface_t interface) 704 { 705 struct mv88e6xxx_chip *chip = ds->priv; 706 const struct mv88e6xxx_ops *ops; 707 int err = 0; 708 709 ops = chip->info->ops; 710 711 mv88e6xxx_reg_lock(chip); 712 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 713 mode == MLO_AN_FIXED) && ops->port_set_link) 714 err = ops->port_set_link(chip, port, LINK_FORCED_DOWN); 715 mv88e6xxx_reg_unlock(chip); 716 717 if (err) 718 dev_err(chip->dev, 719 "p%d: failed to force MAC link down\n", port); 720 } 721 722 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 723 unsigned int mode, phy_interface_t interface, 724 struct phy_device *phydev, 725 int speed, int duplex, 726 bool tx_pause, bool rx_pause) 727 { 728 struct mv88e6xxx_chip *chip = ds->priv; 729 const struct mv88e6xxx_ops *ops; 730 int err = 0; 731 732 ops = chip->info->ops; 733 734 mv88e6xxx_reg_lock(chip); 735 if (!mv88e6xxx_port_ppu_updates(chip, port) || mode == MLO_AN_FIXED) { 736 /* FIXME: for an automedia port, should we force the link 737 * down here - what if the link comes up due to "other" media 738 * while we're bringing the port up, how is the exclusivity 739 * handled in the Marvell hardware? E.g. port 2 on 88E6390 740 * shared between internal PHY and Serdes. 741 */ 742 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 743 duplex); 744 if (err) 745 goto error; 746 747 if (ops->port_set_speed_duplex) { 748 err = ops->port_set_speed_duplex(chip, port, 749 speed, duplex); 750 if (err && err != -EOPNOTSUPP) 751 goto error; 752 } 753 754 if (ops->port_set_link) 755 err = ops->port_set_link(chip, port, LINK_FORCED_UP); 756 } 757 error: 758 mv88e6xxx_reg_unlock(chip); 759 760 if (err && err != -EOPNOTSUPP) 761 dev_err(ds->dev, 762 "p%d: failed to configure MAC link up\n", port); 763 } 764 765 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 766 { 767 if (!chip->info->ops->stats_snapshot) 768 return -EOPNOTSUPP; 769 770 return chip->info->ops->stats_snapshot(chip, port); 771 } 772 773 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 774 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 775 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 776 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 777 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 778 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 779 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 780 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 781 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 782 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 783 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 784 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 785 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 786 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 787 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 788 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 789 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 790 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 791 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 792 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 793 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 794 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 795 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 796 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 797 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 798 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 799 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 800 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 801 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 802 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 803 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 804 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 805 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 806 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 807 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 808 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 809 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 810 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 811 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 812 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 813 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 814 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 815 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 816 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 817 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 818 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 819 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 820 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 821 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 822 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 823 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 824 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 825 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 826 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 827 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 828 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 829 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 830 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 831 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 832 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 833 }; 834 835 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 836 struct mv88e6xxx_hw_stat *s, 837 int port, u16 bank1_select, 838 u16 histogram) 839 { 840 u32 low; 841 u32 high = 0; 842 u16 reg = 0; 843 int err; 844 u64 value; 845 846 switch (s->type) { 847 case STATS_TYPE_PORT: 848 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 849 if (err) 850 return U64_MAX; 851 852 low = reg; 853 if (s->size == 4) { 854 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 855 if (err) 856 return U64_MAX; 857 low |= ((u32)reg) << 16; 858 } 859 break; 860 case STATS_TYPE_BANK1: 861 reg = bank1_select; 862 /* fall through */ 863 case STATS_TYPE_BANK0: 864 reg |= s->reg | histogram; 865 mv88e6xxx_g1_stats_read(chip, reg, &low); 866 if (s->size == 8) 867 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 868 break; 869 default: 870 return U64_MAX; 871 } 872 value = (((u64)high) << 32) | low; 873 return value; 874 } 875 876 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 877 uint8_t *data, int types) 878 { 879 struct mv88e6xxx_hw_stat *stat; 880 int i, j; 881 882 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 883 stat = &mv88e6xxx_hw_stats[i]; 884 if (stat->type & types) { 885 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 886 ETH_GSTRING_LEN); 887 j++; 888 } 889 } 890 891 return j; 892 } 893 894 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 895 uint8_t *data) 896 { 897 return mv88e6xxx_stats_get_strings(chip, data, 898 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 899 } 900 901 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 902 uint8_t *data) 903 { 904 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 905 } 906 907 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 908 uint8_t *data) 909 { 910 return mv88e6xxx_stats_get_strings(chip, data, 911 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 912 } 913 914 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 915 "atu_member_violation", 916 "atu_miss_violation", 917 "atu_full_violation", 918 "vtu_member_violation", 919 "vtu_miss_violation", 920 }; 921 922 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 923 { 924 unsigned int i; 925 926 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 927 strlcpy(data + i * ETH_GSTRING_LEN, 928 mv88e6xxx_atu_vtu_stats_strings[i], 929 ETH_GSTRING_LEN); 930 } 931 932 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 933 u32 stringset, uint8_t *data) 934 { 935 struct mv88e6xxx_chip *chip = ds->priv; 936 int count = 0; 937 938 if (stringset != ETH_SS_STATS) 939 return; 940 941 mv88e6xxx_reg_lock(chip); 942 943 if (chip->info->ops->stats_get_strings) 944 count = chip->info->ops->stats_get_strings(chip, data); 945 946 if (chip->info->ops->serdes_get_strings) { 947 data += count * ETH_GSTRING_LEN; 948 count = chip->info->ops->serdes_get_strings(chip, port, data); 949 } 950 951 data += count * ETH_GSTRING_LEN; 952 mv88e6xxx_atu_vtu_get_strings(data); 953 954 mv88e6xxx_reg_unlock(chip); 955 } 956 957 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 958 int types) 959 { 960 struct mv88e6xxx_hw_stat *stat; 961 int i, j; 962 963 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 964 stat = &mv88e6xxx_hw_stats[i]; 965 if (stat->type & types) 966 j++; 967 } 968 return j; 969 } 970 971 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 972 { 973 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 974 STATS_TYPE_PORT); 975 } 976 977 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 978 { 979 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 980 } 981 982 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 983 { 984 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 985 STATS_TYPE_BANK1); 986 } 987 988 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 989 { 990 struct mv88e6xxx_chip *chip = ds->priv; 991 int serdes_count = 0; 992 int count = 0; 993 994 if (sset != ETH_SS_STATS) 995 return 0; 996 997 mv88e6xxx_reg_lock(chip); 998 if (chip->info->ops->stats_get_sset_count) 999 count = chip->info->ops->stats_get_sset_count(chip); 1000 if (count < 0) 1001 goto out; 1002 1003 if (chip->info->ops->serdes_get_sset_count) 1004 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1005 port); 1006 if (serdes_count < 0) { 1007 count = serdes_count; 1008 goto out; 1009 } 1010 count += serdes_count; 1011 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1012 1013 out: 1014 mv88e6xxx_reg_unlock(chip); 1015 1016 return count; 1017 } 1018 1019 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1020 uint64_t *data, int types, 1021 u16 bank1_select, u16 histogram) 1022 { 1023 struct mv88e6xxx_hw_stat *stat; 1024 int i, j; 1025 1026 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1027 stat = &mv88e6xxx_hw_stats[i]; 1028 if (stat->type & types) { 1029 mv88e6xxx_reg_lock(chip); 1030 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1031 bank1_select, 1032 histogram); 1033 mv88e6xxx_reg_unlock(chip); 1034 1035 j++; 1036 } 1037 } 1038 return j; 1039 } 1040 1041 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1042 uint64_t *data) 1043 { 1044 return mv88e6xxx_stats_get_stats(chip, port, data, 1045 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1046 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1047 } 1048 1049 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1050 uint64_t *data) 1051 { 1052 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1053 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1054 } 1055 1056 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1057 uint64_t *data) 1058 { 1059 return mv88e6xxx_stats_get_stats(chip, port, data, 1060 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1061 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1062 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1063 } 1064 1065 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1066 uint64_t *data) 1067 { 1068 return mv88e6xxx_stats_get_stats(chip, port, data, 1069 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1070 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1071 0); 1072 } 1073 1074 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1075 uint64_t *data) 1076 { 1077 *data++ = chip->ports[port].atu_member_violation; 1078 *data++ = chip->ports[port].atu_miss_violation; 1079 *data++ = chip->ports[port].atu_full_violation; 1080 *data++ = chip->ports[port].vtu_member_violation; 1081 *data++ = chip->ports[port].vtu_miss_violation; 1082 } 1083 1084 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1085 uint64_t *data) 1086 { 1087 int count = 0; 1088 1089 if (chip->info->ops->stats_get_stats) 1090 count = chip->info->ops->stats_get_stats(chip, port, data); 1091 1092 mv88e6xxx_reg_lock(chip); 1093 if (chip->info->ops->serdes_get_stats) { 1094 data += count; 1095 count = chip->info->ops->serdes_get_stats(chip, port, data); 1096 } 1097 data += count; 1098 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1099 mv88e6xxx_reg_unlock(chip); 1100 } 1101 1102 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1103 uint64_t *data) 1104 { 1105 struct mv88e6xxx_chip *chip = ds->priv; 1106 int ret; 1107 1108 mv88e6xxx_reg_lock(chip); 1109 1110 ret = mv88e6xxx_stats_snapshot(chip, port); 1111 mv88e6xxx_reg_unlock(chip); 1112 1113 if (ret < 0) 1114 return; 1115 1116 mv88e6xxx_get_stats(chip, port, data); 1117 1118 } 1119 1120 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1121 { 1122 struct mv88e6xxx_chip *chip = ds->priv; 1123 int len; 1124 1125 len = 32 * sizeof(u16); 1126 if (chip->info->ops->serdes_get_regs_len) 1127 len += chip->info->ops->serdes_get_regs_len(chip, port); 1128 1129 return len; 1130 } 1131 1132 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1133 struct ethtool_regs *regs, void *_p) 1134 { 1135 struct mv88e6xxx_chip *chip = ds->priv; 1136 int err; 1137 u16 reg; 1138 u16 *p = _p; 1139 int i; 1140 1141 regs->version = chip->info->prod_num; 1142 1143 memset(p, 0xff, 32 * sizeof(u16)); 1144 1145 mv88e6xxx_reg_lock(chip); 1146 1147 for (i = 0; i < 32; i++) { 1148 1149 err = mv88e6xxx_port_read(chip, port, i, ®); 1150 if (!err) 1151 p[i] = reg; 1152 } 1153 1154 if (chip->info->ops->serdes_get_regs) 1155 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1156 1157 mv88e6xxx_reg_unlock(chip); 1158 } 1159 1160 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1161 struct ethtool_eee *e) 1162 { 1163 /* Nothing to do on the port's MAC */ 1164 return 0; 1165 } 1166 1167 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1168 struct ethtool_eee *e) 1169 { 1170 /* Nothing to do on the port's MAC */ 1171 return 0; 1172 } 1173 1174 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1175 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1176 { 1177 struct dsa_switch *ds = chip->ds; 1178 struct dsa_switch_tree *dst = ds->dst; 1179 struct net_device *br; 1180 struct dsa_port *dp; 1181 bool found = false; 1182 u16 pvlan; 1183 1184 list_for_each_entry(dp, &dst->ports, list) { 1185 if (dp->ds->index == dev && dp->index == port) { 1186 found = true; 1187 break; 1188 } 1189 } 1190 1191 /* Prevent frames from unknown switch or port */ 1192 if (!found) 1193 return 0; 1194 1195 /* Frames from DSA links and CPU ports can egress any local port */ 1196 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1197 return mv88e6xxx_port_mask(chip); 1198 1199 br = dp->bridge_dev; 1200 pvlan = 0; 1201 1202 /* Frames from user ports can egress any local DSA links and CPU ports, 1203 * as well as any local member of their bridge group. 1204 */ 1205 list_for_each_entry(dp, &dst->ports, list) 1206 if (dp->ds == ds && 1207 (dp->type == DSA_PORT_TYPE_CPU || 1208 dp->type == DSA_PORT_TYPE_DSA || 1209 (br && dp->bridge_dev == br))) 1210 pvlan |= BIT(dp->index); 1211 1212 return pvlan; 1213 } 1214 1215 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1216 { 1217 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1218 1219 /* prevent frames from going back out of the port they came in on */ 1220 output_ports &= ~BIT(port); 1221 1222 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1223 } 1224 1225 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1226 u8 state) 1227 { 1228 struct mv88e6xxx_chip *chip = ds->priv; 1229 int err; 1230 1231 mv88e6xxx_reg_lock(chip); 1232 err = mv88e6xxx_port_set_state(chip, port, state); 1233 mv88e6xxx_reg_unlock(chip); 1234 1235 if (err) 1236 dev_err(ds->dev, "p%d: failed to update state\n", port); 1237 } 1238 1239 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1240 { 1241 int err; 1242 1243 if (chip->info->ops->ieee_pri_map) { 1244 err = chip->info->ops->ieee_pri_map(chip); 1245 if (err) 1246 return err; 1247 } 1248 1249 if (chip->info->ops->ip_pri_map) { 1250 err = chip->info->ops->ip_pri_map(chip); 1251 if (err) 1252 return err; 1253 } 1254 1255 return 0; 1256 } 1257 1258 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1259 { 1260 struct dsa_switch *ds = chip->ds; 1261 int target, port; 1262 int err; 1263 1264 if (!chip->info->global2_addr) 1265 return 0; 1266 1267 /* Initialize the routing port to the 32 possible target devices */ 1268 for (target = 0; target < 32; target++) { 1269 port = dsa_routing_port(ds, target); 1270 if (port == ds->num_ports) 1271 port = 0x1f; 1272 1273 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1274 if (err) 1275 return err; 1276 } 1277 1278 if (chip->info->ops->set_cascade_port) { 1279 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1280 err = chip->info->ops->set_cascade_port(chip, port); 1281 if (err) 1282 return err; 1283 } 1284 1285 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1286 if (err) 1287 return err; 1288 1289 return 0; 1290 } 1291 1292 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1293 { 1294 /* Clear all trunk masks and mapping */ 1295 if (chip->info->global2_addr) 1296 return mv88e6xxx_g2_trunk_clear(chip); 1297 1298 return 0; 1299 } 1300 1301 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1302 { 1303 if (chip->info->ops->rmu_disable) 1304 return chip->info->ops->rmu_disable(chip); 1305 1306 return 0; 1307 } 1308 1309 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1310 { 1311 if (chip->info->ops->pot_clear) 1312 return chip->info->ops->pot_clear(chip); 1313 1314 return 0; 1315 } 1316 1317 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1318 { 1319 if (chip->info->ops->mgmt_rsvd2cpu) 1320 return chip->info->ops->mgmt_rsvd2cpu(chip); 1321 1322 return 0; 1323 } 1324 1325 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1326 { 1327 int err; 1328 1329 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1330 if (err) 1331 return err; 1332 1333 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1334 if (err) 1335 return err; 1336 1337 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1338 } 1339 1340 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1341 { 1342 int port; 1343 int err; 1344 1345 if (!chip->info->ops->irl_init_all) 1346 return 0; 1347 1348 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1349 /* Disable ingress rate limiting by resetting all per port 1350 * ingress rate limit resources to their initial state. 1351 */ 1352 err = chip->info->ops->irl_init_all(chip, port); 1353 if (err) 1354 return err; 1355 } 1356 1357 return 0; 1358 } 1359 1360 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1361 { 1362 if (chip->info->ops->set_switch_mac) { 1363 u8 addr[ETH_ALEN]; 1364 1365 eth_random_addr(addr); 1366 1367 return chip->info->ops->set_switch_mac(chip, addr); 1368 } 1369 1370 return 0; 1371 } 1372 1373 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1374 { 1375 u16 pvlan = 0; 1376 1377 if (!mv88e6xxx_has_pvt(chip)) 1378 return 0; 1379 1380 /* Skip the local source device, which uses in-chip port VLAN */ 1381 if (dev != chip->ds->index) 1382 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1383 1384 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1385 } 1386 1387 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1388 { 1389 int dev, port; 1390 int err; 1391 1392 if (!mv88e6xxx_has_pvt(chip)) 1393 return 0; 1394 1395 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1396 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1397 */ 1398 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1399 if (err) 1400 return err; 1401 1402 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1403 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1404 err = mv88e6xxx_pvt_map(chip, dev, port); 1405 if (err) 1406 return err; 1407 } 1408 } 1409 1410 return 0; 1411 } 1412 1413 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1414 { 1415 struct mv88e6xxx_chip *chip = ds->priv; 1416 int err; 1417 1418 mv88e6xxx_reg_lock(chip); 1419 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1420 mv88e6xxx_reg_unlock(chip); 1421 1422 if (err) 1423 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1424 } 1425 1426 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1427 { 1428 if (!chip->info->max_vid) 1429 return 0; 1430 1431 return mv88e6xxx_g1_vtu_flush(chip); 1432 } 1433 1434 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1435 struct mv88e6xxx_vtu_entry *entry) 1436 { 1437 if (!chip->info->ops->vtu_getnext) 1438 return -EOPNOTSUPP; 1439 1440 return chip->info->ops->vtu_getnext(chip, entry); 1441 } 1442 1443 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1444 struct mv88e6xxx_vtu_entry *entry) 1445 { 1446 if (!chip->info->ops->vtu_loadpurge) 1447 return -EOPNOTSUPP; 1448 1449 return chip->info->ops->vtu_loadpurge(chip, entry); 1450 } 1451 1452 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1453 { 1454 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1455 struct mv88e6xxx_vtu_entry vlan; 1456 int i, err; 1457 1458 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1459 1460 /* Set every FID bit used by the (un)bridged ports */ 1461 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1462 err = mv88e6xxx_port_get_fid(chip, i, fid); 1463 if (err) 1464 return err; 1465 1466 set_bit(*fid, fid_bitmap); 1467 } 1468 1469 /* Set every FID bit used by the VLAN entries */ 1470 vlan.vid = chip->info->max_vid; 1471 vlan.valid = false; 1472 1473 do { 1474 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1475 if (err) 1476 return err; 1477 1478 if (!vlan.valid) 1479 break; 1480 1481 set_bit(vlan.fid, fid_bitmap); 1482 } while (vlan.vid < chip->info->max_vid); 1483 1484 /* The reset value 0x000 is used to indicate that multiple address 1485 * databases are not needed. Return the next positive available. 1486 */ 1487 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1488 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1489 return -ENOSPC; 1490 1491 /* Clear the database */ 1492 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1493 } 1494 1495 static int mv88e6xxx_atu_get_hash(struct mv88e6xxx_chip *chip, u8 *hash) 1496 { 1497 if (chip->info->ops->atu_get_hash) 1498 return chip->info->ops->atu_get_hash(chip, hash); 1499 1500 return -EOPNOTSUPP; 1501 } 1502 1503 static int mv88e6xxx_atu_set_hash(struct mv88e6xxx_chip *chip, u8 hash) 1504 { 1505 if (chip->info->ops->atu_set_hash) 1506 return chip->info->ops->atu_set_hash(chip, hash); 1507 1508 return -EOPNOTSUPP; 1509 } 1510 1511 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1512 u16 vid_begin, u16 vid_end) 1513 { 1514 struct mv88e6xxx_chip *chip = ds->priv; 1515 struct mv88e6xxx_vtu_entry vlan; 1516 int i, err; 1517 1518 /* DSA and CPU ports have to be members of multiple vlans */ 1519 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1520 return 0; 1521 1522 if (!vid_begin) 1523 return -EOPNOTSUPP; 1524 1525 vlan.vid = vid_begin - 1; 1526 vlan.valid = false; 1527 1528 do { 1529 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1530 if (err) 1531 return err; 1532 1533 if (!vlan.valid) 1534 break; 1535 1536 if (vlan.vid > vid_end) 1537 break; 1538 1539 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1540 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1541 continue; 1542 1543 if (!dsa_to_port(ds, i)->slave) 1544 continue; 1545 1546 if (vlan.member[i] == 1547 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1548 continue; 1549 1550 if (dsa_to_port(ds, i)->bridge_dev == 1551 dsa_to_port(ds, port)->bridge_dev) 1552 break; /* same bridge, check next VLAN */ 1553 1554 if (!dsa_to_port(ds, i)->bridge_dev) 1555 continue; 1556 1557 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1558 port, vlan.vid, i, 1559 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1560 return -EOPNOTSUPP; 1561 } 1562 } while (vlan.vid < vid_end); 1563 1564 return 0; 1565 } 1566 1567 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1568 bool vlan_filtering) 1569 { 1570 struct mv88e6xxx_chip *chip = ds->priv; 1571 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1572 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1573 int err; 1574 1575 if (!chip->info->max_vid) 1576 return -EOPNOTSUPP; 1577 1578 mv88e6xxx_reg_lock(chip); 1579 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1580 mv88e6xxx_reg_unlock(chip); 1581 1582 return err; 1583 } 1584 1585 static int 1586 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1587 const struct switchdev_obj_port_vlan *vlan) 1588 { 1589 struct mv88e6xxx_chip *chip = ds->priv; 1590 int err; 1591 1592 if (!chip->info->max_vid) 1593 return -EOPNOTSUPP; 1594 1595 /* If the requested port doesn't belong to the same bridge as the VLAN 1596 * members, do not support it (yet) and fallback to software VLAN. 1597 */ 1598 mv88e6xxx_reg_lock(chip); 1599 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1600 vlan->vid_end); 1601 mv88e6xxx_reg_unlock(chip); 1602 1603 /* We don't need any dynamic resource from the kernel (yet), 1604 * so skip the prepare phase. 1605 */ 1606 return err; 1607 } 1608 1609 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1610 const unsigned char *addr, u16 vid, 1611 u8 state) 1612 { 1613 struct mv88e6xxx_atu_entry entry; 1614 struct mv88e6xxx_vtu_entry vlan; 1615 u16 fid; 1616 int err; 1617 1618 /* Null VLAN ID corresponds to the port private database */ 1619 if (vid == 0) { 1620 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1621 if (err) 1622 return err; 1623 } else { 1624 vlan.vid = vid - 1; 1625 vlan.valid = false; 1626 1627 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1628 if (err) 1629 return err; 1630 1631 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1632 if (vlan.vid != vid || !vlan.valid) 1633 return -EOPNOTSUPP; 1634 1635 fid = vlan.fid; 1636 } 1637 1638 entry.state = 0; 1639 ether_addr_copy(entry.mac, addr); 1640 eth_addr_dec(entry.mac); 1641 1642 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1643 if (err) 1644 return err; 1645 1646 /* Initialize a fresh ATU entry if it isn't found */ 1647 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1648 memset(&entry, 0, sizeof(entry)); 1649 ether_addr_copy(entry.mac, addr); 1650 } 1651 1652 /* Purge the ATU entry only if no port is using it anymore */ 1653 if (!state) { 1654 entry.portvec &= ~BIT(port); 1655 if (!entry.portvec) 1656 entry.state = 0; 1657 } else { 1658 entry.portvec |= BIT(port); 1659 entry.state = state; 1660 } 1661 1662 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1663 } 1664 1665 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1666 const struct mv88e6xxx_policy *policy) 1667 { 1668 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1669 enum mv88e6xxx_policy_action action = policy->action; 1670 const u8 *addr = policy->addr; 1671 u16 vid = policy->vid; 1672 u8 state; 1673 int err; 1674 int id; 1675 1676 if (!chip->info->ops->port_set_policy) 1677 return -EOPNOTSUPP; 1678 1679 switch (mapping) { 1680 case MV88E6XXX_POLICY_MAPPING_DA: 1681 case MV88E6XXX_POLICY_MAPPING_SA: 1682 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1683 state = 0; /* Dissociate the port and address */ 1684 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1685 is_multicast_ether_addr(addr)) 1686 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1687 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1688 is_unicast_ether_addr(addr)) 1689 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1690 else 1691 return -EOPNOTSUPP; 1692 1693 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1694 state); 1695 if (err) 1696 return err; 1697 break; 1698 default: 1699 return -EOPNOTSUPP; 1700 } 1701 1702 /* Skip the port's policy clearing if the mapping is still in use */ 1703 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1704 idr_for_each_entry(&chip->policies, policy, id) 1705 if (policy->port == port && 1706 policy->mapping == mapping && 1707 policy->action != action) 1708 return 0; 1709 1710 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1711 } 1712 1713 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1714 struct ethtool_rx_flow_spec *fs) 1715 { 1716 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1717 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1718 enum mv88e6xxx_policy_mapping mapping; 1719 enum mv88e6xxx_policy_action action; 1720 struct mv88e6xxx_policy *policy; 1721 u16 vid = 0; 1722 u8 *addr; 1723 int err; 1724 int id; 1725 1726 if (fs->location != RX_CLS_LOC_ANY) 1727 return -EINVAL; 1728 1729 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1730 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1731 else 1732 return -EOPNOTSUPP; 1733 1734 switch (fs->flow_type & ~FLOW_EXT) { 1735 case ETHER_FLOW: 1736 if (!is_zero_ether_addr(mac_mask->h_dest) && 1737 is_zero_ether_addr(mac_mask->h_source)) { 1738 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1739 addr = mac_entry->h_dest; 1740 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1741 !is_zero_ether_addr(mac_mask->h_source)) { 1742 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1743 addr = mac_entry->h_source; 1744 } else { 1745 /* Cannot support DA and SA mapping in the same rule */ 1746 return -EOPNOTSUPP; 1747 } 1748 break; 1749 default: 1750 return -EOPNOTSUPP; 1751 } 1752 1753 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1754 if (fs->m_ext.vlan_tci != 0xffff) 1755 return -EOPNOTSUPP; 1756 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1757 } 1758 1759 idr_for_each_entry(&chip->policies, policy, id) { 1760 if (policy->port == port && policy->mapping == mapping && 1761 policy->action == action && policy->vid == vid && 1762 ether_addr_equal(policy->addr, addr)) 1763 return -EEXIST; 1764 } 1765 1766 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1767 if (!policy) 1768 return -ENOMEM; 1769 1770 fs->location = 0; 1771 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1772 GFP_KERNEL); 1773 if (err) { 1774 devm_kfree(chip->dev, policy); 1775 return err; 1776 } 1777 1778 memcpy(&policy->fs, fs, sizeof(*fs)); 1779 ether_addr_copy(policy->addr, addr); 1780 policy->mapping = mapping; 1781 policy->action = action; 1782 policy->port = port; 1783 policy->vid = vid; 1784 1785 err = mv88e6xxx_policy_apply(chip, port, policy); 1786 if (err) { 1787 idr_remove(&chip->policies, fs->location); 1788 devm_kfree(chip->dev, policy); 1789 return err; 1790 } 1791 1792 return 0; 1793 } 1794 1795 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1796 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1797 { 1798 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1799 struct mv88e6xxx_chip *chip = ds->priv; 1800 struct mv88e6xxx_policy *policy; 1801 int err; 1802 int id; 1803 1804 mv88e6xxx_reg_lock(chip); 1805 1806 switch (rxnfc->cmd) { 1807 case ETHTOOL_GRXCLSRLCNT: 1808 rxnfc->data = 0; 1809 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1810 rxnfc->rule_cnt = 0; 1811 idr_for_each_entry(&chip->policies, policy, id) 1812 if (policy->port == port) 1813 rxnfc->rule_cnt++; 1814 err = 0; 1815 break; 1816 case ETHTOOL_GRXCLSRULE: 1817 err = -ENOENT; 1818 policy = idr_find(&chip->policies, fs->location); 1819 if (policy) { 1820 memcpy(fs, &policy->fs, sizeof(*fs)); 1821 err = 0; 1822 } 1823 break; 1824 case ETHTOOL_GRXCLSRLALL: 1825 rxnfc->data = 0; 1826 rxnfc->rule_cnt = 0; 1827 idr_for_each_entry(&chip->policies, policy, id) 1828 if (policy->port == port) 1829 rule_locs[rxnfc->rule_cnt++] = id; 1830 err = 0; 1831 break; 1832 default: 1833 err = -EOPNOTSUPP; 1834 break; 1835 } 1836 1837 mv88e6xxx_reg_unlock(chip); 1838 1839 return err; 1840 } 1841 1842 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1843 struct ethtool_rxnfc *rxnfc) 1844 { 1845 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1846 struct mv88e6xxx_chip *chip = ds->priv; 1847 struct mv88e6xxx_policy *policy; 1848 int err; 1849 1850 mv88e6xxx_reg_lock(chip); 1851 1852 switch (rxnfc->cmd) { 1853 case ETHTOOL_SRXCLSRLINS: 1854 err = mv88e6xxx_policy_insert(chip, port, fs); 1855 break; 1856 case ETHTOOL_SRXCLSRLDEL: 1857 err = -ENOENT; 1858 policy = idr_remove(&chip->policies, fs->location); 1859 if (policy) { 1860 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1861 err = mv88e6xxx_policy_apply(chip, port, policy); 1862 devm_kfree(chip->dev, policy); 1863 } 1864 break; 1865 default: 1866 err = -EOPNOTSUPP; 1867 break; 1868 } 1869 1870 mv88e6xxx_reg_unlock(chip); 1871 1872 return err; 1873 } 1874 1875 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1876 u16 vid) 1877 { 1878 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1879 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1880 1881 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1882 } 1883 1884 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1885 { 1886 int port; 1887 int err; 1888 1889 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1890 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1891 if (err) 1892 return err; 1893 } 1894 1895 return 0; 1896 } 1897 1898 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1899 u16 vid, u8 member, bool warn) 1900 { 1901 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1902 struct mv88e6xxx_vtu_entry vlan; 1903 int i, err; 1904 1905 if (!vid) 1906 return -EOPNOTSUPP; 1907 1908 vlan.vid = vid - 1; 1909 vlan.valid = false; 1910 1911 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1912 if (err) 1913 return err; 1914 1915 if (vlan.vid != vid || !vlan.valid) { 1916 memset(&vlan, 0, sizeof(vlan)); 1917 1918 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1919 if (err) 1920 return err; 1921 1922 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1923 if (i == port) 1924 vlan.member[i] = member; 1925 else 1926 vlan.member[i] = non_member; 1927 1928 vlan.vid = vid; 1929 vlan.valid = true; 1930 1931 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1932 if (err) 1933 return err; 1934 1935 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1936 if (err) 1937 return err; 1938 } else if (vlan.member[port] != member) { 1939 vlan.member[port] = member; 1940 1941 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1942 if (err) 1943 return err; 1944 } else if (warn) { 1945 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1946 port, vid); 1947 } 1948 1949 return 0; 1950 } 1951 1952 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1953 const struct switchdev_obj_port_vlan *vlan) 1954 { 1955 struct mv88e6xxx_chip *chip = ds->priv; 1956 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1957 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1958 bool warn; 1959 u8 member; 1960 u16 vid; 1961 1962 if (!chip->info->max_vid) 1963 return; 1964 1965 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1966 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1967 else if (untagged) 1968 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1969 else 1970 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1971 1972 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 1973 * and then the CPU port. Do not warn for duplicates for the CPU port. 1974 */ 1975 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 1976 1977 mv88e6xxx_reg_lock(chip); 1978 1979 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1980 if (mv88e6xxx_port_vlan_join(chip, port, vid, member, warn)) 1981 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1982 vid, untagged ? 'u' : 't'); 1983 1984 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1985 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1986 vlan->vid_end); 1987 1988 mv88e6xxx_reg_unlock(chip); 1989 } 1990 1991 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1992 int port, u16 vid) 1993 { 1994 struct mv88e6xxx_vtu_entry vlan; 1995 int i, err; 1996 1997 if (!vid) 1998 return -EOPNOTSUPP; 1999 2000 vlan.vid = vid - 1; 2001 vlan.valid = false; 2002 2003 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2004 if (err) 2005 return err; 2006 2007 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2008 * tell switchdev that this VLAN is likely handled in software. 2009 */ 2010 if (vlan.vid != vid || !vlan.valid || 2011 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2012 return -EOPNOTSUPP; 2013 2014 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2015 2016 /* keep the VLAN unless all ports are excluded */ 2017 vlan.valid = false; 2018 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2019 if (vlan.member[i] != 2020 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2021 vlan.valid = true; 2022 break; 2023 } 2024 } 2025 2026 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2027 if (err) 2028 return err; 2029 2030 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2031 } 2032 2033 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2034 const struct switchdev_obj_port_vlan *vlan) 2035 { 2036 struct mv88e6xxx_chip *chip = ds->priv; 2037 u16 pvid, vid; 2038 int err = 0; 2039 2040 if (!chip->info->max_vid) 2041 return -EOPNOTSUPP; 2042 2043 mv88e6xxx_reg_lock(chip); 2044 2045 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2046 if (err) 2047 goto unlock; 2048 2049 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 2050 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 2051 if (err) 2052 goto unlock; 2053 2054 if (vid == pvid) { 2055 err = mv88e6xxx_port_set_pvid(chip, port, 0); 2056 if (err) 2057 goto unlock; 2058 } 2059 } 2060 2061 unlock: 2062 mv88e6xxx_reg_unlock(chip); 2063 2064 return err; 2065 } 2066 2067 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2068 const unsigned char *addr, u16 vid) 2069 { 2070 struct mv88e6xxx_chip *chip = ds->priv; 2071 int err; 2072 2073 mv88e6xxx_reg_lock(chip); 2074 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2075 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2076 mv88e6xxx_reg_unlock(chip); 2077 2078 return err; 2079 } 2080 2081 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2082 const unsigned char *addr, u16 vid) 2083 { 2084 struct mv88e6xxx_chip *chip = ds->priv; 2085 int err; 2086 2087 mv88e6xxx_reg_lock(chip); 2088 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2089 mv88e6xxx_reg_unlock(chip); 2090 2091 return err; 2092 } 2093 2094 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2095 u16 fid, u16 vid, int port, 2096 dsa_fdb_dump_cb_t *cb, void *data) 2097 { 2098 struct mv88e6xxx_atu_entry addr; 2099 bool is_static; 2100 int err; 2101 2102 addr.state = 0; 2103 eth_broadcast_addr(addr.mac); 2104 2105 do { 2106 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2107 if (err) 2108 return err; 2109 2110 if (!addr.state) 2111 break; 2112 2113 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2114 continue; 2115 2116 if (!is_unicast_ether_addr(addr.mac)) 2117 continue; 2118 2119 is_static = (addr.state == 2120 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2121 err = cb(addr.mac, vid, is_static, data); 2122 if (err) 2123 return err; 2124 } while (!is_broadcast_ether_addr(addr.mac)); 2125 2126 return err; 2127 } 2128 2129 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2130 dsa_fdb_dump_cb_t *cb, void *data) 2131 { 2132 struct mv88e6xxx_vtu_entry vlan; 2133 u16 fid; 2134 int err; 2135 2136 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2137 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2138 if (err) 2139 return err; 2140 2141 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2142 if (err) 2143 return err; 2144 2145 /* Dump VLANs' Filtering Information Databases */ 2146 vlan.vid = chip->info->max_vid; 2147 vlan.valid = false; 2148 2149 do { 2150 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2151 if (err) 2152 return err; 2153 2154 if (!vlan.valid) 2155 break; 2156 2157 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2158 cb, data); 2159 if (err) 2160 return err; 2161 } while (vlan.vid < chip->info->max_vid); 2162 2163 return err; 2164 } 2165 2166 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2167 dsa_fdb_dump_cb_t *cb, void *data) 2168 { 2169 struct mv88e6xxx_chip *chip = ds->priv; 2170 int err; 2171 2172 mv88e6xxx_reg_lock(chip); 2173 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2174 mv88e6xxx_reg_unlock(chip); 2175 2176 return err; 2177 } 2178 2179 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2180 struct net_device *br) 2181 { 2182 struct dsa_switch *ds = chip->ds; 2183 struct dsa_switch_tree *dst = ds->dst; 2184 struct dsa_port *dp; 2185 int err; 2186 2187 list_for_each_entry(dp, &dst->ports, list) { 2188 if (dp->bridge_dev == br) { 2189 if (dp->ds == ds) { 2190 /* This is a local bridge group member, 2191 * remap its Port VLAN Map. 2192 */ 2193 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2194 if (err) 2195 return err; 2196 } else { 2197 /* This is an external bridge group member, 2198 * remap its cross-chip Port VLAN Table entry. 2199 */ 2200 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2201 dp->index); 2202 if (err) 2203 return err; 2204 } 2205 } 2206 } 2207 2208 return 0; 2209 } 2210 2211 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2212 struct net_device *br) 2213 { 2214 struct mv88e6xxx_chip *chip = ds->priv; 2215 int err; 2216 2217 mv88e6xxx_reg_lock(chip); 2218 err = mv88e6xxx_bridge_map(chip, br); 2219 mv88e6xxx_reg_unlock(chip); 2220 2221 return err; 2222 } 2223 2224 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2225 struct net_device *br) 2226 { 2227 struct mv88e6xxx_chip *chip = ds->priv; 2228 2229 mv88e6xxx_reg_lock(chip); 2230 if (mv88e6xxx_bridge_map(chip, br) || 2231 mv88e6xxx_port_vlan_map(chip, port)) 2232 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2233 mv88e6xxx_reg_unlock(chip); 2234 } 2235 2236 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2237 int tree_index, int sw_index, 2238 int port, struct net_device *br) 2239 { 2240 struct mv88e6xxx_chip *chip = ds->priv; 2241 int err; 2242 2243 if (tree_index != ds->dst->index) 2244 return 0; 2245 2246 mv88e6xxx_reg_lock(chip); 2247 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2248 mv88e6xxx_reg_unlock(chip); 2249 2250 return err; 2251 } 2252 2253 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2254 int tree_index, int sw_index, 2255 int port, struct net_device *br) 2256 { 2257 struct mv88e6xxx_chip *chip = ds->priv; 2258 2259 if (tree_index != ds->dst->index) 2260 return; 2261 2262 mv88e6xxx_reg_lock(chip); 2263 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2264 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2265 mv88e6xxx_reg_unlock(chip); 2266 } 2267 2268 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2269 { 2270 if (chip->info->ops->reset) 2271 return chip->info->ops->reset(chip); 2272 2273 return 0; 2274 } 2275 2276 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2277 { 2278 struct gpio_desc *gpiod = chip->reset; 2279 2280 /* If there is a GPIO connected to the reset pin, toggle it */ 2281 if (gpiod) { 2282 gpiod_set_value_cansleep(gpiod, 1); 2283 usleep_range(10000, 20000); 2284 gpiod_set_value_cansleep(gpiod, 0); 2285 usleep_range(10000, 20000); 2286 } 2287 } 2288 2289 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2290 { 2291 int i, err; 2292 2293 /* Set all ports to the Disabled state */ 2294 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2295 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2296 if (err) 2297 return err; 2298 } 2299 2300 /* Wait for transmit queues to drain, 2301 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2302 */ 2303 usleep_range(2000, 4000); 2304 2305 return 0; 2306 } 2307 2308 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2309 { 2310 int err; 2311 2312 err = mv88e6xxx_disable_ports(chip); 2313 if (err) 2314 return err; 2315 2316 mv88e6xxx_hardware_reset(chip); 2317 2318 return mv88e6xxx_software_reset(chip); 2319 } 2320 2321 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2322 enum mv88e6xxx_frame_mode frame, 2323 enum mv88e6xxx_egress_mode egress, u16 etype) 2324 { 2325 int err; 2326 2327 if (!chip->info->ops->port_set_frame_mode) 2328 return -EOPNOTSUPP; 2329 2330 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2331 if (err) 2332 return err; 2333 2334 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2335 if (err) 2336 return err; 2337 2338 if (chip->info->ops->port_set_ether_type) 2339 return chip->info->ops->port_set_ether_type(chip, port, etype); 2340 2341 return 0; 2342 } 2343 2344 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2345 { 2346 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2347 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2348 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2349 } 2350 2351 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2352 { 2353 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2354 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2355 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2356 } 2357 2358 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2359 { 2360 return mv88e6xxx_set_port_mode(chip, port, 2361 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2362 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2363 ETH_P_EDSA); 2364 } 2365 2366 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2367 { 2368 if (dsa_is_dsa_port(chip->ds, port)) 2369 return mv88e6xxx_set_port_mode_dsa(chip, port); 2370 2371 if (dsa_is_user_port(chip->ds, port)) 2372 return mv88e6xxx_set_port_mode_normal(chip, port); 2373 2374 /* Setup CPU port mode depending on its supported tag format */ 2375 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2376 return mv88e6xxx_set_port_mode_dsa(chip, port); 2377 2378 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2379 return mv88e6xxx_set_port_mode_edsa(chip, port); 2380 2381 return -EINVAL; 2382 } 2383 2384 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2385 { 2386 bool message = dsa_is_dsa_port(chip->ds, port); 2387 2388 return mv88e6xxx_port_set_message_port(chip, port, message); 2389 } 2390 2391 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2392 { 2393 struct dsa_switch *ds = chip->ds; 2394 bool flood; 2395 2396 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2397 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2398 if (chip->info->ops->port_set_egress_floods) 2399 return chip->info->ops->port_set_egress_floods(chip, port, 2400 flood, flood); 2401 2402 return 0; 2403 } 2404 2405 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2406 { 2407 struct mv88e6xxx_port *mvp = dev_id; 2408 struct mv88e6xxx_chip *chip = mvp->chip; 2409 irqreturn_t ret = IRQ_NONE; 2410 int port = mvp->port; 2411 u8 lane; 2412 2413 mv88e6xxx_reg_lock(chip); 2414 lane = mv88e6xxx_serdes_get_lane(chip, port); 2415 if (lane) 2416 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2417 mv88e6xxx_reg_unlock(chip); 2418 2419 return ret; 2420 } 2421 2422 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2423 u8 lane) 2424 { 2425 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2426 unsigned int irq; 2427 int err; 2428 2429 /* Nothing to request if this SERDES port has no IRQ */ 2430 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2431 if (!irq) 2432 return 0; 2433 2434 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2435 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2436 2437 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2438 mv88e6xxx_reg_unlock(chip); 2439 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2440 IRQF_ONESHOT, dev_id->serdes_irq_name, 2441 dev_id); 2442 mv88e6xxx_reg_lock(chip); 2443 if (err) 2444 return err; 2445 2446 dev_id->serdes_irq = irq; 2447 2448 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2449 } 2450 2451 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2452 u8 lane) 2453 { 2454 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2455 unsigned int irq = dev_id->serdes_irq; 2456 int err; 2457 2458 /* Nothing to free if no IRQ has been requested */ 2459 if (!irq) 2460 return 0; 2461 2462 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2463 2464 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2465 mv88e6xxx_reg_unlock(chip); 2466 free_irq(irq, dev_id); 2467 mv88e6xxx_reg_lock(chip); 2468 2469 dev_id->serdes_irq = 0; 2470 2471 return err; 2472 } 2473 2474 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2475 bool on) 2476 { 2477 u8 lane; 2478 int err; 2479 2480 lane = mv88e6xxx_serdes_get_lane(chip, port); 2481 if (!lane) 2482 return 0; 2483 2484 if (on) { 2485 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2486 if (err) 2487 return err; 2488 2489 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2490 } else { 2491 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2492 if (err) 2493 return err; 2494 2495 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2496 } 2497 2498 return err; 2499 } 2500 2501 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2502 { 2503 struct dsa_switch *ds = chip->ds; 2504 int upstream_port; 2505 int err; 2506 2507 upstream_port = dsa_upstream_port(ds, port); 2508 if (chip->info->ops->port_set_upstream_port) { 2509 err = chip->info->ops->port_set_upstream_port(chip, port, 2510 upstream_port); 2511 if (err) 2512 return err; 2513 } 2514 2515 if (port == upstream_port) { 2516 if (chip->info->ops->set_cpu_port) { 2517 err = chip->info->ops->set_cpu_port(chip, 2518 upstream_port); 2519 if (err) 2520 return err; 2521 } 2522 2523 if (chip->info->ops->set_egress_port) { 2524 err = chip->info->ops->set_egress_port(chip, 2525 MV88E6XXX_EGRESS_DIR_INGRESS, 2526 upstream_port); 2527 if (err) 2528 return err; 2529 2530 err = chip->info->ops->set_egress_port(chip, 2531 MV88E6XXX_EGRESS_DIR_EGRESS, 2532 upstream_port); 2533 if (err) 2534 return err; 2535 } 2536 } 2537 2538 return 0; 2539 } 2540 2541 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2542 { 2543 struct dsa_switch *ds = chip->ds; 2544 int err; 2545 u16 reg; 2546 2547 chip->ports[port].chip = chip; 2548 chip->ports[port].port = port; 2549 2550 /* MAC Forcing register: don't force link, speed, duplex or flow control 2551 * state to any particular values on physical ports, but force the CPU 2552 * port and all DSA ports to their maximum bandwidth and full duplex. 2553 */ 2554 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2555 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2556 SPEED_MAX, DUPLEX_FULL, 2557 PAUSE_OFF, 2558 PHY_INTERFACE_MODE_NA); 2559 else 2560 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2561 SPEED_UNFORCED, DUPLEX_UNFORCED, 2562 PAUSE_ON, 2563 PHY_INTERFACE_MODE_NA); 2564 if (err) 2565 return err; 2566 2567 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2568 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2569 * tunneling, determine priority by looking at 802.1p and IP 2570 * priority fields (IP prio has precedence), and set STP state 2571 * to Forwarding. 2572 * 2573 * If this is the CPU link, use DSA or EDSA tagging depending 2574 * on which tagging mode was configured. 2575 * 2576 * If this is a link to another switch, use DSA tagging mode. 2577 * 2578 * If this is the upstream port for this switch, enable 2579 * forwarding of unknown unicasts and multicasts. 2580 */ 2581 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2582 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2583 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2584 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2585 if (err) 2586 return err; 2587 2588 err = mv88e6xxx_setup_port_mode(chip, port); 2589 if (err) 2590 return err; 2591 2592 err = mv88e6xxx_setup_egress_floods(chip, port); 2593 if (err) 2594 return err; 2595 2596 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2597 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2598 * untagged frames on this port, do a destination address lookup on all 2599 * received packets as usual, disable ARP mirroring and don't send a 2600 * copy of all transmitted/received frames on this port to the CPU. 2601 */ 2602 err = mv88e6xxx_port_set_map_da(chip, port); 2603 if (err) 2604 return err; 2605 2606 err = mv88e6xxx_setup_upstream_port(chip, port); 2607 if (err) 2608 return err; 2609 2610 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2611 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2612 if (err) 2613 return err; 2614 2615 if (chip->info->ops->port_set_jumbo_size) { 2616 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2617 if (err) 2618 return err; 2619 } 2620 2621 /* Port Association Vector: when learning source addresses 2622 * of packets, add the address to the address database using 2623 * a port bitmap that has only the bit for this port set and 2624 * the other bits clear. 2625 */ 2626 reg = 1 << port; 2627 /* Disable learning for CPU port */ 2628 if (dsa_is_cpu_port(ds, port)) 2629 reg = 0; 2630 2631 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2632 reg); 2633 if (err) 2634 return err; 2635 2636 /* Egress rate control 2: disable egress rate control. */ 2637 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2638 0x0000); 2639 if (err) 2640 return err; 2641 2642 if (chip->info->ops->port_pause_limit) { 2643 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2644 if (err) 2645 return err; 2646 } 2647 2648 if (chip->info->ops->port_disable_learn_limit) { 2649 err = chip->info->ops->port_disable_learn_limit(chip, port); 2650 if (err) 2651 return err; 2652 } 2653 2654 if (chip->info->ops->port_disable_pri_override) { 2655 err = chip->info->ops->port_disable_pri_override(chip, port); 2656 if (err) 2657 return err; 2658 } 2659 2660 if (chip->info->ops->port_tag_remap) { 2661 err = chip->info->ops->port_tag_remap(chip, port); 2662 if (err) 2663 return err; 2664 } 2665 2666 if (chip->info->ops->port_egress_rate_limiting) { 2667 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2668 if (err) 2669 return err; 2670 } 2671 2672 if (chip->info->ops->port_setup_message_port) { 2673 err = chip->info->ops->port_setup_message_port(chip, port); 2674 if (err) 2675 return err; 2676 } 2677 2678 /* Port based VLAN map: give each port the same default address 2679 * database, and allow bidirectional communication between the 2680 * CPU and DSA port(s), and the other ports. 2681 */ 2682 err = mv88e6xxx_port_set_fid(chip, port, 0); 2683 if (err) 2684 return err; 2685 2686 err = mv88e6xxx_port_vlan_map(chip, port); 2687 if (err) 2688 return err; 2689 2690 /* Default VLAN ID and priority: don't set a default VLAN 2691 * ID, and set the default packet priority to zero. 2692 */ 2693 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2694 } 2695 2696 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2697 struct phy_device *phydev) 2698 { 2699 struct mv88e6xxx_chip *chip = ds->priv; 2700 int err; 2701 2702 mv88e6xxx_reg_lock(chip); 2703 err = mv88e6xxx_serdes_power(chip, port, true); 2704 mv88e6xxx_reg_unlock(chip); 2705 2706 return err; 2707 } 2708 2709 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2710 { 2711 struct mv88e6xxx_chip *chip = ds->priv; 2712 2713 mv88e6xxx_reg_lock(chip); 2714 if (mv88e6xxx_serdes_power(chip, port, false)) 2715 dev_err(chip->dev, "failed to power off SERDES\n"); 2716 mv88e6xxx_reg_unlock(chip); 2717 } 2718 2719 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2720 unsigned int ageing_time) 2721 { 2722 struct mv88e6xxx_chip *chip = ds->priv; 2723 int err; 2724 2725 mv88e6xxx_reg_lock(chip); 2726 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2727 mv88e6xxx_reg_unlock(chip); 2728 2729 return err; 2730 } 2731 2732 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2733 { 2734 int err; 2735 2736 /* Initialize the statistics unit */ 2737 if (chip->info->ops->stats_set_histogram) { 2738 err = chip->info->ops->stats_set_histogram(chip); 2739 if (err) 2740 return err; 2741 } 2742 2743 return mv88e6xxx_g1_stats_clear(chip); 2744 } 2745 2746 /* Check if the errata has already been applied. */ 2747 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2748 { 2749 int port; 2750 int err; 2751 u16 val; 2752 2753 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2754 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2755 if (err) { 2756 dev_err(chip->dev, 2757 "Error reading hidden register: %d\n", err); 2758 return false; 2759 } 2760 if (val != 0x01c0) 2761 return false; 2762 } 2763 2764 return true; 2765 } 2766 2767 /* The 6390 copper ports have an errata which require poking magic 2768 * values into undocumented hidden registers and then performing a 2769 * software reset. 2770 */ 2771 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2772 { 2773 int port; 2774 int err; 2775 2776 if (mv88e6390_setup_errata_applied(chip)) 2777 return 0; 2778 2779 /* Set the ports into blocking mode */ 2780 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2781 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2782 if (err) 2783 return err; 2784 } 2785 2786 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2787 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2788 if (err) 2789 return err; 2790 } 2791 2792 return mv88e6xxx_software_reset(chip); 2793 } 2794 2795 enum mv88e6xxx_devlink_param_id { 2796 MV88E6XXX_DEVLINK_PARAM_ID_BASE = DEVLINK_PARAM_GENERIC_ID_MAX, 2797 MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2798 }; 2799 2800 static int mv88e6xxx_devlink_param_get(struct dsa_switch *ds, u32 id, 2801 struct devlink_param_gset_ctx *ctx) 2802 { 2803 struct mv88e6xxx_chip *chip = ds->priv; 2804 int err; 2805 2806 mv88e6xxx_reg_lock(chip); 2807 2808 switch (id) { 2809 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2810 err = mv88e6xxx_atu_get_hash(chip, &ctx->val.vu8); 2811 break; 2812 default: 2813 err = -EOPNOTSUPP; 2814 break; 2815 } 2816 2817 mv88e6xxx_reg_unlock(chip); 2818 2819 return err; 2820 } 2821 2822 static int mv88e6xxx_devlink_param_set(struct dsa_switch *ds, u32 id, 2823 struct devlink_param_gset_ctx *ctx) 2824 { 2825 struct mv88e6xxx_chip *chip = ds->priv; 2826 int err; 2827 2828 mv88e6xxx_reg_lock(chip); 2829 2830 switch (id) { 2831 case MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH: 2832 err = mv88e6xxx_atu_set_hash(chip, ctx->val.vu8); 2833 break; 2834 default: 2835 err = -EOPNOTSUPP; 2836 break; 2837 } 2838 2839 mv88e6xxx_reg_unlock(chip); 2840 2841 return err; 2842 } 2843 2844 static const struct devlink_param mv88e6xxx_devlink_params[] = { 2845 DSA_DEVLINK_PARAM_DRIVER(MV88E6XXX_DEVLINK_PARAM_ID_ATU_HASH, 2846 "ATU_hash", DEVLINK_PARAM_TYPE_U8, 2847 BIT(DEVLINK_PARAM_CMODE_RUNTIME)), 2848 }; 2849 2850 static int mv88e6xxx_setup_devlink_params(struct dsa_switch *ds) 2851 { 2852 return dsa_devlink_params_register(ds, mv88e6xxx_devlink_params, 2853 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2854 } 2855 2856 static void mv88e6xxx_teardown_devlink_params(struct dsa_switch *ds) 2857 { 2858 dsa_devlink_params_unregister(ds, mv88e6xxx_devlink_params, 2859 ARRAY_SIZE(mv88e6xxx_devlink_params)); 2860 } 2861 2862 enum mv88e6xxx_devlink_resource_id { 2863 MV88E6XXX_RESOURCE_ID_ATU, 2864 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2865 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2866 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2867 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2868 }; 2869 2870 static u64 mv88e6xxx_devlink_atu_bin_get(struct mv88e6xxx_chip *chip, 2871 u16 bin) 2872 { 2873 u16 occupancy = 0; 2874 int err; 2875 2876 mv88e6xxx_reg_lock(chip); 2877 2878 err = mv88e6xxx_g2_atu_stats_set(chip, MV88E6XXX_G2_ATU_STATS_MODE_ALL, 2879 bin); 2880 if (err) { 2881 dev_err(chip->dev, "failed to set ATU stats kind/bin\n"); 2882 goto unlock; 2883 } 2884 2885 err = mv88e6xxx_g1_atu_get_next(chip, 0); 2886 if (err) { 2887 dev_err(chip->dev, "failed to perform ATU get next\n"); 2888 goto unlock; 2889 } 2890 2891 err = mv88e6xxx_g2_atu_stats_get(chip, &occupancy); 2892 if (err) { 2893 dev_err(chip->dev, "failed to get ATU stats\n"); 2894 goto unlock; 2895 } 2896 2897 occupancy &= MV88E6XXX_G2_ATU_STATS_MASK; 2898 2899 unlock: 2900 mv88e6xxx_reg_unlock(chip); 2901 2902 return occupancy; 2903 } 2904 2905 static u64 mv88e6xxx_devlink_atu_bin_0_get(void *priv) 2906 { 2907 struct mv88e6xxx_chip *chip = priv; 2908 2909 return mv88e6xxx_devlink_atu_bin_get(chip, 2910 MV88E6XXX_G2_ATU_STATS_BIN_0); 2911 } 2912 2913 static u64 mv88e6xxx_devlink_atu_bin_1_get(void *priv) 2914 { 2915 struct mv88e6xxx_chip *chip = priv; 2916 2917 return mv88e6xxx_devlink_atu_bin_get(chip, 2918 MV88E6XXX_G2_ATU_STATS_BIN_1); 2919 } 2920 2921 static u64 mv88e6xxx_devlink_atu_bin_2_get(void *priv) 2922 { 2923 struct mv88e6xxx_chip *chip = priv; 2924 2925 return mv88e6xxx_devlink_atu_bin_get(chip, 2926 MV88E6XXX_G2_ATU_STATS_BIN_2); 2927 } 2928 2929 static u64 mv88e6xxx_devlink_atu_bin_3_get(void *priv) 2930 { 2931 struct mv88e6xxx_chip *chip = priv; 2932 2933 return mv88e6xxx_devlink_atu_bin_get(chip, 2934 MV88E6XXX_G2_ATU_STATS_BIN_3); 2935 } 2936 2937 static u64 mv88e6xxx_devlink_atu_get(void *priv) 2938 { 2939 return mv88e6xxx_devlink_atu_bin_0_get(priv) + 2940 mv88e6xxx_devlink_atu_bin_1_get(priv) + 2941 mv88e6xxx_devlink_atu_bin_2_get(priv) + 2942 mv88e6xxx_devlink_atu_bin_3_get(priv); 2943 } 2944 2945 static int mv88e6xxx_setup_devlink_resources(struct dsa_switch *ds) 2946 { 2947 struct devlink_resource_size_params size_params; 2948 struct mv88e6xxx_chip *chip = ds->priv; 2949 int err; 2950 2951 devlink_resource_size_params_init(&size_params, 2952 mv88e6xxx_num_macs(chip), 2953 mv88e6xxx_num_macs(chip), 2954 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2955 2956 err = dsa_devlink_resource_register(ds, "ATU", 2957 mv88e6xxx_num_macs(chip), 2958 MV88E6XXX_RESOURCE_ID_ATU, 2959 DEVLINK_RESOURCE_ID_PARENT_TOP, 2960 &size_params); 2961 if (err) 2962 goto out; 2963 2964 devlink_resource_size_params_init(&size_params, 2965 mv88e6xxx_num_macs(chip) / 4, 2966 mv88e6xxx_num_macs(chip) / 4, 2967 1, DEVLINK_RESOURCE_UNIT_ENTRY); 2968 2969 err = dsa_devlink_resource_register(ds, "ATU_bin_0", 2970 mv88e6xxx_num_macs(chip) / 4, 2971 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 2972 MV88E6XXX_RESOURCE_ID_ATU, 2973 &size_params); 2974 if (err) 2975 goto out; 2976 2977 err = dsa_devlink_resource_register(ds, "ATU_bin_1", 2978 mv88e6xxx_num_macs(chip) / 4, 2979 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 2980 MV88E6XXX_RESOURCE_ID_ATU, 2981 &size_params); 2982 if (err) 2983 goto out; 2984 2985 err = dsa_devlink_resource_register(ds, "ATU_bin_2", 2986 mv88e6xxx_num_macs(chip) / 4, 2987 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 2988 MV88E6XXX_RESOURCE_ID_ATU, 2989 &size_params); 2990 if (err) 2991 goto out; 2992 2993 err = dsa_devlink_resource_register(ds, "ATU_bin_3", 2994 mv88e6xxx_num_macs(chip) / 4, 2995 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 2996 MV88E6XXX_RESOURCE_ID_ATU, 2997 &size_params); 2998 if (err) 2999 goto out; 3000 3001 dsa_devlink_resource_occ_get_register(ds, 3002 MV88E6XXX_RESOURCE_ID_ATU, 3003 mv88e6xxx_devlink_atu_get, 3004 chip); 3005 3006 dsa_devlink_resource_occ_get_register(ds, 3007 MV88E6XXX_RESOURCE_ID_ATU_BIN_0, 3008 mv88e6xxx_devlink_atu_bin_0_get, 3009 chip); 3010 3011 dsa_devlink_resource_occ_get_register(ds, 3012 MV88E6XXX_RESOURCE_ID_ATU_BIN_1, 3013 mv88e6xxx_devlink_atu_bin_1_get, 3014 chip); 3015 3016 dsa_devlink_resource_occ_get_register(ds, 3017 MV88E6XXX_RESOURCE_ID_ATU_BIN_2, 3018 mv88e6xxx_devlink_atu_bin_2_get, 3019 chip); 3020 3021 dsa_devlink_resource_occ_get_register(ds, 3022 MV88E6XXX_RESOURCE_ID_ATU_BIN_3, 3023 mv88e6xxx_devlink_atu_bin_3_get, 3024 chip); 3025 3026 return 0; 3027 3028 out: 3029 dsa_devlink_resources_unregister(ds); 3030 return err; 3031 } 3032 3033 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3034 { 3035 mv88e6xxx_teardown_devlink_params(ds); 3036 dsa_devlink_resources_unregister(ds); 3037 } 3038 3039 static int mv88e6xxx_setup(struct dsa_switch *ds) 3040 { 3041 struct mv88e6xxx_chip *chip = ds->priv; 3042 u8 cmode; 3043 int err; 3044 int i; 3045 3046 chip->ds = ds; 3047 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3048 3049 mv88e6xxx_reg_lock(chip); 3050 3051 if (chip->info->ops->setup_errata) { 3052 err = chip->info->ops->setup_errata(chip); 3053 if (err) 3054 goto unlock; 3055 } 3056 3057 /* Cache the cmode of each port. */ 3058 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3059 if (chip->info->ops->port_get_cmode) { 3060 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3061 if (err) 3062 goto unlock; 3063 3064 chip->ports[i].cmode = cmode; 3065 } 3066 } 3067 3068 /* Setup Switch Port Registers */ 3069 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3070 if (dsa_is_unused_port(ds, i)) 3071 continue; 3072 3073 /* Prevent the use of an invalid port. */ 3074 if (mv88e6xxx_is_invalid_port(chip, i)) { 3075 dev_err(chip->dev, "port %d is invalid\n", i); 3076 err = -EINVAL; 3077 goto unlock; 3078 } 3079 3080 err = mv88e6xxx_setup_port(chip, i); 3081 if (err) 3082 goto unlock; 3083 } 3084 3085 err = mv88e6xxx_irl_setup(chip); 3086 if (err) 3087 goto unlock; 3088 3089 err = mv88e6xxx_mac_setup(chip); 3090 if (err) 3091 goto unlock; 3092 3093 err = mv88e6xxx_phy_setup(chip); 3094 if (err) 3095 goto unlock; 3096 3097 err = mv88e6xxx_vtu_setup(chip); 3098 if (err) 3099 goto unlock; 3100 3101 err = mv88e6xxx_pvt_setup(chip); 3102 if (err) 3103 goto unlock; 3104 3105 err = mv88e6xxx_atu_setup(chip); 3106 if (err) 3107 goto unlock; 3108 3109 err = mv88e6xxx_broadcast_setup(chip, 0); 3110 if (err) 3111 goto unlock; 3112 3113 err = mv88e6xxx_pot_setup(chip); 3114 if (err) 3115 goto unlock; 3116 3117 err = mv88e6xxx_rmu_setup(chip); 3118 if (err) 3119 goto unlock; 3120 3121 err = mv88e6xxx_rsvd2cpu_setup(chip); 3122 if (err) 3123 goto unlock; 3124 3125 err = mv88e6xxx_trunk_setup(chip); 3126 if (err) 3127 goto unlock; 3128 3129 err = mv88e6xxx_devmap_setup(chip); 3130 if (err) 3131 goto unlock; 3132 3133 err = mv88e6xxx_pri_setup(chip); 3134 if (err) 3135 goto unlock; 3136 3137 /* Setup PTP Hardware Clock and timestamping */ 3138 if (chip->info->ptp_support) { 3139 err = mv88e6xxx_ptp_setup(chip); 3140 if (err) 3141 goto unlock; 3142 3143 err = mv88e6xxx_hwtstamp_setup(chip); 3144 if (err) 3145 goto unlock; 3146 } 3147 3148 err = mv88e6xxx_stats_setup(chip); 3149 if (err) 3150 goto unlock; 3151 3152 unlock: 3153 mv88e6xxx_reg_unlock(chip); 3154 3155 if (err) 3156 return err; 3157 3158 /* Have to be called without holding the register lock, since 3159 * they take the devlink lock, and we later take the locks in 3160 * the reverse order when getting/setting parameters or 3161 * resource occupancy. 3162 */ 3163 err = mv88e6xxx_setup_devlink_resources(ds); 3164 if (err) 3165 return err; 3166 3167 err = mv88e6xxx_setup_devlink_params(ds); 3168 if (err) 3169 dsa_devlink_resources_unregister(ds); 3170 3171 return err; 3172 } 3173 3174 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3175 { 3176 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3177 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3178 u16 val; 3179 int err; 3180 3181 if (!chip->info->ops->phy_read) 3182 return -EOPNOTSUPP; 3183 3184 mv88e6xxx_reg_lock(chip); 3185 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3186 mv88e6xxx_reg_unlock(chip); 3187 3188 if (reg == MII_PHYSID2) { 3189 /* Some internal PHYs don't have a model number. */ 3190 if (chip->info->family != MV88E6XXX_FAMILY_6165) 3191 /* Then there is the 6165 family. It gets is 3192 * PHYs correct. But it can also have two 3193 * SERDES interfaces in the PHY address 3194 * space. And these don't have a model 3195 * number. But they are not PHYs, so we don't 3196 * want to give them something a PHY driver 3197 * will recognise. 3198 * 3199 * Use the mv88e6390 family model number 3200 * instead, for anything which really could be 3201 * a PHY, 3202 */ 3203 if (!(val & 0x3f0)) 3204 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 3205 } 3206 3207 return err ? err : val; 3208 } 3209 3210 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3211 { 3212 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3213 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3214 int err; 3215 3216 if (!chip->info->ops->phy_write) 3217 return -EOPNOTSUPP; 3218 3219 mv88e6xxx_reg_lock(chip); 3220 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3221 mv88e6xxx_reg_unlock(chip); 3222 3223 return err; 3224 } 3225 3226 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3227 struct device_node *np, 3228 bool external) 3229 { 3230 static int index; 3231 struct mv88e6xxx_mdio_bus *mdio_bus; 3232 struct mii_bus *bus; 3233 int err; 3234 3235 if (external) { 3236 mv88e6xxx_reg_lock(chip); 3237 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3238 mv88e6xxx_reg_unlock(chip); 3239 3240 if (err) 3241 return err; 3242 } 3243 3244 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3245 if (!bus) 3246 return -ENOMEM; 3247 3248 mdio_bus = bus->priv; 3249 mdio_bus->bus = bus; 3250 mdio_bus->chip = chip; 3251 INIT_LIST_HEAD(&mdio_bus->list); 3252 mdio_bus->external = external; 3253 3254 if (np) { 3255 bus->name = np->full_name; 3256 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3257 } else { 3258 bus->name = "mv88e6xxx SMI"; 3259 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3260 } 3261 3262 bus->read = mv88e6xxx_mdio_read; 3263 bus->write = mv88e6xxx_mdio_write; 3264 bus->parent = chip->dev; 3265 3266 if (!external) { 3267 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3268 if (err) 3269 return err; 3270 } 3271 3272 err = of_mdiobus_register(bus, np); 3273 if (err) { 3274 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3275 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3276 return err; 3277 } 3278 3279 if (external) 3280 list_add_tail(&mdio_bus->list, &chip->mdios); 3281 else 3282 list_add(&mdio_bus->list, &chip->mdios); 3283 3284 return 0; 3285 } 3286 3287 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 3288 { .compatible = "marvell,mv88e6xxx-mdio-external", 3289 .data = (void *)true }, 3290 { }, 3291 }; 3292 3293 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3294 3295 { 3296 struct mv88e6xxx_mdio_bus *mdio_bus; 3297 struct mii_bus *bus; 3298 3299 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3300 bus = mdio_bus->bus; 3301 3302 if (!mdio_bus->external) 3303 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3304 3305 mdiobus_unregister(bus); 3306 } 3307 } 3308 3309 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3310 struct device_node *np) 3311 { 3312 const struct of_device_id *match; 3313 struct device_node *child; 3314 int err; 3315 3316 /* Always register one mdio bus for the internal/default mdio 3317 * bus. This maybe represented in the device tree, but is 3318 * optional. 3319 */ 3320 child = of_get_child_by_name(np, "mdio"); 3321 err = mv88e6xxx_mdio_register(chip, child, false); 3322 if (err) 3323 return err; 3324 3325 /* Walk the device tree, and see if there are any other nodes 3326 * which say they are compatible with the external mdio 3327 * bus. 3328 */ 3329 for_each_available_child_of_node(np, child) { 3330 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3331 if (match) { 3332 err = mv88e6xxx_mdio_register(chip, child, true); 3333 if (err) { 3334 mv88e6xxx_mdios_unregister(chip); 3335 of_node_put(child); 3336 return err; 3337 } 3338 } 3339 } 3340 3341 return 0; 3342 } 3343 3344 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3345 { 3346 struct mv88e6xxx_chip *chip = ds->priv; 3347 3348 return chip->eeprom_len; 3349 } 3350 3351 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3352 struct ethtool_eeprom *eeprom, u8 *data) 3353 { 3354 struct mv88e6xxx_chip *chip = ds->priv; 3355 int err; 3356 3357 if (!chip->info->ops->get_eeprom) 3358 return -EOPNOTSUPP; 3359 3360 mv88e6xxx_reg_lock(chip); 3361 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3362 mv88e6xxx_reg_unlock(chip); 3363 3364 if (err) 3365 return err; 3366 3367 eeprom->magic = 0xc3ec4951; 3368 3369 return 0; 3370 } 3371 3372 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3373 struct ethtool_eeprom *eeprom, u8 *data) 3374 { 3375 struct mv88e6xxx_chip *chip = ds->priv; 3376 int err; 3377 3378 if (!chip->info->ops->set_eeprom) 3379 return -EOPNOTSUPP; 3380 3381 if (eeprom->magic != 0xc3ec4951) 3382 return -EINVAL; 3383 3384 mv88e6xxx_reg_lock(chip); 3385 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3386 mv88e6xxx_reg_unlock(chip); 3387 3388 return err; 3389 } 3390 3391 static const struct mv88e6xxx_ops mv88e6085_ops = { 3392 /* MV88E6XXX_FAMILY_6097 */ 3393 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3394 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3395 .irl_init_all = mv88e6352_g2_irl_init_all, 3396 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3397 .phy_read = mv88e6185_phy_ppu_read, 3398 .phy_write = mv88e6185_phy_ppu_write, 3399 .port_set_link = mv88e6xxx_port_set_link, 3400 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3401 .port_tag_remap = mv88e6095_port_tag_remap, 3402 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3403 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3404 .port_set_ether_type = mv88e6351_port_set_ether_type, 3405 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3406 .port_pause_limit = mv88e6097_port_pause_limit, 3407 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3408 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3409 .port_get_cmode = mv88e6185_port_get_cmode, 3410 .port_setup_message_port = mv88e6xxx_setup_message_port, 3411 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3412 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3413 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3414 .stats_get_strings = mv88e6095_stats_get_strings, 3415 .stats_get_stats = mv88e6095_stats_get_stats, 3416 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3417 .set_egress_port = mv88e6095_g1_set_egress_port, 3418 .watchdog_ops = &mv88e6097_watchdog_ops, 3419 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3420 .pot_clear = mv88e6xxx_g2_pot_clear, 3421 .ppu_enable = mv88e6185_g1_ppu_enable, 3422 .ppu_disable = mv88e6185_g1_ppu_disable, 3423 .reset = mv88e6185_g1_reset, 3424 .rmu_disable = mv88e6085_g1_rmu_disable, 3425 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3426 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3427 .phylink_validate = mv88e6185_phylink_validate, 3428 }; 3429 3430 static const struct mv88e6xxx_ops mv88e6095_ops = { 3431 /* MV88E6XXX_FAMILY_6095 */ 3432 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3433 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3434 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3435 .phy_read = mv88e6185_phy_ppu_read, 3436 .phy_write = mv88e6185_phy_ppu_write, 3437 .port_set_link = mv88e6xxx_port_set_link, 3438 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3439 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3440 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3441 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3442 .port_get_cmode = mv88e6185_port_get_cmode, 3443 .port_setup_message_port = mv88e6xxx_setup_message_port, 3444 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3445 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3446 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3447 .stats_get_strings = mv88e6095_stats_get_strings, 3448 .stats_get_stats = mv88e6095_stats_get_stats, 3449 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3450 .ppu_enable = mv88e6185_g1_ppu_enable, 3451 .ppu_disable = mv88e6185_g1_ppu_disable, 3452 .reset = mv88e6185_g1_reset, 3453 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3454 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3455 .phylink_validate = mv88e6185_phylink_validate, 3456 }; 3457 3458 static const struct mv88e6xxx_ops mv88e6097_ops = { 3459 /* MV88E6XXX_FAMILY_6097 */ 3460 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3461 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3462 .irl_init_all = mv88e6352_g2_irl_init_all, 3463 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3464 .phy_read = mv88e6xxx_g2_smi_phy_read, 3465 .phy_write = mv88e6xxx_g2_smi_phy_write, 3466 .port_set_link = mv88e6xxx_port_set_link, 3467 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3468 .port_tag_remap = mv88e6095_port_tag_remap, 3469 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3470 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3471 .port_set_ether_type = mv88e6351_port_set_ether_type, 3472 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3473 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3474 .port_pause_limit = mv88e6097_port_pause_limit, 3475 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3476 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3477 .port_get_cmode = mv88e6185_port_get_cmode, 3478 .port_setup_message_port = mv88e6xxx_setup_message_port, 3479 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3480 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3481 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3482 .stats_get_strings = mv88e6095_stats_get_strings, 3483 .stats_get_stats = mv88e6095_stats_get_stats, 3484 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3485 .set_egress_port = mv88e6095_g1_set_egress_port, 3486 .watchdog_ops = &mv88e6097_watchdog_ops, 3487 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3488 .pot_clear = mv88e6xxx_g2_pot_clear, 3489 .reset = mv88e6352_g1_reset, 3490 .rmu_disable = mv88e6085_g1_rmu_disable, 3491 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3492 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3493 .phylink_validate = mv88e6185_phylink_validate, 3494 }; 3495 3496 static const struct mv88e6xxx_ops mv88e6123_ops = { 3497 /* MV88E6XXX_FAMILY_6165 */ 3498 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3499 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3500 .irl_init_all = mv88e6352_g2_irl_init_all, 3501 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3502 .phy_read = mv88e6xxx_g2_smi_phy_read, 3503 .phy_write = mv88e6xxx_g2_smi_phy_write, 3504 .port_set_link = mv88e6xxx_port_set_link, 3505 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3506 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3507 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3508 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3509 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3510 .port_get_cmode = mv88e6185_port_get_cmode, 3511 .port_setup_message_port = mv88e6xxx_setup_message_port, 3512 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3513 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3514 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3515 .stats_get_strings = mv88e6095_stats_get_strings, 3516 .stats_get_stats = mv88e6095_stats_get_stats, 3517 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3518 .set_egress_port = mv88e6095_g1_set_egress_port, 3519 .watchdog_ops = &mv88e6097_watchdog_ops, 3520 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3521 .pot_clear = mv88e6xxx_g2_pot_clear, 3522 .reset = mv88e6352_g1_reset, 3523 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3524 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3525 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3526 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3527 .phylink_validate = mv88e6185_phylink_validate, 3528 }; 3529 3530 static const struct mv88e6xxx_ops mv88e6131_ops = { 3531 /* MV88E6XXX_FAMILY_6185 */ 3532 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3533 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3534 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3535 .phy_read = mv88e6185_phy_ppu_read, 3536 .phy_write = mv88e6185_phy_ppu_write, 3537 .port_set_link = mv88e6xxx_port_set_link, 3538 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3539 .port_tag_remap = mv88e6095_port_tag_remap, 3540 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3541 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3542 .port_set_ether_type = mv88e6351_port_set_ether_type, 3543 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3544 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3545 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3546 .port_pause_limit = mv88e6097_port_pause_limit, 3547 .port_set_pause = mv88e6185_port_set_pause, 3548 .port_get_cmode = mv88e6185_port_get_cmode, 3549 .port_setup_message_port = mv88e6xxx_setup_message_port, 3550 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3551 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3552 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3553 .stats_get_strings = mv88e6095_stats_get_strings, 3554 .stats_get_stats = mv88e6095_stats_get_stats, 3555 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3556 .set_egress_port = mv88e6095_g1_set_egress_port, 3557 .watchdog_ops = &mv88e6097_watchdog_ops, 3558 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3559 .ppu_enable = mv88e6185_g1_ppu_enable, 3560 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3561 .ppu_disable = mv88e6185_g1_ppu_disable, 3562 .reset = mv88e6185_g1_reset, 3563 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3564 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3565 .phylink_validate = mv88e6185_phylink_validate, 3566 }; 3567 3568 static const struct mv88e6xxx_ops mv88e6141_ops = { 3569 /* MV88E6XXX_FAMILY_6341 */ 3570 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3571 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3572 .irl_init_all = mv88e6352_g2_irl_init_all, 3573 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3574 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3575 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3576 .phy_read = mv88e6xxx_g2_smi_phy_read, 3577 .phy_write = mv88e6xxx_g2_smi_phy_write, 3578 .port_set_link = mv88e6xxx_port_set_link, 3579 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3580 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3581 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3582 .port_tag_remap = mv88e6095_port_tag_remap, 3583 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3584 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3585 .port_set_ether_type = mv88e6351_port_set_ether_type, 3586 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3587 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3588 .port_pause_limit = mv88e6097_port_pause_limit, 3589 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3590 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3591 .port_get_cmode = mv88e6352_port_get_cmode, 3592 .port_set_cmode = mv88e6341_port_set_cmode, 3593 .port_setup_message_port = mv88e6xxx_setup_message_port, 3594 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3595 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3596 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3597 .stats_get_strings = mv88e6320_stats_get_strings, 3598 .stats_get_stats = mv88e6390_stats_get_stats, 3599 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3600 .set_egress_port = mv88e6390_g1_set_egress_port, 3601 .watchdog_ops = &mv88e6390_watchdog_ops, 3602 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3603 .pot_clear = mv88e6xxx_g2_pot_clear, 3604 .reset = mv88e6352_g1_reset, 3605 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3606 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3607 .serdes_power = mv88e6390_serdes_power, 3608 .serdes_get_lane = mv88e6341_serdes_get_lane, 3609 /* Check status register pause & lpa register */ 3610 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3611 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3612 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3613 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3614 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3615 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3616 .serdes_irq_status = mv88e6390_serdes_irq_status, 3617 .gpio_ops = &mv88e6352_gpio_ops, 3618 .phylink_validate = mv88e6341_phylink_validate, 3619 }; 3620 3621 static const struct mv88e6xxx_ops mv88e6161_ops = { 3622 /* MV88E6XXX_FAMILY_6165 */ 3623 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3624 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3625 .irl_init_all = mv88e6352_g2_irl_init_all, 3626 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3627 .phy_read = mv88e6xxx_g2_smi_phy_read, 3628 .phy_write = mv88e6xxx_g2_smi_phy_write, 3629 .port_set_link = mv88e6xxx_port_set_link, 3630 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3631 .port_tag_remap = mv88e6095_port_tag_remap, 3632 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3633 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3634 .port_set_ether_type = mv88e6351_port_set_ether_type, 3635 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3636 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3637 .port_pause_limit = mv88e6097_port_pause_limit, 3638 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3639 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3640 .port_get_cmode = mv88e6185_port_get_cmode, 3641 .port_setup_message_port = mv88e6xxx_setup_message_port, 3642 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3643 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3644 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3645 .stats_get_strings = mv88e6095_stats_get_strings, 3646 .stats_get_stats = mv88e6095_stats_get_stats, 3647 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3648 .set_egress_port = mv88e6095_g1_set_egress_port, 3649 .watchdog_ops = &mv88e6097_watchdog_ops, 3650 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3651 .pot_clear = mv88e6xxx_g2_pot_clear, 3652 .reset = mv88e6352_g1_reset, 3653 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3654 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3655 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3656 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3657 .avb_ops = &mv88e6165_avb_ops, 3658 .ptp_ops = &mv88e6165_ptp_ops, 3659 .phylink_validate = mv88e6185_phylink_validate, 3660 }; 3661 3662 static const struct mv88e6xxx_ops mv88e6165_ops = { 3663 /* MV88E6XXX_FAMILY_6165 */ 3664 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3665 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3666 .irl_init_all = mv88e6352_g2_irl_init_all, 3667 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3668 .phy_read = mv88e6165_phy_read, 3669 .phy_write = mv88e6165_phy_write, 3670 .port_set_link = mv88e6xxx_port_set_link, 3671 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3672 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3673 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3674 .port_get_cmode = mv88e6185_port_get_cmode, 3675 .port_setup_message_port = mv88e6xxx_setup_message_port, 3676 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3677 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3678 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3679 .stats_get_strings = mv88e6095_stats_get_strings, 3680 .stats_get_stats = mv88e6095_stats_get_stats, 3681 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3682 .set_egress_port = mv88e6095_g1_set_egress_port, 3683 .watchdog_ops = &mv88e6097_watchdog_ops, 3684 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3685 .pot_clear = mv88e6xxx_g2_pot_clear, 3686 .reset = mv88e6352_g1_reset, 3687 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3688 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3689 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3690 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3691 .avb_ops = &mv88e6165_avb_ops, 3692 .ptp_ops = &mv88e6165_ptp_ops, 3693 .phylink_validate = mv88e6185_phylink_validate, 3694 }; 3695 3696 static const struct mv88e6xxx_ops mv88e6171_ops = { 3697 /* MV88E6XXX_FAMILY_6351 */ 3698 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3699 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3700 .irl_init_all = mv88e6352_g2_irl_init_all, 3701 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3702 .phy_read = mv88e6xxx_g2_smi_phy_read, 3703 .phy_write = mv88e6xxx_g2_smi_phy_write, 3704 .port_set_link = mv88e6xxx_port_set_link, 3705 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3706 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3707 .port_tag_remap = mv88e6095_port_tag_remap, 3708 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3709 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3710 .port_set_ether_type = mv88e6351_port_set_ether_type, 3711 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3712 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3713 .port_pause_limit = mv88e6097_port_pause_limit, 3714 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3715 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3716 .port_get_cmode = mv88e6352_port_get_cmode, 3717 .port_setup_message_port = mv88e6xxx_setup_message_port, 3718 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3719 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3720 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3721 .stats_get_strings = mv88e6095_stats_get_strings, 3722 .stats_get_stats = mv88e6095_stats_get_stats, 3723 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3724 .set_egress_port = mv88e6095_g1_set_egress_port, 3725 .watchdog_ops = &mv88e6097_watchdog_ops, 3726 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3727 .pot_clear = mv88e6xxx_g2_pot_clear, 3728 .reset = mv88e6352_g1_reset, 3729 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3730 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3731 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3732 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3733 .phylink_validate = mv88e6185_phylink_validate, 3734 }; 3735 3736 static const struct mv88e6xxx_ops mv88e6172_ops = { 3737 /* MV88E6XXX_FAMILY_6352 */ 3738 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3739 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3740 .irl_init_all = mv88e6352_g2_irl_init_all, 3741 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3742 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3743 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3744 .phy_read = mv88e6xxx_g2_smi_phy_read, 3745 .phy_write = mv88e6xxx_g2_smi_phy_write, 3746 .port_set_link = mv88e6xxx_port_set_link, 3747 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3748 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3749 .port_tag_remap = mv88e6095_port_tag_remap, 3750 .port_set_policy = mv88e6352_port_set_policy, 3751 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3752 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3753 .port_set_ether_type = mv88e6351_port_set_ether_type, 3754 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3755 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3756 .port_pause_limit = mv88e6097_port_pause_limit, 3757 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3758 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3759 .port_get_cmode = mv88e6352_port_get_cmode, 3760 .port_setup_message_port = mv88e6xxx_setup_message_port, 3761 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3762 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3763 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3764 .stats_get_strings = mv88e6095_stats_get_strings, 3765 .stats_get_stats = mv88e6095_stats_get_stats, 3766 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3767 .set_egress_port = mv88e6095_g1_set_egress_port, 3768 .watchdog_ops = &mv88e6097_watchdog_ops, 3769 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3770 .pot_clear = mv88e6xxx_g2_pot_clear, 3771 .reset = mv88e6352_g1_reset, 3772 .rmu_disable = mv88e6352_g1_rmu_disable, 3773 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3774 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3775 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3776 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3777 .serdes_get_lane = mv88e6352_serdes_get_lane, 3778 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3779 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3780 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3781 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3782 .serdes_power = mv88e6352_serdes_power, 3783 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3784 .serdes_get_regs = mv88e6352_serdes_get_regs, 3785 .gpio_ops = &mv88e6352_gpio_ops, 3786 .phylink_validate = mv88e6352_phylink_validate, 3787 }; 3788 3789 static const struct mv88e6xxx_ops mv88e6175_ops = { 3790 /* MV88E6XXX_FAMILY_6351 */ 3791 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3792 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3793 .irl_init_all = mv88e6352_g2_irl_init_all, 3794 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3795 .phy_read = mv88e6xxx_g2_smi_phy_read, 3796 .phy_write = mv88e6xxx_g2_smi_phy_write, 3797 .port_set_link = mv88e6xxx_port_set_link, 3798 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3799 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3800 .port_tag_remap = mv88e6095_port_tag_remap, 3801 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3802 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3803 .port_set_ether_type = mv88e6351_port_set_ether_type, 3804 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3805 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3806 .port_pause_limit = mv88e6097_port_pause_limit, 3807 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3808 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3809 .port_get_cmode = mv88e6352_port_get_cmode, 3810 .port_setup_message_port = mv88e6xxx_setup_message_port, 3811 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3812 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3813 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3814 .stats_get_strings = mv88e6095_stats_get_strings, 3815 .stats_get_stats = mv88e6095_stats_get_stats, 3816 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3817 .set_egress_port = mv88e6095_g1_set_egress_port, 3818 .watchdog_ops = &mv88e6097_watchdog_ops, 3819 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3820 .pot_clear = mv88e6xxx_g2_pot_clear, 3821 .reset = mv88e6352_g1_reset, 3822 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3823 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3824 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3825 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3826 .phylink_validate = mv88e6185_phylink_validate, 3827 }; 3828 3829 static const struct mv88e6xxx_ops mv88e6176_ops = { 3830 /* MV88E6XXX_FAMILY_6352 */ 3831 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3832 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3833 .irl_init_all = mv88e6352_g2_irl_init_all, 3834 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3835 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3836 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3837 .phy_read = mv88e6xxx_g2_smi_phy_read, 3838 .phy_write = mv88e6xxx_g2_smi_phy_write, 3839 .port_set_link = mv88e6xxx_port_set_link, 3840 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3841 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3842 .port_tag_remap = mv88e6095_port_tag_remap, 3843 .port_set_policy = mv88e6352_port_set_policy, 3844 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3845 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3846 .port_set_ether_type = mv88e6351_port_set_ether_type, 3847 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3848 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3849 .port_pause_limit = mv88e6097_port_pause_limit, 3850 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3851 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3852 .port_get_cmode = mv88e6352_port_get_cmode, 3853 .port_setup_message_port = mv88e6xxx_setup_message_port, 3854 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3855 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3856 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3857 .stats_get_strings = mv88e6095_stats_get_strings, 3858 .stats_get_stats = mv88e6095_stats_get_stats, 3859 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3860 .set_egress_port = mv88e6095_g1_set_egress_port, 3861 .watchdog_ops = &mv88e6097_watchdog_ops, 3862 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3863 .pot_clear = mv88e6xxx_g2_pot_clear, 3864 .reset = mv88e6352_g1_reset, 3865 .rmu_disable = mv88e6352_g1_rmu_disable, 3866 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3867 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3868 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3869 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3870 .serdes_get_lane = mv88e6352_serdes_get_lane, 3871 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3872 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3873 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3874 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3875 .serdes_power = mv88e6352_serdes_power, 3876 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3877 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3878 .serdes_irq_status = mv88e6352_serdes_irq_status, 3879 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3880 .serdes_get_regs = mv88e6352_serdes_get_regs, 3881 .gpio_ops = &mv88e6352_gpio_ops, 3882 .phylink_validate = mv88e6352_phylink_validate, 3883 }; 3884 3885 static const struct mv88e6xxx_ops mv88e6185_ops = { 3886 /* MV88E6XXX_FAMILY_6185 */ 3887 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3888 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3889 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3890 .phy_read = mv88e6185_phy_ppu_read, 3891 .phy_write = mv88e6185_phy_ppu_write, 3892 .port_set_link = mv88e6xxx_port_set_link, 3893 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3894 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3895 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3896 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3897 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3898 .port_set_pause = mv88e6185_port_set_pause, 3899 .port_get_cmode = mv88e6185_port_get_cmode, 3900 .port_setup_message_port = mv88e6xxx_setup_message_port, 3901 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3902 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3903 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3904 .stats_get_strings = mv88e6095_stats_get_strings, 3905 .stats_get_stats = mv88e6095_stats_get_stats, 3906 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3907 .set_egress_port = mv88e6095_g1_set_egress_port, 3908 .watchdog_ops = &mv88e6097_watchdog_ops, 3909 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3910 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3911 .ppu_enable = mv88e6185_g1_ppu_enable, 3912 .ppu_disable = mv88e6185_g1_ppu_disable, 3913 .reset = mv88e6185_g1_reset, 3914 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3915 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3916 .phylink_validate = mv88e6185_phylink_validate, 3917 }; 3918 3919 static const struct mv88e6xxx_ops mv88e6190_ops = { 3920 /* MV88E6XXX_FAMILY_6390 */ 3921 .setup_errata = mv88e6390_setup_errata, 3922 .irl_init_all = mv88e6390_g2_irl_init_all, 3923 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3924 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3925 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3926 .phy_read = mv88e6xxx_g2_smi_phy_read, 3927 .phy_write = mv88e6xxx_g2_smi_phy_write, 3928 .port_set_link = mv88e6xxx_port_set_link, 3929 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3930 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 3931 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3932 .port_tag_remap = mv88e6390_port_tag_remap, 3933 .port_set_policy = mv88e6352_port_set_policy, 3934 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3935 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3936 .port_set_ether_type = mv88e6351_port_set_ether_type, 3937 .port_pause_limit = mv88e6390_port_pause_limit, 3938 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3939 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3940 .port_get_cmode = mv88e6352_port_get_cmode, 3941 .port_set_cmode = mv88e6390_port_set_cmode, 3942 .port_setup_message_port = mv88e6xxx_setup_message_port, 3943 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3944 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3945 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3946 .stats_get_strings = mv88e6320_stats_get_strings, 3947 .stats_get_stats = mv88e6390_stats_get_stats, 3948 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3949 .set_egress_port = mv88e6390_g1_set_egress_port, 3950 .watchdog_ops = &mv88e6390_watchdog_ops, 3951 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3952 .pot_clear = mv88e6xxx_g2_pot_clear, 3953 .reset = mv88e6352_g1_reset, 3954 .rmu_disable = mv88e6390_g1_rmu_disable, 3955 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3956 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3957 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3958 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3959 .serdes_power = mv88e6390_serdes_power, 3960 .serdes_get_lane = mv88e6390_serdes_get_lane, 3961 /* Check status register pause & lpa register */ 3962 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3963 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3964 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3965 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3966 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3967 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3968 .serdes_irq_status = mv88e6390_serdes_irq_status, 3969 .serdes_get_strings = mv88e6390_serdes_get_strings, 3970 .serdes_get_stats = mv88e6390_serdes_get_stats, 3971 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3972 .serdes_get_regs = mv88e6390_serdes_get_regs, 3973 .gpio_ops = &mv88e6352_gpio_ops, 3974 .phylink_validate = mv88e6390_phylink_validate, 3975 }; 3976 3977 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3978 /* MV88E6XXX_FAMILY_6390 */ 3979 .setup_errata = mv88e6390_setup_errata, 3980 .irl_init_all = mv88e6390_g2_irl_init_all, 3981 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3982 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3983 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3984 .phy_read = mv88e6xxx_g2_smi_phy_read, 3985 .phy_write = mv88e6xxx_g2_smi_phy_write, 3986 .port_set_link = mv88e6xxx_port_set_link, 3987 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3988 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 3989 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3990 .port_tag_remap = mv88e6390_port_tag_remap, 3991 .port_set_policy = mv88e6352_port_set_policy, 3992 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3993 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3994 .port_set_ether_type = mv88e6351_port_set_ether_type, 3995 .port_pause_limit = mv88e6390_port_pause_limit, 3996 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3997 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3998 .port_get_cmode = mv88e6352_port_get_cmode, 3999 .port_set_cmode = mv88e6390x_port_set_cmode, 4000 .port_setup_message_port = mv88e6xxx_setup_message_port, 4001 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4002 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4003 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4004 .stats_get_strings = mv88e6320_stats_get_strings, 4005 .stats_get_stats = mv88e6390_stats_get_stats, 4006 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4007 .set_egress_port = mv88e6390_g1_set_egress_port, 4008 .watchdog_ops = &mv88e6390_watchdog_ops, 4009 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4010 .pot_clear = mv88e6xxx_g2_pot_clear, 4011 .reset = mv88e6352_g1_reset, 4012 .rmu_disable = mv88e6390_g1_rmu_disable, 4013 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4014 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4015 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4016 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4017 .serdes_power = mv88e6390_serdes_power, 4018 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4019 /* Check status register pause & lpa register */ 4020 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4021 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4022 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4023 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4024 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4025 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4026 .serdes_irq_status = mv88e6390_serdes_irq_status, 4027 .serdes_get_strings = mv88e6390_serdes_get_strings, 4028 .serdes_get_stats = mv88e6390_serdes_get_stats, 4029 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4030 .serdes_get_regs = mv88e6390_serdes_get_regs, 4031 .gpio_ops = &mv88e6352_gpio_ops, 4032 .phylink_validate = mv88e6390x_phylink_validate, 4033 }; 4034 4035 static const struct mv88e6xxx_ops mv88e6191_ops = { 4036 /* MV88E6XXX_FAMILY_6390 */ 4037 .setup_errata = mv88e6390_setup_errata, 4038 .irl_init_all = mv88e6390_g2_irl_init_all, 4039 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4040 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4042 .phy_read = mv88e6xxx_g2_smi_phy_read, 4043 .phy_write = mv88e6xxx_g2_smi_phy_write, 4044 .port_set_link = mv88e6xxx_port_set_link, 4045 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4046 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4047 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4048 .port_tag_remap = mv88e6390_port_tag_remap, 4049 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4050 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4051 .port_set_ether_type = mv88e6351_port_set_ether_type, 4052 .port_pause_limit = mv88e6390_port_pause_limit, 4053 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4054 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4055 .port_get_cmode = mv88e6352_port_get_cmode, 4056 .port_set_cmode = mv88e6390_port_set_cmode, 4057 .port_setup_message_port = mv88e6xxx_setup_message_port, 4058 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4059 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4060 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4061 .stats_get_strings = mv88e6320_stats_get_strings, 4062 .stats_get_stats = mv88e6390_stats_get_stats, 4063 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4064 .set_egress_port = mv88e6390_g1_set_egress_port, 4065 .watchdog_ops = &mv88e6390_watchdog_ops, 4066 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4067 .pot_clear = mv88e6xxx_g2_pot_clear, 4068 .reset = mv88e6352_g1_reset, 4069 .rmu_disable = mv88e6390_g1_rmu_disable, 4070 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4071 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4072 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4073 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4074 .serdes_power = mv88e6390_serdes_power, 4075 .serdes_get_lane = mv88e6390_serdes_get_lane, 4076 /* Check status register pause & lpa register */ 4077 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4078 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4079 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4080 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4081 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4082 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4083 .serdes_irq_status = mv88e6390_serdes_irq_status, 4084 .serdes_get_strings = mv88e6390_serdes_get_strings, 4085 .serdes_get_stats = mv88e6390_serdes_get_stats, 4086 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4087 .serdes_get_regs = mv88e6390_serdes_get_regs, 4088 .avb_ops = &mv88e6390_avb_ops, 4089 .ptp_ops = &mv88e6352_ptp_ops, 4090 .phylink_validate = mv88e6390_phylink_validate, 4091 }; 4092 4093 static const struct mv88e6xxx_ops mv88e6240_ops = { 4094 /* MV88E6XXX_FAMILY_6352 */ 4095 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4096 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4097 .irl_init_all = mv88e6352_g2_irl_init_all, 4098 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4099 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4100 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4101 .phy_read = mv88e6xxx_g2_smi_phy_read, 4102 .phy_write = mv88e6xxx_g2_smi_phy_write, 4103 .port_set_link = mv88e6xxx_port_set_link, 4104 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4105 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4106 .port_tag_remap = mv88e6095_port_tag_remap, 4107 .port_set_policy = mv88e6352_port_set_policy, 4108 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4109 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4110 .port_set_ether_type = mv88e6351_port_set_ether_type, 4111 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4112 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4113 .port_pause_limit = mv88e6097_port_pause_limit, 4114 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4115 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4116 .port_get_cmode = mv88e6352_port_get_cmode, 4117 .port_setup_message_port = mv88e6xxx_setup_message_port, 4118 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4119 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4120 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4121 .stats_get_strings = mv88e6095_stats_get_strings, 4122 .stats_get_stats = mv88e6095_stats_get_stats, 4123 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4124 .set_egress_port = mv88e6095_g1_set_egress_port, 4125 .watchdog_ops = &mv88e6097_watchdog_ops, 4126 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4127 .pot_clear = mv88e6xxx_g2_pot_clear, 4128 .reset = mv88e6352_g1_reset, 4129 .rmu_disable = mv88e6352_g1_rmu_disable, 4130 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4131 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4132 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4133 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4134 .serdes_get_lane = mv88e6352_serdes_get_lane, 4135 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4136 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4137 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4138 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4139 .serdes_power = mv88e6352_serdes_power, 4140 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4141 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4142 .serdes_irq_status = mv88e6352_serdes_irq_status, 4143 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4144 .serdes_get_regs = mv88e6352_serdes_get_regs, 4145 .gpio_ops = &mv88e6352_gpio_ops, 4146 .avb_ops = &mv88e6352_avb_ops, 4147 .ptp_ops = &mv88e6352_ptp_ops, 4148 .phylink_validate = mv88e6352_phylink_validate, 4149 }; 4150 4151 static const struct mv88e6xxx_ops mv88e6250_ops = { 4152 /* MV88E6XXX_FAMILY_6250 */ 4153 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4154 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4155 .irl_init_all = mv88e6352_g2_irl_init_all, 4156 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4157 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4158 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4159 .phy_read = mv88e6xxx_g2_smi_phy_read, 4160 .phy_write = mv88e6xxx_g2_smi_phy_write, 4161 .port_set_link = mv88e6xxx_port_set_link, 4162 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4163 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4164 .port_tag_remap = mv88e6095_port_tag_remap, 4165 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4166 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4167 .port_set_ether_type = mv88e6351_port_set_ether_type, 4168 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4169 .port_pause_limit = mv88e6097_port_pause_limit, 4170 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4171 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4172 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4173 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4174 .stats_get_strings = mv88e6250_stats_get_strings, 4175 .stats_get_stats = mv88e6250_stats_get_stats, 4176 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4177 .set_egress_port = mv88e6095_g1_set_egress_port, 4178 .watchdog_ops = &mv88e6250_watchdog_ops, 4179 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4180 .pot_clear = mv88e6xxx_g2_pot_clear, 4181 .reset = mv88e6250_g1_reset, 4182 .vtu_getnext = mv88e6250_g1_vtu_getnext, 4183 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 4184 .avb_ops = &mv88e6352_avb_ops, 4185 .ptp_ops = &mv88e6250_ptp_ops, 4186 .phylink_validate = mv88e6065_phylink_validate, 4187 }; 4188 4189 static const struct mv88e6xxx_ops mv88e6290_ops = { 4190 /* MV88E6XXX_FAMILY_6390 */ 4191 .setup_errata = mv88e6390_setup_errata, 4192 .irl_init_all = mv88e6390_g2_irl_init_all, 4193 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4194 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4195 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4196 .phy_read = mv88e6xxx_g2_smi_phy_read, 4197 .phy_write = mv88e6xxx_g2_smi_phy_write, 4198 .port_set_link = mv88e6xxx_port_set_link, 4199 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4200 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4201 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4202 .port_tag_remap = mv88e6390_port_tag_remap, 4203 .port_set_policy = mv88e6352_port_set_policy, 4204 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4205 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4206 .port_set_ether_type = mv88e6351_port_set_ether_type, 4207 .port_pause_limit = mv88e6390_port_pause_limit, 4208 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4209 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4210 .port_get_cmode = mv88e6352_port_get_cmode, 4211 .port_set_cmode = mv88e6390_port_set_cmode, 4212 .port_setup_message_port = mv88e6xxx_setup_message_port, 4213 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4214 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4215 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4216 .stats_get_strings = mv88e6320_stats_get_strings, 4217 .stats_get_stats = mv88e6390_stats_get_stats, 4218 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4219 .set_egress_port = mv88e6390_g1_set_egress_port, 4220 .watchdog_ops = &mv88e6390_watchdog_ops, 4221 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4222 .pot_clear = mv88e6xxx_g2_pot_clear, 4223 .reset = mv88e6352_g1_reset, 4224 .rmu_disable = mv88e6390_g1_rmu_disable, 4225 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4226 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4227 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4228 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4229 .serdes_power = mv88e6390_serdes_power, 4230 .serdes_get_lane = mv88e6390_serdes_get_lane, 4231 /* Check status register pause & lpa register */ 4232 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4233 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4234 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4235 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4236 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4237 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4238 .serdes_irq_status = mv88e6390_serdes_irq_status, 4239 .serdes_get_strings = mv88e6390_serdes_get_strings, 4240 .serdes_get_stats = mv88e6390_serdes_get_stats, 4241 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4242 .serdes_get_regs = mv88e6390_serdes_get_regs, 4243 .gpio_ops = &mv88e6352_gpio_ops, 4244 .avb_ops = &mv88e6390_avb_ops, 4245 .ptp_ops = &mv88e6352_ptp_ops, 4246 .phylink_validate = mv88e6390_phylink_validate, 4247 }; 4248 4249 static const struct mv88e6xxx_ops mv88e6320_ops = { 4250 /* MV88E6XXX_FAMILY_6320 */ 4251 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4252 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4253 .irl_init_all = mv88e6352_g2_irl_init_all, 4254 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4255 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4256 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4257 .phy_read = mv88e6xxx_g2_smi_phy_read, 4258 .phy_write = mv88e6xxx_g2_smi_phy_write, 4259 .port_set_link = mv88e6xxx_port_set_link, 4260 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4261 .port_tag_remap = mv88e6095_port_tag_remap, 4262 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4263 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4264 .port_set_ether_type = mv88e6351_port_set_ether_type, 4265 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4266 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4267 .port_pause_limit = mv88e6097_port_pause_limit, 4268 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4269 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4270 .port_get_cmode = mv88e6352_port_get_cmode, 4271 .port_setup_message_port = mv88e6xxx_setup_message_port, 4272 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4273 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4274 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4275 .stats_get_strings = mv88e6320_stats_get_strings, 4276 .stats_get_stats = mv88e6320_stats_get_stats, 4277 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4278 .set_egress_port = mv88e6095_g1_set_egress_port, 4279 .watchdog_ops = &mv88e6390_watchdog_ops, 4280 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4281 .pot_clear = mv88e6xxx_g2_pot_clear, 4282 .reset = mv88e6352_g1_reset, 4283 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4284 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4285 .gpio_ops = &mv88e6352_gpio_ops, 4286 .avb_ops = &mv88e6352_avb_ops, 4287 .ptp_ops = &mv88e6352_ptp_ops, 4288 .phylink_validate = mv88e6185_phylink_validate, 4289 }; 4290 4291 static const struct mv88e6xxx_ops mv88e6321_ops = { 4292 /* MV88E6XXX_FAMILY_6320 */ 4293 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4294 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4295 .irl_init_all = mv88e6352_g2_irl_init_all, 4296 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4297 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4298 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4299 .phy_read = mv88e6xxx_g2_smi_phy_read, 4300 .phy_write = mv88e6xxx_g2_smi_phy_write, 4301 .port_set_link = mv88e6xxx_port_set_link, 4302 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4303 .port_tag_remap = mv88e6095_port_tag_remap, 4304 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4305 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4306 .port_set_ether_type = mv88e6351_port_set_ether_type, 4307 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4308 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4309 .port_pause_limit = mv88e6097_port_pause_limit, 4310 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4311 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4312 .port_get_cmode = mv88e6352_port_get_cmode, 4313 .port_setup_message_port = mv88e6xxx_setup_message_port, 4314 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4315 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4316 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4317 .stats_get_strings = mv88e6320_stats_get_strings, 4318 .stats_get_stats = mv88e6320_stats_get_stats, 4319 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4320 .set_egress_port = mv88e6095_g1_set_egress_port, 4321 .watchdog_ops = &mv88e6390_watchdog_ops, 4322 .reset = mv88e6352_g1_reset, 4323 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4324 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4325 .gpio_ops = &mv88e6352_gpio_ops, 4326 .avb_ops = &mv88e6352_avb_ops, 4327 .ptp_ops = &mv88e6352_ptp_ops, 4328 .phylink_validate = mv88e6185_phylink_validate, 4329 }; 4330 4331 static const struct mv88e6xxx_ops mv88e6341_ops = { 4332 /* MV88E6XXX_FAMILY_6341 */ 4333 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4334 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4335 .irl_init_all = mv88e6352_g2_irl_init_all, 4336 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4337 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4338 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4339 .phy_read = mv88e6xxx_g2_smi_phy_read, 4340 .phy_write = mv88e6xxx_g2_smi_phy_write, 4341 .port_set_link = mv88e6xxx_port_set_link, 4342 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4343 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4344 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4345 .port_tag_remap = mv88e6095_port_tag_remap, 4346 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4347 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4348 .port_set_ether_type = mv88e6351_port_set_ether_type, 4349 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4350 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4351 .port_pause_limit = mv88e6097_port_pause_limit, 4352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4354 .port_get_cmode = mv88e6352_port_get_cmode, 4355 .port_set_cmode = mv88e6341_port_set_cmode, 4356 .port_setup_message_port = mv88e6xxx_setup_message_port, 4357 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4358 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4359 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4360 .stats_get_strings = mv88e6320_stats_get_strings, 4361 .stats_get_stats = mv88e6390_stats_get_stats, 4362 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4363 .set_egress_port = mv88e6390_g1_set_egress_port, 4364 .watchdog_ops = &mv88e6390_watchdog_ops, 4365 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4366 .pot_clear = mv88e6xxx_g2_pot_clear, 4367 .reset = mv88e6352_g1_reset, 4368 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4369 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4370 .serdes_power = mv88e6390_serdes_power, 4371 .serdes_get_lane = mv88e6341_serdes_get_lane, 4372 /* Check status register pause & lpa register */ 4373 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4374 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4375 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4376 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4377 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4378 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4379 .serdes_irq_status = mv88e6390_serdes_irq_status, 4380 .gpio_ops = &mv88e6352_gpio_ops, 4381 .avb_ops = &mv88e6390_avb_ops, 4382 .ptp_ops = &mv88e6352_ptp_ops, 4383 .phylink_validate = mv88e6341_phylink_validate, 4384 }; 4385 4386 static const struct mv88e6xxx_ops mv88e6350_ops = { 4387 /* MV88E6XXX_FAMILY_6351 */ 4388 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4389 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4390 .irl_init_all = mv88e6352_g2_irl_init_all, 4391 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4392 .phy_read = mv88e6xxx_g2_smi_phy_read, 4393 .phy_write = mv88e6xxx_g2_smi_phy_write, 4394 .port_set_link = mv88e6xxx_port_set_link, 4395 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4396 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4397 .port_tag_remap = mv88e6095_port_tag_remap, 4398 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4399 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4400 .port_set_ether_type = mv88e6351_port_set_ether_type, 4401 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4402 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4403 .port_pause_limit = mv88e6097_port_pause_limit, 4404 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4405 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4406 .port_get_cmode = mv88e6352_port_get_cmode, 4407 .port_setup_message_port = mv88e6xxx_setup_message_port, 4408 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4409 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4410 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4411 .stats_get_strings = mv88e6095_stats_get_strings, 4412 .stats_get_stats = mv88e6095_stats_get_stats, 4413 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4414 .set_egress_port = mv88e6095_g1_set_egress_port, 4415 .watchdog_ops = &mv88e6097_watchdog_ops, 4416 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4417 .pot_clear = mv88e6xxx_g2_pot_clear, 4418 .reset = mv88e6352_g1_reset, 4419 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4420 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4421 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4422 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4423 .phylink_validate = mv88e6185_phylink_validate, 4424 }; 4425 4426 static const struct mv88e6xxx_ops mv88e6351_ops = { 4427 /* MV88E6XXX_FAMILY_6351 */ 4428 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4429 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4430 .irl_init_all = mv88e6352_g2_irl_init_all, 4431 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4432 .phy_read = mv88e6xxx_g2_smi_phy_read, 4433 .phy_write = mv88e6xxx_g2_smi_phy_write, 4434 .port_set_link = mv88e6xxx_port_set_link, 4435 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4436 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4437 .port_tag_remap = mv88e6095_port_tag_remap, 4438 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4439 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4440 .port_set_ether_type = mv88e6351_port_set_ether_type, 4441 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4442 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4443 .port_pause_limit = mv88e6097_port_pause_limit, 4444 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4445 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4446 .port_get_cmode = mv88e6352_port_get_cmode, 4447 .port_setup_message_port = mv88e6xxx_setup_message_port, 4448 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4449 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4450 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4451 .stats_get_strings = mv88e6095_stats_get_strings, 4452 .stats_get_stats = mv88e6095_stats_get_stats, 4453 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4454 .set_egress_port = mv88e6095_g1_set_egress_port, 4455 .watchdog_ops = &mv88e6097_watchdog_ops, 4456 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4457 .pot_clear = mv88e6xxx_g2_pot_clear, 4458 .reset = mv88e6352_g1_reset, 4459 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4460 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4461 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4462 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4463 .avb_ops = &mv88e6352_avb_ops, 4464 .ptp_ops = &mv88e6352_ptp_ops, 4465 .phylink_validate = mv88e6185_phylink_validate, 4466 }; 4467 4468 static const struct mv88e6xxx_ops mv88e6352_ops = { 4469 /* MV88E6XXX_FAMILY_6352 */ 4470 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4471 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4472 .irl_init_all = mv88e6352_g2_irl_init_all, 4473 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4474 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4475 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4476 .phy_read = mv88e6xxx_g2_smi_phy_read, 4477 .phy_write = mv88e6xxx_g2_smi_phy_write, 4478 .port_set_link = mv88e6xxx_port_set_link, 4479 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4480 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4481 .port_tag_remap = mv88e6095_port_tag_remap, 4482 .port_set_policy = mv88e6352_port_set_policy, 4483 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4484 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4485 .port_set_ether_type = mv88e6351_port_set_ether_type, 4486 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4487 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4488 .port_pause_limit = mv88e6097_port_pause_limit, 4489 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4490 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4491 .port_get_cmode = mv88e6352_port_get_cmode, 4492 .port_setup_message_port = mv88e6xxx_setup_message_port, 4493 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4494 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4495 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4496 .stats_get_strings = mv88e6095_stats_get_strings, 4497 .stats_get_stats = mv88e6095_stats_get_stats, 4498 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4499 .set_egress_port = mv88e6095_g1_set_egress_port, 4500 .watchdog_ops = &mv88e6097_watchdog_ops, 4501 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4502 .pot_clear = mv88e6xxx_g2_pot_clear, 4503 .reset = mv88e6352_g1_reset, 4504 .rmu_disable = mv88e6352_g1_rmu_disable, 4505 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4506 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4507 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4508 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4509 .serdes_get_lane = mv88e6352_serdes_get_lane, 4510 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4511 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4512 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4513 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4514 .serdes_power = mv88e6352_serdes_power, 4515 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4516 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4517 .serdes_irq_status = mv88e6352_serdes_irq_status, 4518 .gpio_ops = &mv88e6352_gpio_ops, 4519 .avb_ops = &mv88e6352_avb_ops, 4520 .ptp_ops = &mv88e6352_ptp_ops, 4521 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4522 .serdes_get_strings = mv88e6352_serdes_get_strings, 4523 .serdes_get_stats = mv88e6352_serdes_get_stats, 4524 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4525 .serdes_get_regs = mv88e6352_serdes_get_regs, 4526 .phylink_validate = mv88e6352_phylink_validate, 4527 }; 4528 4529 static const struct mv88e6xxx_ops mv88e6390_ops = { 4530 /* MV88E6XXX_FAMILY_6390 */ 4531 .setup_errata = mv88e6390_setup_errata, 4532 .irl_init_all = mv88e6390_g2_irl_init_all, 4533 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4534 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4535 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4536 .phy_read = mv88e6xxx_g2_smi_phy_read, 4537 .phy_write = mv88e6xxx_g2_smi_phy_write, 4538 .port_set_link = mv88e6xxx_port_set_link, 4539 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4540 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4541 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4542 .port_tag_remap = mv88e6390_port_tag_remap, 4543 .port_set_policy = mv88e6352_port_set_policy, 4544 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4545 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4546 .port_set_ether_type = mv88e6351_port_set_ether_type, 4547 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4548 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4549 .port_pause_limit = mv88e6390_port_pause_limit, 4550 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4551 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4552 .port_get_cmode = mv88e6352_port_get_cmode, 4553 .port_set_cmode = mv88e6390_port_set_cmode, 4554 .port_setup_message_port = mv88e6xxx_setup_message_port, 4555 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4556 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4557 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4558 .stats_get_strings = mv88e6320_stats_get_strings, 4559 .stats_get_stats = mv88e6390_stats_get_stats, 4560 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4561 .set_egress_port = mv88e6390_g1_set_egress_port, 4562 .watchdog_ops = &mv88e6390_watchdog_ops, 4563 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4564 .pot_clear = mv88e6xxx_g2_pot_clear, 4565 .reset = mv88e6352_g1_reset, 4566 .rmu_disable = mv88e6390_g1_rmu_disable, 4567 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4568 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4569 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4570 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4571 .serdes_power = mv88e6390_serdes_power, 4572 .serdes_get_lane = mv88e6390_serdes_get_lane, 4573 /* Check status register pause & lpa register */ 4574 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4575 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4576 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4577 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4578 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4579 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4580 .serdes_irq_status = mv88e6390_serdes_irq_status, 4581 .gpio_ops = &mv88e6352_gpio_ops, 4582 .avb_ops = &mv88e6390_avb_ops, 4583 .ptp_ops = &mv88e6352_ptp_ops, 4584 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4585 .serdes_get_strings = mv88e6390_serdes_get_strings, 4586 .serdes_get_stats = mv88e6390_serdes_get_stats, 4587 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4588 .serdes_get_regs = mv88e6390_serdes_get_regs, 4589 .phylink_validate = mv88e6390_phylink_validate, 4590 }; 4591 4592 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4593 /* MV88E6XXX_FAMILY_6390 */ 4594 .setup_errata = mv88e6390_setup_errata, 4595 .irl_init_all = mv88e6390_g2_irl_init_all, 4596 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4597 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4598 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4599 .phy_read = mv88e6xxx_g2_smi_phy_read, 4600 .phy_write = mv88e6xxx_g2_smi_phy_write, 4601 .port_set_link = mv88e6xxx_port_set_link, 4602 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4603 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4604 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4605 .port_tag_remap = mv88e6390_port_tag_remap, 4606 .port_set_policy = mv88e6352_port_set_policy, 4607 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4608 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4609 .port_set_ether_type = mv88e6351_port_set_ether_type, 4610 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4611 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4612 .port_pause_limit = mv88e6390_port_pause_limit, 4613 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4614 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4615 .port_get_cmode = mv88e6352_port_get_cmode, 4616 .port_set_cmode = mv88e6390x_port_set_cmode, 4617 .port_setup_message_port = mv88e6xxx_setup_message_port, 4618 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4619 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4620 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4621 .stats_get_strings = mv88e6320_stats_get_strings, 4622 .stats_get_stats = mv88e6390_stats_get_stats, 4623 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4624 .set_egress_port = mv88e6390_g1_set_egress_port, 4625 .watchdog_ops = &mv88e6390_watchdog_ops, 4626 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4627 .pot_clear = mv88e6xxx_g2_pot_clear, 4628 .reset = mv88e6352_g1_reset, 4629 .rmu_disable = mv88e6390_g1_rmu_disable, 4630 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4631 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4632 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4633 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4634 .serdes_power = mv88e6390_serdes_power, 4635 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4636 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4637 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4638 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4639 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4640 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4641 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4642 .serdes_irq_status = mv88e6390_serdes_irq_status, 4643 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4644 .serdes_get_strings = mv88e6390_serdes_get_strings, 4645 .serdes_get_stats = mv88e6390_serdes_get_stats, 4646 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4647 .serdes_get_regs = mv88e6390_serdes_get_regs, 4648 .gpio_ops = &mv88e6352_gpio_ops, 4649 .avb_ops = &mv88e6390_avb_ops, 4650 .ptp_ops = &mv88e6352_ptp_ops, 4651 .phylink_validate = mv88e6390x_phylink_validate, 4652 }; 4653 4654 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4655 [MV88E6085] = { 4656 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4657 .family = MV88E6XXX_FAMILY_6097, 4658 .name = "Marvell 88E6085", 4659 .num_databases = 4096, 4660 .num_macs = 8192, 4661 .num_ports = 10, 4662 .num_internal_phys = 5, 4663 .max_vid = 4095, 4664 .port_base_addr = 0x10, 4665 .phy_base_addr = 0x0, 4666 .global1_addr = 0x1b, 4667 .global2_addr = 0x1c, 4668 .age_time_coeff = 15000, 4669 .g1_irqs = 8, 4670 .g2_irqs = 10, 4671 .atu_move_port_mask = 0xf, 4672 .pvt = true, 4673 .multi_chip = true, 4674 .tag_protocol = DSA_TAG_PROTO_DSA, 4675 .ops = &mv88e6085_ops, 4676 }, 4677 4678 [MV88E6095] = { 4679 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4680 .family = MV88E6XXX_FAMILY_6095, 4681 .name = "Marvell 88E6095/88E6095F", 4682 .num_databases = 256, 4683 .num_macs = 8192, 4684 .num_ports = 11, 4685 .num_internal_phys = 0, 4686 .max_vid = 4095, 4687 .port_base_addr = 0x10, 4688 .phy_base_addr = 0x0, 4689 .global1_addr = 0x1b, 4690 .global2_addr = 0x1c, 4691 .age_time_coeff = 15000, 4692 .g1_irqs = 8, 4693 .atu_move_port_mask = 0xf, 4694 .multi_chip = true, 4695 .tag_protocol = DSA_TAG_PROTO_DSA, 4696 .ops = &mv88e6095_ops, 4697 }, 4698 4699 [MV88E6097] = { 4700 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4701 .family = MV88E6XXX_FAMILY_6097, 4702 .name = "Marvell 88E6097/88E6097F", 4703 .num_databases = 4096, 4704 .num_macs = 8192, 4705 .num_ports = 11, 4706 .num_internal_phys = 8, 4707 .max_vid = 4095, 4708 .port_base_addr = 0x10, 4709 .phy_base_addr = 0x0, 4710 .global1_addr = 0x1b, 4711 .global2_addr = 0x1c, 4712 .age_time_coeff = 15000, 4713 .g1_irqs = 8, 4714 .g2_irqs = 10, 4715 .atu_move_port_mask = 0xf, 4716 .pvt = true, 4717 .multi_chip = true, 4718 .tag_protocol = DSA_TAG_PROTO_EDSA, 4719 .ops = &mv88e6097_ops, 4720 }, 4721 4722 [MV88E6123] = { 4723 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4724 .family = MV88E6XXX_FAMILY_6165, 4725 .name = "Marvell 88E6123", 4726 .num_databases = 4096, 4727 .num_macs = 1024, 4728 .num_ports = 3, 4729 .num_internal_phys = 5, 4730 .max_vid = 4095, 4731 .port_base_addr = 0x10, 4732 .phy_base_addr = 0x0, 4733 .global1_addr = 0x1b, 4734 .global2_addr = 0x1c, 4735 .age_time_coeff = 15000, 4736 .g1_irqs = 9, 4737 .g2_irqs = 10, 4738 .atu_move_port_mask = 0xf, 4739 .pvt = true, 4740 .multi_chip = true, 4741 .tag_protocol = DSA_TAG_PROTO_EDSA, 4742 .ops = &mv88e6123_ops, 4743 }, 4744 4745 [MV88E6131] = { 4746 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4747 .family = MV88E6XXX_FAMILY_6185, 4748 .name = "Marvell 88E6131", 4749 .num_databases = 256, 4750 .num_macs = 8192, 4751 .num_ports = 8, 4752 .num_internal_phys = 0, 4753 .max_vid = 4095, 4754 .port_base_addr = 0x10, 4755 .phy_base_addr = 0x0, 4756 .global1_addr = 0x1b, 4757 .global2_addr = 0x1c, 4758 .age_time_coeff = 15000, 4759 .g1_irqs = 9, 4760 .atu_move_port_mask = 0xf, 4761 .multi_chip = true, 4762 .tag_protocol = DSA_TAG_PROTO_DSA, 4763 .ops = &mv88e6131_ops, 4764 }, 4765 4766 [MV88E6141] = { 4767 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4768 .family = MV88E6XXX_FAMILY_6341, 4769 .name = "Marvell 88E6141", 4770 .num_databases = 4096, 4771 .num_macs = 2048, 4772 .num_ports = 6, 4773 .num_internal_phys = 5, 4774 .num_gpio = 11, 4775 .max_vid = 4095, 4776 .port_base_addr = 0x10, 4777 .phy_base_addr = 0x10, 4778 .global1_addr = 0x1b, 4779 .global2_addr = 0x1c, 4780 .age_time_coeff = 3750, 4781 .atu_move_port_mask = 0x1f, 4782 .g1_irqs = 9, 4783 .g2_irqs = 10, 4784 .pvt = true, 4785 .multi_chip = true, 4786 .tag_protocol = DSA_TAG_PROTO_EDSA, 4787 .ops = &mv88e6141_ops, 4788 }, 4789 4790 [MV88E6161] = { 4791 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4792 .family = MV88E6XXX_FAMILY_6165, 4793 .name = "Marvell 88E6161", 4794 .num_databases = 4096, 4795 .num_macs = 1024, 4796 .num_ports = 6, 4797 .num_internal_phys = 5, 4798 .max_vid = 4095, 4799 .port_base_addr = 0x10, 4800 .phy_base_addr = 0x0, 4801 .global1_addr = 0x1b, 4802 .global2_addr = 0x1c, 4803 .age_time_coeff = 15000, 4804 .g1_irqs = 9, 4805 .g2_irqs = 10, 4806 .atu_move_port_mask = 0xf, 4807 .pvt = true, 4808 .multi_chip = true, 4809 .tag_protocol = DSA_TAG_PROTO_EDSA, 4810 .ptp_support = true, 4811 .ops = &mv88e6161_ops, 4812 }, 4813 4814 [MV88E6165] = { 4815 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4816 .family = MV88E6XXX_FAMILY_6165, 4817 .name = "Marvell 88E6165", 4818 .num_databases = 4096, 4819 .num_macs = 8192, 4820 .num_ports = 6, 4821 .num_internal_phys = 0, 4822 .max_vid = 4095, 4823 .port_base_addr = 0x10, 4824 .phy_base_addr = 0x0, 4825 .global1_addr = 0x1b, 4826 .global2_addr = 0x1c, 4827 .age_time_coeff = 15000, 4828 .g1_irqs = 9, 4829 .g2_irqs = 10, 4830 .atu_move_port_mask = 0xf, 4831 .pvt = true, 4832 .multi_chip = true, 4833 .tag_protocol = DSA_TAG_PROTO_DSA, 4834 .ptp_support = true, 4835 .ops = &mv88e6165_ops, 4836 }, 4837 4838 [MV88E6171] = { 4839 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4840 .family = MV88E6XXX_FAMILY_6351, 4841 .name = "Marvell 88E6171", 4842 .num_databases = 4096, 4843 .num_macs = 8192, 4844 .num_ports = 7, 4845 .num_internal_phys = 5, 4846 .max_vid = 4095, 4847 .port_base_addr = 0x10, 4848 .phy_base_addr = 0x0, 4849 .global1_addr = 0x1b, 4850 .global2_addr = 0x1c, 4851 .age_time_coeff = 15000, 4852 .g1_irqs = 9, 4853 .g2_irqs = 10, 4854 .atu_move_port_mask = 0xf, 4855 .pvt = true, 4856 .multi_chip = true, 4857 .tag_protocol = DSA_TAG_PROTO_EDSA, 4858 .ops = &mv88e6171_ops, 4859 }, 4860 4861 [MV88E6172] = { 4862 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4863 .family = MV88E6XXX_FAMILY_6352, 4864 .name = "Marvell 88E6172", 4865 .num_databases = 4096, 4866 .num_macs = 8192, 4867 .num_ports = 7, 4868 .num_internal_phys = 5, 4869 .num_gpio = 15, 4870 .max_vid = 4095, 4871 .port_base_addr = 0x10, 4872 .phy_base_addr = 0x0, 4873 .global1_addr = 0x1b, 4874 .global2_addr = 0x1c, 4875 .age_time_coeff = 15000, 4876 .g1_irqs = 9, 4877 .g2_irqs = 10, 4878 .atu_move_port_mask = 0xf, 4879 .pvt = true, 4880 .multi_chip = true, 4881 .tag_protocol = DSA_TAG_PROTO_EDSA, 4882 .ops = &mv88e6172_ops, 4883 }, 4884 4885 [MV88E6175] = { 4886 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4887 .family = MV88E6XXX_FAMILY_6351, 4888 .name = "Marvell 88E6175", 4889 .num_databases = 4096, 4890 .num_macs = 8192, 4891 .num_ports = 7, 4892 .num_internal_phys = 5, 4893 .max_vid = 4095, 4894 .port_base_addr = 0x10, 4895 .phy_base_addr = 0x0, 4896 .global1_addr = 0x1b, 4897 .global2_addr = 0x1c, 4898 .age_time_coeff = 15000, 4899 .g1_irqs = 9, 4900 .g2_irqs = 10, 4901 .atu_move_port_mask = 0xf, 4902 .pvt = true, 4903 .multi_chip = true, 4904 .tag_protocol = DSA_TAG_PROTO_EDSA, 4905 .ops = &mv88e6175_ops, 4906 }, 4907 4908 [MV88E6176] = { 4909 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4910 .family = MV88E6XXX_FAMILY_6352, 4911 .name = "Marvell 88E6176", 4912 .num_databases = 4096, 4913 .num_macs = 8192, 4914 .num_ports = 7, 4915 .num_internal_phys = 5, 4916 .num_gpio = 15, 4917 .max_vid = 4095, 4918 .port_base_addr = 0x10, 4919 .phy_base_addr = 0x0, 4920 .global1_addr = 0x1b, 4921 .global2_addr = 0x1c, 4922 .age_time_coeff = 15000, 4923 .g1_irqs = 9, 4924 .g2_irqs = 10, 4925 .atu_move_port_mask = 0xf, 4926 .pvt = true, 4927 .multi_chip = true, 4928 .tag_protocol = DSA_TAG_PROTO_EDSA, 4929 .ops = &mv88e6176_ops, 4930 }, 4931 4932 [MV88E6185] = { 4933 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4934 .family = MV88E6XXX_FAMILY_6185, 4935 .name = "Marvell 88E6185", 4936 .num_databases = 256, 4937 .num_macs = 8192, 4938 .num_ports = 10, 4939 .num_internal_phys = 0, 4940 .max_vid = 4095, 4941 .port_base_addr = 0x10, 4942 .phy_base_addr = 0x0, 4943 .global1_addr = 0x1b, 4944 .global2_addr = 0x1c, 4945 .age_time_coeff = 15000, 4946 .g1_irqs = 8, 4947 .atu_move_port_mask = 0xf, 4948 .multi_chip = true, 4949 .tag_protocol = DSA_TAG_PROTO_EDSA, 4950 .ops = &mv88e6185_ops, 4951 }, 4952 4953 [MV88E6190] = { 4954 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4955 .family = MV88E6XXX_FAMILY_6390, 4956 .name = "Marvell 88E6190", 4957 .num_databases = 4096, 4958 .num_macs = 16384, 4959 .num_ports = 11, /* 10 + Z80 */ 4960 .num_internal_phys = 9, 4961 .num_gpio = 16, 4962 .max_vid = 8191, 4963 .port_base_addr = 0x0, 4964 .phy_base_addr = 0x0, 4965 .global1_addr = 0x1b, 4966 .global2_addr = 0x1c, 4967 .tag_protocol = DSA_TAG_PROTO_DSA, 4968 .age_time_coeff = 3750, 4969 .g1_irqs = 9, 4970 .g2_irqs = 14, 4971 .pvt = true, 4972 .multi_chip = true, 4973 .atu_move_port_mask = 0x1f, 4974 .ops = &mv88e6190_ops, 4975 }, 4976 4977 [MV88E6190X] = { 4978 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4979 .family = MV88E6XXX_FAMILY_6390, 4980 .name = "Marvell 88E6190X", 4981 .num_databases = 4096, 4982 .num_macs = 16384, 4983 .num_ports = 11, /* 10 + Z80 */ 4984 .num_internal_phys = 9, 4985 .num_gpio = 16, 4986 .max_vid = 8191, 4987 .port_base_addr = 0x0, 4988 .phy_base_addr = 0x0, 4989 .global1_addr = 0x1b, 4990 .global2_addr = 0x1c, 4991 .age_time_coeff = 3750, 4992 .g1_irqs = 9, 4993 .g2_irqs = 14, 4994 .atu_move_port_mask = 0x1f, 4995 .pvt = true, 4996 .multi_chip = true, 4997 .tag_protocol = DSA_TAG_PROTO_DSA, 4998 .ops = &mv88e6190x_ops, 4999 }, 5000 5001 [MV88E6191] = { 5002 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5003 .family = MV88E6XXX_FAMILY_6390, 5004 .name = "Marvell 88E6191", 5005 .num_databases = 4096, 5006 .num_macs = 16384, 5007 .num_ports = 11, /* 10 + Z80 */ 5008 .num_internal_phys = 9, 5009 .max_vid = 8191, 5010 .port_base_addr = 0x0, 5011 .phy_base_addr = 0x0, 5012 .global1_addr = 0x1b, 5013 .global2_addr = 0x1c, 5014 .age_time_coeff = 3750, 5015 .g1_irqs = 9, 5016 .g2_irqs = 14, 5017 .atu_move_port_mask = 0x1f, 5018 .pvt = true, 5019 .multi_chip = true, 5020 .tag_protocol = DSA_TAG_PROTO_DSA, 5021 .ptp_support = true, 5022 .ops = &mv88e6191_ops, 5023 }, 5024 5025 [MV88E6220] = { 5026 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5027 .family = MV88E6XXX_FAMILY_6250, 5028 .name = "Marvell 88E6220", 5029 .num_databases = 64, 5030 5031 /* Ports 2-4 are not routed to pins 5032 * => usable ports 0, 1, 5, 6 5033 */ 5034 .num_ports = 7, 5035 .num_internal_phys = 2, 5036 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5037 .max_vid = 4095, 5038 .port_base_addr = 0x08, 5039 .phy_base_addr = 0x00, 5040 .global1_addr = 0x0f, 5041 .global2_addr = 0x07, 5042 .age_time_coeff = 15000, 5043 .g1_irqs = 9, 5044 .g2_irqs = 10, 5045 .atu_move_port_mask = 0xf, 5046 .dual_chip = true, 5047 .tag_protocol = DSA_TAG_PROTO_DSA, 5048 .ptp_support = true, 5049 .ops = &mv88e6250_ops, 5050 }, 5051 5052 [MV88E6240] = { 5053 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5054 .family = MV88E6XXX_FAMILY_6352, 5055 .name = "Marvell 88E6240", 5056 .num_databases = 4096, 5057 .num_macs = 8192, 5058 .num_ports = 7, 5059 .num_internal_phys = 5, 5060 .num_gpio = 15, 5061 .max_vid = 4095, 5062 .port_base_addr = 0x10, 5063 .phy_base_addr = 0x0, 5064 .global1_addr = 0x1b, 5065 .global2_addr = 0x1c, 5066 .age_time_coeff = 15000, 5067 .g1_irqs = 9, 5068 .g2_irqs = 10, 5069 .atu_move_port_mask = 0xf, 5070 .pvt = true, 5071 .multi_chip = true, 5072 .tag_protocol = DSA_TAG_PROTO_EDSA, 5073 .ptp_support = true, 5074 .ops = &mv88e6240_ops, 5075 }, 5076 5077 [MV88E6250] = { 5078 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5079 .family = MV88E6XXX_FAMILY_6250, 5080 .name = "Marvell 88E6250", 5081 .num_databases = 64, 5082 .num_ports = 7, 5083 .num_internal_phys = 5, 5084 .max_vid = 4095, 5085 .port_base_addr = 0x08, 5086 .phy_base_addr = 0x00, 5087 .global1_addr = 0x0f, 5088 .global2_addr = 0x07, 5089 .age_time_coeff = 15000, 5090 .g1_irqs = 9, 5091 .g2_irqs = 10, 5092 .atu_move_port_mask = 0xf, 5093 .dual_chip = true, 5094 .tag_protocol = DSA_TAG_PROTO_DSA, 5095 .ptp_support = true, 5096 .ops = &mv88e6250_ops, 5097 }, 5098 5099 [MV88E6290] = { 5100 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5101 .family = MV88E6XXX_FAMILY_6390, 5102 .name = "Marvell 88E6290", 5103 .num_databases = 4096, 5104 .num_ports = 11, /* 10 + Z80 */ 5105 .num_internal_phys = 9, 5106 .num_gpio = 16, 5107 .max_vid = 8191, 5108 .port_base_addr = 0x0, 5109 .phy_base_addr = 0x0, 5110 .global1_addr = 0x1b, 5111 .global2_addr = 0x1c, 5112 .age_time_coeff = 3750, 5113 .g1_irqs = 9, 5114 .g2_irqs = 14, 5115 .atu_move_port_mask = 0x1f, 5116 .pvt = true, 5117 .multi_chip = true, 5118 .tag_protocol = DSA_TAG_PROTO_DSA, 5119 .ptp_support = true, 5120 .ops = &mv88e6290_ops, 5121 }, 5122 5123 [MV88E6320] = { 5124 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5125 .family = MV88E6XXX_FAMILY_6320, 5126 .name = "Marvell 88E6320", 5127 .num_databases = 4096, 5128 .num_macs = 8192, 5129 .num_ports = 7, 5130 .num_internal_phys = 5, 5131 .num_gpio = 15, 5132 .max_vid = 4095, 5133 .port_base_addr = 0x10, 5134 .phy_base_addr = 0x0, 5135 .global1_addr = 0x1b, 5136 .global2_addr = 0x1c, 5137 .age_time_coeff = 15000, 5138 .g1_irqs = 8, 5139 .g2_irqs = 10, 5140 .atu_move_port_mask = 0xf, 5141 .pvt = true, 5142 .multi_chip = true, 5143 .tag_protocol = DSA_TAG_PROTO_EDSA, 5144 .ptp_support = true, 5145 .ops = &mv88e6320_ops, 5146 }, 5147 5148 [MV88E6321] = { 5149 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5150 .family = MV88E6XXX_FAMILY_6320, 5151 .name = "Marvell 88E6321", 5152 .num_databases = 4096, 5153 .num_macs = 8192, 5154 .num_ports = 7, 5155 .num_internal_phys = 5, 5156 .num_gpio = 15, 5157 .max_vid = 4095, 5158 .port_base_addr = 0x10, 5159 .phy_base_addr = 0x0, 5160 .global1_addr = 0x1b, 5161 .global2_addr = 0x1c, 5162 .age_time_coeff = 15000, 5163 .g1_irqs = 8, 5164 .g2_irqs = 10, 5165 .atu_move_port_mask = 0xf, 5166 .multi_chip = true, 5167 .tag_protocol = DSA_TAG_PROTO_EDSA, 5168 .ptp_support = true, 5169 .ops = &mv88e6321_ops, 5170 }, 5171 5172 [MV88E6341] = { 5173 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5174 .family = MV88E6XXX_FAMILY_6341, 5175 .name = "Marvell 88E6341", 5176 .num_databases = 4096, 5177 .num_macs = 2048, 5178 .num_internal_phys = 5, 5179 .num_ports = 6, 5180 .num_gpio = 11, 5181 .max_vid = 4095, 5182 .port_base_addr = 0x10, 5183 .phy_base_addr = 0x10, 5184 .global1_addr = 0x1b, 5185 .global2_addr = 0x1c, 5186 .age_time_coeff = 3750, 5187 .atu_move_port_mask = 0x1f, 5188 .g1_irqs = 9, 5189 .g2_irqs = 10, 5190 .pvt = true, 5191 .multi_chip = true, 5192 .tag_protocol = DSA_TAG_PROTO_EDSA, 5193 .ptp_support = true, 5194 .ops = &mv88e6341_ops, 5195 }, 5196 5197 [MV88E6350] = { 5198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5199 .family = MV88E6XXX_FAMILY_6351, 5200 .name = "Marvell 88E6350", 5201 .num_databases = 4096, 5202 .num_macs = 8192, 5203 .num_ports = 7, 5204 .num_internal_phys = 5, 5205 .max_vid = 4095, 5206 .port_base_addr = 0x10, 5207 .phy_base_addr = 0x0, 5208 .global1_addr = 0x1b, 5209 .global2_addr = 0x1c, 5210 .age_time_coeff = 15000, 5211 .g1_irqs = 9, 5212 .g2_irqs = 10, 5213 .atu_move_port_mask = 0xf, 5214 .pvt = true, 5215 .multi_chip = true, 5216 .tag_protocol = DSA_TAG_PROTO_EDSA, 5217 .ops = &mv88e6350_ops, 5218 }, 5219 5220 [MV88E6351] = { 5221 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5222 .family = MV88E6XXX_FAMILY_6351, 5223 .name = "Marvell 88E6351", 5224 .num_databases = 4096, 5225 .num_macs = 8192, 5226 .num_ports = 7, 5227 .num_internal_phys = 5, 5228 .max_vid = 4095, 5229 .port_base_addr = 0x10, 5230 .phy_base_addr = 0x0, 5231 .global1_addr = 0x1b, 5232 .global2_addr = 0x1c, 5233 .age_time_coeff = 15000, 5234 .g1_irqs = 9, 5235 .g2_irqs = 10, 5236 .atu_move_port_mask = 0xf, 5237 .pvt = true, 5238 .multi_chip = true, 5239 .tag_protocol = DSA_TAG_PROTO_EDSA, 5240 .ops = &mv88e6351_ops, 5241 }, 5242 5243 [MV88E6352] = { 5244 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5245 .family = MV88E6XXX_FAMILY_6352, 5246 .name = "Marvell 88E6352", 5247 .num_databases = 4096, 5248 .num_macs = 8192, 5249 .num_ports = 7, 5250 .num_internal_phys = 5, 5251 .num_gpio = 15, 5252 .max_vid = 4095, 5253 .port_base_addr = 0x10, 5254 .phy_base_addr = 0x0, 5255 .global1_addr = 0x1b, 5256 .global2_addr = 0x1c, 5257 .age_time_coeff = 15000, 5258 .g1_irqs = 9, 5259 .g2_irqs = 10, 5260 .atu_move_port_mask = 0xf, 5261 .pvt = true, 5262 .multi_chip = true, 5263 .tag_protocol = DSA_TAG_PROTO_EDSA, 5264 .ptp_support = true, 5265 .ops = &mv88e6352_ops, 5266 }, 5267 [MV88E6390] = { 5268 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5269 .family = MV88E6XXX_FAMILY_6390, 5270 .name = "Marvell 88E6390", 5271 .num_databases = 4096, 5272 .num_macs = 16384, 5273 .num_ports = 11, /* 10 + Z80 */ 5274 .num_internal_phys = 9, 5275 .num_gpio = 16, 5276 .max_vid = 8191, 5277 .port_base_addr = 0x0, 5278 .phy_base_addr = 0x0, 5279 .global1_addr = 0x1b, 5280 .global2_addr = 0x1c, 5281 .age_time_coeff = 3750, 5282 .g1_irqs = 9, 5283 .g2_irqs = 14, 5284 .atu_move_port_mask = 0x1f, 5285 .pvt = true, 5286 .multi_chip = true, 5287 .tag_protocol = DSA_TAG_PROTO_DSA, 5288 .ptp_support = true, 5289 .ops = &mv88e6390_ops, 5290 }, 5291 [MV88E6390X] = { 5292 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5293 .family = MV88E6XXX_FAMILY_6390, 5294 .name = "Marvell 88E6390X", 5295 .num_databases = 4096, 5296 .num_macs = 16384, 5297 .num_ports = 11, /* 10 + Z80 */ 5298 .num_internal_phys = 9, 5299 .num_gpio = 16, 5300 .max_vid = 8191, 5301 .port_base_addr = 0x0, 5302 .phy_base_addr = 0x0, 5303 .global1_addr = 0x1b, 5304 .global2_addr = 0x1c, 5305 .age_time_coeff = 3750, 5306 .g1_irqs = 9, 5307 .g2_irqs = 14, 5308 .atu_move_port_mask = 0x1f, 5309 .pvt = true, 5310 .multi_chip = true, 5311 .tag_protocol = DSA_TAG_PROTO_DSA, 5312 .ptp_support = true, 5313 .ops = &mv88e6390x_ops, 5314 }, 5315 }; 5316 5317 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5318 { 5319 int i; 5320 5321 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5322 if (mv88e6xxx_table[i].prod_num == prod_num) 5323 return &mv88e6xxx_table[i]; 5324 5325 return NULL; 5326 } 5327 5328 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5329 { 5330 const struct mv88e6xxx_info *info; 5331 unsigned int prod_num, rev; 5332 u16 id; 5333 int err; 5334 5335 mv88e6xxx_reg_lock(chip); 5336 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5337 mv88e6xxx_reg_unlock(chip); 5338 if (err) 5339 return err; 5340 5341 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5342 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5343 5344 info = mv88e6xxx_lookup_info(prod_num); 5345 if (!info) 5346 return -ENODEV; 5347 5348 /* Update the compatible info with the probed one */ 5349 chip->info = info; 5350 5351 err = mv88e6xxx_g2_require(chip); 5352 if (err) 5353 return err; 5354 5355 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5356 chip->info->prod_num, chip->info->name, rev); 5357 5358 return 0; 5359 } 5360 5361 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5362 { 5363 struct mv88e6xxx_chip *chip; 5364 5365 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5366 if (!chip) 5367 return NULL; 5368 5369 chip->dev = dev; 5370 5371 mutex_init(&chip->reg_lock); 5372 INIT_LIST_HEAD(&chip->mdios); 5373 idr_init(&chip->policies); 5374 5375 return chip; 5376 } 5377 5378 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5379 int port, 5380 enum dsa_tag_protocol m) 5381 { 5382 struct mv88e6xxx_chip *chip = ds->priv; 5383 5384 return chip->info->tag_protocol; 5385 } 5386 5387 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 5388 const struct switchdev_obj_port_mdb *mdb) 5389 { 5390 /* We don't need any dynamic resource from the kernel (yet), 5391 * so skip the prepare phase. 5392 */ 5393 5394 return 0; 5395 } 5396 5397 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5398 const struct switchdev_obj_port_mdb *mdb) 5399 { 5400 struct mv88e6xxx_chip *chip = ds->priv; 5401 5402 mv88e6xxx_reg_lock(chip); 5403 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5404 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 5405 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 5406 port); 5407 mv88e6xxx_reg_unlock(chip); 5408 } 5409 5410 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5411 const struct switchdev_obj_port_mdb *mdb) 5412 { 5413 struct mv88e6xxx_chip *chip = ds->priv; 5414 int err; 5415 5416 mv88e6xxx_reg_lock(chip); 5417 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5418 mv88e6xxx_reg_unlock(chip); 5419 5420 return err; 5421 } 5422 5423 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5424 struct dsa_mall_mirror_tc_entry *mirror, 5425 bool ingress) 5426 { 5427 enum mv88e6xxx_egress_direction direction = ingress ? 5428 MV88E6XXX_EGRESS_DIR_INGRESS : 5429 MV88E6XXX_EGRESS_DIR_EGRESS; 5430 struct mv88e6xxx_chip *chip = ds->priv; 5431 bool other_mirrors = false; 5432 int i; 5433 int err; 5434 5435 if (!chip->info->ops->set_egress_port) 5436 return -EOPNOTSUPP; 5437 5438 mutex_lock(&chip->reg_lock); 5439 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5440 mirror->to_local_port) { 5441 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5442 other_mirrors |= ingress ? 5443 chip->ports[i].mirror_ingress : 5444 chip->ports[i].mirror_egress; 5445 5446 /* Can't change egress port when other mirror is active */ 5447 if (other_mirrors) { 5448 err = -EBUSY; 5449 goto out; 5450 } 5451 5452 err = chip->info->ops->set_egress_port(chip, 5453 direction, 5454 mirror->to_local_port); 5455 if (err) 5456 goto out; 5457 } 5458 5459 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5460 out: 5461 mutex_unlock(&chip->reg_lock); 5462 5463 return err; 5464 } 5465 5466 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5467 struct dsa_mall_mirror_tc_entry *mirror) 5468 { 5469 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5470 MV88E6XXX_EGRESS_DIR_INGRESS : 5471 MV88E6XXX_EGRESS_DIR_EGRESS; 5472 struct mv88e6xxx_chip *chip = ds->priv; 5473 bool other_mirrors = false; 5474 int i; 5475 5476 mutex_lock(&chip->reg_lock); 5477 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5478 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5479 5480 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5481 other_mirrors |= mirror->ingress ? 5482 chip->ports[i].mirror_ingress : 5483 chip->ports[i].mirror_egress; 5484 5485 /* Reset egress port when no other mirror is active */ 5486 if (!other_mirrors) { 5487 if (chip->info->ops->set_egress_port(chip, 5488 direction, 5489 dsa_upstream_port(ds, 5490 port))) 5491 dev_err(ds->dev, "failed to set egress port\n"); 5492 } 5493 5494 mutex_unlock(&chip->reg_lock); 5495 } 5496 5497 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 5498 bool unicast, bool multicast) 5499 { 5500 struct mv88e6xxx_chip *chip = ds->priv; 5501 int err = -EOPNOTSUPP; 5502 5503 mv88e6xxx_reg_lock(chip); 5504 if (chip->info->ops->port_set_egress_floods) 5505 err = chip->info->ops->port_set_egress_floods(chip, port, 5506 unicast, 5507 multicast); 5508 mv88e6xxx_reg_unlock(chip); 5509 5510 return err; 5511 } 5512 5513 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 5514 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 5515 .setup = mv88e6xxx_setup, 5516 .teardown = mv88e6xxx_teardown, 5517 .phylink_validate = mv88e6xxx_validate, 5518 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 5519 .phylink_mac_config = mv88e6xxx_mac_config, 5520 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 5521 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 5522 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 5523 .get_strings = mv88e6xxx_get_strings, 5524 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 5525 .get_sset_count = mv88e6xxx_get_sset_count, 5526 .port_enable = mv88e6xxx_port_enable, 5527 .port_disable = mv88e6xxx_port_disable, 5528 .get_mac_eee = mv88e6xxx_get_mac_eee, 5529 .set_mac_eee = mv88e6xxx_set_mac_eee, 5530 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 5531 .get_eeprom = mv88e6xxx_get_eeprom, 5532 .set_eeprom = mv88e6xxx_set_eeprom, 5533 .get_regs_len = mv88e6xxx_get_regs_len, 5534 .get_regs = mv88e6xxx_get_regs, 5535 .get_rxnfc = mv88e6xxx_get_rxnfc, 5536 .set_rxnfc = mv88e6xxx_set_rxnfc, 5537 .set_ageing_time = mv88e6xxx_set_ageing_time, 5538 .port_bridge_join = mv88e6xxx_port_bridge_join, 5539 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 5540 .port_egress_floods = mv88e6xxx_port_egress_floods, 5541 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 5542 .port_fast_age = mv88e6xxx_port_fast_age, 5543 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 5544 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 5545 .port_vlan_add = mv88e6xxx_port_vlan_add, 5546 .port_vlan_del = mv88e6xxx_port_vlan_del, 5547 .port_fdb_add = mv88e6xxx_port_fdb_add, 5548 .port_fdb_del = mv88e6xxx_port_fdb_del, 5549 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 5550 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 5551 .port_mdb_add = mv88e6xxx_port_mdb_add, 5552 .port_mdb_del = mv88e6xxx_port_mdb_del, 5553 .port_mirror_add = mv88e6xxx_port_mirror_add, 5554 .port_mirror_del = mv88e6xxx_port_mirror_del, 5555 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 5556 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 5557 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 5558 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 5559 .port_txtstamp = mv88e6xxx_port_txtstamp, 5560 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 5561 .get_ts_info = mv88e6xxx_get_ts_info, 5562 .devlink_param_get = mv88e6xxx_devlink_param_get, 5563 .devlink_param_set = mv88e6xxx_devlink_param_set, 5564 }; 5565 5566 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 5567 { 5568 struct device *dev = chip->dev; 5569 struct dsa_switch *ds; 5570 5571 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 5572 if (!ds) 5573 return -ENOMEM; 5574 5575 ds->dev = dev; 5576 ds->num_ports = mv88e6xxx_num_ports(chip); 5577 ds->priv = chip; 5578 ds->dev = dev; 5579 ds->ops = &mv88e6xxx_switch_ops; 5580 ds->ageing_time_min = chip->info->age_time_coeff; 5581 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 5582 5583 dev_set_drvdata(dev, ds); 5584 5585 return dsa_register_switch(ds); 5586 } 5587 5588 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5589 { 5590 dsa_unregister_switch(chip->ds); 5591 } 5592 5593 static const void *pdata_device_get_match_data(struct device *dev) 5594 { 5595 const struct of_device_id *matches = dev->driver->of_match_table; 5596 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5597 5598 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5599 matches++) { 5600 if (!strcmp(pdata->compatible, matches->compatible)) 5601 return matches->data; 5602 } 5603 return NULL; 5604 } 5605 5606 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5607 * would be lost after a power cycle so prevent it to be suspended. 5608 */ 5609 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5610 { 5611 return -EOPNOTSUPP; 5612 } 5613 5614 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5615 { 5616 return 0; 5617 } 5618 5619 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5620 5621 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5622 { 5623 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5624 const struct mv88e6xxx_info *compat_info = NULL; 5625 struct device *dev = &mdiodev->dev; 5626 struct device_node *np = dev->of_node; 5627 struct mv88e6xxx_chip *chip; 5628 int port; 5629 int err; 5630 5631 if (!np && !pdata) 5632 return -EINVAL; 5633 5634 if (np) 5635 compat_info = of_device_get_match_data(dev); 5636 5637 if (pdata) { 5638 compat_info = pdata_device_get_match_data(dev); 5639 5640 if (!pdata->netdev) 5641 return -EINVAL; 5642 5643 for (port = 0; port < DSA_MAX_PORTS; port++) { 5644 if (!(pdata->enabled_ports & (1 << port))) 5645 continue; 5646 if (strcmp(pdata->cd.port_names[port], "cpu")) 5647 continue; 5648 pdata->cd.netdev[port] = &pdata->netdev->dev; 5649 break; 5650 } 5651 } 5652 5653 if (!compat_info) 5654 return -EINVAL; 5655 5656 chip = mv88e6xxx_alloc_chip(dev); 5657 if (!chip) { 5658 err = -ENOMEM; 5659 goto out; 5660 } 5661 5662 chip->info = compat_info; 5663 5664 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5665 if (err) 5666 goto out; 5667 5668 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5669 if (IS_ERR(chip->reset)) { 5670 err = PTR_ERR(chip->reset); 5671 goto out; 5672 } 5673 if (chip->reset) 5674 usleep_range(1000, 2000); 5675 5676 err = mv88e6xxx_detect(chip); 5677 if (err) 5678 goto out; 5679 5680 mv88e6xxx_phy_init(chip); 5681 5682 if (chip->info->ops->get_eeprom) { 5683 if (np) 5684 of_property_read_u32(np, "eeprom-length", 5685 &chip->eeprom_len); 5686 else 5687 chip->eeprom_len = pdata->eeprom_len; 5688 } 5689 5690 mv88e6xxx_reg_lock(chip); 5691 err = mv88e6xxx_switch_reset(chip); 5692 mv88e6xxx_reg_unlock(chip); 5693 if (err) 5694 goto out; 5695 5696 if (np) { 5697 chip->irq = of_irq_get(np, 0); 5698 if (chip->irq == -EPROBE_DEFER) { 5699 err = chip->irq; 5700 goto out; 5701 } 5702 } 5703 5704 if (pdata) 5705 chip->irq = pdata->irq; 5706 5707 /* Has to be performed before the MDIO bus is created, because 5708 * the PHYs will link their interrupts to these interrupt 5709 * controllers 5710 */ 5711 mv88e6xxx_reg_lock(chip); 5712 if (chip->irq > 0) 5713 err = mv88e6xxx_g1_irq_setup(chip); 5714 else 5715 err = mv88e6xxx_irq_poll_setup(chip); 5716 mv88e6xxx_reg_unlock(chip); 5717 5718 if (err) 5719 goto out; 5720 5721 if (chip->info->g2_irqs > 0) { 5722 err = mv88e6xxx_g2_irq_setup(chip); 5723 if (err) 5724 goto out_g1_irq; 5725 } 5726 5727 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5728 if (err) 5729 goto out_g2_irq; 5730 5731 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5732 if (err) 5733 goto out_g1_atu_prob_irq; 5734 5735 err = mv88e6xxx_mdios_register(chip, np); 5736 if (err) 5737 goto out_g1_vtu_prob_irq; 5738 5739 err = mv88e6xxx_register_switch(chip); 5740 if (err) 5741 goto out_mdio; 5742 5743 return 0; 5744 5745 out_mdio: 5746 mv88e6xxx_mdios_unregister(chip); 5747 out_g1_vtu_prob_irq: 5748 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5749 out_g1_atu_prob_irq: 5750 mv88e6xxx_g1_atu_prob_irq_free(chip); 5751 out_g2_irq: 5752 if (chip->info->g2_irqs > 0) 5753 mv88e6xxx_g2_irq_free(chip); 5754 out_g1_irq: 5755 if (chip->irq > 0) 5756 mv88e6xxx_g1_irq_free(chip); 5757 else 5758 mv88e6xxx_irq_poll_free(chip); 5759 out: 5760 if (pdata) 5761 dev_put(pdata->netdev); 5762 5763 return err; 5764 } 5765 5766 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5767 { 5768 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5769 struct mv88e6xxx_chip *chip = ds->priv; 5770 5771 if (chip->info->ptp_support) { 5772 mv88e6xxx_hwtstamp_free(chip); 5773 mv88e6xxx_ptp_free(chip); 5774 } 5775 5776 mv88e6xxx_phy_destroy(chip); 5777 mv88e6xxx_unregister_switch(chip); 5778 mv88e6xxx_mdios_unregister(chip); 5779 5780 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5781 mv88e6xxx_g1_atu_prob_irq_free(chip); 5782 5783 if (chip->info->g2_irqs > 0) 5784 mv88e6xxx_g2_irq_free(chip); 5785 5786 if (chip->irq > 0) 5787 mv88e6xxx_g1_irq_free(chip); 5788 else 5789 mv88e6xxx_irq_poll_free(chip); 5790 } 5791 5792 static const struct of_device_id mv88e6xxx_of_match[] = { 5793 { 5794 .compatible = "marvell,mv88e6085", 5795 .data = &mv88e6xxx_table[MV88E6085], 5796 }, 5797 { 5798 .compatible = "marvell,mv88e6190", 5799 .data = &mv88e6xxx_table[MV88E6190], 5800 }, 5801 { 5802 .compatible = "marvell,mv88e6250", 5803 .data = &mv88e6xxx_table[MV88E6250], 5804 }, 5805 { /* sentinel */ }, 5806 }; 5807 5808 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5809 5810 static struct mdio_driver mv88e6xxx_driver = { 5811 .probe = mv88e6xxx_probe, 5812 .remove = mv88e6xxx_remove, 5813 .mdiodrv.driver = { 5814 .name = "mv88e6085", 5815 .of_match_table = mv88e6xxx_of_match, 5816 .pm = &mv88e6xxx_pm_ops, 5817 }, 5818 }; 5819 5820 mdio_module_driver(mv88e6xxx_driver); 5821 5822 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5823 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5824 MODULE_LICENSE("GPL"); 5825