1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/platform_data/mv88e6xxx.h> 32 #include <linux/netdevice.h> 33 #include <linux/gpio/consumer.h> 34 #include <linux/phy.h> 35 #include <linux/phylink.h> 36 #include <net/dsa.h> 37 38 #include "chip.h" 39 #include "global1.h" 40 #include "global2.h" 41 #include "hwtstamp.h" 42 #include "phy.h" 43 #include "port.h" 44 #include "ptp.h" 45 #include "serdes.h" 46 #include "smi.h" 47 48 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 49 { 50 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 51 dev_err(chip->dev, "Switch registers lock not held!\n"); 52 dump_stack(); 53 } 54 } 55 56 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 57 { 58 int err; 59 60 assert_reg_lock(chip); 61 62 err = mv88e6xxx_smi_read(chip, addr, reg, val); 63 if (err) 64 return err; 65 66 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 67 addr, reg, *val); 68 69 return 0; 70 } 71 72 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 73 { 74 int err; 75 76 assert_reg_lock(chip); 77 78 err = mv88e6xxx_smi_write(chip, addr, reg, val); 79 if (err) 80 return err; 81 82 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 83 addr, reg, val); 84 85 return 0; 86 } 87 88 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 89 { 90 struct mv88e6xxx_mdio_bus *mdio_bus; 91 92 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 93 list); 94 if (!mdio_bus) 95 return NULL; 96 97 return mdio_bus->bus; 98 } 99 100 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 101 { 102 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 103 unsigned int n = d->hwirq; 104 105 chip->g1_irq.masked |= (1 << n); 106 } 107 108 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 109 { 110 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 111 unsigned int n = d->hwirq; 112 113 chip->g1_irq.masked &= ~(1 << n); 114 } 115 116 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 117 { 118 unsigned int nhandled = 0; 119 unsigned int sub_irq; 120 unsigned int n; 121 u16 reg; 122 u16 ctl1; 123 int err; 124 125 mutex_lock(&chip->reg_lock); 126 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 127 mutex_unlock(&chip->reg_lock); 128 129 if (err) 130 goto out; 131 132 do { 133 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 134 if (reg & (1 << n)) { 135 sub_irq = irq_find_mapping(chip->g1_irq.domain, 136 n); 137 handle_nested_irq(sub_irq); 138 ++nhandled; 139 } 140 } 141 142 mutex_lock(&chip->reg_lock); 143 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 144 if (err) 145 goto unlock; 146 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 147 unlock: 148 mutex_unlock(&chip->reg_lock); 149 if (err) 150 goto out; 151 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 152 } while (reg & ctl1); 153 154 out: 155 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 159 { 160 struct mv88e6xxx_chip *chip = dev_id; 161 162 return mv88e6xxx_g1_irq_thread_work(chip); 163 } 164 165 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 166 { 167 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 168 169 mutex_lock(&chip->reg_lock); 170 } 171 172 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 173 { 174 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 175 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 176 u16 reg; 177 int err; 178 179 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 180 if (err) 181 goto out; 182 183 reg &= ~mask; 184 reg |= (~chip->g1_irq.masked & mask); 185 186 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 187 if (err) 188 goto out; 189 190 out: 191 mutex_unlock(&chip->reg_lock); 192 } 193 194 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 195 .name = "mv88e6xxx-g1", 196 .irq_mask = mv88e6xxx_g1_irq_mask, 197 .irq_unmask = mv88e6xxx_g1_irq_unmask, 198 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 199 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 200 }; 201 202 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 203 unsigned int irq, 204 irq_hw_number_t hwirq) 205 { 206 struct mv88e6xxx_chip *chip = d->host_data; 207 208 irq_set_chip_data(irq, d->host_data); 209 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 210 irq_set_noprobe(irq); 211 212 return 0; 213 } 214 215 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 216 .map = mv88e6xxx_g1_irq_domain_map, 217 .xlate = irq_domain_xlate_twocell, 218 }; 219 220 /* To be called with reg_lock held */ 221 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 222 { 223 int irq, virq; 224 u16 mask; 225 226 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 227 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 228 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 229 230 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 231 virq = irq_find_mapping(chip->g1_irq.domain, irq); 232 irq_dispose_mapping(virq); 233 } 234 235 irq_domain_remove(chip->g1_irq.domain); 236 } 237 238 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 239 { 240 /* 241 * free_irq must be called without reg_lock taken because the irq 242 * handler takes this lock, too. 243 */ 244 free_irq(chip->irq, chip); 245 246 mutex_lock(&chip->reg_lock); 247 mv88e6xxx_g1_irq_free_common(chip); 248 mutex_unlock(&chip->reg_lock); 249 } 250 251 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 252 { 253 int err, irq, virq; 254 u16 reg, mask; 255 256 chip->g1_irq.nirqs = chip->info->g1_irqs; 257 chip->g1_irq.domain = irq_domain_add_simple( 258 NULL, chip->g1_irq.nirqs, 0, 259 &mv88e6xxx_g1_irq_domain_ops, chip); 260 if (!chip->g1_irq.domain) 261 return -ENOMEM; 262 263 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 264 irq_create_mapping(chip->g1_irq.domain, irq); 265 266 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 267 chip->g1_irq.masked = ~0; 268 269 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 270 if (err) 271 goto out_mapping; 272 273 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 274 275 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 276 if (err) 277 goto out_disable; 278 279 /* Reading the interrupt status clears (most of) them */ 280 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 281 if (err) 282 goto out_disable; 283 284 return 0; 285 286 out_disable: 287 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 288 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 289 290 out_mapping: 291 for (irq = 0; irq < 16; irq++) { 292 virq = irq_find_mapping(chip->g1_irq.domain, irq); 293 irq_dispose_mapping(virq); 294 } 295 296 irq_domain_remove(chip->g1_irq.domain); 297 298 return err; 299 } 300 301 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 302 { 303 static struct lock_class_key lock_key; 304 static struct lock_class_key request_key; 305 int err; 306 307 err = mv88e6xxx_g1_irq_setup_common(chip); 308 if (err) 309 return err; 310 311 /* These lock classes tells lockdep that global 1 irqs are in 312 * a different category than their parent GPIO, so it won't 313 * report false recursion. 314 */ 315 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 316 317 mutex_unlock(&chip->reg_lock); 318 err = request_threaded_irq(chip->irq, NULL, 319 mv88e6xxx_g1_irq_thread_fn, 320 IRQF_ONESHOT | IRQF_SHARED, 321 dev_name(chip->dev), chip); 322 mutex_lock(&chip->reg_lock); 323 if (err) 324 mv88e6xxx_g1_irq_free_common(chip); 325 326 return err; 327 } 328 329 static void mv88e6xxx_irq_poll(struct kthread_work *work) 330 { 331 struct mv88e6xxx_chip *chip = container_of(work, 332 struct mv88e6xxx_chip, 333 irq_poll_work.work); 334 mv88e6xxx_g1_irq_thread_work(chip); 335 336 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 337 msecs_to_jiffies(100)); 338 } 339 340 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 341 { 342 int err; 343 344 err = mv88e6xxx_g1_irq_setup_common(chip); 345 if (err) 346 return err; 347 348 kthread_init_delayed_work(&chip->irq_poll_work, 349 mv88e6xxx_irq_poll); 350 351 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 352 if (IS_ERR(chip->kworker)) 353 return PTR_ERR(chip->kworker); 354 355 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 356 msecs_to_jiffies(100)); 357 358 return 0; 359 } 360 361 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 362 { 363 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 364 kthread_destroy_worker(chip->kworker); 365 366 mutex_lock(&chip->reg_lock); 367 mv88e6xxx_g1_irq_free_common(chip); 368 mutex_unlock(&chip->reg_lock); 369 } 370 371 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 372 { 373 int i; 374 375 for (i = 0; i < 16; i++) { 376 u16 val; 377 int err; 378 379 err = mv88e6xxx_read(chip, addr, reg, &val); 380 if (err) 381 return err; 382 383 if (!(val & mask)) 384 return 0; 385 386 usleep_range(1000, 2000); 387 } 388 389 dev_err(chip->dev, "Timeout while waiting for switch\n"); 390 return -ETIMEDOUT; 391 } 392 393 /* Indirect write to single pointer-data register with an Update bit */ 394 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 395 { 396 u16 val; 397 int err; 398 399 /* Wait until the previous operation is completed */ 400 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 401 if (err) 402 return err; 403 404 /* Set the Update bit to trigger a write operation */ 405 val = BIT(15) | update; 406 407 return mv88e6xxx_write(chip, addr, reg, val); 408 } 409 410 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 411 int speed, int duplex, int pause, 412 phy_interface_t mode) 413 { 414 struct phylink_link_state state; 415 int err; 416 417 if (!chip->info->ops->port_set_link) 418 return 0; 419 420 if (!chip->info->ops->port_link_state) 421 return 0; 422 423 err = chip->info->ops->port_link_state(chip, port, &state); 424 if (err) 425 return err; 426 427 /* Has anything actually changed? We don't expect the 428 * interface mode to change without one of the other 429 * parameters also changing 430 */ 431 if (state.link == link && 432 state.speed == speed && 433 state.duplex == duplex) 434 return 0; 435 436 /* Port's MAC control must not be changed unless the link is down */ 437 err = chip->info->ops->port_set_link(chip, port, 0); 438 if (err) 439 return err; 440 441 if (chip->info->ops->port_set_speed) { 442 err = chip->info->ops->port_set_speed(chip, port, speed); 443 if (err && err != -EOPNOTSUPP) 444 goto restore_link; 445 } 446 447 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 448 mode = chip->info->ops->port_max_speed_mode(port); 449 450 if (chip->info->ops->port_set_pause) { 451 err = chip->info->ops->port_set_pause(chip, port, pause); 452 if (err) 453 goto restore_link; 454 } 455 456 if (chip->info->ops->port_set_duplex) { 457 err = chip->info->ops->port_set_duplex(chip, port, duplex); 458 if (err && err != -EOPNOTSUPP) 459 goto restore_link; 460 } 461 462 if (chip->info->ops->port_set_rgmii_delay) { 463 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 464 if (err && err != -EOPNOTSUPP) 465 goto restore_link; 466 } 467 468 if (chip->info->ops->port_set_cmode) { 469 err = chip->info->ops->port_set_cmode(chip, port, mode); 470 if (err && err != -EOPNOTSUPP) 471 goto restore_link; 472 } 473 474 err = 0; 475 restore_link: 476 if (chip->info->ops->port_set_link(chip, port, link)) 477 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 478 479 return err; 480 } 481 482 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 483 { 484 struct mv88e6xxx_chip *chip = ds->priv; 485 486 return port < chip->info->num_internal_phys; 487 } 488 489 /* We expect the switch to perform auto negotiation if there is a real 490 * phy. However, in the case of a fixed link phy, we force the port 491 * settings from the fixed link settings. 492 */ 493 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 494 struct phy_device *phydev) 495 { 496 struct mv88e6xxx_chip *chip = ds->priv; 497 int err; 498 499 if (!phy_is_pseudo_fixed_link(phydev) && 500 mv88e6xxx_phy_is_internal(ds, port)) 501 return; 502 503 mutex_lock(&chip->reg_lock); 504 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 505 phydev->duplex, phydev->pause, 506 phydev->interface); 507 mutex_unlock(&chip->reg_lock); 508 509 if (err && err != -EOPNOTSUPP) 510 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 511 } 512 513 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 514 unsigned long *mask, 515 struct phylink_link_state *state) 516 { 517 if (!phy_interface_mode_is_8023z(state->interface)) { 518 /* 10M and 100M are only supported in non-802.3z mode */ 519 phylink_set(mask, 10baseT_Half); 520 phylink_set(mask, 10baseT_Full); 521 phylink_set(mask, 100baseT_Half); 522 phylink_set(mask, 100baseT_Full); 523 } 524 } 525 526 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 527 unsigned long *mask, 528 struct phylink_link_state *state) 529 { 530 /* FIXME: if the port is in 1000Base-X mode, then it only supports 531 * 1000M FD speeds. In this case, CMODE will indicate 5. 532 */ 533 phylink_set(mask, 1000baseT_Full); 534 phylink_set(mask, 1000baseX_Full); 535 536 mv88e6065_phylink_validate(chip, port, mask, state); 537 } 538 539 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 540 unsigned long *mask, 541 struct phylink_link_state *state) 542 { 543 if (port >= 5) 544 phylink_set(mask, 2500baseX_Full); 545 546 /* No ethtool bits for 200Mbps */ 547 phylink_set(mask, 1000baseT_Full); 548 phylink_set(mask, 1000baseX_Full); 549 550 mv88e6065_phylink_validate(chip, port, mask, state); 551 } 552 553 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 554 unsigned long *mask, 555 struct phylink_link_state *state) 556 { 557 /* No ethtool bits for 200Mbps */ 558 phylink_set(mask, 1000baseT_Full); 559 phylink_set(mask, 1000baseX_Full); 560 561 mv88e6065_phylink_validate(chip, port, mask, state); 562 } 563 564 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 565 unsigned long *mask, 566 struct phylink_link_state *state) 567 { 568 if (port >= 9) { 569 phylink_set(mask, 2500baseX_Full); 570 phylink_set(mask, 2500baseT_Full); 571 } 572 573 /* No ethtool bits for 200Mbps */ 574 phylink_set(mask, 1000baseT_Full); 575 phylink_set(mask, 1000baseX_Full); 576 577 mv88e6065_phylink_validate(chip, port, mask, state); 578 } 579 580 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 581 unsigned long *mask, 582 struct phylink_link_state *state) 583 { 584 if (port >= 9) { 585 phylink_set(mask, 10000baseT_Full); 586 phylink_set(mask, 10000baseKR_Full); 587 } 588 589 mv88e6390_phylink_validate(chip, port, mask, state); 590 } 591 592 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 593 unsigned long *supported, 594 struct phylink_link_state *state) 595 { 596 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 597 struct mv88e6xxx_chip *chip = ds->priv; 598 599 /* Allow all the expected bits */ 600 phylink_set(mask, Autoneg); 601 phylink_set(mask, Pause); 602 phylink_set_port_modes(mask); 603 604 if (chip->info->ops->phylink_validate) 605 chip->info->ops->phylink_validate(chip, port, mask, state); 606 607 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 608 bitmap_and(state->advertising, state->advertising, mask, 609 __ETHTOOL_LINK_MODE_MASK_NBITS); 610 611 /* We can only operate at 2500BaseX or 1000BaseX. If requested 612 * to advertise both, only report advertising at 2500BaseX. 613 */ 614 phylink_helper_basex_speed(state); 615 } 616 617 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 618 struct phylink_link_state *state) 619 { 620 struct mv88e6xxx_chip *chip = ds->priv; 621 int err; 622 623 mutex_lock(&chip->reg_lock); 624 if (chip->info->ops->port_link_state) 625 err = chip->info->ops->port_link_state(chip, port, state); 626 else 627 err = -EOPNOTSUPP; 628 mutex_unlock(&chip->reg_lock); 629 630 return err; 631 } 632 633 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 634 unsigned int mode, 635 const struct phylink_link_state *state) 636 { 637 struct mv88e6xxx_chip *chip = ds->priv; 638 int speed, duplex, link, pause, err; 639 640 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 641 return; 642 643 if (mode == MLO_AN_FIXED) { 644 link = LINK_FORCED_UP; 645 speed = state->speed; 646 duplex = state->duplex; 647 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 648 link = state->link; 649 speed = state->speed; 650 duplex = state->duplex; 651 } else { 652 speed = SPEED_UNFORCED; 653 duplex = DUPLEX_UNFORCED; 654 link = LINK_UNFORCED; 655 } 656 pause = !!phylink_test(state->advertising, Pause); 657 658 mutex_lock(&chip->reg_lock); 659 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 660 state->interface); 661 mutex_unlock(&chip->reg_lock); 662 663 if (err && err != -EOPNOTSUPP) 664 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 665 } 666 667 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 668 { 669 struct mv88e6xxx_chip *chip = ds->priv; 670 int err; 671 672 mutex_lock(&chip->reg_lock); 673 err = chip->info->ops->port_set_link(chip, port, link); 674 mutex_unlock(&chip->reg_lock); 675 676 if (err) 677 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 678 } 679 680 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 681 unsigned int mode, 682 phy_interface_t interface) 683 { 684 if (mode == MLO_AN_FIXED) 685 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 686 } 687 688 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 689 unsigned int mode, phy_interface_t interface, 690 struct phy_device *phydev) 691 { 692 if (mode == MLO_AN_FIXED) 693 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 694 } 695 696 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 697 { 698 if (!chip->info->ops->stats_snapshot) 699 return -EOPNOTSUPP; 700 701 return chip->info->ops->stats_snapshot(chip, port); 702 } 703 704 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 705 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 706 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 707 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 708 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 709 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 710 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 711 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 712 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 713 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 714 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 715 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 716 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 717 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 718 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 719 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 720 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 721 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 722 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 723 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 724 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 725 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 726 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 727 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 728 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 729 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 730 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 731 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 732 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 733 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 734 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 735 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 736 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 737 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 738 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 739 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 740 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 741 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 742 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 743 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 744 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 745 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 746 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 747 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 748 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 749 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 750 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 751 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 752 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 753 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 754 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 755 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 756 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 757 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 758 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 759 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 760 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 761 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 762 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 763 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 764 }; 765 766 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 767 struct mv88e6xxx_hw_stat *s, 768 int port, u16 bank1_select, 769 u16 histogram) 770 { 771 u32 low; 772 u32 high = 0; 773 u16 reg = 0; 774 int err; 775 u64 value; 776 777 switch (s->type) { 778 case STATS_TYPE_PORT: 779 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 780 if (err) 781 return U64_MAX; 782 783 low = reg; 784 if (s->size == 4) { 785 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 786 if (err) 787 return U64_MAX; 788 high = reg; 789 } 790 break; 791 case STATS_TYPE_BANK1: 792 reg = bank1_select; 793 /* fall through */ 794 case STATS_TYPE_BANK0: 795 reg |= s->reg | histogram; 796 mv88e6xxx_g1_stats_read(chip, reg, &low); 797 if (s->size == 8) 798 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 799 break; 800 default: 801 return U64_MAX; 802 } 803 value = (((u64)high) << 32) | low; 804 return value; 805 } 806 807 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 808 uint8_t *data, int types) 809 { 810 struct mv88e6xxx_hw_stat *stat; 811 int i, j; 812 813 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 814 stat = &mv88e6xxx_hw_stats[i]; 815 if (stat->type & types) { 816 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 817 ETH_GSTRING_LEN); 818 j++; 819 } 820 } 821 822 return j; 823 } 824 825 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 826 uint8_t *data) 827 { 828 return mv88e6xxx_stats_get_strings(chip, data, 829 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 830 } 831 832 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 833 uint8_t *data) 834 { 835 return mv88e6xxx_stats_get_strings(chip, data, 836 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 837 } 838 839 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 840 "atu_member_violation", 841 "atu_miss_violation", 842 "atu_full_violation", 843 "vtu_member_violation", 844 "vtu_miss_violation", 845 }; 846 847 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 848 { 849 unsigned int i; 850 851 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 852 strlcpy(data + i * ETH_GSTRING_LEN, 853 mv88e6xxx_atu_vtu_stats_strings[i], 854 ETH_GSTRING_LEN); 855 } 856 857 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 858 u32 stringset, uint8_t *data) 859 { 860 struct mv88e6xxx_chip *chip = ds->priv; 861 int count = 0; 862 863 if (stringset != ETH_SS_STATS) 864 return; 865 866 mutex_lock(&chip->reg_lock); 867 868 if (chip->info->ops->stats_get_strings) 869 count = chip->info->ops->stats_get_strings(chip, data); 870 871 if (chip->info->ops->serdes_get_strings) { 872 data += count * ETH_GSTRING_LEN; 873 count = chip->info->ops->serdes_get_strings(chip, port, data); 874 } 875 876 data += count * ETH_GSTRING_LEN; 877 mv88e6xxx_atu_vtu_get_strings(data); 878 879 mutex_unlock(&chip->reg_lock); 880 } 881 882 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 883 int types) 884 { 885 struct mv88e6xxx_hw_stat *stat; 886 int i, j; 887 888 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 889 stat = &mv88e6xxx_hw_stats[i]; 890 if (stat->type & types) 891 j++; 892 } 893 return j; 894 } 895 896 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 897 { 898 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 899 STATS_TYPE_PORT); 900 } 901 902 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 903 { 904 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 905 STATS_TYPE_BANK1); 906 } 907 908 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 909 { 910 struct mv88e6xxx_chip *chip = ds->priv; 911 int serdes_count = 0; 912 int count = 0; 913 914 if (sset != ETH_SS_STATS) 915 return 0; 916 917 mutex_lock(&chip->reg_lock); 918 if (chip->info->ops->stats_get_sset_count) 919 count = chip->info->ops->stats_get_sset_count(chip); 920 if (count < 0) 921 goto out; 922 923 if (chip->info->ops->serdes_get_sset_count) 924 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 925 port); 926 if (serdes_count < 0) { 927 count = serdes_count; 928 goto out; 929 } 930 count += serdes_count; 931 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 932 933 out: 934 mutex_unlock(&chip->reg_lock); 935 936 return count; 937 } 938 939 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 940 uint64_t *data, int types, 941 u16 bank1_select, u16 histogram) 942 { 943 struct mv88e6xxx_hw_stat *stat; 944 int i, j; 945 946 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 947 stat = &mv88e6xxx_hw_stats[i]; 948 if (stat->type & types) { 949 mutex_lock(&chip->reg_lock); 950 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 951 bank1_select, 952 histogram); 953 mutex_unlock(&chip->reg_lock); 954 955 j++; 956 } 957 } 958 return j; 959 } 960 961 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 962 uint64_t *data) 963 { 964 return mv88e6xxx_stats_get_stats(chip, port, data, 965 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 966 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 967 } 968 969 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 970 uint64_t *data) 971 { 972 return mv88e6xxx_stats_get_stats(chip, port, data, 973 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 974 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 975 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 976 } 977 978 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 979 uint64_t *data) 980 { 981 return mv88e6xxx_stats_get_stats(chip, port, data, 982 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 983 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 984 0); 985 } 986 987 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 988 uint64_t *data) 989 { 990 *data++ = chip->ports[port].atu_member_violation; 991 *data++ = chip->ports[port].atu_miss_violation; 992 *data++ = chip->ports[port].atu_full_violation; 993 *data++ = chip->ports[port].vtu_member_violation; 994 *data++ = chip->ports[port].vtu_miss_violation; 995 } 996 997 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 998 uint64_t *data) 999 { 1000 int count = 0; 1001 1002 if (chip->info->ops->stats_get_stats) 1003 count = chip->info->ops->stats_get_stats(chip, port, data); 1004 1005 mutex_lock(&chip->reg_lock); 1006 if (chip->info->ops->serdes_get_stats) { 1007 data += count; 1008 count = chip->info->ops->serdes_get_stats(chip, port, data); 1009 } 1010 data += count; 1011 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1012 mutex_unlock(&chip->reg_lock); 1013 } 1014 1015 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1016 uint64_t *data) 1017 { 1018 struct mv88e6xxx_chip *chip = ds->priv; 1019 int ret; 1020 1021 mutex_lock(&chip->reg_lock); 1022 1023 ret = mv88e6xxx_stats_snapshot(chip, port); 1024 mutex_unlock(&chip->reg_lock); 1025 1026 if (ret < 0) 1027 return; 1028 1029 mv88e6xxx_get_stats(chip, port, data); 1030 1031 } 1032 1033 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1034 { 1035 return 32 * sizeof(u16); 1036 } 1037 1038 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1039 struct ethtool_regs *regs, void *_p) 1040 { 1041 struct mv88e6xxx_chip *chip = ds->priv; 1042 int err; 1043 u16 reg; 1044 u16 *p = _p; 1045 int i; 1046 1047 regs->version = chip->info->prod_num; 1048 1049 memset(p, 0xff, 32 * sizeof(u16)); 1050 1051 mutex_lock(&chip->reg_lock); 1052 1053 for (i = 0; i < 32; i++) { 1054 1055 err = mv88e6xxx_port_read(chip, port, i, ®); 1056 if (!err) 1057 p[i] = reg; 1058 } 1059 1060 mutex_unlock(&chip->reg_lock); 1061 } 1062 1063 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1064 struct ethtool_eee *e) 1065 { 1066 /* Nothing to do on the port's MAC */ 1067 return 0; 1068 } 1069 1070 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1071 struct ethtool_eee *e) 1072 { 1073 /* Nothing to do on the port's MAC */ 1074 return 0; 1075 } 1076 1077 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1078 { 1079 struct dsa_switch *ds = NULL; 1080 struct net_device *br; 1081 u16 pvlan; 1082 int i; 1083 1084 if (dev < DSA_MAX_SWITCHES) 1085 ds = chip->ds->dst->ds[dev]; 1086 1087 /* Prevent frames from unknown switch or port */ 1088 if (!ds || port >= ds->num_ports) 1089 return 0; 1090 1091 /* Frames from DSA links and CPU ports can egress any local port */ 1092 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1093 return mv88e6xxx_port_mask(chip); 1094 1095 br = ds->ports[port].bridge_dev; 1096 pvlan = 0; 1097 1098 /* Frames from user ports can egress any local DSA links and CPU ports, 1099 * as well as any local member of their bridge group. 1100 */ 1101 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1102 if (dsa_is_cpu_port(chip->ds, i) || 1103 dsa_is_dsa_port(chip->ds, i) || 1104 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1105 pvlan |= BIT(i); 1106 1107 return pvlan; 1108 } 1109 1110 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1111 { 1112 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1113 1114 /* prevent frames from going back out of the port they came in on */ 1115 output_ports &= ~BIT(port); 1116 1117 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1118 } 1119 1120 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1121 u8 state) 1122 { 1123 struct mv88e6xxx_chip *chip = ds->priv; 1124 int err; 1125 1126 mutex_lock(&chip->reg_lock); 1127 err = mv88e6xxx_port_set_state(chip, port, state); 1128 mutex_unlock(&chip->reg_lock); 1129 1130 if (err) 1131 dev_err(ds->dev, "p%d: failed to update state\n", port); 1132 } 1133 1134 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1135 { 1136 int err; 1137 1138 if (chip->info->ops->ieee_pri_map) { 1139 err = chip->info->ops->ieee_pri_map(chip); 1140 if (err) 1141 return err; 1142 } 1143 1144 if (chip->info->ops->ip_pri_map) { 1145 err = chip->info->ops->ip_pri_map(chip); 1146 if (err) 1147 return err; 1148 } 1149 1150 return 0; 1151 } 1152 1153 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1154 { 1155 int target, port; 1156 int err; 1157 1158 if (!chip->info->global2_addr) 1159 return 0; 1160 1161 /* Initialize the routing port to the 32 possible target devices */ 1162 for (target = 0; target < 32; target++) { 1163 port = 0x1f; 1164 if (target < DSA_MAX_SWITCHES) 1165 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1166 port = chip->ds->rtable[target]; 1167 1168 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1169 if (err) 1170 return err; 1171 } 1172 1173 if (chip->info->ops->set_cascade_port) { 1174 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1175 err = chip->info->ops->set_cascade_port(chip, port); 1176 if (err) 1177 return err; 1178 } 1179 1180 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1181 if (err) 1182 return err; 1183 1184 return 0; 1185 } 1186 1187 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1188 { 1189 /* Clear all trunk masks and mapping */ 1190 if (chip->info->global2_addr) 1191 return mv88e6xxx_g2_trunk_clear(chip); 1192 1193 return 0; 1194 } 1195 1196 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1197 { 1198 if (chip->info->ops->rmu_disable) 1199 return chip->info->ops->rmu_disable(chip); 1200 1201 return 0; 1202 } 1203 1204 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1205 { 1206 if (chip->info->ops->pot_clear) 1207 return chip->info->ops->pot_clear(chip); 1208 1209 return 0; 1210 } 1211 1212 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1213 { 1214 if (chip->info->ops->mgmt_rsvd2cpu) 1215 return chip->info->ops->mgmt_rsvd2cpu(chip); 1216 1217 return 0; 1218 } 1219 1220 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1221 { 1222 int err; 1223 1224 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1225 if (err) 1226 return err; 1227 1228 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1229 if (err) 1230 return err; 1231 1232 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1233 } 1234 1235 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1236 { 1237 int port; 1238 int err; 1239 1240 if (!chip->info->ops->irl_init_all) 1241 return 0; 1242 1243 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1244 /* Disable ingress rate limiting by resetting all per port 1245 * ingress rate limit resources to their initial state. 1246 */ 1247 err = chip->info->ops->irl_init_all(chip, port); 1248 if (err) 1249 return err; 1250 } 1251 1252 return 0; 1253 } 1254 1255 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1256 { 1257 if (chip->info->ops->set_switch_mac) { 1258 u8 addr[ETH_ALEN]; 1259 1260 eth_random_addr(addr); 1261 1262 return chip->info->ops->set_switch_mac(chip, addr); 1263 } 1264 1265 return 0; 1266 } 1267 1268 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1269 { 1270 u16 pvlan = 0; 1271 1272 if (!mv88e6xxx_has_pvt(chip)) 1273 return -EOPNOTSUPP; 1274 1275 /* Skip the local source device, which uses in-chip port VLAN */ 1276 if (dev != chip->ds->index) 1277 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1278 1279 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1280 } 1281 1282 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1283 { 1284 int dev, port; 1285 int err; 1286 1287 if (!mv88e6xxx_has_pvt(chip)) 1288 return 0; 1289 1290 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1291 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1292 */ 1293 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1294 if (err) 1295 return err; 1296 1297 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1298 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1299 err = mv88e6xxx_pvt_map(chip, dev, port); 1300 if (err) 1301 return err; 1302 } 1303 } 1304 1305 return 0; 1306 } 1307 1308 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1309 { 1310 struct mv88e6xxx_chip *chip = ds->priv; 1311 int err; 1312 1313 mutex_lock(&chip->reg_lock); 1314 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1315 mutex_unlock(&chip->reg_lock); 1316 1317 if (err) 1318 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1319 } 1320 1321 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1322 { 1323 if (!chip->info->max_vid) 1324 return 0; 1325 1326 return mv88e6xxx_g1_vtu_flush(chip); 1327 } 1328 1329 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1330 struct mv88e6xxx_vtu_entry *entry) 1331 { 1332 if (!chip->info->ops->vtu_getnext) 1333 return -EOPNOTSUPP; 1334 1335 return chip->info->ops->vtu_getnext(chip, entry); 1336 } 1337 1338 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1339 struct mv88e6xxx_vtu_entry *entry) 1340 { 1341 if (!chip->info->ops->vtu_loadpurge) 1342 return -EOPNOTSUPP; 1343 1344 return chip->info->ops->vtu_loadpurge(chip, entry); 1345 } 1346 1347 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1348 { 1349 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1350 struct mv88e6xxx_vtu_entry vlan = { 1351 .vid = chip->info->max_vid, 1352 }; 1353 int i, err; 1354 1355 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1356 1357 /* Set every FID bit used by the (un)bridged ports */ 1358 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1359 err = mv88e6xxx_port_get_fid(chip, i, fid); 1360 if (err) 1361 return err; 1362 1363 set_bit(*fid, fid_bitmap); 1364 } 1365 1366 /* Set every FID bit used by the VLAN entries */ 1367 do { 1368 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1369 if (err) 1370 return err; 1371 1372 if (!vlan.valid) 1373 break; 1374 1375 set_bit(vlan.fid, fid_bitmap); 1376 } while (vlan.vid < chip->info->max_vid); 1377 1378 /* The reset value 0x000 is used to indicate that multiple address 1379 * databases are not needed. Return the next positive available. 1380 */ 1381 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1382 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1383 return -ENOSPC; 1384 1385 /* Clear the database */ 1386 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1387 } 1388 1389 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1390 struct mv88e6xxx_vtu_entry *entry, bool new) 1391 { 1392 int err; 1393 1394 if (!vid) 1395 return -EINVAL; 1396 1397 entry->vid = vid - 1; 1398 entry->valid = false; 1399 1400 err = mv88e6xxx_vtu_getnext(chip, entry); 1401 if (err) 1402 return err; 1403 1404 if (entry->vid == vid && entry->valid) 1405 return 0; 1406 1407 if (new) { 1408 int i; 1409 1410 /* Initialize a fresh VLAN entry */ 1411 memset(entry, 0, sizeof(*entry)); 1412 entry->valid = true; 1413 entry->vid = vid; 1414 1415 /* Exclude all ports */ 1416 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1417 entry->member[i] = 1418 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1419 1420 return mv88e6xxx_atu_new(chip, &entry->fid); 1421 } 1422 1423 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1424 return -EOPNOTSUPP; 1425 } 1426 1427 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1428 u16 vid_begin, u16 vid_end) 1429 { 1430 struct mv88e6xxx_chip *chip = ds->priv; 1431 struct mv88e6xxx_vtu_entry vlan = { 1432 .vid = vid_begin - 1, 1433 }; 1434 int i, err; 1435 1436 /* DSA and CPU ports have to be members of multiple vlans */ 1437 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1438 return 0; 1439 1440 if (!vid_begin) 1441 return -EOPNOTSUPP; 1442 1443 mutex_lock(&chip->reg_lock); 1444 1445 do { 1446 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1447 if (err) 1448 goto unlock; 1449 1450 if (!vlan.valid) 1451 break; 1452 1453 if (vlan.vid > vid_end) 1454 break; 1455 1456 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1457 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1458 continue; 1459 1460 if (!ds->ports[i].slave) 1461 continue; 1462 1463 if (vlan.member[i] == 1464 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1465 continue; 1466 1467 if (dsa_to_port(ds, i)->bridge_dev == 1468 ds->ports[port].bridge_dev) 1469 break; /* same bridge, check next VLAN */ 1470 1471 if (!dsa_to_port(ds, i)->bridge_dev) 1472 continue; 1473 1474 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1475 port, vlan.vid, i, 1476 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1477 err = -EOPNOTSUPP; 1478 goto unlock; 1479 } 1480 } while (vlan.vid < vid_end); 1481 1482 unlock: 1483 mutex_unlock(&chip->reg_lock); 1484 1485 return err; 1486 } 1487 1488 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1489 bool vlan_filtering) 1490 { 1491 struct mv88e6xxx_chip *chip = ds->priv; 1492 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1493 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1494 int err; 1495 1496 if (!chip->info->max_vid) 1497 return -EOPNOTSUPP; 1498 1499 mutex_lock(&chip->reg_lock); 1500 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1501 mutex_unlock(&chip->reg_lock); 1502 1503 return err; 1504 } 1505 1506 static int 1507 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1508 const struct switchdev_obj_port_vlan *vlan) 1509 { 1510 struct mv88e6xxx_chip *chip = ds->priv; 1511 int err; 1512 1513 if (!chip->info->max_vid) 1514 return -EOPNOTSUPP; 1515 1516 /* If the requested port doesn't belong to the same bridge as the VLAN 1517 * members, do not support it (yet) and fallback to software VLAN. 1518 */ 1519 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1520 vlan->vid_end); 1521 if (err) 1522 return err; 1523 1524 /* We don't need any dynamic resource from the kernel (yet), 1525 * so skip the prepare phase. 1526 */ 1527 return 0; 1528 } 1529 1530 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1531 const unsigned char *addr, u16 vid, 1532 u8 state) 1533 { 1534 struct mv88e6xxx_vtu_entry vlan; 1535 struct mv88e6xxx_atu_entry entry; 1536 int err; 1537 1538 /* Null VLAN ID corresponds to the port private database */ 1539 if (vid == 0) 1540 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1541 else 1542 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1543 if (err) 1544 return err; 1545 1546 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1547 ether_addr_copy(entry.mac, addr); 1548 eth_addr_dec(entry.mac); 1549 1550 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1551 if (err) 1552 return err; 1553 1554 /* Initialize a fresh ATU entry if it isn't found */ 1555 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1556 !ether_addr_equal(entry.mac, addr)) { 1557 memset(&entry, 0, sizeof(entry)); 1558 ether_addr_copy(entry.mac, addr); 1559 } 1560 1561 /* Purge the ATU entry only if no port is using it anymore */ 1562 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1563 entry.portvec &= ~BIT(port); 1564 if (!entry.portvec) 1565 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1566 } else { 1567 entry.portvec |= BIT(port); 1568 entry.state = state; 1569 } 1570 1571 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1572 } 1573 1574 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1575 u16 vid) 1576 { 1577 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1578 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1579 1580 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1581 } 1582 1583 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1584 { 1585 int port; 1586 int err; 1587 1588 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1589 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1590 if (err) 1591 return err; 1592 } 1593 1594 return 0; 1595 } 1596 1597 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1598 u16 vid, u8 member) 1599 { 1600 struct mv88e6xxx_vtu_entry vlan; 1601 int err; 1602 1603 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1604 if (err) 1605 return err; 1606 1607 vlan.member[port] = member; 1608 1609 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1610 if (err) 1611 return err; 1612 1613 return mv88e6xxx_broadcast_setup(chip, vid); 1614 } 1615 1616 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1617 const struct switchdev_obj_port_vlan *vlan) 1618 { 1619 struct mv88e6xxx_chip *chip = ds->priv; 1620 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1621 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1622 u8 member; 1623 u16 vid; 1624 1625 if (!chip->info->max_vid) 1626 return; 1627 1628 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1629 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1630 else if (untagged) 1631 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1632 else 1633 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1634 1635 mutex_lock(&chip->reg_lock); 1636 1637 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1638 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1639 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1640 vid, untagged ? 'u' : 't'); 1641 1642 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1643 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1644 vlan->vid_end); 1645 1646 mutex_unlock(&chip->reg_lock); 1647 } 1648 1649 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1650 int port, u16 vid) 1651 { 1652 struct mv88e6xxx_vtu_entry vlan; 1653 int i, err; 1654 1655 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1656 if (err) 1657 return err; 1658 1659 /* Tell switchdev if this VLAN is handled in software */ 1660 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1661 return -EOPNOTSUPP; 1662 1663 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1664 1665 /* keep the VLAN unless all ports are excluded */ 1666 vlan.valid = false; 1667 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1668 if (vlan.member[i] != 1669 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1670 vlan.valid = true; 1671 break; 1672 } 1673 } 1674 1675 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1676 if (err) 1677 return err; 1678 1679 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1680 } 1681 1682 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1683 const struct switchdev_obj_port_vlan *vlan) 1684 { 1685 struct mv88e6xxx_chip *chip = ds->priv; 1686 u16 pvid, vid; 1687 int err = 0; 1688 1689 if (!chip->info->max_vid) 1690 return -EOPNOTSUPP; 1691 1692 mutex_lock(&chip->reg_lock); 1693 1694 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1695 if (err) 1696 goto unlock; 1697 1698 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1699 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1700 if (err) 1701 goto unlock; 1702 1703 if (vid == pvid) { 1704 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1705 if (err) 1706 goto unlock; 1707 } 1708 } 1709 1710 unlock: 1711 mutex_unlock(&chip->reg_lock); 1712 1713 return err; 1714 } 1715 1716 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1717 const unsigned char *addr, u16 vid) 1718 { 1719 struct mv88e6xxx_chip *chip = ds->priv; 1720 int err; 1721 1722 mutex_lock(&chip->reg_lock); 1723 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1724 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1725 mutex_unlock(&chip->reg_lock); 1726 1727 return err; 1728 } 1729 1730 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1731 const unsigned char *addr, u16 vid) 1732 { 1733 struct mv88e6xxx_chip *chip = ds->priv; 1734 int err; 1735 1736 mutex_lock(&chip->reg_lock); 1737 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1738 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1739 mutex_unlock(&chip->reg_lock); 1740 1741 return err; 1742 } 1743 1744 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1745 u16 fid, u16 vid, int port, 1746 dsa_fdb_dump_cb_t *cb, void *data) 1747 { 1748 struct mv88e6xxx_atu_entry addr; 1749 bool is_static; 1750 int err; 1751 1752 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1753 eth_broadcast_addr(addr.mac); 1754 1755 do { 1756 mutex_lock(&chip->reg_lock); 1757 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1758 mutex_unlock(&chip->reg_lock); 1759 if (err) 1760 return err; 1761 1762 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1763 break; 1764 1765 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1766 continue; 1767 1768 if (!is_unicast_ether_addr(addr.mac)) 1769 continue; 1770 1771 is_static = (addr.state == 1772 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1773 err = cb(addr.mac, vid, is_static, data); 1774 if (err) 1775 return err; 1776 } while (!is_broadcast_ether_addr(addr.mac)); 1777 1778 return err; 1779 } 1780 1781 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1782 dsa_fdb_dump_cb_t *cb, void *data) 1783 { 1784 struct mv88e6xxx_vtu_entry vlan = { 1785 .vid = chip->info->max_vid, 1786 }; 1787 u16 fid; 1788 int err; 1789 1790 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1791 mutex_lock(&chip->reg_lock); 1792 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1793 mutex_unlock(&chip->reg_lock); 1794 1795 if (err) 1796 return err; 1797 1798 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1799 if (err) 1800 return err; 1801 1802 /* Dump VLANs' Filtering Information Databases */ 1803 do { 1804 mutex_lock(&chip->reg_lock); 1805 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1806 mutex_unlock(&chip->reg_lock); 1807 if (err) 1808 return err; 1809 1810 if (!vlan.valid) 1811 break; 1812 1813 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1814 cb, data); 1815 if (err) 1816 return err; 1817 } while (vlan.vid < chip->info->max_vid); 1818 1819 return err; 1820 } 1821 1822 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1823 dsa_fdb_dump_cb_t *cb, void *data) 1824 { 1825 struct mv88e6xxx_chip *chip = ds->priv; 1826 1827 return mv88e6xxx_port_db_dump(chip, port, cb, data); 1828 } 1829 1830 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1831 struct net_device *br) 1832 { 1833 struct dsa_switch *ds; 1834 int port; 1835 int dev; 1836 int err; 1837 1838 /* Remap the Port VLAN of each local bridge group member */ 1839 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1840 if (chip->ds->ports[port].bridge_dev == br) { 1841 err = mv88e6xxx_port_vlan_map(chip, port); 1842 if (err) 1843 return err; 1844 } 1845 } 1846 1847 if (!mv88e6xxx_has_pvt(chip)) 1848 return 0; 1849 1850 /* Remap the Port VLAN of each cross-chip bridge group member */ 1851 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1852 ds = chip->ds->dst->ds[dev]; 1853 if (!ds) 1854 break; 1855 1856 for (port = 0; port < ds->num_ports; ++port) { 1857 if (ds->ports[port].bridge_dev == br) { 1858 err = mv88e6xxx_pvt_map(chip, dev, port); 1859 if (err) 1860 return err; 1861 } 1862 } 1863 } 1864 1865 return 0; 1866 } 1867 1868 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1869 struct net_device *br) 1870 { 1871 struct mv88e6xxx_chip *chip = ds->priv; 1872 int err; 1873 1874 mutex_lock(&chip->reg_lock); 1875 err = mv88e6xxx_bridge_map(chip, br); 1876 mutex_unlock(&chip->reg_lock); 1877 1878 return err; 1879 } 1880 1881 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1882 struct net_device *br) 1883 { 1884 struct mv88e6xxx_chip *chip = ds->priv; 1885 1886 mutex_lock(&chip->reg_lock); 1887 if (mv88e6xxx_bridge_map(chip, br) || 1888 mv88e6xxx_port_vlan_map(chip, port)) 1889 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1890 mutex_unlock(&chip->reg_lock); 1891 } 1892 1893 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1894 int port, struct net_device *br) 1895 { 1896 struct mv88e6xxx_chip *chip = ds->priv; 1897 int err; 1898 1899 if (!mv88e6xxx_has_pvt(chip)) 1900 return 0; 1901 1902 mutex_lock(&chip->reg_lock); 1903 err = mv88e6xxx_pvt_map(chip, dev, port); 1904 mutex_unlock(&chip->reg_lock); 1905 1906 return err; 1907 } 1908 1909 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1910 int port, struct net_device *br) 1911 { 1912 struct mv88e6xxx_chip *chip = ds->priv; 1913 1914 if (!mv88e6xxx_has_pvt(chip)) 1915 return; 1916 1917 mutex_lock(&chip->reg_lock); 1918 if (mv88e6xxx_pvt_map(chip, dev, port)) 1919 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1920 mutex_unlock(&chip->reg_lock); 1921 } 1922 1923 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1924 { 1925 if (chip->info->ops->reset) 1926 return chip->info->ops->reset(chip); 1927 1928 return 0; 1929 } 1930 1931 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1932 { 1933 struct gpio_desc *gpiod = chip->reset; 1934 1935 /* If there is a GPIO connected to the reset pin, toggle it */ 1936 if (gpiod) { 1937 gpiod_set_value_cansleep(gpiod, 1); 1938 usleep_range(10000, 20000); 1939 gpiod_set_value_cansleep(gpiod, 0); 1940 usleep_range(10000, 20000); 1941 } 1942 } 1943 1944 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1945 { 1946 int i, err; 1947 1948 /* Set all ports to the Disabled state */ 1949 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1950 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1951 if (err) 1952 return err; 1953 } 1954 1955 /* Wait for transmit queues to drain, 1956 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1957 */ 1958 usleep_range(2000, 4000); 1959 1960 return 0; 1961 } 1962 1963 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1964 { 1965 int err; 1966 1967 err = mv88e6xxx_disable_ports(chip); 1968 if (err) 1969 return err; 1970 1971 mv88e6xxx_hardware_reset(chip); 1972 1973 return mv88e6xxx_software_reset(chip); 1974 } 1975 1976 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1977 enum mv88e6xxx_frame_mode frame, 1978 enum mv88e6xxx_egress_mode egress, u16 etype) 1979 { 1980 int err; 1981 1982 if (!chip->info->ops->port_set_frame_mode) 1983 return -EOPNOTSUPP; 1984 1985 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1986 if (err) 1987 return err; 1988 1989 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1990 if (err) 1991 return err; 1992 1993 if (chip->info->ops->port_set_ether_type) 1994 return chip->info->ops->port_set_ether_type(chip, port, etype); 1995 1996 return 0; 1997 } 1998 1999 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2000 { 2001 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2002 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2003 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2004 } 2005 2006 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2007 { 2008 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2009 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2010 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2011 } 2012 2013 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2014 { 2015 return mv88e6xxx_set_port_mode(chip, port, 2016 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2017 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2018 ETH_P_EDSA); 2019 } 2020 2021 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2022 { 2023 if (dsa_is_dsa_port(chip->ds, port)) 2024 return mv88e6xxx_set_port_mode_dsa(chip, port); 2025 2026 if (dsa_is_user_port(chip->ds, port)) 2027 return mv88e6xxx_set_port_mode_normal(chip, port); 2028 2029 /* Setup CPU port mode depending on its supported tag format */ 2030 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2031 return mv88e6xxx_set_port_mode_dsa(chip, port); 2032 2033 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2034 return mv88e6xxx_set_port_mode_edsa(chip, port); 2035 2036 return -EINVAL; 2037 } 2038 2039 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2040 { 2041 bool message = dsa_is_dsa_port(chip->ds, port); 2042 2043 return mv88e6xxx_port_set_message_port(chip, port, message); 2044 } 2045 2046 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2047 { 2048 struct dsa_switch *ds = chip->ds; 2049 bool flood; 2050 2051 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2052 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2053 if (chip->info->ops->port_set_egress_floods) 2054 return chip->info->ops->port_set_egress_floods(chip, port, 2055 flood, flood); 2056 2057 return 0; 2058 } 2059 2060 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2061 bool on) 2062 { 2063 if (chip->info->ops->serdes_power) 2064 return chip->info->ops->serdes_power(chip, port, on); 2065 2066 return 0; 2067 } 2068 2069 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2070 { 2071 struct dsa_switch *ds = chip->ds; 2072 int upstream_port; 2073 int err; 2074 2075 upstream_port = dsa_upstream_port(ds, port); 2076 if (chip->info->ops->port_set_upstream_port) { 2077 err = chip->info->ops->port_set_upstream_port(chip, port, 2078 upstream_port); 2079 if (err) 2080 return err; 2081 } 2082 2083 if (port == upstream_port) { 2084 if (chip->info->ops->set_cpu_port) { 2085 err = chip->info->ops->set_cpu_port(chip, 2086 upstream_port); 2087 if (err) 2088 return err; 2089 } 2090 2091 if (chip->info->ops->set_egress_port) { 2092 err = chip->info->ops->set_egress_port(chip, 2093 upstream_port); 2094 if (err) 2095 return err; 2096 } 2097 } 2098 2099 return 0; 2100 } 2101 2102 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2103 { 2104 struct dsa_switch *ds = chip->ds; 2105 int err; 2106 u16 reg; 2107 2108 chip->ports[port].chip = chip; 2109 chip->ports[port].port = port; 2110 2111 /* MAC Forcing register: don't force link, speed, duplex or flow control 2112 * state to any particular values on physical ports, but force the CPU 2113 * port and all DSA ports to their maximum bandwidth and full duplex. 2114 */ 2115 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2116 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2117 SPEED_MAX, DUPLEX_FULL, 2118 PAUSE_OFF, 2119 PHY_INTERFACE_MODE_NA); 2120 else 2121 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2122 SPEED_UNFORCED, DUPLEX_UNFORCED, 2123 PAUSE_ON, 2124 PHY_INTERFACE_MODE_NA); 2125 if (err) 2126 return err; 2127 2128 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2129 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2130 * tunneling, determine priority by looking at 802.1p and IP 2131 * priority fields (IP prio has precedence), and set STP state 2132 * to Forwarding. 2133 * 2134 * If this is the CPU link, use DSA or EDSA tagging depending 2135 * on which tagging mode was configured. 2136 * 2137 * If this is a link to another switch, use DSA tagging mode. 2138 * 2139 * If this is the upstream port for this switch, enable 2140 * forwarding of unknown unicasts and multicasts. 2141 */ 2142 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2143 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2144 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2145 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2146 if (err) 2147 return err; 2148 2149 err = mv88e6xxx_setup_port_mode(chip, port); 2150 if (err) 2151 return err; 2152 2153 err = mv88e6xxx_setup_egress_floods(chip, port); 2154 if (err) 2155 return err; 2156 2157 /* Enable the SERDES interface for DSA and CPU ports. Normal 2158 * ports SERDES are enabled when the port is enabled, thus 2159 * saving a bit of power. 2160 */ 2161 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 2162 err = mv88e6xxx_serdes_power(chip, port, true); 2163 if (err) 2164 return err; 2165 } 2166 2167 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2168 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2169 * untagged frames on this port, do a destination address lookup on all 2170 * received packets as usual, disable ARP mirroring and don't send a 2171 * copy of all transmitted/received frames on this port to the CPU. 2172 */ 2173 err = mv88e6xxx_port_set_map_da(chip, port); 2174 if (err) 2175 return err; 2176 2177 err = mv88e6xxx_setup_upstream_port(chip, port); 2178 if (err) 2179 return err; 2180 2181 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2182 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2183 if (err) 2184 return err; 2185 2186 if (chip->info->ops->port_set_jumbo_size) { 2187 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2188 if (err) 2189 return err; 2190 } 2191 2192 /* Port Association Vector: when learning source addresses 2193 * of packets, add the address to the address database using 2194 * a port bitmap that has only the bit for this port set and 2195 * the other bits clear. 2196 */ 2197 reg = 1 << port; 2198 /* Disable learning for CPU port */ 2199 if (dsa_is_cpu_port(ds, port)) 2200 reg = 0; 2201 2202 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2203 reg); 2204 if (err) 2205 return err; 2206 2207 /* Egress rate control 2: disable egress rate control. */ 2208 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2209 0x0000); 2210 if (err) 2211 return err; 2212 2213 if (chip->info->ops->port_pause_limit) { 2214 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2215 if (err) 2216 return err; 2217 } 2218 2219 if (chip->info->ops->port_disable_learn_limit) { 2220 err = chip->info->ops->port_disable_learn_limit(chip, port); 2221 if (err) 2222 return err; 2223 } 2224 2225 if (chip->info->ops->port_disable_pri_override) { 2226 err = chip->info->ops->port_disable_pri_override(chip, port); 2227 if (err) 2228 return err; 2229 } 2230 2231 if (chip->info->ops->port_tag_remap) { 2232 err = chip->info->ops->port_tag_remap(chip, port); 2233 if (err) 2234 return err; 2235 } 2236 2237 if (chip->info->ops->port_egress_rate_limiting) { 2238 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2239 if (err) 2240 return err; 2241 } 2242 2243 err = mv88e6xxx_setup_message_port(chip, port); 2244 if (err) 2245 return err; 2246 2247 /* Port based VLAN map: give each port the same default address 2248 * database, and allow bidirectional communication between the 2249 * CPU and DSA port(s), and the other ports. 2250 */ 2251 err = mv88e6xxx_port_set_fid(chip, port, 0); 2252 if (err) 2253 return err; 2254 2255 err = mv88e6xxx_port_vlan_map(chip, port); 2256 if (err) 2257 return err; 2258 2259 /* Default VLAN ID and priority: don't set a default VLAN 2260 * ID, and set the default packet priority to zero. 2261 */ 2262 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2263 } 2264 2265 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2266 struct phy_device *phydev) 2267 { 2268 struct mv88e6xxx_chip *chip = ds->priv; 2269 int err; 2270 2271 mutex_lock(&chip->reg_lock); 2272 2273 err = mv88e6xxx_serdes_power(chip, port, true); 2274 2275 if (!err && chip->info->ops->serdes_irq_setup) 2276 err = chip->info->ops->serdes_irq_setup(chip, port); 2277 2278 mutex_unlock(&chip->reg_lock); 2279 2280 return err; 2281 } 2282 2283 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2284 { 2285 struct mv88e6xxx_chip *chip = ds->priv; 2286 2287 mutex_lock(&chip->reg_lock); 2288 2289 if (mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED)) 2290 dev_err(chip->dev, "failed to disable port\n"); 2291 2292 if (chip->info->ops->serdes_irq_free) 2293 chip->info->ops->serdes_irq_free(chip, port); 2294 2295 if (mv88e6xxx_serdes_power(chip, port, false)) 2296 dev_err(chip->dev, "failed to power off SERDES\n"); 2297 2298 mutex_unlock(&chip->reg_lock); 2299 } 2300 2301 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2302 unsigned int ageing_time) 2303 { 2304 struct mv88e6xxx_chip *chip = ds->priv; 2305 int err; 2306 2307 mutex_lock(&chip->reg_lock); 2308 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2309 mutex_unlock(&chip->reg_lock); 2310 2311 return err; 2312 } 2313 2314 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2315 { 2316 int err; 2317 2318 /* Initialize the statistics unit */ 2319 if (chip->info->ops->stats_set_histogram) { 2320 err = chip->info->ops->stats_set_histogram(chip); 2321 if (err) 2322 return err; 2323 } 2324 2325 return mv88e6xxx_g1_stats_clear(chip); 2326 } 2327 2328 /* The mv88e6390 has some hidden registers used for debug and 2329 * development. The errata also makes use of them. 2330 */ 2331 static int mv88e6390_hidden_write(struct mv88e6xxx_chip *chip, int port, 2332 int reg, u16 val) 2333 { 2334 u16 ctrl; 2335 int err; 2336 2337 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_DATA_PORT, 2338 PORT_RESERVED_1A, val); 2339 if (err) 2340 return err; 2341 2342 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_WRITE | 2343 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2344 reg; 2345 2346 return mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2347 PORT_RESERVED_1A, ctrl); 2348 } 2349 2350 static int mv88e6390_hidden_wait(struct mv88e6xxx_chip *chip) 2351 { 2352 return mv88e6xxx_wait(chip, PORT_RESERVED_1A_CTRL_PORT, 2353 PORT_RESERVED_1A, PORT_RESERVED_1A_BUSY); 2354 } 2355 2356 2357 static int mv88e6390_hidden_read(struct mv88e6xxx_chip *chip, int port, 2358 int reg, u16 *val) 2359 { 2360 u16 ctrl; 2361 int err; 2362 2363 ctrl = PORT_RESERVED_1A_BUSY | PORT_RESERVED_1A_READ | 2364 PORT_RESERVED_1A_BLOCK | port << PORT_RESERVED_1A_PORT_SHIFT | 2365 reg; 2366 2367 err = mv88e6xxx_port_write(chip, PORT_RESERVED_1A_CTRL_PORT, 2368 PORT_RESERVED_1A, ctrl); 2369 if (err) 2370 return err; 2371 2372 err = mv88e6390_hidden_wait(chip); 2373 if (err) 2374 return err; 2375 2376 return mv88e6xxx_port_read(chip, PORT_RESERVED_1A_DATA_PORT, 2377 PORT_RESERVED_1A, val); 2378 } 2379 2380 /* Check if the errata has already been applied. */ 2381 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2382 { 2383 int port; 2384 int err; 2385 u16 val; 2386 2387 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2388 err = mv88e6390_hidden_read(chip, port, 0, &val); 2389 if (err) { 2390 dev_err(chip->dev, 2391 "Error reading hidden register: %d\n", err); 2392 return false; 2393 } 2394 if (val != 0x01c0) 2395 return false; 2396 } 2397 2398 return true; 2399 } 2400 2401 /* The 6390 copper ports have an errata which require poking magic 2402 * values into undocumented hidden registers and then performing a 2403 * software reset. 2404 */ 2405 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2406 { 2407 int port; 2408 int err; 2409 2410 if (mv88e6390_setup_errata_applied(chip)) 2411 return 0; 2412 2413 /* Set the ports into blocking mode */ 2414 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2415 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2416 if (err) 2417 return err; 2418 } 2419 2420 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2421 err = mv88e6390_hidden_write(chip, port, 0, 0x01c0); 2422 if (err) 2423 return err; 2424 } 2425 2426 return mv88e6xxx_software_reset(chip); 2427 } 2428 2429 static int mv88e6xxx_setup(struct dsa_switch *ds) 2430 { 2431 struct mv88e6xxx_chip *chip = ds->priv; 2432 u8 cmode; 2433 int err; 2434 int i; 2435 2436 chip->ds = ds; 2437 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2438 2439 mutex_lock(&chip->reg_lock); 2440 2441 if (chip->info->ops->setup_errata) { 2442 err = chip->info->ops->setup_errata(chip); 2443 if (err) 2444 goto unlock; 2445 } 2446 2447 /* Cache the cmode of each port. */ 2448 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2449 if (chip->info->ops->port_get_cmode) { 2450 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2451 if (err) 2452 goto unlock; 2453 2454 chip->ports[i].cmode = cmode; 2455 } 2456 } 2457 2458 /* Setup Switch Port Registers */ 2459 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2460 if (dsa_is_unused_port(ds, i)) { 2461 err = mv88e6xxx_port_set_state(chip, i, 2462 BR_STATE_DISABLED); 2463 if (err) 2464 goto unlock; 2465 2466 err = mv88e6xxx_serdes_power(chip, i, false); 2467 if (err) 2468 goto unlock; 2469 2470 continue; 2471 } 2472 2473 err = mv88e6xxx_setup_port(chip, i); 2474 if (err) 2475 goto unlock; 2476 } 2477 2478 err = mv88e6xxx_irl_setup(chip); 2479 if (err) 2480 goto unlock; 2481 2482 err = mv88e6xxx_mac_setup(chip); 2483 if (err) 2484 goto unlock; 2485 2486 err = mv88e6xxx_phy_setup(chip); 2487 if (err) 2488 goto unlock; 2489 2490 err = mv88e6xxx_vtu_setup(chip); 2491 if (err) 2492 goto unlock; 2493 2494 err = mv88e6xxx_pvt_setup(chip); 2495 if (err) 2496 goto unlock; 2497 2498 err = mv88e6xxx_atu_setup(chip); 2499 if (err) 2500 goto unlock; 2501 2502 err = mv88e6xxx_broadcast_setup(chip, 0); 2503 if (err) 2504 goto unlock; 2505 2506 err = mv88e6xxx_pot_setup(chip); 2507 if (err) 2508 goto unlock; 2509 2510 err = mv88e6xxx_rmu_setup(chip); 2511 if (err) 2512 goto unlock; 2513 2514 err = mv88e6xxx_rsvd2cpu_setup(chip); 2515 if (err) 2516 goto unlock; 2517 2518 err = mv88e6xxx_trunk_setup(chip); 2519 if (err) 2520 goto unlock; 2521 2522 err = mv88e6xxx_devmap_setup(chip); 2523 if (err) 2524 goto unlock; 2525 2526 err = mv88e6xxx_pri_setup(chip); 2527 if (err) 2528 goto unlock; 2529 2530 /* Setup PTP Hardware Clock and timestamping */ 2531 if (chip->info->ptp_support) { 2532 err = mv88e6xxx_ptp_setup(chip); 2533 if (err) 2534 goto unlock; 2535 2536 err = mv88e6xxx_hwtstamp_setup(chip); 2537 if (err) 2538 goto unlock; 2539 } 2540 2541 err = mv88e6xxx_stats_setup(chip); 2542 if (err) 2543 goto unlock; 2544 2545 unlock: 2546 mutex_unlock(&chip->reg_lock); 2547 2548 return err; 2549 } 2550 2551 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2552 { 2553 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2554 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2555 u16 val; 2556 int err; 2557 2558 if (!chip->info->ops->phy_read) 2559 return -EOPNOTSUPP; 2560 2561 mutex_lock(&chip->reg_lock); 2562 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2563 mutex_unlock(&chip->reg_lock); 2564 2565 if (reg == MII_PHYSID2) { 2566 /* Some internal PHYs don't have a model number. */ 2567 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2568 /* Then there is the 6165 family. It gets is 2569 * PHYs correct. But it can also have two 2570 * SERDES interfaces in the PHY address 2571 * space. And these don't have a model 2572 * number. But they are not PHYs, so we don't 2573 * want to give them something a PHY driver 2574 * will recognise. 2575 * 2576 * Use the mv88e6390 family model number 2577 * instead, for anything which really could be 2578 * a PHY, 2579 */ 2580 if (!(val & 0x3f0)) 2581 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2582 } 2583 2584 return err ? err : val; 2585 } 2586 2587 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2588 { 2589 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2590 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2591 int err; 2592 2593 if (!chip->info->ops->phy_write) 2594 return -EOPNOTSUPP; 2595 2596 mutex_lock(&chip->reg_lock); 2597 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2598 mutex_unlock(&chip->reg_lock); 2599 2600 return err; 2601 } 2602 2603 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2604 struct device_node *np, 2605 bool external) 2606 { 2607 static int index; 2608 struct mv88e6xxx_mdio_bus *mdio_bus; 2609 struct mii_bus *bus; 2610 int err; 2611 2612 if (external) { 2613 mutex_lock(&chip->reg_lock); 2614 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2615 mutex_unlock(&chip->reg_lock); 2616 2617 if (err) 2618 return err; 2619 } 2620 2621 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2622 if (!bus) 2623 return -ENOMEM; 2624 2625 mdio_bus = bus->priv; 2626 mdio_bus->bus = bus; 2627 mdio_bus->chip = chip; 2628 INIT_LIST_HEAD(&mdio_bus->list); 2629 mdio_bus->external = external; 2630 2631 if (np) { 2632 bus->name = np->full_name; 2633 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2634 } else { 2635 bus->name = "mv88e6xxx SMI"; 2636 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2637 } 2638 2639 bus->read = mv88e6xxx_mdio_read; 2640 bus->write = mv88e6xxx_mdio_write; 2641 bus->parent = chip->dev; 2642 2643 if (!external) { 2644 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2645 if (err) 2646 return err; 2647 } 2648 2649 err = of_mdiobus_register(bus, np); 2650 if (err) { 2651 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2652 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2653 return err; 2654 } 2655 2656 if (external) 2657 list_add_tail(&mdio_bus->list, &chip->mdios); 2658 else 2659 list_add(&mdio_bus->list, &chip->mdios); 2660 2661 return 0; 2662 } 2663 2664 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2665 { .compatible = "marvell,mv88e6xxx-mdio-external", 2666 .data = (void *)true }, 2667 { }, 2668 }; 2669 2670 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2671 2672 { 2673 struct mv88e6xxx_mdio_bus *mdio_bus; 2674 struct mii_bus *bus; 2675 2676 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2677 bus = mdio_bus->bus; 2678 2679 if (!mdio_bus->external) 2680 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2681 2682 mdiobus_unregister(bus); 2683 } 2684 } 2685 2686 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2687 struct device_node *np) 2688 { 2689 const struct of_device_id *match; 2690 struct device_node *child; 2691 int err; 2692 2693 /* Always register one mdio bus for the internal/default mdio 2694 * bus. This maybe represented in the device tree, but is 2695 * optional. 2696 */ 2697 child = of_get_child_by_name(np, "mdio"); 2698 err = mv88e6xxx_mdio_register(chip, child, false); 2699 if (err) 2700 return err; 2701 2702 /* Walk the device tree, and see if there are any other nodes 2703 * which say they are compatible with the external mdio 2704 * bus. 2705 */ 2706 for_each_available_child_of_node(np, child) { 2707 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2708 if (match) { 2709 err = mv88e6xxx_mdio_register(chip, child, true); 2710 if (err) { 2711 mv88e6xxx_mdios_unregister(chip); 2712 return err; 2713 } 2714 } 2715 } 2716 2717 return 0; 2718 } 2719 2720 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2721 { 2722 struct mv88e6xxx_chip *chip = ds->priv; 2723 2724 return chip->eeprom_len; 2725 } 2726 2727 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2728 struct ethtool_eeprom *eeprom, u8 *data) 2729 { 2730 struct mv88e6xxx_chip *chip = ds->priv; 2731 int err; 2732 2733 if (!chip->info->ops->get_eeprom) 2734 return -EOPNOTSUPP; 2735 2736 mutex_lock(&chip->reg_lock); 2737 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2738 mutex_unlock(&chip->reg_lock); 2739 2740 if (err) 2741 return err; 2742 2743 eeprom->magic = 0xc3ec4951; 2744 2745 return 0; 2746 } 2747 2748 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2749 struct ethtool_eeprom *eeprom, u8 *data) 2750 { 2751 struct mv88e6xxx_chip *chip = ds->priv; 2752 int err; 2753 2754 if (!chip->info->ops->set_eeprom) 2755 return -EOPNOTSUPP; 2756 2757 if (eeprom->magic != 0xc3ec4951) 2758 return -EINVAL; 2759 2760 mutex_lock(&chip->reg_lock); 2761 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2762 mutex_unlock(&chip->reg_lock); 2763 2764 return err; 2765 } 2766 2767 static const struct mv88e6xxx_ops mv88e6085_ops = { 2768 /* MV88E6XXX_FAMILY_6097 */ 2769 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2770 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2771 .irl_init_all = mv88e6352_g2_irl_init_all, 2772 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2773 .phy_read = mv88e6185_phy_ppu_read, 2774 .phy_write = mv88e6185_phy_ppu_write, 2775 .port_set_link = mv88e6xxx_port_set_link, 2776 .port_set_duplex = mv88e6xxx_port_set_duplex, 2777 .port_set_speed = mv88e6185_port_set_speed, 2778 .port_tag_remap = mv88e6095_port_tag_remap, 2779 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2780 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2781 .port_set_ether_type = mv88e6351_port_set_ether_type, 2782 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2783 .port_pause_limit = mv88e6097_port_pause_limit, 2784 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2785 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2786 .port_link_state = mv88e6352_port_link_state, 2787 .port_get_cmode = mv88e6185_port_get_cmode, 2788 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2789 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2790 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2791 .stats_get_strings = mv88e6095_stats_get_strings, 2792 .stats_get_stats = mv88e6095_stats_get_stats, 2793 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2794 .set_egress_port = mv88e6095_g1_set_egress_port, 2795 .watchdog_ops = &mv88e6097_watchdog_ops, 2796 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2797 .pot_clear = mv88e6xxx_g2_pot_clear, 2798 .ppu_enable = mv88e6185_g1_ppu_enable, 2799 .ppu_disable = mv88e6185_g1_ppu_disable, 2800 .reset = mv88e6185_g1_reset, 2801 .rmu_disable = mv88e6085_g1_rmu_disable, 2802 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2803 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2804 .phylink_validate = mv88e6185_phylink_validate, 2805 }; 2806 2807 static const struct mv88e6xxx_ops mv88e6095_ops = { 2808 /* MV88E6XXX_FAMILY_6095 */ 2809 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2810 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2811 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2812 .phy_read = mv88e6185_phy_ppu_read, 2813 .phy_write = mv88e6185_phy_ppu_write, 2814 .port_set_link = mv88e6xxx_port_set_link, 2815 .port_set_duplex = mv88e6xxx_port_set_duplex, 2816 .port_set_speed = mv88e6185_port_set_speed, 2817 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2818 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2819 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2820 .port_link_state = mv88e6185_port_link_state, 2821 .port_get_cmode = mv88e6185_port_get_cmode, 2822 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2823 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2824 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2825 .stats_get_strings = mv88e6095_stats_get_strings, 2826 .stats_get_stats = mv88e6095_stats_get_stats, 2827 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2828 .ppu_enable = mv88e6185_g1_ppu_enable, 2829 .ppu_disable = mv88e6185_g1_ppu_disable, 2830 .reset = mv88e6185_g1_reset, 2831 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2832 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2833 .phylink_validate = mv88e6185_phylink_validate, 2834 }; 2835 2836 static const struct mv88e6xxx_ops mv88e6097_ops = { 2837 /* MV88E6XXX_FAMILY_6097 */ 2838 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2839 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2840 .irl_init_all = mv88e6352_g2_irl_init_all, 2841 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2842 .phy_read = mv88e6xxx_g2_smi_phy_read, 2843 .phy_write = mv88e6xxx_g2_smi_phy_write, 2844 .port_set_link = mv88e6xxx_port_set_link, 2845 .port_set_duplex = mv88e6xxx_port_set_duplex, 2846 .port_set_speed = mv88e6185_port_set_speed, 2847 .port_tag_remap = mv88e6095_port_tag_remap, 2848 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2849 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2850 .port_set_ether_type = mv88e6351_port_set_ether_type, 2851 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2852 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2853 .port_pause_limit = mv88e6097_port_pause_limit, 2854 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2855 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2856 .port_link_state = mv88e6352_port_link_state, 2857 .port_get_cmode = mv88e6185_port_get_cmode, 2858 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2859 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2860 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2861 .stats_get_strings = mv88e6095_stats_get_strings, 2862 .stats_get_stats = mv88e6095_stats_get_stats, 2863 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2864 .set_egress_port = mv88e6095_g1_set_egress_port, 2865 .watchdog_ops = &mv88e6097_watchdog_ops, 2866 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2867 .pot_clear = mv88e6xxx_g2_pot_clear, 2868 .reset = mv88e6352_g1_reset, 2869 .rmu_disable = mv88e6085_g1_rmu_disable, 2870 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2871 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2872 .phylink_validate = mv88e6185_phylink_validate, 2873 }; 2874 2875 static const struct mv88e6xxx_ops mv88e6123_ops = { 2876 /* MV88E6XXX_FAMILY_6165 */ 2877 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2878 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2879 .irl_init_all = mv88e6352_g2_irl_init_all, 2880 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2881 .phy_read = mv88e6xxx_g2_smi_phy_read, 2882 .phy_write = mv88e6xxx_g2_smi_phy_write, 2883 .port_set_link = mv88e6xxx_port_set_link, 2884 .port_set_duplex = mv88e6xxx_port_set_duplex, 2885 .port_set_speed = mv88e6185_port_set_speed, 2886 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2887 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2888 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2889 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2890 .port_link_state = mv88e6352_port_link_state, 2891 .port_get_cmode = mv88e6185_port_get_cmode, 2892 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2893 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2894 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2895 .stats_get_strings = mv88e6095_stats_get_strings, 2896 .stats_get_stats = mv88e6095_stats_get_stats, 2897 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2898 .set_egress_port = mv88e6095_g1_set_egress_port, 2899 .watchdog_ops = &mv88e6097_watchdog_ops, 2900 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2901 .pot_clear = mv88e6xxx_g2_pot_clear, 2902 .reset = mv88e6352_g1_reset, 2903 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2904 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2905 .phylink_validate = mv88e6185_phylink_validate, 2906 }; 2907 2908 static const struct mv88e6xxx_ops mv88e6131_ops = { 2909 /* MV88E6XXX_FAMILY_6185 */ 2910 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2911 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2912 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2913 .phy_read = mv88e6185_phy_ppu_read, 2914 .phy_write = mv88e6185_phy_ppu_write, 2915 .port_set_link = mv88e6xxx_port_set_link, 2916 .port_set_duplex = mv88e6xxx_port_set_duplex, 2917 .port_set_speed = mv88e6185_port_set_speed, 2918 .port_tag_remap = mv88e6095_port_tag_remap, 2919 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2920 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2921 .port_set_ether_type = mv88e6351_port_set_ether_type, 2922 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2923 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2924 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2925 .port_pause_limit = mv88e6097_port_pause_limit, 2926 .port_set_pause = mv88e6185_port_set_pause, 2927 .port_link_state = mv88e6352_port_link_state, 2928 .port_get_cmode = mv88e6185_port_get_cmode, 2929 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2930 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2931 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2932 .stats_get_strings = mv88e6095_stats_get_strings, 2933 .stats_get_stats = mv88e6095_stats_get_stats, 2934 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2935 .set_egress_port = mv88e6095_g1_set_egress_port, 2936 .watchdog_ops = &mv88e6097_watchdog_ops, 2937 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2938 .ppu_enable = mv88e6185_g1_ppu_enable, 2939 .set_cascade_port = mv88e6185_g1_set_cascade_port, 2940 .ppu_disable = mv88e6185_g1_ppu_disable, 2941 .reset = mv88e6185_g1_reset, 2942 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2943 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2944 .phylink_validate = mv88e6185_phylink_validate, 2945 }; 2946 2947 static const struct mv88e6xxx_ops mv88e6141_ops = { 2948 /* MV88E6XXX_FAMILY_6341 */ 2949 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2950 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2951 .irl_init_all = mv88e6352_g2_irl_init_all, 2952 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2953 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2954 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2955 .phy_read = mv88e6xxx_g2_smi_phy_read, 2956 .phy_write = mv88e6xxx_g2_smi_phy_write, 2957 .port_set_link = mv88e6xxx_port_set_link, 2958 .port_set_duplex = mv88e6xxx_port_set_duplex, 2959 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2960 .port_set_speed = mv88e6341_port_set_speed, 2961 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 2962 .port_tag_remap = mv88e6095_port_tag_remap, 2963 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2964 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2965 .port_set_ether_type = mv88e6351_port_set_ether_type, 2966 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2967 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2968 .port_pause_limit = mv88e6097_port_pause_limit, 2969 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2970 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2971 .port_link_state = mv88e6352_port_link_state, 2972 .port_get_cmode = mv88e6352_port_get_cmode, 2973 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2974 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 2975 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2976 .stats_get_strings = mv88e6320_stats_get_strings, 2977 .stats_get_stats = mv88e6390_stats_get_stats, 2978 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2979 .set_egress_port = mv88e6390_g1_set_egress_port, 2980 .watchdog_ops = &mv88e6390_watchdog_ops, 2981 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2982 .pot_clear = mv88e6xxx_g2_pot_clear, 2983 .reset = mv88e6352_g1_reset, 2984 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2985 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2986 .serdes_power = mv88e6341_serdes_power, 2987 .gpio_ops = &mv88e6352_gpio_ops, 2988 .phylink_validate = mv88e6341_phylink_validate, 2989 }; 2990 2991 static const struct mv88e6xxx_ops mv88e6161_ops = { 2992 /* MV88E6XXX_FAMILY_6165 */ 2993 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2994 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2995 .irl_init_all = mv88e6352_g2_irl_init_all, 2996 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2997 .phy_read = mv88e6xxx_g2_smi_phy_read, 2998 .phy_write = mv88e6xxx_g2_smi_phy_write, 2999 .port_set_link = mv88e6xxx_port_set_link, 3000 .port_set_duplex = mv88e6xxx_port_set_duplex, 3001 .port_set_speed = mv88e6185_port_set_speed, 3002 .port_tag_remap = mv88e6095_port_tag_remap, 3003 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3004 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3005 .port_set_ether_type = mv88e6351_port_set_ether_type, 3006 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3007 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3008 .port_pause_limit = mv88e6097_port_pause_limit, 3009 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3010 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3011 .port_link_state = mv88e6352_port_link_state, 3012 .port_get_cmode = mv88e6185_port_get_cmode, 3013 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3014 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3015 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3016 .stats_get_strings = mv88e6095_stats_get_strings, 3017 .stats_get_stats = mv88e6095_stats_get_stats, 3018 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3019 .set_egress_port = mv88e6095_g1_set_egress_port, 3020 .watchdog_ops = &mv88e6097_watchdog_ops, 3021 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3022 .pot_clear = mv88e6xxx_g2_pot_clear, 3023 .reset = mv88e6352_g1_reset, 3024 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3025 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3026 .avb_ops = &mv88e6165_avb_ops, 3027 .ptp_ops = &mv88e6165_ptp_ops, 3028 .phylink_validate = mv88e6185_phylink_validate, 3029 }; 3030 3031 static const struct mv88e6xxx_ops mv88e6165_ops = { 3032 /* MV88E6XXX_FAMILY_6165 */ 3033 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3034 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3035 .irl_init_all = mv88e6352_g2_irl_init_all, 3036 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3037 .phy_read = mv88e6165_phy_read, 3038 .phy_write = mv88e6165_phy_write, 3039 .port_set_link = mv88e6xxx_port_set_link, 3040 .port_set_duplex = mv88e6xxx_port_set_duplex, 3041 .port_set_speed = mv88e6185_port_set_speed, 3042 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3043 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3044 .port_link_state = mv88e6352_port_link_state, 3045 .port_get_cmode = mv88e6185_port_get_cmode, 3046 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3047 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3048 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3049 .stats_get_strings = mv88e6095_stats_get_strings, 3050 .stats_get_stats = mv88e6095_stats_get_stats, 3051 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3052 .set_egress_port = mv88e6095_g1_set_egress_port, 3053 .watchdog_ops = &mv88e6097_watchdog_ops, 3054 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3055 .pot_clear = mv88e6xxx_g2_pot_clear, 3056 .reset = mv88e6352_g1_reset, 3057 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3058 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3059 .avb_ops = &mv88e6165_avb_ops, 3060 .ptp_ops = &mv88e6165_ptp_ops, 3061 .phylink_validate = mv88e6185_phylink_validate, 3062 }; 3063 3064 static const struct mv88e6xxx_ops mv88e6171_ops = { 3065 /* MV88E6XXX_FAMILY_6351 */ 3066 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3067 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3068 .irl_init_all = mv88e6352_g2_irl_init_all, 3069 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3070 .phy_read = mv88e6xxx_g2_smi_phy_read, 3071 .phy_write = mv88e6xxx_g2_smi_phy_write, 3072 .port_set_link = mv88e6xxx_port_set_link, 3073 .port_set_duplex = mv88e6xxx_port_set_duplex, 3074 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3075 .port_set_speed = mv88e6185_port_set_speed, 3076 .port_tag_remap = mv88e6095_port_tag_remap, 3077 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3078 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3079 .port_set_ether_type = mv88e6351_port_set_ether_type, 3080 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3081 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3082 .port_pause_limit = mv88e6097_port_pause_limit, 3083 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3084 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3085 .port_link_state = mv88e6352_port_link_state, 3086 .port_get_cmode = mv88e6352_port_get_cmode, 3087 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3088 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3089 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3090 .stats_get_strings = mv88e6095_stats_get_strings, 3091 .stats_get_stats = mv88e6095_stats_get_stats, 3092 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3093 .set_egress_port = mv88e6095_g1_set_egress_port, 3094 .watchdog_ops = &mv88e6097_watchdog_ops, 3095 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3096 .pot_clear = mv88e6xxx_g2_pot_clear, 3097 .reset = mv88e6352_g1_reset, 3098 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3099 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3100 .phylink_validate = mv88e6185_phylink_validate, 3101 }; 3102 3103 static const struct mv88e6xxx_ops mv88e6172_ops = { 3104 /* MV88E6XXX_FAMILY_6352 */ 3105 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3106 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3107 .irl_init_all = mv88e6352_g2_irl_init_all, 3108 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3109 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3110 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3111 .phy_read = mv88e6xxx_g2_smi_phy_read, 3112 .phy_write = mv88e6xxx_g2_smi_phy_write, 3113 .port_set_link = mv88e6xxx_port_set_link, 3114 .port_set_duplex = mv88e6xxx_port_set_duplex, 3115 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3116 .port_set_speed = mv88e6352_port_set_speed, 3117 .port_tag_remap = mv88e6095_port_tag_remap, 3118 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3119 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3120 .port_set_ether_type = mv88e6351_port_set_ether_type, 3121 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3122 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3123 .port_pause_limit = mv88e6097_port_pause_limit, 3124 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3125 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3126 .port_link_state = mv88e6352_port_link_state, 3127 .port_get_cmode = mv88e6352_port_get_cmode, 3128 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3129 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3130 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3131 .stats_get_strings = mv88e6095_stats_get_strings, 3132 .stats_get_stats = mv88e6095_stats_get_stats, 3133 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3134 .set_egress_port = mv88e6095_g1_set_egress_port, 3135 .watchdog_ops = &mv88e6097_watchdog_ops, 3136 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3137 .pot_clear = mv88e6xxx_g2_pot_clear, 3138 .reset = mv88e6352_g1_reset, 3139 .rmu_disable = mv88e6352_g1_rmu_disable, 3140 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3141 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3142 .serdes_power = mv88e6352_serdes_power, 3143 .gpio_ops = &mv88e6352_gpio_ops, 3144 .phylink_validate = mv88e6352_phylink_validate, 3145 }; 3146 3147 static const struct mv88e6xxx_ops mv88e6175_ops = { 3148 /* MV88E6XXX_FAMILY_6351 */ 3149 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3150 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3151 .irl_init_all = mv88e6352_g2_irl_init_all, 3152 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3153 .phy_read = mv88e6xxx_g2_smi_phy_read, 3154 .phy_write = mv88e6xxx_g2_smi_phy_write, 3155 .port_set_link = mv88e6xxx_port_set_link, 3156 .port_set_duplex = mv88e6xxx_port_set_duplex, 3157 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3158 .port_set_speed = mv88e6185_port_set_speed, 3159 .port_tag_remap = mv88e6095_port_tag_remap, 3160 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3161 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3162 .port_set_ether_type = mv88e6351_port_set_ether_type, 3163 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3164 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3165 .port_pause_limit = mv88e6097_port_pause_limit, 3166 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3167 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3168 .port_link_state = mv88e6352_port_link_state, 3169 .port_get_cmode = mv88e6352_port_get_cmode, 3170 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3171 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3172 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3173 .stats_get_strings = mv88e6095_stats_get_strings, 3174 .stats_get_stats = mv88e6095_stats_get_stats, 3175 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3176 .set_egress_port = mv88e6095_g1_set_egress_port, 3177 .watchdog_ops = &mv88e6097_watchdog_ops, 3178 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3179 .pot_clear = mv88e6xxx_g2_pot_clear, 3180 .reset = mv88e6352_g1_reset, 3181 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3182 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3183 .phylink_validate = mv88e6185_phylink_validate, 3184 }; 3185 3186 static const struct mv88e6xxx_ops mv88e6176_ops = { 3187 /* MV88E6XXX_FAMILY_6352 */ 3188 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3189 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3190 .irl_init_all = mv88e6352_g2_irl_init_all, 3191 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3192 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3193 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3194 .phy_read = mv88e6xxx_g2_smi_phy_read, 3195 .phy_write = mv88e6xxx_g2_smi_phy_write, 3196 .port_set_link = mv88e6xxx_port_set_link, 3197 .port_set_duplex = mv88e6xxx_port_set_duplex, 3198 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3199 .port_set_speed = mv88e6352_port_set_speed, 3200 .port_tag_remap = mv88e6095_port_tag_remap, 3201 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3202 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3203 .port_set_ether_type = mv88e6351_port_set_ether_type, 3204 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3205 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3206 .port_pause_limit = mv88e6097_port_pause_limit, 3207 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3208 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3209 .port_link_state = mv88e6352_port_link_state, 3210 .port_get_cmode = mv88e6352_port_get_cmode, 3211 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3212 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3213 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3214 .stats_get_strings = mv88e6095_stats_get_strings, 3215 .stats_get_stats = mv88e6095_stats_get_stats, 3216 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3217 .set_egress_port = mv88e6095_g1_set_egress_port, 3218 .watchdog_ops = &mv88e6097_watchdog_ops, 3219 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3220 .pot_clear = mv88e6xxx_g2_pot_clear, 3221 .reset = mv88e6352_g1_reset, 3222 .rmu_disable = mv88e6352_g1_rmu_disable, 3223 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3224 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3225 .serdes_power = mv88e6352_serdes_power, 3226 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3227 .serdes_irq_free = mv88e6352_serdes_irq_free, 3228 .gpio_ops = &mv88e6352_gpio_ops, 3229 .phylink_validate = mv88e6352_phylink_validate, 3230 }; 3231 3232 static const struct mv88e6xxx_ops mv88e6185_ops = { 3233 /* MV88E6XXX_FAMILY_6185 */ 3234 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3235 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3236 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3237 .phy_read = mv88e6185_phy_ppu_read, 3238 .phy_write = mv88e6185_phy_ppu_write, 3239 .port_set_link = mv88e6xxx_port_set_link, 3240 .port_set_duplex = mv88e6xxx_port_set_duplex, 3241 .port_set_speed = mv88e6185_port_set_speed, 3242 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3243 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3244 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3245 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3246 .port_set_pause = mv88e6185_port_set_pause, 3247 .port_link_state = mv88e6185_port_link_state, 3248 .port_get_cmode = mv88e6185_port_get_cmode, 3249 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3250 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3251 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3252 .stats_get_strings = mv88e6095_stats_get_strings, 3253 .stats_get_stats = mv88e6095_stats_get_stats, 3254 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3255 .set_egress_port = mv88e6095_g1_set_egress_port, 3256 .watchdog_ops = &mv88e6097_watchdog_ops, 3257 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3258 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3259 .ppu_enable = mv88e6185_g1_ppu_enable, 3260 .ppu_disable = mv88e6185_g1_ppu_disable, 3261 .reset = mv88e6185_g1_reset, 3262 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3263 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3264 .phylink_validate = mv88e6185_phylink_validate, 3265 }; 3266 3267 static const struct mv88e6xxx_ops mv88e6190_ops = { 3268 /* MV88E6XXX_FAMILY_6390 */ 3269 .setup_errata = mv88e6390_setup_errata, 3270 .irl_init_all = mv88e6390_g2_irl_init_all, 3271 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3272 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3273 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3274 .phy_read = mv88e6xxx_g2_smi_phy_read, 3275 .phy_write = mv88e6xxx_g2_smi_phy_write, 3276 .port_set_link = mv88e6xxx_port_set_link, 3277 .port_set_duplex = mv88e6xxx_port_set_duplex, 3278 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3279 .port_set_speed = mv88e6390_port_set_speed, 3280 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3281 .port_tag_remap = mv88e6390_port_tag_remap, 3282 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3283 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3284 .port_set_ether_type = mv88e6351_port_set_ether_type, 3285 .port_pause_limit = mv88e6390_port_pause_limit, 3286 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3287 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3288 .port_link_state = mv88e6352_port_link_state, 3289 .port_get_cmode = mv88e6352_port_get_cmode, 3290 .port_set_cmode = mv88e6390_port_set_cmode, 3291 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3292 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3293 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3294 .stats_get_strings = mv88e6320_stats_get_strings, 3295 .stats_get_stats = mv88e6390_stats_get_stats, 3296 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3297 .set_egress_port = mv88e6390_g1_set_egress_port, 3298 .watchdog_ops = &mv88e6390_watchdog_ops, 3299 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3300 .pot_clear = mv88e6xxx_g2_pot_clear, 3301 .reset = mv88e6352_g1_reset, 3302 .rmu_disable = mv88e6390_g1_rmu_disable, 3303 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3304 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3305 .serdes_power = mv88e6390_serdes_power, 3306 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3307 .serdes_irq_free = mv88e6390_serdes_irq_free, 3308 .gpio_ops = &mv88e6352_gpio_ops, 3309 .phylink_validate = mv88e6390_phylink_validate, 3310 }; 3311 3312 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3313 /* MV88E6XXX_FAMILY_6390 */ 3314 .setup_errata = mv88e6390_setup_errata, 3315 .irl_init_all = mv88e6390_g2_irl_init_all, 3316 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3317 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3318 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3319 .phy_read = mv88e6xxx_g2_smi_phy_read, 3320 .phy_write = mv88e6xxx_g2_smi_phy_write, 3321 .port_set_link = mv88e6xxx_port_set_link, 3322 .port_set_duplex = mv88e6xxx_port_set_duplex, 3323 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3324 .port_set_speed = mv88e6390x_port_set_speed, 3325 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3326 .port_tag_remap = mv88e6390_port_tag_remap, 3327 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3328 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3329 .port_set_ether_type = mv88e6351_port_set_ether_type, 3330 .port_pause_limit = mv88e6390_port_pause_limit, 3331 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3332 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3333 .port_link_state = mv88e6352_port_link_state, 3334 .port_get_cmode = mv88e6352_port_get_cmode, 3335 .port_set_cmode = mv88e6390x_port_set_cmode, 3336 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3337 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3338 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3339 .stats_get_strings = mv88e6320_stats_get_strings, 3340 .stats_get_stats = mv88e6390_stats_get_stats, 3341 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3342 .set_egress_port = mv88e6390_g1_set_egress_port, 3343 .watchdog_ops = &mv88e6390_watchdog_ops, 3344 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3345 .pot_clear = mv88e6xxx_g2_pot_clear, 3346 .reset = mv88e6352_g1_reset, 3347 .rmu_disable = mv88e6390_g1_rmu_disable, 3348 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3349 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3350 .serdes_power = mv88e6390x_serdes_power, 3351 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3352 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3353 .gpio_ops = &mv88e6352_gpio_ops, 3354 .phylink_validate = mv88e6390x_phylink_validate, 3355 }; 3356 3357 static const struct mv88e6xxx_ops mv88e6191_ops = { 3358 /* MV88E6XXX_FAMILY_6390 */ 3359 .setup_errata = mv88e6390_setup_errata, 3360 .irl_init_all = mv88e6390_g2_irl_init_all, 3361 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3362 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3363 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3364 .phy_read = mv88e6xxx_g2_smi_phy_read, 3365 .phy_write = mv88e6xxx_g2_smi_phy_write, 3366 .port_set_link = mv88e6xxx_port_set_link, 3367 .port_set_duplex = mv88e6xxx_port_set_duplex, 3368 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3369 .port_set_speed = mv88e6390_port_set_speed, 3370 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3371 .port_tag_remap = mv88e6390_port_tag_remap, 3372 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3373 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3374 .port_set_ether_type = mv88e6351_port_set_ether_type, 3375 .port_pause_limit = mv88e6390_port_pause_limit, 3376 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3377 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3378 .port_link_state = mv88e6352_port_link_state, 3379 .port_get_cmode = mv88e6352_port_get_cmode, 3380 .port_set_cmode = mv88e6390_port_set_cmode, 3381 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3382 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3383 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3384 .stats_get_strings = mv88e6320_stats_get_strings, 3385 .stats_get_stats = mv88e6390_stats_get_stats, 3386 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3387 .set_egress_port = mv88e6390_g1_set_egress_port, 3388 .watchdog_ops = &mv88e6390_watchdog_ops, 3389 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3390 .pot_clear = mv88e6xxx_g2_pot_clear, 3391 .reset = mv88e6352_g1_reset, 3392 .rmu_disable = mv88e6390_g1_rmu_disable, 3393 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3394 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3395 .serdes_power = mv88e6390_serdes_power, 3396 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3397 .serdes_irq_free = mv88e6390_serdes_irq_free, 3398 .avb_ops = &mv88e6390_avb_ops, 3399 .ptp_ops = &mv88e6352_ptp_ops, 3400 .phylink_validate = mv88e6390_phylink_validate, 3401 }; 3402 3403 static const struct mv88e6xxx_ops mv88e6240_ops = { 3404 /* MV88E6XXX_FAMILY_6352 */ 3405 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3406 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3407 .irl_init_all = mv88e6352_g2_irl_init_all, 3408 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3409 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3410 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3411 .phy_read = mv88e6xxx_g2_smi_phy_read, 3412 .phy_write = mv88e6xxx_g2_smi_phy_write, 3413 .port_set_link = mv88e6xxx_port_set_link, 3414 .port_set_duplex = mv88e6xxx_port_set_duplex, 3415 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3416 .port_set_speed = mv88e6352_port_set_speed, 3417 .port_tag_remap = mv88e6095_port_tag_remap, 3418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3419 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3420 .port_set_ether_type = mv88e6351_port_set_ether_type, 3421 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3422 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3423 .port_pause_limit = mv88e6097_port_pause_limit, 3424 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3425 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3426 .port_link_state = mv88e6352_port_link_state, 3427 .port_get_cmode = mv88e6352_port_get_cmode, 3428 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3429 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3430 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3431 .stats_get_strings = mv88e6095_stats_get_strings, 3432 .stats_get_stats = mv88e6095_stats_get_stats, 3433 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3434 .set_egress_port = mv88e6095_g1_set_egress_port, 3435 .watchdog_ops = &mv88e6097_watchdog_ops, 3436 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3437 .pot_clear = mv88e6xxx_g2_pot_clear, 3438 .reset = mv88e6352_g1_reset, 3439 .rmu_disable = mv88e6352_g1_rmu_disable, 3440 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3441 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3442 .serdes_power = mv88e6352_serdes_power, 3443 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3444 .serdes_irq_free = mv88e6352_serdes_irq_free, 3445 .gpio_ops = &mv88e6352_gpio_ops, 3446 .avb_ops = &mv88e6352_avb_ops, 3447 .ptp_ops = &mv88e6352_ptp_ops, 3448 .phylink_validate = mv88e6352_phylink_validate, 3449 }; 3450 3451 static const struct mv88e6xxx_ops mv88e6290_ops = { 3452 /* MV88E6XXX_FAMILY_6390 */ 3453 .setup_errata = mv88e6390_setup_errata, 3454 .irl_init_all = mv88e6390_g2_irl_init_all, 3455 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3456 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3457 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3458 .phy_read = mv88e6xxx_g2_smi_phy_read, 3459 .phy_write = mv88e6xxx_g2_smi_phy_write, 3460 .port_set_link = mv88e6xxx_port_set_link, 3461 .port_set_duplex = mv88e6xxx_port_set_duplex, 3462 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3463 .port_set_speed = mv88e6390_port_set_speed, 3464 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3465 .port_tag_remap = mv88e6390_port_tag_remap, 3466 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3467 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3468 .port_set_ether_type = mv88e6351_port_set_ether_type, 3469 .port_pause_limit = mv88e6390_port_pause_limit, 3470 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3471 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3472 .port_link_state = mv88e6352_port_link_state, 3473 .port_get_cmode = mv88e6352_port_get_cmode, 3474 .port_set_cmode = mv88e6390_port_set_cmode, 3475 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3476 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3477 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3478 .stats_get_strings = mv88e6320_stats_get_strings, 3479 .stats_get_stats = mv88e6390_stats_get_stats, 3480 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3481 .set_egress_port = mv88e6390_g1_set_egress_port, 3482 .watchdog_ops = &mv88e6390_watchdog_ops, 3483 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3484 .pot_clear = mv88e6xxx_g2_pot_clear, 3485 .reset = mv88e6352_g1_reset, 3486 .rmu_disable = mv88e6390_g1_rmu_disable, 3487 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3488 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3489 .serdes_power = mv88e6390_serdes_power, 3490 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3491 .serdes_irq_free = mv88e6390_serdes_irq_free, 3492 .gpio_ops = &mv88e6352_gpio_ops, 3493 .avb_ops = &mv88e6390_avb_ops, 3494 .ptp_ops = &mv88e6352_ptp_ops, 3495 .phylink_validate = mv88e6390_phylink_validate, 3496 }; 3497 3498 static const struct mv88e6xxx_ops mv88e6320_ops = { 3499 /* MV88E6XXX_FAMILY_6320 */ 3500 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3501 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3502 .irl_init_all = mv88e6352_g2_irl_init_all, 3503 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3504 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3505 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3506 .phy_read = mv88e6xxx_g2_smi_phy_read, 3507 .phy_write = mv88e6xxx_g2_smi_phy_write, 3508 .port_set_link = mv88e6xxx_port_set_link, 3509 .port_set_duplex = mv88e6xxx_port_set_duplex, 3510 .port_set_speed = mv88e6185_port_set_speed, 3511 .port_tag_remap = mv88e6095_port_tag_remap, 3512 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3513 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3514 .port_set_ether_type = mv88e6351_port_set_ether_type, 3515 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3516 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3517 .port_pause_limit = mv88e6097_port_pause_limit, 3518 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3519 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3520 .port_link_state = mv88e6352_port_link_state, 3521 .port_get_cmode = mv88e6352_port_get_cmode, 3522 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3523 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3524 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3525 .stats_get_strings = mv88e6320_stats_get_strings, 3526 .stats_get_stats = mv88e6320_stats_get_stats, 3527 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3528 .set_egress_port = mv88e6095_g1_set_egress_port, 3529 .watchdog_ops = &mv88e6390_watchdog_ops, 3530 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3531 .pot_clear = mv88e6xxx_g2_pot_clear, 3532 .reset = mv88e6352_g1_reset, 3533 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3534 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3535 .gpio_ops = &mv88e6352_gpio_ops, 3536 .avb_ops = &mv88e6352_avb_ops, 3537 .ptp_ops = &mv88e6352_ptp_ops, 3538 .phylink_validate = mv88e6185_phylink_validate, 3539 }; 3540 3541 static const struct mv88e6xxx_ops mv88e6321_ops = { 3542 /* MV88E6XXX_FAMILY_6320 */ 3543 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3544 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3545 .irl_init_all = mv88e6352_g2_irl_init_all, 3546 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3547 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3548 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3549 .phy_read = mv88e6xxx_g2_smi_phy_read, 3550 .phy_write = mv88e6xxx_g2_smi_phy_write, 3551 .port_set_link = mv88e6xxx_port_set_link, 3552 .port_set_duplex = mv88e6xxx_port_set_duplex, 3553 .port_set_speed = mv88e6185_port_set_speed, 3554 .port_tag_remap = mv88e6095_port_tag_remap, 3555 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3556 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3557 .port_set_ether_type = mv88e6351_port_set_ether_type, 3558 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3559 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3560 .port_pause_limit = mv88e6097_port_pause_limit, 3561 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3562 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3563 .port_link_state = mv88e6352_port_link_state, 3564 .port_get_cmode = mv88e6352_port_get_cmode, 3565 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3566 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3567 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3568 .stats_get_strings = mv88e6320_stats_get_strings, 3569 .stats_get_stats = mv88e6320_stats_get_stats, 3570 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3571 .set_egress_port = mv88e6095_g1_set_egress_port, 3572 .watchdog_ops = &mv88e6390_watchdog_ops, 3573 .reset = mv88e6352_g1_reset, 3574 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3575 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3576 .gpio_ops = &mv88e6352_gpio_ops, 3577 .avb_ops = &mv88e6352_avb_ops, 3578 .ptp_ops = &mv88e6352_ptp_ops, 3579 .phylink_validate = mv88e6185_phylink_validate, 3580 }; 3581 3582 static const struct mv88e6xxx_ops mv88e6341_ops = { 3583 /* MV88E6XXX_FAMILY_6341 */ 3584 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3585 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3586 .irl_init_all = mv88e6352_g2_irl_init_all, 3587 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3588 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3589 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3590 .phy_read = mv88e6xxx_g2_smi_phy_read, 3591 .phy_write = mv88e6xxx_g2_smi_phy_write, 3592 .port_set_link = mv88e6xxx_port_set_link, 3593 .port_set_duplex = mv88e6xxx_port_set_duplex, 3594 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3595 .port_set_speed = mv88e6341_port_set_speed, 3596 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3597 .port_tag_remap = mv88e6095_port_tag_remap, 3598 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3599 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3600 .port_set_ether_type = mv88e6351_port_set_ether_type, 3601 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3602 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3603 .port_pause_limit = mv88e6097_port_pause_limit, 3604 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3605 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3606 .port_link_state = mv88e6352_port_link_state, 3607 .port_get_cmode = mv88e6352_port_get_cmode, 3608 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3609 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3610 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3611 .stats_get_strings = mv88e6320_stats_get_strings, 3612 .stats_get_stats = mv88e6390_stats_get_stats, 3613 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3614 .set_egress_port = mv88e6390_g1_set_egress_port, 3615 .watchdog_ops = &mv88e6390_watchdog_ops, 3616 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3617 .pot_clear = mv88e6xxx_g2_pot_clear, 3618 .reset = mv88e6352_g1_reset, 3619 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3620 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3621 .serdes_power = mv88e6341_serdes_power, 3622 .gpio_ops = &mv88e6352_gpio_ops, 3623 .avb_ops = &mv88e6390_avb_ops, 3624 .ptp_ops = &mv88e6352_ptp_ops, 3625 .phylink_validate = mv88e6341_phylink_validate, 3626 }; 3627 3628 static const struct mv88e6xxx_ops mv88e6350_ops = { 3629 /* MV88E6XXX_FAMILY_6351 */ 3630 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3631 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3632 .irl_init_all = mv88e6352_g2_irl_init_all, 3633 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3634 .phy_read = mv88e6xxx_g2_smi_phy_read, 3635 .phy_write = mv88e6xxx_g2_smi_phy_write, 3636 .port_set_link = mv88e6xxx_port_set_link, 3637 .port_set_duplex = mv88e6xxx_port_set_duplex, 3638 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3639 .port_set_speed = mv88e6185_port_set_speed, 3640 .port_tag_remap = mv88e6095_port_tag_remap, 3641 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3642 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3643 .port_set_ether_type = mv88e6351_port_set_ether_type, 3644 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3645 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3646 .port_pause_limit = mv88e6097_port_pause_limit, 3647 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3648 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3649 .port_link_state = mv88e6352_port_link_state, 3650 .port_get_cmode = mv88e6352_port_get_cmode, 3651 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3652 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3653 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3654 .stats_get_strings = mv88e6095_stats_get_strings, 3655 .stats_get_stats = mv88e6095_stats_get_stats, 3656 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3657 .set_egress_port = mv88e6095_g1_set_egress_port, 3658 .watchdog_ops = &mv88e6097_watchdog_ops, 3659 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3660 .pot_clear = mv88e6xxx_g2_pot_clear, 3661 .reset = mv88e6352_g1_reset, 3662 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3663 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3664 .phylink_validate = mv88e6185_phylink_validate, 3665 }; 3666 3667 static const struct mv88e6xxx_ops mv88e6351_ops = { 3668 /* MV88E6XXX_FAMILY_6351 */ 3669 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3670 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3671 .irl_init_all = mv88e6352_g2_irl_init_all, 3672 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3673 .phy_read = mv88e6xxx_g2_smi_phy_read, 3674 .phy_write = mv88e6xxx_g2_smi_phy_write, 3675 .port_set_link = mv88e6xxx_port_set_link, 3676 .port_set_duplex = mv88e6xxx_port_set_duplex, 3677 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3678 .port_set_speed = mv88e6185_port_set_speed, 3679 .port_tag_remap = mv88e6095_port_tag_remap, 3680 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3681 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3682 .port_set_ether_type = mv88e6351_port_set_ether_type, 3683 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3684 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3685 .port_pause_limit = mv88e6097_port_pause_limit, 3686 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3687 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3688 .port_link_state = mv88e6352_port_link_state, 3689 .port_get_cmode = mv88e6352_port_get_cmode, 3690 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3691 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3692 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3693 .stats_get_strings = mv88e6095_stats_get_strings, 3694 .stats_get_stats = mv88e6095_stats_get_stats, 3695 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3696 .set_egress_port = mv88e6095_g1_set_egress_port, 3697 .watchdog_ops = &mv88e6097_watchdog_ops, 3698 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3699 .pot_clear = mv88e6xxx_g2_pot_clear, 3700 .reset = mv88e6352_g1_reset, 3701 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3702 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3703 .avb_ops = &mv88e6352_avb_ops, 3704 .ptp_ops = &mv88e6352_ptp_ops, 3705 .phylink_validate = mv88e6185_phylink_validate, 3706 }; 3707 3708 static const struct mv88e6xxx_ops mv88e6352_ops = { 3709 /* MV88E6XXX_FAMILY_6352 */ 3710 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3711 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3712 .irl_init_all = mv88e6352_g2_irl_init_all, 3713 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3714 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3715 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3716 .phy_read = mv88e6xxx_g2_smi_phy_read, 3717 .phy_write = mv88e6xxx_g2_smi_phy_write, 3718 .port_set_link = mv88e6xxx_port_set_link, 3719 .port_set_duplex = mv88e6xxx_port_set_duplex, 3720 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3721 .port_set_speed = mv88e6352_port_set_speed, 3722 .port_tag_remap = mv88e6095_port_tag_remap, 3723 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3724 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3725 .port_set_ether_type = mv88e6351_port_set_ether_type, 3726 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3727 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3728 .port_pause_limit = mv88e6097_port_pause_limit, 3729 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3730 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3731 .port_link_state = mv88e6352_port_link_state, 3732 .port_get_cmode = mv88e6352_port_get_cmode, 3733 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3734 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3735 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3736 .stats_get_strings = mv88e6095_stats_get_strings, 3737 .stats_get_stats = mv88e6095_stats_get_stats, 3738 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3739 .set_egress_port = mv88e6095_g1_set_egress_port, 3740 .watchdog_ops = &mv88e6097_watchdog_ops, 3741 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3742 .pot_clear = mv88e6xxx_g2_pot_clear, 3743 .reset = mv88e6352_g1_reset, 3744 .rmu_disable = mv88e6352_g1_rmu_disable, 3745 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3746 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3747 .serdes_power = mv88e6352_serdes_power, 3748 .serdes_irq_setup = mv88e6352_serdes_irq_setup, 3749 .serdes_irq_free = mv88e6352_serdes_irq_free, 3750 .gpio_ops = &mv88e6352_gpio_ops, 3751 .avb_ops = &mv88e6352_avb_ops, 3752 .ptp_ops = &mv88e6352_ptp_ops, 3753 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 3754 .serdes_get_strings = mv88e6352_serdes_get_strings, 3755 .serdes_get_stats = mv88e6352_serdes_get_stats, 3756 .phylink_validate = mv88e6352_phylink_validate, 3757 }; 3758 3759 static const struct mv88e6xxx_ops mv88e6390_ops = { 3760 /* MV88E6XXX_FAMILY_6390 */ 3761 .setup_errata = mv88e6390_setup_errata, 3762 .irl_init_all = mv88e6390_g2_irl_init_all, 3763 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3764 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3765 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3766 .phy_read = mv88e6xxx_g2_smi_phy_read, 3767 .phy_write = mv88e6xxx_g2_smi_phy_write, 3768 .port_set_link = mv88e6xxx_port_set_link, 3769 .port_set_duplex = mv88e6xxx_port_set_duplex, 3770 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3771 .port_set_speed = mv88e6390_port_set_speed, 3772 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3773 .port_tag_remap = mv88e6390_port_tag_remap, 3774 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3775 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3776 .port_set_ether_type = mv88e6351_port_set_ether_type, 3777 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3778 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3779 .port_pause_limit = mv88e6390_port_pause_limit, 3780 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3781 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3782 .port_link_state = mv88e6352_port_link_state, 3783 .port_get_cmode = mv88e6352_port_get_cmode, 3784 .port_set_cmode = mv88e6390_port_set_cmode, 3785 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3786 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3787 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3788 .stats_get_strings = mv88e6320_stats_get_strings, 3789 .stats_get_stats = mv88e6390_stats_get_stats, 3790 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3791 .set_egress_port = mv88e6390_g1_set_egress_port, 3792 .watchdog_ops = &mv88e6390_watchdog_ops, 3793 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3794 .pot_clear = mv88e6xxx_g2_pot_clear, 3795 .reset = mv88e6352_g1_reset, 3796 .rmu_disable = mv88e6390_g1_rmu_disable, 3797 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3798 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3799 .serdes_power = mv88e6390_serdes_power, 3800 .serdes_irq_setup = mv88e6390_serdes_irq_setup, 3801 .serdes_irq_free = mv88e6390_serdes_irq_free, 3802 .gpio_ops = &mv88e6352_gpio_ops, 3803 .avb_ops = &mv88e6390_avb_ops, 3804 .ptp_ops = &mv88e6352_ptp_ops, 3805 .phylink_validate = mv88e6390_phylink_validate, 3806 }; 3807 3808 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3809 /* MV88E6XXX_FAMILY_6390 */ 3810 .setup_errata = mv88e6390_setup_errata, 3811 .irl_init_all = mv88e6390_g2_irl_init_all, 3812 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3813 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3814 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3815 .phy_read = mv88e6xxx_g2_smi_phy_read, 3816 .phy_write = mv88e6xxx_g2_smi_phy_write, 3817 .port_set_link = mv88e6xxx_port_set_link, 3818 .port_set_duplex = mv88e6xxx_port_set_duplex, 3819 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3820 .port_set_speed = mv88e6390x_port_set_speed, 3821 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3822 .port_tag_remap = mv88e6390_port_tag_remap, 3823 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3824 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3825 .port_set_ether_type = mv88e6351_port_set_ether_type, 3826 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3827 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3828 .port_pause_limit = mv88e6390_port_pause_limit, 3829 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3830 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3831 .port_link_state = mv88e6352_port_link_state, 3832 .port_get_cmode = mv88e6352_port_get_cmode, 3833 .port_set_cmode = mv88e6390x_port_set_cmode, 3834 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3835 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3836 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3837 .stats_get_strings = mv88e6320_stats_get_strings, 3838 .stats_get_stats = mv88e6390_stats_get_stats, 3839 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3840 .set_egress_port = mv88e6390_g1_set_egress_port, 3841 .watchdog_ops = &mv88e6390_watchdog_ops, 3842 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3843 .pot_clear = mv88e6xxx_g2_pot_clear, 3844 .reset = mv88e6352_g1_reset, 3845 .rmu_disable = mv88e6390_g1_rmu_disable, 3846 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3847 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3848 .serdes_power = mv88e6390x_serdes_power, 3849 .serdes_irq_setup = mv88e6390x_serdes_irq_setup, 3850 .serdes_irq_free = mv88e6390x_serdes_irq_free, 3851 .gpio_ops = &mv88e6352_gpio_ops, 3852 .avb_ops = &mv88e6390_avb_ops, 3853 .ptp_ops = &mv88e6352_ptp_ops, 3854 .phylink_validate = mv88e6390x_phylink_validate, 3855 }; 3856 3857 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3858 [MV88E6085] = { 3859 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3860 .family = MV88E6XXX_FAMILY_6097, 3861 .name = "Marvell 88E6085", 3862 .num_databases = 4096, 3863 .num_ports = 10, 3864 .num_internal_phys = 5, 3865 .max_vid = 4095, 3866 .port_base_addr = 0x10, 3867 .phy_base_addr = 0x0, 3868 .global1_addr = 0x1b, 3869 .global2_addr = 0x1c, 3870 .age_time_coeff = 15000, 3871 .g1_irqs = 8, 3872 .g2_irqs = 10, 3873 .atu_move_port_mask = 0xf, 3874 .pvt = true, 3875 .multi_chip = true, 3876 .tag_protocol = DSA_TAG_PROTO_DSA, 3877 .ops = &mv88e6085_ops, 3878 }, 3879 3880 [MV88E6095] = { 3881 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3882 .family = MV88E6XXX_FAMILY_6095, 3883 .name = "Marvell 88E6095/88E6095F", 3884 .num_databases = 256, 3885 .num_ports = 11, 3886 .num_internal_phys = 0, 3887 .max_vid = 4095, 3888 .port_base_addr = 0x10, 3889 .phy_base_addr = 0x0, 3890 .global1_addr = 0x1b, 3891 .global2_addr = 0x1c, 3892 .age_time_coeff = 15000, 3893 .g1_irqs = 8, 3894 .atu_move_port_mask = 0xf, 3895 .multi_chip = true, 3896 .tag_protocol = DSA_TAG_PROTO_DSA, 3897 .ops = &mv88e6095_ops, 3898 }, 3899 3900 [MV88E6097] = { 3901 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3902 .family = MV88E6XXX_FAMILY_6097, 3903 .name = "Marvell 88E6097/88E6097F", 3904 .num_databases = 4096, 3905 .num_ports = 11, 3906 .num_internal_phys = 8, 3907 .max_vid = 4095, 3908 .port_base_addr = 0x10, 3909 .phy_base_addr = 0x0, 3910 .global1_addr = 0x1b, 3911 .global2_addr = 0x1c, 3912 .age_time_coeff = 15000, 3913 .g1_irqs = 8, 3914 .g2_irqs = 10, 3915 .atu_move_port_mask = 0xf, 3916 .pvt = true, 3917 .multi_chip = true, 3918 .tag_protocol = DSA_TAG_PROTO_EDSA, 3919 .ops = &mv88e6097_ops, 3920 }, 3921 3922 [MV88E6123] = { 3923 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3924 .family = MV88E6XXX_FAMILY_6165, 3925 .name = "Marvell 88E6123", 3926 .num_databases = 4096, 3927 .num_ports = 3, 3928 .num_internal_phys = 5, 3929 .max_vid = 4095, 3930 .port_base_addr = 0x10, 3931 .phy_base_addr = 0x0, 3932 .global1_addr = 0x1b, 3933 .global2_addr = 0x1c, 3934 .age_time_coeff = 15000, 3935 .g1_irqs = 9, 3936 .g2_irqs = 10, 3937 .atu_move_port_mask = 0xf, 3938 .pvt = true, 3939 .multi_chip = true, 3940 .tag_protocol = DSA_TAG_PROTO_EDSA, 3941 .ops = &mv88e6123_ops, 3942 }, 3943 3944 [MV88E6131] = { 3945 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3946 .family = MV88E6XXX_FAMILY_6185, 3947 .name = "Marvell 88E6131", 3948 .num_databases = 256, 3949 .num_ports = 8, 3950 .num_internal_phys = 0, 3951 .max_vid = 4095, 3952 .port_base_addr = 0x10, 3953 .phy_base_addr = 0x0, 3954 .global1_addr = 0x1b, 3955 .global2_addr = 0x1c, 3956 .age_time_coeff = 15000, 3957 .g1_irqs = 9, 3958 .atu_move_port_mask = 0xf, 3959 .multi_chip = true, 3960 .tag_protocol = DSA_TAG_PROTO_DSA, 3961 .ops = &mv88e6131_ops, 3962 }, 3963 3964 [MV88E6141] = { 3965 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3966 .family = MV88E6XXX_FAMILY_6341, 3967 .name = "Marvell 88E6141", 3968 .num_databases = 4096, 3969 .num_ports = 6, 3970 .num_internal_phys = 5, 3971 .num_gpio = 11, 3972 .max_vid = 4095, 3973 .port_base_addr = 0x10, 3974 .phy_base_addr = 0x10, 3975 .global1_addr = 0x1b, 3976 .global2_addr = 0x1c, 3977 .age_time_coeff = 3750, 3978 .atu_move_port_mask = 0x1f, 3979 .g1_irqs = 9, 3980 .g2_irqs = 10, 3981 .pvt = true, 3982 .multi_chip = true, 3983 .tag_protocol = DSA_TAG_PROTO_EDSA, 3984 .ops = &mv88e6141_ops, 3985 }, 3986 3987 [MV88E6161] = { 3988 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3989 .family = MV88E6XXX_FAMILY_6165, 3990 .name = "Marvell 88E6161", 3991 .num_databases = 4096, 3992 .num_ports = 6, 3993 .num_internal_phys = 5, 3994 .max_vid = 4095, 3995 .port_base_addr = 0x10, 3996 .phy_base_addr = 0x0, 3997 .global1_addr = 0x1b, 3998 .global2_addr = 0x1c, 3999 .age_time_coeff = 15000, 4000 .g1_irqs = 9, 4001 .g2_irqs = 10, 4002 .atu_move_port_mask = 0xf, 4003 .pvt = true, 4004 .multi_chip = true, 4005 .tag_protocol = DSA_TAG_PROTO_EDSA, 4006 .ptp_support = true, 4007 .ops = &mv88e6161_ops, 4008 }, 4009 4010 [MV88E6165] = { 4011 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4012 .family = MV88E6XXX_FAMILY_6165, 4013 .name = "Marvell 88E6165", 4014 .num_databases = 4096, 4015 .num_ports = 6, 4016 .num_internal_phys = 0, 4017 .max_vid = 4095, 4018 .port_base_addr = 0x10, 4019 .phy_base_addr = 0x0, 4020 .global1_addr = 0x1b, 4021 .global2_addr = 0x1c, 4022 .age_time_coeff = 15000, 4023 .g1_irqs = 9, 4024 .g2_irqs = 10, 4025 .atu_move_port_mask = 0xf, 4026 .pvt = true, 4027 .multi_chip = true, 4028 .tag_protocol = DSA_TAG_PROTO_DSA, 4029 .ptp_support = true, 4030 .ops = &mv88e6165_ops, 4031 }, 4032 4033 [MV88E6171] = { 4034 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4035 .family = MV88E6XXX_FAMILY_6351, 4036 .name = "Marvell 88E6171", 4037 .num_databases = 4096, 4038 .num_ports = 7, 4039 .num_internal_phys = 5, 4040 .max_vid = 4095, 4041 .port_base_addr = 0x10, 4042 .phy_base_addr = 0x0, 4043 .global1_addr = 0x1b, 4044 .global2_addr = 0x1c, 4045 .age_time_coeff = 15000, 4046 .g1_irqs = 9, 4047 .g2_irqs = 10, 4048 .atu_move_port_mask = 0xf, 4049 .pvt = true, 4050 .multi_chip = true, 4051 .tag_protocol = DSA_TAG_PROTO_EDSA, 4052 .ops = &mv88e6171_ops, 4053 }, 4054 4055 [MV88E6172] = { 4056 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4057 .family = MV88E6XXX_FAMILY_6352, 4058 .name = "Marvell 88E6172", 4059 .num_databases = 4096, 4060 .num_ports = 7, 4061 .num_internal_phys = 5, 4062 .num_gpio = 15, 4063 .max_vid = 4095, 4064 .port_base_addr = 0x10, 4065 .phy_base_addr = 0x0, 4066 .global1_addr = 0x1b, 4067 .global2_addr = 0x1c, 4068 .age_time_coeff = 15000, 4069 .g1_irqs = 9, 4070 .g2_irqs = 10, 4071 .atu_move_port_mask = 0xf, 4072 .pvt = true, 4073 .multi_chip = true, 4074 .tag_protocol = DSA_TAG_PROTO_EDSA, 4075 .ops = &mv88e6172_ops, 4076 }, 4077 4078 [MV88E6175] = { 4079 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4080 .family = MV88E6XXX_FAMILY_6351, 4081 .name = "Marvell 88E6175", 4082 .num_databases = 4096, 4083 .num_ports = 7, 4084 .num_internal_phys = 5, 4085 .max_vid = 4095, 4086 .port_base_addr = 0x10, 4087 .phy_base_addr = 0x0, 4088 .global1_addr = 0x1b, 4089 .global2_addr = 0x1c, 4090 .age_time_coeff = 15000, 4091 .g1_irqs = 9, 4092 .g2_irqs = 10, 4093 .atu_move_port_mask = 0xf, 4094 .pvt = true, 4095 .multi_chip = true, 4096 .tag_protocol = DSA_TAG_PROTO_EDSA, 4097 .ops = &mv88e6175_ops, 4098 }, 4099 4100 [MV88E6176] = { 4101 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4102 .family = MV88E6XXX_FAMILY_6352, 4103 .name = "Marvell 88E6176", 4104 .num_databases = 4096, 4105 .num_ports = 7, 4106 .num_internal_phys = 5, 4107 .num_gpio = 15, 4108 .max_vid = 4095, 4109 .port_base_addr = 0x10, 4110 .phy_base_addr = 0x0, 4111 .global1_addr = 0x1b, 4112 .global2_addr = 0x1c, 4113 .age_time_coeff = 15000, 4114 .g1_irqs = 9, 4115 .g2_irqs = 10, 4116 .atu_move_port_mask = 0xf, 4117 .pvt = true, 4118 .multi_chip = true, 4119 .tag_protocol = DSA_TAG_PROTO_EDSA, 4120 .ops = &mv88e6176_ops, 4121 }, 4122 4123 [MV88E6185] = { 4124 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4125 .family = MV88E6XXX_FAMILY_6185, 4126 .name = "Marvell 88E6185", 4127 .num_databases = 256, 4128 .num_ports = 10, 4129 .num_internal_phys = 0, 4130 .max_vid = 4095, 4131 .port_base_addr = 0x10, 4132 .phy_base_addr = 0x0, 4133 .global1_addr = 0x1b, 4134 .global2_addr = 0x1c, 4135 .age_time_coeff = 15000, 4136 .g1_irqs = 8, 4137 .atu_move_port_mask = 0xf, 4138 .multi_chip = true, 4139 .tag_protocol = DSA_TAG_PROTO_EDSA, 4140 .ops = &mv88e6185_ops, 4141 }, 4142 4143 [MV88E6190] = { 4144 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4145 .family = MV88E6XXX_FAMILY_6390, 4146 .name = "Marvell 88E6190", 4147 .num_databases = 4096, 4148 .num_ports = 11, /* 10 + Z80 */ 4149 .num_internal_phys = 9, 4150 .num_gpio = 16, 4151 .max_vid = 8191, 4152 .port_base_addr = 0x0, 4153 .phy_base_addr = 0x0, 4154 .global1_addr = 0x1b, 4155 .global2_addr = 0x1c, 4156 .tag_protocol = DSA_TAG_PROTO_DSA, 4157 .age_time_coeff = 3750, 4158 .g1_irqs = 9, 4159 .g2_irqs = 14, 4160 .pvt = true, 4161 .multi_chip = true, 4162 .atu_move_port_mask = 0x1f, 4163 .ops = &mv88e6190_ops, 4164 }, 4165 4166 [MV88E6190X] = { 4167 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4168 .family = MV88E6XXX_FAMILY_6390, 4169 .name = "Marvell 88E6190X", 4170 .num_databases = 4096, 4171 .num_ports = 11, /* 10 + Z80 */ 4172 .num_internal_phys = 9, 4173 .num_gpio = 16, 4174 .max_vid = 8191, 4175 .port_base_addr = 0x0, 4176 .phy_base_addr = 0x0, 4177 .global1_addr = 0x1b, 4178 .global2_addr = 0x1c, 4179 .age_time_coeff = 3750, 4180 .g1_irqs = 9, 4181 .g2_irqs = 14, 4182 .atu_move_port_mask = 0x1f, 4183 .pvt = true, 4184 .multi_chip = true, 4185 .tag_protocol = DSA_TAG_PROTO_DSA, 4186 .ops = &mv88e6190x_ops, 4187 }, 4188 4189 [MV88E6191] = { 4190 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4191 .family = MV88E6XXX_FAMILY_6390, 4192 .name = "Marvell 88E6191", 4193 .num_databases = 4096, 4194 .num_ports = 11, /* 10 + Z80 */ 4195 .num_internal_phys = 9, 4196 .max_vid = 8191, 4197 .port_base_addr = 0x0, 4198 .phy_base_addr = 0x0, 4199 .global1_addr = 0x1b, 4200 .global2_addr = 0x1c, 4201 .age_time_coeff = 3750, 4202 .g1_irqs = 9, 4203 .g2_irqs = 14, 4204 .atu_move_port_mask = 0x1f, 4205 .pvt = true, 4206 .multi_chip = true, 4207 .tag_protocol = DSA_TAG_PROTO_DSA, 4208 .ptp_support = true, 4209 .ops = &mv88e6191_ops, 4210 }, 4211 4212 [MV88E6240] = { 4213 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4214 .family = MV88E6XXX_FAMILY_6352, 4215 .name = "Marvell 88E6240", 4216 .num_databases = 4096, 4217 .num_ports = 7, 4218 .num_internal_phys = 5, 4219 .num_gpio = 15, 4220 .max_vid = 4095, 4221 .port_base_addr = 0x10, 4222 .phy_base_addr = 0x0, 4223 .global1_addr = 0x1b, 4224 .global2_addr = 0x1c, 4225 .age_time_coeff = 15000, 4226 .g1_irqs = 9, 4227 .g2_irqs = 10, 4228 .atu_move_port_mask = 0xf, 4229 .pvt = true, 4230 .multi_chip = true, 4231 .tag_protocol = DSA_TAG_PROTO_EDSA, 4232 .ptp_support = true, 4233 .ops = &mv88e6240_ops, 4234 }, 4235 4236 [MV88E6290] = { 4237 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4238 .family = MV88E6XXX_FAMILY_6390, 4239 .name = "Marvell 88E6290", 4240 .num_databases = 4096, 4241 .num_ports = 11, /* 10 + Z80 */ 4242 .num_internal_phys = 9, 4243 .num_gpio = 16, 4244 .max_vid = 8191, 4245 .port_base_addr = 0x0, 4246 .phy_base_addr = 0x0, 4247 .global1_addr = 0x1b, 4248 .global2_addr = 0x1c, 4249 .age_time_coeff = 3750, 4250 .g1_irqs = 9, 4251 .g2_irqs = 14, 4252 .atu_move_port_mask = 0x1f, 4253 .pvt = true, 4254 .multi_chip = true, 4255 .tag_protocol = DSA_TAG_PROTO_DSA, 4256 .ptp_support = true, 4257 .ops = &mv88e6290_ops, 4258 }, 4259 4260 [MV88E6320] = { 4261 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4262 .family = MV88E6XXX_FAMILY_6320, 4263 .name = "Marvell 88E6320", 4264 .num_databases = 4096, 4265 .num_ports = 7, 4266 .num_internal_phys = 5, 4267 .num_gpio = 15, 4268 .max_vid = 4095, 4269 .port_base_addr = 0x10, 4270 .phy_base_addr = 0x0, 4271 .global1_addr = 0x1b, 4272 .global2_addr = 0x1c, 4273 .age_time_coeff = 15000, 4274 .g1_irqs = 8, 4275 .g2_irqs = 10, 4276 .atu_move_port_mask = 0xf, 4277 .pvt = true, 4278 .multi_chip = true, 4279 .tag_protocol = DSA_TAG_PROTO_EDSA, 4280 .ptp_support = true, 4281 .ops = &mv88e6320_ops, 4282 }, 4283 4284 [MV88E6321] = { 4285 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4286 .family = MV88E6XXX_FAMILY_6320, 4287 .name = "Marvell 88E6321", 4288 .num_databases = 4096, 4289 .num_ports = 7, 4290 .num_internal_phys = 5, 4291 .num_gpio = 15, 4292 .max_vid = 4095, 4293 .port_base_addr = 0x10, 4294 .phy_base_addr = 0x0, 4295 .global1_addr = 0x1b, 4296 .global2_addr = 0x1c, 4297 .age_time_coeff = 15000, 4298 .g1_irqs = 8, 4299 .g2_irqs = 10, 4300 .atu_move_port_mask = 0xf, 4301 .multi_chip = true, 4302 .tag_protocol = DSA_TAG_PROTO_EDSA, 4303 .ptp_support = true, 4304 .ops = &mv88e6321_ops, 4305 }, 4306 4307 [MV88E6341] = { 4308 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4309 .family = MV88E6XXX_FAMILY_6341, 4310 .name = "Marvell 88E6341", 4311 .num_databases = 4096, 4312 .num_internal_phys = 5, 4313 .num_ports = 6, 4314 .num_gpio = 11, 4315 .max_vid = 4095, 4316 .port_base_addr = 0x10, 4317 .phy_base_addr = 0x10, 4318 .global1_addr = 0x1b, 4319 .global2_addr = 0x1c, 4320 .age_time_coeff = 3750, 4321 .atu_move_port_mask = 0x1f, 4322 .g1_irqs = 9, 4323 .g2_irqs = 10, 4324 .pvt = true, 4325 .multi_chip = true, 4326 .tag_protocol = DSA_TAG_PROTO_EDSA, 4327 .ptp_support = true, 4328 .ops = &mv88e6341_ops, 4329 }, 4330 4331 [MV88E6350] = { 4332 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4333 .family = MV88E6XXX_FAMILY_6351, 4334 .name = "Marvell 88E6350", 4335 .num_databases = 4096, 4336 .num_ports = 7, 4337 .num_internal_phys = 5, 4338 .max_vid = 4095, 4339 .port_base_addr = 0x10, 4340 .phy_base_addr = 0x0, 4341 .global1_addr = 0x1b, 4342 .global2_addr = 0x1c, 4343 .age_time_coeff = 15000, 4344 .g1_irqs = 9, 4345 .g2_irqs = 10, 4346 .atu_move_port_mask = 0xf, 4347 .pvt = true, 4348 .multi_chip = true, 4349 .tag_protocol = DSA_TAG_PROTO_EDSA, 4350 .ops = &mv88e6350_ops, 4351 }, 4352 4353 [MV88E6351] = { 4354 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4355 .family = MV88E6XXX_FAMILY_6351, 4356 .name = "Marvell 88E6351", 4357 .num_databases = 4096, 4358 .num_ports = 7, 4359 .num_internal_phys = 5, 4360 .max_vid = 4095, 4361 .port_base_addr = 0x10, 4362 .phy_base_addr = 0x0, 4363 .global1_addr = 0x1b, 4364 .global2_addr = 0x1c, 4365 .age_time_coeff = 15000, 4366 .g1_irqs = 9, 4367 .g2_irqs = 10, 4368 .atu_move_port_mask = 0xf, 4369 .pvt = true, 4370 .multi_chip = true, 4371 .tag_protocol = DSA_TAG_PROTO_EDSA, 4372 .ops = &mv88e6351_ops, 4373 }, 4374 4375 [MV88E6352] = { 4376 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4377 .family = MV88E6XXX_FAMILY_6352, 4378 .name = "Marvell 88E6352", 4379 .num_databases = 4096, 4380 .num_ports = 7, 4381 .num_internal_phys = 5, 4382 .num_gpio = 15, 4383 .max_vid = 4095, 4384 .port_base_addr = 0x10, 4385 .phy_base_addr = 0x0, 4386 .global1_addr = 0x1b, 4387 .global2_addr = 0x1c, 4388 .age_time_coeff = 15000, 4389 .g1_irqs = 9, 4390 .g2_irqs = 10, 4391 .atu_move_port_mask = 0xf, 4392 .pvt = true, 4393 .multi_chip = true, 4394 .tag_protocol = DSA_TAG_PROTO_EDSA, 4395 .ptp_support = true, 4396 .ops = &mv88e6352_ops, 4397 }, 4398 [MV88E6390] = { 4399 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4400 .family = MV88E6XXX_FAMILY_6390, 4401 .name = "Marvell 88E6390", 4402 .num_databases = 4096, 4403 .num_ports = 11, /* 10 + Z80 */ 4404 .num_internal_phys = 9, 4405 .num_gpio = 16, 4406 .max_vid = 8191, 4407 .port_base_addr = 0x0, 4408 .phy_base_addr = 0x0, 4409 .global1_addr = 0x1b, 4410 .global2_addr = 0x1c, 4411 .age_time_coeff = 3750, 4412 .g1_irqs = 9, 4413 .g2_irqs = 14, 4414 .atu_move_port_mask = 0x1f, 4415 .pvt = true, 4416 .multi_chip = true, 4417 .tag_protocol = DSA_TAG_PROTO_DSA, 4418 .ptp_support = true, 4419 .ops = &mv88e6390_ops, 4420 }, 4421 [MV88E6390X] = { 4422 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4423 .family = MV88E6XXX_FAMILY_6390, 4424 .name = "Marvell 88E6390X", 4425 .num_databases = 4096, 4426 .num_ports = 11, /* 10 + Z80 */ 4427 .num_internal_phys = 9, 4428 .num_gpio = 16, 4429 .max_vid = 8191, 4430 .port_base_addr = 0x0, 4431 .phy_base_addr = 0x0, 4432 .global1_addr = 0x1b, 4433 .global2_addr = 0x1c, 4434 .age_time_coeff = 3750, 4435 .g1_irqs = 9, 4436 .g2_irqs = 14, 4437 .atu_move_port_mask = 0x1f, 4438 .pvt = true, 4439 .multi_chip = true, 4440 .tag_protocol = DSA_TAG_PROTO_DSA, 4441 .ptp_support = true, 4442 .ops = &mv88e6390x_ops, 4443 }, 4444 }; 4445 4446 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4447 { 4448 int i; 4449 4450 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4451 if (mv88e6xxx_table[i].prod_num == prod_num) 4452 return &mv88e6xxx_table[i]; 4453 4454 return NULL; 4455 } 4456 4457 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4458 { 4459 const struct mv88e6xxx_info *info; 4460 unsigned int prod_num, rev; 4461 u16 id; 4462 int err; 4463 4464 mutex_lock(&chip->reg_lock); 4465 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4466 mutex_unlock(&chip->reg_lock); 4467 if (err) 4468 return err; 4469 4470 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4471 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4472 4473 info = mv88e6xxx_lookup_info(prod_num); 4474 if (!info) 4475 return -ENODEV; 4476 4477 /* Update the compatible info with the probed one */ 4478 chip->info = info; 4479 4480 err = mv88e6xxx_g2_require(chip); 4481 if (err) 4482 return err; 4483 4484 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4485 chip->info->prod_num, chip->info->name, rev); 4486 4487 return 0; 4488 } 4489 4490 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4491 { 4492 struct mv88e6xxx_chip *chip; 4493 4494 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4495 if (!chip) 4496 return NULL; 4497 4498 chip->dev = dev; 4499 4500 mutex_init(&chip->reg_lock); 4501 INIT_LIST_HEAD(&chip->mdios); 4502 4503 return chip; 4504 } 4505 4506 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4507 int port) 4508 { 4509 struct mv88e6xxx_chip *chip = ds->priv; 4510 4511 return chip->info->tag_protocol; 4512 } 4513 4514 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4515 const struct switchdev_obj_port_mdb *mdb) 4516 { 4517 /* We don't need any dynamic resource from the kernel (yet), 4518 * so skip the prepare phase. 4519 */ 4520 4521 return 0; 4522 } 4523 4524 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4525 const struct switchdev_obj_port_mdb *mdb) 4526 { 4527 struct mv88e6xxx_chip *chip = ds->priv; 4528 4529 mutex_lock(&chip->reg_lock); 4530 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4531 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4532 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4533 port); 4534 mutex_unlock(&chip->reg_lock); 4535 } 4536 4537 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4538 const struct switchdev_obj_port_mdb *mdb) 4539 { 4540 struct mv88e6xxx_chip *chip = ds->priv; 4541 int err; 4542 4543 mutex_lock(&chip->reg_lock); 4544 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4545 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 4546 mutex_unlock(&chip->reg_lock); 4547 4548 return err; 4549 } 4550 4551 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 4552 bool unicast, bool multicast) 4553 { 4554 struct mv88e6xxx_chip *chip = ds->priv; 4555 int err = -EOPNOTSUPP; 4556 4557 mutex_lock(&chip->reg_lock); 4558 if (chip->info->ops->port_set_egress_floods) 4559 err = chip->info->ops->port_set_egress_floods(chip, port, 4560 unicast, 4561 multicast); 4562 mutex_unlock(&chip->reg_lock); 4563 4564 return err; 4565 } 4566 4567 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4568 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4569 .setup = mv88e6xxx_setup, 4570 .adjust_link = mv88e6xxx_adjust_link, 4571 .phylink_validate = mv88e6xxx_validate, 4572 .phylink_mac_link_state = mv88e6xxx_link_state, 4573 .phylink_mac_config = mv88e6xxx_mac_config, 4574 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4575 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4576 .get_strings = mv88e6xxx_get_strings, 4577 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4578 .get_sset_count = mv88e6xxx_get_sset_count, 4579 .port_enable = mv88e6xxx_port_enable, 4580 .port_disable = mv88e6xxx_port_disable, 4581 .get_mac_eee = mv88e6xxx_get_mac_eee, 4582 .set_mac_eee = mv88e6xxx_set_mac_eee, 4583 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4584 .get_eeprom = mv88e6xxx_get_eeprom, 4585 .set_eeprom = mv88e6xxx_set_eeprom, 4586 .get_regs_len = mv88e6xxx_get_regs_len, 4587 .get_regs = mv88e6xxx_get_regs, 4588 .set_ageing_time = mv88e6xxx_set_ageing_time, 4589 .port_bridge_join = mv88e6xxx_port_bridge_join, 4590 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4591 .port_egress_floods = mv88e6xxx_port_egress_floods, 4592 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4593 .port_fast_age = mv88e6xxx_port_fast_age, 4594 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4595 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4596 .port_vlan_add = mv88e6xxx_port_vlan_add, 4597 .port_vlan_del = mv88e6xxx_port_vlan_del, 4598 .port_fdb_add = mv88e6xxx_port_fdb_add, 4599 .port_fdb_del = mv88e6xxx_port_fdb_del, 4600 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4601 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4602 .port_mdb_add = mv88e6xxx_port_mdb_add, 4603 .port_mdb_del = mv88e6xxx_port_mdb_del, 4604 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4605 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4606 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4607 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4608 .port_txtstamp = mv88e6xxx_port_txtstamp, 4609 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4610 .get_ts_info = mv88e6xxx_get_ts_info, 4611 }; 4612 4613 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4614 { 4615 struct device *dev = chip->dev; 4616 struct dsa_switch *ds; 4617 4618 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4619 if (!ds) 4620 return -ENOMEM; 4621 4622 ds->priv = chip; 4623 ds->dev = dev; 4624 ds->ops = &mv88e6xxx_switch_ops; 4625 ds->ageing_time_min = chip->info->age_time_coeff; 4626 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4627 4628 dev_set_drvdata(dev, ds); 4629 4630 return dsa_register_switch(ds); 4631 } 4632 4633 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4634 { 4635 dsa_unregister_switch(chip->ds); 4636 } 4637 4638 static const void *pdata_device_get_match_data(struct device *dev) 4639 { 4640 const struct of_device_id *matches = dev->driver->of_match_table; 4641 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 4642 4643 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 4644 matches++) { 4645 if (!strcmp(pdata->compatible, matches->compatible)) 4646 return matches->data; 4647 } 4648 return NULL; 4649 } 4650 4651 /* There is no suspend to RAM support at DSA level yet, the switch configuration 4652 * would be lost after a power cycle so prevent it to be suspended. 4653 */ 4654 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 4655 { 4656 return -EOPNOTSUPP; 4657 } 4658 4659 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 4660 { 4661 return 0; 4662 } 4663 4664 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 4665 4666 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4667 { 4668 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 4669 const struct mv88e6xxx_info *compat_info = NULL; 4670 struct device *dev = &mdiodev->dev; 4671 struct device_node *np = dev->of_node; 4672 struct mv88e6xxx_chip *chip; 4673 int port; 4674 int err; 4675 4676 if (!np && !pdata) 4677 return -EINVAL; 4678 4679 if (np) 4680 compat_info = of_device_get_match_data(dev); 4681 4682 if (pdata) { 4683 compat_info = pdata_device_get_match_data(dev); 4684 4685 if (!pdata->netdev) 4686 return -EINVAL; 4687 4688 for (port = 0; port < DSA_MAX_PORTS; port++) { 4689 if (!(pdata->enabled_ports & (1 << port))) 4690 continue; 4691 if (strcmp(pdata->cd.port_names[port], "cpu")) 4692 continue; 4693 pdata->cd.netdev[port] = &pdata->netdev->dev; 4694 break; 4695 } 4696 } 4697 4698 if (!compat_info) 4699 return -EINVAL; 4700 4701 chip = mv88e6xxx_alloc_chip(dev); 4702 if (!chip) { 4703 err = -ENOMEM; 4704 goto out; 4705 } 4706 4707 chip->info = compat_info; 4708 4709 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4710 if (err) 4711 goto out; 4712 4713 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4714 if (IS_ERR(chip->reset)) { 4715 err = PTR_ERR(chip->reset); 4716 goto out; 4717 } 4718 4719 err = mv88e6xxx_detect(chip); 4720 if (err) 4721 goto out; 4722 4723 mv88e6xxx_phy_init(chip); 4724 4725 if (chip->info->ops->get_eeprom) { 4726 if (np) 4727 of_property_read_u32(np, "eeprom-length", 4728 &chip->eeprom_len); 4729 else 4730 chip->eeprom_len = pdata->eeprom_len; 4731 } 4732 4733 mutex_lock(&chip->reg_lock); 4734 err = mv88e6xxx_switch_reset(chip); 4735 mutex_unlock(&chip->reg_lock); 4736 if (err) 4737 goto out; 4738 4739 if (np) { 4740 chip->irq = of_irq_get(np, 0); 4741 if (chip->irq == -EPROBE_DEFER) { 4742 err = chip->irq; 4743 goto out; 4744 } 4745 } 4746 4747 if (pdata) 4748 chip->irq = pdata->irq; 4749 4750 /* Has to be performed before the MDIO bus is created, because 4751 * the PHYs will link their interrupts to these interrupt 4752 * controllers 4753 */ 4754 mutex_lock(&chip->reg_lock); 4755 if (chip->irq > 0) 4756 err = mv88e6xxx_g1_irq_setup(chip); 4757 else 4758 err = mv88e6xxx_irq_poll_setup(chip); 4759 mutex_unlock(&chip->reg_lock); 4760 4761 if (err) 4762 goto out; 4763 4764 if (chip->info->g2_irqs > 0) { 4765 err = mv88e6xxx_g2_irq_setup(chip); 4766 if (err) 4767 goto out_g1_irq; 4768 } 4769 4770 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 4771 if (err) 4772 goto out_g2_irq; 4773 4774 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 4775 if (err) 4776 goto out_g1_atu_prob_irq; 4777 4778 err = mv88e6xxx_mdios_register(chip, np); 4779 if (err) 4780 goto out_g1_vtu_prob_irq; 4781 4782 err = mv88e6xxx_register_switch(chip); 4783 if (err) 4784 goto out_mdio; 4785 4786 return 0; 4787 4788 out_mdio: 4789 mv88e6xxx_mdios_unregister(chip); 4790 out_g1_vtu_prob_irq: 4791 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4792 out_g1_atu_prob_irq: 4793 mv88e6xxx_g1_atu_prob_irq_free(chip); 4794 out_g2_irq: 4795 if (chip->info->g2_irqs > 0) 4796 mv88e6xxx_g2_irq_free(chip); 4797 out_g1_irq: 4798 if (chip->irq > 0) 4799 mv88e6xxx_g1_irq_free(chip); 4800 else 4801 mv88e6xxx_irq_poll_free(chip); 4802 out: 4803 if (pdata) 4804 dev_put(pdata->netdev); 4805 4806 return err; 4807 } 4808 4809 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4810 { 4811 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4812 struct mv88e6xxx_chip *chip = ds->priv; 4813 4814 if (chip->info->ptp_support) { 4815 mv88e6xxx_hwtstamp_free(chip); 4816 mv88e6xxx_ptp_free(chip); 4817 } 4818 4819 mv88e6xxx_phy_destroy(chip); 4820 mv88e6xxx_unregister_switch(chip); 4821 mv88e6xxx_mdios_unregister(chip); 4822 4823 mv88e6xxx_g1_vtu_prob_irq_free(chip); 4824 mv88e6xxx_g1_atu_prob_irq_free(chip); 4825 4826 if (chip->info->g2_irqs > 0) 4827 mv88e6xxx_g2_irq_free(chip); 4828 4829 if (chip->irq > 0) 4830 mv88e6xxx_g1_irq_free(chip); 4831 else 4832 mv88e6xxx_irq_poll_free(chip); 4833 } 4834 4835 static const struct of_device_id mv88e6xxx_of_match[] = { 4836 { 4837 .compatible = "marvell,mv88e6085", 4838 .data = &mv88e6xxx_table[MV88E6085], 4839 }, 4840 { 4841 .compatible = "marvell,mv88e6190", 4842 .data = &mv88e6xxx_table[MV88E6190], 4843 }, 4844 { /* sentinel */ }, 4845 }; 4846 4847 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4848 4849 static struct mdio_driver mv88e6xxx_driver = { 4850 .probe = mv88e6xxx_probe, 4851 .remove = mv88e6xxx_remove, 4852 .mdiodrv.driver = { 4853 .name = "mv88e6085", 4854 .of_match_table = mv88e6xxx_of_match, 4855 .pm = &mv88e6xxx_pm_ops, 4856 }, 4857 }; 4858 4859 mdio_module_driver(mv88e6xxx_driver); 4860 4861 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4862 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4863 MODULE_LICENSE("GPL"); 4864