1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/etherdevice.h> 16 #include <linux/ethtool.h> 17 #include <linux/if_bridge.h> 18 #include <linux/interrupt.h> 19 #include <linux/irq.h> 20 #include <linux/irqdomain.h> 21 #include <linux/jiffies.h> 22 #include <linux/list.h> 23 #include <linux/mdio.h> 24 #include <linux/module.h> 25 #include <linux/of_device.h> 26 #include <linux/of_irq.h> 27 #include <linux/of_mdio.h> 28 #include <linux/platform_data/mv88e6xxx.h> 29 #include <linux/netdevice.h> 30 #include <linux/gpio/consumer.h> 31 #include <linux/phylink.h> 32 #include <net/dsa.h> 33 34 #include "chip.h" 35 #include "global1.h" 36 #include "global2.h" 37 #include "hwtstamp.h" 38 #include "phy.h" 39 #include "port.h" 40 #include "ptp.h" 41 #include "serdes.h" 42 #include "smi.h" 43 44 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 45 { 46 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 47 dev_err(chip->dev, "Switch registers lock not held!\n"); 48 dump_stack(); 49 } 50 } 51 52 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 53 { 54 int err; 55 56 assert_reg_lock(chip); 57 58 err = mv88e6xxx_smi_read(chip, addr, reg, val); 59 if (err) 60 return err; 61 62 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 63 addr, reg, *val); 64 65 return 0; 66 } 67 68 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 69 { 70 int err; 71 72 assert_reg_lock(chip); 73 74 err = mv88e6xxx_smi_write(chip, addr, reg, val); 75 if (err) 76 return err; 77 78 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 79 addr, reg, val); 80 81 return 0; 82 } 83 84 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 85 u16 mask, u16 val) 86 { 87 u16 data; 88 int err; 89 int i; 90 91 /* There's no bus specific operation to wait for a mask */ 92 for (i = 0; i < 16; i++) { 93 err = mv88e6xxx_read(chip, addr, reg, &data); 94 if (err) 95 return err; 96 97 if ((data & mask) == val) 98 return 0; 99 100 usleep_range(1000, 2000); 101 } 102 103 dev_err(chip->dev, "Timeout while waiting for switch\n"); 104 return -ETIMEDOUT; 105 } 106 107 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 108 int bit, int val) 109 { 110 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 111 val ? BIT(bit) : 0x0000); 112 } 113 114 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 115 { 116 struct mv88e6xxx_mdio_bus *mdio_bus; 117 118 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 119 list); 120 if (!mdio_bus) 121 return NULL; 122 123 return mdio_bus->bus; 124 } 125 126 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 127 { 128 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 129 unsigned int n = d->hwirq; 130 131 chip->g1_irq.masked |= (1 << n); 132 } 133 134 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 135 { 136 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 137 unsigned int n = d->hwirq; 138 139 chip->g1_irq.masked &= ~(1 << n); 140 } 141 142 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 143 { 144 unsigned int nhandled = 0; 145 unsigned int sub_irq; 146 unsigned int n; 147 u16 reg; 148 u16 ctl1; 149 int err; 150 151 mv88e6xxx_reg_lock(chip); 152 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 153 mv88e6xxx_reg_unlock(chip); 154 155 if (err) 156 goto out; 157 158 do { 159 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 160 if (reg & (1 << n)) { 161 sub_irq = irq_find_mapping(chip->g1_irq.domain, 162 n); 163 handle_nested_irq(sub_irq); 164 ++nhandled; 165 } 166 } 167 168 mv88e6xxx_reg_lock(chip); 169 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 170 if (err) 171 goto unlock; 172 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 173 unlock: 174 mv88e6xxx_reg_unlock(chip); 175 if (err) 176 goto out; 177 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 178 } while (reg & ctl1); 179 180 out: 181 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 182 } 183 184 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 185 { 186 struct mv88e6xxx_chip *chip = dev_id; 187 188 return mv88e6xxx_g1_irq_thread_work(chip); 189 } 190 191 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 192 { 193 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 194 195 mv88e6xxx_reg_lock(chip); 196 } 197 198 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 199 { 200 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 201 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 202 u16 reg; 203 int err; 204 205 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 206 if (err) 207 goto out; 208 209 reg &= ~mask; 210 reg |= (~chip->g1_irq.masked & mask); 211 212 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 213 if (err) 214 goto out; 215 216 out: 217 mv88e6xxx_reg_unlock(chip); 218 } 219 220 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 221 .name = "mv88e6xxx-g1", 222 .irq_mask = mv88e6xxx_g1_irq_mask, 223 .irq_unmask = mv88e6xxx_g1_irq_unmask, 224 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 225 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 226 }; 227 228 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 229 unsigned int irq, 230 irq_hw_number_t hwirq) 231 { 232 struct mv88e6xxx_chip *chip = d->host_data; 233 234 irq_set_chip_data(irq, d->host_data); 235 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 236 irq_set_noprobe(irq); 237 238 return 0; 239 } 240 241 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 242 .map = mv88e6xxx_g1_irq_domain_map, 243 .xlate = irq_domain_xlate_twocell, 244 }; 245 246 /* To be called with reg_lock held */ 247 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 248 { 249 int irq, virq; 250 u16 mask; 251 252 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 253 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 254 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 255 256 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 257 virq = irq_find_mapping(chip->g1_irq.domain, irq); 258 irq_dispose_mapping(virq); 259 } 260 261 irq_domain_remove(chip->g1_irq.domain); 262 } 263 264 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 265 { 266 /* 267 * free_irq must be called without reg_lock taken because the irq 268 * handler takes this lock, too. 269 */ 270 free_irq(chip->irq, chip); 271 272 mv88e6xxx_reg_lock(chip); 273 mv88e6xxx_g1_irq_free_common(chip); 274 mv88e6xxx_reg_unlock(chip); 275 } 276 277 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 278 { 279 int err, irq, virq; 280 u16 reg, mask; 281 282 chip->g1_irq.nirqs = chip->info->g1_irqs; 283 chip->g1_irq.domain = irq_domain_add_simple( 284 NULL, chip->g1_irq.nirqs, 0, 285 &mv88e6xxx_g1_irq_domain_ops, chip); 286 if (!chip->g1_irq.domain) 287 return -ENOMEM; 288 289 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 290 irq_create_mapping(chip->g1_irq.domain, irq); 291 292 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 293 chip->g1_irq.masked = ~0; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 296 if (err) 297 goto out_mapping; 298 299 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 300 301 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 302 if (err) 303 goto out_disable; 304 305 /* Reading the interrupt status clears (most of) them */ 306 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 307 if (err) 308 goto out_disable; 309 310 return 0; 311 312 out_disable: 313 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 314 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 315 316 out_mapping: 317 for (irq = 0; irq < 16; irq++) { 318 virq = irq_find_mapping(chip->g1_irq.domain, irq); 319 irq_dispose_mapping(virq); 320 } 321 322 irq_domain_remove(chip->g1_irq.domain); 323 324 return err; 325 } 326 327 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 328 { 329 static struct lock_class_key lock_key; 330 static struct lock_class_key request_key; 331 int err; 332 333 err = mv88e6xxx_g1_irq_setup_common(chip); 334 if (err) 335 return err; 336 337 /* These lock classes tells lockdep that global 1 irqs are in 338 * a different category than their parent GPIO, so it won't 339 * report false recursion. 340 */ 341 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 342 343 mv88e6xxx_reg_unlock(chip); 344 err = request_threaded_irq(chip->irq, NULL, 345 mv88e6xxx_g1_irq_thread_fn, 346 IRQF_ONESHOT | IRQF_SHARED, 347 dev_name(chip->dev), chip); 348 mv88e6xxx_reg_lock(chip); 349 if (err) 350 mv88e6xxx_g1_irq_free_common(chip); 351 352 return err; 353 } 354 355 static void mv88e6xxx_irq_poll(struct kthread_work *work) 356 { 357 struct mv88e6xxx_chip *chip = container_of(work, 358 struct mv88e6xxx_chip, 359 irq_poll_work.work); 360 mv88e6xxx_g1_irq_thread_work(chip); 361 362 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 363 msecs_to_jiffies(100)); 364 } 365 366 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 367 { 368 int err; 369 370 err = mv88e6xxx_g1_irq_setup_common(chip); 371 if (err) 372 return err; 373 374 kthread_init_delayed_work(&chip->irq_poll_work, 375 mv88e6xxx_irq_poll); 376 377 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 378 if (IS_ERR(chip->kworker)) 379 return PTR_ERR(chip->kworker); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 384 return 0; 385 } 386 387 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 388 { 389 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 390 kthread_destroy_worker(chip->kworker); 391 392 mv88e6xxx_reg_lock(chip); 393 mv88e6xxx_g1_irq_free_common(chip); 394 mv88e6xxx_reg_unlock(chip); 395 } 396 397 int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, int link, 398 int speed, int duplex, int pause, 399 phy_interface_t mode) 400 { 401 struct phylink_link_state state; 402 int err; 403 404 if (!chip->info->ops->port_set_link) 405 return 0; 406 407 if (!chip->info->ops->port_link_state) 408 return 0; 409 410 err = chip->info->ops->port_link_state(chip, port, &state); 411 if (err) 412 return err; 413 414 /* Has anything actually changed? We don't expect the 415 * interface mode to change without one of the other 416 * parameters also changing 417 */ 418 if (state.link == link && 419 state.speed == speed && 420 state.duplex == duplex && 421 (state.interface == mode || 422 state.interface == PHY_INTERFACE_MODE_NA)) 423 return 0; 424 425 /* Port's MAC control must not be changed unless the link is down */ 426 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 427 if (err) 428 return err; 429 430 if (chip->info->ops->port_set_speed) { 431 err = chip->info->ops->port_set_speed(chip, port, speed); 432 if (err && err != -EOPNOTSUPP) 433 goto restore_link; 434 } 435 436 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 437 mode = chip->info->ops->port_max_speed_mode(port); 438 439 if (chip->info->ops->port_set_pause) { 440 err = chip->info->ops->port_set_pause(chip, port, pause); 441 if (err) 442 goto restore_link; 443 } 444 445 if (chip->info->ops->port_set_duplex) { 446 err = chip->info->ops->port_set_duplex(chip, port, duplex); 447 if (err && err != -EOPNOTSUPP) 448 goto restore_link; 449 } 450 451 if (chip->info->ops->port_set_rgmii_delay) { 452 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 453 if (err && err != -EOPNOTSUPP) 454 goto restore_link; 455 } 456 457 if (chip->info->ops->port_set_cmode) { 458 err = chip->info->ops->port_set_cmode(chip, port, mode); 459 if (err && err != -EOPNOTSUPP) 460 goto restore_link; 461 } 462 463 err = 0; 464 restore_link: 465 if (chip->info->ops->port_set_link(chip, port, link)) 466 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 467 468 return err; 469 } 470 471 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 472 { 473 struct mv88e6xxx_chip *chip = ds->priv; 474 475 return port < chip->info->num_internal_phys; 476 } 477 478 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 479 unsigned long *mask, 480 struct phylink_link_state *state) 481 { 482 if (!phy_interface_mode_is_8023z(state->interface)) { 483 /* 10M and 100M are only supported in non-802.3z mode */ 484 phylink_set(mask, 10baseT_Half); 485 phylink_set(mask, 10baseT_Full); 486 phylink_set(mask, 100baseT_Half); 487 phylink_set(mask, 100baseT_Full); 488 } 489 } 490 491 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 492 unsigned long *mask, 493 struct phylink_link_state *state) 494 { 495 /* FIXME: if the port is in 1000Base-X mode, then it only supports 496 * 1000M FD speeds. In this case, CMODE will indicate 5. 497 */ 498 phylink_set(mask, 1000baseT_Full); 499 phylink_set(mask, 1000baseX_Full); 500 501 mv88e6065_phylink_validate(chip, port, mask, state); 502 } 503 504 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 505 unsigned long *mask, 506 struct phylink_link_state *state) 507 { 508 if (port >= 5) 509 phylink_set(mask, 2500baseX_Full); 510 511 /* No ethtool bits for 200Mbps */ 512 phylink_set(mask, 1000baseT_Full); 513 phylink_set(mask, 1000baseX_Full); 514 515 mv88e6065_phylink_validate(chip, port, mask, state); 516 } 517 518 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 519 unsigned long *mask, 520 struct phylink_link_state *state) 521 { 522 /* No ethtool bits for 200Mbps */ 523 phylink_set(mask, 1000baseT_Full); 524 phylink_set(mask, 1000baseX_Full); 525 526 mv88e6065_phylink_validate(chip, port, mask, state); 527 } 528 529 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 530 unsigned long *mask, 531 struct phylink_link_state *state) 532 { 533 if (port >= 9) { 534 phylink_set(mask, 2500baseX_Full); 535 phylink_set(mask, 2500baseT_Full); 536 } 537 538 /* No ethtool bits for 200Mbps */ 539 phylink_set(mask, 1000baseT_Full); 540 phylink_set(mask, 1000baseX_Full); 541 542 mv88e6065_phylink_validate(chip, port, mask, state); 543 } 544 545 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 546 unsigned long *mask, 547 struct phylink_link_state *state) 548 { 549 if (port >= 9) { 550 phylink_set(mask, 10000baseT_Full); 551 phylink_set(mask, 10000baseKR_Full); 552 } 553 554 mv88e6390_phylink_validate(chip, port, mask, state); 555 } 556 557 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 558 unsigned long *supported, 559 struct phylink_link_state *state) 560 { 561 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 562 struct mv88e6xxx_chip *chip = ds->priv; 563 564 /* Allow all the expected bits */ 565 phylink_set(mask, Autoneg); 566 phylink_set(mask, Pause); 567 phylink_set_port_modes(mask); 568 569 if (chip->info->ops->phylink_validate) 570 chip->info->ops->phylink_validate(chip, port, mask, state); 571 572 bitmap_and(supported, supported, mask, __ETHTOOL_LINK_MODE_MASK_NBITS); 573 bitmap_and(state->advertising, state->advertising, mask, 574 __ETHTOOL_LINK_MODE_MASK_NBITS); 575 576 /* We can only operate at 2500BaseX or 1000BaseX. If requested 577 * to advertise both, only report advertising at 2500BaseX. 578 */ 579 phylink_helper_basex_speed(state); 580 } 581 582 static int mv88e6xxx_link_state(struct dsa_switch *ds, int port, 583 struct phylink_link_state *state) 584 { 585 struct mv88e6xxx_chip *chip = ds->priv; 586 int err; 587 588 mv88e6xxx_reg_lock(chip); 589 if (chip->info->ops->port_link_state) 590 err = chip->info->ops->port_link_state(chip, port, state); 591 else 592 err = -EOPNOTSUPP; 593 mv88e6xxx_reg_unlock(chip); 594 595 return err; 596 } 597 598 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 599 unsigned int mode, 600 const struct phylink_link_state *state) 601 { 602 struct mv88e6xxx_chip *chip = ds->priv; 603 int speed, duplex, link, pause, err; 604 605 if ((mode == MLO_AN_PHY) && mv88e6xxx_phy_is_internal(ds, port)) 606 return; 607 608 if (mode == MLO_AN_FIXED) { 609 link = LINK_FORCED_UP; 610 speed = state->speed; 611 duplex = state->duplex; 612 } else if (!mv88e6xxx_phy_is_internal(ds, port)) { 613 link = state->link; 614 speed = state->speed; 615 duplex = state->duplex; 616 } else { 617 speed = SPEED_UNFORCED; 618 duplex = DUPLEX_UNFORCED; 619 link = LINK_UNFORCED; 620 } 621 pause = !!phylink_test(state->advertising, Pause); 622 623 mv88e6xxx_reg_lock(chip); 624 err = mv88e6xxx_port_setup_mac(chip, port, link, speed, duplex, pause, 625 state->interface); 626 mv88e6xxx_reg_unlock(chip); 627 628 if (err && err != -EOPNOTSUPP) 629 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 630 } 631 632 static void mv88e6xxx_mac_link_force(struct dsa_switch *ds, int port, int link) 633 { 634 struct mv88e6xxx_chip *chip = ds->priv; 635 int err; 636 637 mv88e6xxx_reg_lock(chip); 638 err = chip->info->ops->port_set_link(chip, port, link); 639 mv88e6xxx_reg_unlock(chip); 640 641 if (err) 642 dev_err(chip->dev, "p%d: failed to force MAC link\n", port); 643 } 644 645 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 646 unsigned int mode, 647 phy_interface_t interface) 648 { 649 if (mode == MLO_AN_FIXED) 650 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_DOWN); 651 } 652 653 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 654 unsigned int mode, phy_interface_t interface, 655 struct phy_device *phydev) 656 { 657 if (mode == MLO_AN_FIXED) 658 mv88e6xxx_mac_link_force(ds, port, LINK_FORCED_UP); 659 } 660 661 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 662 { 663 if (!chip->info->ops->stats_snapshot) 664 return -EOPNOTSUPP; 665 666 return chip->info->ops->stats_snapshot(chip, port); 667 } 668 669 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 670 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 671 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 672 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 673 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 674 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 675 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 676 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 677 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 678 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 679 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 680 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 681 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 682 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 683 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 684 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 685 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 686 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 687 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 688 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 689 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 690 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 691 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 692 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 693 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 694 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 695 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 696 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 697 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 698 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 699 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 700 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 701 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 702 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 703 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 704 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 705 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 706 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 707 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 708 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 709 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 710 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 711 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 712 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 713 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 714 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 715 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 716 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 717 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 718 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 719 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 720 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 721 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 722 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 723 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 724 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 725 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 726 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 727 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 728 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 729 }; 730 731 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 732 struct mv88e6xxx_hw_stat *s, 733 int port, u16 bank1_select, 734 u16 histogram) 735 { 736 u32 low; 737 u32 high = 0; 738 u16 reg = 0; 739 int err; 740 u64 value; 741 742 switch (s->type) { 743 case STATS_TYPE_PORT: 744 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 745 if (err) 746 return U64_MAX; 747 748 low = reg; 749 if (s->size == 4) { 750 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 751 if (err) 752 return U64_MAX; 753 low |= ((u32)reg) << 16; 754 } 755 break; 756 case STATS_TYPE_BANK1: 757 reg = bank1_select; 758 /* fall through */ 759 case STATS_TYPE_BANK0: 760 reg |= s->reg | histogram; 761 mv88e6xxx_g1_stats_read(chip, reg, &low); 762 if (s->size == 8) 763 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 764 break; 765 default: 766 return U64_MAX; 767 } 768 value = (((u64)high) << 32) | low; 769 return value; 770 } 771 772 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 773 uint8_t *data, int types) 774 { 775 struct mv88e6xxx_hw_stat *stat; 776 int i, j; 777 778 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 779 stat = &mv88e6xxx_hw_stats[i]; 780 if (stat->type & types) { 781 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 782 ETH_GSTRING_LEN); 783 j++; 784 } 785 } 786 787 return j; 788 } 789 790 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 791 uint8_t *data) 792 { 793 return mv88e6xxx_stats_get_strings(chip, data, 794 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 795 } 796 797 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 798 uint8_t *data) 799 { 800 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 801 } 802 803 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 804 uint8_t *data) 805 { 806 return mv88e6xxx_stats_get_strings(chip, data, 807 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 808 } 809 810 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 811 "atu_member_violation", 812 "atu_miss_violation", 813 "atu_full_violation", 814 "vtu_member_violation", 815 "vtu_miss_violation", 816 }; 817 818 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 819 { 820 unsigned int i; 821 822 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 823 strlcpy(data + i * ETH_GSTRING_LEN, 824 mv88e6xxx_atu_vtu_stats_strings[i], 825 ETH_GSTRING_LEN); 826 } 827 828 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 829 u32 stringset, uint8_t *data) 830 { 831 struct mv88e6xxx_chip *chip = ds->priv; 832 int count = 0; 833 834 if (stringset != ETH_SS_STATS) 835 return; 836 837 mv88e6xxx_reg_lock(chip); 838 839 if (chip->info->ops->stats_get_strings) 840 count = chip->info->ops->stats_get_strings(chip, data); 841 842 if (chip->info->ops->serdes_get_strings) { 843 data += count * ETH_GSTRING_LEN; 844 count = chip->info->ops->serdes_get_strings(chip, port, data); 845 } 846 847 data += count * ETH_GSTRING_LEN; 848 mv88e6xxx_atu_vtu_get_strings(data); 849 850 mv88e6xxx_reg_unlock(chip); 851 } 852 853 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 854 int types) 855 { 856 struct mv88e6xxx_hw_stat *stat; 857 int i, j; 858 859 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 860 stat = &mv88e6xxx_hw_stats[i]; 861 if (stat->type & types) 862 j++; 863 } 864 return j; 865 } 866 867 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 868 { 869 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 870 STATS_TYPE_PORT); 871 } 872 873 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 874 { 875 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 876 } 877 878 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 879 { 880 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 881 STATS_TYPE_BANK1); 882 } 883 884 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 885 { 886 struct mv88e6xxx_chip *chip = ds->priv; 887 int serdes_count = 0; 888 int count = 0; 889 890 if (sset != ETH_SS_STATS) 891 return 0; 892 893 mv88e6xxx_reg_lock(chip); 894 if (chip->info->ops->stats_get_sset_count) 895 count = chip->info->ops->stats_get_sset_count(chip); 896 if (count < 0) 897 goto out; 898 899 if (chip->info->ops->serdes_get_sset_count) 900 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 901 port); 902 if (serdes_count < 0) { 903 count = serdes_count; 904 goto out; 905 } 906 count += serdes_count; 907 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 908 909 out: 910 mv88e6xxx_reg_unlock(chip); 911 912 return count; 913 } 914 915 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 916 uint64_t *data, int types, 917 u16 bank1_select, u16 histogram) 918 { 919 struct mv88e6xxx_hw_stat *stat; 920 int i, j; 921 922 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 923 stat = &mv88e6xxx_hw_stats[i]; 924 if (stat->type & types) { 925 mv88e6xxx_reg_lock(chip); 926 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 927 bank1_select, 928 histogram); 929 mv88e6xxx_reg_unlock(chip); 930 931 j++; 932 } 933 } 934 return j; 935 } 936 937 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 938 uint64_t *data) 939 { 940 return mv88e6xxx_stats_get_stats(chip, port, data, 941 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 942 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 943 } 944 945 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 946 uint64_t *data) 947 { 948 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 949 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 950 } 951 952 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 953 uint64_t *data) 954 { 955 return mv88e6xxx_stats_get_stats(chip, port, data, 956 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 957 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 958 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 959 } 960 961 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 962 uint64_t *data) 963 { 964 return mv88e6xxx_stats_get_stats(chip, port, data, 965 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 966 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 967 0); 968 } 969 970 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 971 uint64_t *data) 972 { 973 *data++ = chip->ports[port].atu_member_violation; 974 *data++ = chip->ports[port].atu_miss_violation; 975 *data++ = chip->ports[port].atu_full_violation; 976 *data++ = chip->ports[port].vtu_member_violation; 977 *data++ = chip->ports[port].vtu_miss_violation; 978 } 979 980 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 981 uint64_t *data) 982 { 983 int count = 0; 984 985 if (chip->info->ops->stats_get_stats) 986 count = chip->info->ops->stats_get_stats(chip, port, data); 987 988 mv88e6xxx_reg_lock(chip); 989 if (chip->info->ops->serdes_get_stats) { 990 data += count; 991 count = chip->info->ops->serdes_get_stats(chip, port, data); 992 } 993 data += count; 994 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 995 mv88e6xxx_reg_unlock(chip); 996 } 997 998 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 999 uint64_t *data) 1000 { 1001 struct mv88e6xxx_chip *chip = ds->priv; 1002 int ret; 1003 1004 mv88e6xxx_reg_lock(chip); 1005 1006 ret = mv88e6xxx_stats_snapshot(chip, port); 1007 mv88e6xxx_reg_unlock(chip); 1008 1009 if (ret < 0) 1010 return; 1011 1012 mv88e6xxx_get_stats(chip, port, data); 1013 1014 } 1015 1016 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1017 { 1018 return 32 * sizeof(u16); 1019 } 1020 1021 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1022 struct ethtool_regs *regs, void *_p) 1023 { 1024 struct mv88e6xxx_chip *chip = ds->priv; 1025 int err; 1026 u16 reg; 1027 u16 *p = _p; 1028 int i; 1029 1030 regs->version = chip->info->prod_num; 1031 1032 memset(p, 0xff, 32 * sizeof(u16)); 1033 1034 mv88e6xxx_reg_lock(chip); 1035 1036 for (i = 0; i < 32; i++) { 1037 1038 err = mv88e6xxx_port_read(chip, port, i, ®); 1039 if (!err) 1040 p[i] = reg; 1041 } 1042 1043 mv88e6xxx_reg_unlock(chip); 1044 } 1045 1046 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1047 struct ethtool_eee *e) 1048 { 1049 /* Nothing to do on the port's MAC */ 1050 return 0; 1051 } 1052 1053 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1054 struct ethtool_eee *e) 1055 { 1056 /* Nothing to do on the port's MAC */ 1057 return 0; 1058 } 1059 1060 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1061 { 1062 struct dsa_switch *ds = NULL; 1063 struct net_device *br; 1064 u16 pvlan; 1065 int i; 1066 1067 if (dev < DSA_MAX_SWITCHES) 1068 ds = chip->ds->dst->ds[dev]; 1069 1070 /* Prevent frames from unknown switch or port */ 1071 if (!ds || port >= ds->num_ports) 1072 return 0; 1073 1074 /* Frames from DSA links and CPU ports can egress any local port */ 1075 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1076 return mv88e6xxx_port_mask(chip); 1077 1078 br = ds->ports[port].bridge_dev; 1079 pvlan = 0; 1080 1081 /* Frames from user ports can egress any local DSA links and CPU ports, 1082 * as well as any local member of their bridge group. 1083 */ 1084 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1085 if (dsa_is_cpu_port(chip->ds, i) || 1086 dsa_is_dsa_port(chip->ds, i) || 1087 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 1088 pvlan |= BIT(i); 1089 1090 return pvlan; 1091 } 1092 1093 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1094 { 1095 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1096 1097 /* prevent frames from going back out of the port they came in on */ 1098 output_ports &= ~BIT(port); 1099 1100 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1101 } 1102 1103 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1104 u8 state) 1105 { 1106 struct mv88e6xxx_chip *chip = ds->priv; 1107 int err; 1108 1109 mv88e6xxx_reg_lock(chip); 1110 err = mv88e6xxx_port_set_state(chip, port, state); 1111 mv88e6xxx_reg_unlock(chip); 1112 1113 if (err) 1114 dev_err(ds->dev, "p%d: failed to update state\n", port); 1115 } 1116 1117 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1118 { 1119 int err; 1120 1121 if (chip->info->ops->ieee_pri_map) { 1122 err = chip->info->ops->ieee_pri_map(chip); 1123 if (err) 1124 return err; 1125 } 1126 1127 if (chip->info->ops->ip_pri_map) { 1128 err = chip->info->ops->ip_pri_map(chip); 1129 if (err) 1130 return err; 1131 } 1132 1133 return 0; 1134 } 1135 1136 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1137 { 1138 int target, port; 1139 int err; 1140 1141 if (!chip->info->global2_addr) 1142 return 0; 1143 1144 /* Initialize the routing port to the 32 possible target devices */ 1145 for (target = 0; target < 32; target++) { 1146 port = 0x1f; 1147 if (target < DSA_MAX_SWITCHES) 1148 if (chip->ds->rtable[target] != DSA_RTABLE_NONE) 1149 port = chip->ds->rtable[target]; 1150 1151 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1152 if (err) 1153 return err; 1154 } 1155 1156 if (chip->info->ops->set_cascade_port) { 1157 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1158 err = chip->info->ops->set_cascade_port(chip, port); 1159 if (err) 1160 return err; 1161 } 1162 1163 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1164 if (err) 1165 return err; 1166 1167 return 0; 1168 } 1169 1170 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1171 { 1172 /* Clear all trunk masks and mapping */ 1173 if (chip->info->global2_addr) 1174 return mv88e6xxx_g2_trunk_clear(chip); 1175 1176 return 0; 1177 } 1178 1179 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1180 { 1181 if (chip->info->ops->rmu_disable) 1182 return chip->info->ops->rmu_disable(chip); 1183 1184 return 0; 1185 } 1186 1187 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1188 { 1189 if (chip->info->ops->pot_clear) 1190 return chip->info->ops->pot_clear(chip); 1191 1192 return 0; 1193 } 1194 1195 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1196 { 1197 if (chip->info->ops->mgmt_rsvd2cpu) 1198 return chip->info->ops->mgmt_rsvd2cpu(chip); 1199 1200 return 0; 1201 } 1202 1203 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1204 { 1205 int err; 1206 1207 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1208 if (err) 1209 return err; 1210 1211 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1212 if (err) 1213 return err; 1214 1215 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1216 } 1217 1218 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1219 { 1220 int port; 1221 int err; 1222 1223 if (!chip->info->ops->irl_init_all) 1224 return 0; 1225 1226 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1227 /* Disable ingress rate limiting by resetting all per port 1228 * ingress rate limit resources to their initial state. 1229 */ 1230 err = chip->info->ops->irl_init_all(chip, port); 1231 if (err) 1232 return err; 1233 } 1234 1235 return 0; 1236 } 1237 1238 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1239 { 1240 if (chip->info->ops->set_switch_mac) { 1241 u8 addr[ETH_ALEN]; 1242 1243 eth_random_addr(addr); 1244 1245 return chip->info->ops->set_switch_mac(chip, addr); 1246 } 1247 1248 return 0; 1249 } 1250 1251 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1252 { 1253 u16 pvlan = 0; 1254 1255 if (!mv88e6xxx_has_pvt(chip)) 1256 return -EOPNOTSUPP; 1257 1258 /* Skip the local source device, which uses in-chip port VLAN */ 1259 if (dev != chip->ds->index) 1260 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1261 1262 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1263 } 1264 1265 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1266 { 1267 int dev, port; 1268 int err; 1269 1270 if (!mv88e6xxx_has_pvt(chip)) 1271 return 0; 1272 1273 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1274 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1275 */ 1276 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1277 if (err) 1278 return err; 1279 1280 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1281 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1282 err = mv88e6xxx_pvt_map(chip, dev, port); 1283 if (err) 1284 return err; 1285 } 1286 } 1287 1288 return 0; 1289 } 1290 1291 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1292 { 1293 struct mv88e6xxx_chip *chip = ds->priv; 1294 int err; 1295 1296 mv88e6xxx_reg_lock(chip); 1297 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1298 mv88e6xxx_reg_unlock(chip); 1299 1300 if (err) 1301 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1302 } 1303 1304 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1305 { 1306 if (!chip->info->max_vid) 1307 return 0; 1308 1309 return mv88e6xxx_g1_vtu_flush(chip); 1310 } 1311 1312 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1313 struct mv88e6xxx_vtu_entry *entry) 1314 { 1315 if (!chip->info->ops->vtu_getnext) 1316 return -EOPNOTSUPP; 1317 1318 return chip->info->ops->vtu_getnext(chip, entry); 1319 } 1320 1321 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1322 struct mv88e6xxx_vtu_entry *entry) 1323 { 1324 if (!chip->info->ops->vtu_loadpurge) 1325 return -EOPNOTSUPP; 1326 1327 return chip->info->ops->vtu_loadpurge(chip, entry); 1328 } 1329 1330 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1331 { 1332 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1333 struct mv88e6xxx_vtu_entry vlan; 1334 int i, err; 1335 1336 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1337 1338 /* Set every FID bit used by the (un)bridged ports */ 1339 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1340 err = mv88e6xxx_port_get_fid(chip, i, fid); 1341 if (err) 1342 return err; 1343 1344 set_bit(*fid, fid_bitmap); 1345 } 1346 1347 /* Set every FID bit used by the VLAN entries */ 1348 vlan.vid = chip->info->max_vid; 1349 vlan.valid = false; 1350 1351 do { 1352 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1353 if (err) 1354 return err; 1355 1356 if (!vlan.valid) 1357 break; 1358 1359 set_bit(vlan.fid, fid_bitmap); 1360 } while (vlan.vid < chip->info->max_vid); 1361 1362 /* The reset value 0x000 is used to indicate that multiple address 1363 * databases are not needed. Return the next positive available. 1364 */ 1365 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1366 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1367 return -ENOSPC; 1368 1369 /* Clear the database */ 1370 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1371 } 1372 1373 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1374 u16 vid_begin, u16 vid_end) 1375 { 1376 struct mv88e6xxx_chip *chip = ds->priv; 1377 struct mv88e6xxx_vtu_entry vlan; 1378 int i, err; 1379 1380 /* DSA and CPU ports have to be members of multiple vlans */ 1381 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1382 return 0; 1383 1384 if (!vid_begin) 1385 return -EOPNOTSUPP; 1386 1387 vlan.vid = vid_begin - 1; 1388 vlan.valid = false; 1389 1390 do { 1391 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1392 if (err) 1393 return err; 1394 1395 if (!vlan.valid) 1396 break; 1397 1398 if (vlan.vid > vid_end) 1399 break; 1400 1401 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1402 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1403 continue; 1404 1405 if (!ds->ports[i].slave) 1406 continue; 1407 1408 if (vlan.member[i] == 1409 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1410 continue; 1411 1412 if (dsa_to_port(ds, i)->bridge_dev == 1413 ds->ports[port].bridge_dev) 1414 break; /* same bridge, check next VLAN */ 1415 1416 if (!dsa_to_port(ds, i)->bridge_dev) 1417 continue; 1418 1419 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1420 port, vlan.vid, i, 1421 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1422 return -EOPNOTSUPP; 1423 } 1424 } while (vlan.vid < vid_end); 1425 1426 return 0; 1427 } 1428 1429 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1430 bool vlan_filtering) 1431 { 1432 struct mv88e6xxx_chip *chip = ds->priv; 1433 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1434 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1435 int err; 1436 1437 if (!chip->info->max_vid) 1438 return -EOPNOTSUPP; 1439 1440 mv88e6xxx_reg_lock(chip); 1441 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1442 mv88e6xxx_reg_unlock(chip); 1443 1444 return err; 1445 } 1446 1447 static int 1448 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1449 const struct switchdev_obj_port_vlan *vlan) 1450 { 1451 struct mv88e6xxx_chip *chip = ds->priv; 1452 int err; 1453 1454 if (!chip->info->max_vid) 1455 return -EOPNOTSUPP; 1456 1457 /* If the requested port doesn't belong to the same bridge as the VLAN 1458 * members, do not support it (yet) and fallback to software VLAN. 1459 */ 1460 mv88e6xxx_reg_lock(chip); 1461 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1462 vlan->vid_end); 1463 mv88e6xxx_reg_unlock(chip); 1464 1465 /* We don't need any dynamic resource from the kernel (yet), 1466 * so skip the prepare phase. 1467 */ 1468 return err; 1469 } 1470 1471 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1472 const unsigned char *addr, u16 vid, 1473 u8 state) 1474 { 1475 struct mv88e6xxx_atu_entry entry; 1476 struct mv88e6xxx_vtu_entry vlan; 1477 u16 fid; 1478 int err; 1479 1480 /* Null VLAN ID corresponds to the port private database */ 1481 if (vid == 0) { 1482 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1483 if (err) 1484 return err; 1485 } else { 1486 vlan.vid = vid - 1; 1487 vlan.valid = false; 1488 1489 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1490 if (err) 1491 return err; 1492 1493 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1494 if (vlan.vid != vid || !vlan.valid) 1495 return -EOPNOTSUPP; 1496 1497 fid = vlan.fid; 1498 } 1499 1500 entry.state = 0; 1501 ether_addr_copy(entry.mac, addr); 1502 eth_addr_dec(entry.mac); 1503 1504 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1505 if (err) 1506 return err; 1507 1508 /* Initialize a fresh ATU entry if it isn't found */ 1509 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1510 memset(&entry, 0, sizeof(entry)); 1511 ether_addr_copy(entry.mac, addr); 1512 } 1513 1514 /* Purge the ATU entry only if no port is using it anymore */ 1515 if (!state) { 1516 entry.portvec &= ~BIT(port); 1517 if (!entry.portvec) 1518 entry.state = 0; 1519 } else { 1520 entry.portvec |= BIT(port); 1521 entry.state = state; 1522 } 1523 1524 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1525 } 1526 1527 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1528 const struct mv88e6xxx_policy *policy) 1529 { 1530 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1531 enum mv88e6xxx_policy_action action = policy->action; 1532 const u8 *addr = policy->addr; 1533 u16 vid = policy->vid; 1534 u8 state; 1535 int err; 1536 int id; 1537 1538 if (!chip->info->ops->port_set_policy) 1539 return -EOPNOTSUPP; 1540 1541 switch (mapping) { 1542 case MV88E6XXX_POLICY_MAPPING_DA: 1543 case MV88E6XXX_POLICY_MAPPING_SA: 1544 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1545 state = 0; /* Dissociate the port and address */ 1546 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1547 is_multicast_ether_addr(addr)) 1548 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1549 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1550 is_unicast_ether_addr(addr)) 1551 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1552 else 1553 return -EOPNOTSUPP; 1554 1555 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1556 state); 1557 if (err) 1558 return err; 1559 break; 1560 default: 1561 return -EOPNOTSUPP; 1562 } 1563 1564 /* Skip the port's policy clearing if the mapping is still in use */ 1565 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1566 idr_for_each_entry(&chip->policies, policy, id) 1567 if (policy->port == port && 1568 policy->mapping == mapping && 1569 policy->action != action) 1570 return 0; 1571 1572 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1573 } 1574 1575 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1576 struct ethtool_rx_flow_spec *fs) 1577 { 1578 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1579 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1580 enum mv88e6xxx_policy_mapping mapping; 1581 enum mv88e6xxx_policy_action action; 1582 struct mv88e6xxx_policy *policy; 1583 u16 vid = 0; 1584 u8 *addr; 1585 int err; 1586 int id; 1587 1588 if (fs->location != RX_CLS_LOC_ANY) 1589 return -EINVAL; 1590 1591 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1592 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1593 else 1594 return -EOPNOTSUPP; 1595 1596 switch (fs->flow_type & ~FLOW_EXT) { 1597 case ETHER_FLOW: 1598 if (!is_zero_ether_addr(mac_mask->h_dest) && 1599 is_zero_ether_addr(mac_mask->h_source)) { 1600 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1601 addr = mac_entry->h_dest; 1602 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1603 !is_zero_ether_addr(mac_mask->h_source)) { 1604 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1605 addr = mac_entry->h_source; 1606 } else { 1607 /* Cannot support DA and SA mapping in the same rule */ 1608 return -EOPNOTSUPP; 1609 } 1610 break; 1611 default: 1612 return -EOPNOTSUPP; 1613 } 1614 1615 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1616 if (fs->m_ext.vlan_tci != 0xffff) 1617 return -EOPNOTSUPP; 1618 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1619 } 1620 1621 idr_for_each_entry(&chip->policies, policy, id) { 1622 if (policy->port == port && policy->mapping == mapping && 1623 policy->action == action && policy->vid == vid && 1624 ether_addr_equal(policy->addr, addr)) 1625 return -EEXIST; 1626 } 1627 1628 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1629 if (!policy) 1630 return -ENOMEM; 1631 1632 fs->location = 0; 1633 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1634 GFP_KERNEL); 1635 if (err) { 1636 devm_kfree(chip->dev, policy); 1637 return err; 1638 } 1639 1640 memcpy(&policy->fs, fs, sizeof(*fs)); 1641 ether_addr_copy(policy->addr, addr); 1642 policy->mapping = mapping; 1643 policy->action = action; 1644 policy->port = port; 1645 policy->vid = vid; 1646 1647 err = mv88e6xxx_policy_apply(chip, port, policy); 1648 if (err) { 1649 idr_remove(&chip->policies, fs->location); 1650 devm_kfree(chip->dev, policy); 1651 return err; 1652 } 1653 1654 return 0; 1655 } 1656 1657 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1658 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1659 { 1660 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1661 struct mv88e6xxx_chip *chip = ds->priv; 1662 struct mv88e6xxx_policy *policy; 1663 int err; 1664 int id; 1665 1666 mv88e6xxx_reg_lock(chip); 1667 1668 switch (rxnfc->cmd) { 1669 case ETHTOOL_GRXCLSRLCNT: 1670 rxnfc->data = 0; 1671 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1672 rxnfc->rule_cnt = 0; 1673 idr_for_each_entry(&chip->policies, policy, id) 1674 if (policy->port == port) 1675 rxnfc->rule_cnt++; 1676 err = 0; 1677 break; 1678 case ETHTOOL_GRXCLSRULE: 1679 err = -ENOENT; 1680 policy = idr_find(&chip->policies, fs->location); 1681 if (policy) { 1682 memcpy(fs, &policy->fs, sizeof(*fs)); 1683 err = 0; 1684 } 1685 break; 1686 case ETHTOOL_GRXCLSRLALL: 1687 rxnfc->data = 0; 1688 rxnfc->rule_cnt = 0; 1689 idr_for_each_entry(&chip->policies, policy, id) 1690 if (policy->port == port) 1691 rule_locs[rxnfc->rule_cnt++] = id; 1692 err = 0; 1693 break; 1694 default: 1695 err = -EOPNOTSUPP; 1696 break; 1697 } 1698 1699 mv88e6xxx_reg_unlock(chip); 1700 1701 return err; 1702 } 1703 1704 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 1705 struct ethtool_rxnfc *rxnfc) 1706 { 1707 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1708 struct mv88e6xxx_chip *chip = ds->priv; 1709 struct mv88e6xxx_policy *policy; 1710 int err; 1711 1712 mv88e6xxx_reg_lock(chip); 1713 1714 switch (rxnfc->cmd) { 1715 case ETHTOOL_SRXCLSRLINS: 1716 err = mv88e6xxx_policy_insert(chip, port, fs); 1717 break; 1718 case ETHTOOL_SRXCLSRLDEL: 1719 err = -ENOENT; 1720 policy = idr_remove(&chip->policies, fs->location); 1721 if (policy) { 1722 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 1723 err = mv88e6xxx_policy_apply(chip, port, policy); 1724 devm_kfree(chip->dev, policy); 1725 } 1726 break; 1727 default: 1728 err = -EOPNOTSUPP; 1729 break; 1730 } 1731 1732 mv88e6xxx_reg_unlock(chip); 1733 1734 return err; 1735 } 1736 1737 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 1738 u16 vid) 1739 { 1740 const char broadcast[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; 1741 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 1742 1743 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 1744 } 1745 1746 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 1747 { 1748 int port; 1749 int err; 1750 1751 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1752 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 1753 if (err) 1754 return err; 1755 } 1756 1757 return 0; 1758 } 1759 1760 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 1761 u16 vid, u8 member) 1762 { 1763 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1764 struct mv88e6xxx_vtu_entry vlan; 1765 int i, err; 1766 1767 if (!vid) 1768 return -EOPNOTSUPP; 1769 1770 vlan.vid = vid - 1; 1771 vlan.valid = false; 1772 1773 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1774 if (err) 1775 return err; 1776 1777 if (vlan.vid != vid || !vlan.valid) { 1778 memset(&vlan, 0, sizeof(vlan)); 1779 1780 err = mv88e6xxx_atu_new(chip, &vlan.fid); 1781 if (err) 1782 return err; 1783 1784 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1785 if (i == port) 1786 vlan.member[i] = member; 1787 else 1788 vlan.member[i] = non_member; 1789 1790 vlan.vid = vid; 1791 vlan.valid = true; 1792 1793 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1794 if (err) 1795 return err; 1796 1797 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 1798 if (err) 1799 return err; 1800 } else if (vlan.member[port] != member) { 1801 vlan.member[port] = member; 1802 1803 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1804 if (err) 1805 return err; 1806 } else { 1807 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 1808 port, vid); 1809 } 1810 1811 return 0; 1812 } 1813 1814 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1815 const struct switchdev_obj_port_vlan *vlan) 1816 { 1817 struct mv88e6xxx_chip *chip = ds->priv; 1818 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1819 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1820 u8 member; 1821 u16 vid; 1822 1823 if (!chip->info->max_vid) 1824 return; 1825 1826 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1827 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1828 else if (untagged) 1829 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1830 else 1831 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1832 1833 mv88e6xxx_reg_lock(chip); 1834 1835 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1836 if (mv88e6xxx_port_vlan_join(chip, port, vid, member)) 1837 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1838 vid, untagged ? 'u' : 't'); 1839 1840 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1841 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1842 vlan->vid_end); 1843 1844 mv88e6xxx_reg_unlock(chip); 1845 } 1846 1847 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 1848 int port, u16 vid) 1849 { 1850 struct mv88e6xxx_vtu_entry vlan; 1851 int i, err; 1852 1853 if (!vid) 1854 return -EOPNOTSUPP; 1855 1856 vlan.vid = vid - 1; 1857 vlan.valid = false; 1858 1859 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1860 if (err) 1861 return err; 1862 1863 /* If the VLAN doesn't exist in hardware or the port isn't a member, 1864 * tell switchdev that this VLAN is likely handled in software. 1865 */ 1866 if (vlan.vid != vid || !vlan.valid || 1867 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1868 return -EOPNOTSUPP; 1869 1870 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1871 1872 /* keep the VLAN unless all ports are excluded */ 1873 vlan.valid = false; 1874 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1875 if (vlan.member[i] != 1876 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1877 vlan.valid = true; 1878 break; 1879 } 1880 } 1881 1882 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1883 if (err) 1884 return err; 1885 1886 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1887 } 1888 1889 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1890 const struct switchdev_obj_port_vlan *vlan) 1891 { 1892 struct mv88e6xxx_chip *chip = ds->priv; 1893 u16 pvid, vid; 1894 int err = 0; 1895 1896 if (!chip->info->max_vid) 1897 return -EOPNOTSUPP; 1898 1899 mv88e6xxx_reg_lock(chip); 1900 1901 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1902 if (err) 1903 goto unlock; 1904 1905 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1906 err = mv88e6xxx_port_vlan_leave(chip, port, vid); 1907 if (err) 1908 goto unlock; 1909 1910 if (vid == pvid) { 1911 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1912 if (err) 1913 goto unlock; 1914 } 1915 } 1916 1917 unlock: 1918 mv88e6xxx_reg_unlock(chip); 1919 1920 return err; 1921 } 1922 1923 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1924 const unsigned char *addr, u16 vid) 1925 { 1926 struct mv88e6xxx_chip *chip = ds->priv; 1927 int err; 1928 1929 mv88e6xxx_reg_lock(chip); 1930 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1931 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1932 mv88e6xxx_reg_unlock(chip); 1933 1934 return err; 1935 } 1936 1937 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1938 const unsigned char *addr, u16 vid) 1939 { 1940 struct mv88e6xxx_chip *chip = ds->priv; 1941 int err; 1942 1943 mv88e6xxx_reg_lock(chip); 1944 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 1945 mv88e6xxx_reg_unlock(chip); 1946 1947 return err; 1948 } 1949 1950 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1951 u16 fid, u16 vid, int port, 1952 dsa_fdb_dump_cb_t *cb, void *data) 1953 { 1954 struct mv88e6xxx_atu_entry addr; 1955 bool is_static; 1956 int err; 1957 1958 addr.state = 0; 1959 eth_broadcast_addr(addr.mac); 1960 1961 do { 1962 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1963 if (err) 1964 return err; 1965 1966 if (!addr.state) 1967 break; 1968 1969 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1970 continue; 1971 1972 if (!is_unicast_ether_addr(addr.mac)) 1973 continue; 1974 1975 is_static = (addr.state == 1976 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1977 err = cb(addr.mac, vid, is_static, data); 1978 if (err) 1979 return err; 1980 } while (!is_broadcast_ether_addr(addr.mac)); 1981 1982 return err; 1983 } 1984 1985 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1986 dsa_fdb_dump_cb_t *cb, void *data) 1987 { 1988 struct mv88e6xxx_vtu_entry vlan; 1989 u16 fid; 1990 int err; 1991 1992 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1993 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1994 if (err) 1995 return err; 1996 1997 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1998 if (err) 1999 return err; 2000 2001 /* Dump VLANs' Filtering Information Databases */ 2002 vlan.vid = chip->info->max_vid; 2003 vlan.valid = false; 2004 2005 do { 2006 err = mv88e6xxx_vtu_getnext(chip, &vlan); 2007 if (err) 2008 return err; 2009 2010 if (!vlan.valid) 2011 break; 2012 2013 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2014 cb, data); 2015 if (err) 2016 return err; 2017 } while (vlan.vid < chip->info->max_vid); 2018 2019 return err; 2020 } 2021 2022 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2023 dsa_fdb_dump_cb_t *cb, void *data) 2024 { 2025 struct mv88e6xxx_chip *chip = ds->priv; 2026 int err; 2027 2028 mv88e6xxx_reg_lock(chip); 2029 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2030 mv88e6xxx_reg_unlock(chip); 2031 2032 return err; 2033 } 2034 2035 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2036 struct net_device *br) 2037 { 2038 struct dsa_switch *ds; 2039 int port; 2040 int dev; 2041 int err; 2042 2043 /* Remap the Port VLAN of each local bridge group member */ 2044 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 2045 if (chip->ds->ports[port].bridge_dev == br) { 2046 err = mv88e6xxx_port_vlan_map(chip, port); 2047 if (err) 2048 return err; 2049 } 2050 } 2051 2052 if (!mv88e6xxx_has_pvt(chip)) 2053 return 0; 2054 2055 /* Remap the Port VLAN of each cross-chip bridge group member */ 2056 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 2057 ds = chip->ds->dst->ds[dev]; 2058 if (!ds) 2059 break; 2060 2061 for (port = 0; port < ds->num_ports; ++port) { 2062 if (ds->ports[port].bridge_dev == br) { 2063 err = mv88e6xxx_pvt_map(chip, dev, port); 2064 if (err) 2065 return err; 2066 } 2067 } 2068 } 2069 2070 return 0; 2071 } 2072 2073 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2074 struct net_device *br) 2075 { 2076 struct mv88e6xxx_chip *chip = ds->priv; 2077 int err; 2078 2079 mv88e6xxx_reg_lock(chip); 2080 err = mv88e6xxx_bridge_map(chip, br); 2081 mv88e6xxx_reg_unlock(chip); 2082 2083 return err; 2084 } 2085 2086 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2087 struct net_device *br) 2088 { 2089 struct mv88e6xxx_chip *chip = ds->priv; 2090 2091 mv88e6xxx_reg_lock(chip); 2092 if (mv88e6xxx_bridge_map(chip, br) || 2093 mv88e6xxx_port_vlan_map(chip, port)) 2094 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2095 mv88e6xxx_reg_unlock(chip); 2096 } 2097 2098 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 2099 int port, struct net_device *br) 2100 { 2101 struct mv88e6xxx_chip *chip = ds->priv; 2102 int err; 2103 2104 if (!mv88e6xxx_has_pvt(chip)) 2105 return 0; 2106 2107 mv88e6xxx_reg_lock(chip); 2108 err = mv88e6xxx_pvt_map(chip, dev, port); 2109 mv88e6xxx_reg_unlock(chip); 2110 2111 return err; 2112 } 2113 2114 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 2115 int port, struct net_device *br) 2116 { 2117 struct mv88e6xxx_chip *chip = ds->priv; 2118 2119 if (!mv88e6xxx_has_pvt(chip)) 2120 return; 2121 2122 mv88e6xxx_reg_lock(chip); 2123 if (mv88e6xxx_pvt_map(chip, dev, port)) 2124 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2125 mv88e6xxx_reg_unlock(chip); 2126 } 2127 2128 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2129 { 2130 if (chip->info->ops->reset) 2131 return chip->info->ops->reset(chip); 2132 2133 return 0; 2134 } 2135 2136 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2137 { 2138 struct gpio_desc *gpiod = chip->reset; 2139 2140 /* If there is a GPIO connected to the reset pin, toggle it */ 2141 if (gpiod) { 2142 gpiod_set_value_cansleep(gpiod, 1); 2143 usleep_range(10000, 20000); 2144 gpiod_set_value_cansleep(gpiod, 0); 2145 usleep_range(10000, 20000); 2146 } 2147 } 2148 2149 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2150 { 2151 int i, err; 2152 2153 /* Set all ports to the Disabled state */ 2154 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2155 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2156 if (err) 2157 return err; 2158 } 2159 2160 /* Wait for transmit queues to drain, 2161 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2162 */ 2163 usleep_range(2000, 4000); 2164 2165 return 0; 2166 } 2167 2168 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2169 { 2170 int err; 2171 2172 err = mv88e6xxx_disable_ports(chip); 2173 if (err) 2174 return err; 2175 2176 mv88e6xxx_hardware_reset(chip); 2177 2178 return mv88e6xxx_software_reset(chip); 2179 } 2180 2181 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2182 enum mv88e6xxx_frame_mode frame, 2183 enum mv88e6xxx_egress_mode egress, u16 etype) 2184 { 2185 int err; 2186 2187 if (!chip->info->ops->port_set_frame_mode) 2188 return -EOPNOTSUPP; 2189 2190 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2191 if (err) 2192 return err; 2193 2194 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2195 if (err) 2196 return err; 2197 2198 if (chip->info->ops->port_set_ether_type) 2199 return chip->info->ops->port_set_ether_type(chip, port, etype); 2200 2201 return 0; 2202 } 2203 2204 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2205 { 2206 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2207 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2208 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2209 } 2210 2211 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2212 { 2213 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2214 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2215 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2216 } 2217 2218 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2219 { 2220 return mv88e6xxx_set_port_mode(chip, port, 2221 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2222 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2223 ETH_P_EDSA); 2224 } 2225 2226 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2227 { 2228 if (dsa_is_dsa_port(chip->ds, port)) 2229 return mv88e6xxx_set_port_mode_dsa(chip, port); 2230 2231 if (dsa_is_user_port(chip->ds, port)) 2232 return mv88e6xxx_set_port_mode_normal(chip, port); 2233 2234 /* Setup CPU port mode depending on its supported tag format */ 2235 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 2236 return mv88e6xxx_set_port_mode_dsa(chip, port); 2237 2238 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 2239 return mv88e6xxx_set_port_mode_edsa(chip, port); 2240 2241 return -EINVAL; 2242 } 2243 2244 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2245 { 2246 bool message = dsa_is_dsa_port(chip->ds, port); 2247 2248 return mv88e6xxx_port_set_message_port(chip, port, message); 2249 } 2250 2251 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2252 { 2253 struct dsa_switch *ds = chip->ds; 2254 bool flood; 2255 2256 /* Upstream ports flood frames with unknown unicast or multicast DA */ 2257 flood = dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port); 2258 if (chip->info->ops->port_set_egress_floods) 2259 return chip->info->ops->port_set_egress_floods(chip, port, 2260 flood, flood); 2261 2262 return 0; 2263 } 2264 2265 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2266 { 2267 struct mv88e6xxx_port *mvp = dev_id; 2268 struct mv88e6xxx_chip *chip = mvp->chip; 2269 irqreturn_t ret = IRQ_NONE; 2270 int port = mvp->port; 2271 u8 lane; 2272 2273 mv88e6xxx_reg_lock(chip); 2274 lane = mv88e6xxx_serdes_get_lane(chip, port); 2275 if (lane) 2276 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2277 mv88e6xxx_reg_unlock(chip); 2278 2279 return ret; 2280 } 2281 2282 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2283 u8 lane) 2284 { 2285 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2286 unsigned int irq; 2287 int err; 2288 2289 /* Nothing to request if this SERDES port has no IRQ */ 2290 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2291 if (!irq) 2292 return 0; 2293 2294 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2295 mv88e6xxx_reg_unlock(chip); 2296 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2297 IRQF_ONESHOT, "mv88e6xxx-serdes", dev_id); 2298 mv88e6xxx_reg_lock(chip); 2299 if (err) 2300 return err; 2301 2302 dev_id->serdes_irq = irq; 2303 2304 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2305 } 2306 2307 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2308 u8 lane) 2309 { 2310 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2311 unsigned int irq = dev_id->serdes_irq; 2312 int err; 2313 2314 /* Nothing to free if no IRQ has been requested */ 2315 if (!irq) 2316 return 0; 2317 2318 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2319 2320 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2321 mv88e6xxx_reg_unlock(chip); 2322 free_irq(irq, dev_id); 2323 mv88e6xxx_reg_lock(chip); 2324 2325 dev_id->serdes_irq = 0; 2326 2327 return err; 2328 } 2329 2330 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2331 bool on) 2332 { 2333 u8 lane; 2334 int err; 2335 2336 lane = mv88e6xxx_serdes_get_lane(chip, port); 2337 if (!lane) 2338 return 0; 2339 2340 if (on) { 2341 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2342 if (err) 2343 return err; 2344 2345 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2346 } else { 2347 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2348 if (err) 2349 return err; 2350 2351 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2352 } 2353 2354 return err; 2355 } 2356 2357 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2358 { 2359 struct dsa_switch *ds = chip->ds; 2360 int upstream_port; 2361 int err; 2362 2363 upstream_port = dsa_upstream_port(ds, port); 2364 if (chip->info->ops->port_set_upstream_port) { 2365 err = chip->info->ops->port_set_upstream_port(chip, port, 2366 upstream_port); 2367 if (err) 2368 return err; 2369 } 2370 2371 if (port == upstream_port) { 2372 if (chip->info->ops->set_cpu_port) { 2373 err = chip->info->ops->set_cpu_port(chip, 2374 upstream_port); 2375 if (err) 2376 return err; 2377 } 2378 2379 if (chip->info->ops->set_egress_port) { 2380 err = chip->info->ops->set_egress_port(chip, 2381 upstream_port); 2382 if (err) 2383 return err; 2384 } 2385 } 2386 2387 return 0; 2388 } 2389 2390 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2391 { 2392 struct dsa_switch *ds = chip->ds; 2393 int err; 2394 u16 reg; 2395 2396 chip->ports[port].chip = chip; 2397 chip->ports[port].port = port; 2398 2399 /* MAC Forcing register: don't force link, speed, duplex or flow control 2400 * state to any particular values on physical ports, but force the CPU 2401 * port and all DSA ports to their maximum bandwidth and full duplex. 2402 */ 2403 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2404 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2405 SPEED_MAX, DUPLEX_FULL, 2406 PAUSE_OFF, 2407 PHY_INTERFACE_MODE_NA); 2408 else 2409 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2410 SPEED_UNFORCED, DUPLEX_UNFORCED, 2411 PAUSE_ON, 2412 PHY_INTERFACE_MODE_NA); 2413 if (err) 2414 return err; 2415 2416 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2417 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2418 * tunneling, determine priority by looking at 802.1p and IP 2419 * priority fields (IP prio has precedence), and set STP state 2420 * to Forwarding. 2421 * 2422 * If this is the CPU link, use DSA or EDSA tagging depending 2423 * on which tagging mode was configured. 2424 * 2425 * If this is a link to another switch, use DSA tagging mode. 2426 * 2427 * If this is the upstream port for this switch, enable 2428 * forwarding of unknown unicasts and multicasts. 2429 */ 2430 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2431 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2432 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2433 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2434 if (err) 2435 return err; 2436 2437 err = mv88e6xxx_setup_port_mode(chip, port); 2438 if (err) 2439 return err; 2440 2441 err = mv88e6xxx_setup_egress_floods(chip, port); 2442 if (err) 2443 return err; 2444 2445 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2446 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2447 * untagged frames on this port, do a destination address lookup on all 2448 * received packets as usual, disable ARP mirroring and don't send a 2449 * copy of all transmitted/received frames on this port to the CPU. 2450 */ 2451 err = mv88e6xxx_port_set_map_da(chip, port); 2452 if (err) 2453 return err; 2454 2455 err = mv88e6xxx_setup_upstream_port(chip, port); 2456 if (err) 2457 return err; 2458 2459 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2460 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2461 if (err) 2462 return err; 2463 2464 if (chip->info->ops->port_set_jumbo_size) { 2465 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 2466 if (err) 2467 return err; 2468 } 2469 2470 /* Port Association Vector: when learning source addresses 2471 * of packets, add the address to the address database using 2472 * a port bitmap that has only the bit for this port set and 2473 * the other bits clear. 2474 */ 2475 reg = 1 << port; 2476 /* Disable learning for CPU port */ 2477 if (dsa_is_cpu_port(ds, port)) 2478 reg = 0; 2479 2480 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2481 reg); 2482 if (err) 2483 return err; 2484 2485 /* Egress rate control 2: disable egress rate control. */ 2486 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2487 0x0000); 2488 if (err) 2489 return err; 2490 2491 if (chip->info->ops->port_pause_limit) { 2492 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2493 if (err) 2494 return err; 2495 } 2496 2497 if (chip->info->ops->port_disable_learn_limit) { 2498 err = chip->info->ops->port_disable_learn_limit(chip, port); 2499 if (err) 2500 return err; 2501 } 2502 2503 if (chip->info->ops->port_disable_pri_override) { 2504 err = chip->info->ops->port_disable_pri_override(chip, port); 2505 if (err) 2506 return err; 2507 } 2508 2509 if (chip->info->ops->port_tag_remap) { 2510 err = chip->info->ops->port_tag_remap(chip, port); 2511 if (err) 2512 return err; 2513 } 2514 2515 if (chip->info->ops->port_egress_rate_limiting) { 2516 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2517 if (err) 2518 return err; 2519 } 2520 2521 if (chip->info->ops->port_setup_message_port) { 2522 err = chip->info->ops->port_setup_message_port(chip, port); 2523 if (err) 2524 return err; 2525 } 2526 2527 /* Port based VLAN map: give each port the same default address 2528 * database, and allow bidirectional communication between the 2529 * CPU and DSA port(s), and the other ports. 2530 */ 2531 err = mv88e6xxx_port_set_fid(chip, port, 0); 2532 if (err) 2533 return err; 2534 2535 err = mv88e6xxx_port_vlan_map(chip, port); 2536 if (err) 2537 return err; 2538 2539 /* Default VLAN ID and priority: don't set a default VLAN 2540 * ID, and set the default packet priority to zero. 2541 */ 2542 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 2543 } 2544 2545 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 2546 struct phy_device *phydev) 2547 { 2548 struct mv88e6xxx_chip *chip = ds->priv; 2549 int err; 2550 2551 mv88e6xxx_reg_lock(chip); 2552 err = mv88e6xxx_serdes_power(chip, port, true); 2553 mv88e6xxx_reg_unlock(chip); 2554 2555 return err; 2556 } 2557 2558 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 2559 { 2560 struct mv88e6xxx_chip *chip = ds->priv; 2561 2562 mv88e6xxx_reg_lock(chip); 2563 if (mv88e6xxx_serdes_power(chip, port, false)) 2564 dev_err(chip->dev, "failed to power off SERDES\n"); 2565 mv88e6xxx_reg_unlock(chip); 2566 } 2567 2568 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2569 unsigned int ageing_time) 2570 { 2571 struct mv88e6xxx_chip *chip = ds->priv; 2572 int err; 2573 2574 mv88e6xxx_reg_lock(chip); 2575 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 2576 mv88e6xxx_reg_unlock(chip); 2577 2578 return err; 2579 } 2580 2581 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 2582 { 2583 int err; 2584 2585 /* Initialize the statistics unit */ 2586 if (chip->info->ops->stats_set_histogram) { 2587 err = chip->info->ops->stats_set_histogram(chip); 2588 if (err) 2589 return err; 2590 } 2591 2592 return mv88e6xxx_g1_stats_clear(chip); 2593 } 2594 2595 /* Check if the errata has already been applied. */ 2596 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 2597 { 2598 int port; 2599 int err; 2600 u16 val; 2601 2602 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2603 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 2604 if (err) { 2605 dev_err(chip->dev, 2606 "Error reading hidden register: %d\n", err); 2607 return false; 2608 } 2609 if (val != 0x01c0) 2610 return false; 2611 } 2612 2613 return true; 2614 } 2615 2616 /* The 6390 copper ports have an errata which require poking magic 2617 * values into undocumented hidden registers and then performing a 2618 * software reset. 2619 */ 2620 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 2621 { 2622 int port; 2623 int err; 2624 2625 if (mv88e6390_setup_errata_applied(chip)) 2626 return 0; 2627 2628 /* Set the ports into blocking mode */ 2629 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2630 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 2631 if (err) 2632 return err; 2633 } 2634 2635 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2636 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 2637 if (err) 2638 return err; 2639 } 2640 2641 return mv88e6xxx_software_reset(chip); 2642 } 2643 2644 static int mv88e6xxx_setup(struct dsa_switch *ds) 2645 { 2646 struct mv88e6xxx_chip *chip = ds->priv; 2647 u8 cmode; 2648 int err; 2649 int i; 2650 2651 chip->ds = ds; 2652 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2653 2654 mv88e6xxx_reg_lock(chip); 2655 2656 if (chip->info->ops->setup_errata) { 2657 err = chip->info->ops->setup_errata(chip); 2658 if (err) 2659 goto unlock; 2660 } 2661 2662 /* Cache the cmode of each port. */ 2663 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2664 if (chip->info->ops->port_get_cmode) { 2665 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 2666 if (err) 2667 goto unlock; 2668 2669 chip->ports[i].cmode = cmode; 2670 } 2671 } 2672 2673 /* Setup Switch Port Registers */ 2674 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2675 if (dsa_is_unused_port(ds, i)) 2676 continue; 2677 2678 /* Prevent the use of an invalid port. */ 2679 if (mv88e6xxx_is_invalid_port(chip, i)) { 2680 dev_err(chip->dev, "port %d is invalid\n", i); 2681 err = -EINVAL; 2682 goto unlock; 2683 } 2684 2685 err = mv88e6xxx_setup_port(chip, i); 2686 if (err) 2687 goto unlock; 2688 } 2689 2690 err = mv88e6xxx_irl_setup(chip); 2691 if (err) 2692 goto unlock; 2693 2694 err = mv88e6xxx_mac_setup(chip); 2695 if (err) 2696 goto unlock; 2697 2698 err = mv88e6xxx_phy_setup(chip); 2699 if (err) 2700 goto unlock; 2701 2702 err = mv88e6xxx_vtu_setup(chip); 2703 if (err) 2704 goto unlock; 2705 2706 err = mv88e6xxx_pvt_setup(chip); 2707 if (err) 2708 goto unlock; 2709 2710 err = mv88e6xxx_atu_setup(chip); 2711 if (err) 2712 goto unlock; 2713 2714 err = mv88e6xxx_broadcast_setup(chip, 0); 2715 if (err) 2716 goto unlock; 2717 2718 err = mv88e6xxx_pot_setup(chip); 2719 if (err) 2720 goto unlock; 2721 2722 err = mv88e6xxx_rmu_setup(chip); 2723 if (err) 2724 goto unlock; 2725 2726 err = mv88e6xxx_rsvd2cpu_setup(chip); 2727 if (err) 2728 goto unlock; 2729 2730 err = mv88e6xxx_trunk_setup(chip); 2731 if (err) 2732 goto unlock; 2733 2734 err = mv88e6xxx_devmap_setup(chip); 2735 if (err) 2736 goto unlock; 2737 2738 err = mv88e6xxx_pri_setup(chip); 2739 if (err) 2740 goto unlock; 2741 2742 /* Setup PTP Hardware Clock and timestamping */ 2743 if (chip->info->ptp_support) { 2744 err = mv88e6xxx_ptp_setup(chip); 2745 if (err) 2746 goto unlock; 2747 2748 err = mv88e6xxx_hwtstamp_setup(chip); 2749 if (err) 2750 goto unlock; 2751 } 2752 2753 err = mv88e6xxx_stats_setup(chip); 2754 if (err) 2755 goto unlock; 2756 2757 unlock: 2758 mv88e6xxx_reg_unlock(chip); 2759 2760 return err; 2761 } 2762 2763 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2764 { 2765 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2766 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2767 u16 val; 2768 int err; 2769 2770 if (!chip->info->ops->phy_read) 2771 return -EOPNOTSUPP; 2772 2773 mv88e6xxx_reg_lock(chip); 2774 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2775 mv88e6xxx_reg_unlock(chip); 2776 2777 if (reg == MII_PHYSID2) { 2778 /* Some internal PHYs don't have a model number. */ 2779 if (chip->info->family != MV88E6XXX_FAMILY_6165) 2780 /* Then there is the 6165 family. It gets is 2781 * PHYs correct. But it can also have two 2782 * SERDES interfaces in the PHY address 2783 * space. And these don't have a model 2784 * number. But they are not PHYs, so we don't 2785 * want to give them something a PHY driver 2786 * will recognise. 2787 * 2788 * Use the mv88e6390 family model number 2789 * instead, for anything which really could be 2790 * a PHY, 2791 */ 2792 if (!(val & 0x3f0)) 2793 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2794 } 2795 2796 return err ? err : val; 2797 } 2798 2799 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2800 { 2801 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2802 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2803 int err; 2804 2805 if (!chip->info->ops->phy_write) 2806 return -EOPNOTSUPP; 2807 2808 mv88e6xxx_reg_lock(chip); 2809 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2810 mv88e6xxx_reg_unlock(chip); 2811 2812 return err; 2813 } 2814 2815 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2816 struct device_node *np, 2817 bool external) 2818 { 2819 static int index; 2820 struct mv88e6xxx_mdio_bus *mdio_bus; 2821 struct mii_bus *bus; 2822 int err; 2823 2824 if (external) { 2825 mv88e6xxx_reg_lock(chip); 2826 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 2827 mv88e6xxx_reg_unlock(chip); 2828 2829 if (err) 2830 return err; 2831 } 2832 2833 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2834 if (!bus) 2835 return -ENOMEM; 2836 2837 mdio_bus = bus->priv; 2838 mdio_bus->bus = bus; 2839 mdio_bus->chip = chip; 2840 INIT_LIST_HEAD(&mdio_bus->list); 2841 mdio_bus->external = external; 2842 2843 if (np) { 2844 bus->name = np->full_name; 2845 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2846 } else { 2847 bus->name = "mv88e6xxx SMI"; 2848 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2849 } 2850 2851 bus->read = mv88e6xxx_mdio_read; 2852 bus->write = mv88e6xxx_mdio_write; 2853 bus->parent = chip->dev; 2854 2855 if (!external) { 2856 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 2857 if (err) 2858 return err; 2859 } 2860 2861 err = of_mdiobus_register(bus, np); 2862 if (err) { 2863 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2864 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2865 return err; 2866 } 2867 2868 if (external) 2869 list_add_tail(&mdio_bus->list, &chip->mdios); 2870 else 2871 list_add(&mdio_bus->list, &chip->mdios); 2872 2873 return 0; 2874 } 2875 2876 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2877 { .compatible = "marvell,mv88e6xxx-mdio-external", 2878 .data = (void *)true }, 2879 { }, 2880 }; 2881 2882 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2883 2884 { 2885 struct mv88e6xxx_mdio_bus *mdio_bus; 2886 struct mii_bus *bus; 2887 2888 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2889 bus = mdio_bus->bus; 2890 2891 if (!mdio_bus->external) 2892 mv88e6xxx_g2_irq_mdio_free(chip, bus); 2893 2894 mdiobus_unregister(bus); 2895 } 2896 } 2897 2898 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2899 struct device_node *np) 2900 { 2901 const struct of_device_id *match; 2902 struct device_node *child; 2903 int err; 2904 2905 /* Always register one mdio bus for the internal/default mdio 2906 * bus. This maybe represented in the device tree, but is 2907 * optional. 2908 */ 2909 child = of_get_child_by_name(np, "mdio"); 2910 err = mv88e6xxx_mdio_register(chip, child, false); 2911 if (err) 2912 return err; 2913 2914 /* Walk the device tree, and see if there are any other nodes 2915 * which say they are compatible with the external mdio 2916 * bus. 2917 */ 2918 for_each_available_child_of_node(np, child) { 2919 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2920 if (match) { 2921 err = mv88e6xxx_mdio_register(chip, child, true); 2922 if (err) { 2923 mv88e6xxx_mdios_unregister(chip); 2924 of_node_put(child); 2925 return err; 2926 } 2927 } 2928 } 2929 2930 return 0; 2931 } 2932 2933 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2934 { 2935 struct mv88e6xxx_chip *chip = ds->priv; 2936 2937 return chip->eeprom_len; 2938 } 2939 2940 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2941 struct ethtool_eeprom *eeprom, u8 *data) 2942 { 2943 struct mv88e6xxx_chip *chip = ds->priv; 2944 int err; 2945 2946 if (!chip->info->ops->get_eeprom) 2947 return -EOPNOTSUPP; 2948 2949 mv88e6xxx_reg_lock(chip); 2950 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2951 mv88e6xxx_reg_unlock(chip); 2952 2953 if (err) 2954 return err; 2955 2956 eeprom->magic = 0xc3ec4951; 2957 2958 return 0; 2959 } 2960 2961 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2962 struct ethtool_eeprom *eeprom, u8 *data) 2963 { 2964 struct mv88e6xxx_chip *chip = ds->priv; 2965 int err; 2966 2967 if (!chip->info->ops->set_eeprom) 2968 return -EOPNOTSUPP; 2969 2970 if (eeprom->magic != 0xc3ec4951) 2971 return -EINVAL; 2972 2973 mv88e6xxx_reg_lock(chip); 2974 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2975 mv88e6xxx_reg_unlock(chip); 2976 2977 return err; 2978 } 2979 2980 static const struct mv88e6xxx_ops mv88e6085_ops = { 2981 /* MV88E6XXX_FAMILY_6097 */ 2982 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 2983 .ip_pri_map = mv88e6085_g1_ip_pri_map, 2984 .irl_init_all = mv88e6352_g2_irl_init_all, 2985 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2986 .phy_read = mv88e6185_phy_ppu_read, 2987 .phy_write = mv88e6185_phy_ppu_write, 2988 .port_set_link = mv88e6xxx_port_set_link, 2989 .port_set_duplex = mv88e6xxx_port_set_duplex, 2990 .port_set_speed = mv88e6185_port_set_speed, 2991 .port_tag_remap = mv88e6095_port_tag_remap, 2992 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2993 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2994 .port_set_ether_type = mv88e6351_port_set_ether_type, 2995 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2996 .port_pause_limit = mv88e6097_port_pause_limit, 2997 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2998 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2999 .port_link_state = mv88e6352_port_link_state, 3000 .port_get_cmode = mv88e6185_port_get_cmode, 3001 .port_setup_message_port = mv88e6xxx_setup_message_port, 3002 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3003 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3004 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3005 .stats_get_strings = mv88e6095_stats_get_strings, 3006 .stats_get_stats = mv88e6095_stats_get_stats, 3007 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3008 .set_egress_port = mv88e6095_g1_set_egress_port, 3009 .watchdog_ops = &mv88e6097_watchdog_ops, 3010 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3011 .pot_clear = mv88e6xxx_g2_pot_clear, 3012 .ppu_enable = mv88e6185_g1_ppu_enable, 3013 .ppu_disable = mv88e6185_g1_ppu_disable, 3014 .reset = mv88e6185_g1_reset, 3015 .rmu_disable = mv88e6085_g1_rmu_disable, 3016 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3017 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3018 .phylink_validate = mv88e6185_phylink_validate, 3019 }; 3020 3021 static const struct mv88e6xxx_ops mv88e6095_ops = { 3022 /* MV88E6XXX_FAMILY_6095 */ 3023 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3024 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3025 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3026 .phy_read = mv88e6185_phy_ppu_read, 3027 .phy_write = mv88e6185_phy_ppu_write, 3028 .port_set_link = mv88e6xxx_port_set_link, 3029 .port_set_duplex = mv88e6xxx_port_set_duplex, 3030 .port_set_speed = mv88e6185_port_set_speed, 3031 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3032 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3033 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3034 .port_link_state = mv88e6185_port_link_state, 3035 .port_get_cmode = mv88e6185_port_get_cmode, 3036 .port_setup_message_port = mv88e6xxx_setup_message_port, 3037 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3038 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3039 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3040 .stats_get_strings = mv88e6095_stats_get_strings, 3041 .stats_get_stats = mv88e6095_stats_get_stats, 3042 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3043 .ppu_enable = mv88e6185_g1_ppu_enable, 3044 .ppu_disable = mv88e6185_g1_ppu_disable, 3045 .reset = mv88e6185_g1_reset, 3046 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3047 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3048 .phylink_validate = mv88e6185_phylink_validate, 3049 }; 3050 3051 static const struct mv88e6xxx_ops mv88e6097_ops = { 3052 /* MV88E6XXX_FAMILY_6097 */ 3053 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3054 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3055 .irl_init_all = mv88e6352_g2_irl_init_all, 3056 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3057 .phy_read = mv88e6xxx_g2_smi_phy_read, 3058 .phy_write = mv88e6xxx_g2_smi_phy_write, 3059 .port_set_link = mv88e6xxx_port_set_link, 3060 .port_set_duplex = mv88e6xxx_port_set_duplex, 3061 .port_set_speed = mv88e6185_port_set_speed, 3062 .port_tag_remap = mv88e6095_port_tag_remap, 3063 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3064 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3065 .port_set_ether_type = mv88e6351_port_set_ether_type, 3066 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3067 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3068 .port_pause_limit = mv88e6097_port_pause_limit, 3069 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3070 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3071 .port_link_state = mv88e6352_port_link_state, 3072 .port_get_cmode = mv88e6185_port_get_cmode, 3073 .port_setup_message_port = mv88e6xxx_setup_message_port, 3074 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3075 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3076 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3077 .stats_get_strings = mv88e6095_stats_get_strings, 3078 .stats_get_stats = mv88e6095_stats_get_stats, 3079 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3080 .set_egress_port = mv88e6095_g1_set_egress_port, 3081 .watchdog_ops = &mv88e6097_watchdog_ops, 3082 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3083 .pot_clear = mv88e6xxx_g2_pot_clear, 3084 .reset = mv88e6352_g1_reset, 3085 .rmu_disable = mv88e6085_g1_rmu_disable, 3086 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3087 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3088 .phylink_validate = mv88e6185_phylink_validate, 3089 }; 3090 3091 static const struct mv88e6xxx_ops mv88e6123_ops = { 3092 /* MV88E6XXX_FAMILY_6165 */ 3093 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3094 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3095 .irl_init_all = mv88e6352_g2_irl_init_all, 3096 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3097 .phy_read = mv88e6xxx_g2_smi_phy_read, 3098 .phy_write = mv88e6xxx_g2_smi_phy_write, 3099 .port_set_link = mv88e6xxx_port_set_link, 3100 .port_set_duplex = mv88e6xxx_port_set_duplex, 3101 .port_set_speed = mv88e6185_port_set_speed, 3102 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3103 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3104 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3105 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3106 .port_link_state = mv88e6352_port_link_state, 3107 .port_get_cmode = mv88e6185_port_get_cmode, 3108 .port_setup_message_port = mv88e6xxx_setup_message_port, 3109 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3110 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3111 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3112 .stats_get_strings = mv88e6095_stats_get_strings, 3113 .stats_get_stats = mv88e6095_stats_get_stats, 3114 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3115 .set_egress_port = mv88e6095_g1_set_egress_port, 3116 .watchdog_ops = &mv88e6097_watchdog_ops, 3117 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3118 .pot_clear = mv88e6xxx_g2_pot_clear, 3119 .reset = mv88e6352_g1_reset, 3120 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3121 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3122 .phylink_validate = mv88e6185_phylink_validate, 3123 }; 3124 3125 static const struct mv88e6xxx_ops mv88e6131_ops = { 3126 /* MV88E6XXX_FAMILY_6185 */ 3127 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3128 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3129 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3130 .phy_read = mv88e6185_phy_ppu_read, 3131 .phy_write = mv88e6185_phy_ppu_write, 3132 .port_set_link = mv88e6xxx_port_set_link, 3133 .port_set_duplex = mv88e6xxx_port_set_duplex, 3134 .port_set_speed = mv88e6185_port_set_speed, 3135 .port_tag_remap = mv88e6095_port_tag_remap, 3136 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3137 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3138 .port_set_ether_type = mv88e6351_port_set_ether_type, 3139 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3140 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3141 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3142 .port_pause_limit = mv88e6097_port_pause_limit, 3143 .port_set_pause = mv88e6185_port_set_pause, 3144 .port_link_state = mv88e6352_port_link_state, 3145 .port_get_cmode = mv88e6185_port_get_cmode, 3146 .port_setup_message_port = mv88e6xxx_setup_message_port, 3147 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3148 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3149 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3150 .stats_get_strings = mv88e6095_stats_get_strings, 3151 .stats_get_stats = mv88e6095_stats_get_stats, 3152 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3153 .set_egress_port = mv88e6095_g1_set_egress_port, 3154 .watchdog_ops = &mv88e6097_watchdog_ops, 3155 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3156 .ppu_enable = mv88e6185_g1_ppu_enable, 3157 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3158 .ppu_disable = mv88e6185_g1_ppu_disable, 3159 .reset = mv88e6185_g1_reset, 3160 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3161 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3162 .phylink_validate = mv88e6185_phylink_validate, 3163 }; 3164 3165 static const struct mv88e6xxx_ops mv88e6141_ops = { 3166 /* MV88E6XXX_FAMILY_6341 */ 3167 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3168 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3169 .irl_init_all = mv88e6352_g2_irl_init_all, 3170 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3171 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3172 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3173 .phy_read = mv88e6xxx_g2_smi_phy_read, 3174 .phy_write = mv88e6xxx_g2_smi_phy_write, 3175 .port_set_link = mv88e6xxx_port_set_link, 3176 .port_set_duplex = mv88e6xxx_port_set_duplex, 3177 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3178 .port_set_speed = mv88e6341_port_set_speed, 3179 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3180 .port_tag_remap = mv88e6095_port_tag_remap, 3181 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3182 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3183 .port_set_ether_type = mv88e6351_port_set_ether_type, 3184 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3185 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3186 .port_pause_limit = mv88e6097_port_pause_limit, 3187 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3188 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3189 .port_link_state = mv88e6352_port_link_state, 3190 .port_get_cmode = mv88e6352_port_get_cmode, 3191 .port_set_cmode = mv88e6341_port_set_cmode, 3192 .port_setup_message_port = mv88e6xxx_setup_message_port, 3193 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3194 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3195 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3196 .stats_get_strings = mv88e6320_stats_get_strings, 3197 .stats_get_stats = mv88e6390_stats_get_stats, 3198 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3199 .set_egress_port = mv88e6390_g1_set_egress_port, 3200 .watchdog_ops = &mv88e6390_watchdog_ops, 3201 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3202 .pot_clear = mv88e6xxx_g2_pot_clear, 3203 .reset = mv88e6352_g1_reset, 3204 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3205 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3206 .serdes_power = mv88e6390_serdes_power, 3207 .serdes_get_lane = mv88e6341_serdes_get_lane, 3208 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3209 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3210 .serdes_irq_status = mv88e6390_serdes_irq_status, 3211 .gpio_ops = &mv88e6352_gpio_ops, 3212 .phylink_validate = mv88e6341_phylink_validate, 3213 }; 3214 3215 static const struct mv88e6xxx_ops mv88e6161_ops = { 3216 /* MV88E6XXX_FAMILY_6165 */ 3217 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3218 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3219 .irl_init_all = mv88e6352_g2_irl_init_all, 3220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3221 .phy_read = mv88e6xxx_g2_smi_phy_read, 3222 .phy_write = mv88e6xxx_g2_smi_phy_write, 3223 .port_set_link = mv88e6xxx_port_set_link, 3224 .port_set_duplex = mv88e6xxx_port_set_duplex, 3225 .port_set_speed = mv88e6185_port_set_speed, 3226 .port_tag_remap = mv88e6095_port_tag_remap, 3227 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3228 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3229 .port_set_ether_type = mv88e6351_port_set_ether_type, 3230 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3231 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3232 .port_pause_limit = mv88e6097_port_pause_limit, 3233 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3234 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3235 .port_link_state = mv88e6352_port_link_state, 3236 .port_get_cmode = mv88e6185_port_get_cmode, 3237 .port_setup_message_port = mv88e6xxx_setup_message_port, 3238 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3239 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3240 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3241 .stats_get_strings = mv88e6095_stats_get_strings, 3242 .stats_get_stats = mv88e6095_stats_get_stats, 3243 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3244 .set_egress_port = mv88e6095_g1_set_egress_port, 3245 .watchdog_ops = &mv88e6097_watchdog_ops, 3246 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3247 .pot_clear = mv88e6xxx_g2_pot_clear, 3248 .reset = mv88e6352_g1_reset, 3249 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3250 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3251 .avb_ops = &mv88e6165_avb_ops, 3252 .ptp_ops = &mv88e6165_ptp_ops, 3253 .phylink_validate = mv88e6185_phylink_validate, 3254 }; 3255 3256 static const struct mv88e6xxx_ops mv88e6165_ops = { 3257 /* MV88E6XXX_FAMILY_6165 */ 3258 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3259 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3260 .irl_init_all = mv88e6352_g2_irl_init_all, 3261 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3262 .phy_read = mv88e6165_phy_read, 3263 .phy_write = mv88e6165_phy_write, 3264 .port_set_link = mv88e6xxx_port_set_link, 3265 .port_set_duplex = mv88e6xxx_port_set_duplex, 3266 .port_set_speed = mv88e6185_port_set_speed, 3267 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3268 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3269 .port_link_state = mv88e6352_port_link_state, 3270 .port_get_cmode = mv88e6185_port_get_cmode, 3271 .port_setup_message_port = mv88e6xxx_setup_message_port, 3272 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3273 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3274 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3275 .stats_get_strings = mv88e6095_stats_get_strings, 3276 .stats_get_stats = mv88e6095_stats_get_stats, 3277 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3278 .set_egress_port = mv88e6095_g1_set_egress_port, 3279 .watchdog_ops = &mv88e6097_watchdog_ops, 3280 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3281 .pot_clear = mv88e6xxx_g2_pot_clear, 3282 .reset = mv88e6352_g1_reset, 3283 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3284 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3285 .avb_ops = &mv88e6165_avb_ops, 3286 .ptp_ops = &mv88e6165_ptp_ops, 3287 .phylink_validate = mv88e6185_phylink_validate, 3288 }; 3289 3290 static const struct mv88e6xxx_ops mv88e6171_ops = { 3291 /* MV88E6XXX_FAMILY_6351 */ 3292 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3293 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3294 .irl_init_all = mv88e6352_g2_irl_init_all, 3295 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3296 .phy_read = mv88e6xxx_g2_smi_phy_read, 3297 .phy_write = mv88e6xxx_g2_smi_phy_write, 3298 .port_set_link = mv88e6xxx_port_set_link, 3299 .port_set_duplex = mv88e6xxx_port_set_duplex, 3300 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3301 .port_set_speed = mv88e6185_port_set_speed, 3302 .port_tag_remap = mv88e6095_port_tag_remap, 3303 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3304 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3305 .port_set_ether_type = mv88e6351_port_set_ether_type, 3306 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3307 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3308 .port_pause_limit = mv88e6097_port_pause_limit, 3309 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3310 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3311 .port_link_state = mv88e6352_port_link_state, 3312 .port_get_cmode = mv88e6352_port_get_cmode, 3313 .port_setup_message_port = mv88e6xxx_setup_message_port, 3314 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3315 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3316 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3317 .stats_get_strings = mv88e6095_stats_get_strings, 3318 .stats_get_stats = mv88e6095_stats_get_stats, 3319 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3320 .set_egress_port = mv88e6095_g1_set_egress_port, 3321 .watchdog_ops = &mv88e6097_watchdog_ops, 3322 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3323 .pot_clear = mv88e6xxx_g2_pot_clear, 3324 .reset = mv88e6352_g1_reset, 3325 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3326 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3327 .phylink_validate = mv88e6185_phylink_validate, 3328 }; 3329 3330 static const struct mv88e6xxx_ops mv88e6172_ops = { 3331 /* MV88E6XXX_FAMILY_6352 */ 3332 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3333 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3334 .irl_init_all = mv88e6352_g2_irl_init_all, 3335 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3336 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3337 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3338 .phy_read = mv88e6xxx_g2_smi_phy_read, 3339 .phy_write = mv88e6xxx_g2_smi_phy_write, 3340 .port_set_link = mv88e6xxx_port_set_link, 3341 .port_set_duplex = mv88e6xxx_port_set_duplex, 3342 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3343 .port_set_speed = mv88e6352_port_set_speed, 3344 .port_tag_remap = mv88e6095_port_tag_remap, 3345 .port_set_policy = mv88e6352_port_set_policy, 3346 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3347 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3348 .port_set_ether_type = mv88e6351_port_set_ether_type, 3349 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3350 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3351 .port_pause_limit = mv88e6097_port_pause_limit, 3352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3354 .port_link_state = mv88e6352_port_link_state, 3355 .port_get_cmode = mv88e6352_port_get_cmode, 3356 .port_setup_message_port = mv88e6xxx_setup_message_port, 3357 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3358 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3359 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3360 .stats_get_strings = mv88e6095_stats_get_strings, 3361 .stats_get_stats = mv88e6095_stats_get_stats, 3362 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3363 .set_egress_port = mv88e6095_g1_set_egress_port, 3364 .watchdog_ops = &mv88e6097_watchdog_ops, 3365 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3366 .pot_clear = mv88e6xxx_g2_pot_clear, 3367 .reset = mv88e6352_g1_reset, 3368 .rmu_disable = mv88e6352_g1_rmu_disable, 3369 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3370 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3371 .serdes_get_lane = mv88e6352_serdes_get_lane, 3372 .serdes_power = mv88e6352_serdes_power, 3373 .gpio_ops = &mv88e6352_gpio_ops, 3374 .phylink_validate = mv88e6352_phylink_validate, 3375 }; 3376 3377 static const struct mv88e6xxx_ops mv88e6175_ops = { 3378 /* MV88E6XXX_FAMILY_6351 */ 3379 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3380 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3381 .irl_init_all = mv88e6352_g2_irl_init_all, 3382 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3383 .phy_read = mv88e6xxx_g2_smi_phy_read, 3384 .phy_write = mv88e6xxx_g2_smi_phy_write, 3385 .port_set_link = mv88e6xxx_port_set_link, 3386 .port_set_duplex = mv88e6xxx_port_set_duplex, 3387 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3388 .port_set_speed = mv88e6185_port_set_speed, 3389 .port_tag_remap = mv88e6095_port_tag_remap, 3390 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3391 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3392 .port_set_ether_type = mv88e6351_port_set_ether_type, 3393 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3394 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3395 .port_pause_limit = mv88e6097_port_pause_limit, 3396 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3397 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3398 .port_link_state = mv88e6352_port_link_state, 3399 .port_get_cmode = mv88e6352_port_get_cmode, 3400 .port_setup_message_port = mv88e6xxx_setup_message_port, 3401 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3402 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3403 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3404 .stats_get_strings = mv88e6095_stats_get_strings, 3405 .stats_get_stats = mv88e6095_stats_get_stats, 3406 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3407 .set_egress_port = mv88e6095_g1_set_egress_port, 3408 .watchdog_ops = &mv88e6097_watchdog_ops, 3409 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3410 .pot_clear = mv88e6xxx_g2_pot_clear, 3411 .reset = mv88e6352_g1_reset, 3412 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3413 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3414 .phylink_validate = mv88e6185_phylink_validate, 3415 }; 3416 3417 static const struct mv88e6xxx_ops mv88e6176_ops = { 3418 /* MV88E6XXX_FAMILY_6352 */ 3419 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3420 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3421 .irl_init_all = mv88e6352_g2_irl_init_all, 3422 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3423 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3424 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3425 .phy_read = mv88e6xxx_g2_smi_phy_read, 3426 .phy_write = mv88e6xxx_g2_smi_phy_write, 3427 .port_set_link = mv88e6xxx_port_set_link, 3428 .port_set_duplex = mv88e6xxx_port_set_duplex, 3429 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3430 .port_set_speed = mv88e6352_port_set_speed, 3431 .port_tag_remap = mv88e6095_port_tag_remap, 3432 .port_set_policy = mv88e6352_port_set_policy, 3433 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3434 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3435 .port_set_ether_type = mv88e6351_port_set_ether_type, 3436 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3437 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3438 .port_pause_limit = mv88e6097_port_pause_limit, 3439 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3440 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3441 .port_link_state = mv88e6352_port_link_state, 3442 .port_get_cmode = mv88e6352_port_get_cmode, 3443 .port_setup_message_port = mv88e6xxx_setup_message_port, 3444 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3445 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3446 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3447 .stats_get_strings = mv88e6095_stats_get_strings, 3448 .stats_get_stats = mv88e6095_stats_get_stats, 3449 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3450 .set_egress_port = mv88e6095_g1_set_egress_port, 3451 .watchdog_ops = &mv88e6097_watchdog_ops, 3452 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3453 .pot_clear = mv88e6xxx_g2_pot_clear, 3454 .reset = mv88e6352_g1_reset, 3455 .rmu_disable = mv88e6352_g1_rmu_disable, 3456 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3457 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3458 .serdes_get_lane = mv88e6352_serdes_get_lane, 3459 .serdes_power = mv88e6352_serdes_power, 3460 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3461 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3462 .serdes_irq_status = mv88e6352_serdes_irq_status, 3463 .gpio_ops = &mv88e6352_gpio_ops, 3464 .phylink_validate = mv88e6352_phylink_validate, 3465 }; 3466 3467 static const struct mv88e6xxx_ops mv88e6185_ops = { 3468 /* MV88E6XXX_FAMILY_6185 */ 3469 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3470 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3471 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3472 .phy_read = mv88e6185_phy_ppu_read, 3473 .phy_write = mv88e6185_phy_ppu_write, 3474 .port_set_link = mv88e6xxx_port_set_link, 3475 .port_set_duplex = mv88e6xxx_port_set_duplex, 3476 .port_set_speed = mv88e6185_port_set_speed, 3477 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3478 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 3479 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3480 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3481 .port_set_pause = mv88e6185_port_set_pause, 3482 .port_link_state = mv88e6185_port_link_state, 3483 .port_get_cmode = mv88e6185_port_get_cmode, 3484 .port_setup_message_port = mv88e6xxx_setup_message_port, 3485 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3486 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3487 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3488 .stats_get_strings = mv88e6095_stats_get_strings, 3489 .stats_get_stats = mv88e6095_stats_get_stats, 3490 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3491 .set_egress_port = mv88e6095_g1_set_egress_port, 3492 .watchdog_ops = &mv88e6097_watchdog_ops, 3493 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3494 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3495 .ppu_enable = mv88e6185_g1_ppu_enable, 3496 .ppu_disable = mv88e6185_g1_ppu_disable, 3497 .reset = mv88e6185_g1_reset, 3498 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3499 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3500 .phylink_validate = mv88e6185_phylink_validate, 3501 }; 3502 3503 static const struct mv88e6xxx_ops mv88e6190_ops = { 3504 /* MV88E6XXX_FAMILY_6390 */ 3505 .setup_errata = mv88e6390_setup_errata, 3506 .irl_init_all = mv88e6390_g2_irl_init_all, 3507 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3508 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3509 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3510 .phy_read = mv88e6xxx_g2_smi_phy_read, 3511 .phy_write = mv88e6xxx_g2_smi_phy_write, 3512 .port_set_link = mv88e6xxx_port_set_link, 3513 .port_set_duplex = mv88e6xxx_port_set_duplex, 3514 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3515 .port_set_speed = mv88e6390_port_set_speed, 3516 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3517 .port_tag_remap = mv88e6390_port_tag_remap, 3518 .port_set_policy = mv88e6352_port_set_policy, 3519 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3520 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3521 .port_set_ether_type = mv88e6351_port_set_ether_type, 3522 .port_pause_limit = mv88e6390_port_pause_limit, 3523 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3524 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3525 .port_link_state = mv88e6352_port_link_state, 3526 .port_get_cmode = mv88e6352_port_get_cmode, 3527 .port_set_cmode = mv88e6390_port_set_cmode, 3528 .port_setup_message_port = mv88e6xxx_setup_message_port, 3529 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3530 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3531 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3532 .stats_get_strings = mv88e6320_stats_get_strings, 3533 .stats_get_stats = mv88e6390_stats_get_stats, 3534 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3535 .set_egress_port = mv88e6390_g1_set_egress_port, 3536 .watchdog_ops = &mv88e6390_watchdog_ops, 3537 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3538 .pot_clear = mv88e6xxx_g2_pot_clear, 3539 .reset = mv88e6352_g1_reset, 3540 .rmu_disable = mv88e6390_g1_rmu_disable, 3541 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3542 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3543 .serdes_power = mv88e6390_serdes_power, 3544 .serdes_get_lane = mv88e6390_serdes_get_lane, 3545 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3546 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3547 .serdes_irq_status = mv88e6390_serdes_irq_status, 3548 .gpio_ops = &mv88e6352_gpio_ops, 3549 .phylink_validate = mv88e6390_phylink_validate, 3550 }; 3551 3552 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3553 /* MV88E6XXX_FAMILY_6390 */ 3554 .setup_errata = mv88e6390_setup_errata, 3555 .irl_init_all = mv88e6390_g2_irl_init_all, 3556 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3557 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3558 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3559 .phy_read = mv88e6xxx_g2_smi_phy_read, 3560 .phy_write = mv88e6xxx_g2_smi_phy_write, 3561 .port_set_link = mv88e6xxx_port_set_link, 3562 .port_set_duplex = mv88e6xxx_port_set_duplex, 3563 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3564 .port_set_speed = mv88e6390x_port_set_speed, 3565 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 3566 .port_tag_remap = mv88e6390_port_tag_remap, 3567 .port_set_policy = mv88e6352_port_set_policy, 3568 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3569 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3570 .port_set_ether_type = mv88e6351_port_set_ether_type, 3571 .port_pause_limit = mv88e6390_port_pause_limit, 3572 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3573 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3574 .port_link_state = mv88e6352_port_link_state, 3575 .port_get_cmode = mv88e6352_port_get_cmode, 3576 .port_set_cmode = mv88e6390x_port_set_cmode, 3577 .port_setup_message_port = mv88e6xxx_setup_message_port, 3578 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3579 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3580 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3581 .stats_get_strings = mv88e6320_stats_get_strings, 3582 .stats_get_stats = mv88e6390_stats_get_stats, 3583 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3584 .set_egress_port = mv88e6390_g1_set_egress_port, 3585 .watchdog_ops = &mv88e6390_watchdog_ops, 3586 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3587 .pot_clear = mv88e6xxx_g2_pot_clear, 3588 .reset = mv88e6352_g1_reset, 3589 .rmu_disable = mv88e6390_g1_rmu_disable, 3590 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3591 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3592 .serdes_power = mv88e6390_serdes_power, 3593 .serdes_get_lane = mv88e6390x_serdes_get_lane, 3594 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3595 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3596 .serdes_irq_status = mv88e6390_serdes_irq_status, 3597 .gpio_ops = &mv88e6352_gpio_ops, 3598 .phylink_validate = mv88e6390x_phylink_validate, 3599 }; 3600 3601 static const struct mv88e6xxx_ops mv88e6191_ops = { 3602 /* MV88E6XXX_FAMILY_6390 */ 3603 .setup_errata = mv88e6390_setup_errata, 3604 .irl_init_all = mv88e6390_g2_irl_init_all, 3605 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3606 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3607 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3608 .phy_read = mv88e6xxx_g2_smi_phy_read, 3609 .phy_write = mv88e6xxx_g2_smi_phy_write, 3610 .port_set_link = mv88e6xxx_port_set_link, 3611 .port_set_duplex = mv88e6xxx_port_set_duplex, 3612 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3613 .port_set_speed = mv88e6390_port_set_speed, 3614 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3615 .port_tag_remap = mv88e6390_port_tag_remap, 3616 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3617 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3618 .port_set_ether_type = mv88e6351_port_set_ether_type, 3619 .port_pause_limit = mv88e6390_port_pause_limit, 3620 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3621 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3622 .port_link_state = mv88e6352_port_link_state, 3623 .port_get_cmode = mv88e6352_port_get_cmode, 3624 .port_set_cmode = mv88e6390_port_set_cmode, 3625 .port_setup_message_port = mv88e6xxx_setup_message_port, 3626 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3627 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3628 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3629 .stats_get_strings = mv88e6320_stats_get_strings, 3630 .stats_get_stats = mv88e6390_stats_get_stats, 3631 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3632 .set_egress_port = mv88e6390_g1_set_egress_port, 3633 .watchdog_ops = &mv88e6390_watchdog_ops, 3634 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3635 .pot_clear = mv88e6xxx_g2_pot_clear, 3636 .reset = mv88e6352_g1_reset, 3637 .rmu_disable = mv88e6390_g1_rmu_disable, 3638 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3639 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3640 .serdes_power = mv88e6390_serdes_power, 3641 .serdes_get_lane = mv88e6390_serdes_get_lane, 3642 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3643 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3644 .serdes_irq_status = mv88e6390_serdes_irq_status, 3645 .avb_ops = &mv88e6390_avb_ops, 3646 .ptp_ops = &mv88e6352_ptp_ops, 3647 .phylink_validate = mv88e6390_phylink_validate, 3648 }; 3649 3650 static const struct mv88e6xxx_ops mv88e6240_ops = { 3651 /* MV88E6XXX_FAMILY_6352 */ 3652 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3653 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3654 .irl_init_all = mv88e6352_g2_irl_init_all, 3655 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3656 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3657 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3658 .phy_read = mv88e6xxx_g2_smi_phy_read, 3659 .phy_write = mv88e6xxx_g2_smi_phy_write, 3660 .port_set_link = mv88e6xxx_port_set_link, 3661 .port_set_duplex = mv88e6xxx_port_set_duplex, 3662 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3663 .port_set_speed = mv88e6352_port_set_speed, 3664 .port_tag_remap = mv88e6095_port_tag_remap, 3665 .port_set_policy = mv88e6352_port_set_policy, 3666 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3667 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3668 .port_set_ether_type = mv88e6351_port_set_ether_type, 3669 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3670 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3671 .port_pause_limit = mv88e6097_port_pause_limit, 3672 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3673 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3674 .port_link_state = mv88e6352_port_link_state, 3675 .port_get_cmode = mv88e6352_port_get_cmode, 3676 .port_setup_message_port = mv88e6xxx_setup_message_port, 3677 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3678 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3679 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3680 .stats_get_strings = mv88e6095_stats_get_strings, 3681 .stats_get_stats = mv88e6095_stats_get_stats, 3682 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3683 .set_egress_port = mv88e6095_g1_set_egress_port, 3684 .watchdog_ops = &mv88e6097_watchdog_ops, 3685 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3686 .pot_clear = mv88e6xxx_g2_pot_clear, 3687 .reset = mv88e6352_g1_reset, 3688 .rmu_disable = mv88e6352_g1_rmu_disable, 3689 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3690 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3691 .serdes_get_lane = mv88e6352_serdes_get_lane, 3692 .serdes_power = mv88e6352_serdes_power, 3693 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 3694 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 3695 .serdes_irq_status = mv88e6352_serdes_irq_status, 3696 .gpio_ops = &mv88e6352_gpio_ops, 3697 .avb_ops = &mv88e6352_avb_ops, 3698 .ptp_ops = &mv88e6352_ptp_ops, 3699 .phylink_validate = mv88e6352_phylink_validate, 3700 }; 3701 3702 static const struct mv88e6xxx_ops mv88e6250_ops = { 3703 /* MV88E6XXX_FAMILY_6250 */ 3704 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 3705 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3706 .irl_init_all = mv88e6352_g2_irl_init_all, 3707 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3708 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3709 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3710 .phy_read = mv88e6xxx_g2_smi_phy_read, 3711 .phy_write = mv88e6xxx_g2_smi_phy_write, 3712 .port_set_link = mv88e6xxx_port_set_link, 3713 .port_set_duplex = mv88e6xxx_port_set_duplex, 3714 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3715 .port_set_speed = mv88e6250_port_set_speed, 3716 .port_tag_remap = mv88e6095_port_tag_remap, 3717 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3718 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3719 .port_set_ether_type = mv88e6351_port_set_ether_type, 3720 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3721 .port_pause_limit = mv88e6097_port_pause_limit, 3722 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3723 .port_link_state = mv88e6250_port_link_state, 3724 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3725 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3726 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 3727 .stats_get_strings = mv88e6250_stats_get_strings, 3728 .stats_get_stats = mv88e6250_stats_get_stats, 3729 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3730 .set_egress_port = mv88e6095_g1_set_egress_port, 3731 .watchdog_ops = &mv88e6250_watchdog_ops, 3732 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3733 .pot_clear = mv88e6xxx_g2_pot_clear, 3734 .reset = mv88e6250_g1_reset, 3735 .vtu_getnext = mv88e6250_g1_vtu_getnext, 3736 .vtu_loadpurge = mv88e6250_g1_vtu_loadpurge, 3737 .avb_ops = &mv88e6352_avb_ops, 3738 .ptp_ops = &mv88e6250_ptp_ops, 3739 .phylink_validate = mv88e6065_phylink_validate, 3740 }; 3741 3742 static const struct mv88e6xxx_ops mv88e6290_ops = { 3743 /* MV88E6XXX_FAMILY_6390 */ 3744 .setup_errata = mv88e6390_setup_errata, 3745 .irl_init_all = mv88e6390_g2_irl_init_all, 3746 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3747 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3748 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3749 .phy_read = mv88e6xxx_g2_smi_phy_read, 3750 .phy_write = mv88e6xxx_g2_smi_phy_write, 3751 .port_set_link = mv88e6xxx_port_set_link, 3752 .port_set_duplex = mv88e6xxx_port_set_duplex, 3753 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3754 .port_set_speed = mv88e6390_port_set_speed, 3755 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 3756 .port_tag_remap = mv88e6390_port_tag_remap, 3757 .port_set_policy = mv88e6352_port_set_policy, 3758 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3759 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3760 .port_set_ether_type = mv88e6351_port_set_ether_type, 3761 .port_pause_limit = mv88e6390_port_pause_limit, 3762 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3763 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3764 .port_link_state = mv88e6352_port_link_state, 3765 .port_get_cmode = mv88e6352_port_get_cmode, 3766 .port_set_cmode = mv88e6390_port_set_cmode, 3767 .port_setup_message_port = mv88e6xxx_setup_message_port, 3768 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3769 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3770 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3771 .stats_get_strings = mv88e6320_stats_get_strings, 3772 .stats_get_stats = mv88e6390_stats_get_stats, 3773 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3774 .set_egress_port = mv88e6390_g1_set_egress_port, 3775 .watchdog_ops = &mv88e6390_watchdog_ops, 3776 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3777 .pot_clear = mv88e6xxx_g2_pot_clear, 3778 .reset = mv88e6352_g1_reset, 3779 .rmu_disable = mv88e6390_g1_rmu_disable, 3780 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3781 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3782 .serdes_power = mv88e6390_serdes_power, 3783 .serdes_get_lane = mv88e6390_serdes_get_lane, 3784 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3785 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3786 .serdes_irq_status = mv88e6390_serdes_irq_status, 3787 .gpio_ops = &mv88e6352_gpio_ops, 3788 .avb_ops = &mv88e6390_avb_ops, 3789 .ptp_ops = &mv88e6352_ptp_ops, 3790 .phylink_validate = mv88e6390_phylink_validate, 3791 }; 3792 3793 static const struct mv88e6xxx_ops mv88e6320_ops = { 3794 /* MV88E6XXX_FAMILY_6320 */ 3795 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3796 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3797 .irl_init_all = mv88e6352_g2_irl_init_all, 3798 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3799 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3800 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3801 .phy_read = mv88e6xxx_g2_smi_phy_read, 3802 .phy_write = mv88e6xxx_g2_smi_phy_write, 3803 .port_set_link = mv88e6xxx_port_set_link, 3804 .port_set_duplex = mv88e6xxx_port_set_duplex, 3805 .port_set_speed = mv88e6185_port_set_speed, 3806 .port_tag_remap = mv88e6095_port_tag_remap, 3807 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3808 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3809 .port_set_ether_type = mv88e6351_port_set_ether_type, 3810 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3811 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3812 .port_pause_limit = mv88e6097_port_pause_limit, 3813 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3814 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3815 .port_link_state = mv88e6352_port_link_state, 3816 .port_get_cmode = mv88e6352_port_get_cmode, 3817 .port_setup_message_port = mv88e6xxx_setup_message_port, 3818 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3819 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3820 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3821 .stats_get_strings = mv88e6320_stats_get_strings, 3822 .stats_get_stats = mv88e6320_stats_get_stats, 3823 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3824 .set_egress_port = mv88e6095_g1_set_egress_port, 3825 .watchdog_ops = &mv88e6390_watchdog_ops, 3826 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3827 .pot_clear = mv88e6xxx_g2_pot_clear, 3828 .reset = mv88e6352_g1_reset, 3829 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3830 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3831 .gpio_ops = &mv88e6352_gpio_ops, 3832 .avb_ops = &mv88e6352_avb_ops, 3833 .ptp_ops = &mv88e6352_ptp_ops, 3834 .phylink_validate = mv88e6185_phylink_validate, 3835 }; 3836 3837 static const struct mv88e6xxx_ops mv88e6321_ops = { 3838 /* MV88E6XXX_FAMILY_6320 */ 3839 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3840 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3841 .irl_init_all = mv88e6352_g2_irl_init_all, 3842 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3843 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3844 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3845 .phy_read = mv88e6xxx_g2_smi_phy_read, 3846 .phy_write = mv88e6xxx_g2_smi_phy_write, 3847 .port_set_link = mv88e6xxx_port_set_link, 3848 .port_set_duplex = mv88e6xxx_port_set_duplex, 3849 .port_set_speed = mv88e6185_port_set_speed, 3850 .port_tag_remap = mv88e6095_port_tag_remap, 3851 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3852 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3853 .port_set_ether_type = mv88e6351_port_set_ether_type, 3854 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3855 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3856 .port_pause_limit = mv88e6097_port_pause_limit, 3857 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3858 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3859 .port_link_state = mv88e6352_port_link_state, 3860 .port_get_cmode = mv88e6352_port_get_cmode, 3861 .port_setup_message_port = mv88e6xxx_setup_message_port, 3862 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3863 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3864 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3865 .stats_get_strings = mv88e6320_stats_get_strings, 3866 .stats_get_stats = mv88e6320_stats_get_stats, 3867 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3868 .set_egress_port = mv88e6095_g1_set_egress_port, 3869 .watchdog_ops = &mv88e6390_watchdog_ops, 3870 .reset = mv88e6352_g1_reset, 3871 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3872 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3873 .gpio_ops = &mv88e6352_gpio_ops, 3874 .avb_ops = &mv88e6352_avb_ops, 3875 .ptp_ops = &mv88e6352_ptp_ops, 3876 .phylink_validate = mv88e6185_phylink_validate, 3877 }; 3878 3879 static const struct mv88e6xxx_ops mv88e6341_ops = { 3880 /* MV88E6XXX_FAMILY_6341 */ 3881 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3882 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3883 .irl_init_all = mv88e6352_g2_irl_init_all, 3884 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3885 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3886 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3887 .phy_read = mv88e6xxx_g2_smi_phy_read, 3888 .phy_write = mv88e6xxx_g2_smi_phy_write, 3889 .port_set_link = mv88e6xxx_port_set_link, 3890 .port_set_duplex = mv88e6xxx_port_set_duplex, 3891 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3892 .port_set_speed = mv88e6341_port_set_speed, 3893 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3894 .port_tag_remap = mv88e6095_port_tag_remap, 3895 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3896 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3897 .port_set_ether_type = mv88e6351_port_set_ether_type, 3898 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3899 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3900 .port_pause_limit = mv88e6097_port_pause_limit, 3901 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3902 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3903 .port_link_state = mv88e6352_port_link_state, 3904 .port_get_cmode = mv88e6352_port_get_cmode, 3905 .port_set_cmode = mv88e6341_port_set_cmode, 3906 .port_setup_message_port = mv88e6xxx_setup_message_port, 3907 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3908 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3909 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3910 .stats_get_strings = mv88e6320_stats_get_strings, 3911 .stats_get_stats = mv88e6390_stats_get_stats, 3912 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3913 .set_egress_port = mv88e6390_g1_set_egress_port, 3914 .watchdog_ops = &mv88e6390_watchdog_ops, 3915 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3916 .pot_clear = mv88e6xxx_g2_pot_clear, 3917 .reset = mv88e6352_g1_reset, 3918 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3919 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3920 .serdes_power = mv88e6390_serdes_power, 3921 .serdes_get_lane = mv88e6341_serdes_get_lane, 3922 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3923 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3924 .serdes_irq_status = mv88e6390_serdes_irq_status, 3925 .gpio_ops = &mv88e6352_gpio_ops, 3926 .avb_ops = &mv88e6390_avb_ops, 3927 .ptp_ops = &mv88e6352_ptp_ops, 3928 .phylink_validate = mv88e6341_phylink_validate, 3929 }; 3930 3931 static const struct mv88e6xxx_ops mv88e6350_ops = { 3932 /* MV88E6XXX_FAMILY_6351 */ 3933 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3934 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3935 .irl_init_all = mv88e6352_g2_irl_init_all, 3936 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3937 .phy_read = mv88e6xxx_g2_smi_phy_read, 3938 .phy_write = mv88e6xxx_g2_smi_phy_write, 3939 .port_set_link = mv88e6xxx_port_set_link, 3940 .port_set_duplex = mv88e6xxx_port_set_duplex, 3941 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3942 .port_set_speed = mv88e6185_port_set_speed, 3943 .port_tag_remap = mv88e6095_port_tag_remap, 3944 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3945 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3946 .port_set_ether_type = mv88e6351_port_set_ether_type, 3947 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3948 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3949 .port_pause_limit = mv88e6097_port_pause_limit, 3950 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3951 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3952 .port_link_state = mv88e6352_port_link_state, 3953 .port_get_cmode = mv88e6352_port_get_cmode, 3954 .port_setup_message_port = mv88e6xxx_setup_message_port, 3955 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3956 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3957 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3958 .stats_get_strings = mv88e6095_stats_get_strings, 3959 .stats_get_stats = mv88e6095_stats_get_stats, 3960 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3961 .set_egress_port = mv88e6095_g1_set_egress_port, 3962 .watchdog_ops = &mv88e6097_watchdog_ops, 3963 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3964 .pot_clear = mv88e6xxx_g2_pot_clear, 3965 .reset = mv88e6352_g1_reset, 3966 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3967 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3968 .phylink_validate = mv88e6185_phylink_validate, 3969 }; 3970 3971 static const struct mv88e6xxx_ops mv88e6351_ops = { 3972 /* MV88E6XXX_FAMILY_6351 */ 3973 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3974 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3975 .irl_init_all = mv88e6352_g2_irl_init_all, 3976 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3977 .phy_read = mv88e6xxx_g2_smi_phy_read, 3978 .phy_write = mv88e6xxx_g2_smi_phy_write, 3979 .port_set_link = mv88e6xxx_port_set_link, 3980 .port_set_duplex = mv88e6xxx_port_set_duplex, 3981 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3982 .port_set_speed = mv88e6185_port_set_speed, 3983 .port_tag_remap = mv88e6095_port_tag_remap, 3984 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3985 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3986 .port_set_ether_type = mv88e6351_port_set_ether_type, 3987 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3988 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3989 .port_pause_limit = mv88e6097_port_pause_limit, 3990 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3991 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3992 .port_link_state = mv88e6352_port_link_state, 3993 .port_get_cmode = mv88e6352_port_get_cmode, 3994 .port_setup_message_port = mv88e6xxx_setup_message_port, 3995 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3996 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3997 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3998 .stats_get_strings = mv88e6095_stats_get_strings, 3999 .stats_get_stats = mv88e6095_stats_get_stats, 4000 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4001 .set_egress_port = mv88e6095_g1_set_egress_port, 4002 .watchdog_ops = &mv88e6097_watchdog_ops, 4003 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4004 .pot_clear = mv88e6xxx_g2_pot_clear, 4005 .reset = mv88e6352_g1_reset, 4006 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4007 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4008 .avb_ops = &mv88e6352_avb_ops, 4009 .ptp_ops = &mv88e6352_ptp_ops, 4010 .phylink_validate = mv88e6185_phylink_validate, 4011 }; 4012 4013 static const struct mv88e6xxx_ops mv88e6352_ops = { 4014 /* MV88E6XXX_FAMILY_6352 */ 4015 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4016 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4017 .irl_init_all = mv88e6352_g2_irl_init_all, 4018 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4019 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4020 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4021 .phy_read = mv88e6xxx_g2_smi_phy_read, 4022 .phy_write = mv88e6xxx_g2_smi_phy_write, 4023 .port_set_link = mv88e6xxx_port_set_link, 4024 .port_set_duplex = mv88e6xxx_port_set_duplex, 4025 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4026 .port_set_speed = mv88e6352_port_set_speed, 4027 .port_tag_remap = mv88e6095_port_tag_remap, 4028 .port_set_policy = mv88e6352_port_set_policy, 4029 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4030 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4031 .port_set_ether_type = mv88e6351_port_set_ether_type, 4032 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4033 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4034 .port_pause_limit = mv88e6097_port_pause_limit, 4035 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4036 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4037 .port_link_state = mv88e6352_port_link_state, 4038 .port_get_cmode = mv88e6352_port_get_cmode, 4039 .port_setup_message_port = mv88e6xxx_setup_message_port, 4040 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4041 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4042 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4043 .stats_get_strings = mv88e6095_stats_get_strings, 4044 .stats_get_stats = mv88e6095_stats_get_stats, 4045 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4046 .set_egress_port = mv88e6095_g1_set_egress_port, 4047 .watchdog_ops = &mv88e6097_watchdog_ops, 4048 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4049 .pot_clear = mv88e6xxx_g2_pot_clear, 4050 .reset = mv88e6352_g1_reset, 4051 .rmu_disable = mv88e6352_g1_rmu_disable, 4052 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4053 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4054 .serdes_get_lane = mv88e6352_serdes_get_lane, 4055 .serdes_power = mv88e6352_serdes_power, 4056 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4057 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4058 .serdes_irq_status = mv88e6352_serdes_irq_status, 4059 .gpio_ops = &mv88e6352_gpio_ops, 4060 .avb_ops = &mv88e6352_avb_ops, 4061 .ptp_ops = &mv88e6352_ptp_ops, 4062 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4063 .serdes_get_strings = mv88e6352_serdes_get_strings, 4064 .serdes_get_stats = mv88e6352_serdes_get_stats, 4065 .phylink_validate = mv88e6352_phylink_validate, 4066 }; 4067 4068 static const struct mv88e6xxx_ops mv88e6390_ops = { 4069 /* MV88E6XXX_FAMILY_6390 */ 4070 .setup_errata = mv88e6390_setup_errata, 4071 .irl_init_all = mv88e6390_g2_irl_init_all, 4072 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4073 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4074 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4075 .phy_read = mv88e6xxx_g2_smi_phy_read, 4076 .phy_write = mv88e6xxx_g2_smi_phy_write, 4077 .port_set_link = mv88e6xxx_port_set_link, 4078 .port_set_duplex = mv88e6xxx_port_set_duplex, 4079 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4080 .port_set_speed = mv88e6390_port_set_speed, 4081 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4082 .port_tag_remap = mv88e6390_port_tag_remap, 4083 .port_set_policy = mv88e6352_port_set_policy, 4084 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4085 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4086 .port_set_ether_type = mv88e6351_port_set_ether_type, 4087 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4088 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4089 .port_pause_limit = mv88e6390_port_pause_limit, 4090 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4091 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4092 .port_link_state = mv88e6352_port_link_state, 4093 .port_get_cmode = mv88e6352_port_get_cmode, 4094 .port_set_cmode = mv88e6390_port_set_cmode, 4095 .port_setup_message_port = mv88e6xxx_setup_message_port, 4096 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4097 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4098 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4099 .stats_get_strings = mv88e6320_stats_get_strings, 4100 .stats_get_stats = mv88e6390_stats_get_stats, 4101 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4102 .set_egress_port = mv88e6390_g1_set_egress_port, 4103 .watchdog_ops = &mv88e6390_watchdog_ops, 4104 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4105 .pot_clear = mv88e6xxx_g2_pot_clear, 4106 .reset = mv88e6352_g1_reset, 4107 .rmu_disable = mv88e6390_g1_rmu_disable, 4108 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4109 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4110 .serdes_power = mv88e6390_serdes_power, 4111 .serdes_get_lane = mv88e6390_serdes_get_lane, 4112 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4113 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4114 .serdes_irq_status = mv88e6390_serdes_irq_status, 4115 .gpio_ops = &mv88e6352_gpio_ops, 4116 .avb_ops = &mv88e6390_avb_ops, 4117 .ptp_ops = &mv88e6352_ptp_ops, 4118 .phylink_validate = mv88e6390_phylink_validate, 4119 }; 4120 4121 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4122 /* MV88E6XXX_FAMILY_6390 */ 4123 .setup_errata = mv88e6390_setup_errata, 4124 .irl_init_all = mv88e6390_g2_irl_init_all, 4125 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4126 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4127 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4128 .phy_read = mv88e6xxx_g2_smi_phy_read, 4129 .phy_write = mv88e6xxx_g2_smi_phy_write, 4130 .port_set_link = mv88e6xxx_port_set_link, 4131 .port_set_duplex = mv88e6xxx_port_set_duplex, 4132 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4133 .port_set_speed = mv88e6390x_port_set_speed, 4134 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4135 .port_tag_remap = mv88e6390_port_tag_remap, 4136 .port_set_policy = mv88e6352_port_set_policy, 4137 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4138 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 4139 .port_set_ether_type = mv88e6351_port_set_ether_type, 4140 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4141 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4142 .port_pause_limit = mv88e6390_port_pause_limit, 4143 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4144 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4145 .port_link_state = mv88e6352_port_link_state, 4146 .port_get_cmode = mv88e6352_port_get_cmode, 4147 .port_set_cmode = mv88e6390x_port_set_cmode, 4148 .port_setup_message_port = mv88e6xxx_setup_message_port, 4149 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4150 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4151 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4152 .stats_get_strings = mv88e6320_stats_get_strings, 4153 .stats_get_stats = mv88e6390_stats_get_stats, 4154 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4155 .set_egress_port = mv88e6390_g1_set_egress_port, 4156 .watchdog_ops = &mv88e6390_watchdog_ops, 4157 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4158 .pot_clear = mv88e6xxx_g2_pot_clear, 4159 .reset = mv88e6352_g1_reset, 4160 .rmu_disable = mv88e6390_g1_rmu_disable, 4161 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4162 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4163 .serdes_power = mv88e6390_serdes_power, 4164 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4165 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4166 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4167 .serdes_irq_status = mv88e6390_serdes_irq_status, 4168 .gpio_ops = &mv88e6352_gpio_ops, 4169 .avb_ops = &mv88e6390_avb_ops, 4170 .ptp_ops = &mv88e6352_ptp_ops, 4171 .phylink_validate = mv88e6390x_phylink_validate, 4172 }; 4173 4174 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4175 [MV88E6085] = { 4176 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4177 .family = MV88E6XXX_FAMILY_6097, 4178 .name = "Marvell 88E6085", 4179 .num_databases = 4096, 4180 .num_ports = 10, 4181 .num_internal_phys = 5, 4182 .max_vid = 4095, 4183 .port_base_addr = 0x10, 4184 .phy_base_addr = 0x0, 4185 .global1_addr = 0x1b, 4186 .global2_addr = 0x1c, 4187 .age_time_coeff = 15000, 4188 .g1_irqs = 8, 4189 .g2_irqs = 10, 4190 .atu_move_port_mask = 0xf, 4191 .pvt = true, 4192 .multi_chip = true, 4193 .tag_protocol = DSA_TAG_PROTO_DSA, 4194 .ops = &mv88e6085_ops, 4195 }, 4196 4197 [MV88E6095] = { 4198 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4199 .family = MV88E6XXX_FAMILY_6095, 4200 .name = "Marvell 88E6095/88E6095F", 4201 .num_databases = 256, 4202 .num_ports = 11, 4203 .num_internal_phys = 0, 4204 .max_vid = 4095, 4205 .port_base_addr = 0x10, 4206 .phy_base_addr = 0x0, 4207 .global1_addr = 0x1b, 4208 .global2_addr = 0x1c, 4209 .age_time_coeff = 15000, 4210 .g1_irqs = 8, 4211 .atu_move_port_mask = 0xf, 4212 .multi_chip = true, 4213 .tag_protocol = DSA_TAG_PROTO_DSA, 4214 .ops = &mv88e6095_ops, 4215 }, 4216 4217 [MV88E6097] = { 4218 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 4219 .family = MV88E6XXX_FAMILY_6097, 4220 .name = "Marvell 88E6097/88E6097F", 4221 .num_databases = 4096, 4222 .num_ports = 11, 4223 .num_internal_phys = 8, 4224 .max_vid = 4095, 4225 .port_base_addr = 0x10, 4226 .phy_base_addr = 0x0, 4227 .global1_addr = 0x1b, 4228 .global2_addr = 0x1c, 4229 .age_time_coeff = 15000, 4230 .g1_irqs = 8, 4231 .g2_irqs = 10, 4232 .atu_move_port_mask = 0xf, 4233 .pvt = true, 4234 .multi_chip = true, 4235 .tag_protocol = DSA_TAG_PROTO_EDSA, 4236 .ops = &mv88e6097_ops, 4237 }, 4238 4239 [MV88E6123] = { 4240 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 4241 .family = MV88E6XXX_FAMILY_6165, 4242 .name = "Marvell 88E6123", 4243 .num_databases = 4096, 4244 .num_ports = 3, 4245 .num_internal_phys = 5, 4246 .max_vid = 4095, 4247 .port_base_addr = 0x10, 4248 .phy_base_addr = 0x0, 4249 .global1_addr = 0x1b, 4250 .global2_addr = 0x1c, 4251 .age_time_coeff = 15000, 4252 .g1_irqs = 9, 4253 .g2_irqs = 10, 4254 .atu_move_port_mask = 0xf, 4255 .pvt = true, 4256 .multi_chip = true, 4257 .tag_protocol = DSA_TAG_PROTO_EDSA, 4258 .ops = &mv88e6123_ops, 4259 }, 4260 4261 [MV88E6131] = { 4262 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 4263 .family = MV88E6XXX_FAMILY_6185, 4264 .name = "Marvell 88E6131", 4265 .num_databases = 256, 4266 .num_ports = 8, 4267 .num_internal_phys = 0, 4268 .max_vid = 4095, 4269 .port_base_addr = 0x10, 4270 .phy_base_addr = 0x0, 4271 .global1_addr = 0x1b, 4272 .global2_addr = 0x1c, 4273 .age_time_coeff = 15000, 4274 .g1_irqs = 9, 4275 .atu_move_port_mask = 0xf, 4276 .multi_chip = true, 4277 .tag_protocol = DSA_TAG_PROTO_DSA, 4278 .ops = &mv88e6131_ops, 4279 }, 4280 4281 [MV88E6141] = { 4282 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 4283 .family = MV88E6XXX_FAMILY_6341, 4284 .name = "Marvell 88E6141", 4285 .num_databases = 4096, 4286 .num_ports = 6, 4287 .num_internal_phys = 5, 4288 .num_gpio = 11, 4289 .max_vid = 4095, 4290 .port_base_addr = 0x10, 4291 .phy_base_addr = 0x10, 4292 .global1_addr = 0x1b, 4293 .global2_addr = 0x1c, 4294 .age_time_coeff = 3750, 4295 .atu_move_port_mask = 0x1f, 4296 .g1_irqs = 9, 4297 .g2_irqs = 10, 4298 .pvt = true, 4299 .multi_chip = true, 4300 .tag_protocol = DSA_TAG_PROTO_EDSA, 4301 .ops = &mv88e6141_ops, 4302 }, 4303 4304 [MV88E6161] = { 4305 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 4306 .family = MV88E6XXX_FAMILY_6165, 4307 .name = "Marvell 88E6161", 4308 .num_databases = 4096, 4309 .num_ports = 6, 4310 .num_internal_phys = 5, 4311 .max_vid = 4095, 4312 .port_base_addr = 0x10, 4313 .phy_base_addr = 0x0, 4314 .global1_addr = 0x1b, 4315 .global2_addr = 0x1c, 4316 .age_time_coeff = 15000, 4317 .g1_irqs = 9, 4318 .g2_irqs = 10, 4319 .atu_move_port_mask = 0xf, 4320 .pvt = true, 4321 .multi_chip = true, 4322 .tag_protocol = DSA_TAG_PROTO_EDSA, 4323 .ptp_support = true, 4324 .ops = &mv88e6161_ops, 4325 }, 4326 4327 [MV88E6165] = { 4328 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 4329 .family = MV88E6XXX_FAMILY_6165, 4330 .name = "Marvell 88E6165", 4331 .num_databases = 4096, 4332 .num_ports = 6, 4333 .num_internal_phys = 0, 4334 .max_vid = 4095, 4335 .port_base_addr = 0x10, 4336 .phy_base_addr = 0x0, 4337 .global1_addr = 0x1b, 4338 .global2_addr = 0x1c, 4339 .age_time_coeff = 15000, 4340 .g1_irqs = 9, 4341 .g2_irqs = 10, 4342 .atu_move_port_mask = 0xf, 4343 .pvt = true, 4344 .multi_chip = true, 4345 .tag_protocol = DSA_TAG_PROTO_DSA, 4346 .ptp_support = true, 4347 .ops = &mv88e6165_ops, 4348 }, 4349 4350 [MV88E6171] = { 4351 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 4352 .family = MV88E6XXX_FAMILY_6351, 4353 .name = "Marvell 88E6171", 4354 .num_databases = 4096, 4355 .num_ports = 7, 4356 .num_internal_phys = 5, 4357 .max_vid = 4095, 4358 .port_base_addr = 0x10, 4359 .phy_base_addr = 0x0, 4360 .global1_addr = 0x1b, 4361 .global2_addr = 0x1c, 4362 .age_time_coeff = 15000, 4363 .g1_irqs = 9, 4364 .g2_irqs = 10, 4365 .atu_move_port_mask = 0xf, 4366 .pvt = true, 4367 .multi_chip = true, 4368 .tag_protocol = DSA_TAG_PROTO_EDSA, 4369 .ops = &mv88e6171_ops, 4370 }, 4371 4372 [MV88E6172] = { 4373 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 4374 .family = MV88E6XXX_FAMILY_6352, 4375 .name = "Marvell 88E6172", 4376 .num_databases = 4096, 4377 .num_ports = 7, 4378 .num_internal_phys = 5, 4379 .num_gpio = 15, 4380 .max_vid = 4095, 4381 .port_base_addr = 0x10, 4382 .phy_base_addr = 0x0, 4383 .global1_addr = 0x1b, 4384 .global2_addr = 0x1c, 4385 .age_time_coeff = 15000, 4386 .g1_irqs = 9, 4387 .g2_irqs = 10, 4388 .atu_move_port_mask = 0xf, 4389 .pvt = true, 4390 .multi_chip = true, 4391 .tag_protocol = DSA_TAG_PROTO_EDSA, 4392 .ops = &mv88e6172_ops, 4393 }, 4394 4395 [MV88E6175] = { 4396 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 4397 .family = MV88E6XXX_FAMILY_6351, 4398 .name = "Marvell 88E6175", 4399 .num_databases = 4096, 4400 .num_ports = 7, 4401 .num_internal_phys = 5, 4402 .max_vid = 4095, 4403 .port_base_addr = 0x10, 4404 .phy_base_addr = 0x0, 4405 .global1_addr = 0x1b, 4406 .global2_addr = 0x1c, 4407 .age_time_coeff = 15000, 4408 .g1_irqs = 9, 4409 .g2_irqs = 10, 4410 .atu_move_port_mask = 0xf, 4411 .pvt = true, 4412 .multi_chip = true, 4413 .tag_protocol = DSA_TAG_PROTO_EDSA, 4414 .ops = &mv88e6175_ops, 4415 }, 4416 4417 [MV88E6176] = { 4418 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 4419 .family = MV88E6XXX_FAMILY_6352, 4420 .name = "Marvell 88E6176", 4421 .num_databases = 4096, 4422 .num_ports = 7, 4423 .num_internal_phys = 5, 4424 .num_gpio = 15, 4425 .max_vid = 4095, 4426 .port_base_addr = 0x10, 4427 .phy_base_addr = 0x0, 4428 .global1_addr = 0x1b, 4429 .global2_addr = 0x1c, 4430 .age_time_coeff = 15000, 4431 .g1_irqs = 9, 4432 .g2_irqs = 10, 4433 .atu_move_port_mask = 0xf, 4434 .pvt = true, 4435 .multi_chip = true, 4436 .tag_protocol = DSA_TAG_PROTO_EDSA, 4437 .ops = &mv88e6176_ops, 4438 }, 4439 4440 [MV88E6185] = { 4441 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 4442 .family = MV88E6XXX_FAMILY_6185, 4443 .name = "Marvell 88E6185", 4444 .num_databases = 256, 4445 .num_ports = 10, 4446 .num_internal_phys = 0, 4447 .max_vid = 4095, 4448 .port_base_addr = 0x10, 4449 .phy_base_addr = 0x0, 4450 .global1_addr = 0x1b, 4451 .global2_addr = 0x1c, 4452 .age_time_coeff = 15000, 4453 .g1_irqs = 8, 4454 .atu_move_port_mask = 0xf, 4455 .multi_chip = true, 4456 .tag_protocol = DSA_TAG_PROTO_EDSA, 4457 .ops = &mv88e6185_ops, 4458 }, 4459 4460 [MV88E6190] = { 4461 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 4462 .family = MV88E6XXX_FAMILY_6390, 4463 .name = "Marvell 88E6190", 4464 .num_databases = 4096, 4465 .num_ports = 11, /* 10 + Z80 */ 4466 .num_internal_phys = 9, 4467 .num_gpio = 16, 4468 .max_vid = 8191, 4469 .port_base_addr = 0x0, 4470 .phy_base_addr = 0x0, 4471 .global1_addr = 0x1b, 4472 .global2_addr = 0x1c, 4473 .tag_protocol = DSA_TAG_PROTO_DSA, 4474 .age_time_coeff = 3750, 4475 .g1_irqs = 9, 4476 .g2_irqs = 14, 4477 .pvt = true, 4478 .multi_chip = true, 4479 .atu_move_port_mask = 0x1f, 4480 .ops = &mv88e6190_ops, 4481 }, 4482 4483 [MV88E6190X] = { 4484 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 4485 .family = MV88E6XXX_FAMILY_6390, 4486 .name = "Marvell 88E6190X", 4487 .num_databases = 4096, 4488 .num_ports = 11, /* 10 + Z80 */ 4489 .num_internal_phys = 9, 4490 .num_gpio = 16, 4491 .max_vid = 8191, 4492 .port_base_addr = 0x0, 4493 .phy_base_addr = 0x0, 4494 .global1_addr = 0x1b, 4495 .global2_addr = 0x1c, 4496 .age_time_coeff = 3750, 4497 .g1_irqs = 9, 4498 .g2_irqs = 14, 4499 .atu_move_port_mask = 0x1f, 4500 .pvt = true, 4501 .multi_chip = true, 4502 .tag_protocol = DSA_TAG_PROTO_DSA, 4503 .ops = &mv88e6190x_ops, 4504 }, 4505 4506 [MV88E6191] = { 4507 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 4508 .family = MV88E6XXX_FAMILY_6390, 4509 .name = "Marvell 88E6191", 4510 .num_databases = 4096, 4511 .num_ports = 11, /* 10 + Z80 */ 4512 .num_internal_phys = 9, 4513 .max_vid = 8191, 4514 .port_base_addr = 0x0, 4515 .phy_base_addr = 0x0, 4516 .global1_addr = 0x1b, 4517 .global2_addr = 0x1c, 4518 .age_time_coeff = 3750, 4519 .g1_irqs = 9, 4520 .g2_irqs = 14, 4521 .atu_move_port_mask = 0x1f, 4522 .pvt = true, 4523 .multi_chip = true, 4524 .tag_protocol = DSA_TAG_PROTO_DSA, 4525 .ptp_support = true, 4526 .ops = &mv88e6191_ops, 4527 }, 4528 4529 [MV88E6220] = { 4530 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 4531 .family = MV88E6XXX_FAMILY_6250, 4532 .name = "Marvell 88E6220", 4533 .num_databases = 64, 4534 4535 /* Ports 2-4 are not routed to pins 4536 * => usable ports 0, 1, 5, 6 4537 */ 4538 .num_ports = 7, 4539 .num_internal_phys = 2, 4540 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 4541 .max_vid = 4095, 4542 .port_base_addr = 0x08, 4543 .phy_base_addr = 0x00, 4544 .global1_addr = 0x0f, 4545 .global2_addr = 0x07, 4546 .age_time_coeff = 15000, 4547 .g1_irqs = 9, 4548 .g2_irqs = 10, 4549 .atu_move_port_mask = 0xf, 4550 .dual_chip = true, 4551 .tag_protocol = DSA_TAG_PROTO_DSA, 4552 .ptp_support = true, 4553 .ops = &mv88e6250_ops, 4554 }, 4555 4556 [MV88E6240] = { 4557 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 4558 .family = MV88E6XXX_FAMILY_6352, 4559 .name = "Marvell 88E6240", 4560 .num_databases = 4096, 4561 .num_ports = 7, 4562 .num_internal_phys = 5, 4563 .num_gpio = 15, 4564 .max_vid = 4095, 4565 .port_base_addr = 0x10, 4566 .phy_base_addr = 0x0, 4567 .global1_addr = 0x1b, 4568 .global2_addr = 0x1c, 4569 .age_time_coeff = 15000, 4570 .g1_irqs = 9, 4571 .g2_irqs = 10, 4572 .atu_move_port_mask = 0xf, 4573 .pvt = true, 4574 .multi_chip = true, 4575 .tag_protocol = DSA_TAG_PROTO_EDSA, 4576 .ptp_support = true, 4577 .ops = &mv88e6240_ops, 4578 }, 4579 4580 [MV88E6250] = { 4581 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 4582 .family = MV88E6XXX_FAMILY_6250, 4583 .name = "Marvell 88E6250", 4584 .num_databases = 64, 4585 .num_ports = 7, 4586 .num_internal_phys = 5, 4587 .max_vid = 4095, 4588 .port_base_addr = 0x08, 4589 .phy_base_addr = 0x00, 4590 .global1_addr = 0x0f, 4591 .global2_addr = 0x07, 4592 .age_time_coeff = 15000, 4593 .g1_irqs = 9, 4594 .g2_irqs = 10, 4595 .atu_move_port_mask = 0xf, 4596 .dual_chip = true, 4597 .tag_protocol = DSA_TAG_PROTO_DSA, 4598 .ptp_support = true, 4599 .ops = &mv88e6250_ops, 4600 }, 4601 4602 [MV88E6290] = { 4603 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 4604 .family = MV88E6XXX_FAMILY_6390, 4605 .name = "Marvell 88E6290", 4606 .num_databases = 4096, 4607 .num_ports = 11, /* 10 + Z80 */ 4608 .num_internal_phys = 9, 4609 .num_gpio = 16, 4610 .max_vid = 8191, 4611 .port_base_addr = 0x0, 4612 .phy_base_addr = 0x0, 4613 .global1_addr = 0x1b, 4614 .global2_addr = 0x1c, 4615 .age_time_coeff = 3750, 4616 .g1_irqs = 9, 4617 .g2_irqs = 14, 4618 .atu_move_port_mask = 0x1f, 4619 .pvt = true, 4620 .multi_chip = true, 4621 .tag_protocol = DSA_TAG_PROTO_DSA, 4622 .ptp_support = true, 4623 .ops = &mv88e6290_ops, 4624 }, 4625 4626 [MV88E6320] = { 4627 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 4628 .family = MV88E6XXX_FAMILY_6320, 4629 .name = "Marvell 88E6320", 4630 .num_databases = 4096, 4631 .num_ports = 7, 4632 .num_internal_phys = 5, 4633 .num_gpio = 15, 4634 .max_vid = 4095, 4635 .port_base_addr = 0x10, 4636 .phy_base_addr = 0x0, 4637 .global1_addr = 0x1b, 4638 .global2_addr = 0x1c, 4639 .age_time_coeff = 15000, 4640 .g1_irqs = 8, 4641 .g2_irqs = 10, 4642 .atu_move_port_mask = 0xf, 4643 .pvt = true, 4644 .multi_chip = true, 4645 .tag_protocol = DSA_TAG_PROTO_EDSA, 4646 .ptp_support = true, 4647 .ops = &mv88e6320_ops, 4648 }, 4649 4650 [MV88E6321] = { 4651 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 4652 .family = MV88E6XXX_FAMILY_6320, 4653 .name = "Marvell 88E6321", 4654 .num_databases = 4096, 4655 .num_ports = 7, 4656 .num_internal_phys = 5, 4657 .num_gpio = 15, 4658 .max_vid = 4095, 4659 .port_base_addr = 0x10, 4660 .phy_base_addr = 0x0, 4661 .global1_addr = 0x1b, 4662 .global2_addr = 0x1c, 4663 .age_time_coeff = 15000, 4664 .g1_irqs = 8, 4665 .g2_irqs = 10, 4666 .atu_move_port_mask = 0xf, 4667 .multi_chip = true, 4668 .tag_protocol = DSA_TAG_PROTO_EDSA, 4669 .ptp_support = true, 4670 .ops = &mv88e6321_ops, 4671 }, 4672 4673 [MV88E6341] = { 4674 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 4675 .family = MV88E6XXX_FAMILY_6341, 4676 .name = "Marvell 88E6341", 4677 .num_databases = 4096, 4678 .num_internal_phys = 5, 4679 .num_ports = 6, 4680 .num_gpio = 11, 4681 .max_vid = 4095, 4682 .port_base_addr = 0x10, 4683 .phy_base_addr = 0x10, 4684 .global1_addr = 0x1b, 4685 .global2_addr = 0x1c, 4686 .age_time_coeff = 3750, 4687 .atu_move_port_mask = 0x1f, 4688 .g1_irqs = 9, 4689 .g2_irqs = 10, 4690 .pvt = true, 4691 .multi_chip = true, 4692 .tag_protocol = DSA_TAG_PROTO_EDSA, 4693 .ptp_support = true, 4694 .ops = &mv88e6341_ops, 4695 }, 4696 4697 [MV88E6350] = { 4698 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 4699 .family = MV88E6XXX_FAMILY_6351, 4700 .name = "Marvell 88E6350", 4701 .num_databases = 4096, 4702 .num_ports = 7, 4703 .num_internal_phys = 5, 4704 .max_vid = 4095, 4705 .port_base_addr = 0x10, 4706 .phy_base_addr = 0x0, 4707 .global1_addr = 0x1b, 4708 .global2_addr = 0x1c, 4709 .age_time_coeff = 15000, 4710 .g1_irqs = 9, 4711 .g2_irqs = 10, 4712 .atu_move_port_mask = 0xf, 4713 .pvt = true, 4714 .multi_chip = true, 4715 .tag_protocol = DSA_TAG_PROTO_EDSA, 4716 .ops = &mv88e6350_ops, 4717 }, 4718 4719 [MV88E6351] = { 4720 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 4721 .family = MV88E6XXX_FAMILY_6351, 4722 .name = "Marvell 88E6351", 4723 .num_databases = 4096, 4724 .num_ports = 7, 4725 .num_internal_phys = 5, 4726 .max_vid = 4095, 4727 .port_base_addr = 0x10, 4728 .phy_base_addr = 0x0, 4729 .global1_addr = 0x1b, 4730 .global2_addr = 0x1c, 4731 .age_time_coeff = 15000, 4732 .g1_irqs = 9, 4733 .g2_irqs = 10, 4734 .atu_move_port_mask = 0xf, 4735 .pvt = true, 4736 .multi_chip = true, 4737 .tag_protocol = DSA_TAG_PROTO_EDSA, 4738 .ops = &mv88e6351_ops, 4739 }, 4740 4741 [MV88E6352] = { 4742 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 4743 .family = MV88E6XXX_FAMILY_6352, 4744 .name = "Marvell 88E6352", 4745 .num_databases = 4096, 4746 .num_ports = 7, 4747 .num_internal_phys = 5, 4748 .num_gpio = 15, 4749 .max_vid = 4095, 4750 .port_base_addr = 0x10, 4751 .phy_base_addr = 0x0, 4752 .global1_addr = 0x1b, 4753 .global2_addr = 0x1c, 4754 .age_time_coeff = 15000, 4755 .g1_irqs = 9, 4756 .g2_irqs = 10, 4757 .atu_move_port_mask = 0xf, 4758 .pvt = true, 4759 .multi_chip = true, 4760 .tag_protocol = DSA_TAG_PROTO_EDSA, 4761 .ptp_support = true, 4762 .ops = &mv88e6352_ops, 4763 }, 4764 [MV88E6390] = { 4765 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 4766 .family = MV88E6XXX_FAMILY_6390, 4767 .name = "Marvell 88E6390", 4768 .num_databases = 4096, 4769 .num_ports = 11, /* 10 + Z80 */ 4770 .num_internal_phys = 9, 4771 .num_gpio = 16, 4772 .max_vid = 8191, 4773 .port_base_addr = 0x0, 4774 .phy_base_addr = 0x0, 4775 .global1_addr = 0x1b, 4776 .global2_addr = 0x1c, 4777 .age_time_coeff = 3750, 4778 .g1_irqs = 9, 4779 .g2_irqs = 14, 4780 .atu_move_port_mask = 0x1f, 4781 .pvt = true, 4782 .multi_chip = true, 4783 .tag_protocol = DSA_TAG_PROTO_DSA, 4784 .ptp_support = true, 4785 .ops = &mv88e6390_ops, 4786 }, 4787 [MV88E6390X] = { 4788 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 4789 .family = MV88E6XXX_FAMILY_6390, 4790 .name = "Marvell 88E6390X", 4791 .num_databases = 4096, 4792 .num_ports = 11, /* 10 + Z80 */ 4793 .num_internal_phys = 9, 4794 .num_gpio = 16, 4795 .max_vid = 8191, 4796 .port_base_addr = 0x0, 4797 .phy_base_addr = 0x0, 4798 .global1_addr = 0x1b, 4799 .global2_addr = 0x1c, 4800 .age_time_coeff = 3750, 4801 .g1_irqs = 9, 4802 .g2_irqs = 14, 4803 .atu_move_port_mask = 0x1f, 4804 .pvt = true, 4805 .multi_chip = true, 4806 .tag_protocol = DSA_TAG_PROTO_DSA, 4807 .ptp_support = true, 4808 .ops = &mv88e6390x_ops, 4809 }, 4810 }; 4811 4812 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4813 { 4814 int i; 4815 4816 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4817 if (mv88e6xxx_table[i].prod_num == prod_num) 4818 return &mv88e6xxx_table[i]; 4819 4820 return NULL; 4821 } 4822 4823 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4824 { 4825 const struct mv88e6xxx_info *info; 4826 unsigned int prod_num, rev; 4827 u16 id; 4828 int err; 4829 4830 mv88e6xxx_reg_lock(chip); 4831 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 4832 mv88e6xxx_reg_unlock(chip); 4833 if (err) 4834 return err; 4835 4836 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 4837 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 4838 4839 info = mv88e6xxx_lookup_info(prod_num); 4840 if (!info) 4841 return -ENODEV; 4842 4843 /* Update the compatible info with the probed one */ 4844 chip->info = info; 4845 4846 err = mv88e6xxx_g2_require(chip); 4847 if (err) 4848 return err; 4849 4850 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4851 chip->info->prod_num, chip->info->name, rev); 4852 4853 return 0; 4854 } 4855 4856 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4857 { 4858 struct mv88e6xxx_chip *chip; 4859 4860 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4861 if (!chip) 4862 return NULL; 4863 4864 chip->dev = dev; 4865 4866 mutex_init(&chip->reg_lock); 4867 INIT_LIST_HEAD(&chip->mdios); 4868 idr_init(&chip->policies); 4869 4870 return chip; 4871 } 4872 4873 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 4874 int port) 4875 { 4876 struct mv88e6xxx_chip *chip = ds->priv; 4877 4878 return chip->info->tag_protocol; 4879 } 4880 4881 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4882 const struct switchdev_obj_port_mdb *mdb) 4883 { 4884 /* We don't need any dynamic resource from the kernel (yet), 4885 * so skip the prepare phase. 4886 */ 4887 4888 return 0; 4889 } 4890 4891 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4892 const struct switchdev_obj_port_mdb *mdb) 4893 { 4894 struct mv88e6xxx_chip *chip = ds->priv; 4895 4896 mv88e6xxx_reg_lock(chip); 4897 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4898 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 4899 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 4900 port); 4901 mv88e6xxx_reg_unlock(chip); 4902 } 4903 4904 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4905 const struct switchdev_obj_port_mdb *mdb) 4906 { 4907 struct mv88e6xxx_chip *chip = ds->priv; 4908 int err; 4909 4910 mv88e6xxx_reg_lock(chip); 4911 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 4912 mv88e6xxx_reg_unlock(chip); 4913 4914 return err; 4915 } 4916 4917 static int mv88e6xxx_port_egress_floods(struct dsa_switch *ds, int port, 4918 bool unicast, bool multicast) 4919 { 4920 struct mv88e6xxx_chip *chip = ds->priv; 4921 int err = -EOPNOTSUPP; 4922 4923 mv88e6xxx_reg_lock(chip); 4924 if (chip->info->ops->port_set_egress_floods) 4925 err = chip->info->ops->port_set_egress_floods(chip, port, 4926 unicast, 4927 multicast); 4928 mv88e6xxx_reg_unlock(chip); 4929 4930 return err; 4931 } 4932 4933 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4934 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4935 .setup = mv88e6xxx_setup, 4936 .phylink_validate = mv88e6xxx_validate, 4937 .phylink_mac_link_state = mv88e6xxx_link_state, 4938 .phylink_mac_config = mv88e6xxx_mac_config, 4939 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 4940 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 4941 .get_strings = mv88e6xxx_get_strings, 4942 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4943 .get_sset_count = mv88e6xxx_get_sset_count, 4944 .port_enable = mv88e6xxx_port_enable, 4945 .port_disable = mv88e6xxx_port_disable, 4946 .get_mac_eee = mv88e6xxx_get_mac_eee, 4947 .set_mac_eee = mv88e6xxx_set_mac_eee, 4948 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4949 .get_eeprom = mv88e6xxx_get_eeprom, 4950 .set_eeprom = mv88e6xxx_set_eeprom, 4951 .get_regs_len = mv88e6xxx_get_regs_len, 4952 .get_regs = mv88e6xxx_get_regs, 4953 .get_rxnfc = mv88e6xxx_get_rxnfc, 4954 .set_rxnfc = mv88e6xxx_set_rxnfc, 4955 .set_ageing_time = mv88e6xxx_set_ageing_time, 4956 .port_bridge_join = mv88e6xxx_port_bridge_join, 4957 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4958 .port_egress_floods = mv88e6xxx_port_egress_floods, 4959 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4960 .port_fast_age = mv88e6xxx_port_fast_age, 4961 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4962 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4963 .port_vlan_add = mv88e6xxx_port_vlan_add, 4964 .port_vlan_del = mv88e6xxx_port_vlan_del, 4965 .port_fdb_add = mv88e6xxx_port_fdb_add, 4966 .port_fdb_del = mv88e6xxx_port_fdb_del, 4967 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4968 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4969 .port_mdb_add = mv88e6xxx_port_mdb_add, 4970 .port_mdb_del = mv88e6xxx_port_mdb_del, 4971 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 4972 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 4973 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 4974 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 4975 .port_txtstamp = mv88e6xxx_port_txtstamp, 4976 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 4977 .get_ts_info = mv88e6xxx_get_ts_info, 4978 }; 4979 4980 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4981 { 4982 struct device *dev = chip->dev; 4983 struct dsa_switch *ds; 4984 4985 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 4986 if (!ds) 4987 return -ENOMEM; 4988 4989 ds->priv = chip; 4990 ds->dev = dev; 4991 ds->ops = &mv88e6xxx_switch_ops; 4992 ds->ageing_time_min = chip->info->age_time_coeff; 4993 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 4994 4995 dev_set_drvdata(dev, ds); 4996 4997 return dsa_register_switch(ds); 4998 } 4999 5000 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 5001 { 5002 dsa_unregister_switch(chip->ds); 5003 } 5004 5005 static const void *pdata_device_get_match_data(struct device *dev) 5006 { 5007 const struct of_device_id *matches = dev->driver->of_match_table; 5008 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 5009 5010 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 5011 matches++) { 5012 if (!strcmp(pdata->compatible, matches->compatible)) 5013 return matches->data; 5014 } 5015 return NULL; 5016 } 5017 5018 /* There is no suspend to RAM support at DSA level yet, the switch configuration 5019 * would be lost after a power cycle so prevent it to be suspended. 5020 */ 5021 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 5022 { 5023 return -EOPNOTSUPP; 5024 } 5025 5026 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 5027 { 5028 return 0; 5029 } 5030 5031 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 5032 5033 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 5034 { 5035 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 5036 const struct mv88e6xxx_info *compat_info = NULL; 5037 struct device *dev = &mdiodev->dev; 5038 struct device_node *np = dev->of_node; 5039 struct mv88e6xxx_chip *chip; 5040 int port; 5041 int err; 5042 5043 if (!np && !pdata) 5044 return -EINVAL; 5045 5046 if (np) 5047 compat_info = of_device_get_match_data(dev); 5048 5049 if (pdata) { 5050 compat_info = pdata_device_get_match_data(dev); 5051 5052 if (!pdata->netdev) 5053 return -EINVAL; 5054 5055 for (port = 0; port < DSA_MAX_PORTS; port++) { 5056 if (!(pdata->enabled_ports & (1 << port))) 5057 continue; 5058 if (strcmp(pdata->cd.port_names[port], "cpu")) 5059 continue; 5060 pdata->cd.netdev[port] = &pdata->netdev->dev; 5061 break; 5062 } 5063 } 5064 5065 if (!compat_info) 5066 return -EINVAL; 5067 5068 chip = mv88e6xxx_alloc_chip(dev); 5069 if (!chip) { 5070 err = -ENOMEM; 5071 goto out; 5072 } 5073 5074 chip->info = compat_info; 5075 5076 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 5077 if (err) 5078 goto out; 5079 5080 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 5081 if (IS_ERR(chip->reset)) { 5082 err = PTR_ERR(chip->reset); 5083 goto out; 5084 } 5085 if (chip->reset) 5086 usleep_range(1000, 2000); 5087 5088 err = mv88e6xxx_detect(chip); 5089 if (err) 5090 goto out; 5091 5092 mv88e6xxx_phy_init(chip); 5093 5094 if (chip->info->ops->get_eeprom) { 5095 if (np) 5096 of_property_read_u32(np, "eeprom-length", 5097 &chip->eeprom_len); 5098 else 5099 chip->eeprom_len = pdata->eeprom_len; 5100 } 5101 5102 mv88e6xxx_reg_lock(chip); 5103 err = mv88e6xxx_switch_reset(chip); 5104 mv88e6xxx_reg_unlock(chip); 5105 if (err) 5106 goto out; 5107 5108 if (np) { 5109 chip->irq = of_irq_get(np, 0); 5110 if (chip->irq == -EPROBE_DEFER) { 5111 err = chip->irq; 5112 goto out; 5113 } 5114 } 5115 5116 if (pdata) 5117 chip->irq = pdata->irq; 5118 5119 /* Has to be performed before the MDIO bus is created, because 5120 * the PHYs will link their interrupts to these interrupt 5121 * controllers 5122 */ 5123 mv88e6xxx_reg_lock(chip); 5124 if (chip->irq > 0) 5125 err = mv88e6xxx_g1_irq_setup(chip); 5126 else 5127 err = mv88e6xxx_irq_poll_setup(chip); 5128 mv88e6xxx_reg_unlock(chip); 5129 5130 if (err) 5131 goto out; 5132 5133 if (chip->info->g2_irqs > 0) { 5134 err = mv88e6xxx_g2_irq_setup(chip); 5135 if (err) 5136 goto out_g1_irq; 5137 } 5138 5139 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 5140 if (err) 5141 goto out_g2_irq; 5142 5143 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 5144 if (err) 5145 goto out_g1_atu_prob_irq; 5146 5147 err = mv88e6xxx_mdios_register(chip, np); 5148 if (err) 5149 goto out_g1_vtu_prob_irq; 5150 5151 err = mv88e6xxx_register_switch(chip); 5152 if (err) 5153 goto out_mdio; 5154 5155 return 0; 5156 5157 out_mdio: 5158 mv88e6xxx_mdios_unregister(chip); 5159 out_g1_vtu_prob_irq: 5160 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5161 out_g1_atu_prob_irq: 5162 mv88e6xxx_g1_atu_prob_irq_free(chip); 5163 out_g2_irq: 5164 if (chip->info->g2_irqs > 0) 5165 mv88e6xxx_g2_irq_free(chip); 5166 out_g1_irq: 5167 if (chip->irq > 0) 5168 mv88e6xxx_g1_irq_free(chip); 5169 else 5170 mv88e6xxx_irq_poll_free(chip); 5171 out: 5172 if (pdata) 5173 dev_put(pdata->netdev); 5174 5175 return err; 5176 } 5177 5178 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 5179 { 5180 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 5181 struct mv88e6xxx_chip *chip = ds->priv; 5182 5183 if (chip->info->ptp_support) { 5184 mv88e6xxx_hwtstamp_free(chip); 5185 mv88e6xxx_ptp_free(chip); 5186 } 5187 5188 mv88e6xxx_phy_destroy(chip); 5189 mv88e6xxx_unregister_switch(chip); 5190 mv88e6xxx_mdios_unregister(chip); 5191 5192 mv88e6xxx_g1_vtu_prob_irq_free(chip); 5193 mv88e6xxx_g1_atu_prob_irq_free(chip); 5194 5195 if (chip->info->g2_irqs > 0) 5196 mv88e6xxx_g2_irq_free(chip); 5197 5198 if (chip->irq > 0) 5199 mv88e6xxx_g1_irq_free(chip); 5200 else 5201 mv88e6xxx_irq_poll_free(chip); 5202 } 5203 5204 static const struct of_device_id mv88e6xxx_of_match[] = { 5205 { 5206 .compatible = "marvell,mv88e6085", 5207 .data = &mv88e6xxx_table[MV88E6085], 5208 }, 5209 { 5210 .compatible = "marvell,mv88e6190", 5211 .data = &mv88e6xxx_table[MV88E6190], 5212 }, 5213 { 5214 .compatible = "marvell,mv88e6250", 5215 .data = &mv88e6xxx_table[MV88E6250], 5216 }, 5217 { /* sentinel */ }, 5218 }; 5219 5220 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 5221 5222 static struct mdio_driver mv88e6xxx_driver = { 5223 .probe = mv88e6xxx_probe, 5224 .remove = mv88e6xxx_remove, 5225 .mdiodrv.driver = { 5226 .name = "mv88e6085", 5227 .of_match_table = mv88e6xxx_of_match, 5228 .pm = &mv88e6xxx_pm_ops, 5229 }, 5230 }; 5231 5232 mdio_module_driver(mv88e6xxx_driver); 5233 5234 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 5235 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 5236 MODULE_LICENSE("GPL"); 5237