1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121 } 122 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125 { 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128 } 129 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131 { 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140 } 141 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143 { 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148 } 149 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151 { 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159 { 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189 unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196 out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198 } 199 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201 { 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212 } 213 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215 { 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232 out: 233 mv88e6xxx_reg_unlock(chip); 234 } 235 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242 }; 243 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247 { 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255 } 256 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260 }; 261 262 /* To be called with reg_lock held */ 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264 { 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278 } 279 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281 { 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291 } 292 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294 { 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328 out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332 out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341 } 342 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344 { 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372 } 373 374 static void mv88e6xxx_irq_poll(struct kthread_work *work) 375 { 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 } 384 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386 { 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404 } 405 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407 { 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414 } 415 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418 { 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436 } 437 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441 { 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466 restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471 } 472 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474 { 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478 } 479 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481 { 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500 } 501 502 static const u8 mv88e6185_phy_interface_modes[] = { 503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 510 }; 511 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 513 struct phylink_config *config) 514 { 515 u8 cmode = chip->ports[port].cmode; 516 517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 518 519 if (mv88e6xxx_phy_is_internal(chip, port)) { 520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 521 } else { 522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 523 mv88e6185_phy_interface_modes[cmode]) 524 __set_bit(mv88e6185_phy_interface_modes[cmode], 525 config->supported_interfaces); 526 527 config->mac_capabilities |= MAC_1000FD; 528 } 529 } 530 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 532 struct phylink_config *config) 533 { 534 u8 cmode = chip->ports[port].cmode; 535 536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 537 mv88e6185_phy_interface_modes[cmode]) 538 __set_bit(mv88e6185_phy_interface_modes[cmode], 539 config->supported_interfaces); 540 541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 542 MAC_1000FD; 543 } 544 545 static const u8 mv88e6xxx_phy_interface_modes[] = { 546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 554 /* higher interface modes are not needed here, since ports supporting 555 * them are writable, and so the supported interfaces are filled in the 556 * corresponding .phylink_set_interfaces() implementation below 557 */ 558 }; 559 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 561 { 562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 563 mv88e6xxx_phy_interface_modes[cmode]) 564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 566 phy_interface_set_rgmii(supported); 567 } 568 569 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 570 struct phylink_config *config) 571 { 572 unsigned long *supported = config->supported_interfaces; 573 574 /* Translate the default cmode */ 575 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 576 577 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 578 } 579 580 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 581 { 582 u16 reg, val; 583 int err; 584 585 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 586 if (err) 587 return err; 588 589 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 590 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 591 return 0xf; 592 593 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 594 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 595 if (err) 596 return err; 597 598 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 599 if (err) 600 return err; 601 602 /* Restore PHY_DETECT value */ 603 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 604 if (err) 605 return err; 606 607 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 608 } 609 610 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 611 struct phylink_config *config) 612 { 613 unsigned long *supported = config->supported_interfaces; 614 int err, cmode; 615 616 /* Translate the default cmode */ 617 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 618 619 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 620 MAC_1000FD; 621 622 /* Port 4 supports automedia if the serdes is associated with it. */ 623 if (port == 4) { 624 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 625 if (err < 0) 626 dev_err(chip->dev, "p%d: failed to read scratch\n", 627 port); 628 if (err <= 0) 629 return; 630 631 cmode = mv88e6352_get_port4_serdes_cmode(chip); 632 if (cmode < 0) 633 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 634 port); 635 else 636 mv88e6xxx_translate_cmode(cmode, supported); 637 } 638 } 639 640 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 641 struct phylink_config *config) 642 { 643 unsigned long *supported = config->supported_interfaces; 644 645 /* Translate the default cmode */ 646 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 647 648 /* No ethtool bits for 200Mbps */ 649 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 650 MAC_1000FD; 651 652 /* The C_Mode field is programmable on port 5 */ 653 if (port == 5) { 654 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 655 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 656 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 657 658 config->mac_capabilities |= MAC_2500FD; 659 } 660 } 661 662 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 663 struct phylink_config *config) 664 { 665 unsigned long *supported = config->supported_interfaces; 666 667 /* Translate the default cmode */ 668 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 669 670 /* No ethtool bits for 200Mbps */ 671 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 672 MAC_1000FD; 673 674 /* The C_Mode field is programmable on ports 9 and 10 */ 675 if (port == 9 || port == 10) { 676 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 677 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 678 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 679 680 config->mac_capabilities |= MAC_2500FD; 681 } 682 } 683 684 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 685 struct phylink_config *config) 686 { 687 unsigned long *supported = config->supported_interfaces; 688 689 mv88e6390_phylink_get_caps(chip, port, config); 690 691 /* For the 6x90X, ports 2-7 can be in automedia mode. 692 * (Note that 6x90 doesn't support RXAUI nor XAUI). 693 * 694 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 695 * configured for 1000BASE-X, SGMII or 2500BASE-X. 696 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 697 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 698 * 699 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 700 * configured for 1000BASE-X, SGMII or 2500BASE-X. 701 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 702 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 703 * 704 * For now, be permissive (as the old code was) and allow 1000BASE-X 705 * on ports 2..7. 706 */ 707 if (port >= 2 && port <= 7) 708 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 709 710 /* The C_Mode field can also be programmed for 10G speeds */ 711 if (port == 9 || port == 10) { 712 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 713 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 714 715 config->mac_capabilities |= MAC_10000FD; 716 } 717 } 718 719 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 720 struct phylink_config *config) 721 { 722 unsigned long *supported = config->supported_interfaces; 723 bool is_6191x = 724 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 725 bool is_6361 = 726 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 727 728 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 729 730 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 731 MAC_1000FD; 732 733 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 734 if (port == 0 || port == 9 || port == 10) { 735 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 736 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 737 738 /* 6191X supports >1G modes only on port 10 */ 739 if (!is_6191x || port == 10) { 740 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 741 config->mac_capabilities |= MAC_2500FD; 742 743 /* 6361 only supports up to 2500BaseX */ 744 if (!is_6361) { 745 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 746 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 747 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 748 config->mac_capabilities |= MAC_5000FD | 749 MAC_10000FD; 750 } 751 } 752 } 753 754 if (port == 0) { 755 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 756 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 757 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 758 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 759 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 760 } 761 } 762 763 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 764 struct phylink_config *config) 765 { 766 struct mv88e6xxx_chip *chip = ds->priv; 767 768 mv88e6xxx_reg_lock(chip); 769 chip->info->ops->phylink_get_caps(chip, port, config); 770 mv88e6xxx_reg_unlock(chip); 771 772 if (mv88e6xxx_phy_is_internal(chip, port)) { 773 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 774 config->supported_interfaces); 775 /* Internal ports with no phy-mode need GMII for PHYLIB */ 776 __set_bit(PHY_INTERFACE_MODE_GMII, 777 config->supported_interfaces); 778 } 779 } 780 781 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds, 782 int port, 783 phy_interface_t interface) 784 { 785 struct mv88e6xxx_chip *chip = ds->priv; 786 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); 787 788 if (chip->info->ops->pcs_ops) 789 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port, 790 interface); 791 792 return pcs; 793 } 794 795 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 796 unsigned int mode, phy_interface_t interface) 797 { 798 struct mv88e6xxx_chip *chip = ds->priv; 799 int err = 0; 800 801 /* In inband mode, the link may come up at any time while the link 802 * is not forced down. Force the link down while we reconfigure the 803 * interface mode. 804 */ 805 if (mode == MLO_AN_INBAND && 806 chip->ports[port].interface != interface && 807 chip->info->ops->port_set_link) { 808 mv88e6xxx_reg_lock(chip); 809 err = chip->info->ops->port_set_link(chip, port, 810 LINK_FORCED_DOWN); 811 mv88e6xxx_reg_unlock(chip); 812 } 813 814 return err; 815 } 816 817 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 818 unsigned int mode, 819 const struct phylink_link_state *state) 820 { 821 struct mv88e6xxx_chip *chip = ds->priv; 822 int err = 0; 823 824 mv88e6xxx_reg_lock(chip); 825 826 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 827 err = mv88e6xxx_port_config_interface(chip, port, 828 state->interface); 829 if (err && err != -EOPNOTSUPP) 830 goto err_unlock; 831 } 832 833 err_unlock: 834 mv88e6xxx_reg_unlock(chip); 835 836 if (err && err != -EOPNOTSUPP) 837 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 838 } 839 840 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 841 unsigned int mode, phy_interface_t interface) 842 { 843 struct mv88e6xxx_chip *chip = ds->priv; 844 int err = 0; 845 846 /* Undo the forced down state above after completing configuration 847 * irrespective of its state on entry, which allows the link to come 848 * up in the in-band case where there is no separate SERDES. Also 849 * ensure that the link can come up if the PPU is in use and we are 850 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 851 */ 852 mv88e6xxx_reg_lock(chip); 853 854 if (chip->info->ops->port_set_link && 855 ((mode == MLO_AN_INBAND && 856 chip->ports[port].interface != interface) || 857 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 858 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 859 860 mv88e6xxx_reg_unlock(chip); 861 862 chip->ports[port].interface = interface; 863 864 return err; 865 } 866 867 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 868 unsigned int mode, 869 phy_interface_t interface) 870 { 871 struct mv88e6xxx_chip *chip = ds->priv; 872 const struct mv88e6xxx_ops *ops; 873 int err = 0; 874 875 ops = chip->info->ops; 876 877 mv88e6xxx_reg_lock(chip); 878 /* Force the link down if we know the port may not be automatically 879 * updated by the switch or if we are using fixed-link mode. 880 */ 881 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 882 mode == MLO_AN_FIXED) && ops->port_sync_link) 883 err = ops->port_sync_link(chip, port, mode, false); 884 885 if (!err && ops->port_set_speed_duplex) 886 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 887 DUPLEX_UNFORCED); 888 mv88e6xxx_reg_unlock(chip); 889 890 if (err) 891 dev_err(chip->dev, 892 "p%d: failed to force MAC link down\n", port); 893 } 894 895 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 896 unsigned int mode, phy_interface_t interface, 897 struct phy_device *phydev, 898 int speed, int duplex, 899 bool tx_pause, bool rx_pause) 900 { 901 struct mv88e6xxx_chip *chip = ds->priv; 902 const struct mv88e6xxx_ops *ops; 903 int err = 0; 904 905 ops = chip->info->ops; 906 907 mv88e6xxx_reg_lock(chip); 908 /* Configure and force the link up if we know that the port may not 909 * automatically updated by the switch or if we are using fixed-link 910 * mode. 911 */ 912 if (!mv88e6xxx_port_ppu_updates(chip, port) || 913 mode == MLO_AN_FIXED) { 914 if (ops->port_set_speed_duplex) { 915 err = ops->port_set_speed_duplex(chip, port, 916 speed, duplex); 917 if (err && err != -EOPNOTSUPP) 918 goto error; 919 } 920 921 if (ops->port_sync_link) 922 err = ops->port_sync_link(chip, port, mode, true); 923 } 924 error: 925 mv88e6xxx_reg_unlock(chip); 926 927 if (err && err != -EOPNOTSUPP) 928 dev_err(ds->dev, 929 "p%d: failed to configure MAC link up\n", port); 930 } 931 932 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 933 { 934 if (!chip->info->ops->stats_snapshot) 935 return -EOPNOTSUPP; 936 937 return chip->info->ops->stats_snapshot(chip, port); 938 } 939 940 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 941 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 942 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 943 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 944 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 945 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 946 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 947 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 948 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 949 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 950 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 951 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 952 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 953 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 954 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 955 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 956 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 957 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 958 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 959 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 960 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 961 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 962 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 963 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 964 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 965 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 966 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 967 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 968 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 969 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 970 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 971 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 972 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 973 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 974 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 975 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 976 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 977 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 978 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 979 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 980 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 981 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 982 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 983 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 984 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 985 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 986 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 987 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 988 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 989 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 990 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 991 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 992 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 993 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 994 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 995 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 996 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 997 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 998 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 999 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1000 }; 1001 1002 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1003 struct mv88e6xxx_hw_stat *s, 1004 int port, u16 bank1_select, 1005 u16 histogram) 1006 { 1007 u32 low; 1008 u32 high = 0; 1009 u16 reg = 0; 1010 int err; 1011 u64 value; 1012 1013 switch (s->type) { 1014 case STATS_TYPE_PORT: 1015 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1016 if (err) 1017 return U64_MAX; 1018 1019 low = reg; 1020 if (s->size == 4) { 1021 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1022 if (err) 1023 return U64_MAX; 1024 low |= ((u32)reg) << 16; 1025 } 1026 break; 1027 case STATS_TYPE_BANK1: 1028 reg = bank1_select; 1029 fallthrough; 1030 case STATS_TYPE_BANK0: 1031 reg |= s->reg | histogram; 1032 mv88e6xxx_g1_stats_read(chip, reg, &low); 1033 if (s->size == 8) 1034 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1035 break; 1036 default: 1037 return U64_MAX; 1038 } 1039 value = (((u64)high) << 32) | low; 1040 return value; 1041 } 1042 1043 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1044 uint8_t *data, int types) 1045 { 1046 struct mv88e6xxx_hw_stat *stat; 1047 int i, j; 1048 1049 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1050 stat = &mv88e6xxx_hw_stats[i]; 1051 if (stat->type & types) { 1052 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1053 ETH_GSTRING_LEN); 1054 j++; 1055 } 1056 } 1057 1058 return j; 1059 } 1060 1061 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1062 uint8_t *data) 1063 { 1064 return mv88e6xxx_stats_get_strings(chip, data, 1065 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1066 } 1067 1068 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1069 uint8_t *data) 1070 { 1071 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1072 } 1073 1074 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1075 uint8_t *data) 1076 { 1077 return mv88e6xxx_stats_get_strings(chip, data, 1078 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1079 } 1080 1081 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1082 "atu_member_violation", 1083 "atu_miss_violation", 1084 "atu_full_violation", 1085 "vtu_member_violation", 1086 "vtu_miss_violation", 1087 }; 1088 1089 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1090 { 1091 unsigned int i; 1092 1093 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1094 strscpy(data + i * ETH_GSTRING_LEN, 1095 mv88e6xxx_atu_vtu_stats_strings[i], 1096 ETH_GSTRING_LEN); 1097 } 1098 1099 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1100 u32 stringset, uint8_t *data) 1101 { 1102 struct mv88e6xxx_chip *chip = ds->priv; 1103 int count = 0; 1104 1105 if (stringset != ETH_SS_STATS) 1106 return; 1107 1108 mv88e6xxx_reg_lock(chip); 1109 1110 if (chip->info->ops->stats_get_strings) 1111 count = chip->info->ops->stats_get_strings(chip, data); 1112 1113 if (chip->info->ops->serdes_get_strings) { 1114 data += count * ETH_GSTRING_LEN; 1115 count = chip->info->ops->serdes_get_strings(chip, port, data); 1116 } 1117 1118 data += count * ETH_GSTRING_LEN; 1119 mv88e6xxx_atu_vtu_get_strings(data); 1120 1121 mv88e6xxx_reg_unlock(chip); 1122 } 1123 1124 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1125 int types) 1126 { 1127 struct mv88e6xxx_hw_stat *stat; 1128 int i, j; 1129 1130 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1131 stat = &mv88e6xxx_hw_stats[i]; 1132 if (stat->type & types) 1133 j++; 1134 } 1135 return j; 1136 } 1137 1138 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1139 { 1140 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1141 STATS_TYPE_PORT); 1142 } 1143 1144 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1145 { 1146 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1147 } 1148 1149 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1150 { 1151 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1152 STATS_TYPE_BANK1); 1153 } 1154 1155 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1156 { 1157 struct mv88e6xxx_chip *chip = ds->priv; 1158 int serdes_count = 0; 1159 int count = 0; 1160 1161 if (sset != ETH_SS_STATS) 1162 return 0; 1163 1164 mv88e6xxx_reg_lock(chip); 1165 if (chip->info->ops->stats_get_sset_count) 1166 count = chip->info->ops->stats_get_sset_count(chip); 1167 if (count < 0) 1168 goto out; 1169 1170 if (chip->info->ops->serdes_get_sset_count) 1171 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1172 port); 1173 if (serdes_count < 0) { 1174 count = serdes_count; 1175 goto out; 1176 } 1177 count += serdes_count; 1178 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1179 1180 out: 1181 mv88e6xxx_reg_unlock(chip); 1182 1183 return count; 1184 } 1185 1186 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1187 uint64_t *data, int types, 1188 u16 bank1_select, u16 histogram) 1189 { 1190 struct mv88e6xxx_hw_stat *stat; 1191 int i, j; 1192 1193 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1194 stat = &mv88e6xxx_hw_stats[i]; 1195 if (stat->type & types) { 1196 mv88e6xxx_reg_lock(chip); 1197 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1198 bank1_select, 1199 histogram); 1200 mv88e6xxx_reg_unlock(chip); 1201 1202 j++; 1203 } 1204 } 1205 return j; 1206 } 1207 1208 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1209 uint64_t *data) 1210 { 1211 return mv88e6xxx_stats_get_stats(chip, port, data, 1212 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1213 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1214 } 1215 1216 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1217 uint64_t *data) 1218 { 1219 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1220 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1221 } 1222 1223 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1224 uint64_t *data) 1225 { 1226 return mv88e6xxx_stats_get_stats(chip, port, data, 1227 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1228 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1229 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1230 } 1231 1232 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1233 uint64_t *data) 1234 { 1235 return mv88e6xxx_stats_get_stats(chip, port, data, 1236 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1237 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1238 0); 1239 } 1240 1241 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1242 uint64_t *data) 1243 { 1244 *data++ = chip->ports[port].atu_member_violation; 1245 *data++ = chip->ports[port].atu_miss_violation; 1246 *data++ = chip->ports[port].atu_full_violation; 1247 *data++ = chip->ports[port].vtu_member_violation; 1248 *data++ = chip->ports[port].vtu_miss_violation; 1249 } 1250 1251 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1252 uint64_t *data) 1253 { 1254 int count = 0; 1255 1256 if (chip->info->ops->stats_get_stats) 1257 count = chip->info->ops->stats_get_stats(chip, port, data); 1258 1259 mv88e6xxx_reg_lock(chip); 1260 if (chip->info->ops->serdes_get_stats) { 1261 data += count; 1262 count = chip->info->ops->serdes_get_stats(chip, port, data); 1263 } 1264 data += count; 1265 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1266 mv88e6xxx_reg_unlock(chip); 1267 } 1268 1269 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1270 uint64_t *data) 1271 { 1272 struct mv88e6xxx_chip *chip = ds->priv; 1273 int ret; 1274 1275 mv88e6xxx_reg_lock(chip); 1276 1277 ret = mv88e6xxx_stats_snapshot(chip, port); 1278 mv88e6xxx_reg_unlock(chip); 1279 1280 if (ret < 0) 1281 return; 1282 1283 mv88e6xxx_get_stats(chip, port, data); 1284 1285 } 1286 1287 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1288 { 1289 struct mv88e6xxx_chip *chip = ds->priv; 1290 int len; 1291 1292 len = 32 * sizeof(u16); 1293 if (chip->info->ops->serdes_get_regs_len) 1294 len += chip->info->ops->serdes_get_regs_len(chip, port); 1295 1296 return len; 1297 } 1298 1299 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1300 struct ethtool_regs *regs, void *_p) 1301 { 1302 struct mv88e6xxx_chip *chip = ds->priv; 1303 int err; 1304 u16 reg; 1305 u16 *p = _p; 1306 int i; 1307 1308 regs->version = chip->info->prod_num; 1309 1310 memset(p, 0xff, 32 * sizeof(u16)); 1311 1312 mv88e6xxx_reg_lock(chip); 1313 1314 for (i = 0; i < 32; i++) { 1315 1316 err = mv88e6xxx_port_read(chip, port, i, ®); 1317 if (!err) 1318 p[i] = reg; 1319 } 1320 1321 if (chip->info->ops->serdes_get_regs) 1322 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1323 1324 mv88e6xxx_reg_unlock(chip); 1325 } 1326 1327 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1328 struct ethtool_eee *e) 1329 { 1330 /* Nothing to do on the port's MAC */ 1331 return 0; 1332 } 1333 1334 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1335 struct ethtool_eee *e) 1336 { 1337 /* Nothing to do on the port's MAC */ 1338 return 0; 1339 } 1340 1341 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1342 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1343 { 1344 struct dsa_switch *ds = chip->ds; 1345 struct dsa_switch_tree *dst = ds->dst; 1346 struct dsa_port *dp, *other_dp; 1347 bool found = false; 1348 u16 pvlan; 1349 1350 /* dev is a physical switch */ 1351 if (dev <= dst->last_switch) { 1352 list_for_each_entry(dp, &dst->ports, list) { 1353 if (dp->ds->index == dev && dp->index == port) { 1354 /* dp might be a DSA link or a user port, so it 1355 * might or might not have a bridge. 1356 * Use the "found" variable for both cases. 1357 */ 1358 found = true; 1359 break; 1360 } 1361 } 1362 /* dev is a virtual bridge */ 1363 } else { 1364 list_for_each_entry(dp, &dst->ports, list) { 1365 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1366 1367 if (!bridge_num) 1368 continue; 1369 1370 if (bridge_num + dst->last_switch != dev) 1371 continue; 1372 1373 found = true; 1374 break; 1375 } 1376 } 1377 1378 /* Prevent frames from unknown switch or virtual bridge */ 1379 if (!found) 1380 return 0; 1381 1382 /* Frames from DSA links and CPU ports can egress any local port */ 1383 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1384 return mv88e6xxx_port_mask(chip); 1385 1386 pvlan = 0; 1387 1388 /* Frames from standalone user ports can only egress on the 1389 * upstream port. 1390 */ 1391 if (!dsa_port_bridge_dev_get(dp)) 1392 return BIT(dsa_switch_upstream_port(ds)); 1393 1394 /* Frames from bridged user ports can egress any local DSA 1395 * links and CPU ports, as well as any local member of their 1396 * bridge group. 1397 */ 1398 dsa_switch_for_each_port(other_dp, ds) 1399 if (other_dp->type == DSA_PORT_TYPE_CPU || 1400 other_dp->type == DSA_PORT_TYPE_DSA || 1401 dsa_port_bridge_same(dp, other_dp)) 1402 pvlan |= BIT(other_dp->index); 1403 1404 return pvlan; 1405 } 1406 1407 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1408 { 1409 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1410 1411 /* prevent frames from going back out of the port they came in on */ 1412 output_ports &= ~BIT(port); 1413 1414 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1415 } 1416 1417 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1418 u8 state) 1419 { 1420 struct mv88e6xxx_chip *chip = ds->priv; 1421 int err; 1422 1423 mv88e6xxx_reg_lock(chip); 1424 err = mv88e6xxx_port_set_state(chip, port, state); 1425 mv88e6xxx_reg_unlock(chip); 1426 1427 if (err) 1428 dev_err(ds->dev, "p%d: failed to update state\n", port); 1429 } 1430 1431 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1432 { 1433 int err; 1434 1435 if (chip->info->ops->ieee_pri_map) { 1436 err = chip->info->ops->ieee_pri_map(chip); 1437 if (err) 1438 return err; 1439 } 1440 1441 if (chip->info->ops->ip_pri_map) { 1442 err = chip->info->ops->ip_pri_map(chip); 1443 if (err) 1444 return err; 1445 } 1446 1447 return 0; 1448 } 1449 1450 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1451 { 1452 struct dsa_switch *ds = chip->ds; 1453 int target, port; 1454 int err; 1455 1456 if (!chip->info->global2_addr) 1457 return 0; 1458 1459 /* Initialize the routing port to the 32 possible target devices */ 1460 for (target = 0; target < 32; target++) { 1461 port = dsa_routing_port(ds, target); 1462 if (port == ds->num_ports) 1463 port = 0x1f; 1464 1465 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1466 if (err) 1467 return err; 1468 } 1469 1470 if (chip->info->ops->set_cascade_port) { 1471 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1472 err = chip->info->ops->set_cascade_port(chip, port); 1473 if (err) 1474 return err; 1475 } 1476 1477 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1478 if (err) 1479 return err; 1480 1481 return 0; 1482 } 1483 1484 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1485 { 1486 /* Clear all trunk masks and mapping */ 1487 if (chip->info->global2_addr) 1488 return mv88e6xxx_g2_trunk_clear(chip); 1489 1490 return 0; 1491 } 1492 1493 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1494 { 1495 if (chip->info->ops->rmu_disable) 1496 return chip->info->ops->rmu_disable(chip); 1497 1498 return 0; 1499 } 1500 1501 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1502 { 1503 if (chip->info->ops->pot_clear) 1504 return chip->info->ops->pot_clear(chip); 1505 1506 return 0; 1507 } 1508 1509 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1510 { 1511 if (chip->info->ops->mgmt_rsvd2cpu) 1512 return chip->info->ops->mgmt_rsvd2cpu(chip); 1513 1514 return 0; 1515 } 1516 1517 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1518 { 1519 int err; 1520 1521 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1522 if (err) 1523 return err; 1524 1525 /* The chips that have a "learn2all" bit in Global1, ATU 1526 * Control are precisely those whose port registers have a 1527 * Message Port bit in Port Control 1 and hence implement 1528 * ->port_setup_message_port. 1529 */ 1530 if (chip->info->ops->port_setup_message_port) { 1531 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1532 if (err) 1533 return err; 1534 } 1535 1536 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1537 } 1538 1539 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1540 { 1541 int port; 1542 int err; 1543 1544 if (!chip->info->ops->irl_init_all) 1545 return 0; 1546 1547 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1548 /* Disable ingress rate limiting by resetting all per port 1549 * ingress rate limit resources to their initial state. 1550 */ 1551 err = chip->info->ops->irl_init_all(chip, port); 1552 if (err) 1553 return err; 1554 } 1555 1556 return 0; 1557 } 1558 1559 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1560 { 1561 if (chip->info->ops->set_switch_mac) { 1562 u8 addr[ETH_ALEN]; 1563 1564 eth_random_addr(addr); 1565 1566 return chip->info->ops->set_switch_mac(chip, addr); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1573 { 1574 struct dsa_switch_tree *dst = chip->ds->dst; 1575 struct dsa_switch *ds; 1576 struct dsa_port *dp; 1577 u16 pvlan = 0; 1578 1579 if (!mv88e6xxx_has_pvt(chip)) 1580 return 0; 1581 1582 /* Skip the local source device, which uses in-chip port VLAN */ 1583 if (dev != chip->ds->index) { 1584 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1585 1586 ds = dsa_switch_find(dst->index, dev); 1587 dp = ds ? dsa_to_port(ds, port) : NULL; 1588 if (dp && dp->lag) { 1589 /* As the PVT is used to limit flooding of 1590 * FORWARD frames, which use the LAG ID as the 1591 * source port, we must translate dev/port to 1592 * the special "LAG device" in the PVT, using 1593 * the LAG ID (one-based) as the port number 1594 * (zero-based). 1595 */ 1596 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1597 port = dsa_port_lag_id_get(dp) - 1; 1598 } 1599 } 1600 1601 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1602 } 1603 1604 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1605 { 1606 int dev, port; 1607 int err; 1608 1609 if (!mv88e6xxx_has_pvt(chip)) 1610 return 0; 1611 1612 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1613 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1614 */ 1615 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1616 if (err) 1617 return err; 1618 1619 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1620 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1621 err = mv88e6xxx_pvt_map(chip, dev, port); 1622 if (err) 1623 return err; 1624 } 1625 } 1626 1627 return 0; 1628 } 1629 1630 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1631 u16 fid) 1632 { 1633 if (dsa_to_port(chip->ds, port)->lag) 1634 /* Hardware is incapable of fast-aging a LAG through a 1635 * regular ATU move operation. Until we have something 1636 * more fancy in place this is a no-op. 1637 */ 1638 return -EOPNOTSUPP; 1639 1640 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1641 } 1642 1643 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1644 { 1645 struct mv88e6xxx_chip *chip = ds->priv; 1646 int err; 1647 1648 mv88e6xxx_reg_lock(chip); 1649 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1650 mv88e6xxx_reg_unlock(chip); 1651 1652 if (err) 1653 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1654 port, err); 1655 } 1656 1657 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1658 { 1659 if (!mv88e6xxx_max_vid(chip)) 1660 return 0; 1661 1662 return mv88e6xxx_g1_vtu_flush(chip); 1663 } 1664 1665 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1666 struct mv88e6xxx_vtu_entry *entry) 1667 { 1668 int err; 1669 1670 if (!chip->info->ops->vtu_getnext) 1671 return -EOPNOTSUPP; 1672 1673 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1674 entry->valid = false; 1675 1676 err = chip->info->ops->vtu_getnext(chip, entry); 1677 1678 if (entry->vid != vid) 1679 entry->valid = false; 1680 1681 return err; 1682 } 1683 1684 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1685 int (*cb)(struct mv88e6xxx_chip *chip, 1686 const struct mv88e6xxx_vtu_entry *entry, 1687 void *priv), 1688 void *priv) 1689 { 1690 struct mv88e6xxx_vtu_entry entry = { 1691 .vid = mv88e6xxx_max_vid(chip), 1692 .valid = false, 1693 }; 1694 int err; 1695 1696 if (!chip->info->ops->vtu_getnext) 1697 return -EOPNOTSUPP; 1698 1699 do { 1700 err = chip->info->ops->vtu_getnext(chip, &entry); 1701 if (err) 1702 return err; 1703 1704 if (!entry.valid) 1705 break; 1706 1707 err = cb(chip, &entry, priv); 1708 if (err) 1709 return err; 1710 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1711 1712 return 0; 1713 } 1714 1715 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1716 struct mv88e6xxx_vtu_entry *entry) 1717 { 1718 if (!chip->info->ops->vtu_loadpurge) 1719 return -EOPNOTSUPP; 1720 1721 return chip->info->ops->vtu_loadpurge(chip, entry); 1722 } 1723 1724 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1725 const struct mv88e6xxx_vtu_entry *entry, 1726 void *_fid_bitmap) 1727 { 1728 unsigned long *fid_bitmap = _fid_bitmap; 1729 1730 set_bit(entry->fid, fid_bitmap); 1731 return 0; 1732 } 1733 1734 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1735 { 1736 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1737 1738 /* Every FID has an associated VID, so walking the VTU 1739 * will discover the full set of FIDs in use. 1740 */ 1741 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1742 } 1743 1744 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1745 { 1746 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1747 int err; 1748 1749 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1750 if (err) 1751 return err; 1752 1753 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1754 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1755 return -ENOSPC; 1756 1757 /* Clear the database */ 1758 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1759 } 1760 1761 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1762 struct mv88e6xxx_stu_entry *entry) 1763 { 1764 if (!chip->info->ops->stu_loadpurge) 1765 return -EOPNOTSUPP; 1766 1767 return chip->info->ops->stu_loadpurge(chip, entry); 1768 } 1769 1770 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1771 { 1772 struct mv88e6xxx_stu_entry stu = { 1773 .valid = true, 1774 .sid = 0 1775 }; 1776 1777 if (!mv88e6xxx_has_stu(chip)) 1778 return 0; 1779 1780 /* Make sure that SID 0 is always valid. This is used by VTU 1781 * entries that do not make use of the STU, e.g. when creating 1782 * a VLAN upper on a port that is also part of a VLAN 1783 * filtering bridge. 1784 */ 1785 return mv88e6xxx_stu_loadpurge(chip, &stu); 1786 } 1787 1788 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1789 { 1790 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1791 struct mv88e6xxx_mst *mst; 1792 1793 __set_bit(0, busy); 1794 1795 list_for_each_entry(mst, &chip->msts, node) 1796 __set_bit(mst->stu.sid, busy); 1797 1798 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1799 1800 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1801 } 1802 1803 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1804 { 1805 struct mv88e6xxx_mst *mst, *tmp; 1806 int err; 1807 1808 if (!sid) 1809 return 0; 1810 1811 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1812 if (mst->stu.sid != sid) 1813 continue; 1814 1815 if (!refcount_dec_and_test(&mst->refcnt)) 1816 return 0; 1817 1818 mst->stu.valid = false; 1819 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1820 if (err) { 1821 refcount_set(&mst->refcnt, 1); 1822 return err; 1823 } 1824 1825 list_del(&mst->node); 1826 kfree(mst); 1827 return 0; 1828 } 1829 1830 return -ENOENT; 1831 } 1832 1833 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1834 u16 msti, u8 *sid) 1835 { 1836 struct mv88e6xxx_mst *mst; 1837 int err, i; 1838 1839 if (!mv88e6xxx_has_stu(chip)) { 1840 err = -EOPNOTSUPP; 1841 goto err; 1842 } 1843 1844 if (!msti) { 1845 *sid = 0; 1846 return 0; 1847 } 1848 1849 list_for_each_entry(mst, &chip->msts, node) { 1850 if (mst->br == br && mst->msti == msti) { 1851 refcount_inc(&mst->refcnt); 1852 *sid = mst->stu.sid; 1853 return 0; 1854 } 1855 } 1856 1857 err = mv88e6xxx_sid_get(chip, sid); 1858 if (err) 1859 goto err; 1860 1861 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1862 if (!mst) { 1863 err = -ENOMEM; 1864 goto err; 1865 } 1866 1867 INIT_LIST_HEAD(&mst->node); 1868 refcount_set(&mst->refcnt, 1); 1869 mst->br = br; 1870 mst->msti = msti; 1871 mst->stu.valid = true; 1872 mst->stu.sid = *sid; 1873 1874 /* The bridge starts out all ports in the disabled state. But 1875 * a STU state of disabled means to go by the port-global 1876 * state. So we set all user port's initial state to blocking, 1877 * to match the bridge's behavior. 1878 */ 1879 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1880 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1881 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1882 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1883 1884 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1885 if (err) 1886 goto err_free; 1887 1888 list_add_tail(&mst->node, &chip->msts); 1889 return 0; 1890 1891 err_free: 1892 kfree(mst); 1893 err: 1894 return err; 1895 } 1896 1897 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1898 const struct switchdev_mst_state *st) 1899 { 1900 struct dsa_port *dp = dsa_to_port(ds, port); 1901 struct mv88e6xxx_chip *chip = ds->priv; 1902 struct mv88e6xxx_mst *mst; 1903 u8 state; 1904 int err; 1905 1906 if (!mv88e6xxx_has_stu(chip)) 1907 return -EOPNOTSUPP; 1908 1909 switch (st->state) { 1910 case BR_STATE_DISABLED: 1911 case BR_STATE_BLOCKING: 1912 case BR_STATE_LISTENING: 1913 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1914 break; 1915 case BR_STATE_LEARNING: 1916 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1917 break; 1918 case BR_STATE_FORWARDING: 1919 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1920 break; 1921 default: 1922 return -EINVAL; 1923 } 1924 1925 list_for_each_entry(mst, &chip->msts, node) { 1926 if (mst->br == dsa_port_bridge_dev_get(dp) && 1927 mst->msti == st->msti) { 1928 if (mst->stu.state[port] == state) 1929 return 0; 1930 1931 mst->stu.state[port] = state; 1932 mv88e6xxx_reg_lock(chip); 1933 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1934 mv88e6xxx_reg_unlock(chip); 1935 return err; 1936 } 1937 } 1938 1939 return -ENOENT; 1940 } 1941 1942 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1943 u16 vid) 1944 { 1945 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1946 struct mv88e6xxx_chip *chip = ds->priv; 1947 struct mv88e6xxx_vtu_entry vlan; 1948 int err; 1949 1950 /* DSA and CPU ports have to be members of multiple vlans */ 1951 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 1952 return 0; 1953 1954 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1955 if (err) 1956 return err; 1957 1958 if (!vlan.valid) 1959 return 0; 1960 1961 dsa_switch_for_each_user_port(other_dp, ds) { 1962 struct net_device *other_br; 1963 1964 if (vlan.member[other_dp->index] == 1965 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1966 continue; 1967 1968 if (dsa_port_bridge_same(dp, other_dp)) 1969 break; /* same bridge, check next VLAN */ 1970 1971 other_br = dsa_port_bridge_dev_get(other_dp); 1972 if (!other_br) 1973 continue; 1974 1975 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1976 port, vlan.vid, other_dp->index, netdev_name(other_br)); 1977 return -EOPNOTSUPP; 1978 } 1979 1980 return 0; 1981 } 1982 1983 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1984 { 1985 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1986 struct net_device *br = dsa_port_bridge_dev_get(dp); 1987 struct mv88e6xxx_port *p = &chip->ports[port]; 1988 u16 pvid = MV88E6XXX_VID_STANDALONE; 1989 bool drop_untagged = false; 1990 int err; 1991 1992 if (br) { 1993 if (br_vlan_enabled(br)) { 1994 pvid = p->bridge_pvid.vid; 1995 drop_untagged = !p->bridge_pvid.valid; 1996 } else { 1997 pvid = MV88E6XXX_VID_BRIDGED; 1998 } 1999 } 2000 2001 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2002 if (err) 2003 return err; 2004 2005 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2006 } 2007 2008 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2009 bool vlan_filtering, 2010 struct netlink_ext_ack *extack) 2011 { 2012 struct mv88e6xxx_chip *chip = ds->priv; 2013 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2014 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2015 int err; 2016 2017 if (!mv88e6xxx_max_vid(chip)) 2018 return -EOPNOTSUPP; 2019 2020 mv88e6xxx_reg_lock(chip); 2021 2022 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2023 if (err) 2024 goto unlock; 2025 2026 err = mv88e6xxx_port_commit_pvid(chip, port); 2027 if (err) 2028 goto unlock; 2029 2030 unlock: 2031 mv88e6xxx_reg_unlock(chip); 2032 2033 return err; 2034 } 2035 2036 static int 2037 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2038 const struct switchdev_obj_port_vlan *vlan) 2039 { 2040 struct mv88e6xxx_chip *chip = ds->priv; 2041 int err; 2042 2043 if (!mv88e6xxx_max_vid(chip)) 2044 return -EOPNOTSUPP; 2045 2046 /* If the requested port doesn't belong to the same bridge as the VLAN 2047 * members, do not support it (yet) and fallback to software VLAN. 2048 */ 2049 mv88e6xxx_reg_lock(chip); 2050 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2051 mv88e6xxx_reg_unlock(chip); 2052 2053 return err; 2054 } 2055 2056 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2057 const unsigned char *addr, u16 vid, 2058 u8 state) 2059 { 2060 struct mv88e6xxx_atu_entry entry; 2061 struct mv88e6xxx_vtu_entry vlan; 2062 u16 fid; 2063 int err; 2064 2065 /* Ports have two private address databases: one for when the port is 2066 * standalone and one for when the port is under a bridge and the 2067 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2068 * address database to remain 100% empty, so we never load an ATU entry 2069 * into a standalone port's database. Therefore, translate the null 2070 * VLAN ID into the port's database used for VLAN-unaware bridging. 2071 */ 2072 if (vid == 0) { 2073 fid = MV88E6XXX_FID_BRIDGED; 2074 } else { 2075 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2076 if (err) 2077 return err; 2078 2079 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2080 if (!vlan.valid) 2081 return -EOPNOTSUPP; 2082 2083 fid = vlan.fid; 2084 } 2085 2086 entry.state = 0; 2087 ether_addr_copy(entry.mac, addr); 2088 eth_addr_dec(entry.mac); 2089 2090 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2091 if (err) 2092 return err; 2093 2094 /* Initialize a fresh ATU entry if it isn't found */ 2095 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2096 memset(&entry, 0, sizeof(entry)); 2097 ether_addr_copy(entry.mac, addr); 2098 } 2099 2100 /* Purge the ATU entry only if no port is using it anymore */ 2101 if (!state) { 2102 entry.portvec &= ~BIT(port); 2103 if (!entry.portvec) 2104 entry.state = 0; 2105 } else { 2106 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2107 entry.portvec = BIT(port); 2108 else 2109 entry.portvec |= BIT(port); 2110 2111 entry.state = state; 2112 } 2113 2114 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2115 } 2116 2117 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2118 const struct mv88e6xxx_policy *policy) 2119 { 2120 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2121 enum mv88e6xxx_policy_action action = policy->action; 2122 const u8 *addr = policy->addr; 2123 u16 vid = policy->vid; 2124 u8 state; 2125 int err; 2126 int id; 2127 2128 if (!chip->info->ops->port_set_policy) 2129 return -EOPNOTSUPP; 2130 2131 switch (mapping) { 2132 case MV88E6XXX_POLICY_MAPPING_DA: 2133 case MV88E6XXX_POLICY_MAPPING_SA: 2134 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2135 state = 0; /* Dissociate the port and address */ 2136 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2137 is_multicast_ether_addr(addr)) 2138 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2139 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2140 is_unicast_ether_addr(addr)) 2141 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2142 else 2143 return -EOPNOTSUPP; 2144 2145 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2146 state); 2147 if (err) 2148 return err; 2149 break; 2150 default: 2151 return -EOPNOTSUPP; 2152 } 2153 2154 /* Skip the port's policy clearing if the mapping is still in use */ 2155 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2156 idr_for_each_entry(&chip->policies, policy, id) 2157 if (policy->port == port && 2158 policy->mapping == mapping && 2159 policy->action != action) 2160 return 0; 2161 2162 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2163 } 2164 2165 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2166 struct ethtool_rx_flow_spec *fs) 2167 { 2168 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2169 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2170 enum mv88e6xxx_policy_mapping mapping; 2171 enum mv88e6xxx_policy_action action; 2172 struct mv88e6xxx_policy *policy; 2173 u16 vid = 0; 2174 u8 *addr; 2175 int err; 2176 int id; 2177 2178 if (fs->location != RX_CLS_LOC_ANY) 2179 return -EINVAL; 2180 2181 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2182 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2183 else 2184 return -EOPNOTSUPP; 2185 2186 switch (fs->flow_type & ~FLOW_EXT) { 2187 case ETHER_FLOW: 2188 if (!is_zero_ether_addr(mac_mask->h_dest) && 2189 is_zero_ether_addr(mac_mask->h_source)) { 2190 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2191 addr = mac_entry->h_dest; 2192 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2193 !is_zero_ether_addr(mac_mask->h_source)) { 2194 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2195 addr = mac_entry->h_source; 2196 } else { 2197 /* Cannot support DA and SA mapping in the same rule */ 2198 return -EOPNOTSUPP; 2199 } 2200 break; 2201 default: 2202 return -EOPNOTSUPP; 2203 } 2204 2205 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2206 if (fs->m_ext.vlan_tci != htons(0xffff)) 2207 return -EOPNOTSUPP; 2208 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2209 } 2210 2211 idr_for_each_entry(&chip->policies, policy, id) { 2212 if (policy->port == port && policy->mapping == mapping && 2213 policy->action == action && policy->vid == vid && 2214 ether_addr_equal(policy->addr, addr)) 2215 return -EEXIST; 2216 } 2217 2218 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2219 if (!policy) 2220 return -ENOMEM; 2221 2222 fs->location = 0; 2223 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2224 GFP_KERNEL); 2225 if (err) { 2226 devm_kfree(chip->dev, policy); 2227 return err; 2228 } 2229 2230 memcpy(&policy->fs, fs, sizeof(*fs)); 2231 ether_addr_copy(policy->addr, addr); 2232 policy->mapping = mapping; 2233 policy->action = action; 2234 policy->port = port; 2235 policy->vid = vid; 2236 2237 err = mv88e6xxx_policy_apply(chip, port, policy); 2238 if (err) { 2239 idr_remove(&chip->policies, fs->location); 2240 devm_kfree(chip->dev, policy); 2241 return err; 2242 } 2243 2244 return 0; 2245 } 2246 2247 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2248 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2249 { 2250 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2251 struct mv88e6xxx_chip *chip = ds->priv; 2252 struct mv88e6xxx_policy *policy; 2253 int err; 2254 int id; 2255 2256 mv88e6xxx_reg_lock(chip); 2257 2258 switch (rxnfc->cmd) { 2259 case ETHTOOL_GRXCLSRLCNT: 2260 rxnfc->data = 0; 2261 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2262 rxnfc->rule_cnt = 0; 2263 idr_for_each_entry(&chip->policies, policy, id) 2264 if (policy->port == port) 2265 rxnfc->rule_cnt++; 2266 err = 0; 2267 break; 2268 case ETHTOOL_GRXCLSRULE: 2269 err = -ENOENT; 2270 policy = idr_find(&chip->policies, fs->location); 2271 if (policy) { 2272 memcpy(fs, &policy->fs, sizeof(*fs)); 2273 err = 0; 2274 } 2275 break; 2276 case ETHTOOL_GRXCLSRLALL: 2277 rxnfc->data = 0; 2278 rxnfc->rule_cnt = 0; 2279 idr_for_each_entry(&chip->policies, policy, id) 2280 if (policy->port == port) 2281 rule_locs[rxnfc->rule_cnt++] = id; 2282 err = 0; 2283 break; 2284 default: 2285 err = -EOPNOTSUPP; 2286 break; 2287 } 2288 2289 mv88e6xxx_reg_unlock(chip); 2290 2291 return err; 2292 } 2293 2294 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2295 struct ethtool_rxnfc *rxnfc) 2296 { 2297 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2298 struct mv88e6xxx_chip *chip = ds->priv; 2299 struct mv88e6xxx_policy *policy; 2300 int err; 2301 2302 mv88e6xxx_reg_lock(chip); 2303 2304 switch (rxnfc->cmd) { 2305 case ETHTOOL_SRXCLSRLINS: 2306 err = mv88e6xxx_policy_insert(chip, port, fs); 2307 break; 2308 case ETHTOOL_SRXCLSRLDEL: 2309 err = -ENOENT; 2310 policy = idr_remove(&chip->policies, fs->location); 2311 if (policy) { 2312 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2313 err = mv88e6xxx_policy_apply(chip, port, policy); 2314 devm_kfree(chip->dev, policy); 2315 } 2316 break; 2317 default: 2318 err = -EOPNOTSUPP; 2319 break; 2320 } 2321 2322 mv88e6xxx_reg_unlock(chip); 2323 2324 return err; 2325 } 2326 2327 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2328 u16 vid) 2329 { 2330 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2331 u8 broadcast[ETH_ALEN]; 2332 2333 eth_broadcast_addr(broadcast); 2334 2335 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2336 } 2337 2338 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2339 { 2340 int port; 2341 int err; 2342 2343 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2344 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2345 struct net_device *brport; 2346 2347 if (dsa_is_unused_port(chip->ds, port)) 2348 continue; 2349 2350 brport = dsa_port_to_bridge_port(dp); 2351 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2352 /* Skip bridged user ports where broadcast 2353 * flooding is disabled. 2354 */ 2355 continue; 2356 2357 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2358 if (err) 2359 return err; 2360 } 2361 2362 return 0; 2363 } 2364 2365 struct mv88e6xxx_port_broadcast_sync_ctx { 2366 int port; 2367 bool flood; 2368 }; 2369 2370 static int 2371 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2372 const struct mv88e6xxx_vtu_entry *vlan, 2373 void *_ctx) 2374 { 2375 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2376 u8 broadcast[ETH_ALEN]; 2377 u8 state; 2378 2379 if (ctx->flood) 2380 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2381 else 2382 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2383 2384 eth_broadcast_addr(broadcast); 2385 2386 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2387 vlan->vid, state); 2388 } 2389 2390 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2391 bool flood) 2392 { 2393 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2394 .port = port, 2395 .flood = flood, 2396 }; 2397 struct mv88e6xxx_vtu_entry vid0 = { 2398 .vid = 0, 2399 }; 2400 int err; 2401 2402 /* Update the port's private database... */ 2403 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2404 if (err) 2405 return err; 2406 2407 /* ...and the database for all VLANs. */ 2408 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2409 &ctx); 2410 } 2411 2412 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2413 u16 vid, u8 member, bool warn) 2414 { 2415 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2416 struct mv88e6xxx_vtu_entry vlan; 2417 int i, err; 2418 2419 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2420 if (err) 2421 return err; 2422 2423 if (!vlan.valid) { 2424 memset(&vlan, 0, sizeof(vlan)); 2425 2426 if (vid == MV88E6XXX_VID_STANDALONE) 2427 vlan.policy = true; 2428 2429 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2430 if (err) 2431 return err; 2432 2433 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2434 if (i == port) 2435 vlan.member[i] = member; 2436 else 2437 vlan.member[i] = non_member; 2438 2439 vlan.vid = vid; 2440 vlan.valid = true; 2441 2442 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2443 if (err) 2444 return err; 2445 2446 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2447 if (err) 2448 return err; 2449 } else if (vlan.member[port] != member) { 2450 vlan.member[port] = member; 2451 2452 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2453 if (err) 2454 return err; 2455 } else if (warn) { 2456 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2457 port, vid); 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2464 const struct switchdev_obj_port_vlan *vlan, 2465 struct netlink_ext_ack *extack) 2466 { 2467 struct mv88e6xxx_chip *chip = ds->priv; 2468 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2469 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2470 struct mv88e6xxx_port *p = &chip->ports[port]; 2471 bool warn; 2472 u8 member; 2473 int err; 2474 2475 if (!vlan->vid) 2476 return 0; 2477 2478 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2479 if (err) 2480 return err; 2481 2482 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2483 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2484 else if (untagged) 2485 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2486 else 2487 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2488 2489 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2490 * and then the CPU port. Do not warn for duplicates for the CPU port. 2491 */ 2492 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2493 2494 mv88e6xxx_reg_lock(chip); 2495 2496 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2497 if (err) { 2498 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2499 vlan->vid, untagged ? 'u' : 't'); 2500 goto out; 2501 } 2502 2503 if (pvid) { 2504 p->bridge_pvid.vid = vlan->vid; 2505 p->bridge_pvid.valid = true; 2506 2507 err = mv88e6xxx_port_commit_pvid(chip, port); 2508 if (err) 2509 goto out; 2510 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2511 /* The old pvid was reinstalled as a non-pvid VLAN */ 2512 p->bridge_pvid.valid = false; 2513 2514 err = mv88e6xxx_port_commit_pvid(chip, port); 2515 if (err) 2516 goto out; 2517 } 2518 2519 out: 2520 mv88e6xxx_reg_unlock(chip); 2521 2522 return err; 2523 } 2524 2525 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2526 int port, u16 vid) 2527 { 2528 struct mv88e6xxx_vtu_entry vlan; 2529 int i, err; 2530 2531 if (!vid) 2532 return 0; 2533 2534 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2535 if (err) 2536 return err; 2537 2538 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2539 * tell switchdev that this VLAN is likely handled in software. 2540 */ 2541 if (!vlan.valid || 2542 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2543 return -EOPNOTSUPP; 2544 2545 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2546 2547 /* keep the VLAN unless all ports are excluded */ 2548 vlan.valid = false; 2549 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2550 if (vlan.member[i] != 2551 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2552 vlan.valid = true; 2553 break; 2554 } 2555 } 2556 2557 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2558 if (err) 2559 return err; 2560 2561 if (!vlan.valid) { 2562 err = mv88e6xxx_mst_put(chip, vlan.sid); 2563 if (err) 2564 return err; 2565 } 2566 2567 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2568 } 2569 2570 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2571 const struct switchdev_obj_port_vlan *vlan) 2572 { 2573 struct mv88e6xxx_chip *chip = ds->priv; 2574 struct mv88e6xxx_port *p = &chip->ports[port]; 2575 int err = 0; 2576 u16 pvid; 2577 2578 if (!mv88e6xxx_max_vid(chip)) 2579 return -EOPNOTSUPP; 2580 2581 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2582 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2583 * switchdev workqueue to ensure that all FDB entries are deleted 2584 * before we remove the VLAN. 2585 */ 2586 dsa_flush_workqueue(); 2587 2588 mv88e6xxx_reg_lock(chip); 2589 2590 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2591 if (err) 2592 goto unlock; 2593 2594 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2595 if (err) 2596 goto unlock; 2597 2598 if (vlan->vid == pvid) { 2599 p->bridge_pvid.valid = false; 2600 2601 err = mv88e6xxx_port_commit_pvid(chip, port); 2602 if (err) 2603 goto unlock; 2604 } 2605 2606 unlock: 2607 mv88e6xxx_reg_unlock(chip); 2608 2609 return err; 2610 } 2611 2612 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2613 { 2614 struct mv88e6xxx_chip *chip = ds->priv; 2615 struct mv88e6xxx_vtu_entry vlan; 2616 int err; 2617 2618 mv88e6xxx_reg_lock(chip); 2619 2620 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2621 if (err) 2622 goto unlock; 2623 2624 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2625 2626 unlock: 2627 mv88e6xxx_reg_unlock(chip); 2628 2629 return err; 2630 } 2631 2632 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2633 struct dsa_bridge bridge, 2634 const struct switchdev_vlan_msti *msti) 2635 { 2636 struct mv88e6xxx_chip *chip = ds->priv; 2637 struct mv88e6xxx_vtu_entry vlan; 2638 u8 old_sid, new_sid; 2639 int err; 2640 2641 if (!mv88e6xxx_has_stu(chip)) 2642 return -EOPNOTSUPP; 2643 2644 mv88e6xxx_reg_lock(chip); 2645 2646 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2647 if (err) 2648 goto unlock; 2649 2650 if (!vlan.valid) { 2651 err = -EINVAL; 2652 goto unlock; 2653 } 2654 2655 old_sid = vlan.sid; 2656 2657 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2658 if (err) 2659 goto unlock; 2660 2661 if (new_sid != old_sid) { 2662 vlan.sid = new_sid; 2663 2664 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2665 if (err) { 2666 mv88e6xxx_mst_put(chip, new_sid); 2667 goto unlock; 2668 } 2669 } 2670 2671 err = mv88e6xxx_mst_put(chip, old_sid); 2672 2673 unlock: 2674 mv88e6xxx_reg_unlock(chip); 2675 return err; 2676 } 2677 2678 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2679 const unsigned char *addr, u16 vid, 2680 struct dsa_db db) 2681 { 2682 struct mv88e6xxx_chip *chip = ds->priv; 2683 int err; 2684 2685 mv88e6xxx_reg_lock(chip); 2686 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2687 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2688 mv88e6xxx_reg_unlock(chip); 2689 2690 return err; 2691 } 2692 2693 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2694 const unsigned char *addr, u16 vid, 2695 struct dsa_db db) 2696 { 2697 struct mv88e6xxx_chip *chip = ds->priv; 2698 int err; 2699 2700 mv88e6xxx_reg_lock(chip); 2701 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2702 mv88e6xxx_reg_unlock(chip); 2703 2704 return err; 2705 } 2706 2707 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2708 u16 fid, u16 vid, int port, 2709 dsa_fdb_dump_cb_t *cb, void *data) 2710 { 2711 struct mv88e6xxx_atu_entry addr; 2712 bool is_static; 2713 int err; 2714 2715 addr.state = 0; 2716 eth_broadcast_addr(addr.mac); 2717 2718 do { 2719 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2720 if (err) 2721 return err; 2722 2723 if (!addr.state) 2724 break; 2725 2726 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2727 continue; 2728 2729 if (!is_unicast_ether_addr(addr.mac)) 2730 continue; 2731 2732 is_static = (addr.state == 2733 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2734 err = cb(addr.mac, vid, is_static, data); 2735 if (err) 2736 return err; 2737 } while (!is_broadcast_ether_addr(addr.mac)); 2738 2739 return err; 2740 } 2741 2742 struct mv88e6xxx_port_db_dump_vlan_ctx { 2743 int port; 2744 dsa_fdb_dump_cb_t *cb; 2745 void *data; 2746 }; 2747 2748 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2749 const struct mv88e6xxx_vtu_entry *entry, 2750 void *_data) 2751 { 2752 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2753 2754 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2755 ctx->port, ctx->cb, ctx->data); 2756 } 2757 2758 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2759 dsa_fdb_dump_cb_t *cb, void *data) 2760 { 2761 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2762 .port = port, 2763 .cb = cb, 2764 .data = data, 2765 }; 2766 u16 fid; 2767 int err; 2768 2769 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2770 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2771 if (err) 2772 return err; 2773 2774 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2775 if (err) 2776 return err; 2777 2778 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2779 } 2780 2781 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2782 dsa_fdb_dump_cb_t *cb, void *data) 2783 { 2784 struct mv88e6xxx_chip *chip = ds->priv; 2785 int err; 2786 2787 mv88e6xxx_reg_lock(chip); 2788 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2789 mv88e6xxx_reg_unlock(chip); 2790 2791 return err; 2792 } 2793 2794 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2795 struct dsa_bridge bridge) 2796 { 2797 struct dsa_switch *ds = chip->ds; 2798 struct dsa_switch_tree *dst = ds->dst; 2799 struct dsa_port *dp; 2800 int err; 2801 2802 list_for_each_entry(dp, &dst->ports, list) { 2803 if (dsa_port_offloads_bridge(dp, &bridge)) { 2804 if (dp->ds == ds) { 2805 /* This is a local bridge group member, 2806 * remap its Port VLAN Map. 2807 */ 2808 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2809 if (err) 2810 return err; 2811 } else { 2812 /* This is an external bridge group member, 2813 * remap its cross-chip Port VLAN Table entry. 2814 */ 2815 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2816 dp->index); 2817 if (err) 2818 return err; 2819 } 2820 } 2821 } 2822 2823 return 0; 2824 } 2825 2826 /* Treat the software bridge as a virtual single-port switch behind the 2827 * CPU and map in the PVT. First dst->last_switch elements are taken by 2828 * physical switches, so start from beyond that range. 2829 */ 2830 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2831 unsigned int bridge_num) 2832 { 2833 u8 dev = bridge_num + ds->dst->last_switch; 2834 struct mv88e6xxx_chip *chip = ds->priv; 2835 2836 return mv88e6xxx_pvt_map(chip, dev, 0); 2837 } 2838 2839 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2840 struct dsa_bridge bridge, 2841 bool *tx_fwd_offload, 2842 struct netlink_ext_ack *extack) 2843 { 2844 struct mv88e6xxx_chip *chip = ds->priv; 2845 int err; 2846 2847 mv88e6xxx_reg_lock(chip); 2848 2849 err = mv88e6xxx_bridge_map(chip, bridge); 2850 if (err) 2851 goto unlock; 2852 2853 err = mv88e6xxx_port_set_map_da(chip, port, true); 2854 if (err) 2855 goto unlock; 2856 2857 err = mv88e6xxx_port_commit_pvid(chip, port); 2858 if (err) 2859 goto unlock; 2860 2861 if (mv88e6xxx_has_pvt(chip)) { 2862 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2863 if (err) 2864 goto unlock; 2865 2866 *tx_fwd_offload = true; 2867 } 2868 2869 unlock: 2870 mv88e6xxx_reg_unlock(chip); 2871 2872 return err; 2873 } 2874 2875 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2876 struct dsa_bridge bridge) 2877 { 2878 struct mv88e6xxx_chip *chip = ds->priv; 2879 int err; 2880 2881 mv88e6xxx_reg_lock(chip); 2882 2883 if (bridge.tx_fwd_offload && 2884 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2885 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2886 2887 if (mv88e6xxx_bridge_map(chip, bridge) || 2888 mv88e6xxx_port_vlan_map(chip, port)) 2889 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2890 2891 err = mv88e6xxx_port_set_map_da(chip, port, false); 2892 if (err) 2893 dev_err(ds->dev, 2894 "port %d failed to restore map-DA: %pe\n", 2895 port, ERR_PTR(err)); 2896 2897 err = mv88e6xxx_port_commit_pvid(chip, port); 2898 if (err) 2899 dev_err(ds->dev, 2900 "port %d failed to restore standalone pvid: %pe\n", 2901 port, ERR_PTR(err)); 2902 2903 mv88e6xxx_reg_unlock(chip); 2904 } 2905 2906 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2907 int tree_index, int sw_index, 2908 int port, struct dsa_bridge bridge, 2909 struct netlink_ext_ack *extack) 2910 { 2911 struct mv88e6xxx_chip *chip = ds->priv; 2912 int err; 2913 2914 if (tree_index != ds->dst->index) 2915 return 0; 2916 2917 mv88e6xxx_reg_lock(chip); 2918 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2919 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2920 mv88e6xxx_reg_unlock(chip); 2921 2922 return err; 2923 } 2924 2925 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2926 int tree_index, int sw_index, 2927 int port, struct dsa_bridge bridge) 2928 { 2929 struct mv88e6xxx_chip *chip = ds->priv; 2930 2931 if (tree_index != ds->dst->index) 2932 return; 2933 2934 mv88e6xxx_reg_lock(chip); 2935 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2936 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2937 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2938 mv88e6xxx_reg_unlock(chip); 2939 } 2940 2941 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2942 { 2943 if (chip->info->ops->reset) 2944 return chip->info->ops->reset(chip); 2945 2946 return 0; 2947 } 2948 2949 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2950 { 2951 struct gpio_desc *gpiod = chip->reset; 2952 2953 /* If there is a GPIO connected to the reset pin, toggle it */ 2954 if (gpiod) { 2955 gpiod_set_value_cansleep(gpiod, 1); 2956 usleep_range(10000, 20000); 2957 gpiod_set_value_cansleep(gpiod, 0); 2958 usleep_range(10000, 20000); 2959 2960 mv88e6xxx_g1_wait_eeprom_done(chip); 2961 } 2962 } 2963 2964 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2965 { 2966 int i, err; 2967 2968 /* Set all ports to the Disabled state */ 2969 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2970 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2971 if (err) 2972 return err; 2973 } 2974 2975 /* Wait for transmit queues to drain, 2976 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2977 */ 2978 usleep_range(2000, 4000); 2979 2980 return 0; 2981 } 2982 2983 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2984 { 2985 int err; 2986 2987 err = mv88e6xxx_disable_ports(chip); 2988 if (err) 2989 return err; 2990 2991 mv88e6xxx_hardware_reset(chip); 2992 2993 return mv88e6xxx_software_reset(chip); 2994 } 2995 2996 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2997 enum mv88e6xxx_frame_mode frame, 2998 enum mv88e6xxx_egress_mode egress, u16 etype) 2999 { 3000 int err; 3001 3002 if (!chip->info->ops->port_set_frame_mode) 3003 return -EOPNOTSUPP; 3004 3005 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3006 if (err) 3007 return err; 3008 3009 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3010 if (err) 3011 return err; 3012 3013 if (chip->info->ops->port_set_ether_type) 3014 return chip->info->ops->port_set_ether_type(chip, port, etype); 3015 3016 return 0; 3017 } 3018 3019 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3020 { 3021 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3022 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3023 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3024 } 3025 3026 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3027 { 3028 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3029 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3030 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3031 } 3032 3033 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3034 { 3035 return mv88e6xxx_set_port_mode(chip, port, 3036 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3037 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3038 ETH_P_EDSA); 3039 } 3040 3041 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3042 { 3043 if (dsa_is_dsa_port(chip->ds, port)) 3044 return mv88e6xxx_set_port_mode_dsa(chip, port); 3045 3046 if (dsa_is_user_port(chip->ds, port)) 3047 return mv88e6xxx_set_port_mode_normal(chip, port); 3048 3049 /* Setup CPU port mode depending on its supported tag format */ 3050 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3051 return mv88e6xxx_set_port_mode_dsa(chip, port); 3052 3053 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3054 return mv88e6xxx_set_port_mode_edsa(chip, port); 3055 3056 return -EINVAL; 3057 } 3058 3059 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3060 { 3061 bool message = dsa_is_dsa_port(chip->ds, port); 3062 3063 return mv88e6xxx_port_set_message_port(chip, port, message); 3064 } 3065 3066 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3067 { 3068 int err; 3069 3070 if (chip->info->ops->port_set_ucast_flood) { 3071 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3072 if (err) 3073 return err; 3074 } 3075 if (chip->info->ops->port_set_mcast_flood) { 3076 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3077 if (err) 3078 return err; 3079 } 3080 3081 return 0; 3082 } 3083 3084 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3085 enum mv88e6xxx_egress_direction direction, 3086 int port) 3087 { 3088 int err; 3089 3090 if (!chip->info->ops->set_egress_port) 3091 return -EOPNOTSUPP; 3092 3093 err = chip->info->ops->set_egress_port(chip, direction, port); 3094 if (err) 3095 return err; 3096 3097 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3098 chip->ingress_dest_port = port; 3099 else 3100 chip->egress_dest_port = port; 3101 3102 return 0; 3103 } 3104 3105 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3106 { 3107 struct dsa_switch *ds = chip->ds; 3108 int upstream_port; 3109 int err; 3110 3111 upstream_port = dsa_upstream_port(ds, port); 3112 if (chip->info->ops->port_set_upstream_port) { 3113 err = chip->info->ops->port_set_upstream_port(chip, port, 3114 upstream_port); 3115 if (err) 3116 return err; 3117 } 3118 3119 if (port == upstream_port) { 3120 if (chip->info->ops->set_cpu_port) { 3121 err = chip->info->ops->set_cpu_port(chip, 3122 upstream_port); 3123 if (err) 3124 return err; 3125 } 3126 3127 err = mv88e6xxx_set_egress_port(chip, 3128 MV88E6XXX_EGRESS_DIR_INGRESS, 3129 upstream_port); 3130 if (err && err != -EOPNOTSUPP) 3131 return err; 3132 3133 err = mv88e6xxx_set_egress_port(chip, 3134 MV88E6XXX_EGRESS_DIR_EGRESS, 3135 upstream_port); 3136 if (err && err != -EOPNOTSUPP) 3137 return err; 3138 } 3139 3140 return 0; 3141 } 3142 3143 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3144 { 3145 struct device_node *phy_handle = NULL; 3146 struct dsa_switch *ds = chip->ds; 3147 struct dsa_port *dp; 3148 int tx_amp; 3149 int err; 3150 u16 reg; 3151 3152 chip->ports[port].chip = chip; 3153 chip->ports[port].port = port; 3154 3155 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3156 SPEED_UNFORCED, DUPLEX_UNFORCED, 3157 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3158 if (err) 3159 return err; 3160 3161 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3162 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3163 * tunneling, determine priority by looking at 802.1p and IP 3164 * priority fields (IP prio has precedence), and set STP state 3165 * to Forwarding. 3166 * 3167 * If this is the CPU link, use DSA or EDSA tagging depending 3168 * on which tagging mode was configured. 3169 * 3170 * If this is a link to another switch, use DSA tagging mode. 3171 * 3172 * If this is the upstream port for this switch, enable 3173 * forwarding of unknown unicasts and multicasts. 3174 */ 3175 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3176 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3177 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3178 * by a USER port to the CPU port to allow snooping. 3179 */ 3180 if (dsa_is_user_port(ds, port)) 3181 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3182 3183 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3184 if (err) 3185 return err; 3186 3187 err = mv88e6xxx_setup_port_mode(chip, port); 3188 if (err) 3189 return err; 3190 3191 err = mv88e6xxx_setup_egress_floods(chip, port); 3192 if (err) 3193 return err; 3194 3195 /* Port Control 2: don't force a good FCS, set the MTU size to 3196 * 10222 bytes, disable 802.1q tags checking, don't discard 3197 * tagged or untagged frames on this port, skip destination 3198 * address lookup on user ports, disable ARP mirroring and don't 3199 * send a copy of all transmitted/received frames on this port 3200 * to the CPU. 3201 */ 3202 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3203 if (err) 3204 return err; 3205 3206 err = mv88e6xxx_setup_upstream_port(chip, port); 3207 if (err) 3208 return err; 3209 3210 /* On chips that support it, set all downstream DSA ports' 3211 * VLAN policy to TRAP. In combination with loading 3212 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3213 * provides a better isolation barrier between standalone 3214 * ports, as the ATU is bypassed on any intermediate switches 3215 * between the incoming port and the CPU. 3216 */ 3217 if (dsa_is_downstream_port(ds, port) && 3218 chip->info->ops->port_set_policy) { 3219 err = chip->info->ops->port_set_policy(chip, port, 3220 MV88E6XXX_POLICY_MAPPING_VTU, 3221 MV88E6XXX_POLICY_ACTION_TRAP); 3222 if (err) 3223 return err; 3224 } 3225 3226 /* User ports start out in standalone mode and 802.1Q is 3227 * therefore disabled. On DSA ports, all valid VIDs are always 3228 * loaded in the VTU - therefore, enable 802.1Q in order to take 3229 * advantage of VLAN policy on chips that supports it. 3230 */ 3231 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3232 dsa_is_user_port(ds, port) ? 3233 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3234 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3235 if (err) 3236 return err; 3237 3238 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3239 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3240 * the first free FID. This will be used as the private PVID for 3241 * unbridged ports. Shared (DSA and CPU) ports must also be 3242 * members of this VID, in order to trap all frames assigned to 3243 * it to the CPU. 3244 */ 3245 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3246 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3247 false); 3248 if (err) 3249 return err; 3250 3251 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3252 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3253 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3254 * as the private PVID on ports under a VLAN-unaware bridge. 3255 * Shared (DSA and CPU) ports must also be members of it, to translate 3256 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3257 * relying on their port default FID. 3258 */ 3259 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3260 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3261 false); 3262 if (err) 3263 return err; 3264 3265 if (chip->info->ops->port_set_jumbo_size) { 3266 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3267 if (err) 3268 return err; 3269 } 3270 3271 /* Port Association Vector: disable automatic address learning 3272 * on all user ports since they start out in standalone 3273 * mode. When joining a bridge, learning will be configured to 3274 * match the bridge port settings. Enable learning on all 3275 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3276 * learning process. 3277 * 3278 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3279 * and RefreshLocked. I.e. setup standard automatic learning. 3280 */ 3281 if (dsa_is_user_port(ds, port)) 3282 reg = 0; 3283 else 3284 reg = 1 << port; 3285 3286 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3287 reg); 3288 if (err) 3289 return err; 3290 3291 /* Egress rate control 2: disable egress rate control. */ 3292 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3293 0x0000); 3294 if (err) 3295 return err; 3296 3297 if (chip->info->ops->port_pause_limit) { 3298 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3299 if (err) 3300 return err; 3301 } 3302 3303 if (chip->info->ops->port_disable_learn_limit) { 3304 err = chip->info->ops->port_disable_learn_limit(chip, port); 3305 if (err) 3306 return err; 3307 } 3308 3309 if (chip->info->ops->port_disable_pri_override) { 3310 err = chip->info->ops->port_disable_pri_override(chip, port); 3311 if (err) 3312 return err; 3313 } 3314 3315 if (chip->info->ops->port_tag_remap) { 3316 err = chip->info->ops->port_tag_remap(chip, port); 3317 if (err) 3318 return err; 3319 } 3320 3321 if (chip->info->ops->port_egress_rate_limiting) { 3322 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3323 if (err) 3324 return err; 3325 } 3326 3327 if (chip->info->ops->port_setup_message_port) { 3328 err = chip->info->ops->port_setup_message_port(chip, port); 3329 if (err) 3330 return err; 3331 } 3332 3333 if (chip->info->ops->serdes_set_tx_amplitude) { 3334 dp = dsa_to_port(ds, port); 3335 if (dp) 3336 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3337 3338 if (phy_handle && !of_property_read_u32(phy_handle, 3339 "tx-p2p-microvolt", 3340 &tx_amp)) 3341 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3342 port, tx_amp); 3343 if (phy_handle) { 3344 of_node_put(phy_handle); 3345 if (err) 3346 return err; 3347 } 3348 } 3349 3350 /* Port based VLAN map: give each port the same default address 3351 * database, and allow bidirectional communication between the 3352 * CPU and DSA port(s), and the other ports. 3353 */ 3354 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3355 if (err) 3356 return err; 3357 3358 err = mv88e6xxx_port_vlan_map(chip, port); 3359 if (err) 3360 return err; 3361 3362 /* Default VLAN ID and priority: don't set a default VLAN 3363 * ID, and set the default packet priority to zero. 3364 */ 3365 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3366 } 3367 3368 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3369 { 3370 struct mv88e6xxx_chip *chip = ds->priv; 3371 3372 if (chip->info->ops->port_set_jumbo_size) 3373 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3374 else if (chip->info->ops->set_max_frame_size) 3375 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3376 return ETH_DATA_LEN; 3377 } 3378 3379 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3380 { 3381 struct mv88e6xxx_chip *chip = ds->priv; 3382 int ret = 0; 3383 3384 /* For families where we don't know how to alter the MTU, 3385 * just accept any value up to ETH_DATA_LEN 3386 */ 3387 if (!chip->info->ops->port_set_jumbo_size && 3388 !chip->info->ops->set_max_frame_size) { 3389 if (new_mtu > ETH_DATA_LEN) 3390 return -EINVAL; 3391 3392 return 0; 3393 } 3394 3395 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3396 new_mtu += EDSA_HLEN; 3397 3398 mv88e6xxx_reg_lock(chip); 3399 if (chip->info->ops->port_set_jumbo_size) 3400 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3401 else if (chip->info->ops->set_max_frame_size) 3402 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3403 mv88e6xxx_reg_unlock(chip); 3404 3405 return ret; 3406 } 3407 3408 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3409 unsigned int ageing_time) 3410 { 3411 struct mv88e6xxx_chip *chip = ds->priv; 3412 int err; 3413 3414 mv88e6xxx_reg_lock(chip); 3415 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3416 mv88e6xxx_reg_unlock(chip); 3417 3418 return err; 3419 } 3420 3421 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3422 { 3423 int err; 3424 3425 /* Initialize the statistics unit */ 3426 if (chip->info->ops->stats_set_histogram) { 3427 err = chip->info->ops->stats_set_histogram(chip); 3428 if (err) 3429 return err; 3430 } 3431 3432 return mv88e6xxx_g1_stats_clear(chip); 3433 } 3434 3435 /* Check if the errata has already been applied. */ 3436 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3437 { 3438 int port; 3439 int err; 3440 u16 val; 3441 3442 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3443 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3444 if (err) { 3445 dev_err(chip->dev, 3446 "Error reading hidden register: %d\n", err); 3447 return false; 3448 } 3449 if (val != 0x01c0) 3450 return false; 3451 } 3452 3453 return true; 3454 } 3455 3456 /* The 6390 copper ports have an errata which require poking magic 3457 * values into undocumented hidden registers and then performing a 3458 * software reset. 3459 */ 3460 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3461 { 3462 int port; 3463 int err; 3464 3465 if (mv88e6390_setup_errata_applied(chip)) 3466 return 0; 3467 3468 /* Set the ports into blocking mode */ 3469 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3470 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3471 if (err) 3472 return err; 3473 } 3474 3475 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3476 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3477 if (err) 3478 return err; 3479 } 3480 3481 return mv88e6xxx_software_reset(chip); 3482 } 3483 3484 /* prod_id for switch families which do not have a PHY model number */ 3485 static const u16 family_prod_id_table[] = { 3486 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3487 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3488 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3489 }; 3490 3491 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3492 { 3493 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3494 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3495 u16 prod_id; 3496 u16 val; 3497 int err; 3498 3499 if (!chip->info->ops->phy_read) 3500 return -EOPNOTSUPP; 3501 3502 mv88e6xxx_reg_lock(chip); 3503 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3504 mv88e6xxx_reg_unlock(chip); 3505 3506 /* Some internal PHYs don't have a model number. */ 3507 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3508 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3509 prod_id = family_prod_id_table[chip->info->family]; 3510 if (prod_id) 3511 val |= prod_id >> 4; 3512 } 3513 3514 return err ? err : val; 3515 } 3516 3517 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3518 int reg) 3519 { 3520 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3521 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3522 u16 val; 3523 int err; 3524 3525 if (!chip->info->ops->phy_read_c45) 3526 return -EOPNOTSUPP; 3527 3528 mv88e6xxx_reg_lock(chip); 3529 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3530 mv88e6xxx_reg_unlock(chip); 3531 3532 return err ? err : val; 3533 } 3534 3535 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3536 { 3537 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3538 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3539 int err; 3540 3541 if (!chip->info->ops->phy_write) 3542 return -EOPNOTSUPP; 3543 3544 mv88e6xxx_reg_lock(chip); 3545 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3546 mv88e6xxx_reg_unlock(chip); 3547 3548 return err; 3549 } 3550 3551 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3552 int reg, u16 val) 3553 { 3554 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3555 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3556 int err; 3557 3558 if (!chip->info->ops->phy_write_c45) 3559 return -EOPNOTSUPP; 3560 3561 mv88e6xxx_reg_lock(chip); 3562 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3563 mv88e6xxx_reg_unlock(chip); 3564 3565 return err; 3566 } 3567 3568 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3569 struct device_node *np, 3570 bool external) 3571 { 3572 static int index; 3573 struct mv88e6xxx_mdio_bus *mdio_bus; 3574 struct mii_bus *bus; 3575 int err; 3576 3577 if (external) { 3578 mv88e6xxx_reg_lock(chip); 3579 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3580 mv88e6xxx_reg_unlock(chip); 3581 3582 if (err) 3583 return err; 3584 } 3585 3586 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3587 if (!bus) 3588 return -ENOMEM; 3589 3590 mdio_bus = bus->priv; 3591 mdio_bus->bus = bus; 3592 mdio_bus->chip = chip; 3593 INIT_LIST_HEAD(&mdio_bus->list); 3594 mdio_bus->external = external; 3595 3596 if (np) { 3597 bus->name = np->full_name; 3598 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3599 } else { 3600 bus->name = "mv88e6xxx SMI"; 3601 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3602 } 3603 3604 bus->read = mv88e6xxx_mdio_read; 3605 bus->write = mv88e6xxx_mdio_write; 3606 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3607 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3608 bus->parent = chip->dev; 3609 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3610 mv88e6xxx_num_ports(chip) - 1, 3611 chip->info->phy_base_addr); 3612 3613 if (!external) { 3614 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3615 if (err) 3616 goto out; 3617 } 3618 3619 err = of_mdiobus_register(bus, np); 3620 if (err) { 3621 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3622 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3623 goto out; 3624 } 3625 3626 if (external) 3627 list_add_tail(&mdio_bus->list, &chip->mdios); 3628 else 3629 list_add(&mdio_bus->list, &chip->mdios); 3630 3631 return 0; 3632 3633 out: 3634 mdiobus_free(bus); 3635 return err; 3636 } 3637 3638 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3639 3640 { 3641 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3642 struct mii_bus *bus; 3643 3644 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3645 bus = mdio_bus->bus; 3646 3647 if (!mdio_bus->external) 3648 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3649 3650 mdiobus_unregister(bus); 3651 mdiobus_free(bus); 3652 } 3653 } 3654 3655 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3656 { 3657 struct device_node *np = chip->dev->of_node; 3658 struct device_node *child; 3659 int err; 3660 3661 /* Always register one mdio bus for the internal/default mdio 3662 * bus. This maybe represented in the device tree, but is 3663 * optional. 3664 */ 3665 child = of_get_child_by_name(np, "mdio"); 3666 err = mv88e6xxx_mdio_register(chip, child, false); 3667 of_node_put(child); 3668 if (err) 3669 return err; 3670 3671 /* Walk the device tree, and see if there are any other nodes 3672 * which say they are compatible with the external mdio 3673 * bus. 3674 */ 3675 for_each_available_child_of_node(np, child) { 3676 if (of_device_is_compatible( 3677 child, "marvell,mv88e6xxx-mdio-external")) { 3678 err = mv88e6xxx_mdio_register(chip, child, true); 3679 if (err) { 3680 mv88e6xxx_mdios_unregister(chip); 3681 of_node_put(child); 3682 return err; 3683 } 3684 } 3685 } 3686 3687 return 0; 3688 } 3689 3690 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3691 { 3692 struct mv88e6xxx_chip *chip = ds->priv; 3693 3694 mv88e6xxx_teardown_devlink_params(ds); 3695 dsa_devlink_resources_unregister(ds); 3696 mv88e6xxx_teardown_devlink_regions_global(ds); 3697 mv88e6xxx_mdios_unregister(chip); 3698 } 3699 3700 static int mv88e6xxx_setup(struct dsa_switch *ds) 3701 { 3702 struct mv88e6xxx_chip *chip = ds->priv; 3703 u8 cmode; 3704 int err; 3705 int i; 3706 3707 err = mv88e6xxx_mdios_register(chip); 3708 if (err) 3709 return err; 3710 3711 chip->ds = ds; 3712 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3713 3714 /* Since virtual bridges are mapped in the PVT, the number we support 3715 * depends on the physical switch topology. We need to let DSA figure 3716 * that out and therefore we cannot set this at dsa_register_switch() 3717 * time. 3718 */ 3719 if (mv88e6xxx_has_pvt(chip)) 3720 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3721 ds->dst->last_switch - 1; 3722 3723 mv88e6xxx_reg_lock(chip); 3724 3725 if (chip->info->ops->setup_errata) { 3726 err = chip->info->ops->setup_errata(chip); 3727 if (err) 3728 goto unlock; 3729 } 3730 3731 /* Cache the cmode of each port. */ 3732 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3733 if (chip->info->ops->port_get_cmode) { 3734 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3735 if (err) 3736 goto unlock; 3737 3738 chip->ports[i].cmode = cmode; 3739 } 3740 } 3741 3742 err = mv88e6xxx_vtu_setup(chip); 3743 if (err) 3744 goto unlock; 3745 3746 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3747 * VTU, thereby also flushing the STU). 3748 */ 3749 err = mv88e6xxx_stu_setup(chip); 3750 if (err) 3751 goto unlock; 3752 3753 /* Setup Switch Port Registers */ 3754 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3755 if (dsa_is_unused_port(ds, i)) 3756 continue; 3757 3758 /* Prevent the use of an invalid port. */ 3759 if (mv88e6xxx_is_invalid_port(chip, i)) { 3760 dev_err(chip->dev, "port %d is invalid\n", i); 3761 err = -EINVAL; 3762 goto unlock; 3763 } 3764 3765 err = mv88e6xxx_setup_port(chip, i); 3766 if (err) 3767 goto unlock; 3768 } 3769 3770 err = mv88e6xxx_irl_setup(chip); 3771 if (err) 3772 goto unlock; 3773 3774 err = mv88e6xxx_mac_setup(chip); 3775 if (err) 3776 goto unlock; 3777 3778 err = mv88e6xxx_phy_setup(chip); 3779 if (err) 3780 goto unlock; 3781 3782 err = mv88e6xxx_pvt_setup(chip); 3783 if (err) 3784 goto unlock; 3785 3786 err = mv88e6xxx_atu_setup(chip); 3787 if (err) 3788 goto unlock; 3789 3790 err = mv88e6xxx_broadcast_setup(chip, 0); 3791 if (err) 3792 goto unlock; 3793 3794 err = mv88e6xxx_pot_setup(chip); 3795 if (err) 3796 goto unlock; 3797 3798 err = mv88e6xxx_rmu_setup(chip); 3799 if (err) 3800 goto unlock; 3801 3802 err = mv88e6xxx_rsvd2cpu_setup(chip); 3803 if (err) 3804 goto unlock; 3805 3806 err = mv88e6xxx_trunk_setup(chip); 3807 if (err) 3808 goto unlock; 3809 3810 err = mv88e6xxx_devmap_setup(chip); 3811 if (err) 3812 goto unlock; 3813 3814 err = mv88e6xxx_pri_setup(chip); 3815 if (err) 3816 goto unlock; 3817 3818 /* Setup PTP Hardware Clock and timestamping */ 3819 if (chip->info->ptp_support) { 3820 err = mv88e6xxx_ptp_setup(chip); 3821 if (err) 3822 goto unlock; 3823 3824 err = mv88e6xxx_hwtstamp_setup(chip); 3825 if (err) 3826 goto unlock; 3827 } 3828 3829 err = mv88e6xxx_stats_setup(chip); 3830 if (err) 3831 goto unlock; 3832 3833 unlock: 3834 mv88e6xxx_reg_unlock(chip); 3835 3836 if (err) 3837 goto out_mdios; 3838 3839 /* Have to be called without holding the register lock, since 3840 * they take the devlink lock, and we later take the locks in 3841 * the reverse order when getting/setting parameters or 3842 * resource occupancy. 3843 */ 3844 err = mv88e6xxx_setup_devlink_resources(ds); 3845 if (err) 3846 goto out_mdios; 3847 3848 err = mv88e6xxx_setup_devlink_params(ds); 3849 if (err) 3850 goto out_resources; 3851 3852 err = mv88e6xxx_setup_devlink_regions_global(ds); 3853 if (err) 3854 goto out_params; 3855 3856 return 0; 3857 3858 out_params: 3859 mv88e6xxx_teardown_devlink_params(ds); 3860 out_resources: 3861 dsa_devlink_resources_unregister(ds); 3862 out_mdios: 3863 mv88e6xxx_mdios_unregister(chip); 3864 3865 return err; 3866 } 3867 3868 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3869 { 3870 struct mv88e6xxx_chip *chip = ds->priv; 3871 int err; 3872 3873 if (chip->info->ops->pcs_ops->pcs_init) { 3874 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 3875 if (err) 3876 return err; 3877 } 3878 3879 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3880 } 3881 3882 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3883 { 3884 struct mv88e6xxx_chip *chip = ds->priv; 3885 3886 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3887 3888 if (chip->info->ops->pcs_ops->pcs_teardown) 3889 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 3890 } 3891 3892 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3893 { 3894 struct mv88e6xxx_chip *chip = ds->priv; 3895 3896 return chip->eeprom_len; 3897 } 3898 3899 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3900 struct ethtool_eeprom *eeprom, u8 *data) 3901 { 3902 struct mv88e6xxx_chip *chip = ds->priv; 3903 int err; 3904 3905 if (!chip->info->ops->get_eeprom) 3906 return -EOPNOTSUPP; 3907 3908 mv88e6xxx_reg_lock(chip); 3909 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3910 mv88e6xxx_reg_unlock(chip); 3911 3912 if (err) 3913 return err; 3914 3915 eeprom->magic = 0xc3ec4951; 3916 3917 return 0; 3918 } 3919 3920 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3921 struct ethtool_eeprom *eeprom, u8 *data) 3922 { 3923 struct mv88e6xxx_chip *chip = ds->priv; 3924 int err; 3925 3926 if (!chip->info->ops->set_eeprom) 3927 return -EOPNOTSUPP; 3928 3929 if (eeprom->magic != 0xc3ec4951) 3930 return -EINVAL; 3931 3932 mv88e6xxx_reg_lock(chip); 3933 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3934 mv88e6xxx_reg_unlock(chip); 3935 3936 return err; 3937 } 3938 3939 static const struct mv88e6xxx_ops mv88e6085_ops = { 3940 /* MV88E6XXX_FAMILY_6097 */ 3941 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3942 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3943 .irl_init_all = mv88e6352_g2_irl_init_all, 3944 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3945 .phy_read = mv88e6185_phy_ppu_read, 3946 .phy_write = mv88e6185_phy_ppu_write, 3947 .port_set_link = mv88e6xxx_port_set_link, 3948 .port_sync_link = mv88e6xxx_port_sync_link, 3949 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3950 .port_tag_remap = mv88e6095_port_tag_remap, 3951 .port_set_policy = mv88e6352_port_set_policy, 3952 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3953 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3954 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3955 .port_set_ether_type = mv88e6351_port_set_ether_type, 3956 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3957 .port_pause_limit = mv88e6097_port_pause_limit, 3958 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3959 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3960 .port_get_cmode = mv88e6185_port_get_cmode, 3961 .port_setup_message_port = mv88e6xxx_setup_message_port, 3962 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3963 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3964 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3965 .stats_get_strings = mv88e6095_stats_get_strings, 3966 .stats_get_stats = mv88e6095_stats_get_stats, 3967 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3968 .set_egress_port = mv88e6095_g1_set_egress_port, 3969 .watchdog_ops = &mv88e6097_watchdog_ops, 3970 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3971 .pot_clear = mv88e6xxx_g2_pot_clear, 3972 .ppu_enable = mv88e6185_g1_ppu_enable, 3973 .ppu_disable = mv88e6185_g1_ppu_disable, 3974 .reset = mv88e6185_g1_reset, 3975 .rmu_disable = mv88e6085_g1_rmu_disable, 3976 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3977 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3978 .stu_getnext = mv88e6352_g1_stu_getnext, 3979 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 3980 .phylink_get_caps = mv88e6185_phylink_get_caps, 3981 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3982 }; 3983 3984 static const struct mv88e6xxx_ops mv88e6095_ops = { 3985 /* MV88E6XXX_FAMILY_6095 */ 3986 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3987 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3988 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3989 .phy_read = mv88e6185_phy_ppu_read, 3990 .phy_write = mv88e6185_phy_ppu_write, 3991 .port_set_link = mv88e6xxx_port_set_link, 3992 .port_sync_link = mv88e6185_port_sync_link, 3993 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3994 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3995 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3996 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3997 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3998 .port_get_cmode = mv88e6185_port_get_cmode, 3999 .port_setup_message_port = mv88e6xxx_setup_message_port, 4000 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4001 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4002 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4003 .stats_get_strings = mv88e6095_stats_get_strings, 4004 .stats_get_stats = mv88e6095_stats_get_stats, 4005 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4006 .ppu_enable = mv88e6185_g1_ppu_enable, 4007 .ppu_disable = mv88e6185_g1_ppu_disable, 4008 .reset = mv88e6185_g1_reset, 4009 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4010 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4011 .phylink_get_caps = mv88e6095_phylink_get_caps, 4012 .pcs_ops = &mv88e6185_pcs_ops, 4013 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4014 }; 4015 4016 static const struct mv88e6xxx_ops mv88e6097_ops = { 4017 /* MV88E6XXX_FAMILY_6097 */ 4018 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4019 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4020 .irl_init_all = mv88e6352_g2_irl_init_all, 4021 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4022 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4023 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4024 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4025 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4026 .port_set_link = mv88e6xxx_port_set_link, 4027 .port_sync_link = mv88e6185_port_sync_link, 4028 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4029 .port_tag_remap = mv88e6095_port_tag_remap, 4030 .port_set_policy = mv88e6352_port_set_policy, 4031 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4032 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4033 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4034 .port_set_ether_type = mv88e6351_port_set_ether_type, 4035 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4036 .port_pause_limit = mv88e6097_port_pause_limit, 4037 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4038 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4039 .port_get_cmode = mv88e6185_port_get_cmode, 4040 .port_setup_message_port = mv88e6xxx_setup_message_port, 4041 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4042 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4043 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4044 .stats_get_strings = mv88e6095_stats_get_strings, 4045 .stats_get_stats = mv88e6095_stats_get_stats, 4046 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4047 .set_egress_port = mv88e6095_g1_set_egress_port, 4048 .watchdog_ops = &mv88e6097_watchdog_ops, 4049 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4050 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4051 .pot_clear = mv88e6xxx_g2_pot_clear, 4052 .reset = mv88e6352_g1_reset, 4053 .rmu_disable = mv88e6085_g1_rmu_disable, 4054 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4055 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4056 .phylink_get_caps = mv88e6095_phylink_get_caps, 4057 .pcs_ops = &mv88e6185_pcs_ops, 4058 .stu_getnext = mv88e6352_g1_stu_getnext, 4059 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4060 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4061 }; 4062 4063 static const struct mv88e6xxx_ops mv88e6123_ops = { 4064 /* MV88E6XXX_FAMILY_6165 */ 4065 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4066 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4067 .irl_init_all = mv88e6352_g2_irl_init_all, 4068 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4069 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4070 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4071 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4072 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4073 .port_set_link = mv88e6xxx_port_set_link, 4074 .port_sync_link = mv88e6xxx_port_sync_link, 4075 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4076 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4077 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4078 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4079 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4080 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4081 .port_get_cmode = mv88e6185_port_get_cmode, 4082 .port_setup_message_port = mv88e6xxx_setup_message_port, 4083 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4084 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4085 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4086 .stats_get_strings = mv88e6095_stats_get_strings, 4087 .stats_get_stats = mv88e6095_stats_get_stats, 4088 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4089 .set_egress_port = mv88e6095_g1_set_egress_port, 4090 .watchdog_ops = &mv88e6097_watchdog_ops, 4091 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4092 .pot_clear = mv88e6xxx_g2_pot_clear, 4093 .reset = mv88e6352_g1_reset, 4094 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4095 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4096 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4097 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4098 .stu_getnext = mv88e6352_g1_stu_getnext, 4099 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4100 .phylink_get_caps = mv88e6185_phylink_get_caps, 4101 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4102 }; 4103 4104 static const struct mv88e6xxx_ops mv88e6131_ops = { 4105 /* MV88E6XXX_FAMILY_6185 */ 4106 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4107 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4108 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4109 .phy_read = mv88e6185_phy_ppu_read, 4110 .phy_write = mv88e6185_phy_ppu_write, 4111 .port_set_link = mv88e6xxx_port_set_link, 4112 .port_sync_link = mv88e6xxx_port_sync_link, 4113 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4114 .port_tag_remap = mv88e6095_port_tag_remap, 4115 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4116 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4117 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4118 .port_set_ether_type = mv88e6351_port_set_ether_type, 4119 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4120 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4121 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4122 .port_pause_limit = mv88e6097_port_pause_limit, 4123 .port_set_pause = mv88e6185_port_set_pause, 4124 .port_get_cmode = mv88e6185_port_get_cmode, 4125 .port_setup_message_port = mv88e6xxx_setup_message_port, 4126 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4127 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4128 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4129 .stats_get_strings = mv88e6095_stats_get_strings, 4130 .stats_get_stats = mv88e6095_stats_get_stats, 4131 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4132 .set_egress_port = mv88e6095_g1_set_egress_port, 4133 .watchdog_ops = &mv88e6097_watchdog_ops, 4134 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4135 .ppu_enable = mv88e6185_g1_ppu_enable, 4136 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4137 .ppu_disable = mv88e6185_g1_ppu_disable, 4138 .reset = mv88e6185_g1_reset, 4139 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4140 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4141 .phylink_get_caps = mv88e6185_phylink_get_caps, 4142 }; 4143 4144 static const struct mv88e6xxx_ops mv88e6141_ops = { 4145 /* MV88E6XXX_FAMILY_6341 */ 4146 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4147 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4148 .irl_init_all = mv88e6352_g2_irl_init_all, 4149 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4150 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4151 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4152 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4153 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4154 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4155 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4156 .port_set_link = mv88e6xxx_port_set_link, 4157 .port_sync_link = mv88e6xxx_port_sync_link, 4158 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4159 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4160 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4161 .port_tag_remap = mv88e6095_port_tag_remap, 4162 .port_set_policy = mv88e6352_port_set_policy, 4163 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4164 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4165 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4166 .port_set_ether_type = mv88e6351_port_set_ether_type, 4167 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4168 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4169 .port_pause_limit = mv88e6097_port_pause_limit, 4170 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4171 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4172 .port_get_cmode = mv88e6352_port_get_cmode, 4173 .port_set_cmode = mv88e6341_port_set_cmode, 4174 .port_setup_message_port = mv88e6xxx_setup_message_port, 4175 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4176 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4177 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4178 .stats_get_strings = mv88e6320_stats_get_strings, 4179 .stats_get_stats = mv88e6390_stats_get_stats, 4180 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4181 .set_egress_port = mv88e6390_g1_set_egress_port, 4182 .watchdog_ops = &mv88e6390_watchdog_ops, 4183 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4184 .pot_clear = mv88e6xxx_g2_pot_clear, 4185 .reset = mv88e6352_g1_reset, 4186 .rmu_disable = mv88e6390_g1_rmu_disable, 4187 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4188 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4189 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4190 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4191 .stu_getnext = mv88e6352_g1_stu_getnext, 4192 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4193 .serdes_get_lane = mv88e6341_serdes_get_lane, 4194 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4195 .gpio_ops = &mv88e6352_gpio_ops, 4196 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4197 .serdes_get_strings = mv88e6390_serdes_get_strings, 4198 .serdes_get_stats = mv88e6390_serdes_get_stats, 4199 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4200 .serdes_get_regs = mv88e6390_serdes_get_regs, 4201 .phylink_get_caps = mv88e6341_phylink_get_caps, 4202 .pcs_ops = &mv88e6390_pcs_ops, 4203 }; 4204 4205 static const struct mv88e6xxx_ops mv88e6161_ops = { 4206 /* MV88E6XXX_FAMILY_6165 */ 4207 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4208 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4209 .irl_init_all = mv88e6352_g2_irl_init_all, 4210 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4211 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4212 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4213 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4214 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4215 .port_set_link = mv88e6xxx_port_set_link, 4216 .port_sync_link = mv88e6xxx_port_sync_link, 4217 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4218 .port_tag_remap = mv88e6095_port_tag_remap, 4219 .port_set_policy = mv88e6352_port_set_policy, 4220 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4221 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4222 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4223 .port_set_ether_type = mv88e6351_port_set_ether_type, 4224 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4225 .port_pause_limit = mv88e6097_port_pause_limit, 4226 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4227 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4228 .port_get_cmode = mv88e6185_port_get_cmode, 4229 .port_setup_message_port = mv88e6xxx_setup_message_port, 4230 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4231 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4232 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4233 .stats_get_strings = mv88e6095_stats_get_strings, 4234 .stats_get_stats = mv88e6095_stats_get_stats, 4235 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4236 .set_egress_port = mv88e6095_g1_set_egress_port, 4237 .watchdog_ops = &mv88e6097_watchdog_ops, 4238 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4239 .pot_clear = mv88e6xxx_g2_pot_clear, 4240 .reset = mv88e6352_g1_reset, 4241 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4242 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4243 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4244 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4245 .stu_getnext = mv88e6352_g1_stu_getnext, 4246 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4247 .avb_ops = &mv88e6165_avb_ops, 4248 .ptp_ops = &mv88e6165_ptp_ops, 4249 .phylink_get_caps = mv88e6185_phylink_get_caps, 4250 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4251 }; 4252 4253 static const struct mv88e6xxx_ops mv88e6165_ops = { 4254 /* MV88E6XXX_FAMILY_6165 */ 4255 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4256 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4257 .irl_init_all = mv88e6352_g2_irl_init_all, 4258 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4259 .phy_read = mv88e6165_phy_read, 4260 .phy_write = mv88e6165_phy_write, 4261 .port_set_link = mv88e6xxx_port_set_link, 4262 .port_sync_link = mv88e6xxx_port_sync_link, 4263 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4264 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4265 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4266 .port_get_cmode = mv88e6185_port_get_cmode, 4267 .port_setup_message_port = mv88e6xxx_setup_message_port, 4268 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4269 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4270 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4271 .stats_get_strings = mv88e6095_stats_get_strings, 4272 .stats_get_stats = mv88e6095_stats_get_stats, 4273 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4274 .set_egress_port = mv88e6095_g1_set_egress_port, 4275 .watchdog_ops = &mv88e6097_watchdog_ops, 4276 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4277 .pot_clear = mv88e6xxx_g2_pot_clear, 4278 .reset = mv88e6352_g1_reset, 4279 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4280 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4281 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4282 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4283 .stu_getnext = mv88e6352_g1_stu_getnext, 4284 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4285 .avb_ops = &mv88e6165_avb_ops, 4286 .ptp_ops = &mv88e6165_ptp_ops, 4287 .phylink_get_caps = mv88e6185_phylink_get_caps, 4288 }; 4289 4290 static const struct mv88e6xxx_ops mv88e6171_ops = { 4291 /* MV88E6XXX_FAMILY_6351 */ 4292 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4293 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4294 .irl_init_all = mv88e6352_g2_irl_init_all, 4295 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4296 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4297 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4298 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4299 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4300 .port_set_link = mv88e6xxx_port_set_link, 4301 .port_sync_link = mv88e6xxx_port_sync_link, 4302 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4303 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4304 .port_tag_remap = mv88e6095_port_tag_remap, 4305 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4306 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4307 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4308 .port_set_ether_type = mv88e6351_port_set_ether_type, 4309 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4310 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4311 .port_pause_limit = mv88e6097_port_pause_limit, 4312 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4313 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4314 .port_get_cmode = mv88e6352_port_get_cmode, 4315 .port_setup_message_port = mv88e6xxx_setup_message_port, 4316 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4317 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4318 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4319 .stats_get_strings = mv88e6095_stats_get_strings, 4320 .stats_get_stats = mv88e6095_stats_get_stats, 4321 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4322 .set_egress_port = mv88e6095_g1_set_egress_port, 4323 .watchdog_ops = &mv88e6097_watchdog_ops, 4324 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4325 .pot_clear = mv88e6xxx_g2_pot_clear, 4326 .reset = mv88e6352_g1_reset, 4327 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4328 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4329 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4330 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4331 .stu_getnext = mv88e6352_g1_stu_getnext, 4332 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4333 .phylink_get_caps = mv88e6185_phylink_get_caps, 4334 }; 4335 4336 static const struct mv88e6xxx_ops mv88e6172_ops = { 4337 /* MV88E6XXX_FAMILY_6352 */ 4338 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4339 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4340 .irl_init_all = mv88e6352_g2_irl_init_all, 4341 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4342 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4343 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4344 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4345 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4346 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4347 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4348 .port_set_link = mv88e6xxx_port_set_link, 4349 .port_sync_link = mv88e6xxx_port_sync_link, 4350 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4351 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4352 .port_tag_remap = mv88e6095_port_tag_remap, 4353 .port_set_policy = mv88e6352_port_set_policy, 4354 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4355 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4356 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4357 .port_set_ether_type = mv88e6351_port_set_ether_type, 4358 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4359 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4360 .port_pause_limit = mv88e6097_port_pause_limit, 4361 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4362 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4363 .port_get_cmode = mv88e6352_port_get_cmode, 4364 .port_setup_message_port = mv88e6xxx_setup_message_port, 4365 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4366 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4367 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4368 .stats_get_strings = mv88e6095_stats_get_strings, 4369 .stats_get_stats = mv88e6095_stats_get_stats, 4370 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4371 .set_egress_port = mv88e6095_g1_set_egress_port, 4372 .watchdog_ops = &mv88e6097_watchdog_ops, 4373 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4374 .pot_clear = mv88e6xxx_g2_pot_clear, 4375 .reset = mv88e6352_g1_reset, 4376 .rmu_disable = mv88e6352_g1_rmu_disable, 4377 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4378 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4379 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4380 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4381 .stu_getnext = mv88e6352_g1_stu_getnext, 4382 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4383 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4384 .serdes_get_regs = mv88e6352_serdes_get_regs, 4385 .gpio_ops = &mv88e6352_gpio_ops, 4386 .phylink_get_caps = mv88e6352_phylink_get_caps, 4387 .pcs_ops = &mv88e6352_pcs_ops, 4388 }; 4389 4390 static const struct mv88e6xxx_ops mv88e6175_ops = { 4391 /* MV88E6XXX_FAMILY_6351 */ 4392 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4393 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4394 .irl_init_all = mv88e6352_g2_irl_init_all, 4395 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4396 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4397 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4398 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4399 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4400 .port_set_link = mv88e6xxx_port_set_link, 4401 .port_sync_link = mv88e6xxx_port_sync_link, 4402 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4403 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4404 .port_tag_remap = mv88e6095_port_tag_remap, 4405 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4406 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4407 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4408 .port_set_ether_type = mv88e6351_port_set_ether_type, 4409 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4410 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4411 .port_pause_limit = mv88e6097_port_pause_limit, 4412 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4413 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4414 .port_get_cmode = mv88e6352_port_get_cmode, 4415 .port_setup_message_port = mv88e6xxx_setup_message_port, 4416 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4417 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4418 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4419 .stats_get_strings = mv88e6095_stats_get_strings, 4420 .stats_get_stats = mv88e6095_stats_get_stats, 4421 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4422 .set_egress_port = mv88e6095_g1_set_egress_port, 4423 .watchdog_ops = &mv88e6097_watchdog_ops, 4424 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4425 .pot_clear = mv88e6xxx_g2_pot_clear, 4426 .reset = mv88e6352_g1_reset, 4427 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4428 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4429 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4430 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4431 .stu_getnext = mv88e6352_g1_stu_getnext, 4432 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4433 .phylink_get_caps = mv88e6185_phylink_get_caps, 4434 }; 4435 4436 static const struct mv88e6xxx_ops mv88e6176_ops = { 4437 /* MV88E6XXX_FAMILY_6352 */ 4438 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4439 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4440 .irl_init_all = mv88e6352_g2_irl_init_all, 4441 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4442 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4443 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4444 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4445 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4446 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4447 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4448 .port_set_link = mv88e6xxx_port_set_link, 4449 .port_sync_link = mv88e6xxx_port_sync_link, 4450 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4451 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4452 .port_tag_remap = mv88e6095_port_tag_remap, 4453 .port_set_policy = mv88e6352_port_set_policy, 4454 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4455 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4456 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4457 .port_set_ether_type = mv88e6351_port_set_ether_type, 4458 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4459 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4460 .port_pause_limit = mv88e6097_port_pause_limit, 4461 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4462 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4463 .port_get_cmode = mv88e6352_port_get_cmode, 4464 .port_setup_message_port = mv88e6xxx_setup_message_port, 4465 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4466 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4467 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4468 .stats_get_strings = mv88e6095_stats_get_strings, 4469 .stats_get_stats = mv88e6095_stats_get_stats, 4470 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4471 .set_egress_port = mv88e6095_g1_set_egress_port, 4472 .watchdog_ops = &mv88e6097_watchdog_ops, 4473 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4474 .pot_clear = mv88e6xxx_g2_pot_clear, 4475 .reset = mv88e6352_g1_reset, 4476 .rmu_disable = mv88e6352_g1_rmu_disable, 4477 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4478 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4479 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4480 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4481 .stu_getnext = mv88e6352_g1_stu_getnext, 4482 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4483 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4484 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4485 .serdes_get_regs = mv88e6352_serdes_get_regs, 4486 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4487 .gpio_ops = &mv88e6352_gpio_ops, 4488 .phylink_get_caps = mv88e6352_phylink_get_caps, 4489 .pcs_ops = &mv88e6352_pcs_ops, 4490 }; 4491 4492 static const struct mv88e6xxx_ops mv88e6185_ops = { 4493 /* MV88E6XXX_FAMILY_6185 */ 4494 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4495 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4496 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4497 .phy_read = mv88e6185_phy_ppu_read, 4498 .phy_write = mv88e6185_phy_ppu_write, 4499 .port_set_link = mv88e6xxx_port_set_link, 4500 .port_sync_link = mv88e6185_port_sync_link, 4501 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4502 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4503 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4504 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4505 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4506 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4507 .port_set_pause = mv88e6185_port_set_pause, 4508 .port_get_cmode = mv88e6185_port_get_cmode, 4509 .port_setup_message_port = mv88e6xxx_setup_message_port, 4510 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4511 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4512 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4513 .stats_get_strings = mv88e6095_stats_get_strings, 4514 .stats_get_stats = mv88e6095_stats_get_stats, 4515 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4516 .set_egress_port = mv88e6095_g1_set_egress_port, 4517 .watchdog_ops = &mv88e6097_watchdog_ops, 4518 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4519 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4520 .ppu_enable = mv88e6185_g1_ppu_enable, 4521 .ppu_disable = mv88e6185_g1_ppu_disable, 4522 .reset = mv88e6185_g1_reset, 4523 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4524 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4525 .phylink_get_caps = mv88e6185_phylink_get_caps, 4526 .pcs_ops = &mv88e6185_pcs_ops, 4527 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4528 }; 4529 4530 static const struct mv88e6xxx_ops mv88e6190_ops = { 4531 /* MV88E6XXX_FAMILY_6390 */ 4532 .setup_errata = mv88e6390_setup_errata, 4533 .irl_init_all = mv88e6390_g2_irl_init_all, 4534 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4535 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4536 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4537 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4538 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4539 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4540 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4541 .port_set_link = mv88e6xxx_port_set_link, 4542 .port_sync_link = mv88e6xxx_port_sync_link, 4543 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4544 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4545 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4546 .port_tag_remap = mv88e6390_port_tag_remap, 4547 .port_set_policy = mv88e6352_port_set_policy, 4548 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4549 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4550 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4551 .port_set_ether_type = mv88e6351_port_set_ether_type, 4552 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4553 .port_pause_limit = mv88e6390_port_pause_limit, 4554 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4555 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4556 .port_get_cmode = mv88e6352_port_get_cmode, 4557 .port_set_cmode = mv88e6390_port_set_cmode, 4558 .port_setup_message_port = mv88e6xxx_setup_message_port, 4559 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4560 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4561 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4562 .stats_get_strings = mv88e6320_stats_get_strings, 4563 .stats_get_stats = mv88e6390_stats_get_stats, 4564 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4565 .set_egress_port = mv88e6390_g1_set_egress_port, 4566 .watchdog_ops = &mv88e6390_watchdog_ops, 4567 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4568 .pot_clear = mv88e6xxx_g2_pot_clear, 4569 .reset = mv88e6352_g1_reset, 4570 .rmu_disable = mv88e6390_g1_rmu_disable, 4571 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4572 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4573 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4574 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4575 .stu_getnext = mv88e6390_g1_stu_getnext, 4576 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4577 .serdes_get_lane = mv88e6390_serdes_get_lane, 4578 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4579 .serdes_get_strings = mv88e6390_serdes_get_strings, 4580 .serdes_get_stats = mv88e6390_serdes_get_stats, 4581 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4582 .serdes_get_regs = mv88e6390_serdes_get_regs, 4583 .gpio_ops = &mv88e6352_gpio_ops, 4584 .phylink_get_caps = mv88e6390_phylink_get_caps, 4585 .pcs_ops = &mv88e6390_pcs_ops, 4586 }; 4587 4588 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4589 /* MV88E6XXX_FAMILY_6390 */ 4590 .setup_errata = mv88e6390_setup_errata, 4591 .irl_init_all = mv88e6390_g2_irl_init_all, 4592 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4593 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4594 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4595 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4596 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4597 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4598 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4599 .port_set_link = mv88e6xxx_port_set_link, 4600 .port_sync_link = mv88e6xxx_port_sync_link, 4601 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4602 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4603 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4604 .port_tag_remap = mv88e6390_port_tag_remap, 4605 .port_set_policy = mv88e6352_port_set_policy, 4606 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4607 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4608 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4609 .port_set_ether_type = mv88e6351_port_set_ether_type, 4610 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4611 .port_pause_limit = mv88e6390_port_pause_limit, 4612 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4613 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4614 .port_get_cmode = mv88e6352_port_get_cmode, 4615 .port_set_cmode = mv88e6390x_port_set_cmode, 4616 .port_setup_message_port = mv88e6xxx_setup_message_port, 4617 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4618 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4619 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4620 .stats_get_strings = mv88e6320_stats_get_strings, 4621 .stats_get_stats = mv88e6390_stats_get_stats, 4622 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4623 .set_egress_port = mv88e6390_g1_set_egress_port, 4624 .watchdog_ops = &mv88e6390_watchdog_ops, 4625 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4626 .pot_clear = mv88e6xxx_g2_pot_clear, 4627 .reset = mv88e6352_g1_reset, 4628 .rmu_disable = mv88e6390_g1_rmu_disable, 4629 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4630 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4631 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4632 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4633 .stu_getnext = mv88e6390_g1_stu_getnext, 4634 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4635 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4636 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4637 .serdes_get_strings = mv88e6390_serdes_get_strings, 4638 .serdes_get_stats = mv88e6390_serdes_get_stats, 4639 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4640 .serdes_get_regs = mv88e6390_serdes_get_regs, 4641 .gpio_ops = &mv88e6352_gpio_ops, 4642 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4643 .pcs_ops = &mv88e6390_pcs_ops, 4644 }; 4645 4646 static const struct mv88e6xxx_ops mv88e6191_ops = { 4647 /* MV88E6XXX_FAMILY_6390 */ 4648 .setup_errata = mv88e6390_setup_errata, 4649 .irl_init_all = mv88e6390_g2_irl_init_all, 4650 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4651 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4652 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4653 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4654 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4655 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4656 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4657 .port_set_link = mv88e6xxx_port_set_link, 4658 .port_sync_link = mv88e6xxx_port_sync_link, 4659 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4660 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4661 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4662 .port_tag_remap = mv88e6390_port_tag_remap, 4663 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4664 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4665 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4666 .port_set_ether_type = mv88e6351_port_set_ether_type, 4667 .port_pause_limit = mv88e6390_port_pause_limit, 4668 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4669 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4670 .port_get_cmode = mv88e6352_port_get_cmode, 4671 .port_set_cmode = mv88e6390_port_set_cmode, 4672 .port_setup_message_port = mv88e6xxx_setup_message_port, 4673 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4674 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4675 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4676 .stats_get_strings = mv88e6320_stats_get_strings, 4677 .stats_get_stats = mv88e6390_stats_get_stats, 4678 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4679 .set_egress_port = mv88e6390_g1_set_egress_port, 4680 .watchdog_ops = &mv88e6390_watchdog_ops, 4681 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4682 .pot_clear = mv88e6xxx_g2_pot_clear, 4683 .reset = mv88e6352_g1_reset, 4684 .rmu_disable = mv88e6390_g1_rmu_disable, 4685 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4686 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4687 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4688 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4689 .stu_getnext = mv88e6390_g1_stu_getnext, 4690 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4691 .serdes_get_lane = mv88e6390_serdes_get_lane, 4692 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4693 .serdes_get_strings = mv88e6390_serdes_get_strings, 4694 .serdes_get_stats = mv88e6390_serdes_get_stats, 4695 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4696 .serdes_get_regs = mv88e6390_serdes_get_regs, 4697 .avb_ops = &mv88e6390_avb_ops, 4698 .ptp_ops = &mv88e6352_ptp_ops, 4699 .phylink_get_caps = mv88e6390_phylink_get_caps, 4700 .pcs_ops = &mv88e6390_pcs_ops, 4701 }; 4702 4703 static const struct mv88e6xxx_ops mv88e6240_ops = { 4704 /* MV88E6XXX_FAMILY_6352 */ 4705 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4706 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4707 .irl_init_all = mv88e6352_g2_irl_init_all, 4708 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4709 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4710 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4711 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4712 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4713 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4714 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4715 .port_set_link = mv88e6xxx_port_set_link, 4716 .port_sync_link = mv88e6xxx_port_sync_link, 4717 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4718 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4719 .port_tag_remap = mv88e6095_port_tag_remap, 4720 .port_set_policy = mv88e6352_port_set_policy, 4721 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4722 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4723 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4724 .port_set_ether_type = mv88e6351_port_set_ether_type, 4725 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4726 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4727 .port_pause_limit = mv88e6097_port_pause_limit, 4728 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4729 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4730 .port_get_cmode = mv88e6352_port_get_cmode, 4731 .port_setup_message_port = mv88e6xxx_setup_message_port, 4732 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4733 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4734 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4735 .stats_get_strings = mv88e6095_stats_get_strings, 4736 .stats_get_stats = mv88e6095_stats_get_stats, 4737 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4738 .set_egress_port = mv88e6095_g1_set_egress_port, 4739 .watchdog_ops = &mv88e6097_watchdog_ops, 4740 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4741 .pot_clear = mv88e6xxx_g2_pot_clear, 4742 .reset = mv88e6352_g1_reset, 4743 .rmu_disable = mv88e6352_g1_rmu_disable, 4744 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4745 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4746 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4747 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4748 .stu_getnext = mv88e6352_g1_stu_getnext, 4749 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4750 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4751 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4752 .serdes_get_regs = mv88e6352_serdes_get_regs, 4753 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4754 .gpio_ops = &mv88e6352_gpio_ops, 4755 .avb_ops = &mv88e6352_avb_ops, 4756 .ptp_ops = &mv88e6352_ptp_ops, 4757 .phylink_get_caps = mv88e6352_phylink_get_caps, 4758 .pcs_ops = &mv88e6352_pcs_ops, 4759 }; 4760 4761 static const struct mv88e6xxx_ops mv88e6250_ops = { 4762 /* MV88E6XXX_FAMILY_6250 */ 4763 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4764 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4765 .irl_init_all = mv88e6352_g2_irl_init_all, 4766 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4767 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4768 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4769 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4770 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4771 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4772 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4773 .port_set_link = mv88e6xxx_port_set_link, 4774 .port_sync_link = mv88e6xxx_port_sync_link, 4775 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4776 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4777 .port_tag_remap = mv88e6095_port_tag_remap, 4778 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4779 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4780 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4781 .port_set_ether_type = mv88e6351_port_set_ether_type, 4782 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4783 .port_pause_limit = mv88e6097_port_pause_limit, 4784 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4785 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4786 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4787 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4788 .stats_get_strings = mv88e6250_stats_get_strings, 4789 .stats_get_stats = mv88e6250_stats_get_stats, 4790 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4791 .set_egress_port = mv88e6095_g1_set_egress_port, 4792 .watchdog_ops = &mv88e6250_watchdog_ops, 4793 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4794 .pot_clear = mv88e6xxx_g2_pot_clear, 4795 .reset = mv88e6250_g1_reset, 4796 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4797 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4798 .avb_ops = &mv88e6352_avb_ops, 4799 .ptp_ops = &mv88e6250_ptp_ops, 4800 .phylink_get_caps = mv88e6250_phylink_get_caps, 4801 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4802 }; 4803 4804 static const struct mv88e6xxx_ops mv88e6290_ops = { 4805 /* MV88E6XXX_FAMILY_6390 */ 4806 .setup_errata = mv88e6390_setup_errata, 4807 .irl_init_all = mv88e6390_g2_irl_init_all, 4808 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4809 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4810 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4811 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4812 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4813 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4814 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4815 .port_set_link = mv88e6xxx_port_set_link, 4816 .port_sync_link = mv88e6xxx_port_sync_link, 4817 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4818 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4819 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4820 .port_tag_remap = mv88e6390_port_tag_remap, 4821 .port_set_policy = mv88e6352_port_set_policy, 4822 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4823 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4824 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4825 .port_set_ether_type = mv88e6351_port_set_ether_type, 4826 .port_pause_limit = mv88e6390_port_pause_limit, 4827 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4828 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4829 .port_get_cmode = mv88e6352_port_get_cmode, 4830 .port_set_cmode = mv88e6390_port_set_cmode, 4831 .port_setup_message_port = mv88e6xxx_setup_message_port, 4832 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4833 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4834 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4835 .stats_get_strings = mv88e6320_stats_get_strings, 4836 .stats_get_stats = mv88e6390_stats_get_stats, 4837 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4838 .set_egress_port = mv88e6390_g1_set_egress_port, 4839 .watchdog_ops = &mv88e6390_watchdog_ops, 4840 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4841 .pot_clear = mv88e6xxx_g2_pot_clear, 4842 .reset = mv88e6352_g1_reset, 4843 .rmu_disable = mv88e6390_g1_rmu_disable, 4844 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4845 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4846 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4847 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4848 .stu_getnext = mv88e6390_g1_stu_getnext, 4849 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4850 .serdes_get_lane = mv88e6390_serdes_get_lane, 4851 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4852 .serdes_get_strings = mv88e6390_serdes_get_strings, 4853 .serdes_get_stats = mv88e6390_serdes_get_stats, 4854 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4855 .serdes_get_regs = mv88e6390_serdes_get_regs, 4856 .gpio_ops = &mv88e6352_gpio_ops, 4857 .avb_ops = &mv88e6390_avb_ops, 4858 .ptp_ops = &mv88e6390_ptp_ops, 4859 .phylink_get_caps = mv88e6390_phylink_get_caps, 4860 .pcs_ops = &mv88e6390_pcs_ops, 4861 }; 4862 4863 static const struct mv88e6xxx_ops mv88e6320_ops = { 4864 /* MV88E6XXX_FAMILY_6320 */ 4865 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4866 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4867 .irl_init_all = mv88e6352_g2_irl_init_all, 4868 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4869 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4870 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4871 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4872 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4873 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4874 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4875 .port_set_link = mv88e6xxx_port_set_link, 4876 .port_sync_link = mv88e6xxx_port_sync_link, 4877 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 4878 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4879 .port_tag_remap = mv88e6095_port_tag_remap, 4880 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4881 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4882 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4883 .port_set_ether_type = mv88e6351_port_set_ether_type, 4884 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4885 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4886 .port_pause_limit = mv88e6097_port_pause_limit, 4887 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4888 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4889 .port_get_cmode = mv88e6352_port_get_cmode, 4890 .port_setup_message_port = mv88e6xxx_setup_message_port, 4891 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4892 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4893 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4894 .stats_get_strings = mv88e6320_stats_get_strings, 4895 .stats_get_stats = mv88e6320_stats_get_stats, 4896 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4897 .set_egress_port = mv88e6095_g1_set_egress_port, 4898 .watchdog_ops = &mv88e6390_watchdog_ops, 4899 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4900 .pot_clear = mv88e6xxx_g2_pot_clear, 4901 .reset = mv88e6352_g1_reset, 4902 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4903 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4904 .gpio_ops = &mv88e6352_gpio_ops, 4905 .avb_ops = &mv88e6352_avb_ops, 4906 .ptp_ops = &mv88e6352_ptp_ops, 4907 .phylink_get_caps = mv88e6185_phylink_get_caps, 4908 }; 4909 4910 static const struct mv88e6xxx_ops mv88e6321_ops = { 4911 /* MV88E6XXX_FAMILY_6320 */ 4912 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4913 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4914 .irl_init_all = mv88e6352_g2_irl_init_all, 4915 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4916 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4917 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4918 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4919 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4920 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4921 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4922 .port_set_link = mv88e6xxx_port_set_link, 4923 .port_sync_link = mv88e6xxx_port_sync_link, 4924 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 4925 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4926 .port_tag_remap = mv88e6095_port_tag_remap, 4927 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4928 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4929 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4930 .port_set_ether_type = mv88e6351_port_set_ether_type, 4931 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4932 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4933 .port_pause_limit = mv88e6097_port_pause_limit, 4934 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4935 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4936 .port_get_cmode = mv88e6352_port_get_cmode, 4937 .port_setup_message_port = mv88e6xxx_setup_message_port, 4938 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4939 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4940 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4941 .stats_get_strings = mv88e6320_stats_get_strings, 4942 .stats_get_stats = mv88e6320_stats_get_stats, 4943 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4944 .set_egress_port = mv88e6095_g1_set_egress_port, 4945 .watchdog_ops = &mv88e6390_watchdog_ops, 4946 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4947 .reset = mv88e6352_g1_reset, 4948 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4949 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4950 .gpio_ops = &mv88e6352_gpio_ops, 4951 .avb_ops = &mv88e6352_avb_ops, 4952 .ptp_ops = &mv88e6352_ptp_ops, 4953 .phylink_get_caps = mv88e6185_phylink_get_caps, 4954 }; 4955 4956 static const struct mv88e6xxx_ops mv88e6341_ops = { 4957 /* MV88E6XXX_FAMILY_6341 */ 4958 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4959 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4960 .irl_init_all = mv88e6352_g2_irl_init_all, 4961 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4962 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4963 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4964 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4965 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4966 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4967 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4968 .port_set_link = mv88e6xxx_port_set_link, 4969 .port_sync_link = mv88e6xxx_port_sync_link, 4970 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4971 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4972 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4973 .port_tag_remap = mv88e6095_port_tag_remap, 4974 .port_set_policy = mv88e6352_port_set_policy, 4975 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4976 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4977 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4978 .port_set_ether_type = mv88e6351_port_set_ether_type, 4979 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4980 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4981 .port_pause_limit = mv88e6097_port_pause_limit, 4982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4984 .port_get_cmode = mv88e6352_port_get_cmode, 4985 .port_set_cmode = mv88e6341_port_set_cmode, 4986 .port_setup_message_port = mv88e6xxx_setup_message_port, 4987 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4988 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4989 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4990 .stats_get_strings = mv88e6320_stats_get_strings, 4991 .stats_get_stats = mv88e6390_stats_get_stats, 4992 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4993 .set_egress_port = mv88e6390_g1_set_egress_port, 4994 .watchdog_ops = &mv88e6390_watchdog_ops, 4995 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4996 .pot_clear = mv88e6xxx_g2_pot_clear, 4997 .reset = mv88e6352_g1_reset, 4998 .rmu_disable = mv88e6390_g1_rmu_disable, 4999 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5000 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5001 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5002 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5003 .stu_getnext = mv88e6352_g1_stu_getnext, 5004 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5005 .serdes_get_lane = mv88e6341_serdes_get_lane, 5006 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5007 .gpio_ops = &mv88e6352_gpio_ops, 5008 .avb_ops = &mv88e6390_avb_ops, 5009 .ptp_ops = &mv88e6352_ptp_ops, 5010 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5011 .serdes_get_strings = mv88e6390_serdes_get_strings, 5012 .serdes_get_stats = mv88e6390_serdes_get_stats, 5013 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5014 .serdes_get_regs = mv88e6390_serdes_get_regs, 5015 .phylink_get_caps = mv88e6341_phylink_get_caps, 5016 .pcs_ops = &mv88e6390_pcs_ops, 5017 }; 5018 5019 static const struct mv88e6xxx_ops mv88e6350_ops = { 5020 /* MV88E6XXX_FAMILY_6351 */ 5021 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5022 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5023 .irl_init_all = mv88e6352_g2_irl_init_all, 5024 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5025 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5026 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5027 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5028 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5029 .port_set_link = mv88e6xxx_port_set_link, 5030 .port_sync_link = mv88e6xxx_port_sync_link, 5031 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5032 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5033 .port_tag_remap = mv88e6095_port_tag_remap, 5034 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5035 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5036 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5037 .port_set_ether_type = mv88e6351_port_set_ether_type, 5038 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5039 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5040 .port_pause_limit = mv88e6097_port_pause_limit, 5041 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5042 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5043 .port_get_cmode = mv88e6352_port_get_cmode, 5044 .port_setup_message_port = mv88e6xxx_setup_message_port, 5045 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5046 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5047 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5048 .stats_get_strings = mv88e6095_stats_get_strings, 5049 .stats_get_stats = mv88e6095_stats_get_stats, 5050 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5051 .set_egress_port = mv88e6095_g1_set_egress_port, 5052 .watchdog_ops = &mv88e6097_watchdog_ops, 5053 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5054 .pot_clear = mv88e6xxx_g2_pot_clear, 5055 .reset = mv88e6352_g1_reset, 5056 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5057 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5058 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5059 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5060 .stu_getnext = mv88e6352_g1_stu_getnext, 5061 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5062 .phylink_get_caps = mv88e6185_phylink_get_caps, 5063 }; 5064 5065 static const struct mv88e6xxx_ops mv88e6351_ops = { 5066 /* MV88E6XXX_FAMILY_6351 */ 5067 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5068 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5069 .irl_init_all = mv88e6352_g2_irl_init_all, 5070 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5071 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5072 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5073 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5074 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5075 .port_set_link = mv88e6xxx_port_set_link, 5076 .port_sync_link = mv88e6xxx_port_sync_link, 5077 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5078 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5079 .port_tag_remap = mv88e6095_port_tag_remap, 5080 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5081 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5082 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5083 .port_set_ether_type = mv88e6351_port_set_ether_type, 5084 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5085 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5086 .port_pause_limit = mv88e6097_port_pause_limit, 5087 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5088 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5089 .port_get_cmode = mv88e6352_port_get_cmode, 5090 .port_setup_message_port = mv88e6xxx_setup_message_port, 5091 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5092 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5093 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5094 .stats_get_strings = mv88e6095_stats_get_strings, 5095 .stats_get_stats = mv88e6095_stats_get_stats, 5096 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5097 .set_egress_port = mv88e6095_g1_set_egress_port, 5098 .watchdog_ops = &mv88e6097_watchdog_ops, 5099 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5100 .pot_clear = mv88e6xxx_g2_pot_clear, 5101 .reset = mv88e6352_g1_reset, 5102 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5103 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5104 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5105 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5106 .stu_getnext = mv88e6352_g1_stu_getnext, 5107 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5108 .avb_ops = &mv88e6352_avb_ops, 5109 .ptp_ops = &mv88e6352_ptp_ops, 5110 .phylink_get_caps = mv88e6185_phylink_get_caps, 5111 }; 5112 5113 static const struct mv88e6xxx_ops mv88e6352_ops = { 5114 /* MV88E6XXX_FAMILY_6352 */ 5115 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5116 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5117 .irl_init_all = mv88e6352_g2_irl_init_all, 5118 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5119 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5120 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5121 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5122 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5123 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5124 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5125 .port_set_link = mv88e6xxx_port_set_link, 5126 .port_sync_link = mv88e6xxx_port_sync_link, 5127 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5128 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5129 .port_tag_remap = mv88e6095_port_tag_remap, 5130 .port_set_policy = mv88e6352_port_set_policy, 5131 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5132 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5133 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5134 .port_set_ether_type = mv88e6351_port_set_ether_type, 5135 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5136 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5137 .port_pause_limit = mv88e6097_port_pause_limit, 5138 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5139 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5140 .port_get_cmode = mv88e6352_port_get_cmode, 5141 .port_setup_message_port = mv88e6xxx_setup_message_port, 5142 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5143 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5144 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5145 .stats_get_strings = mv88e6095_stats_get_strings, 5146 .stats_get_stats = mv88e6095_stats_get_stats, 5147 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5148 .set_egress_port = mv88e6095_g1_set_egress_port, 5149 .watchdog_ops = &mv88e6097_watchdog_ops, 5150 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5151 .pot_clear = mv88e6xxx_g2_pot_clear, 5152 .reset = mv88e6352_g1_reset, 5153 .rmu_disable = mv88e6352_g1_rmu_disable, 5154 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5155 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5156 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5157 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5158 .stu_getnext = mv88e6352_g1_stu_getnext, 5159 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5160 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5161 .gpio_ops = &mv88e6352_gpio_ops, 5162 .avb_ops = &mv88e6352_avb_ops, 5163 .ptp_ops = &mv88e6352_ptp_ops, 5164 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5165 .serdes_get_strings = mv88e6352_serdes_get_strings, 5166 .serdes_get_stats = mv88e6352_serdes_get_stats, 5167 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5168 .serdes_get_regs = mv88e6352_serdes_get_regs, 5169 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5170 .phylink_get_caps = mv88e6352_phylink_get_caps, 5171 .pcs_ops = &mv88e6352_pcs_ops, 5172 }; 5173 5174 static const struct mv88e6xxx_ops mv88e6390_ops = { 5175 /* MV88E6XXX_FAMILY_6390 */ 5176 .setup_errata = mv88e6390_setup_errata, 5177 .irl_init_all = mv88e6390_g2_irl_init_all, 5178 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5179 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5180 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5181 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5182 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5183 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5184 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5185 .port_set_link = mv88e6xxx_port_set_link, 5186 .port_sync_link = mv88e6xxx_port_sync_link, 5187 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5188 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5189 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5190 .port_tag_remap = mv88e6390_port_tag_remap, 5191 .port_set_policy = mv88e6352_port_set_policy, 5192 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5193 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5194 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5195 .port_set_ether_type = mv88e6351_port_set_ether_type, 5196 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5197 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5198 .port_pause_limit = mv88e6390_port_pause_limit, 5199 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5200 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5201 .port_get_cmode = mv88e6352_port_get_cmode, 5202 .port_set_cmode = mv88e6390_port_set_cmode, 5203 .port_setup_message_port = mv88e6xxx_setup_message_port, 5204 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5205 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5206 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5207 .stats_get_strings = mv88e6320_stats_get_strings, 5208 .stats_get_stats = mv88e6390_stats_get_stats, 5209 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5210 .set_egress_port = mv88e6390_g1_set_egress_port, 5211 .watchdog_ops = &mv88e6390_watchdog_ops, 5212 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5213 .pot_clear = mv88e6xxx_g2_pot_clear, 5214 .reset = mv88e6352_g1_reset, 5215 .rmu_disable = mv88e6390_g1_rmu_disable, 5216 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5217 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5218 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5219 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5220 .stu_getnext = mv88e6390_g1_stu_getnext, 5221 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5222 .serdes_get_lane = mv88e6390_serdes_get_lane, 5223 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5224 .gpio_ops = &mv88e6352_gpio_ops, 5225 .avb_ops = &mv88e6390_avb_ops, 5226 .ptp_ops = &mv88e6390_ptp_ops, 5227 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5228 .serdes_get_strings = mv88e6390_serdes_get_strings, 5229 .serdes_get_stats = mv88e6390_serdes_get_stats, 5230 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5231 .serdes_get_regs = mv88e6390_serdes_get_regs, 5232 .phylink_get_caps = mv88e6390_phylink_get_caps, 5233 .pcs_ops = &mv88e6390_pcs_ops, 5234 }; 5235 5236 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5237 /* MV88E6XXX_FAMILY_6390 */ 5238 .setup_errata = mv88e6390_setup_errata, 5239 .irl_init_all = mv88e6390_g2_irl_init_all, 5240 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5241 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5242 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5243 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5244 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5245 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5246 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5247 .port_set_link = mv88e6xxx_port_set_link, 5248 .port_sync_link = mv88e6xxx_port_sync_link, 5249 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5250 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5251 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5252 .port_tag_remap = mv88e6390_port_tag_remap, 5253 .port_set_policy = mv88e6352_port_set_policy, 5254 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5255 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5256 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5257 .port_set_ether_type = mv88e6351_port_set_ether_type, 5258 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5259 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5260 .port_pause_limit = mv88e6390_port_pause_limit, 5261 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5262 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5263 .port_get_cmode = mv88e6352_port_get_cmode, 5264 .port_set_cmode = mv88e6390x_port_set_cmode, 5265 .port_setup_message_port = mv88e6xxx_setup_message_port, 5266 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5267 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5268 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5269 .stats_get_strings = mv88e6320_stats_get_strings, 5270 .stats_get_stats = mv88e6390_stats_get_stats, 5271 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5272 .set_egress_port = mv88e6390_g1_set_egress_port, 5273 .watchdog_ops = &mv88e6390_watchdog_ops, 5274 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5275 .pot_clear = mv88e6xxx_g2_pot_clear, 5276 .reset = mv88e6352_g1_reset, 5277 .rmu_disable = mv88e6390_g1_rmu_disable, 5278 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5279 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5280 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5281 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5282 .stu_getnext = mv88e6390_g1_stu_getnext, 5283 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5284 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5285 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5286 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5287 .serdes_get_strings = mv88e6390_serdes_get_strings, 5288 .serdes_get_stats = mv88e6390_serdes_get_stats, 5289 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5290 .serdes_get_regs = mv88e6390_serdes_get_regs, 5291 .gpio_ops = &mv88e6352_gpio_ops, 5292 .avb_ops = &mv88e6390_avb_ops, 5293 .ptp_ops = &mv88e6390_ptp_ops, 5294 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5295 .pcs_ops = &mv88e6390_pcs_ops, 5296 }; 5297 5298 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5299 /* MV88E6XXX_FAMILY_6393 */ 5300 .irl_init_all = mv88e6390_g2_irl_init_all, 5301 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5302 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5303 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5304 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5305 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5306 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5307 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5308 .port_set_link = mv88e6xxx_port_set_link, 5309 .port_sync_link = mv88e6xxx_port_sync_link, 5310 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5311 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5312 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5313 .port_tag_remap = mv88e6390_port_tag_remap, 5314 .port_set_policy = mv88e6393x_port_set_policy, 5315 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5316 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5317 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5318 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5319 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5320 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5321 .port_pause_limit = mv88e6390_port_pause_limit, 5322 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5323 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5324 .port_get_cmode = mv88e6352_port_get_cmode, 5325 .port_set_cmode = mv88e6393x_port_set_cmode, 5326 .port_setup_message_port = mv88e6xxx_setup_message_port, 5327 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5328 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5329 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5330 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5331 .stats_get_strings = mv88e6320_stats_get_strings, 5332 .stats_get_stats = mv88e6390_stats_get_stats, 5333 /* .set_cpu_port is missing because this family does not support a global 5334 * CPU port, only per port CPU port which is set via 5335 * .port_set_upstream_port method. 5336 */ 5337 .set_egress_port = mv88e6393x_set_egress_port, 5338 .watchdog_ops = &mv88e6393x_watchdog_ops, 5339 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5340 .pot_clear = mv88e6xxx_g2_pot_clear, 5341 .reset = mv88e6352_g1_reset, 5342 .rmu_disable = mv88e6390_g1_rmu_disable, 5343 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5344 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5345 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5346 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5347 .stu_getnext = mv88e6390_g1_stu_getnext, 5348 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5349 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5350 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5351 /* TODO: serdes stats */ 5352 .gpio_ops = &mv88e6352_gpio_ops, 5353 .avb_ops = &mv88e6390_avb_ops, 5354 .ptp_ops = &mv88e6352_ptp_ops, 5355 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5356 .pcs_ops = &mv88e6393x_pcs_ops, 5357 }; 5358 5359 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5360 [MV88E6020] = { 5361 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5362 .family = MV88E6XXX_FAMILY_6250, 5363 .name = "Marvell 88E6020", 5364 .num_databases = 64, 5365 .num_ports = 4, 5366 .num_internal_phys = 2, 5367 .max_vid = 4095, 5368 .port_base_addr = 0x8, 5369 .phy_base_addr = 0x0, 5370 .global1_addr = 0xf, 5371 .global2_addr = 0x7, 5372 .age_time_coeff = 15000, 5373 .g1_irqs = 9, 5374 .g2_irqs = 5, 5375 .atu_move_port_mask = 0xf, 5376 .dual_chip = true, 5377 .ops = &mv88e6250_ops, 5378 }, 5379 5380 [MV88E6071] = { 5381 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5382 .family = MV88E6XXX_FAMILY_6250, 5383 .name = "Marvell 88E6071", 5384 .num_databases = 64, 5385 .num_ports = 7, 5386 .num_internal_phys = 5, 5387 .max_vid = 4095, 5388 .port_base_addr = 0x08, 5389 .phy_base_addr = 0x00, 5390 .global1_addr = 0x0f, 5391 .global2_addr = 0x07, 5392 .age_time_coeff = 15000, 5393 .g1_irqs = 9, 5394 .g2_irqs = 5, 5395 .atu_move_port_mask = 0xf, 5396 .dual_chip = true, 5397 .ops = &mv88e6250_ops, 5398 }, 5399 5400 [MV88E6085] = { 5401 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5402 .family = MV88E6XXX_FAMILY_6097, 5403 .name = "Marvell 88E6085", 5404 .num_databases = 4096, 5405 .num_macs = 8192, 5406 .num_ports = 10, 5407 .num_internal_phys = 5, 5408 .max_vid = 4095, 5409 .max_sid = 63, 5410 .port_base_addr = 0x10, 5411 .phy_base_addr = 0x0, 5412 .global1_addr = 0x1b, 5413 .global2_addr = 0x1c, 5414 .age_time_coeff = 15000, 5415 .g1_irqs = 8, 5416 .g2_irqs = 10, 5417 .atu_move_port_mask = 0xf, 5418 .pvt = true, 5419 .multi_chip = true, 5420 .ops = &mv88e6085_ops, 5421 }, 5422 5423 [MV88E6095] = { 5424 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5425 .family = MV88E6XXX_FAMILY_6095, 5426 .name = "Marvell 88E6095/88E6095F", 5427 .num_databases = 256, 5428 .num_macs = 8192, 5429 .num_ports = 11, 5430 .num_internal_phys = 0, 5431 .max_vid = 4095, 5432 .port_base_addr = 0x10, 5433 .phy_base_addr = 0x0, 5434 .global1_addr = 0x1b, 5435 .global2_addr = 0x1c, 5436 .age_time_coeff = 15000, 5437 .g1_irqs = 8, 5438 .atu_move_port_mask = 0xf, 5439 .multi_chip = true, 5440 .ops = &mv88e6095_ops, 5441 }, 5442 5443 [MV88E6097] = { 5444 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5445 .family = MV88E6XXX_FAMILY_6097, 5446 .name = "Marvell 88E6097/88E6097F", 5447 .num_databases = 4096, 5448 .num_macs = 8192, 5449 .num_ports = 11, 5450 .num_internal_phys = 8, 5451 .max_vid = 4095, 5452 .max_sid = 63, 5453 .port_base_addr = 0x10, 5454 .phy_base_addr = 0x0, 5455 .global1_addr = 0x1b, 5456 .global2_addr = 0x1c, 5457 .age_time_coeff = 15000, 5458 .g1_irqs = 8, 5459 .g2_irqs = 10, 5460 .atu_move_port_mask = 0xf, 5461 .pvt = true, 5462 .multi_chip = true, 5463 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5464 .ops = &mv88e6097_ops, 5465 }, 5466 5467 [MV88E6123] = { 5468 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5469 .family = MV88E6XXX_FAMILY_6165, 5470 .name = "Marvell 88E6123", 5471 .num_databases = 4096, 5472 .num_macs = 1024, 5473 .num_ports = 3, 5474 .num_internal_phys = 5, 5475 .max_vid = 4095, 5476 .max_sid = 63, 5477 .port_base_addr = 0x10, 5478 .phy_base_addr = 0x0, 5479 .global1_addr = 0x1b, 5480 .global2_addr = 0x1c, 5481 .age_time_coeff = 15000, 5482 .g1_irqs = 9, 5483 .g2_irqs = 10, 5484 .atu_move_port_mask = 0xf, 5485 .pvt = true, 5486 .multi_chip = true, 5487 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5488 .ops = &mv88e6123_ops, 5489 }, 5490 5491 [MV88E6131] = { 5492 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5493 .family = MV88E6XXX_FAMILY_6185, 5494 .name = "Marvell 88E6131", 5495 .num_databases = 256, 5496 .num_macs = 8192, 5497 .num_ports = 8, 5498 .num_internal_phys = 0, 5499 .max_vid = 4095, 5500 .port_base_addr = 0x10, 5501 .phy_base_addr = 0x0, 5502 .global1_addr = 0x1b, 5503 .global2_addr = 0x1c, 5504 .age_time_coeff = 15000, 5505 .g1_irqs = 9, 5506 .atu_move_port_mask = 0xf, 5507 .multi_chip = true, 5508 .ops = &mv88e6131_ops, 5509 }, 5510 5511 [MV88E6141] = { 5512 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5513 .family = MV88E6XXX_FAMILY_6341, 5514 .name = "Marvell 88E6141", 5515 .num_databases = 4096, 5516 .num_macs = 2048, 5517 .num_ports = 6, 5518 .num_internal_phys = 5, 5519 .num_gpio = 11, 5520 .max_vid = 4095, 5521 .max_sid = 63, 5522 .port_base_addr = 0x10, 5523 .phy_base_addr = 0x10, 5524 .global1_addr = 0x1b, 5525 .global2_addr = 0x1c, 5526 .age_time_coeff = 3750, 5527 .atu_move_port_mask = 0x1f, 5528 .g1_irqs = 9, 5529 .g2_irqs = 10, 5530 .pvt = true, 5531 .multi_chip = true, 5532 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5533 .ops = &mv88e6141_ops, 5534 }, 5535 5536 [MV88E6161] = { 5537 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5538 .family = MV88E6XXX_FAMILY_6165, 5539 .name = "Marvell 88E6161", 5540 .num_databases = 4096, 5541 .num_macs = 1024, 5542 .num_ports = 6, 5543 .num_internal_phys = 5, 5544 .max_vid = 4095, 5545 .max_sid = 63, 5546 .port_base_addr = 0x10, 5547 .phy_base_addr = 0x0, 5548 .global1_addr = 0x1b, 5549 .global2_addr = 0x1c, 5550 .age_time_coeff = 15000, 5551 .g1_irqs = 9, 5552 .g2_irqs = 10, 5553 .atu_move_port_mask = 0xf, 5554 .pvt = true, 5555 .multi_chip = true, 5556 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5557 .ptp_support = true, 5558 .ops = &mv88e6161_ops, 5559 }, 5560 5561 [MV88E6165] = { 5562 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5563 .family = MV88E6XXX_FAMILY_6165, 5564 .name = "Marvell 88E6165", 5565 .num_databases = 4096, 5566 .num_macs = 8192, 5567 .num_ports = 6, 5568 .num_internal_phys = 0, 5569 .max_vid = 4095, 5570 .max_sid = 63, 5571 .port_base_addr = 0x10, 5572 .phy_base_addr = 0x0, 5573 .global1_addr = 0x1b, 5574 .global2_addr = 0x1c, 5575 .age_time_coeff = 15000, 5576 .g1_irqs = 9, 5577 .g2_irqs = 10, 5578 .atu_move_port_mask = 0xf, 5579 .pvt = true, 5580 .multi_chip = true, 5581 .ptp_support = true, 5582 .ops = &mv88e6165_ops, 5583 }, 5584 5585 [MV88E6171] = { 5586 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5587 .family = MV88E6XXX_FAMILY_6351, 5588 .name = "Marvell 88E6171", 5589 .num_databases = 4096, 5590 .num_macs = 8192, 5591 .num_ports = 7, 5592 .num_internal_phys = 5, 5593 .max_vid = 4095, 5594 .max_sid = 63, 5595 .port_base_addr = 0x10, 5596 .phy_base_addr = 0x0, 5597 .global1_addr = 0x1b, 5598 .global2_addr = 0x1c, 5599 .age_time_coeff = 15000, 5600 .g1_irqs = 9, 5601 .g2_irqs = 10, 5602 .atu_move_port_mask = 0xf, 5603 .pvt = true, 5604 .multi_chip = true, 5605 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5606 .ops = &mv88e6171_ops, 5607 }, 5608 5609 [MV88E6172] = { 5610 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5611 .family = MV88E6XXX_FAMILY_6352, 5612 .name = "Marvell 88E6172", 5613 .num_databases = 4096, 5614 .num_macs = 8192, 5615 .num_ports = 7, 5616 .num_internal_phys = 5, 5617 .num_gpio = 15, 5618 .max_vid = 4095, 5619 .max_sid = 63, 5620 .port_base_addr = 0x10, 5621 .phy_base_addr = 0x0, 5622 .global1_addr = 0x1b, 5623 .global2_addr = 0x1c, 5624 .age_time_coeff = 15000, 5625 .g1_irqs = 9, 5626 .g2_irqs = 10, 5627 .atu_move_port_mask = 0xf, 5628 .pvt = true, 5629 .multi_chip = true, 5630 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5631 .ops = &mv88e6172_ops, 5632 }, 5633 5634 [MV88E6175] = { 5635 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5636 .family = MV88E6XXX_FAMILY_6351, 5637 .name = "Marvell 88E6175", 5638 .num_databases = 4096, 5639 .num_macs = 8192, 5640 .num_ports = 7, 5641 .num_internal_phys = 5, 5642 .max_vid = 4095, 5643 .max_sid = 63, 5644 .port_base_addr = 0x10, 5645 .phy_base_addr = 0x0, 5646 .global1_addr = 0x1b, 5647 .global2_addr = 0x1c, 5648 .age_time_coeff = 15000, 5649 .g1_irqs = 9, 5650 .g2_irqs = 10, 5651 .atu_move_port_mask = 0xf, 5652 .pvt = true, 5653 .multi_chip = true, 5654 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5655 .ops = &mv88e6175_ops, 5656 }, 5657 5658 [MV88E6176] = { 5659 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5660 .family = MV88E6XXX_FAMILY_6352, 5661 .name = "Marvell 88E6176", 5662 .num_databases = 4096, 5663 .num_macs = 8192, 5664 .num_ports = 7, 5665 .num_internal_phys = 5, 5666 .num_gpio = 15, 5667 .max_vid = 4095, 5668 .max_sid = 63, 5669 .port_base_addr = 0x10, 5670 .phy_base_addr = 0x0, 5671 .global1_addr = 0x1b, 5672 .global2_addr = 0x1c, 5673 .age_time_coeff = 15000, 5674 .g1_irqs = 9, 5675 .g2_irqs = 10, 5676 .atu_move_port_mask = 0xf, 5677 .pvt = true, 5678 .multi_chip = true, 5679 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5680 .ops = &mv88e6176_ops, 5681 }, 5682 5683 [MV88E6185] = { 5684 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5685 .family = MV88E6XXX_FAMILY_6185, 5686 .name = "Marvell 88E6185", 5687 .num_databases = 256, 5688 .num_macs = 8192, 5689 .num_ports = 10, 5690 .num_internal_phys = 0, 5691 .max_vid = 4095, 5692 .port_base_addr = 0x10, 5693 .phy_base_addr = 0x0, 5694 .global1_addr = 0x1b, 5695 .global2_addr = 0x1c, 5696 .age_time_coeff = 15000, 5697 .g1_irqs = 8, 5698 .atu_move_port_mask = 0xf, 5699 .multi_chip = true, 5700 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5701 .ops = &mv88e6185_ops, 5702 }, 5703 5704 [MV88E6190] = { 5705 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5706 .family = MV88E6XXX_FAMILY_6390, 5707 .name = "Marvell 88E6190", 5708 .num_databases = 4096, 5709 .num_macs = 16384, 5710 .num_ports = 11, /* 10 + Z80 */ 5711 .num_internal_phys = 9, 5712 .num_gpio = 16, 5713 .max_vid = 8191, 5714 .max_sid = 63, 5715 .port_base_addr = 0x0, 5716 .phy_base_addr = 0x0, 5717 .global1_addr = 0x1b, 5718 .global2_addr = 0x1c, 5719 .age_time_coeff = 3750, 5720 .g1_irqs = 9, 5721 .g2_irqs = 14, 5722 .pvt = true, 5723 .multi_chip = true, 5724 .atu_move_port_mask = 0x1f, 5725 .ops = &mv88e6190_ops, 5726 }, 5727 5728 [MV88E6190X] = { 5729 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5730 .family = MV88E6XXX_FAMILY_6390, 5731 .name = "Marvell 88E6190X", 5732 .num_databases = 4096, 5733 .num_macs = 16384, 5734 .num_ports = 11, /* 10 + Z80 */ 5735 .num_internal_phys = 9, 5736 .num_gpio = 16, 5737 .max_vid = 8191, 5738 .max_sid = 63, 5739 .port_base_addr = 0x0, 5740 .phy_base_addr = 0x0, 5741 .global1_addr = 0x1b, 5742 .global2_addr = 0x1c, 5743 .age_time_coeff = 3750, 5744 .g1_irqs = 9, 5745 .g2_irqs = 14, 5746 .atu_move_port_mask = 0x1f, 5747 .pvt = true, 5748 .multi_chip = true, 5749 .ops = &mv88e6190x_ops, 5750 }, 5751 5752 [MV88E6191] = { 5753 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5754 .family = MV88E6XXX_FAMILY_6390, 5755 .name = "Marvell 88E6191", 5756 .num_databases = 4096, 5757 .num_macs = 16384, 5758 .num_ports = 11, /* 10 + Z80 */ 5759 .num_internal_phys = 9, 5760 .max_vid = 8191, 5761 .max_sid = 63, 5762 .port_base_addr = 0x0, 5763 .phy_base_addr = 0x0, 5764 .global1_addr = 0x1b, 5765 .global2_addr = 0x1c, 5766 .age_time_coeff = 3750, 5767 .g1_irqs = 9, 5768 .g2_irqs = 14, 5769 .atu_move_port_mask = 0x1f, 5770 .pvt = true, 5771 .multi_chip = true, 5772 .ptp_support = true, 5773 .ops = &mv88e6191_ops, 5774 }, 5775 5776 [MV88E6191X] = { 5777 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5778 .family = MV88E6XXX_FAMILY_6393, 5779 .name = "Marvell 88E6191X", 5780 .num_databases = 4096, 5781 .num_ports = 11, /* 10 + Z80 */ 5782 .num_internal_phys = 8, 5783 .internal_phys_offset = 1, 5784 .max_vid = 8191, 5785 .max_sid = 63, 5786 .port_base_addr = 0x0, 5787 .phy_base_addr = 0x0, 5788 .global1_addr = 0x1b, 5789 .global2_addr = 0x1c, 5790 .age_time_coeff = 3750, 5791 .g1_irqs = 10, 5792 .g2_irqs = 14, 5793 .atu_move_port_mask = 0x1f, 5794 .pvt = true, 5795 .multi_chip = true, 5796 .ptp_support = true, 5797 .ops = &mv88e6393x_ops, 5798 }, 5799 5800 [MV88E6193X] = { 5801 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5802 .family = MV88E6XXX_FAMILY_6393, 5803 .name = "Marvell 88E6193X", 5804 .num_databases = 4096, 5805 .num_ports = 11, /* 10 + Z80 */ 5806 .num_internal_phys = 8, 5807 .internal_phys_offset = 1, 5808 .max_vid = 8191, 5809 .max_sid = 63, 5810 .port_base_addr = 0x0, 5811 .phy_base_addr = 0x0, 5812 .global1_addr = 0x1b, 5813 .global2_addr = 0x1c, 5814 .age_time_coeff = 3750, 5815 .g1_irqs = 10, 5816 .g2_irqs = 14, 5817 .atu_move_port_mask = 0x1f, 5818 .pvt = true, 5819 .multi_chip = true, 5820 .ptp_support = true, 5821 .ops = &mv88e6393x_ops, 5822 }, 5823 5824 [MV88E6220] = { 5825 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5826 .family = MV88E6XXX_FAMILY_6250, 5827 .name = "Marvell 88E6220", 5828 .num_databases = 64, 5829 5830 /* Ports 2-4 are not routed to pins 5831 * => usable ports 0, 1, 5, 6 5832 */ 5833 .num_ports = 7, 5834 .num_internal_phys = 2, 5835 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5836 .max_vid = 4095, 5837 .port_base_addr = 0x08, 5838 .phy_base_addr = 0x00, 5839 .global1_addr = 0x0f, 5840 .global2_addr = 0x07, 5841 .age_time_coeff = 15000, 5842 .g1_irqs = 9, 5843 .g2_irqs = 10, 5844 .atu_move_port_mask = 0xf, 5845 .dual_chip = true, 5846 .ptp_support = true, 5847 .ops = &mv88e6250_ops, 5848 }, 5849 5850 [MV88E6240] = { 5851 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5852 .family = MV88E6XXX_FAMILY_6352, 5853 .name = "Marvell 88E6240", 5854 .num_databases = 4096, 5855 .num_macs = 8192, 5856 .num_ports = 7, 5857 .num_internal_phys = 5, 5858 .num_gpio = 15, 5859 .max_vid = 4095, 5860 .max_sid = 63, 5861 .port_base_addr = 0x10, 5862 .phy_base_addr = 0x0, 5863 .global1_addr = 0x1b, 5864 .global2_addr = 0x1c, 5865 .age_time_coeff = 15000, 5866 .g1_irqs = 9, 5867 .g2_irqs = 10, 5868 .atu_move_port_mask = 0xf, 5869 .pvt = true, 5870 .multi_chip = true, 5871 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5872 .ptp_support = true, 5873 .ops = &mv88e6240_ops, 5874 }, 5875 5876 [MV88E6250] = { 5877 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5878 .family = MV88E6XXX_FAMILY_6250, 5879 .name = "Marvell 88E6250", 5880 .num_databases = 64, 5881 .num_ports = 7, 5882 .num_internal_phys = 5, 5883 .max_vid = 4095, 5884 .port_base_addr = 0x08, 5885 .phy_base_addr = 0x00, 5886 .global1_addr = 0x0f, 5887 .global2_addr = 0x07, 5888 .age_time_coeff = 15000, 5889 .g1_irqs = 9, 5890 .g2_irqs = 10, 5891 .atu_move_port_mask = 0xf, 5892 .dual_chip = true, 5893 .ptp_support = true, 5894 .ops = &mv88e6250_ops, 5895 }, 5896 5897 [MV88E6290] = { 5898 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5899 .family = MV88E6XXX_FAMILY_6390, 5900 .name = "Marvell 88E6290", 5901 .num_databases = 4096, 5902 .num_ports = 11, /* 10 + Z80 */ 5903 .num_internal_phys = 9, 5904 .num_gpio = 16, 5905 .max_vid = 8191, 5906 .max_sid = 63, 5907 .port_base_addr = 0x0, 5908 .phy_base_addr = 0x0, 5909 .global1_addr = 0x1b, 5910 .global2_addr = 0x1c, 5911 .age_time_coeff = 3750, 5912 .g1_irqs = 9, 5913 .g2_irqs = 14, 5914 .atu_move_port_mask = 0x1f, 5915 .pvt = true, 5916 .multi_chip = true, 5917 .ptp_support = true, 5918 .ops = &mv88e6290_ops, 5919 }, 5920 5921 [MV88E6320] = { 5922 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5923 .family = MV88E6XXX_FAMILY_6320, 5924 .name = "Marvell 88E6320", 5925 .num_databases = 4096, 5926 .num_macs = 8192, 5927 .num_ports = 7, 5928 .num_internal_phys = 5, 5929 .num_gpio = 15, 5930 .max_vid = 4095, 5931 .port_base_addr = 0x10, 5932 .phy_base_addr = 0x0, 5933 .global1_addr = 0x1b, 5934 .global2_addr = 0x1c, 5935 .age_time_coeff = 15000, 5936 .g1_irqs = 8, 5937 .g2_irqs = 10, 5938 .atu_move_port_mask = 0xf, 5939 .pvt = true, 5940 .multi_chip = true, 5941 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5942 .ptp_support = true, 5943 .ops = &mv88e6320_ops, 5944 }, 5945 5946 [MV88E6321] = { 5947 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5948 .family = MV88E6XXX_FAMILY_6320, 5949 .name = "Marvell 88E6321", 5950 .num_databases = 4096, 5951 .num_macs = 8192, 5952 .num_ports = 7, 5953 .num_internal_phys = 5, 5954 .num_gpio = 15, 5955 .max_vid = 4095, 5956 .port_base_addr = 0x10, 5957 .phy_base_addr = 0x0, 5958 .global1_addr = 0x1b, 5959 .global2_addr = 0x1c, 5960 .age_time_coeff = 15000, 5961 .g1_irqs = 8, 5962 .g2_irqs = 10, 5963 .atu_move_port_mask = 0xf, 5964 .multi_chip = true, 5965 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5966 .ptp_support = true, 5967 .ops = &mv88e6321_ops, 5968 }, 5969 5970 [MV88E6341] = { 5971 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5972 .family = MV88E6XXX_FAMILY_6341, 5973 .name = "Marvell 88E6341", 5974 .num_databases = 4096, 5975 .num_macs = 2048, 5976 .num_internal_phys = 5, 5977 .num_ports = 6, 5978 .num_gpio = 11, 5979 .max_vid = 4095, 5980 .max_sid = 63, 5981 .port_base_addr = 0x10, 5982 .phy_base_addr = 0x10, 5983 .global1_addr = 0x1b, 5984 .global2_addr = 0x1c, 5985 .age_time_coeff = 3750, 5986 .atu_move_port_mask = 0x1f, 5987 .g1_irqs = 9, 5988 .g2_irqs = 10, 5989 .pvt = true, 5990 .multi_chip = true, 5991 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5992 .ptp_support = true, 5993 .ops = &mv88e6341_ops, 5994 }, 5995 5996 [MV88E6350] = { 5997 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5998 .family = MV88E6XXX_FAMILY_6351, 5999 .name = "Marvell 88E6350", 6000 .num_databases = 4096, 6001 .num_macs = 8192, 6002 .num_ports = 7, 6003 .num_internal_phys = 5, 6004 .max_vid = 4095, 6005 .max_sid = 63, 6006 .port_base_addr = 0x10, 6007 .phy_base_addr = 0x0, 6008 .global1_addr = 0x1b, 6009 .global2_addr = 0x1c, 6010 .age_time_coeff = 15000, 6011 .g1_irqs = 9, 6012 .g2_irqs = 10, 6013 .atu_move_port_mask = 0xf, 6014 .pvt = true, 6015 .multi_chip = true, 6016 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6017 .ops = &mv88e6350_ops, 6018 }, 6019 6020 [MV88E6351] = { 6021 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6022 .family = MV88E6XXX_FAMILY_6351, 6023 .name = "Marvell 88E6351", 6024 .num_databases = 4096, 6025 .num_macs = 8192, 6026 .num_ports = 7, 6027 .num_internal_phys = 5, 6028 .max_vid = 4095, 6029 .max_sid = 63, 6030 .port_base_addr = 0x10, 6031 .phy_base_addr = 0x0, 6032 .global1_addr = 0x1b, 6033 .global2_addr = 0x1c, 6034 .age_time_coeff = 15000, 6035 .g1_irqs = 9, 6036 .g2_irqs = 10, 6037 .atu_move_port_mask = 0xf, 6038 .pvt = true, 6039 .multi_chip = true, 6040 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6041 .ops = &mv88e6351_ops, 6042 }, 6043 6044 [MV88E6352] = { 6045 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6046 .family = MV88E6XXX_FAMILY_6352, 6047 .name = "Marvell 88E6352", 6048 .num_databases = 4096, 6049 .num_macs = 8192, 6050 .num_ports = 7, 6051 .num_internal_phys = 5, 6052 .num_gpio = 15, 6053 .max_vid = 4095, 6054 .max_sid = 63, 6055 .port_base_addr = 0x10, 6056 .phy_base_addr = 0x0, 6057 .global1_addr = 0x1b, 6058 .global2_addr = 0x1c, 6059 .age_time_coeff = 15000, 6060 .g1_irqs = 9, 6061 .g2_irqs = 10, 6062 .atu_move_port_mask = 0xf, 6063 .pvt = true, 6064 .multi_chip = true, 6065 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6066 .ptp_support = true, 6067 .ops = &mv88e6352_ops, 6068 }, 6069 [MV88E6361] = { 6070 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6071 .family = MV88E6XXX_FAMILY_6393, 6072 .name = "Marvell 88E6361", 6073 .num_databases = 4096, 6074 .num_macs = 16384, 6075 .num_ports = 11, 6076 /* Ports 1, 2 and 8 are not routed */ 6077 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6078 .num_internal_phys = 5, 6079 .internal_phys_offset = 3, 6080 .max_vid = 4095, 6081 .max_sid = 63, 6082 .port_base_addr = 0x0, 6083 .phy_base_addr = 0x0, 6084 .global1_addr = 0x1b, 6085 .global2_addr = 0x1c, 6086 .age_time_coeff = 3750, 6087 .g1_irqs = 10, 6088 .g2_irqs = 14, 6089 .atu_move_port_mask = 0x1f, 6090 .pvt = true, 6091 .multi_chip = true, 6092 .ptp_support = true, 6093 .ops = &mv88e6393x_ops, 6094 }, 6095 [MV88E6390] = { 6096 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6097 .family = MV88E6XXX_FAMILY_6390, 6098 .name = "Marvell 88E6390", 6099 .num_databases = 4096, 6100 .num_macs = 16384, 6101 .num_ports = 11, /* 10 + Z80 */ 6102 .num_internal_phys = 9, 6103 .num_gpio = 16, 6104 .max_vid = 8191, 6105 .max_sid = 63, 6106 .port_base_addr = 0x0, 6107 .phy_base_addr = 0x0, 6108 .global1_addr = 0x1b, 6109 .global2_addr = 0x1c, 6110 .age_time_coeff = 3750, 6111 .g1_irqs = 9, 6112 .g2_irqs = 14, 6113 .atu_move_port_mask = 0x1f, 6114 .pvt = true, 6115 .multi_chip = true, 6116 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6117 .ptp_support = true, 6118 .ops = &mv88e6390_ops, 6119 }, 6120 [MV88E6390X] = { 6121 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6122 .family = MV88E6XXX_FAMILY_6390, 6123 .name = "Marvell 88E6390X", 6124 .num_databases = 4096, 6125 .num_macs = 16384, 6126 .num_ports = 11, /* 10 + Z80 */ 6127 .num_internal_phys = 9, 6128 .num_gpio = 16, 6129 .max_vid = 8191, 6130 .max_sid = 63, 6131 .port_base_addr = 0x0, 6132 .phy_base_addr = 0x0, 6133 .global1_addr = 0x1b, 6134 .global2_addr = 0x1c, 6135 .age_time_coeff = 3750, 6136 .g1_irqs = 9, 6137 .g2_irqs = 14, 6138 .atu_move_port_mask = 0x1f, 6139 .pvt = true, 6140 .multi_chip = true, 6141 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6142 .ptp_support = true, 6143 .ops = &mv88e6390x_ops, 6144 }, 6145 6146 [MV88E6393X] = { 6147 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6148 .family = MV88E6XXX_FAMILY_6393, 6149 .name = "Marvell 88E6393X", 6150 .num_databases = 4096, 6151 .num_ports = 11, /* 10 + Z80 */ 6152 .num_internal_phys = 8, 6153 .internal_phys_offset = 1, 6154 .max_vid = 8191, 6155 .max_sid = 63, 6156 .port_base_addr = 0x0, 6157 .phy_base_addr = 0x0, 6158 .global1_addr = 0x1b, 6159 .global2_addr = 0x1c, 6160 .age_time_coeff = 3750, 6161 .g1_irqs = 10, 6162 .g2_irqs = 14, 6163 .atu_move_port_mask = 0x1f, 6164 .pvt = true, 6165 .multi_chip = true, 6166 .ptp_support = true, 6167 .ops = &mv88e6393x_ops, 6168 }, 6169 }; 6170 6171 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6172 { 6173 int i; 6174 6175 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6176 if (mv88e6xxx_table[i].prod_num == prod_num) 6177 return &mv88e6xxx_table[i]; 6178 6179 return NULL; 6180 } 6181 6182 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6183 { 6184 const struct mv88e6xxx_info *info; 6185 unsigned int prod_num, rev; 6186 u16 id; 6187 int err; 6188 6189 mv88e6xxx_reg_lock(chip); 6190 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6191 mv88e6xxx_reg_unlock(chip); 6192 if (err) 6193 return err; 6194 6195 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6196 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6197 6198 info = mv88e6xxx_lookup_info(prod_num); 6199 if (!info) 6200 return -ENODEV; 6201 6202 /* Update the compatible info with the probed one */ 6203 chip->info = info; 6204 6205 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6206 chip->info->prod_num, chip->info->name, rev); 6207 6208 return 0; 6209 } 6210 6211 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6212 struct mdio_device *mdiodev) 6213 { 6214 int err; 6215 6216 /* dual_chip takes precedence over single/multi-chip modes */ 6217 if (chip->info->dual_chip) 6218 return -EINVAL; 6219 6220 /* If the mdio addr is 16 indicating the first port address of a switch 6221 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6222 * configured in single chip addressing mode. Setup the smi access as 6223 * single chip addressing mode and attempt to detect the model of the 6224 * switch, if this fails the device is not configured in single chip 6225 * addressing mode. 6226 */ 6227 if (mdiodev->addr != 16) 6228 return -EINVAL; 6229 6230 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6231 if (err) 6232 return err; 6233 6234 return mv88e6xxx_detect(chip); 6235 } 6236 6237 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6238 { 6239 struct mv88e6xxx_chip *chip; 6240 6241 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6242 if (!chip) 6243 return NULL; 6244 6245 chip->dev = dev; 6246 6247 mutex_init(&chip->reg_lock); 6248 INIT_LIST_HEAD(&chip->mdios); 6249 idr_init(&chip->policies); 6250 INIT_LIST_HEAD(&chip->msts); 6251 6252 return chip; 6253 } 6254 6255 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6256 int port, 6257 enum dsa_tag_protocol m) 6258 { 6259 struct mv88e6xxx_chip *chip = ds->priv; 6260 6261 return chip->tag_protocol; 6262 } 6263 6264 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6265 enum dsa_tag_protocol proto) 6266 { 6267 struct mv88e6xxx_chip *chip = ds->priv; 6268 enum dsa_tag_protocol old_protocol; 6269 struct dsa_port *cpu_dp; 6270 int err; 6271 6272 switch (proto) { 6273 case DSA_TAG_PROTO_EDSA: 6274 switch (chip->info->edsa_support) { 6275 case MV88E6XXX_EDSA_UNSUPPORTED: 6276 return -EPROTONOSUPPORT; 6277 case MV88E6XXX_EDSA_UNDOCUMENTED: 6278 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6279 fallthrough; 6280 case MV88E6XXX_EDSA_SUPPORTED: 6281 break; 6282 } 6283 break; 6284 case DSA_TAG_PROTO_DSA: 6285 break; 6286 default: 6287 return -EPROTONOSUPPORT; 6288 } 6289 6290 old_protocol = chip->tag_protocol; 6291 chip->tag_protocol = proto; 6292 6293 mv88e6xxx_reg_lock(chip); 6294 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6295 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6296 if (err) { 6297 mv88e6xxx_reg_unlock(chip); 6298 goto unwind; 6299 } 6300 } 6301 mv88e6xxx_reg_unlock(chip); 6302 6303 return 0; 6304 6305 unwind: 6306 chip->tag_protocol = old_protocol; 6307 6308 mv88e6xxx_reg_lock(chip); 6309 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6310 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6311 mv88e6xxx_reg_unlock(chip); 6312 6313 return err; 6314 } 6315 6316 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6317 const struct switchdev_obj_port_mdb *mdb, 6318 struct dsa_db db) 6319 { 6320 struct mv88e6xxx_chip *chip = ds->priv; 6321 int err; 6322 6323 mv88e6xxx_reg_lock(chip); 6324 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6325 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6326 mv88e6xxx_reg_unlock(chip); 6327 6328 return err; 6329 } 6330 6331 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6332 const struct switchdev_obj_port_mdb *mdb, 6333 struct dsa_db db) 6334 { 6335 struct mv88e6xxx_chip *chip = ds->priv; 6336 int err; 6337 6338 mv88e6xxx_reg_lock(chip); 6339 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6340 mv88e6xxx_reg_unlock(chip); 6341 6342 return err; 6343 } 6344 6345 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6346 struct dsa_mall_mirror_tc_entry *mirror, 6347 bool ingress, 6348 struct netlink_ext_ack *extack) 6349 { 6350 enum mv88e6xxx_egress_direction direction = ingress ? 6351 MV88E6XXX_EGRESS_DIR_INGRESS : 6352 MV88E6XXX_EGRESS_DIR_EGRESS; 6353 struct mv88e6xxx_chip *chip = ds->priv; 6354 bool other_mirrors = false; 6355 int i; 6356 int err; 6357 6358 mutex_lock(&chip->reg_lock); 6359 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6360 mirror->to_local_port) { 6361 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6362 other_mirrors |= ingress ? 6363 chip->ports[i].mirror_ingress : 6364 chip->ports[i].mirror_egress; 6365 6366 /* Can't change egress port when other mirror is active */ 6367 if (other_mirrors) { 6368 err = -EBUSY; 6369 goto out; 6370 } 6371 6372 err = mv88e6xxx_set_egress_port(chip, direction, 6373 mirror->to_local_port); 6374 if (err) 6375 goto out; 6376 } 6377 6378 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6379 out: 6380 mutex_unlock(&chip->reg_lock); 6381 6382 return err; 6383 } 6384 6385 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6386 struct dsa_mall_mirror_tc_entry *mirror) 6387 { 6388 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6389 MV88E6XXX_EGRESS_DIR_INGRESS : 6390 MV88E6XXX_EGRESS_DIR_EGRESS; 6391 struct mv88e6xxx_chip *chip = ds->priv; 6392 bool other_mirrors = false; 6393 int i; 6394 6395 mutex_lock(&chip->reg_lock); 6396 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6397 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6398 6399 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6400 other_mirrors |= mirror->ingress ? 6401 chip->ports[i].mirror_ingress : 6402 chip->ports[i].mirror_egress; 6403 6404 /* Reset egress port when no other mirror is active */ 6405 if (!other_mirrors) { 6406 if (mv88e6xxx_set_egress_port(chip, direction, 6407 dsa_upstream_port(ds, port))) 6408 dev_err(ds->dev, "failed to set egress port\n"); 6409 } 6410 6411 mutex_unlock(&chip->reg_lock); 6412 } 6413 6414 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6415 struct switchdev_brport_flags flags, 6416 struct netlink_ext_ack *extack) 6417 { 6418 struct mv88e6xxx_chip *chip = ds->priv; 6419 const struct mv88e6xxx_ops *ops; 6420 6421 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6422 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6423 return -EINVAL; 6424 6425 ops = chip->info->ops; 6426 6427 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6428 return -EINVAL; 6429 6430 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6431 return -EINVAL; 6432 6433 return 0; 6434 } 6435 6436 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6437 struct switchdev_brport_flags flags, 6438 struct netlink_ext_ack *extack) 6439 { 6440 struct mv88e6xxx_chip *chip = ds->priv; 6441 int err = 0; 6442 6443 mv88e6xxx_reg_lock(chip); 6444 6445 if (flags.mask & BR_LEARNING) { 6446 bool learning = !!(flags.val & BR_LEARNING); 6447 u16 pav = learning ? (1 << port) : 0; 6448 6449 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6450 if (err) 6451 goto out; 6452 } 6453 6454 if (flags.mask & BR_FLOOD) { 6455 bool unicast = !!(flags.val & BR_FLOOD); 6456 6457 err = chip->info->ops->port_set_ucast_flood(chip, port, 6458 unicast); 6459 if (err) 6460 goto out; 6461 } 6462 6463 if (flags.mask & BR_MCAST_FLOOD) { 6464 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6465 6466 err = chip->info->ops->port_set_mcast_flood(chip, port, 6467 multicast); 6468 if (err) 6469 goto out; 6470 } 6471 6472 if (flags.mask & BR_BCAST_FLOOD) { 6473 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6474 6475 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6476 if (err) 6477 goto out; 6478 } 6479 6480 if (flags.mask & BR_PORT_MAB) { 6481 bool mab = !!(flags.val & BR_PORT_MAB); 6482 6483 mv88e6xxx_port_set_mab(chip, port, mab); 6484 } 6485 6486 if (flags.mask & BR_PORT_LOCKED) { 6487 bool locked = !!(flags.val & BR_PORT_LOCKED); 6488 6489 err = mv88e6xxx_port_set_lock(chip, port, locked); 6490 if (err) 6491 goto out; 6492 } 6493 out: 6494 mv88e6xxx_reg_unlock(chip); 6495 6496 return err; 6497 } 6498 6499 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6500 struct dsa_lag lag, 6501 struct netdev_lag_upper_info *info, 6502 struct netlink_ext_ack *extack) 6503 { 6504 struct mv88e6xxx_chip *chip = ds->priv; 6505 struct dsa_port *dp; 6506 int members = 0; 6507 6508 if (!mv88e6xxx_has_lag(chip)) { 6509 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6510 return false; 6511 } 6512 6513 if (!lag.id) 6514 return false; 6515 6516 dsa_lag_foreach_port(dp, ds->dst, &lag) 6517 /* Includes the port joining the LAG */ 6518 members++; 6519 6520 if (members > 8) { 6521 NL_SET_ERR_MSG_MOD(extack, 6522 "Cannot offload more than 8 LAG ports"); 6523 return false; 6524 } 6525 6526 /* We could potentially relax this to include active 6527 * backup in the future. 6528 */ 6529 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6530 NL_SET_ERR_MSG_MOD(extack, 6531 "Can only offload LAG using hash TX type"); 6532 return false; 6533 } 6534 6535 /* Ideally we would also validate that the hash type matches 6536 * the hardware. Alas, this is always set to unknown on team 6537 * interfaces. 6538 */ 6539 return true; 6540 } 6541 6542 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6543 { 6544 struct mv88e6xxx_chip *chip = ds->priv; 6545 struct dsa_port *dp; 6546 u16 map = 0; 6547 int id; 6548 6549 /* DSA LAG IDs are one-based, hardware is zero-based */ 6550 id = lag.id - 1; 6551 6552 /* Build the map of all ports to distribute flows destined for 6553 * this LAG. This can be either a local user port, or a DSA 6554 * port if the LAG port is on a remote chip. 6555 */ 6556 dsa_lag_foreach_port(dp, ds->dst, &lag) 6557 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6558 6559 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6560 } 6561 6562 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6563 /* Row number corresponds to the number of active members in a 6564 * LAG. Each column states which of the eight hash buckets are 6565 * mapped to the column:th port in the LAG. 6566 * 6567 * Example: In a LAG with three active ports, the second port 6568 * ([2][1]) would be selected for traffic mapped to buckets 6569 * 3,4,5 (0x38). 6570 */ 6571 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6572 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6573 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6574 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6575 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6576 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6577 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6578 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6579 }; 6580 6581 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6582 int num_tx, int nth) 6583 { 6584 u8 active = 0; 6585 int i; 6586 6587 num_tx = num_tx <= 8 ? num_tx : 8; 6588 if (nth < num_tx) 6589 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6590 6591 for (i = 0; i < 8; i++) { 6592 if (BIT(i) & active) 6593 mask[i] |= BIT(port); 6594 } 6595 } 6596 6597 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6598 { 6599 struct mv88e6xxx_chip *chip = ds->priv; 6600 unsigned int id, num_tx; 6601 struct dsa_port *dp; 6602 struct dsa_lag *lag; 6603 int i, err, nth; 6604 u16 mask[8]; 6605 u16 ivec; 6606 6607 /* Assume no port is a member of any LAG. */ 6608 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6609 6610 /* Disable all masks for ports that _are_ members of a LAG. */ 6611 dsa_switch_for_each_port(dp, ds) { 6612 if (!dp->lag) 6613 continue; 6614 6615 ivec &= ~BIT(dp->index); 6616 } 6617 6618 for (i = 0; i < 8; i++) 6619 mask[i] = ivec; 6620 6621 /* Enable the correct subset of masks for all LAG ports that 6622 * are in the Tx set. 6623 */ 6624 dsa_lags_foreach_id(id, ds->dst) { 6625 lag = dsa_lag_by_id(ds->dst, id); 6626 if (!lag) 6627 continue; 6628 6629 num_tx = 0; 6630 dsa_lag_foreach_port(dp, ds->dst, lag) { 6631 if (dp->lag_tx_enabled) 6632 num_tx++; 6633 } 6634 6635 if (!num_tx) 6636 continue; 6637 6638 nth = 0; 6639 dsa_lag_foreach_port(dp, ds->dst, lag) { 6640 if (!dp->lag_tx_enabled) 6641 continue; 6642 6643 if (dp->ds == ds) 6644 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6645 num_tx, nth); 6646 6647 nth++; 6648 } 6649 } 6650 6651 for (i = 0; i < 8; i++) { 6652 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6653 if (err) 6654 return err; 6655 } 6656 6657 return 0; 6658 } 6659 6660 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6661 struct dsa_lag lag) 6662 { 6663 int err; 6664 6665 err = mv88e6xxx_lag_sync_masks(ds); 6666 6667 if (!err) 6668 err = mv88e6xxx_lag_sync_map(ds, lag); 6669 6670 return err; 6671 } 6672 6673 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6674 { 6675 struct mv88e6xxx_chip *chip = ds->priv; 6676 int err; 6677 6678 mv88e6xxx_reg_lock(chip); 6679 err = mv88e6xxx_lag_sync_masks(ds); 6680 mv88e6xxx_reg_unlock(chip); 6681 return err; 6682 } 6683 6684 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6685 struct dsa_lag lag, 6686 struct netdev_lag_upper_info *info, 6687 struct netlink_ext_ack *extack) 6688 { 6689 struct mv88e6xxx_chip *chip = ds->priv; 6690 int err, id; 6691 6692 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6693 return -EOPNOTSUPP; 6694 6695 /* DSA LAG IDs are one-based */ 6696 id = lag.id - 1; 6697 6698 mv88e6xxx_reg_lock(chip); 6699 6700 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6701 if (err) 6702 goto err_unlock; 6703 6704 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6705 if (err) 6706 goto err_clear_trunk; 6707 6708 mv88e6xxx_reg_unlock(chip); 6709 return 0; 6710 6711 err_clear_trunk: 6712 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6713 err_unlock: 6714 mv88e6xxx_reg_unlock(chip); 6715 return err; 6716 } 6717 6718 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6719 struct dsa_lag lag) 6720 { 6721 struct mv88e6xxx_chip *chip = ds->priv; 6722 int err_sync, err_trunk; 6723 6724 mv88e6xxx_reg_lock(chip); 6725 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6726 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6727 mv88e6xxx_reg_unlock(chip); 6728 return err_sync ? : err_trunk; 6729 } 6730 6731 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6732 int port) 6733 { 6734 struct mv88e6xxx_chip *chip = ds->priv; 6735 int err; 6736 6737 mv88e6xxx_reg_lock(chip); 6738 err = mv88e6xxx_lag_sync_masks(ds); 6739 mv88e6xxx_reg_unlock(chip); 6740 return err; 6741 } 6742 6743 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6744 int port, struct dsa_lag lag, 6745 struct netdev_lag_upper_info *info, 6746 struct netlink_ext_ack *extack) 6747 { 6748 struct mv88e6xxx_chip *chip = ds->priv; 6749 int err; 6750 6751 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6752 return -EOPNOTSUPP; 6753 6754 mv88e6xxx_reg_lock(chip); 6755 6756 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6757 if (err) 6758 goto unlock; 6759 6760 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6761 6762 unlock: 6763 mv88e6xxx_reg_unlock(chip); 6764 return err; 6765 } 6766 6767 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6768 int port, struct dsa_lag lag) 6769 { 6770 struct mv88e6xxx_chip *chip = ds->priv; 6771 int err_sync, err_pvt; 6772 6773 mv88e6xxx_reg_lock(chip); 6774 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6775 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6776 mv88e6xxx_reg_unlock(chip); 6777 return err_sync ? : err_pvt; 6778 } 6779 6780 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6781 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6782 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6783 .setup = mv88e6xxx_setup, 6784 .teardown = mv88e6xxx_teardown, 6785 .port_setup = mv88e6xxx_port_setup, 6786 .port_teardown = mv88e6xxx_port_teardown, 6787 .phylink_get_caps = mv88e6xxx_get_caps, 6788 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs, 6789 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 6790 .phylink_mac_config = mv88e6xxx_mac_config, 6791 .phylink_mac_finish = mv88e6xxx_mac_finish, 6792 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6793 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6794 .get_strings = mv88e6xxx_get_strings, 6795 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6796 .get_sset_count = mv88e6xxx_get_sset_count, 6797 .port_max_mtu = mv88e6xxx_get_max_mtu, 6798 .port_change_mtu = mv88e6xxx_change_mtu, 6799 .get_mac_eee = mv88e6xxx_get_mac_eee, 6800 .set_mac_eee = mv88e6xxx_set_mac_eee, 6801 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6802 .get_eeprom = mv88e6xxx_get_eeprom, 6803 .set_eeprom = mv88e6xxx_set_eeprom, 6804 .get_regs_len = mv88e6xxx_get_regs_len, 6805 .get_regs = mv88e6xxx_get_regs, 6806 .get_rxnfc = mv88e6xxx_get_rxnfc, 6807 .set_rxnfc = mv88e6xxx_set_rxnfc, 6808 .set_ageing_time = mv88e6xxx_set_ageing_time, 6809 .port_bridge_join = mv88e6xxx_port_bridge_join, 6810 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6811 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6812 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6813 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6814 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6815 .port_fast_age = mv88e6xxx_port_fast_age, 6816 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6817 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6818 .port_vlan_add = mv88e6xxx_port_vlan_add, 6819 .port_vlan_del = mv88e6xxx_port_vlan_del, 6820 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6821 .port_fdb_add = mv88e6xxx_port_fdb_add, 6822 .port_fdb_del = mv88e6xxx_port_fdb_del, 6823 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6824 .port_mdb_add = mv88e6xxx_port_mdb_add, 6825 .port_mdb_del = mv88e6xxx_port_mdb_del, 6826 .port_mirror_add = mv88e6xxx_port_mirror_add, 6827 .port_mirror_del = mv88e6xxx_port_mirror_del, 6828 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6829 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6830 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6831 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6832 .port_txtstamp = mv88e6xxx_port_txtstamp, 6833 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6834 .get_ts_info = mv88e6xxx_get_ts_info, 6835 .devlink_param_get = mv88e6xxx_devlink_param_get, 6836 .devlink_param_set = mv88e6xxx_devlink_param_set, 6837 .devlink_info_get = mv88e6xxx_devlink_info_get, 6838 .port_lag_change = mv88e6xxx_port_lag_change, 6839 .port_lag_join = mv88e6xxx_port_lag_join, 6840 .port_lag_leave = mv88e6xxx_port_lag_leave, 6841 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6842 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6843 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6844 }; 6845 6846 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6847 { 6848 struct device *dev = chip->dev; 6849 struct dsa_switch *ds; 6850 6851 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6852 if (!ds) 6853 return -ENOMEM; 6854 6855 ds->dev = dev; 6856 ds->num_ports = mv88e6xxx_num_ports(chip); 6857 ds->priv = chip; 6858 ds->dev = dev; 6859 ds->ops = &mv88e6xxx_switch_ops; 6860 ds->ageing_time_min = chip->info->age_time_coeff; 6861 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6862 6863 /* Some chips support up to 32, but that requires enabling the 6864 * 5-bit port mode, which we do not support. 640k^W16 ought to 6865 * be enough for anyone. 6866 */ 6867 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6868 6869 dev_set_drvdata(dev, ds); 6870 6871 return dsa_register_switch(ds); 6872 } 6873 6874 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6875 { 6876 dsa_unregister_switch(chip->ds); 6877 } 6878 6879 static const void *pdata_device_get_match_data(struct device *dev) 6880 { 6881 const struct of_device_id *matches = dev->driver->of_match_table; 6882 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6883 6884 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6885 matches++) { 6886 if (!strcmp(pdata->compatible, matches->compatible)) 6887 return matches->data; 6888 } 6889 return NULL; 6890 } 6891 6892 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6893 * would be lost after a power cycle so prevent it to be suspended. 6894 */ 6895 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6896 { 6897 return -EOPNOTSUPP; 6898 } 6899 6900 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6901 { 6902 return 0; 6903 } 6904 6905 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6906 6907 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6908 { 6909 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6910 const struct mv88e6xxx_info *compat_info = NULL; 6911 struct device *dev = &mdiodev->dev; 6912 struct device_node *np = dev->of_node; 6913 struct mv88e6xxx_chip *chip; 6914 int port; 6915 int err; 6916 6917 if (!np && !pdata) 6918 return -EINVAL; 6919 6920 if (np) 6921 compat_info = of_device_get_match_data(dev); 6922 6923 if (pdata) { 6924 compat_info = pdata_device_get_match_data(dev); 6925 6926 if (!pdata->netdev) 6927 return -EINVAL; 6928 6929 for (port = 0; port < DSA_MAX_PORTS; port++) { 6930 if (!(pdata->enabled_ports & (1 << port))) 6931 continue; 6932 if (strcmp(pdata->cd.port_names[port], "cpu")) 6933 continue; 6934 pdata->cd.netdev[port] = &pdata->netdev->dev; 6935 break; 6936 } 6937 } 6938 6939 if (!compat_info) 6940 return -EINVAL; 6941 6942 chip = mv88e6xxx_alloc_chip(dev); 6943 if (!chip) { 6944 err = -ENOMEM; 6945 goto out; 6946 } 6947 6948 chip->info = compat_info; 6949 6950 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6951 if (IS_ERR(chip->reset)) { 6952 err = PTR_ERR(chip->reset); 6953 goto out; 6954 } 6955 if (chip->reset) 6956 usleep_range(10000, 20000); 6957 6958 /* Detect if the device is configured in single chip addressing mode, 6959 * otherwise continue with address specific smi init/detection. 6960 */ 6961 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 6962 if (err) { 6963 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6964 if (err) 6965 goto out; 6966 6967 err = mv88e6xxx_detect(chip); 6968 if (err) 6969 goto out; 6970 } 6971 6972 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6973 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6974 else 6975 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6976 6977 mv88e6xxx_phy_init(chip); 6978 6979 if (chip->info->ops->get_eeprom) { 6980 if (np) 6981 of_property_read_u32(np, "eeprom-length", 6982 &chip->eeprom_len); 6983 else 6984 chip->eeprom_len = pdata->eeprom_len; 6985 } 6986 6987 mv88e6xxx_reg_lock(chip); 6988 err = mv88e6xxx_switch_reset(chip); 6989 mv88e6xxx_reg_unlock(chip); 6990 if (err) 6991 goto out; 6992 6993 if (np) { 6994 chip->irq = of_irq_get(np, 0); 6995 if (chip->irq == -EPROBE_DEFER) { 6996 err = chip->irq; 6997 goto out; 6998 } 6999 } 7000 7001 if (pdata) 7002 chip->irq = pdata->irq; 7003 7004 /* Has to be performed before the MDIO bus is created, because 7005 * the PHYs will link their interrupts to these interrupt 7006 * controllers 7007 */ 7008 mv88e6xxx_reg_lock(chip); 7009 if (chip->irq > 0) 7010 err = mv88e6xxx_g1_irq_setup(chip); 7011 else 7012 err = mv88e6xxx_irq_poll_setup(chip); 7013 mv88e6xxx_reg_unlock(chip); 7014 7015 if (err) 7016 goto out; 7017 7018 if (chip->info->g2_irqs > 0) { 7019 err = mv88e6xxx_g2_irq_setup(chip); 7020 if (err) 7021 goto out_g1_irq; 7022 } 7023 7024 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7025 if (err) 7026 goto out_g2_irq; 7027 7028 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7029 if (err) 7030 goto out_g1_atu_prob_irq; 7031 7032 err = mv88e6xxx_register_switch(chip); 7033 if (err) 7034 goto out_g1_vtu_prob_irq; 7035 7036 return 0; 7037 7038 out_g1_vtu_prob_irq: 7039 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7040 out_g1_atu_prob_irq: 7041 mv88e6xxx_g1_atu_prob_irq_free(chip); 7042 out_g2_irq: 7043 if (chip->info->g2_irqs > 0) 7044 mv88e6xxx_g2_irq_free(chip); 7045 out_g1_irq: 7046 if (chip->irq > 0) 7047 mv88e6xxx_g1_irq_free(chip); 7048 else 7049 mv88e6xxx_irq_poll_free(chip); 7050 out: 7051 if (pdata) 7052 dev_put(pdata->netdev); 7053 7054 return err; 7055 } 7056 7057 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7058 { 7059 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7060 struct mv88e6xxx_chip *chip; 7061 7062 if (!ds) 7063 return; 7064 7065 chip = ds->priv; 7066 7067 if (chip->info->ptp_support) { 7068 mv88e6xxx_hwtstamp_free(chip); 7069 mv88e6xxx_ptp_free(chip); 7070 } 7071 7072 mv88e6xxx_phy_destroy(chip); 7073 mv88e6xxx_unregister_switch(chip); 7074 7075 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7076 mv88e6xxx_g1_atu_prob_irq_free(chip); 7077 7078 if (chip->info->g2_irqs > 0) 7079 mv88e6xxx_g2_irq_free(chip); 7080 7081 if (chip->irq > 0) 7082 mv88e6xxx_g1_irq_free(chip); 7083 else 7084 mv88e6xxx_irq_poll_free(chip); 7085 } 7086 7087 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7088 { 7089 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7090 7091 if (!ds) 7092 return; 7093 7094 dsa_switch_shutdown(ds); 7095 7096 dev_set_drvdata(&mdiodev->dev, NULL); 7097 } 7098 7099 static const struct of_device_id mv88e6xxx_of_match[] = { 7100 { 7101 .compatible = "marvell,mv88e6085", 7102 .data = &mv88e6xxx_table[MV88E6085], 7103 }, 7104 { 7105 .compatible = "marvell,mv88e6190", 7106 .data = &mv88e6xxx_table[MV88E6190], 7107 }, 7108 { 7109 .compatible = "marvell,mv88e6250", 7110 .data = &mv88e6xxx_table[MV88E6250], 7111 }, 7112 { /* sentinel */ }, 7113 }; 7114 7115 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7116 7117 static struct mdio_driver mv88e6xxx_driver = { 7118 .probe = mv88e6xxx_probe, 7119 .remove = mv88e6xxx_remove, 7120 .shutdown = mv88e6xxx_shutdown, 7121 .mdiodrv.driver = { 7122 .name = "mv88e6085", 7123 .of_match_table = mv88e6xxx_of_match, 7124 .pm = &mv88e6xxx_pm_ops, 7125 }, 7126 }; 7127 7128 mdio_module_driver(mv88e6xxx_driver); 7129 7130 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7131 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7132 MODULE_LICENSE("GPL"); 7133