1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 7 * 8 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 9 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 36 #include "chip.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "phy.h" 40 #include "port.h" 41 #include "serdes.h" 42 43 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 44 { 45 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 46 dev_err(chip->dev, "Switch registers lock not held!\n"); 47 dump_stack(); 48 } 49 } 50 51 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 52 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 53 * 54 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 55 * is the only device connected to the SMI master. In this mode it responds to 56 * all 32 possible SMI addresses, and thus maps directly the internal devices. 57 * 58 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 59 * multiple devices to share the SMI interface. In this mode it responds to only 60 * 2 registers, used to indirectly access the internal SMI devices. 61 */ 62 63 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 64 int addr, int reg, u16 *val) 65 { 66 if (!chip->smi_ops) 67 return -EOPNOTSUPP; 68 69 return chip->smi_ops->read(chip, addr, reg, val); 70 } 71 72 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 73 int addr, int reg, u16 val) 74 { 75 if (!chip->smi_ops) 76 return -EOPNOTSUPP; 77 78 return chip->smi_ops->write(chip, addr, reg, val); 79 } 80 81 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 82 int addr, int reg, u16 *val) 83 { 84 int ret; 85 86 ret = mdiobus_read_nested(chip->bus, addr, reg); 87 if (ret < 0) 88 return ret; 89 90 *val = ret & 0xffff; 91 92 return 0; 93 } 94 95 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 96 int addr, int reg, u16 val) 97 { 98 int ret; 99 100 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 101 if (ret < 0) 102 return ret; 103 104 return 0; 105 } 106 107 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 108 .read = mv88e6xxx_smi_single_chip_read, 109 .write = mv88e6xxx_smi_single_chip_write, 110 }; 111 112 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 113 { 114 int ret; 115 int i; 116 117 for (i = 0; i < 16; i++) { 118 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 119 if (ret < 0) 120 return ret; 121 122 if ((ret & SMI_CMD_BUSY) == 0) 123 return 0; 124 } 125 126 return -ETIMEDOUT; 127 } 128 129 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 130 int addr, int reg, u16 *val) 131 { 132 int ret; 133 134 /* Wait for the bus to become free. */ 135 ret = mv88e6xxx_smi_multi_chip_wait(chip); 136 if (ret < 0) 137 return ret; 138 139 /* Transmit the read command. */ 140 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 141 SMI_CMD_OP_22_READ | (addr << 5) | reg); 142 if (ret < 0) 143 return ret; 144 145 /* Wait for the read command to complete. */ 146 ret = mv88e6xxx_smi_multi_chip_wait(chip); 147 if (ret < 0) 148 return ret; 149 150 /* Read the data. */ 151 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 152 if (ret < 0) 153 return ret; 154 155 *val = ret & 0xffff; 156 157 return 0; 158 } 159 160 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 161 int addr, int reg, u16 val) 162 { 163 int ret; 164 165 /* Wait for the bus to become free. */ 166 ret = mv88e6xxx_smi_multi_chip_wait(chip); 167 if (ret < 0) 168 return ret; 169 170 /* Transmit the data to write. */ 171 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 172 if (ret < 0) 173 return ret; 174 175 /* Transmit the write command. */ 176 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 177 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 178 if (ret < 0) 179 return ret; 180 181 /* Wait for the write command to complete. */ 182 ret = mv88e6xxx_smi_multi_chip_wait(chip); 183 if (ret < 0) 184 return ret; 185 186 return 0; 187 } 188 189 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 190 .read = mv88e6xxx_smi_multi_chip_read, 191 .write = mv88e6xxx_smi_multi_chip_write, 192 }; 193 194 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 195 { 196 int err; 197 198 assert_reg_lock(chip); 199 200 err = mv88e6xxx_smi_read(chip, addr, reg, val); 201 if (err) 202 return err; 203 204 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 205 addr, reg, *val); 206 207 return 0; 208 } 209 210 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 211 { 212 int err; 213 214 assert_reg_lock(chip); 215 216 err = mv88e6xxx_smi_write(chip, addr, reg, val); 217 if (err) 218 return err; 219 220 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 221 addr, reg, val); 222 223 return 0; 224 } 225 226 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 227 { 228 struct mv88e6xxx_mdio_bus *mdio_bus; 229 230 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 231 list); 232 if (!mdio_bus) 233 return NULL; 234 235 return mdio_bus->bus; 236 } 237 238 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 239 { 240 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 241 unsigned int n = d->hwirq; 242 243 chip->g1_irq.masked |= (1 << n); 244 } 245 246 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 247 { 248 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 249 unsigned int n = d->hwirq; 250 251 chip->g1_irq.masked &= ~(1 << n); 252 } 253 254 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 255 { 256 struct mv88e6xxx_chip *chip = dev_id; 257 unsigned int nhandled = 0; 258 unsigned int sub_irq; 259 unsigned int n; 260 u16 reg; 261 int err; 262 263 mutex_lock(&chip->reg_lock); 264 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 265 mutex_unlock(&chip->reg_lock); 266 267 if (err) 268 goto out; 269 270 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 271 if (reg & (1 << n)) { 272 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 273 handle_nested_irq(sub_irq); 274 ++nhandled; 275 } 276 } 277 out: 278 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 279 } 280 281 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 282 { 283 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 284 285 mutex_lock(&chip->reg_lock); 286 } 287 288 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 289 { 290 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 291 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 292 u16 reg; 293 int err; 294 295 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 296 if (err) 297 goto out; 298 299 reg &= ~mask; 300 reg |= (~chip->g1_irq.masked & mask); 301 302 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 303 if (err) 304 goto out; 305 306 out: 307 mutex_unlock(&chip->reg_lock); 308 } 309 310 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 311 .name = "mv88e6xxx-g1", 312 .irq_mask = mv88e6xxx_g1_irq_mask, 313 .irq_unmask = mv88e6xxx_g1_irq_unmask, 314 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 315 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 316 }; 317 318 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 319 unsigned int irq, 320 irq_hw_number_t hwirq) 321 { 322 struct mv88e6xxx_chip *chip = d->host_data; 323 324 irq_set_chip_data(irq, d->host_data); 325 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 326 irq_set_noprobe(irq); 327 328 return 0; 329 } 330 331 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 332 .map = mv88e6xxx_g1_irq_domain_map, 333 .xlate = irq_domain_xlate_twocell, 334 }; 335 336 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 337 { 338 int irq, virq; 339 u16 mask; 340 341 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 342 mask |= GENMASK(chip->g1_irq.nirqs, 0); 343 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 344 345 free_irq(chip->irq, chip); 346 347 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 348 virq = irq_find_mapping(chip->g1_irq.domain, irq); 349 irq_dispose_mapping(virq); 350 } 351 352 irq_domain_remove(chip->g1_irq.domain); 353 } 354 355 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 356 { 357 int err, irq, virq; 358 u16 reg, mask; 359 360 chip->g1_irq.nirqs = chip->info->g1_irqs; 361 chip->g1_irq.domain = irq_domain_add_simple( 362 NULL, chip->g1_irq.nirqs, 0, 363 &mv88e6xxx_g1_irq_domain_ops, chip); 364 if (!chip->g1_irq.domain) 365 return -ENOMEM; 366 367 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 368 irq_create_mapping(chip->g1_irq.domain, irq); 369 370 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 371 chip->g1_irq.masked = ~0; 372 373 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 374 if (err) 375 goto out_mapping; 376 377 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 378 379 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 380 if (err) 381 goto out_disable; 382 383 /* Reading the interrupt status clears (most of) them */ 384 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 385 if (err) 386 goto out_disable; 387 388 err = request_threaded_irq(chip->irq, NULL, 389 mv88e6xxx_g1_irq_thread_fn, 390 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 391 dev_name(chip->dev), chip); 392 if (err) 393 goto out_disable; 394 395 return 0; 396 397 out_disable: 398 mask |= GENMASK(chip->g1_irq.nirqs, 0); 399 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 400 401 out_mapping: 402 for (irq = 0; irq < 16; irq++) { 403 virq = irq_find_mapping(chip->g1_irq.domain, irq); 404 irq_dispose_mapping(virq); 405 } 406 407 irq_domain_remove(chip->g1_irq.domain); 408 409 return err; 410 } 411 412 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 413 { 414 int i; 415 416 for (i = 0; i < 16; i++) { 417 u16 val; 418 int err; 419 420 err = mv88e6xxx_read(chip, addr, reg, &val); 421 if (err) 422 return err; 423 424 if (!(val & mask)) 425 return 0; 426 427 usleep_range(1000, 2000); 428 } 429 430 dev_err(chip->dev, "Timeout while waiting for switch\n"); 431 return -ETIMEDOUT; 432 } 433 434 /* Indirect write to single pointer-data register with an Update bit */ 435 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 436 { 437 u16 val; 438 int err; 439 440 /* Wait until the previous operation is completed */ 441 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 442 if (err) 443 return err; 444 445 /* Set the Update bit to trigger a write operation */ 446 val = BIT(15) | update; 447 448 return mv88e6xxx_write(chip, addr, reg, val); 449 } 450 451 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 452 int link, int speed, int duplex, 453 phy_interface_t mode) 454 { 455 int err; 456 457 if (!chip->info->ops->port_set_link) 458 return 0; 459 460 /* Port's MAC control must not be changed unless the link is down */ 461 err = chip->info->ops->port_set_link(chip, port, 0); 462 if (err) 463 return err; 464 465 if (chip->info->ops->port_set_speed) { 466 err = chip->info->ops->port_set_speed(chip, port, speed); 467 if (err && err != -EOPNOTSUPP) 468 goto restore_link; 469 } 470 471 if (chip->info->ops->port_set_duplex) { 472 err = chip->info->ops->port_set_duplex(chip, port, duplex); 473 if (err && err != -EOPNOTSUPP) 474 goto restore_link; 475 } 476 477 if (chip->info->ops->port_set_rgmii_delay) { 478 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 479 if (err && err != -EOPNOTSUPP) 480 goto restore_link; 481 } 482 483 if (chip->info->ops->port_set_cmode) { 484 err = chip->info->ops->port_set_cmode(chip, port, mode); 485 if (err && err != -EOPNOTSUPP) 486 goto restore_link; 487 } 488 489 err = 0; 490 restore_link: 491 if (chip->info->ops->port_set_link(chip, port, link)) 492 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 493 494 return err; 495 } 496 497 /* We expect the switch to perform auto negotiation if there is a real 498 * phy. However, in the case of a fixed link phy, we force the port 499 * settings from the fixed link settings. 500 */ 501 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 502 struct phy_device *phydev) 503 { 504 struct mv88e6xxx_chip *chip = ds->priv; 505 int err; 506 507 if (!phy_is_pseudo_fixed_link(phydev)) 508 return; 509 510 mutex_lock(&chip->reg_lock); 511 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 512 phydev->duplex, phydev->interface); 513 mutex_unlock(&chip->reg_lock); 514 515 if (err && err != -EOPNOTSUPP) 516 dev_err(ds->dev, "p%d: failed to configure MAC\n", port); 517 } 518 519 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 520 { 521 if (!chip->info->ops->stats_snapshot) 522 return -EOPNOTSUPP; 523 524 return chip->info->ops->stats_snapshot(chip, port); 525 } 526 527 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 528 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 529 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 530 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 531 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 532 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 533 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 534 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 535 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 536 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 537 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 538 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 539 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 540 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 541 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 542 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 543 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 544 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 545 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 546 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 547 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 548 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 549 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 550 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 551 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 552 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 553 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 554 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 555 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 556 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 557 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 558 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 559 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 560 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 561 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 562 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 563 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 564 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 565 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 566 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 567 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 568 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 569 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 570 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 571 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 572 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 573 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 574 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 575 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 576 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 577 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 578 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 579 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 580 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 581 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 582 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 583 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 584 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 585 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 586 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 587 }; 588 589 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 590 struct mv88e6xxx_hw_stat *s, 591 int port, u16 bank1_select, 592 u16 histogram) 593 { 594 u32 low; 595 u32 high = 0; 596 u16 reg = 0; 597 int err; 598 u64 value; 599 600 switch (s->type) { 601 case STATS_TYPE_PORT: 602 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 603 if (err) 604 return UINT64_MAX; 605 606 low = reg; 607 if (s->sizeof_stat == 4) { 608 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 609 if (err) 610 return UINT64_MAX; 611 high = reg; 612 } 613 break; 614 case STATS_TYPE_BANK1: 615 reg = bank1_select; 616 /* fall through */ 617 case STATS_TYPE_BANK0: 618 reg |= s->reg | histogram; 619 mv88e6xxx_g1_stats_read(chip, reg, &low); 620 if (s->sizeof_stat == 8) 621 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 622 break; 623 default: 624 return UINT64_MAX; 625 } 626 value = (((u64)high) << 16) | low; 627 return value; 628 } 629 630 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 631 uint8_t *data, int types) 632 { 633 struct mv88e6xxx_hw_stat *stat; 634 int i, j; 635 636 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 637 stat = &mv88e6xxx_hw_stats[i]; 638 if (stat->type & types) { 639 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 640 ETH_GSTRING_LEN); 641 j++; 642 } 643 } 644 } 645 646 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 647 uint8_t *data) 648 { 649 mv88e6xxx_stats_get_strings(chip, data, 650 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 651 } 652 653 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 654 uint8_t *data) 655 { 656 mv88e6xxx_stats_get_strings(chip, data, 657 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 658 } 659 660 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 661 uint8_t *data) 662 { 663 struct mv88e6xxx_chip *chip = ds->priv; 664 665 if (chip->info->ops->stats_get_strings) 666 chip->info->ops->stats_get_strings(chip, data); 667 } 668 669 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 670 int types) 671 { 672 struct mv88e6xxx_hw_stat *stat; 673 int i, j; 674 675 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 676 stat = &mv88e6xxx_hw_stats[i]; 677 if (stat->type & types) 678 j++; 679 } 680 return j; 681 } 682 683 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 684 { 685 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 686 STATS_TYPE_PORT); 687 } 688 689 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 690 { 691 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 692 STATS_TYPE_BANK1); 693 } 694 695 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 696 { 697 struct mv88e6xxx_chip *chip = ds->priv; 698 699 if (chip->info->ops->stats_get_sset_count) 700 return chip->info->ops->stats_get_sset_count(chip); 701 702 return 0; 703 } 704 705 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 706 uint64_t *data, int types, 707 u16 bank1_select, u16 histogram) 708 { 709 struct mv88e6xxx_hw_stat *stat; 710 int i, j; 711 712 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 713 stat = &mv88e6xxx_hw_stats[i]; 714 if (stat->type & types) { 715 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 716 bank1_select, 717 histogram); 718 j++; 719 } 720 } 721 } 722 723 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 724 uint64_t *data) 725 { 726 return mv88e6xxx_stats_get_stats(chip, port, data, 727 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 728 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 729 } 730 731 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 732 uint64_t *data) 733 { 734 return mv88e6xxx_stats_get_stats(chip, port, data, 735 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 736 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 737 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 738 } 739 740 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 741 uint64_t *data) 742 { 743 return mv88e6xxx_stats_get_stats(chip, port, data, 744 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 745 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 746 0); 747 } 748 749 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 750 uint64_t *data) 751 { 752 if (chip->info->ops->stats_get_stats) 753 chip->info->ops->stats_get_stats(chip, port, data); 754 } 755 756 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 757 uint64_t *data) 758 { 759 struct mv88e6xxx_chip *chip = ds->priv; 760 int ret; 761 762 mutex_lock(&chip->reg_lock); 763 764 ret = mv88e6xxx_stats_snapshot(chip, port); 765 if (ret < 0) { 766 mutex_unlock(&chip->reg_lock); 767 return; 768 } 769 770 mv88e6xxx_get_stats(chip, port, data); 771 772 mutex_unlock(&chip->reg_lock); 773 } 774 775 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 776 { 777 if (chip->info->ops->stats_set_histogram) 778 return chip->info->ops->stats_set_histogram(chip); 779 780 return 0; 781 } 782 783 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 784 { 785 return 32 * sizeof(u16); 786 } 787 788 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 789 struct ethtool_regs *regs, void *_p) 790 { 791 struct mv88e6xxx_chip *chip = ds->priv; 792 int err; 793 u16 reg; 794 u16 *p = _p; 795 int i; 796 797 regs->version = 0; 798 799 memset(p, 0xff, 32 * sizeof(u16)); 800 801 mutex_lock(&chip->reg_lock); 802 803 for (i = 0; i < 32; i++) { 804 805 err = mv88e6xxx_port_read(chip, port, i, ®); 806 if (!err) 807 p[i] = reg; 808 } 809 810 mutex_unlock(&chip->reg_lock); 811 } 812 813 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 814 struct ethtool_eee *e) 815 { 816 /* Nothing to do on the port's MAC */ 817 return 0; 818 } 819 820 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 821 struct ethtool_eee *e) 822 { 823 /* Nothing to do on the port's MAC */ 824 return 0; 825 } 826 827 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 828 { 829 struct dsa_switch *ds = NULL; 830 struct net_device *br; 831 u16 pvlan; 832 int i; 833 834 if (dev < DSA_MAX_SWITCHES) 835 ds = chip->ds->dst->ds[dev]; 836 837 /* Prevent frames from unknown switch or port */ 838 if (!ds || port >= ds->num_ports) 839 return 0; 840 841 /* Frames from DSA links and CPU ports can egress any local port */ 842 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 843 return mv88e6xxx_port_mask(chip); 844 845 br = ds->ports[port].bridge_dev; 846 pvlan = 0; 847 848 /* Frames from user ports can egress any local DSA links and CPU ports, 849 * as well as any local member of their bridge group. 850 */ 851 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 852 if (dsa_is_cpu_port(chip->ds, i) || 853 dsa_is_dsa_port(chip->ds, i) || 854 (br && dsa_to_port(chip->ds, i)->bridge_dev == br)) 855 pvlan |= BIT(i); 856 857 return pvlan; 858 } 859 860 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 861 { 862 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 863 864 /* prevent frames from going back out of the port they came in on */ 865 output_ports &= ~BIT(port); 866 867 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 868 } 869 870 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 871 u8 state) 872 { 873 struct mv88e6xxx_chip *chip = ds->priv; 874 int err; 875 876 mutex_lock(&chip->reg_lock); 877 err = mv88e6xxx_port_set_state(chip, port, state); 878 mutex_unlock(&chip->reg_lock); 879 880 if (err) 881 dev_err(ds->dev, "p%d: failed to update state\n", port); 882 } 883 884 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 885 { 886 if (chip->info->ops->pot_clear) 887 return chip->info->ops->pot_clear(chip); 888 889 return 0; 890 } 891 892 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 893 { 894 if (chip->info->ops->mgmt_rsvd2cpu) 895 return chip->info->ops->mgmt_rsvd2cpu(chip); 896 897 return 0; 898 } 899 900 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 901 { 902 int err; 903 904 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 905 if (err) 906 return err; 907 908 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 909 if (err) 910 return err; 911 912 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 913 } 914 915 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 916 { 917 int port; 918 int err; 919 920 if (!chip->info->ops->irl_init_all) 921 return 0; 922 923 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 924 /* Disable ingress rate limiting by resetting all per port 925 * ingress rate limit resources to their initial state. 926 */ 927 err = chip->info->ops->irl_init_all(chip, port); 928 if (err) 929 return err; 930 } 931 932 return 0; 933 } 934 935 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 936 { 937 if (chip->info->ops->set_switch_mac) { 938 u8 addr[ETH_ALEN]; 939 940 eth_random_addr(addr); 941 942 return chip->info->ops->set_switch_mac(chip, addr); 943 } 944 945 return 0; 946 } 947 948 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 949 { 950 u16 pvlan = 0; 951 952 if (!mv88e6xxx_has_pvt(chip)) 953 return -EOPNOTSUPP; 954 955 /* Skip the local source device, which uses in-chip port VLAN */ 956 if (dev != chip->ds->index) 957 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 958 959 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 960 } 961 962 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 963 { 964 int dev, port; 965 int err; 966 967 if (!mv88e6xxx_has_pvt(chip)) 968 return 0; 969 970 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 971 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 972 */ 973 err = mv88e6xxx_g2_misc_4_bit_port(chip); 974 if (err) 975 return err; 976 977 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 978 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 979 err = mv88e6xxx_pvt_map(chip, dev, port); 980 if (err) 981 return err; 982 } 983 } 984 985 return 0; 986 } 987 988 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 989 { 990 struct mv88e6xxx_chip *chip = ds->priv; 991 int err; 992 993 mutex_lock(&chip->reg_lock); 994 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 995 mutex_unlock(&chip->reg_lock); 996 997 if (err) 998 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 999 } 1000 1001 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1002 { 1003 if (!chip->info->max_vid) 1004 return 0; 1005 1006 return mv88e6xxx_g1_vtu_flush(chip); 1007 } 1008 1009 static int mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1010 struct mv88e6xxx_vtu_entry *entry) 1011 { 1012 if (!chip->info->ops->vtu_getnext) 1013 return -EOPNOTSUPP; 1014 1015 return chip->info->ops->vtu_getnext(chip, entry); 1016 } 1017 1018 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1019 struct mv88e6xxx_vtu_entry *entry) 1020 { 1021 if (!chip->info->ops->vtu_loadpurge) 1022 return -EOPNOTSUPP; 1023 1024 return chip->info->ops->vtu_loadpurge(chip, entry); 1025 } 1026 1027 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1028 { 1029 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1030 struct mv88e6xxx_vtu_entry vlan = { 1031 .vid = chip->info->max_vid, 1032 }; 1033 int i, err; 1034 1035 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1036 1037 /* Set every FID bit used by the (un)bridged ports */ 1038 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1039 err = mv88e6xxx_port_get_fid(chip, i, fid); 1040 if (err) 1041 return err; 1042 1043 set_bit(*fid, fid_bitmap); 1044 } 1045 1046 /* Set every FID bit used by the VLAN entries */ 1047 do { 1048 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1049 if (err) 1050 return err; 1051 1052 if (!vlan.valid) 1053 break; 1054 1055 set_bit(vlan.fid, fid_bitmap); 1056 } while (vlan.vid < chip->info->max_vid); 1057 1058 /* The reset value 0x000 is used to indicate that multiple address 1059 * databases are not needed. Return the next positive available. 1060 */ 1061 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1062 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1063 return -ENOSPC; 1064 1065 /* Clear the database */ 1066 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1067 } 1068 1069 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1070 struct mv88e6xxx_vtu_entry *entry, bool new) 1071 { 1072 int err; 1073 1074 if (!vid) 1075 return -EINVAL; 1076 1077 entry->vid = vid - 1; 1078 entry->valid = false; 1079 1080 err = mv88e6xxx_vtu_getnext(chip, entry); 1081 if (err) 1082 return err; 1083 1084 if (entry->vid == vid && entry->valid) 1085 return 0; 1086 1087 if (new) { 1088 int i; 1089 1090 /* Initialize a fresh VLAN entry */ 1091 memset(entry, 0, sizeof(*entry)); 1092 entry->valid = true; 1093 entry->vid = vid; 1094 1095 /* Exclude all ports */ 1096 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1097 entry->member[i] = 1098 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1099 1100 return mv88e6xxx_atu_new(chip, &entry->fid); 1101 } 1102 1103 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1104 return -EOPNOTSUPP; 1105 } 1106 1107 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1108 u16 vid_begin, u16 vid_end) 1109 { 1110 struct mv88e6xxx_chip *chip = ds->priv; 1111 struct mv88e6xxx_vtu_entry vlan = { 1112 .vid = vid_begin - 1, 1113 }; 1114 int i, err; 1115 1116 /* DSA and CPU ports have to be members of multiple vlans */ 1117 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1118 return 0; 1119 1120 if (!vid_begin) 1121 return -EOPNOTSUPP; 1122 1123 mutex_lock(&chip->reg_lock); 1124 1125 do { 1126 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1127 if (err) 1128 goto unlock; 1129 1130 if (!vlan.valid) 1131 break; 1132 1133 if (vlan.vid > vid_end) 1134 break; 1135 1136 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1137 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1138 continue; 1139 1140 if (!ds->ports[port].slave) 1141 continue; 1142 1143 if (vlan.member[i] == 1144 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1145 continue; 1146 1147 if (dsa_to_port(ds, i)->bridge_dev == 1148 ds->ports[port].bridge_dev) 1149 break; /* same bridge, check next VLAN */ 1150 1151 if (!dsa_to_port(ds, i)->bridge_dev) 1152 continue; 1153 1154 dev_err(ds->dev, "p%d: hw VLAN %d already used by %s\n", 1155 port, vlan.vid, 1156 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1157 err = -EOPNOTSUPP; 1158 goto unlock; 1159 } 1160 } while (vlan.vid < vid_end); 1161 1162 unlock: 1163 mutex_unlock(&chip->reg_lock); 1164 1165 return err; 1166 } 1167 1168 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1169 bool vlan_filtering) 1170 { 1171 struct mv88e6xxx_chip *chip = ds->priv; 1172 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1173 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1174 int err; 1175 1176 if (!chip->info->max_vid) 1177 return -EOPNOTSUPP; 1178 1179 mutex_lock(&chip->reg_lock); 1180 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1181 mutex_unlock(&chip->reg_lock); 1182 1183 return err; 1184 } 1185 1186 static int 1187 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1188 const struct switchdev_obj_port_vlan *vlan, 1189 struct switchdev_trans *trans) 1190 { 1191 struct mv88e6xxx_chip *chip = ds->priv; 1192 int err; 1193 1194 if (!chip->info->max_vid) 1195 return -EOPNOTSUPP; 1196 1197 /* If the requested port doesn't belong to the same bridge as the VLAN 1198 * members, do not support it (yet) and fallback to software VLAN. 1199 */ 1200 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1201 vlan->vid_end); 1202 if (err) 1203 return err; 1204 1205 /* We don't need any dynamic resource from the kernel (yet), 1206 * so skip the prepare phase. 1207 */ 1208 return 0; 1209 } 1210 1211 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1212 u16 vid, u8 member) 1213 { 1214 struct mv88e6xxx_vtu_entry vlan; 1215 int err; 1216 1217 err = mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1218 if (err) 1219 return err; 1220 1221 vlan.member[port] = member; 1222 1223 return mv88e6xxx_vtu_loadpurge(chip, &vlan); 1224 } 1225 1226 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1227 const struct switchdev_obj_port_vlan *vlan, 1228 struct switchdev_trans *trans) 1229 { 1230 struct mv88e6xxx_chip *chip = ds->priv; 1231 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1232 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1233 u8 member; 1234 u16 vid; 1235 1236 if (!chip->info->max_vid) 1237 return; 1238 1239 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1240 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 1241 else if (untagged) 1242 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 1243 else 1244 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 1245 1246 mutex_lock(&chip->reg_lock); 1247 1248 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1249 if (_mv88e6xxx_port_vlan_add(chip, port, vid, member)) 1250 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 1251 vid, untagged ? 'u' : 't'); 1252 1253 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1254 dev_err(ds->dev, "p%d: failed to set PVID %d\n", port, 1255 vlan->vid_end); 1256 1257 mutex_unlock(&chip->reg_lock); 1258 } 1259 1260 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1261 int port, u16 vid) 1262 { 1263 struct mv88e6xxx_vtu_entry vlan; 1264 int i, err; 1265 1266 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1267 if (err) 1268 return err; 1269 1270 /* Tell switchdev if this VLAN is handled in software */ 1271 if (vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1272 return -EOPNOTSUPP; 1273 1274 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1275 1276 /* keep the VLAN unless all ports are excluded */ 1277 vlan.valid = false; 1278 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1279 if (vlan.member[i] != 1280 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1281 vlan.valid = true; 1282 break; 1283 } 1284 } 1285 1286 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 1287 if (err) 1288 return err; 1289 1290 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 1291 } 1292 1293 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1294 const struct switchdev_obj_port_vlan *vlan) 1295 { 1296 struct mv88e6xxx_chip *chip = ds->priv; 1297 u16 pvid, vid; 1298 int err = 0; 1299 1300 if (!chip->info->max_vid) 1301 return -EOPNOTSUPP; 1302 1303 mutex_lock(&chip->reg_lock); 1304 1305 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1306 if (err) 1307 goto unlock; 1308 1309 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1310 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1311 if (err) 1312 goto unlock; 1313 1314 if (vid == pvid) { 1315 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1316 if (err) 1317 goto unlock; 1318 } 1319 } 1320 1321 unlock: 1322 mutex_unlock(&chip->reg_lock); 1323 1324 return err; 1325 } 1326 1327 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1328 const unsigned char *addr, u16 vid, 1329 u8 state) 1330 { 1331 struct mv88e6xxx_vtu_entry vlan; 1332 struct mv88e6xxx_atu_entry entry; 1333 int err; 1334 1335 /* Null VLAN ID corresponds to the port private database */ 1336 if (vid == 0) 1337 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 1338 else 1339 err = mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1340 if (err) 1341 return err; 1342 1343 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1344 ether_addr_copy(entry.mac, addr); 1345 eth_addr_dec(entry.mac); 1346 1347 err = mv88e6xxx_g1_atu_getnext(chip, vlan.fid, &entry); 1348 if (err) 1349 return err; 1350 1351 /* Initialize a fresh ATU entry if it isn't found */ 1352 if (entry.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED || 1353 !ether_addr_equal(entry.mac, addr)) { 1354 memset(&entry, 0, sizeof(entry)); 1355 ether_addr_copy(entry.mac, addr); 1356 } 1357 1358 /* Purge the ATU entry only if no port is using it anymore */ 1359 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) { 1360 entry.portvec &= ~BIT(port); 1361 if (!entry.portvec) 1362 entry.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1363 } else { 1364 entry.portvec |= BIT(port); 1365 entry.state = state; 1366 } 1367 1368 return mv88e6xxx_g1_atu_loadpurge(chip, vlan.fid, &entry); 1369 } 1370 1371 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 1372 const unsigned char *addr, u16 vid) 1373 { 1374 struct mv88e6xxx_chip *chip = ds->priv; 1375 int err; 1376 1377 mutex_lock(&chip->reg_lock); 1378 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1379 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1380 mutex_unlock(&chip->reg_lock); 1381 1382 return err; 1383 } 1384 1385 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 1386 const unsigned char *addr, u16 vid) 1387 { 1388 struct mv88e6xxx_chip *chip = ds->priv; 1389 int err; 1390 1391 mutex_lock(&chip->reg_lock); 1392 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1393 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 1394 mutex_unlock(&chip->reg_lock); 1395 1396 return err; 1397 } 1398 1399 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 1400 u16 fid, u16 vid, int port, 1401 dsa_fdb_dump_cb_t *cb, void *data) 1402 { 1403 struct mv88e6xxx_atu_entry addr; 1404 bool is_static; 1405 int err; 1406 1407 addr.state = MV88E6XXX_G1_ATU_DATA_STATE_UNUSED; 1408 eth_broadcast_addr(addr.mac); 1409 1410 do { 1411 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 1412 if (err) 1413 return err; 1414 1415 if (addr.state == MV88E6XXX_G1_ATU_DATA_STATE_UNUSED) 1416 break; 1417 1418 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 1419 continue; 1420 1421 if (!is_unicast_ether_addr(addr.mac)) 1422 continue; 1423 1424 is_static = (addr.state == 1425 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 1426 err = cb(addr.mac, vid, is_static, data); 1427 if (err) 1428 return err; 1429 } while (!is_broadcast_ether_addr(addr.mac)); 1430 1431 return err; 1432 } 1433 1434 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 1435 dsa_fdb_dump_cb_t *cb, void *data) 1436 { 1437 struct mv88e6xxx_vtu_entry vlan = { 1438 .vid = chip->info->max_vid, 1439 }; 1440 u16 fid; 1441 int err; 1442 1443 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 1444 err = mv88e6xxx_port_get_fid(chip, port, &fid); 1445 if (err) 1446 return err; 1447 1448 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 1449 if (err) 1450 return err; 1451 1452 /* Dump VLANs' Filtering Information Databases */ 1453 do { 1454 err = mv88e6xxx_vtu_getnext(chip, &vlan); 1455 if (err) 1456 return err; 1457 1458 if (!vlan.valid) 1459 break; 1460 1461 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 1462 cb, data); 1463 if (err) 1464 return err; 1465 } while (vlan.vid < chip->info->max_vid); 1466 1467 return err; 1468 } 1469 1470 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 1471 dsa_fdb_dump_cb_t *cb, void *data) 1472 { 1473 struct mv88e6xxx_chip *chip = ds->priv; 1474 int err; 1475 1476 mutex_lock(&chip->reg_lock); 1477 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 1478 mutex_unlock(&chip->reg_lock); 1479 1480 return err; 1481 } 1482 1483 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 1484 struct net_device *br) 1485 { 1486 struct dsa_switch *ds; 1487 int port; 1488 int dev; 1489 int err; 1490 1491 /* Remap the Port VLAN of each local bridge group member */ 1492 for (port = 0; port < mv88e6xxx_num_ports(chip); ++port) { 1493 if (chip->ds->ports[port].bridge_dev == br) { 1494 err = mv88e6xxx_port_vlan_map(chip, port); 1495 if (err) 1496 return err; 1497 } 1498 } 1499 1500 if (!mv88e6xxx_has_pvt(chip)) 1501 return 0; 1502 1503 /* Remap the Port VLAN of each cross-chip bridge group member */ 1504 for (dev = 0; dev < DSA_MAX_SWITCHES; ++dev) { 1505 ds = chip->ds->dst->ds[dev]; 1506 if (!ds) 1507 break; 1508 1509 for (port = 0; port < ds->num_ports; ++port) { 1510 if (ds->ports[port].bridge_dev == br) { 1511 err = mv88e6xxx_pvt_map(chip, dev, port); 1512 if (err) 1513 return err; 1514 } 1515 } 1516 } 1517 1518 return 0; 1519 } 1520 1521 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 1522 struct net_device *br) 1523 { 1524 struct mv88e6xxx_chip *chip = ds->priv; 1525 int err; 1526 1527 mutex_lock(&chip->reg_lock); 1528 err = mv88e6xxx_bridge_map(chip, br); 1529 mutex_unlock(&chip->reg_lock); 1530 1531 return err; 1532 } 1533 1534 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 1535 struct net_device *br) 1536 { 1537 struct mv88e6xxx_chip *chip = ds->priv; 1538 1539 mutex_lock(&chip->reg_lock); 1540 if (mv88e6xxx_bridge_map(chip, br) || 1541 mv88e6xxx_port_vlan_map(chip, port)) 1542 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 1543 mutex_unlock(&chip->reg_lock); 1544 } 1545 1546 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, int dev, 1547 int port, struct net_device *br) 1548 { 1549 struct mv88e6xxx_chip *chip = ds->priv; 1550 int err; 1551 1552 if (!mv88e6xxx_has_pvt(chip)) 1553 return 0; 1554 1555 mutex_lock(&chip->reg_lock); 1556 err = mv88e6xxx_pvt_map(chip, dev, port); 1557 mutex_unlock(&chip->reg_lock); 1558 1559 return err; 1560 } 1561 1562 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, int dev, 1563 int port, struct net_device *br) 1564 { 1565 struct mv88e6xxx_chip *chip = ds->priv; 1566 1567 if (!mv88e6xxx_has_pvt(chip)) 1568 return; 1569 1570 mutex_lock(&chip->reg_lock); 1571 if (mv88e6xxx_pvt_map(chip, dev, port)) 1572 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 1573 mutex_unlock(&chip->reg_lock); 1574 } 1575 1576 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 1577 { 1578 if (chip->info->ops->reset) 1579 return chip->info->ops->reset(chip); 1580 1581 return 0; 1582 } 1583 1584 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 1585 { 1586 struct gpio_desc *gpiod = chip->reset; 1587 1588 /* If there is a GPIO connected to the reset pin, toggle it */ 1589 if (gpiod) { 1590 gpiod_set_value_cansleep(gpiod, 1); 1591 usleep_range(10000, 20000); 1592 gpiod_set_value_cansleep(gpiod, 0); 1593 usleep_range(10000, 20000); 1594 } 1595 } 1596 1597 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 1598 { 1599 int i, err; 1600 1601 /* Set all ports to the Disabled state */ 1602 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 1603 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 1604 if (err) 1605 return err; 1606 } 1607 1608 /* Wait for transmit queues to drain, 1609 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 1610 */ 1611 usleep_range(2000, 4000); 1612 1613 return 0; 1614 } 1615 1616 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 1617 { 1618 int err; 1619 1620 err = mv88e6xxx_disable_ports(chip); 1621 if (err) 1622 return err; 1623 1624 mv88e6xxx_hardware_reset(chip); 1625 1626 return mv88e6xxx_software_reset(chip); 1627 } 1628 1629 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 1630 enum mv88e6xxx_frame_mode frame, 1631 enum mv88e6xxx_egress_mode egress, u16 etype) 1632 { 1633 int err; 1634 1635 if (!chip->info->ops->port_set_frame_mode) 1636 return -EOPNOTSUPP; 1637 1638 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 1639 if (err) 1640 return err; 1641 1642 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 1643 if (err) 1644 return err; 1645 1646 if (chip->info->ops->port_set_ether_type) 1647 return chip->info->ops->port_set_ether_type(chip, port, etype); 1648 1649 return 0; 1650 } 1651 1652 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 1653 { 1654 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 1655 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1656 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1657 } 1658 1659 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 1660 { 1661 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 1662 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 1663 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 1664 } 1665 1666 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 1667 { 1668 return mv88e6xxx_set_port_mode(chip, port, 1669 MV88E6XXX_FRAME_MODE_ETHERTYPE, 1670 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 1671 ETH_P_EDSA); 1672 } 1673 1674 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 1675 { 1676 if (dsa_is_dsa_port(chip->ds, port)) 1677 return mv88e6xxx_set_port_mode_dsa(chip, port); 1678 1679 if (dsa_is_user_port(chip->ds, port)) 1680 return mv88e6xxx_set_port_mode_normal(chip, port); 1681 1682 /* Setup CPU port mode depending on its supported tag format */ 1683 if (chip->info->tag_protocol == DSA_TAG_PROTO_DSA) 1684 return mv88e6xxx_set_port_mode_dsa(chip, port); 1685 1686 if (chip->info->tag_protocol == DSA_TAG_PROTO_EDSA) 1687 return mv88e6xxx_set_port_mode_edsa(chip, port); 1688 1689 return -EINVAL; 1690 } 1691 1692 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 1693 { 1694 bool message = dsa_is_dsa_port(chip->ds, port); 1695 1696 return mv88e6xxx_port_set_message_port(chip, port, message); 1697 } 1698 1699 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 1700 { 1701 bool flood = port == dsa_upstream_port(chip->ds); 1702 1703 /* Upstream ports flood frames with unknown unicast or multicast DA */ 1704 if (chip->info->ops->port_set_egress_floods) 1705 return chip->info->ops->port_set_egress_floods(chip, port, 1706 flood, flood); 1707 1708 return 0; 1709 } 1710 1711 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 1712 bool on) 1713 { 1714 if (chip->info->ops->serdes_power) 1715 return chip->info->ops->serdes_power(chip, port, on); 1716 1717 return 0; 1718 } 1719 1720 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 1721 { 1722 struct dsa_switch *ds = chip->ds; 1723 int err; 1724 u16 reg; 1725 1726 /* MAC Forcing register: don't force link, speed, duplex or flow control 1727 * state to any particular values on physical ports, but force the CPU 1728 * port and all DSA ports to their maximum bandwidth and full duplex. 1729 */ 1730 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 1731 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 1732 SPEED_MAX, DUPLEX_FULL, 1733 PHY_INTERFACE_MODE_NA); 1734 else 1735 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 1736 SPEED_UNFORCED, DUPLEX_UNFORCED, 1737 PHY_INTERFACE_MODE_NA); 1738 if (err) 1739 return err; 1740 1741 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 1742 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 1743 * tunneling, determine priority by looking at 802.1p and IP 1744 * priority fields (IP prio has precedence), and set STP state 1745 * to Forwarding. 1746 * 1747 * If this is the CPU link, use DSA or EDSA tagging depending 1748 * on which tagging mode was configured. 1749 * 1750 * If this is a link to another switch, use DSA tagging mode. 1751 * 1752 * If this is the upstream port for this switch, enable 1753 * forwarding of unknown unicasts and multicasts. 1754 */ 1755 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 1756 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 1757 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1758 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 1759 if (err) 1760 return err; 1761 1762 err = mv88e6xxx_setup_port_mode(chip, port); 1763 if (err) 1764 return err; 1765 1766 err = mv88e6xxx_setup_egress_floods(chip, port); 1767 if (err) 1768 return err; 1769 1770 /* Enable the SERDES interface for DSA and CPU ports. Normal 1771 * ports SERDES are enabled when the port is enabled, thus 1772 * saving a bit of power. 1773 */ 1774 if ((dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port))) { 1775 err = mv88e6xxx_serdes_power(chip, port, true); 1776 if (err) 1777 return err; 1778 } 1779 1780 /* Port Control 2: don't force a good FCS, set the maximum frame size to 1781 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 1782 * untagged frames on this port, do a destination address lookup on all 1783 * received packets as usual, disable ARP mirroring and don't send a 1784 * copy of all transmitted/received frames on this port to the CPU. 1785 */ 1786 err = mv88e6xxx_port_set_map_da(chip, port); 1787 if (err) 1788 return err; 1789 1790 reg = 0; 1791 if (chip->info->ops->port_set_upstream_port) { 1792 err = chip->info->ops->port_set_upstream_port( 1793 chip, port, dsa_upstream_port(ds)); 1794 if (err) 1795 return err; 1796 } 1797 1798 err = mv88e6xxx_port_set_8021q_mode(chip, port, 1799 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 1800 if (err) 1801 return err; 1802 1803 if (chip->info->ops->port_set_jumbo_size) { 1804 err = chip->info->ops->port_set_jumbo_size(chip, port, 10240); 1805 if (err) 1806 return err; 1807 } 1808 1809 /* Port Association Vector: when learning source addresses 1810 * of packets, add the address to the address database using 1811 * a port bitmap that has only the bit for this port set and 1812 * the other bits clear. 1813 */ 1814 reg = 1 << port; 1815 /* Disable learning for CPU port */ 1816 if (dsa_is_cpu_port(ds, port)) 1817 reg = 0; 1818 1819 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 1820 reg); 1821 if (err) 1822 return err; 1823 1824 /* Egress rate control 2: disable egress rate control. */ 1825 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 1826 0x0000); 1827 if (err) 1828 return err; 1829 1830 if (chip->info->ops->port_pause_limit) { 1831 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 1832 if (err) 1833 return err; 1834 } 1835 1836 if (chip->info->ops->port_disable_learn_limit) { 1837 err = chip->info->ops->port_disable_learn_limit(chip, port); 1838 if (err) 1839 return err; 1840 } 1841 1842 if (chip->info->ops->port_disable_pri_override) { 1843 err = chip->info->ops->port_disable_pri_override(chip, port); 1844 if (err) 1845 return err; 1846 } 1847 1848 if (chip->info->ops->port_tag_remap) { 1849 err = chip->info->ops->port_tag_remap(chip, port); 1850 if (err) 1851 return err; 1852 } 1853 1854 if (chip->info->ops->port_egress_rate_limiting) { 1855 err = chip->info->ops->port_egress_rate_limiting(chip, port); 1856 if (err) 1857 return err; 1858 } 1859 1860 err = mv88e6xxx_setup_message_port(chip, port); 1861 if (err) 1862 return err; 1863 1864 /* Port based VLAN map: give each port the same default address 1865 * database, and allow bidirectional communication between the 1866 * CPU and DSA port(s), and the other ports. 1867 */ 1868 err = mv88e6xxx_port_set_fid(chip, port, 0); 1869 if (err) 1870 return err; 1871 1872 err = mv88e6xxx_port_vlan_map(chip, port); 1873 if (err) 1874 return err; 1875 1876 /* Default VLAN ID and priority: don't set a default VLAN 1877 * ID, and set the default packet priority to zero. 1878 */ 1879 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 1880 } 1881 1882 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 1883 struct phy_device *phydev) 1884 { 1885 struct mv88e6xxx_chip *chip = ds->priv; 1886 int err; 1887 1888 mutex_lock(&chip->reg_lock); 1889 err = mv88e6xxx_serdes_power(chip, port, true); 1890 mutex_unlock(&chip->reg_lock); 1891 1892 return err; 1893 } 1894 1895 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port, 1896 struct phy_device *phydev) 1897 { 1898 struct mv88e6xxx_chip *chip = ds->priv; 1899 1900 mutex_lock(&chip->reg_lock); 1901 if (mv88e6xxx_serdes_power(chip, port, false)) 1902 dev_err(chip->dev, "failed to power off SERDES\n"); 1903 mutex_unlock(&chip->reg_lock); 1904 } 1905 1906 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 1907 unsigned int ageing_time) 1908 { 1909 struct mv88e6xxx_chip *chip = ds->priv; 1910 int err; 1911 1912 mutex_lock(&chip->reg_lock); 1913 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 1914 mutex_unlock(&chip->reg_lock); 1915 1916 return err; 1917 } 1918 1919 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 1920 { 1921 struct dsa_switch *ds = chip->ds; 1922 u32 upstream_port = dsa_upstream_port(ds); 1923 int err; 1924 1925 if (chip->info->ops->set_cpu_port) { 1926 err = chip->info->ops->set_cpu_port(chip, upstream_port); 1927 if (err) 1928 return err; 1929 } 1930 1931 if (chip->info->ops->set_egress_port) { 1932 err = chip->info->ops->set_egress_port(chip, upstream_port); 1933 if (err) 1934 return err; 1935 } 1936 1937 /* Disable remote management, and set the switch's DSA device number. */ 1938 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL2, 1939 MV88E6XXX_G1_CTL2_MULTIPLE_CASCADE | 1940 (ds->index & 0x1f)); 1941 if (err) 1942 return err; 1943 1944 /* Configure the IP ToS mapping registers. */ 1945 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_0, 0x0000); 1946 if (err) 1947 return err; 1948 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_1, 0x0000); 1949 if (err) 1950 return err; 1951 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_2, 0x5555); 1952 if (err) 1953 return err; 1954 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_3, 0x5555); 1955 if (err) 1956 return err; 1957 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_4, 0xaaaa); 1958 if (err) 1959 return err; 1960 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_5, 0xaaaa); 1961 if (err) 1962 return err; 1963 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_6, 0xffff); 1964 if (err) 1965 return err; 1966 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IP_PRI_7, 0xffff); 1967 if (err) 1968 return err; 1969 1970 /* Configure the IEEE 802.1p priority mapping register. */ 1971 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_IEEE_PRI, 0xfa41); 1972 if (err) 1973 return err; 1974 1975 /* Initialize the statistics unit */ 1976 err = mv88e6xxx_stats_set_histogram(chip); 1977 if (err) 1978 return err; 1979 1980 /* Clear the statistics counters for all ports */ 1981 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_STATS_OP, 1982 MV88E6XXX_G1_STATS_OP_BUSY | 1983 MV88E6XXX_G1_STATS_OP_FLUSH_ALL); 1984 if (err) 1985 return err; 1986 1987 /* Wait for the flush to complete. */ 1988 err = mv88e6xxx_g1_stats_wait(chip); 1989 if (err) 1990 return err; 1991 1992 return 0; 1993 } 1994 1995 static int mv88e6xxx_setup(struct dsa_switch *ds) 1996 { 1997 struct mv88e6xxx_chip *chip = ds->priv; 1998 int err; 1999 int i; 2000 2001 chip->ds = ds; 2002 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2003 2004 mutex_lock(&chip->reg_lock); 2005 2006 /* Setup Switch Port Registers */ 2007 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2008 if (dsa_is_unused_port(ds, i)) 2009 continue; 2010 2011 err = mv88e6xxx_setup_port(chip, i); 2012 if (err) 2013 goto unlock; 2014 } 2015 2016 /* Setup Switch Global 1 Registers */ 2017 err = mv88e6xxx_g1_setup(chip); 2018 if (err) 2019 goto unlock; 2020 2021 /* Setup Switch Global 2 Registers */ 2022 if (chip->info->global2_addr) { 2023 err = mv88e6xxx_g2_setup(chip); 2024 if (err) 2025 goto unlock; 2026 } 2027 2028 err = mv88e6xxx_irl_setup(chip); 2029 if (err) 2030 goto unlock; 2031 2032 err = mv88e6xxx_mac_setup(chip); 2033 if (err) 2034 goto unlock; 2035 2036 err = mv88e6xxx_phy_setup(chip); 2037 if (err) 2038 goto unlock; 2039 2040 err = mv88e6xxx_vtu_setup(chip); 2041 if (err) 2042 goto unlock; 2043 2044 err = mv88e6xxx_pvt_setup(chip); 2045 if (err) 2046 goto unlock; 2047 2048 err = mv88e6xxx_atu_setup(chip); 2049 if (err) 2050 goto unlock; 2051 2052 err = mv88e6xxx_pot_setup(chip); 2053 if (err) 2054 goto unlock; 2055 2056 err = mv88e6xxx_rsvd2cpu_setup(chip); 2057 if (err) 2058 goto unlock; 2059 2060 unlock: 2061 mutex_unlock(&chip->reg_lock); 2062 2063 return err; 2064 } 2065 2066 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2067 { 2068 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2069 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2070 u16 val; 2071 int err; 2072 2073 if (!chip->info->ops->phy_read) 2074 return -EOPNOTSUPP; 2075 2076 mutex_lock(&chip->reg_lock); 2077 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2078 mutex_unlock(&chip->reg_lock); 2079 2080 if (reg == MII_PHYSID2) { 2081 /* Some internal PHYS don't have a model number. Use 2082 * the mv88e6390 family model number instead. 2083 */ 2084 if (!(val & 0x3f0)) 2085 val |= MV88E6XXX_PORT_SWITCH_ID_PROD_6390 >> 4; 2086 } 2087 2088 return err ? err : val; 2089 } 2090 2091 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2092 { 2093 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2094 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2095 int err; 2096 2097 if (!chip->info->ops->phy_write) 2098 return -EOPNOTSUPP; 2099 2100 mutex_lock(&chip->reg_lock); 2101 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2102 mutex_unlock(&chip->reg_lock); 2103 2104 return err; 2105 } 2106 2107 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2108 struct device_node *np, 2109 bool external) 2110 { 2111 static int index; 2112 struct mv88e6xxx_mdio_bus *mdio_bus; 2113 struct mii_bus *bus; 2114 int err; 2115 2116 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2117 if (!bus) 2118 return -ENOMEM; 2119 2120 mdio_bus = bus->priv; 2121 mdio_bus->bus = bus; 2122 mdio_bus->chip = chip; 2123 INIT_LIST_HEAD(&mdio_bus->list); 2124 mdio_bus->external = external; 2125 2126 if (np) { 2127 bus->name = np->full_name; 2128 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 2129 } else { 2130 bus->name = "mv88e6xxx SMI"; 2131 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2132 } 2133 2134 bus->read = mv88e6xxx_mdio_read; 2135 bus->write = mv88e6xxx_mdio_write; 2136 bus->parent = chip->dev; 2137 2138 if (np) 2139 err = of_mdiobus_register(bus, np); 2140 else 2141 err = mdiobus_register(bus); 2142 if (err) { 2143 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2144 return err; 2145 } 2146 2147 if (external) 2148 list_add_tail(&mdio_bus->list, &chip->mdios); 2149 else 2150 list_add(&mdio_bus->list, &chip->mdios); 2151 2152 return 0; 2153 } 2154 2155 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2156 { .compatible = "marvell,mv88e6xxx-mdio-external", 2157 .data = (void *)true }, 2158 { }, 2159 }; 2160 2161 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 2162 struct device_node *np) 2163 { 2164 const struct of_device_id *match; 2165 struct device_node *child; 2166 int err; 2167 2168 /* Always register one mdio bus for the internal/default mdio 2169 * bus. This maybe represented in the device tree, but is 2170 * optional. 2171 */ 2172 child = of_get_child_by_name(np, "mdio"); 2173 err = mv88e6xxx_mdio_register(chip, child, false); 2174 if (err) 2175 return err; 2176 2177 /* Walk the device tree, and see if there are any other nodes 2178 * which say they are compatible with the external mdio 2179 * bus. 2180 */ 2181 for_each_available_child_of_node(np, child) { 2182 match = of_match_node(mv88e6xxx_mdio_external_match, child); 2183 if (match) { 2184 err = mv88e6xxx_mdio_register(chip, child, true); 2185 if (err) 2186 return err; 2187 } 2188 } 2189 2190 return 0; 2191 } 2192 2193 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 2194 2195 { 2196 struct mv88e6xxx_mdio_bus *mdio_bus; 2197 struct mii_bus *bus; 2198 2199 list_for_each_entry(mdio_bus, &chip->mdios, list) { 2200 bus = mdio_bus->bus; 2201 2202 mdiobus_unregister(bus); 2203 } 2204 } 2205 2206 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 2207 { 2208 struct mv88e6xxx_chip *chip = ds->priv; 2209 2210 return chip->eeprom_len; 2211 } 2212 2213 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 2214 struct ethtool_eeprom *eeprom, u8 *data) 2215 { 2216 struct mv88e6xxx_chip *chip = ds->priv; 2217 int err; 2218 2219 if (!chip->info->ops->get_eeprom) 2220 return -EOPNOTSUPP; 2221 2222 mutex_lock(&chip->reg_lock); 2223 err = chip->info->ops->get_eeprom(chip, eeprom, data); 2224 mutex_unlock(&chip->reg_lock); 2225 2226 if (err) 2227 return err; 2228 2229 eeprom->magic = 0xc3ec4951; 2230 2231 return 0; 2232 } 2233 2234 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 2235 struct ethtool_eeprom *eeprom, u8 *data) 2236 { 2237 struct mv88e6xxx_chip *chip = ds->priv; 2238 int err; 2239 2240 if (!chip->info->ops->set_eeprom) 2241 return -EOPNOTSUPP; 2242 2243 if (eeprom->magic != 0xc3ec4951) 2244 return -EINVAL; 2245 2246 mutex_lock(&chip->reg_lock); 2247 err = chip->info->ops->set_eeprom(chip, eeprom, data); 2248 mutex_unlock(&chip->reg_lock); 2249 2250 return err; 2251 } 2252 2253 static const struct mv88e6xxx_ops mv88e6085_ops = { 2254 /* MV88E6XXX_FAMILY_6097 */ 2255 .irl_init_all = mv88e6352_g2_irl_init_all, 2256 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2257 .phy_read = mv88e6185_phy_ppu_read, 2258 .phy_write = mv88e6185_phy_ppu_write, 2259 .port_set_link = mv88e6xxx_port_set_link, 2260 .port_set_duplex = mv88e6xxx_port_set_duplex, 2261 .port_set_speed = mv88e6185_port_set_speed, 2262 .port_tag_remap = mv88e6095_port_tag_remap, 2263 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2264 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2265 .port_set_ether_type = mv88e6351_port_set_ether_type, 2266 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2267 .port_pause_limit = mv88e6097_port_pause_limit, 2268 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2269 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2270 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2271 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2272 .stats_get_strings = mv88e6095_stats_get_strings, 2273 .stats_get_stats = mv88e6095_stats_get_stats, 2274 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2275 .set_egress_port = mv88e6095_g1_set_egress_port, 2276 .watchdog_ops = &mv88e6097_watchdog_ops, 2277 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2278 .pot_clear = mv88e6xxx_g2_pot_clear, 2279 .ppu_enable = mv88e6185_g1_ppu_enable, 2280 .ppu_disable = mv88e6185_g1_ppu_disable, 2281 .reset = mv88e6185_g1_reset, 2282 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2283 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2284 }; 2285 2286 static const struct mv88e6xxx_ops mv88e6095_ops = { 2287 /* MV88E6XXX_FAMILY_6095 */ 2288 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2289 .phy_read = mv88e6185_phy_ppu_read, 2290 .phy_write = mv88e6185_phy_ppu_write, 2291 .port_set_link = mv88e6xxx_port_set_link, 2292 .port_set_duplex = mv88e6xxx_port_set_duplex, 2293 .port_set_speed = mv88e6185_port_set_speed, 2294 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2295 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2296 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2297 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2298 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2299 .stats_get_strings = mv88e6095_stats_get_strings, 2300 .stats_get_stats = mv88e6095_stats_get_stats, 2301 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2302 .ppu_enable = mv88e6185_g1_ppu_enable, 2303 .ppu_disable = mv88e6185_g1_ppu_disable, 2304 .reset = mv88e6185_g1_reset, 2305 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2306 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2307 }; 2308 2309 static const struct mv88e6xxx_ops mv88e6097_ops = { 2310 /* MV88E6XXX_FAMILY_6097 */ 2311 .irl_init_all = mv88e6352_g2_irl_init_all, 2312 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2313 .phy_read = mv88e6xxx_g2_smi_phy_read, 2314 .phy_write = mv88e6xxx_g2_smi_phy_write, 2315 .port_set_link = mv88e6xxx_port_set_link, 2316 .port_set_duplex = mv88e6xxx_port_set_duplex, 2317 .port_set_speed = mv88e6185_port_set_speed, 2318 .port_tag_remap = mv88e6095_port_tag_remap, 2319 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2320 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2321 .port_set_ether_type = mv88e6351_port_set_ether_type, 2322 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2323 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2324 .port_pause_limit = mv88e6097_port_pause_limit, 2325 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2326 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2327 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2328 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2329 .stats_get_strings = mv88e6095_stats_get_strings, 2330 .stats_get_stats = mv88e6095_stats_get_stats, 2331 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2332 .set_egress_port = mv88e6095_g1_set_egress_port, 2333 .watchdog_ops = &mv88e6097_watchdog_ops, 2334 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2335 .pot_clear = mv88e6xxx_g2_pot_clear, 2336 .reset = mv88e6352_g1_reset, 2337 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2338 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2339 }; 2340 2341 static const struct mv88e6xxx_ops mv88e6123_ops = { 2342 /* MV88E6XXX_FAMILY_6165 */ 2343 .irl_init_all = mv88e6352_g2_irl_init_all, 2344 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2345 .phy_read = mv88e6xxx_g2_smi_phy_read, 2346 .phy_write = mv88e6xxx_g2_smi_phy_write, 2347 .port_set_link = mv88e6xxx_port_set_link, 2348 .port_set_duplex = mv88e6xxx_port_set_duplex, 2349 .port_set_speed = mv88e6185_port_set_speed, 2350 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2351 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2352 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2353 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2354 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2355 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2356 .stats_get_strings = mv88e6095_stats_get_strings, 2357 .stats_get_stats = mv88e6095_stats_get_stats, 2358 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2359 .set_egress_port = mv88e6095_g1_set_egress_port, 2360 .watchdog_ops = &mv88e6097_watchdog_ops, 2361 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2362 .pot_clear = mv88e6xxx_g2_pot_clear, 2363 .reset = mv88e6352_g1_reset, 2364 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2365 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2366 }; 2367 2368 static const struct mv88e6xxx_ops mv88e6131_ops = { 2369 /* MV88E6XXX_FAMILY_6185 */ 2370 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2371 .phy_read = mv88e6185_phy_ppu_read, 2372 .phy_write = mv88e6185_phy_ppu_write, 2373 .port_set_link = mv88e6xxx_port_set_link, 2374 .port_set_duplex = mv88e6xxx_port_set_duplex, 2375 .port_set_speed = mv88e6185_port_set_speed, 2376 .port_tag_remap = mv88e6095_port_tag_remap, 2377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2378 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2379 .port_set_ether_type = mv88e6351_port_set_ether_type, 2380 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2381 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2383 .port_pause_limit = mv88e6097_port_pause_limit, 2384 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2385 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2386 .stats_get_strings = mv88e6095_stats_get_strings, 2387 .stats_get_stats = mv88e6095_stats_get_stats, 2388 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2389 .set_egress_port = mv88e6095_g1_set_egress_port, 2390 .watchdog_ops = &mv88e6097_watchdog_ops, 2391 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2392 .ppu_enable = mv88e6185_g1_ppu_enable, 2393 .ppu_disable = mv88e6185_g1_ppu_disable, 2394 .reset = mv88e6185_g1_reset, 2395 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2396 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2397 }; 2398 2399 static const struct mv88e6xxx_ops mv88e6141_ops = { 2400 /* MV88E6XXX_FAMILY_6341 */ 2401 .irl_init_all = mv88e6352_g2_irl_init_all, 2402 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2403 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2405 .phy_read = mv88e6xxx_g2_smi_phy_read, 2406 .phy_write = mv88e6xxx_g2_smi_phy_write, 2407 .port_set_link = mv88e6xxx_port_set_link, 2408 .port_set_duplex = mv88e6xxx_port_set_duplex, 2409 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2410 .port_set_speed = mv88e6390_port_set_speed, 2411 .port_tag_remap = mv88e6095_port_tag_remap, 2412 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2413 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2414 .port_set_ether_type = mv88e6351_port_set_ether_type, 2415 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2416 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2417 .port_pause_limit = mv88e6097_port_pause_limit, 2418 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2419 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2420 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2421 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2422 .stats_get_strings = mv88e6320_stats_get_strings, 2423 .stats_get_stats = mv88e6390_stats_get_stats, 2424 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2425 .set_egress_port = mv88e6390_g1_set_egress_port, 2426 .watchdog_ops = &mv88e6390_watchdog_ops, 2427 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2428 .pot_clear = mv88e6xxx_g2_pot_clear, 2429 .reset = mv88e6352_g1_reset, 2430 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2431 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2432 }; 2433 2434 static const struct mv88e6xxx_ops mv88e6161_ops = { 2435 /* MV88E6XXX_FAMILY_6165 */ 2436 .irl_init_all = mv88e6352_g2_irl_init_all, 2437 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2438 .phy_read = mv88e6xxx_g2_smi_phy_read, 2439 .phy_write = mv88e6xxx_g2_smi_phy_write, 2440 .port_set_link = mv88e6xxx_port_set_link, 2441 .port_set_duplex = mv88e6xxx_port_set_duplex, 2442 .port_set_speed = mv88e6185_port_set_speed, 2443 .port_tag_remap = mv88e6095_port_tag_remap, 2444 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2445 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2446 .port_set_ether_type = mv88e6351_port_set_ether_type, 2447 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2448 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2449 .port_pause_limit = mv88e6097_port_pause_limit, 2450 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2451 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2452 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2453 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2454 .stats_get_strings = mv88e6095_stats_get_strings, 2455 .stats_get_stats = mv88e6095_stats_get_stats, 2456 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2457 .set_egress_port = mv88e6095_g1_set_egress_port, 2458 .watchdog_ops = &mv88e6097_watchdog_ops, 2459 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2460 .pot_clear = mv88e6xxx_g2_pot_clear, 2461 .reset = mv88e6352_g1_reset, 2462 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2463 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2464 }; 2465 2466 static const struct mv88e6xxx_ops mv88e6165_ops = { 2467 /* MV88E6XXX_FAMILY_6165 */ 2468 .irl_init_all = mv88e6352_g2_irl_init_all, 2469 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2470 .phy_read = mv88e6165_phy_read, 2471 .phy_write = mv88e6165_phy_write, 2472 .port_set_link = mv88e6xxx_port_set_link, 2473 .port_set_duplex = mv88e6xxx_port_set_duplex, 2474 .port_set_speed = mv88e6185_port_set_speed, 2475 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2476 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2477 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2478 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2479 .stats_get_strings = mv88e6095_stats_get_strings, 2480 .stats_get_stats = mv88e6095_stats_get_stats, 2481 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2482 .set_egress_port = mv88e6095_g1_set_egress_port, 2483 .watchdog_ops = &mv88e6097_watchdog_ops, 2484 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2485 .pot_clear = mv88e6xxx_g2_pot_clear, 2486 .reset = mv88e6352_g1_reset, 2487 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2488 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2489 }; 2490 2491 static const struct mv88e6xxx_ops mv88e6171_ops = { 2492 /* MV88E6XXX_FAMILY_6351 */ 2493 .irl_init_all = mv88e6352_g2_irl_init_all, 2494 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2495 .phy_read = mv88e6xxx_g2_smi_phy_read, 2496 .phy_write = mv88e6xxx_g2_smi_phy_write, 2497 .port_set_link = mv88e6xxx_port_set_link, 2498 .port_set_duplex = mv88e6xxx_port_set_duplex, 2499 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2500 .port_set_speed = mv88e6185_port_set_speed, 2501 .port_tag_remap = mv88e6095_port_tag_remap, 2502 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2503 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2504 .port_set_ether_type = mv88e6351_port_set_ether_type, 2505 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2506 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2507 .port_pause_limit = mv88e6097_port_pause_limit, 2508 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2509 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2510 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2511 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2512 .stats_get_strings = mv88e6095_stats_get_strings, 2513 .stats_get_stats = mv88e6095_stats_get_stats, 2514 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2515 .set_egress_port = mv88e6095_g1_set_egress_port, 2516 .watchdog_ops = &mv88e6097_watchdog_ops, 2517 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2518 .pot_clear = mv88e6xxx_g2_pot_clear, 2519 .reset = mv88e6352_g1_reset, 2520 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2521 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2522 }; 2523 2524 static const struct mv88e6xxx_ops mv88e6172_ops = { 2525 /* MV88E6XXX_FAMILY_6352 */ 2526 .irl_init_all = mv88e6352_g2_irl_init_all, 2527 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2528 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2529 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2530 .phy_read = mv88e6xxx_g2_smi_phy_read, 2531 .phy_write = mv88e6xxx_g2_smi_phy_write, 2532 .port_set_link = mv88e6xxx_port_set_link, 2533 .port_set_duplex = mv88e6xxx_port_set_duplex, 2534 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2535 .port_set_speed = mv88e6352_port_set_speed, 2536 .port_tag_remap = mv88e6095_port_tag_remap, 2537 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2538 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2539 .port_set_ether_type = mv88e6351_port_set_ether_type, 2540 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2541 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2542 .port_pause_limit = mv88e6097_port_pause_limit, 2543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2545 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2546 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2547 .stats_get_strings = mv88e6095_stats_get_strings, 2548 .stats_get_stats = mv88e6095_stats_get_stats, 2549 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2550 .set_egress_port = mv88e6095_g1_set_egress_port, 2551 .watchdog_ops = &mv88e6097_watchdog_ops, 2552 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2553 .pot_clear = mv88e6xxx_g2_pot_clear, 2554 .reset = mv88e6352_g1_reset, 2555 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2556 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2557 .serdes_power = mv88e6352_serdes_power, 2558 }; 2559 2560 static const struct mv88e6xxx_ops mv88e6175_ops = { 2561 /* MV88E6XXX_FAMILY_6351 */ 2562 .irl_init_all = mv88e6352_g2_irl_init_all, 2563 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2564 .phy_read = mv88e6xxx_g2_smi_phy_read, 2565 .phy_write = mv88e6xxx_g2_smi_phy_write, 2566 .port_set_link = mv88e6xxx_port_set_link, 2567 .port_set_duplex = mv88e6xxx_port_set_duplex, 2568 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2569 .port_set_speed = mv88e6185_port_set_speed, 2570 .port_tag_remap = mv88e6095_port_tag_remap, 2571 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2572 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2573 .port_set_ether_type = mv88e6351_port_set_ether_type, 2574 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2575 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2576 .port_pause_limit = mv88e6097_port_pause_limit, 2577 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2578 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2579 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2580 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2581 .stats_get_strings = mv88e6095_stats_get_strings, 2582 .stats_get_stats = mv88e6095_stats_get_stats, 2583 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2584 .set_egress_port = mv88e6095_g1_set_egress_port, 2585 .watchdog_ops = &mv88e6097_watchdog_ops, 2586 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2587 .pot_clear = mv88e6xxx_g2_pot_clear, 2588 .reset = mv88e6352_g1_reset, 2589 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2590 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2591 }; 2592 2593 static const struct mv88e6xxx_ops mv88e6176_ops = { 2594 /* MV88E6XXX_FAMILY_6352 */ 2595 .irl_init_all = mv88e6352_g2_irl_init_all, 2596 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2597 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2598 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2599 .phy_read = mv88e6xxx_g2_smi_phy_read, 2600 .phy_write = mv88e6xxx_g2_smi_phy_write, 2601 .port_set_link = mv88e6xxx_port_set_link, 2602 .port_set_duplex = mv88e6xxx_port_set_duplex, 2603 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2604 .port_set_speed = mv88e6352_port_set_speed, 2605 .port_tag_remap = mv88e6095_port_tag_remap, 2606 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2607 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2608 .port_set_ether_type = mv88e6351_port_set_ether_type, 2609 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2610 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2611 .port_pause_limit = mv88e6097_port_pause_limit, 2612 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2613 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2614 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2615 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2616 .stats_get_strings = mv88e6095_stats_get_strings, 2617 .stats_get_stats = mv88e6095_stats_get_stats, 2618 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2619 .set_egress_port = mv88e6095_g1_set_egress_port, 2620 .watchdog_ops = &mv88e6097_watchdog_ops, 2621 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2622 .pot_clear = mv88e6xxx_g2_pot_clear, 2623 .reset = mv88e6352_g1_reset, 2624 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2625 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2626 .serdes_power = mv88e6352_serdes_power, 2627 }; 2628 2629 static const struct mv88e6xxx_ops mv88e6185_ops = { 2630 /* MV88E6XXX_FAMILY_6185 */ 2631 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 2632 .phy_read = mv88e6185_phy_ppu_read, 2633 .phy_write = mv88e6185_phy_ppu_write, 2634 .port_set_link = mv88e6xxx_port_set_link, 2635 .port_set_duplex = mv88e6xxx_port_set_duplex, 2636 .port_set_speed = mv88e6185_port_set_speed, 2637 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 2638 .port_set_egress_floods = mv88e6185_port_set_egress_floods, 2639 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 2640 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 2641 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 2642 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2643 .stats_get_strings = mv88e6095_stats_get_strings, 2644 .stats_get_stats = mv88e6095_stats_get_stats, 2645 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2646 .set_egress_port = mv88e6095_g1_set_egress_port, 2647 .watchdog_ops = &mv88e6097_watchdog_ops, 2648 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 2649 .ppu_enable = mv88e6185_g1_ppu_enable, 2650 .ppu_disable = mv88e6185_g1_ppu_disable, 2651 .reset = mv88e6185_g1_reset, 2652 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2653 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2654 }; 2655 2656 static const struct mv88e6xxx_ops mv88e6190_ops = { 2657 /* MV88E6XXX_FAMILY_6390 */ 2658 .irl_init_all = mv88e6390_g2_irl_init_all, 2659 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2660 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2661 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2662 .phy_read = mv88e6xxx_g2_smi_phy_read, 2663 .phy_write = mv88e6xxx_g2_smi_phy_write, 2664 .port_set_link = mv88e6xxx_port_set_link, 2665 .port_set_duplex = mv88e6xxx_port_set_duplex, 2666 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2667 .port_set_speed = mv88e6390_port_set_speed, 2668 .port_tag_remap = mv88e6390_port_tag_remap, 2669 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2670 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2671 .port_set_ether_type = mv88e6351_port_set_ether_type, 2672 .port_pause_limit = mv88e6390_port_pause_limit, 2673 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2674 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2675 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2676 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2677 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2678 .stats_get_strings = mv88e6320_stats_get_strings, 2679 .stats_get_stats = mv88e6390_stats_get_stats, 2680 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2681 .set_egress_port = mv88e6390_g1_set_egress_port, 2682 .watchdog_ops = &mv88e6390_watchdog_ops, 2683 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2684 .pot_clear = mv88e6xxx_g2_pot_clear, 2685 .reset = mv88e6352_g1_reset, 2686 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2687 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2688 .serdes_power = mv88e6390_serdes_power, 2689 }; 2690 2691 static const struct mv88e6xxx_ops mv88e6190x_ops = { 2692 /* MV88E6XXX_FAMILY_6390 */ 2693 .irl_init_all = mv88e6390_g2_irl_init_all, 2694 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2695 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2696 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2697 .phy_read = mv88e6xxx_g2_smi_phy_read, 2698 .phy_write = mv88e6xxx_g2_smi_phy_write, 2699 .port_set_link = mv88e6xxx_port_set_link, 2700 .port_set_duplex = mv88e6xxx_port_set_duplex, 2701 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2702 .port_set_speed = mv88e6390x_port_set_speed, 2703 .port_tag_remap = mv88e6390_port_tag_remap, 2704 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2705 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2706 .port_set_ether_type = mv88e6351_port_set_ether_type, 2707 .port_pause_limit = mv88e6390_port_pause_limit, 2708 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2709 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2710 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2711 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2712 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2713 .stats_get_strings = mv88e6320_stats_get_strings, 2714 .stats_get_stats = mv88e6390_stats_get_stats, 2715 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2716 .set_egress_port = mv88e6390_g1_set_egress_port, 2717 .watchdog_ops = &mv88e6390_watchdog_ops, 2718 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2719 .pot_clear = mv88e6xxx_g2_pot_clear, 2720 .reset = mv88e6352_g1_reset, 2721 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2722 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2723 .serdes_power = mv88e6390_serdes_power, 2724 }; 2725 2726 static const struct mv88e6xxx_ops mv88e6191_ops = { 2727 /* MV88E6XXX_FAMILY_6390 */ 2728 .irl_init_all = mv88e6390_g2_irl_init_all, 2729 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2730 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2731 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2732 .phy_read = mv88e6xxx_g2_smi_phy_read, 2733 .phy_write = mv88e6xxx_g2_smi_phy_write, 2734 .port_set_link = mv88e6xxx_port_set_link, 2735 .port_set_duplex = mv88e6xxx_port_set_duplex, 2736 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2737 .port_set_speed = mv88e6390_port_set_speed, 2738 .port_tag_remap = mv88e6390_port_tag_remap, 2739 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2740 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2741 .port_set_ether_type = mv88e6351_port_set_ether_type, 2742 .port_pause_limit = mv88e6390_port_pause_limit, 2743 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2744 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2745 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2746 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2747 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2748 .stats_get_strings = mv88e6320_stats_get_strings, 2749 .stats_get_stats = mv88e6390_stats_get_stats, 2750 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2751 .set_egress_port = mv88e6390_g1_set_egress_port, 2752 .watchdog_ops = &mv88e6390_watchdog_ops, 2753 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2754 .pot_clear = mv88e6xxx_g2_pot_clear, 2755 .reset = mv88e6352_g1_reset, 2756 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2757 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2758 .serdes_power = mv88e6390_serdes_power, 2759 }; 2760 2761 static const struct mv88e6xxx_ops mv88e6240_ops = { 2762 /* MV88E6XXX_FAMILY_6352 */ 2763 .irl_init_all = mv88e6352_g2_irl_init_all, 2764 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2765 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2766 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2767 .phy_read = mv88e6xxx_g2_smi_phy_read, 2768 .phy_write = mv88e6xxx_g2_smi_phy_write, 2769 .port_set_link = mv88e6xxx_port_set_link, 2770 .port_set_duplex = mv88e6xxx_port_set_duplex, 2771 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2772 .port_set_speed = mv88e6352_port_set_speed, 2773 .port_tag_remap = mv88e6095_port_tag_remap, 2774 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2775 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2776 .port_set_ether_type = mv88e6351_port_set_ether_type, 2777 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2778 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2779 .port_pause_limit = mv88e6097_port_pause_limit, 2780 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2781 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2782 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2783 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2784 .stats_get_strings = mv88e6095_stats_get_strings, 2785 .stats_get_stats = mv88e6095_stats_get_stats, 2786 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2787 .set_egress_port = mv88e6095_g1_set_egress_port, 2788 .watchdog_ops = &mv88e6097_watchdog_ops, 2789 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2790 .pot_clear = mv88e6xxx_g2_pot_clear, 2791 .reset = mv88e6352_g1_reset, 2792 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2793 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2794 .serdes_power = mv88e6352_serdes_power, 2795 }; 2796 2797 static const struct mv88e6xxx_ops mv88e6290_ops = { 2798 /* MV88E6XXX_FAMILY_6390 */ 2799 .irl_init_all = mv88e6390_g2_irl_init_all, 2800 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2801 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2802 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2803 .phy_read = mv88e6xxx_g2_smi_phy_read, 2804 .phy_write = mv88e6xxx_g2_smi_phy_write, 2805 .port_set_link = mv88e6xxx_port_set_link, 2806 .port_set_duplex = mv88e6xxx_port_set_duplex, 2807 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2808 .port_set_speed = mv88e6390_port_set_speed, 2809 .port_tag_remap = mv88e6390_port_tag_remap, 2810 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2811 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2812 .port_set_ether_type = mv88e6351_port_set_ether_type, 2813 .port_pause_limit = mv88e6390_port_pause_limit, 2814 .port_set_cmode = mv88e6390x_port_set_cmode, 2815 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2816 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2817 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2818 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 2819 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2820 .stats_get_strings = mv88e6320_stats_get_strings, 2821 .stats_get_stats = mv88e6390_stats_get_stats, 2822 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2823 .set_egress_port = mv88e6390_g1_set_egress_port, 2824 .watchdog_ops = &mv88e6390_watchdog_ops, 2825 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2826 .pot_clear = mv88e6xxx_g2_pot_clear, 2827 .reset = mv88e6352_g1_reset, 2828 .vtu_getnext = mv88e6390_g1_vtu_getnext, 2829 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 2830 .serdes_power = mv88e6390_serdes_power, 2831 }; 2832 2833 static const struct mv88e6xxx_ops mv88e6320_ops = { 2834 /* MV88E6XXX_FAMILY_6320 */ 2835 .irl_init_all = mv88e6352_g2_irl_init_all, 2836 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2837 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2838 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2839 .phy_read = mv88e6xxx_g2_smi_phy_read, 2840 .phy_write = mv88e6xxx_g2_smi_phy_write, 2841 .port_set_link = mv88e6xxx_port_set_link, 2842 .port_set_duplex = mv88e6xxx_port_set_duplex, 2843 .port_set_speed = mv88e6185_port_set_speed, 2844 .port_tag_remap = mv88e6095_port_tag_remap, 2845 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2846 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2847 .port_set_ether_type = mv88e6351_port_set_ether_type, 2848 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2849 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2850 .port_pause_limit = mv88e6097_port_pause_limit, 2851 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2852 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2853 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2854 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2855 .stats_get_strings = mv88e6320_stats_get_strings, 2856 .stats_get_stats = mv88e6320_stats_get_stats, 2857 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2858 .set_egress_port = mv88e6095_g1_set_egress_port, 2859 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2860 .pot_clear = mv88e6xxx_g2_pot_clear, 2861 .reset = mv88e6352_g1_reset, 2862 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2863 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2864 }; 2865 2866 static const struct mv88e6xxx_ops mv88e6321_ops = { 2867 /* MV88E6XXX_FAMILY_6320 */ 2868 .irl_init_all = mv88e6352_g2_irl_init_all, 2869 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 2870 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 2871 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2872 .phy_read = mv88e6xxx_g2_smi_phy_read, 2873 .phy_write = mv88e6xxx_g2_smi_phy_write, 2874 .port_set_link = mv88e6xxx_port_set_link, 2875 .port_set_duplex = mv88e6xxx_port_set_duplex, 2876 .port_set_speed = mv88e6185_port_set_speed, 2877 .port_tag_remap = mv88e6095_port_tag_remap, 2878 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2879 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2880 .port_set_ether_type = mv88e6351_port_set_ether_type, 2881 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2882 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2883 .port_pause_limit = mv88e6097_port_pause_limit, 2884 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2885 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2886 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2887 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2888 .stats_get_strings = mv88e6320_stats_get_strings, 2889 .stats_get_stats = mv88e6320_stats_get_stats, 2890 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2891 .set_egress_port = mv88e6095_g1_set_egress_port, 2892 .reset = mv88e6352_g1_reset, 2893 .vtu_getnext = mv88e6185_g1_vtu_getnext, 2894 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 2895 }; 2896 2897 static const struct mv88e6xxx_ops mv88e6341_ops = { 2898 /* MV88E6XXX_FAMILY_6341 */ 2899 .irl_init_all = mv88e6352_g2_irl_init_all, 2900 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 2901 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 2902 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2903 .phy_read = mv88e6xxx_g2_smi_phy_read, 2904 .phy_write = mv88e6xxx_g2_smi_phy_write, 2905 .port_set_link = mv88e6xxx_port_set_link, 2906 .port_set_duplex = mv88e6xxx_port_set_duplex, 2907 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 2908 .port_set_speed = mv88e6390_port_set_speed, 2909 .port_tag_remap = mv88e6095_port_tag_remap, 2910 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2911 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2912 .port_set_ether_type = mv88e6351_port_set_ether_type, 2913 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2914 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2915 .port_pause_limit = mv88e6097_port_pause_limit, 2916 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2917 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2918 .stats_snapshot = mv88e6390_g1_stats_snapshot, 2919 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 2920 .stats_get_strings = mv88e6320_stats_get_strings, 2921 .stats_get_stats = mv88e6390_stats_get_stats, 2922 .set_cpu_port = mv88e6390_g1_set_cpu_port, 2923 .set_egress_port = mv88e6390_g1_set_egress_port, 2924 .watchdog_ops = &mv88e6390_watchdog_ops, 2925 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 2926 .pot_clear = mv88e6xxx_g2_pot_clear, 2927 .reset = mv88e6352_g1_reset, 2928 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2929 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2930 }; 2931 2932 static const struct mv88e6xxx_ops mv88e6350_ops = { 2933 /* MV88E6XXX_FAMILY_6351 */ 2934 .irl_init_all = mv88e6352_g2_irl_init_all, 2935 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2936 .phy_read = mv88e6xxx_g2_smi_phy_read, 2937 .phy_write = mv88e6xxx_g2_smi_phy_write, 2938 .port_set_link = mv88e6xxx_port_set_link, 2939 .port_set_duplex = mv88e6xxx_port_set_duplex, 2940 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2941 .port_set_speed = mv88e6185_port_set_speed, 2942 .port_tag_remap = mv88e6095_port_tag_remap, 2943 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2944 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2945 .port_set_ether_type = mv88e6351_port_set_ether_type, 2946 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2947 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2948 .port_pause_limit = mv88e6097_port_pause_limit, 2949 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2950 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2951 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2952 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2953 .stats_get_strings = mv88e6095_stats_get_strings, 2954 .stats_get_stats = mv88e6095_stats_get_stats, 2955 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2956 .set_egress_port = mv88e6095_g1_set_egress_port, 2957 .watchdog_ops = &mv88e6097_watchdog_ops, 2958 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2959 .pot_clear = mv88e6xxx_g2_pot_clear, 2960 .reset = mv88e6352_g1_reset, 2961 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2962 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2963 }; 2964 2965 static const struct mv88e6xxx_ops mv88e6351_ops = { 2966 /* MV88E6XXX_FAMILY_6351 */ 2967 .irl_init_all = mv88e6352_g2_irl_init_all, 2968 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 2969 .phy_read = mv88e6xxx_g2_smi_phy_read, 2970 .phy_write = mv88e6xxx_g2_smi_phy_write, 2971 .port_set_link = mv88e6xxx_port_set_link, 2972 .port_set_duplex = mv88e6xxx_port_set_duplex, 2973 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 2974 .port_set_speed = mv88e6185_port_set_speed, 2975 .port_tag_remap = mv88e6095_port_tag_remap, 2976 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 2977 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 2978 .port_set_ether_type = mv88e6351_port_set_ether_type, 2979 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 2980 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 2981 .port_pause_limit = mv88e6097_port_pause_limit, 2982 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 2983 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 2984 .stats_snapshot = mv88e6320_g1_stats_snapshot, 2985 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 2986 .stats_get_strings = mv88e6095_stats_get_strings, 2987 .stats_get_stats = mv88e6095_stats_get_stats, 2988 .set_cpu_port = mv88e6095_g1_set_cpu_port, 2989 .set_egress_port = mv88e6095_g1_set_egress_port, 2990 .watchdog_ops = &mv88e6097_watchdog_ops, 2991 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 2992 .pot_clear = mv88e6xxx_g2_pot_clear, 2993 .reset = mv88e6352_g1_reset, 2994 .vtu_getnext = mv88e6352_g1_vtu_getnext, 2995 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 2996 }; 2997 2998 static const struct mv88e6xxx_ops mv88e6352_ops = { 2999 /* MV88E6XXX_FAMILY_6352 */ 3000 .irl_init_all = mv88e6352_g2_irl_init_all, 3001 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3002 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3003 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3004 .phy_read = mv88e6xxx_g2_smi_phy_read, 3005 .phy_write = mv88e6xxx_g2_smi_phy_write, 3006 .port_set_link = mv88e6xxx_port_set_link, 3007 .port_set_duplex = mv88e6xxx_port_set_duplex, 3008 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3009 .port_set_speed = mv88e6352_port_set_speed, 3010 .port_tag_remap = mv88e6095_port_tag_remap, 3011 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3012 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3013 .port_set_ether_type = mv88e6351_port_set_ether_type, 3014 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3015 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3016 .port_pause_limit = mv88e6097_port_pause_limit, 3017 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3018 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3019 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3020 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3021 .stats_get_strings = mv88e6095_stats_get_strings, 3022 .stats_get_stats = mv88e6095_stats_get_stats, 3023 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3024 .set_egress_port = mv88e6095_g1_set_egress_port, 3025 .watchdog_ops = &mv88e6097_watchdog_ops, 3026 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3027 .pot_clear = mv88e6xxx_g2_pot_clear, 3028 .reset = mv88e6352_g1_reset, 3029 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3030 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3031 .serdes_power = mv88e6352_serdes_power, 3032 }; 3033 3034 static const struct mv88e6xxx_ops mv88e6390_ops = { 3035 /* MV88E6XXX_FAMILY_6390 */ 3036 .irl_init_all = mv88e6390_g2_irl_init_all, 3037 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3038 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3039 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3040 .phy_read = mv88e6xxx_g2_smi_phy_read, 3041 .phy_write = mv88e6xxx_g2_smi_phy_write, 3042 .port_set_link = mv88e6xxx_port_set_link, 3043 .port_set_duplex = mv88e6xxx_port_set_duplex, 3044 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3045 .port_set_speed = mv88e6390_port_set_speed, 3046 .port_tag_remap = mv88e6390_port_tag_remap, 3047 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3048 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3049 .port_set_ether_type = mv88e6351_port_set_ether_type, 3050 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3051 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3052 .port_pause_limit = mv88e6390_port_pause_limit, 3053 .port_set_cmode = mv88e6390x_port_set_cmode, 3054 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3055 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3056 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3057 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3058 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3059 .stats_get_strings = mv88e6320_stats_get_strings, 3060 .stats_get_stats = mv88e6390_stats_get_stats, 3061 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3062 .set_egress_port = mv88e6390_g1_set_egress_port, 3063 .watchdog_ops = &mv88e6390_watchdog_ops, 3064 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3065 .pot_clear = mv88e6xxx_g2_pot_clear, 3066 .reset = mv88e6352_g1_reset, 3067 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3068 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3069 .serdes_power = mv88e6390_serdes_power, 3070 }; 3071 3072 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3073 /* MV88E6XXX_FAMILY_6390 */ 3074 .irl_init_all = mv88e6390_g2_irl_init_all, 3075 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3076 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3077 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3078 .phy_read = mv88e6xxx_g2_smi_phy_read, 3079 .phy_write = mv88e6xxx_g2_smi_phy_write, 3080 .port_set_link = mv88e6xxx_port_set_link, 3081 .port_set_duplex = mv88e6xxx_port_set_duplex, 3082 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3083 .port_set_speed = mv88e6390x_port_set_speed, 3084 .port_tag_remap = mv88e6390_port_tag_remap, 3085 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3086 .port_set_egress_floods = mv88e6352_port_set_egress_floods, 3087 .port_set_ether_type = mv88e6351_port_set_ether_type, 3088 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3089 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3090 .port_pause_limit = mv88e6390_port_pause_limit, 3091 .port_set_cmode = mv88e6390x_port_set_cmode, 3092 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3093 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3094 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3095 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3096 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3097 .stats_get_strings = mv88e6320_stats_get_strings, 3098 .stats_get_stats = mv88e6390_stats_get_stats, 3099 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3100 .set_egress_port = mv88e6390_g1_set_egress_port, 3101 .watchdog_ops = &mv88e6390_watchdog_ops, 3102 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3103 .pot_clear = mv88e6xxx_g2_pot_clear, 3104 .reset = mv88e6352_g1_reset, 3105 .vtu_getnext = mv88e6390_g1_vtu_getnext, 3106 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 3107 .serdes_power = mv88e6390_serdes_power, 3108 }; 3109 3110 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3111 [MV88E6085] = { 3112 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 3113 .family = MV88E6XXX_FAMILY_6097, 3114 .name = "Marvell 88E6085", 3115 .num_databases = 4096, 3116 .num_ports = 10, 3117 .max_vid = 4095, 3118 .port_base_addr = 0x10, 3119 .global1_addr = 0x1b, 3120 .global2_addr = 0x1c, 3121 .age_time_coeff = 15000, 3122 .g1_irqs = 8, 3123 .g2_irqs = 10, 3124 .atu_move_port_mask = 0xf, 3125 .pvt = true, 3126 .multi_chip = true, 3127 .tag_protocol = DSA_TAG_PROTO_DSA, 3128 .ops = &mv88e6085_ops, 3129 }, 3130 3131 [MV88E6095] = { 3132 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 3133 .family = MV88E6XXX_FAMILY_6095, 3134 .name = "Marvell 88E6095/88E6095F", 3135 .num_databases = 256, 3136 .num_ports = 11, 3137 .max_vid = 4095, 3138 .port_base_addr = 0x10, 3139 .global1_addr = 0x1b, 3140 .global2_addr = 0x1c, 3141 .age_time_coeff = 15000, 3142 .g1_irqs = 8, 3143 .atu_move_port_mask = 0xf, 3144 .multi_chip = true, 3145 .tag_protocol = DSA_TAG_PROTO_DSA, 3146 .ops = &mv88e6095_ops, 3147 }, 3148 3149 [MV88E6097] = { 3150 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 3151 .family = MV88E6XXX_FAMILY_6097, 3152 .name = "Marvell 88E6097/88E6097F", 3153 .num_databases = 4096, 3154 .num_ports = 11, 3155 .max_vid = 4095, 3156 .port_base_addr = 0x10, 3157 .global1_addr = 0x1b, 3158 .global2_addr = 0x1c, 3159 .age_time_coeff = 15000, 3160 .g1_irqs = 8, 3161 .g2_irqs = 10, 3162 .atu_move_port_mask = 0xf, 3163 .pvt = true, 3164 .multi_chip = true, 3165 .tag_protocol = DSA_TAG_PROTO_EDSA, 3166 .ops = &mv88e6097_ops, 3167 }, 3168 3169 [MV88E6123] = { 3170 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 3171 .family = MV88E6XXX_FAMILY_6165, 3172 .name = "Marvell 88E6123", 3173 .num_databases = 4096, 3174 .num_ports = 3, 3175 .max_vid = 4095, 3176 .port_base_addr = 0x10, 3177 .global1_addr = 0x1b, 3178 .global2_addr = 0x1c, 3179 .age_time_coeff = 15000, 3180 .g1_irqs = 9, 3181 .g2_irqs = 10, 3182 .atu_move_port_mask = 0xf, 3183 .pvt = true, 3184 .multi_chip = true, 3185 .tag_protocol = DSA_TAG_PROTO_EDSA, 3186 .ops = &mv88e6123_ops, 3187 }, 3188 3189 [MV88E6131] = { 3190 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 3191 .family = MV88E6XXX_FAMILY_6185, 3192 .name = "Marvell 88E6131", 3193 .num_databases = 256, 3194 .num_ports = 8, 3195 .max_vid = 4095, 3196 .port_base_addr = 0x10, 3197 .global1_addr = 0x1b, 3198 .global2_addr = 0x1c, 3199 .age_time_coeff = 15000, 3200 .g1_irqs = 9, 3201 .atu_move_port_mask = 0xf, 3202 .multi_chip = true, 3203 .tag_protocol = DSA_TAG_PROTO_DSA, 3204 .ops = &mv88e6131_ops, 3205 }, 3206 3207 [MV88E6141] = { 3208 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 3209 .family = MV88E6XXX_FAMILY_6341, 3210 .name = "Marvell 88E6341", 3211 .num_databases = 4096, 3212 .num_ports = 6, 3213 .max_vid = 4095, 3214 .port_base_addr = 0x10, 3215 .global1_addr = 0x1b, 3216 .global2_addr = 0x1c, 3217 .age_time_coeff = 3750, 3218 .atu_move_port_mask = 0x1f, 3219 .g2_irqs = 10, 3220 .pvt = true, 3221 .multi_chip = true, 3222 .tag_protocol = DSA_TAG_PROTO_EDSA, 3223 .ops = &mv88e6141_ops, 3224 }, 3225 3226 [MV88E6161] = { 3227 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 3228 .family = MV88E6XXX_FAMILY_6165, 3229 .name = "Marvell 88E6161", 3230 .num_databases = 4096, 3231 .num_ports = 6, 3232 .max_vid = 4095, 3233 .port_base_addr = 0x10, 3234 .global1_addr = 0x1b, 3235 .global2_addr = 0x1c, 3236 .age_time_coeff = 15000, 3237 .g1_irqs = 9, 3238 .g2_irqs = 10, 3239 .atu_move_port_mask = 0xf, 3240 .pvt = true, 3241 .multi_chip = true, 3242 .tag_protocol = DSA_TAG_PROTO_EDSA, 3243 .ops = &mv88e6161_ops, 3244 }, 3245 3246 [MV88E6165] = { 3247 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 3248 .family = MV88E6XXX_FAMILY_6165, 3249 .name = "Marvell 88E6165", 3250 .num_databases = 4096, 3251 .num_ports = 6, 3252 .max_vid = 4095, 3253 .port_base_addr = 0x10, 3254 .global1_addr = 0x1b, 3255 .global2_addr = 0x1c, 3256 .age_time_coeff = 15000, 3257 .g1_irqs = 9, 3258 .g2_irqs = 10, 3259 .atu_move_port_mask = 0xf, 3260 .pvt = true, 3261 .multi_chip = true, 3262 .tag_protocol = DSA_TAG_PROTO_DSA, 3263 .ops = &mv88e6165_ops, 3264 }, 3265 3266 [MV88E6171] = { 3267 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 3268 .family = MV88E6XXX_FAMILY_6351, 3269 .name = "Marvell 88E6171", 3270 .num_databases = 4096, 3271 .num_ports = 7, 3272 .max_vid = 4095, 3273 .port_base_addr = 0x10, 3274 .global1_addr = 0x1b, 3275 .global2_addr = 0x1c, 3276 .age_time_coeff = 15000, 3277 .g1_irqs = 9, 3278 .g2_irqs = 10, 3279 .atu_move_port_mask = 0xf, 3280 .pvt = true, 3281 .multi_chip = true, 3282 .tag_protocol = DSA_TAG_PROTO_EDSA, 3283 .ops = &mv88e6171_ops, 3284 }, 3285 3286 [MV88E6172] = { 3287 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 3288 .family = MV88E6XXX_FAMILY_6352, 3289 .name = "Marvell 88E6172", 3290 .num_databases = 4096, 3291 .num_ports = 7, 3292 .max_vid = 4095, 3293 .port_base_addr = 0x10, 3294 .global1_addr = 0x1b, 3295 .global2_addr = 0x1c, 3296 .age_time_coeff = 15000, 3297 .g1_irqs = 9, 3298 .g2_irqs = 10, 3299 .atu_move_port_mask = 0xf, 3300 .pvt = true, 3301 .multi_chip = true, 3302 .tag_protocol = DSA_TAG_PROTO_EDSA, 3303 .ops = &mv88e6172_ops, 3304 }, 3305 3306 [MV88E6175] = { 3307 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 3308 .family = MV88E6XXX_FAMILY_6351, 3309 .name = "Marvell 88E6175", 3310 .num_databases = 4096, 3311 .num_ports = 7, 3312 .max_vid = 4095, 3313 .port_base_addr = 0x10, 3314 .global1_addr = 0x1b, 3315 .global2_addr = 0x1c, 3316 .age_time_coeff = 15000, 3317 .g1_irqs = 9, 3318 .g2_irqs = 10, 3319 .atu_move_port_mask = 0xf, 3320 .pvt = true, 3321 .multi_chip = true, 3322 .tag_protocol = DSA_TAG_PROTO_EDSA, 3323 .ops = &mv88e6175_ops, 3324 }, 3325 3326 [MV88E6176] = { 3327 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 3328 .family = MV88E6XXX_FAMILY_6352, 3329 .name = "Marvell 88E6176", 3330 .num_databases = 4096, 3331 .num_ports = 7, 3332 .max_vid = 4095, 3333 .port_base_addr = 0x10, 3334 .global1_addr = 0x1b, 3335 .global2_addr = 0x1c, 3336 .age_time_coeff = 15000, 3337 .g1_irqs = 9, 3338 .g2_irqs = 10, 3339 .atu_move_port_mask = 0xf, 3340 .pvt = true, 3341 .multi_chip = true, 3342 .tag_protocol = DSA_TAG_PROTO_EDSA, 3343 .ops = &mv88e6176_ops, 3344 }, 3345 3346 [MV88E6185] = { 3347 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 3348 .family = MV88E6XXX_FAMILY_6185, 3349 .name = "Marvell 88E6185", 3350 .num_databases = 256, 3351 .num_ports = 10, 3352 .max_vid = 4095, 3353 .port_base_addr = 0x10, 3354 .global1_addr = 0x1b, 3355 .global2_addr = 0x1c, 3356 .age_time_coeff = 15000, 3357 .g1_irqs = 8, 3358 .atu_move_port_mask = 0xf, 3359 .multi_chip = true, 3360 .tag_protocol = DSA_TAG_PROTO_EDSA, 3361 .ops = &mv88e6185_ops, 3362 }, 3363 3364 [MV88E6190] = { 3365 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 3366 .family = MV88E6XXX_FAMILY_6390, 3367 .name = "Marvell 88E6190", 3368 .num_databases = 4096, 3369 .num_ports = 11, /* 10 + Z80 */ 3370 .max_vid = 8191, 3371 .port_base_addr = 0x0, 3372 .global1_addr = 0x1b, 3373 .global2_addr = 0x1c, 3374 .tag_protocol = DSA_TAG_PROTO_DSA, 3375 .age_time_coeff = 3750, 3376 .g1_irqs = 9, 3377 .g2_irqs = 14, 3378 .pvt = true, 3379 .multi_chip = true, 3380 .atu_move_port_mask = 0x1f, 3381 .ops = &mv88e6190_ops, 3382 }, 3383 3384 [MV88E6190X] = { 3385 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 3386 .family = MV88E6XXX_FAMILY_6390, 3387 .name = "Marvell 88E6190X", 3388 .num_databases = 4096, 3389 .num_ports = 11, /* 10 + Z80 */ 3390 .max_vid = 8191, 3391 .port_base_addr = 0x0, 3392 .global1_addr = 0x1b, 3393 .global2_addr = 0x1c, 3394 .age_time_coeff = 3750, 3395 .g1_irqs = 9, 3396 .g2_irqs = 14, 3397 .atu_move_port_mask = 0x1f, 3398 .pvt = true, 3399 .multi_chip = true, 3400 .tag_protocol = DSA_TAG_PROTO_DSA, 3401 .ops = &mv88e6190x_ops, 3402 }, 3403 3404 [MV88E6191] = { 3405 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 3406 .family = MV88E6XXX_FAMILY_6390, 3407 .name = "Marvell 88E6191", 3408 .num_databases = 4096, 3409 .num_ports = 11, /* 10 + Z80 */ 3410 .max_vid = 8191, 3411 .port_base_addr = 0x0, 3412 .global1_addr = 0x1b, 3413 .global2_addr = 0x1c, 3414 .age_time_coeff = 3750, 3415 .g1_irqs = 9, 3416 .g2_irqs = 14, 3417 .atu_move_port_mask = 0x1f, 3418 .pvt = true, 3419 .multi_chip = true, 3420 .tag_protocol = DSA_TAG_PROTO_DSA, 3421 .ops = &mv88e6191_ops, 3422 }, 3423 3424 [MV88E6240] = { 3425 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 3426 .family = MV88E6XXX_FAMILY_6352, 3427 .name = "Marvell 88E6240", 3428 .num_databases = 4096, 3429 .num_ports = 7, 3430 .max_vid = 4095, 3431 .port_base_addr = 0x10, 3432 .global1_addr = 0x1b, 3433 .global2_addr = 0x1c, 3434 .age_time_coeff = 15000, 3435 .g1_irqs = 9, 3436 .g2_irqs = 10, 3437 .atu_move_port_mask = 0xf, 3438 .pvt = true, 3439 .multi_chip = true, 3440 .tag_protocol = DSA_TAG_PROTO_EDSA, 3441 .ops = &mv88e6240_ops, 3442 }, 3443 3444 [MV88E6290] = { 3445 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 3446 .family = MV88E6XXX_FAMILY_6390, 3447 .name = "Marvell 88E6290", 3448 .num_databases = 4096, 3449 .num_ports = 11, /* 10 + Z80 */ 3450 .max_vid = 8191, 3451 .port_base_addr = 0x0, 3452 .global1_addr = 0x1b, 3453 .global2_addr = 0x1c, 3454 .age_time_coeff = 3750, 3455 .g1_irqs = 9, 3456 .g2_irqs = 14, 3457 .atu_move_port_mask = 0x1f, 3458 .pvt = true, 3459 .multi_chip = true, 3460 .tag_protocol = DSA_TAG_PROTO_DSA, 3461 .ops = &mv88e6290_ops, 3462 }, 3463 3464 [MV88E6320] = { 3465 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 3466 .family = MV88E6XXX_FAMILY_6320, 3467 .name = "Marvell 88E6320", 3468 .num_databases = 4096, 3469 .num_ports = 7, 3470 .max_vid = 4095, 3471 .port_base_addr = 0x10, 3472 .global1_addr = 0x1b, 3473 .global2_addr = 0x1c, 3474 .age_time_coeff = 15000, 3475 .g1_irqs = 8, 3476 .atu_move_port_mask = 0xf, 3477 .pvt = true, 3478 .multi_chip = true, 3479 .tag_protocol = DSA_TAG_PROTO_EDSA, 3480 .ops = &mv88e6320_ops, 3481 }, 3482 3483 [MV88E6321] = { 3484 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 3485 .family = MV88E6XXX_FAMILY_6320, 3486 .name = "Marvell 88E6321", 3487 .num_databases = 4096, 3488 .num_ports = 7, 3489 .max_vid = 4095, 3490 .port_base_addr = 0x10, 3491 .global1_addr = 0x1b, 3492 .global2_addr = 0x1c, 3493 .age_time_coeff = 15000, 3494 .g1_irqs = 8, 3495 .atu_move_port_mask = 0xf, 3496 .multi_chip = true, 3497 .tag_protocol = DSA_TAG_PROTO_EDSA, 3498 .ops = &mv88e6321_ops, 3499 }, 3500 3501 [MV88E6341] = { 3502 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3503 .family = MV88E6XXX_FAMILY_6341, 3504 .name = "Marvell 88E6341", 3505 .num_databases = 4096, 3506 .num_ports = 6, 3507 .max_vid = 4095, 3508 .port_base_addr = 0x10, 3509 .global1_addr = 0x1b, 3510 .global2_addr = 0x1c, 3511 .age_time_coeff = 3750, 3512 .atu_move_port_mask = 0x1f, 3513 .g2_irqs = 10, 3514 .pvt = true, 3515 .multi_chip = true, 3516 .tag_protocol = DSA_TAG_PROTO_EDSA, 3517 .ops = &mv88e6341_ops, 3518 }, 3519 3520 [MV88E6350] = { 3521 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 3522 .family = MV88E6XXX_FAMILY_6351, 3523 .name = "Marvell 88E6350", 3524 .num_databases = 4096, 3525 .num_ports = 7, 3526 .max_vid = 4095, 3527 .port_base_addr = 0x10, 3528 .global1_addr = 0x1b, 3529 .global2_addr = 0x1c, 3530 .age_time_coeff = 15000, 3531 .g1_irqs = 9, 3532 .g2_irqs = 10, 3533 .atu_move_port_mask = 0xf, 3534 .pvt = true, 3535 .multi_chip = true, 3536 .tag_protocol = DSA_TAG_PROTO_EDSA, 3537 .ops = &mv88e6350_ops, 3538 }, 3539 3540 [MV88E6351] = { 3541 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 3542 .family = MV88E6XXX_FAMILY_6351, 3543 .name = "Marvell 88E6351", 3544 .num_databases = 4096, 3545 .num_ports = 7, 3546 .max_vid = 4095, 3547 .port_base_addr = 0x10, 3548 .global1_addr = 0x1b, 3549 .global2_addr = 0x1c, 3550 .age_time_coeff = 15000, 3551 .g1_irqs = 9, 3552 .g2_irqs = 10, 3553 .atu_move_port_mask = 0xf, 3554 .pvt = true, 3555 .multi_chip = true, 3556 .tag_protocol = DSA_TAG_PROTO_EDSA, 3557 .ops = &mv88e6351_ops, 3558 }, 3559 3560 [MV88E6352] = { 3561 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 3562 .family = MV88E6XXX_FAMILY_6352, 3563 .name = "Marvell 88E6352", 3564 .num_databases = 4096, 3565 .num_ports = 7, 3566 .max_vid = 4095, 3567 .port_base_addr = 0x10, 3568 .global1_addr = 0x1b, 3569 .global2_addr = 0x1c, 3570 .age_time_coeff = 15000, 3571 .g1_irqs = 9, 3572 .g2_irqs = 10, 3573 .atu_move_port_mask = 0xf, 3574 .pvt = true, 3575 .multi_chip = true, 3576 .tag_protocol = DSA_TAG_PROTO_EDSA, 3577 .ops = &mv88e6352_ops, 3578 }, 3579 [MV88E6390] = { 3580 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3581 .family = MV88E6XXX_FAMILY_6390, 3582 .name = "Marvell 88E6390", 3583 .num_databases = 4096, 3584 .num_ports = 11, /* 10 + Z80 */ 3585 .max_vid = 8191, 3586 .port_base_addr = 0x0, 3587 .global1_addr = 0x1b, 3588 .global2_addr = 0x1c, 3589 .age_time_coeff = 3750, 3590 .g1_irqs = 9, 3591 .g2_irqs = 14, 3592 .atu_move_port_mask = 0x1f, 3593 .pvt = true, 3594 .multi_chip = true, 3595 .tag_protocol = DSA_TAG_PROTO_DSA, 3596 .ops = &mv88e6390_ops, 3597 }, 3598 [MV88E6390X] = { 3599 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 3600 .family = MV88E6XXX_FAMILY_6390, 3601 .name = "Marvell 88E6390X", 3602 .num_databases = 4096, 3603 .num_ports = 11, /* 10 + Z80 */ 3604 .max_vid = 8191, 3605 .port_base_addr = 0x0, 3606 .global1_addr = 0x1b, 3607 .global2_addr = 0x1c, 3608 .age_time_coeff = 3750, 3609 .g1_irqs = 9, 3610 .g2_irqs = 14, 3611 .atu_move_port_mask = 0x1f, 3612 .pvt = true, 3613 .multi_chip = true, 3614 .tag_protocol = DSA_TAG_PROTO_DSA, 3615 .ops = &mv88e6390x_ops, 3616 }, 3617 }; 3618 3619 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 3620 { 3621 int i; 3622 3623 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 3624 if (mv88e6xxx_table[i].prod_num == prod_num) 3625 return &mv88e6xxx_table[i]; 3626 3627 return NULL; 3628 } 3629 3630 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 3631 { 3632 const struct mv88e6xxx_info *info; 3633 unsigned int prod_num, rev; 3634 u16 id; 3635 int err; 3636 3637 mutex_lock(&chip->reg_lock); 3638 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 3639 mutex_unlock(&chip->reg_lock); 3640 if (err) 3641 return err; 3642 3643 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 3644 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 3645 3646 info = mv88e6xxx_lookup_info(prod_num); 3647 if (!info) 3648 return -ENODEV; 3649 3650 /* Update the compatible info with the probed one */ 3651 chip->info = info; 3652 3653 err = mv88e6xxx_g2_require(chip); 3654 if (err) 3655 return err; 3656 3657 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 3658 chip->info->prod_num, chip->info->name, rev); 3659 3660 return 0; 3661 } 3662 3663 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 3664 { 3665 struct mv88e6xxx_chip *chip; 3666 3667 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 3668 if (!chip) 3669 return NULL; 3670 3671 chip->dev = dev; 3672 3673 mutex_init(&chip->reg_lock); 3674 INIT_LIST_HEAD(&chip->mdios); 3675 3676 return chip; 3677 } 3678 3679 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 3680 struct mii_bus *bus, int sw_addr) 3681 { 3682 if (sw_addr == 0) 3683 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 3684 else if (chip->info->multi_chip) 3685 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 3686 else 3687 return -EINVAL; 3688 3689 chip->bus = bus; 3690 chip->sw_addr = sw_addr; 3691 3692 return 0; 3693 } 3694 3695 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 3696 { 3697 struct mv88e6xxx_chip *chip = ds->priv; 3698 3699 return chip->info->tag_protocol; 3700 } 3701 3702 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 3703 struct device *host_dev, int sw_addr, 3704 void **priv) 3705 { 3706 struct mv88e6xxx_chip *chip; 3707 struct mii_bus *bus; 3708 int err; 3709 3710 bus = dsa_host_dev_to_mii_bus(host_dev); 3711 if (!bus) 3712 return NULL; 3713 3714 chip = mv88e6xxx_alloc_chip(dsa_dev); 3715 if (!chip) 3716 return NULL; 3717 3718 /* Legacy SMI probing will only support chips similar to 88E6085 */ 3719 chip->info = &mv88e6xxx_table[MV88E6085]; 3720 3721 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 3722 if (err) 3723 goto free; 3724 3725 err = mv88e6xxx_detect(chip); 3726 if (err) 3727 goto free; 3728 3729 mutex_lock(&chip->reg_lock); 3730 err = mv88e6xxx_switch_reset(chip); 3731 mutex_unlock(&chip->reg_lock); 3732 if (err) 3733 goto free; 3734 3735 mv88e6xxx_phy_init(chip); 3736 3737 err = mv88e6xxx_mdios_register(chip, NULL); 3738 if (err) 3739 goto free; 3740 3741 *priv = chip; 3742 3743 return chip->info->name; 3744 free: 3745 devm_kfree(dsa_dev, chip); 3746 3747 return NULL; 3748 } 3749 3750 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 3751 const struct switchdev_obj_port_mdb *mdb, 3752 struct switchdev_trans *trans) 3753 { 3754 /* We don't need any dynamic resource from the kernel (yet), 3755 * so skip the prepare phase. 3756 */ 3757 3758 return 0; 3759 } 3760 3761 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 3762 const struct switchdev_obj_port_mdb *mdb, 3763 struct switchdev_trans *trans) 3764 { 3765 struct mv88e6xxx_chip *chip = ds->priv; 3766 3767 mutex_lock(&chip->reg_lock); 3768 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3769 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC)) 3770 dev_err(ds->dev, "p%d: failed to load multicast MAC address\n", 3771 port); 3772 mutex_unlock(&chip->reg_lock); 3773 } 3774 3775 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 3776 const struct switchdev_obj_port_mdb *mdb) 3777 { 3778 struct mv88e6xxx_chip *chip = ds->priv; 3779 int err; 3780 3781 mutex_lock(&chip->reg_lock); 3782 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 3783 MV88E6XXX_G1_ATU_DATA_STATE_UNUSED); 3784 mutex_unlock(&chip->reg_lock); 3785 3786 return err; 3787 } 3788 3789 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 3790 .probe = mv88e6xxx_drv_probe, 3791 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 3792 .setup = mv88e6xxx_setup, 3793 .adjust_link = mv88e6xxx_adjust_link, 3794 .get_strings = mv88e6xxx_get_strings, 3795 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 3796 .get_sset_count = mv88e6xxx_get_sset_count, 3797 .port_enable = mv88e6xxx_port_enable, 3798 .port_disable = mv88e6xxx_port_disable, 3799 .get_mac_eee = mv88e6xxx_get_mac_eee, 3800 .set_mac_eee = mv88e6xxx_set_mac_eee, 3801 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 3802 .get_eeprom = mv88e6xxx_get_eeprom, 3803 .set_eeprom = mv88e6xxx_set_eeprom, 3804 .get_regs_len = mv88e6xxx_get_regs_len, 3805 .get_regs = mv88e6xxx_get_regs, 3806 .set_ageing_time = mv88e6xxx_set_ageing_time, 3807 .port_bridge_join = mv88e6xxx_port_bridge_join, 3808 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 3809 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 3810 .port_fast_age = mv88e6xxx_port_fast_age, 3811 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 3812 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 3813 .port_vlan_add = mv88e6xxx_port_vlan_add, 3814 .port_vlan_del = mv88e6xxx_port_vlan_del, 3815 .port_fdb_add = mv88e6xxx_port_fdb_add, 3816 .port_fdb_del = mv88e6xxx_port_fdb_del, 3817 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 3818 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 3819 .port_mdb_add = mv88e6xxx_port_mdb_add, 3820 .port_mdb_del = mv88e6xxx_port_mdb_del, 3821 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 3822 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 3823 }; 3824 3825 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 3826 .ops = &mv88e6xxx_switch_ops, 3827 }; 3828 3829 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 3830 { 3831 struct device *dev = chip->dev; 3832 struct dsa_switch *ds; 3833 3834 ds = dsa_switch_alloc(dev, mv88e6xxx_num_ports(chip)); 3835 if (!ds) 3836 return -ENOMEM; 3837 3838 ds->priv = chip; 3839 ds->ops = &mv88e6xxx_switch_ops; 3840 ds->ageing_time_min = chip->info->age_time_coeff; 3841 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 3842 3843 dev_set_drvdata(dev, ds); 3844 3845 return dsa_register_switch(ds); 3846 } 3847 3848 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 3849 { 3850 dsa_unregister_switch(chip->ds); 3851 } 3852 3853 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 3854 { 3855 struct device *dev = &mdiodev->dev; 3856 struct device_node *np = dev->of_node; 3857 const struct mv88e6xxx_info *compat_info; 3858 struct mv88e6xxx_chip *chip; 3859 u32 eeprom_len; 3860 int err; 3861 3862 compat_info = of_device_get_match_data(dev); 3863 if (!compat_info) 3864 return -EINVAL; 3865 3866 chip = mv88e6xxx_alloc_chip(dev); 3867 if (!chip) 3868 return -ENOMEM; 3869 3870 chip->info = compat_info; 3871 3872 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 3873 if (err) 3874 return err; 3875 3876 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 3877 if (IS_ERR(chip->reset)) 3878 return PTR_ERR(chip->reset); 3879 3880 err = mv88e6xxx_detect(chip); 3881 if (err) 3882 return err; 3883 3884 mv88e6xxx_phy_init(chip); 3885 3886 if (chip->info->ops->get_eeprom && 3887 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 3888 chip->eeprom_len = eeprom_len; 3889 3890 mutex_lock(&chip->reg_lock); 3891 err = mv88e6xxx_switch_reset(chip); 3892 mutex_unlock(&chip->reg_lock); 3893 if (err) 3894 goto out; 3895 3896 chip->irq = of_irq_get(np, 0); 3897 if (chip->irq == -EPROBE_DEFER) { 3898 err = chip->irq; 3899 goto out; 3900 } 3901 3902 if (chip->irq > 0) { 3903 /* Has to be performed before the MDIO bus is created, 3904 * because the PHYs will link there interrupts to these 3905 * interrupt controllers 3906 */ 3907 mutex_lock(&chip->reg_lock); 3908 err = mv88e6xxx_g1_irq_setup(chip); 3909 mutex_unlock(&chip->reg_lock); 3910 3911 if (err) 3912 goto out; 3913 3914 if (chip->info->g2_irqs > 0) { 3915 err = mv88e6xxx_g2_irq_setup(chip); 3916 if (err) 3917 goto out_g1_irq; 3918 } 3919 } 3920 3921 err = mv88e6xxx_mdios_register(chip, np); 3922 if (err) 3923 goto out_g2_irq; 3924 3925 err = mv88e6xxx_register_switch(chip); 3926 if (err) 3927 goto out_mdio; 3928 3929 return 0; 3930 3931 out_mdio: 3932 mv88e6xxx_mdios_unregister(chip); 3933 out_g2_irq: 3934 if (chip->info->g2_irqs > 0 && chip->irq > 0) 3935 mv88e6xxx_g2_irq_free(chip); 3936 out_g1_irq: 3937 if (chip->irq > 0) { 3938 mutex_lock(&chip->reg_lock); 3939 mv88e6xxx_g1_irq_free(chip); 3940 mutex_unlock(&chip->reg_lock); 3941 } 3942 out: 3943 return err; 3944 } 3945 3946 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 3947 { 3948 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 3949 struct mv88e6xxx_chip *chip = ds->priv; 3950 3951 mv88e6xxx_phy_destroy(chip); 3952 mv88e6xxx_unregister_switch(chip); 3953 mv88e6xxx_mdios_unregister(chip); 3954 3955 if (chip->irq > 0) { 3956 if (chip->info->g2_irqs > 0) 3957 mv88e6xxx_g2_irq_free(chip); 3958 mutex_lock(&chip->reg_lock); 3959 mv88e6xxx_g1_irq_free(chip); 3960 mutex_unlock(&chip->reg_lock); 3961 } 3962 } 3963 3964 static const struct of_device_id mv88e6xxx_of_match[] = { 3965 { 3966 .compatible = "marvell,mv88e6085", 3967 .data = &mv88e6xxx_table[MV88E6085], 3968 }, 3969 { 3970 .compatible = "marvell,mv88e6190", 3971 .data = &mv88e6xxx_table[MV88E6190], 3972 }, 3973 { /* sentinel */ }, 3974 }; 3975 3976 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 3977 3978 static struct mdio_driver mv88e6xxx_driver = { 3979 .probe = mv88e6xxx_probe, 3980 .remove = mv88e6xxx_remove, 3981 .mdiodrv.driver = { 3982 .name = "mv88e6085", 3983 .of_match_table = mv88e6xxx_of_match, 3984 }, 3985 }; 3986 3987 static int __init mv88e6xxx_init(void) 3988 { 3989 register_switch_driver(&mv88e6xxx_switch_drv); 3990 return mdio_driver_register(&mv88e6xxx_driver); 3991 } 3992 module_init(mv88e6xxx_init); 3993 3994 static void __exit mv88e6xxx_cleanup(void) 3995 { 3996 mdio_driver_unregister(&mv88e6xxx_driver); 3997 unregister_switch_driver(&mv88e6xxx_switch_drv); 3998 } 3999 module_exit(mv88e6xxx_cleanup); 4000 4001 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4002 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4003 MODULE_LICENSE("GPL"); 4004