1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 err = mv88e6xxx_read(chip, addr, reg, &data); 113 if (err) 114 return err; 115 116 if ((data & mask) == val) 117 return 0; 118 119 dev_err(chip->dev, "Timeout while waiting for switch\n"); 120 return -ETIMEDOUT; 121 } 122 123 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 124 int bit, int val) 125 { 126 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 127 val ? BIT(bit) : 0x0000); 128 } 129 130 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 131 { 132 struct mv88e6xxx_mdio_bus *mdio_bus; 133 134 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 135 list); 136 if (!mdio_bus) 137 return NULL; 138 139 return mdio_bus->bus; 140 } 141 142 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 143 { 144 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 145 unsigned int n = d->hwirq; 146 147 chip->g1_irq.masked |= (1 << n); 148 } 149 150 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 151 { 152 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 153 unsigned int n = d->hwirq; 154 155 chip->g1_irq.masked &= ~(1 << n); 156 } 157 158 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 159 { 160 unsigned int nhandled = 0; 161 unsigned int sub_irq; 162 unsigned int n; 163 u16 reg; 164 u16 ctl1; 165 int err; 166 167 mv88e6xxx_reg_lock(chip); 168 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 169 mv88e6xxx_reg_unlock(chip); 170 171 if (err) 172 goto out; 173 174 do { 175 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 176 if (reg & (1 << n)) { 177 sub_irq = irq_find_mapping(chip->g1_irq.domain, 178 n); 179 handle_nested_irq(sub_irq); 180 ++nhandled; 181 } 182 } 183 184 mv88e6xxx_reg_lock(chip); 185 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 186 if (err) 187 goto unlock; 188 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 189 unlock: 190 mv88e6xxx_reg_unlock(chip); 191 if (err) 192 goto out; 193 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 194 } while (reg & ctl1); 195 196 out: 197 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 198 } 199 200 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 201 { 202 struct mv88e6xxx_chip *chip = dev_id; 203 204 return mv88e6xxx_g1_irq_thread_work(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 211 mv88e6xxx_reg_lock(chip); 212 } 213 214 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 215 { 216 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 217 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 218 u16 reg; 219 int err; 220 221 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 222 if (err) 223 goto out; 224 225 reg &= ~mask; 226 reg |= (~chip->g1_irq.masked & mask); 227 228 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 229 if (err) 230 goto out; 231 232 out: 233 mv88e6xxx_reg_unlock(chip); 234 } 235 236 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 237 .name = "mv88e6xxx-g1", 238 .irq_mask = mv88e6xxx_g1_irq_mask, 239 .irq_unmask = mv88e6xxx_g1_irq_unmask, 240 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 241 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 242 }; 243 244 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 245 unsigned int irq, 246 irq_hw_number_t hwirq) 247 { 248 struct mv88e6xxx_chip *chip = d->host_data; 249 250 irq_set_chip_data(irq, d->host_data); 251 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 252 irq_set_noprobe(irq); 253 254 return 0; 255 } 256 257 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 258 .map = mv88e6xxx_g1_irq_domain_map, 259 .xlate = irq_domain_xlate_twocell, 260 }; 261 262 /* To be called with reg_lock held */ 263 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 264 { 265 int irq, virq; 266 u16 mask; 267 268 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 269 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 270 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 271 272 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 273 virq = irq_find_mapping(chip->g1_irq.domain, irq); 274 irq_dispose_mapping(virq); 275 } 276 277 irq_domain_remove(chip->g1_irq.domain); 278 } 279 280 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 281 { 282 /* 283 * free_irq must be called without reg_lock taken because the irq 284 * handler takes this lock, too. 285 */ 286 free_irq(chip->irq, chip); 287 288 mv88e6xxx_reg_lock(chip); 289 mv88e6xxx_g1_irq_free_common(chip); 290 mv88e6xxx_reg_unlock(chip); 291 } 292 293 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 294 { 295 int err, irq, virq; 296 u16 reg, mask; 297 298 chip->g1_irq.nirqs = chip->info->g1_irqs; 299 chip->g1_irq.domain = irq_domain_add_simple( 300 NULL, chip->g1_irq.nirqs, 0, 301 &mv88e6xxx_g1_irq_domain_ops, chip); 302 if (!chip->g1_irq.domain) 303 return -ENOMEM; 304 305 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 306 irq_create_mapping(chip->g1_irq.domain, irq); 307 308 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 309 chip->g1_irq.masked = ~0; 310 311 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 312 if (err) 313 goto out_mapping; 314 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 317 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 318 if (err) 319 goto out_disable; 320 321 /* Reading the interrupt status clears (most of) them */ 322 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 323 if (err) 324 goto out_disable; 325 326 return 0; 327 328 out_disable: 329 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 330 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 331 332 out_mapping: 333 for (irq = 0; irq < 16; irq++) { 334 virq = irq_find_mapping(chip->g1_irq.domain, irq); 335 irq_dispose_mapping(virq); 336 } 337 338 irq_domain_remove(chip->g1_irq.domain); 339 340 return err; 341 } 342 343 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 344 { 345 static struct lock_class_key lock_key; 346 static struct lock_class_key request_key; 347 int err; 348 349 err = mv88e6xxx_g1_irq_setup_common(chip); 350 if (err) 351 return err; 352 353 /* These lock classes tells lockdep that global 1 irqs are in 354 * a different category than their parent GPIO, so it won't 355 * report false recursion. 356 */ 357 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 358 359 snprintf(chip->irq_name, sizeof(chip->irq_name), 360 "mv88e6xxx-%s", dev_name(chip->dev)); 361 362 mv88e6xxx_reg_unlock(chip); 363 err = request_threaded_irq(chip->irq, NULL, 364 mv88e6xxx_g1_irq_thread_fn, 365 IRQF_ONESHOT | IRQF_SHARED, 366 chip->irq_name, chip); 367 mv88e6xxx_reg_lock(chip); 368 if (err) 369 mv88e6xxx_g1_irq_free_common(chip); 370 371 return err; 372 } 373 374 static void mv88e6xxx_irq_poll(struct kthread_work *work) 375 { 376 struct mv88e6xxx_chip *chip = container_of(work, 377 struct mv88e6xxx_chip, 378 irq_poll_work.work); 379 mv88e6xxx_g1_irq_thread_work(chip); 380 381 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 382 msecs_to_jiffies(100)); 383 } 384 385 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 386 { 387 int err; 388 389 err = mv88e6xxx_g1_irq_setup_common(chip); 390 if (err) 391 return err; 392 393 kthread_init_delayed_work(&chip->irq_poll_work, 394 mv88e6xxx_irq_poll); 395 396 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 397 if (IS_ERR(chip->kworker)) 398 return PTR_ERR(chip->kworker); 399 400 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 401 msecs_to_jiffies(100)); 402 403 return 0; 404 } 405 406 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 407 { 408 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 409 kthread_destroy_worker(chip->kworker); 410 411 mv88e6xxx_reg_lock(chip); 412 mv88e6xxx_g1_irq_free_common(chip); 413 mv88e6xxx_reg_unlock(chip); 414 } 415 416 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 417 int port, phy_interface_t interface) 418 { 419 int err; 420 421 if (chip->info->ops->port_set_rgmii_delay) { 422 err = chip->info->ops->port_set_rgmii_delay(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 if (chip->info->ops->port_set_cmode) { 429 err = chip->info->ops->port_set_cmode(chip, port, 430 interface); 431 if (err && err != -EOPNOTSUPP) 432 return err; 433 } 434 435 return 0; 436 } 437 438 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 439 int link, int speed, int duplex, int pause, 440 phy_interface_t mode) 441 { 442 int err; 443 444 if (!chip->info->ops->port_set_link) 445 return 0; 446 447 /* Port's MAC control must not be changed unless the link is down */ 448 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 449 if (err) 450 return err; 451 452 if (chip->info->ops->port_set_speed_duplex) { 453 err = chip->info->ops->port_set_speed_duplex(chip, port, 454 speed, duplex); 455 if (err && err != -EOPNOTSUPP) 456 goto restore_link; 457 } 458 459 if (chip->info->ops->port_set_pause) { 460 err = chip->info->ops->port_set_pause(chip, port, pause); 461 if (err) 462 goto restore_link; 463 } 464 465 err = mv88e6xxx_port_config_interface(chip, port, mode); 466 restore_link: 467 if (chip->info->ops->port_set_link(chip, port, link)) 468 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 469 470 return err; 471 } 472 473 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 474 { 475 return port >= chip->info->internal_phys_offset && 476 port < chip->info->num_internal_phys + 477 chip->info->internal_phys_offset; 478 } 479 480 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 481 { 482 u16 reg; 483 int err; 484 485 /* The 88e6250 family does not have the PHY detect bit. Instead, 486 * report whether the port is internal. 487 */ 488 if (chip->info->family == MV88E6XXX_FAMILY_6250) 489 return mv88e6xxx_phy_is_internal(chip, port); 490 491 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 492 if (err) { 493 dev_err(chip->dev, 494 "p%d: %s: failed to read port status\n", 495 port, __func__); 496 return err; 497 } 498 499 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 500 } 501 502 static const u8 mv88e6185_phy_interface_modes[] = { 503 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 504 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 505 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 506 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 507 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 508 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 509 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 510 }; 511 512 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 513 struct phylink_config *config) 514 { 515 u8 cmode = chip->ports[port].cmode; 516 517 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 518 519 if (mv88e6xxx_phy_is_internal(chip, port)) { 520 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 521 } else { 522 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 523 mv88e6185_phy_interface_modes[cmode]) 524 __set_bit(mv88e6185_phy_interface_modes[cmode], 525 config->supported_interfaces); 526 527 config->mac_capabilities |= MAC_1000FD; 528 } 529 } 530 531 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 532 struct phylink_config *config) 533 { 534 u8 cmode = chip->ports[port].cmode; 535 536 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 537 mv88e6185_phy_interface_modes[cmode]) 538 __set_bit(mv88e6185_phy_interface_modes[cmode], 539 config->supported_interfaces); 540 541 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 542 MAC_1000FD; 543 } 544 545 static const u8 mv88e6xxx_phy_interface_modes[] = { 546 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 547 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 548 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 549 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 550 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 551 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 552 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 553 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 554 /* higher interface modes are not needed here, since ports supporting 555 * them are writable, and so the supported interfaces are filled in the 556 * corresponding .phylink_set_interfaces() implementation below 557 */ 558 }; 559 560 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 561 { 562 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 563 mv88e6xxx_phy_interface_modes[cmode]) 564 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 565 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 566 phy_interface_set_rgmii(supported); 567 } 568 569 static void 570 mv88e6250_setup_supported_interfaces(struct mv88e6xxx_chip *chip, int port, 571 struct phylink_config *config) 572 { 573 unsigned long *supported = config->supported_interfaces; 574 int err; 575 u16 reg; 576 577 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 578 if (err) { 579 dev_err(chip->dev, "p%d: failed to read port status\n", port); 580 return; 581 } 582 583 switch (reg & MV88E6250_PORT_STS_PORTMODE_MASK) { 584 case MV88E6250_PORT_STS_PORTMODE_MII_10_HALF_PHY: 585 case MV88E6250_PORT_STS_PORTMODE_MII_100_HALF_PHY: 586 case MV88E6250_PORT_STS_PORTMODE_MII_10_FULL_PHY: 587 case MV88E6250_PORT_STS_PORTMODE_MII_100_FULL_PHY: 588 __set_bit(PHY_INTERFACE_MODE_REVMII, supported); 589 break; 590 591 case MV88E6250_PORT_STS_PORTMODE_MII_HALF: 592 case MV88E6250_PORT_STS_PORTMODE_MII_FULL: 593 __set_bit(PHY_INTERFACE_MODE_MII, supported); 594 break; 595 596 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL_PHY: 597 case MV88E6250_PORT_STS_PORTMODE_MII_200_RMII_FULL_PHY: 598 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_HALF_PHY: 599 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL_PHY: 600 __set_bit(PHY_INTERFACE_MODE_REVRMII, supported); 601 break; 602 603 case MV88E6250_PORT_STS_PORTMODE_MII_DUAL_100_RMII_FULL: 604 case MV88E6250_PORT_STS_PORTMODE_MII_10_100_RMII_FULL: 605 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 606 break; 607 608 case MV88E6250_PORT_STS_PORTMODE_MII_100_RGMII: 609 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 610 break; 611 612 default: 613 dev_err(chip->dev, 614 "p%d: invalid port mode in status register: %04x\n", 615 port, reg); 616 } 617 } 618 619 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 620 struct phylink_config *config) 621 { 622 if (!mv88e6xxx_phy_is_internal(chip, port)) 623 mv88e6250_setup_supported_interfaces(chip, port, config); 624 625 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 626 } 627 628 static void mv88e6351_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 629 struct phylink_config *config) 630 { 631 unsigned long *supported = config->supported_interfaces; 632 633 /* Translate the default cmode */ 634 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 635 636 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 637 MAC_1000FD; 638 } 639 640 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 641 { 642 u16 reg, val; 643 int err; 644 645 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 646 if (err) 647 return err; 648 649 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 650 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 651 return 0xf; 652 653 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 654 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 655 if (err) 656 return err; 657 658 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 659 if (err) 660 return err; 661 662 /* Restore PHY_DETECT value */ 663 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 664 if (err) 665 return err; 666 667 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 668 } 669 670 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 671 struct phylink_config *config) 672 { 673 unsigned long *supported = config->supported_interfaces; 674 int err, cmode; 675 676 /* Translate the default cmode */ 677 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 678 679 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 680 MAC_1000FD; 681 682 /* Port 4 supports automedia if the serdes is associated with it. */ 683 if (port == 4) { 684 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 685 if (err < 0) 686 dev_err(chip->dev, "p%d: failed to read scratch\n", 687 port); 688 if (err <= 0) 689 return; 690 691 cmode = mv88e6352_get_port4_serdes_cmode(chip); 692 if (cmode < 0) 693 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 694 port); 695 else 696 mv88e6xxx_translate_cmode(cmode, supported); 697 } 698 } 699 700 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 701 struct phylink_config *config) 702 { 703 unsigned long *supported = config->supported_interfaces; 704 705 /* Translate the default cmode */ 706 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 707 708 /* No ethtool bits for 200Mbps */ 709 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 710 MAC_1000FD; 711 712 /* The C_Mode field is programmable on port 5 */ 713 if (port == 5) { 714 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 715 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 716 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 717 718 config->mac_capabilities |= MAC_2500FD; 719 } 720 } 721 722 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 723 struct phylink_config *config) 724 { 725 unsigned long *supported = config->supported_interfaces; 726 727 /* Translate the default cmode */ 728 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 729 730 /* No ethtool bits for 200Mbps */ 731 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 732 MAC_1000FD; 733 734 /* The C_Mode field is programmable on ports 9 and 10 */ 735 if (port == 9 || port == 10) { 736 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 737 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 738 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 739 740 config->mac_capabilities |= MAC_2500FD; 741 } 742 } 743 744 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 745 struct phylink_config *config) 746 { 747 unsigned long *supported = config->supported_interfaces; 748 749 mv88e6390_phylink_get_caps(chip, port, config); 750 751 /* For the 6x90X, ports 2-7 can be in automedia mode. 752 * (Note that 6x90 doesn't support RXAUI nor XAUI). 753 * 754 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 755 * configured for 1000BASE-X, SGMII or 2500BASE-X. 756 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 757 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 758 * 759 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 760 * configured for 1000BASE-X, SGMII or 2500BASE-X. 761 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 762 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 763 * 764 * For now, be permissive (as the old code was) and allow 1000BASE-X 765 * on ports 2..7. 766 */ 767 if (port >= 2 && port <= 7) 768 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 769 770 /* The C_Mode field can also be programmed for 10G speeds */ 771 if (port == 9 || port == 10) { 772 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 773 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 774 775 config->mac_capabilities |= MAC_10000FD; 776 } 777 } 778 779 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 780 struct phylink_config *config) 781 { 782 unsigned long *supported = config->supported_interfaces; 783 bool is_6191x = 784 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 785 bool is_6361 = 786 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 787 788 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 789 790 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 791 MAC_1000FD; 792 793 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 794 if (port == 0 || port == 9 || port == 10) { 795 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 796 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 797 798 /* 6191X supports >1G modes only on port 10 */ 799 if (!is_6191x || port == 10) { 800 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 801 config->mac_capabilities |= MAC_2500FD; 802 803 /* 6361 only supports up to 2500BaseX */ 804 if (!is_6361) { 805 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 806 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 807 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 808 config->mac_capabilities |= MAC_5000FD | 809 MAC_10000FD; 810 } 811 } 812 } 813 814 if (port == 0) { 815 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 816 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 817 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 818 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 819 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 820 } 821 } 822 823 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 824 struct phylink_config *config) 825 { 826 struct mv88e6xxx_chip *chip = ds->priv; 827 828 mv88e6xxx_reg_lock(chip); 829 chip->info->ops->phylink_get_caps(chip, port, config); 830 mv88e6xxx_reg_unlock(chip); 831 832 if (mv88e6xxx_phy_is_internal(chip, port)) { 833 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 834 config->supported_interfaces); 835 /* Internal ports with no phy-mode need GMII for PHYLIB */ 836 __set_bit(PHY_INTERFACE_MODE_GMII, 837 config->supported_interfaces); 838 } 839 } 840 841 static struct phylink_pcs *mv88e6xxx_mac_select_pcs(struct dsa_switch *ds, 842 int port, 843 phy_interface_t interface) 844 { 845 struct mv88e6xxx_chip *chip = ds->priv; 846 struct phylink_pcs *pcs = ERR_PTR(-EOPNOTSUPP); 847 848 if (chip->info->ops->pcs_ops) 849 pcs = chip->info->ops->pcs_ops->pcs_select(chip, port, 850 interface); 851 852 return pcs; 853 } 854 855 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 856 unsigned int mode, phy_interface_t interface) 857 { 858 struct mv88e6xxx_chip *chip = ds->priv; 859 int err = 0; 860 861 /* In inband mode, the link may come up at any time while the link 862 * is not forced down. Force the link down while we reconfigure the 863 * interface mode. 864 */ 865 if (mode == MLO_AN_INBAND && 866 chip->ports[port].interface != interface && 867 chip->info->ops->port_set_link) { 868 mv88e6xxx_reg_lock(chip); 869 err = chip->info->ops->port_set_link(chip, port, 870 LINK_FORCED_DOWN); 871 mv88e6xxx_reg_unlock(chip); 872 } 873 874 return err; 875 } 876 877 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 878 unsigned int mode, 879 const struct phylink_link_state *state) 880 { 881 struct mv88e6xxx_chip *chip = ds->priv; 882 int err = 0; 883 884 mv88e6xxx_reg_lock(chip); 885 886 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 887 err = mv88e6xxx_port_config_interface(chip, port, 888 state->interface); 889 if (err && err != -EOPNOTSUPP) 890 goto err_unlock; 891 } 892 893 err_unlock: 894 mv88e6xxx_reg_unlock(chip); 895 896 if (err && err != -EOPNOTSUPP) 897 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 898 } 899 900 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 901 unsigned int mode, phy_interface_t interface) 902 { 903 struct mv88e6xxx_chip *chip = ds->priv; 904 int err = 0; 905 906 /* Undo the forced down state above after completing configuration 907 * irrespective of its state on entry, which allows the link to come 908 * up in the in-band case where there is no separate SERDES. Also 909 * ensure that the link can come up if the PPU is in use and we are 910 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 911 */ 912 mv88e6xxx_reg_lock(chip); 913 914 if (chip->info->ops->port_set_link && 915 ((mode == MLO_AN_INBAND && 916 chip->ports[port].interface != interface) || 917 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 918 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 919 920 mv88e6xxx_reg_unlock(chip); 921 922 chip->ports[port].interface = interface; 923 924 return err; 925 } 926 927 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 928 unsigned int mode, 929 phy_interface_t interface) 930 { 931 struct mv88e6xxx_chip *chip = ds->priv; 932 const struct mv88e6xxx_ops *ops; 933 int err = 0; 934 935 ops = chip->info->ops; 936 937 mv88e6xxx_reg_lock(chip); 938 /* Force the link down if we know the port may not be automatically 939 * updated by the switch or if we are using fixed-link mode. 940 */ 941 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 942 mode == MLO_AN_FIXED) && ops->port_sync_link) 943 err = ops->port_sync_link(chip, port, mode, false); 944 945 if (!err && ops->port_set_speed_duplex) 946 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 947 DUPLEX_UNFORCED); 948 mv88e6xxx_reg_unlock(chip); 949 950 if (err) 951 dev_err(chip->dev, 952 "p%d: failed to force MAC link down\n", port); 953 } 954 955 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 956 unsigned int mode, phy_interface_t interface, 957 struct phy_device *phydev, 958 int speed, int duplex, 959 bool tx_pause, bool rx_pause) 960 { 961 struct mv88e6xxx_chip *chip = ds->priv; 962 const struct mv88e6xxx_ops *ops; 963 int err = 0; 964 965 ops = chip->info->ops; 966 967 mv88e6xxx_reg_lock(chip); 968 /* Configure and force the link up if we know that the port may not 969 * automatically updated by the switch or if we are using fixed-link 970 * mode. 971 */ 972 if (!mv88e6xxx_port_ppu_updates(chip, port) || 973 mode == MLO_AN_FIXED) { 974 if (ops->port_set_speed_duplex) { 975 err = ops->port_set_speed_duplex(chip, port, 976 speed, duplex); 977 if (err && err != -EOPNOTSUPP) 978 goto error; 979 } 980 981 if (ops->port_sync_link) 982 err = ops->port_sync_link(chip, port, mode, true); 983 } 984 error: 985 mv88e6xxx_reg_unlock(chip); 986 987 if (err && err != -EOPNOTSUPP) 988 dev_err(ds->dev, 989 "p%d: failed to configure MAC link up\n", port); 990 } 991 992 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 993 { 994 if (!chip->info->ops->stats_snapshot) 995 return -EOPNOTSUPP; 996 997 return chip->info->ops->stats_snapshot(chip, port); 998 } 999 1000 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1001 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 1002 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 1003 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 1004 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 1005 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 1006 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 1007 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 1008 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 1009 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 1010 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 1011 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 1012 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1013 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1014 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1015 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1016 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1017 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1018 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1019 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1020 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1021 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1022 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1023 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1024 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1025 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1026 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1027 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1028 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1029 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1030 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1031 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1032 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1033 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1034 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1035 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1036 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1037 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1038 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1039 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1040 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1041 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1042 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1043 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1044 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1045 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1046 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1047 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1048 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1049 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1050 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1051 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1052 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1053 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1054 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1055 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1056 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1057 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1058 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1059 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1060 }; 1061 1062 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1063 struct mv88e6xxx_hw_stat *s, 1064 int port, u16 bank1_select, 1065 u16 histogram) 1066 { 1067 u32 low; 1068 u32 high = 0; 1069 u16 reg = 0; 1070 int err; 1071 u64 value; 1072 1073 switch (s->type) { 1074 case STATS_TYPE_PORT: 1075 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1076 if (err) 1077 return U64_MAX; 1078 1079 low = reg; 1080 if (s->size == 4) { 1081 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1082 if (err) 1083 return U64_MAX; 1084 low |= ((u32)reg) << 16; 1085 } 1086 break; 1087 case STATS_TYPE_BANK1: 1088 reg = bank1_select; 1089 fallthrough; 1090 case STATS_TYPE_BANK0: 1091 reg |= s->reg | histogram; 1092 mv88e6xxx_g1_stats_read(chip, reg, &low); 1093 if (s->size == 8) 1094 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1095 break; 1096 default: 1097 return U64_MAX; 1098 } 1099 value = (((u64)high) << 32) | low; 1100 return value; 1101 } 1102 1103 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1104 uint8_t *data, int types) 1105 { 1106 struct mv88e6xxx_hw_stat *stat; 1107 int i, j; 1108 1109 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1110 stat = &mv88e6xxx_hw_stats[i]; 1111 if (stat->type & types) { 1112 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1113 ETH_GSTRING_LEN); 1114 j++; 1115 } 1116 } 1117 1118 return j; 1119 } 1120 1121 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1122 uint8_t *data) 1123 { 1124 return mv88e6xxx_stats_get_strings(chip, data, 1125 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1126 } 1127 1128 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1129 uint8_t *data) 1130 { 1131 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1132 } 1133 1134 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1135 uint8_t *data) 1136 { 1137 return mv88e6xxx_stats_get_strings(chip, data, 1138 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1139 } 1140 1141 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1142 "atu_member_violation", 1143 "atu_miss_violation", 1144 "atu_full_violation", 1145 "vtu_member_violation", 1146 "vtu_miss_violation", 1147 }; 1148 1149 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1150 { 1151 unsigned int i; 1152 1153 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1154 strscpy(data + i * ETH_GSTRING_LEN, 1155 mv88e6xxx_atu_vtu_stats_strings[i], 1156 ETH_GSTRING_LEN); 1157 } 1158 1159 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1160 u32 stringset, uint8_t *data) 1161 { 1162 struct mv88e6xxx_chip *chip = ds->priv; 1163 int count = 0; 1164 1165 if (stringset != ETH_SS_STATS) 1166 return; 1167 1168 mv88e6xxx_reg_lock(chip); 1169 1170 if (chip->info->ops->stats_get_strings) 1171 count = chip->info->ops->stats_get_strings(chip, data); 1172 1173 if (chip->info->ops->serdes_get_strings) { 1174 data += count * ETH_GSTRING_LEN; 1175 count = chip->info->ops->serdes_get_strings(chip, port, data); 1176 } 1177 1178 data += count * ETH_GSTRING_LEN; 1179 mv88e6xxx_atu_vtu_get_strings(data); 1180 1181 mv88e6xxx_reg_unlock(chip); 1182 } 1183 1184 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1185 int types) 1186 { 1187 struct mv88e6xxx_hw_stat *stat; 1188 int i, j; 1189 1190 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1191 stat = &mv88e6xxx_hw_stats[i]; 1192 if (stat->type & types) 1193 j++; 1194 } 1195 return j; 1196 } 1197 1198 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1199 { 1200 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1201 STATS_TYPE_PORT); 1202 } 1203 1204 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1205 { 1206 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1207 } 1208 1209 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1210 { 1211 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1212 STATS_TYPE_BANK1); 1213 } 1214 1215 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1216 { 1217 struct mv88e6xxx_chip *chip = ds->priv; 1218 int serdes_count = 0; 1219 int count = 0; 1220 1221 if (sset != ETH_SS_STATS) 1222 return 0; 1223 1224 mv88e6xxx_reg_lock(chip); 1225 if (chip->info->ops->stats_get_sset_count) 1226 count = chip->info->ops->stats_get_sset_count(chip); 1227 if (count < 0) 1228 goto out; 1229 1230 if (chip->info->ops->serdes_get_sset_count) 1231 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1232 port); 1233 if (serdes_count < 0) { 1234 count = serdes_count; 1235 goto out; 1236 } 1237 count += serdes_count; 1238 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1239 1240 out: 1241 mv88e6xxx_reg_unlock(chip); 1242 1243 return count; 1244 } 1245 1246 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1247 uint64_t *data, int types, 1248 u16 bank1_select, u16 histogram) 1249 { 1250 struct mv88e6xxx_hw_stat *stat; 1251 int i, j; 1252 1253 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1254 stat = &mv88e6xxx_hw_stats[i]; 1255 if (stat->type & types) { 1256 mv88e6xxx_reg_lock(chip); 1257 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1258 bank1_select, 1259 histogram); 1260 mv88e6xxx_reg_unlock(chip); 1261 1262 j++; 1263 } 1264 } 1265 return j; 1266 } 1267 1268 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1269 uint64_t *data) 1270 { 1271 return mv88e6xxx_stats_get_stats(chip, port, data, 1272 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1273 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1274 } 1275 1276 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1277 uint64_t *data) 1278 { 1279 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1280 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1281 } 1282 1283 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1284 uint64_t *data) 1285 { 1286 return mv88e6xxx_stats_get_stats(chip, port, data, 1287 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1288 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1289 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1290 } 1291 1292 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1293 uint64_t *data) 1294 { 1295 return mv88e6xxx_stats_get_stats(chip, port, data, 1296 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1297 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1298 0); 1299 } 1300 1301 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1302 uint64_t *data) 1303 { 1304 *data++ = chip->ports[port].atu_member_violation; 1305 *data++ = chip->ports[port].atu_miss_violation; 1306 *data++ = chip->ports[port].atu_full_violation; 1307 *data++ = chip->ports[port].vtu_member_violation; 1308 *data++ = chip->ports[port].vtu_miss_violation; 1309 } 1310 1311 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1312 uint64_t *data) 1313 { 1314 int count = 0; 1315 1316 if (chip->info->ops->stats_get_stats) 1317 count = chip->info->ops->stats_get_stats(chip, port, data); 1318 1319 mv88e6xxx_reg_lock(chip); 1320 if (chip->info->ops->serdes_get_stats) { 1321 data += count; 1322 count = chip->info->ops->serdes_get_stats(chip, port, data); 1323 } 1324 data += count; 1325 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1326 mv88e6xxx_reg_unlock(chip); 1327 } 1328 1329 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1330 uint64_t *data) 1331 { 1332 struct mv88e6xxx_chip *chip = ds->priv; 1333 int ret; 1334 1335 mv88e6xxx_reg_lock(chip); 1336 1337 ret = mv88e6xxx_stats_snapshot(chip, port); 1338 mv88e6xxx_reg_unlock(chip); 1339 1340 if (ret < 0) 1341 return; 1342 1343 mv88e6xxx_get_stats(chip, port, data); 1344 1345 } 1346 1347 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1348 { 1349 struct mv88e6xxx_chip *chip = ds->priv; 1350 int len; 1351 1352 len = 32 * sizeof(u16); 1353 if (chip->info->ops->serdes_get_regs_len) 1354 len += chip->info->ops->serdes_get_regs_len(chip, port); 1355 1356 return len; 1357 } 1358 1359 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1360 struct ethtool_regs *regs, void *_p) 1361 { 1362 struct mv88e6xxx_chip *chip = ds->priv; 1363 int err; 1364 u16 reg; 1365 u16 *p = _p; 1366 int i; 1367 1368 regs->version = chip->info->prod_num; 1369 1370 memset(p, 0xff, 32 * sizeof(u16)); 1371 1372 mv88e6xxx_reg_lock(chip); 1373 1374 for (i = 0; i < 32; i++) { 1375 1376 err = mv88e6xxx_port_read(chip, port, i, ®); 1377 if (!err) 1378 p[i] = reg; 1379 } 1380 1381 if (chip->info->ops->serdes_get_regs) 1382 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1383 1384 mv88e6xxx_reg_unlock(chip); 1385 } 1386 1387 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1388 struct ethtool_eee *e) 1389 { 1390 /* Nothing to do on the port's MAC */ 1391 return 0; 1392 } 1393 1394 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1395 struct ethtool_eee *e) 1396 { 1397 /* Nothing to do on the port's MAC */ 1398 return 0; 1399 } 1400 1401 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1402 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1403 { 1404 struct dsa_switch *ds = chip->ds; 1405 struct dsa_switch_tree *dst = ds->dst; 1406 struct dsa_port *dp, *other_dp; 1407 bool found = false; 1408 u16 pvlan; 1409 1410 /* dev is a physical switch */ 1411 if (dev <= dst->last_switch) { 1412 list_for_each_entry(dp, &dst->ports, list) { 1413 if (dp->ds->index == dev && dp->index == port) { 1414 /* dp might be a DSA link or a user port, so it 1415 * might or might not have a bridge. 1416 * Use the "found" variable for both cases. 1417 */ 1418 found = true; 1419 break; 1420 } 1421 } 1422 /* dev is a virtual bridge */ 1423 } else { 1424 list_for_each_entry(dp, &dst->ports, list) { 1425 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1426 1427 if (!bridge_num) 1428 continue; 1429 1430 if (bridge_num + dst->last_switch != dev) 1431 continue; 1432 1433 found = true; 1434 break; 1435 } 1436 } 1437 1438 /* Prevent frames from unknown switch or virtual bridge */ 1439 if (!found) 1440 return 0; 1441 1442 /* Frames from DSA links and CPU ports can egress any local port */ 1443 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1444 return mv88e6xxx_port_mask(chip); 1445 1446 pvlan = 0; 1447 1448 /* Frames from standalone user ports can only egress on the 1449 * upstream port. 1450 */ 1451 if (!dsa_port_bridge_dev_get(dp)) 1452 return BIT(dsa_switch_upstream_port(ds)); 1453 1454 /* Frames from bridged user ports can egress any local DSA 1455 * links and CPU ports, as well as any local member of their 1456 * bridge group. 1457 */ 1458 dsa_switch_for_each_port(other_dp, ds) 1459 if (other_dp->type == DSA_PORT_TYPE_CPU || 1460 other_dp->type == DSA_PORT_TYPE_DSA || 1461 dsa_port_bridge_same(dp, other_dp)) 1462 pvlan |= BIT(other_dp->index); 1463 1464 return pvlan; 1465 } 1466 1467 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1468 { 1469 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1470 1471 /* prevent frames from going back out of the port they came in on */ 1472 output_ports &= ~BIT(port); 1473 1474 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1475 } 1476 1477 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1478 u8 state) 1479 { 1480 struct mv88e6xxx_chip *chip = ds->priv; 1481 int err; 1482 1483 mv88e6xxx_reg_lock(chip); 1484 err = mv88e6xxx_port_set_state(chip, port, state); 1485 mv88e6xxx_reg_unlock(chip); 1486 1487 if (err) 1488 dev_err(ds->dev, "p%d: failed to update state\n", port); 1489 } 1490 1491 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1492 { 1493 int err; 1494 1495 if (chip->info->ops->ieee_pri_map) { 1496 err = chip->info->ops->ieee_pri_map(chip); 1497 if (err) 1498 return err; 1499 } 1500 1501 if (chip->info->ops->ip_pri_map) { 1502 err = chip->info->ops->ip_pri_map(chip); 1503 if (err) 1504 return err; 1505 } 1506 1507 return 0; 1508 } 1509 1510 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1511 { 1512 struct dsa_switch *ds = chip->ds; 1513 int target, port; 1514 int err; 1515 1516 if (!chip->info->global2_addr) 1517 return 0; 1518 1519 /* Initialize the routing port to the 32 possible target devices */ 1520 for (target = 0; target < 32; target++) { 1521 port = dsa_routing_port(ds, target); 1522 if (port == ds->num_ports) 1523 port = 0x1f; 1524 1525 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1526 if (err) 1527 return err; 1528 } 1529 1530 if (chip->info->ops->set_cascade_port) { 1531 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1532 err = chip->info->ops->set_cascade_port(chip, port); 1533 if (err) 1534 return err; 1535 } 1536 1537 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1538 if (err) 1539 return err; 1540 1541 return 0; 1542 } 1543 1544 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1545 { 1546 /* Clear all trunk masks and mapping */ 1547 if (chip->info->global2_addr) 1548 return mv88e6xxx_g2_trunk_clear(chip); 1549 1550 return 0; 1551 } 1552 1553 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1554 { 1555 if (chip->info->ops->rmu_disable) 1556 return chip->info->ops->rmu_disable(chip); 1557 1558 return 0; 1559 } 1560 1561 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1562 { 1563 if (chip->info->ops->pot_clear) 1564 return chip->info->ops->pot_clear(chip); 1565 1566 return 0; 1567 } 1568 1569 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1570 { 1571 if (chip->info->ops->mgmt_rsvd2cpu) 1572 return chip->info->ops->mgmt_rsvd2cpu(chip); 1573 1574 return 0; 1575 } 1576 1577 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1578 { 1579 int err; 1580 1581 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1582 if (err) 1583 return err; 1584 1585 /* The chips that have a "learn2all" bit in Global1, ATU 1586 * Control are precisely those whose port registers have a 1587 * Message Port bit in Port Control 1 and hence implement 1588 * ->port_setup_message_port. 1589 */ 1590 if (chip->info->ops->port_setup_message_port) { 1591 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1592 if (err) 1593 return err; 1594 } 1595 1596 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1597 } 1598 1599 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1600 { 1601 int port; 1602 int err; 1603 1604 if (!chip->info->ops->irl_init_all) 1605 return 0; 1606 1607 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1608 /* Disable ingress rate limiting by resetting all per port 1609 * ingress rate limit resources to their initial state. 1610 */ 1611 err = chip->info->ops->irl_init_all(chip, port); 1612 if (err) 1613 return err; 1614 } 1615 1616 return 0; 1617 } 1618 1619 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1620 { 1621 if (chip->info->ops->set_switch_mac) { 1622 u8 addr[ETH_ALEN]; 1623 1624 eth_random_addr(addr); 1625 1626 return chip->info->ops->set_switch_mac(chip, addr); 1627 } 1628 1629 return 0; 1630 } 1631 1632 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1633 { 1634 struct dsa_switch_tree *dst = chip->ds->dst; 1635 struct dsa_switch *ds; 1636 struct dsa_port *dp; 1637 u16 pvlan = 0; 1638 1639 if (!mv88e6xxx_has_pvt(chip)) 1640 return 0; 1641 1642 /* Skip the local source device, which uses in-chip port VLAN */ 1643 if (dev != chip->ds->index) { 1644 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1645 1646 ds = dsa_switch_find(dst->index, dev); 1647 dp = ds ? dsa_to_port(ds, port) : NULL; 1648 if (dp && dp->lag) { 1649 /* As the PVT is used to limit flooding of 1650 * FORWARD frames, which use the LAG ID as the 1651 * source port, we must translate dev/port to 1652 * the special "LAG device" in the PVT, using 1653 * the LAG ID (one-based) as the port number 1654 * (zero-based). 1655 */ 1656 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1657 port = dsa_port_lag_id_get(dp) - 1; 1658 } 1659 } 1660 1661 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1662 } 1663 1664 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1665 { 1666 int dev, port; 1667 int err; 1668 1669 if (!mv88e6xxx_has_pvt(chip)) 1670 return 0; 1671 1672 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1673 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1674 */ 1675 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1676 if (err) 1677 return err; 1678 1679 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1680 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1681 err = mv88e6xxx_pvt_map(chip, dev, port); 1682 if (err) 1683 return err; 1684 } 1685 } 1686 1687 return 0; 1688 } 1689 1690 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1691 u16 fid) 1692 { 1693 if (dsa_to_port(chip->ds, port)->lag) 1694 /* Hardware is incapable of fast-aging a LAG through a 1695 * regular ATU move operation. Until we have something 1696 * more fancy in place this is a no-op. 1697 */ 1698 return -EOPNOTSUPP; 1699 1700 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1701 } 1702 1703 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1704 { 1705 struct mv88e6xxx_chip *chip = ds->priv; 1706 int err; 1707 1708 mv88e6xxx_reg_lock(chip); 1709 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1710 mv88e6xxx_reg_unlock(chip); 1711 1712 if (err) 1713 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1714 port, err); 1715 } 1716 1717 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1718 { 1719 if (!mv88e6xxx_max_vid(chip)) 1720 return 0; 1721 1722 return mv88e6xxx_g1_vtu_flush(chip); 1723 } 1724 1725 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1726 struct mv88e6xxx_vtu_entry *entry) 1727 { 1728 int err; 1729 1730 if (!chip->info->ops->vtu_getnext) 1731 return -EOPNOTSUPP; 1732 1733 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1734 entry->valid = false; 1735 1736 err = chip->info->ops->vtu_getnext(chip, entry); 1737 1738 if (entry->vid != vid) 1739 entry->valid = false; 1740 1741 return err; 1742 } 1743 1744 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1745 int (*cb)(struct mv88e6xxx_chip *chip, 1746 const struct mv88e6xxx_vtu_entry *entry, 1747 void *priv), 1748 void *priv) 1749 { 1750 struct mv88e6xxx_vtu_entry entry = { 1751 .vid = mv88e6xxx_max_vid(chip), 1752 .valid = false, 1753 }; 1754 int err; 1755 1756 if (!chip->info->ops->vtu_getnext) 1757 return -EOPNOTSUPP; 1758 1759 do { 1760 err = chip->info->ops->vtu_getnext(chip, &entry); 1761 if (err) 1762 return err; 1763 1764 if (!entry.valid) 1765 break; 1766 1767 err = cb(chip, &entry, priv); 1768 if (err) 1769 return err; 1770 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1771 1772 return 0; 1773 } 1774 1775 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1776 struct mv88e6xxx_vtu_entry *entry) 1777 { 1778 if (!chip->info->ops->vtu_loadpurge) 1779 return -EOPNOTSUPP; 1780 1781 return chip->info->ops->vtu_loadpurge(chip, entry); 1782 } 1783 1784 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1785 const struct mv88e6xxx_vtu_entry *entry, 1786 void *_fid_bitmap) 1787 { 1788 unsigned long *fid_bitmap = _fid_bitmap; 1789 1790 set_bit(entry->fid, fid_bitmap); 1791 return 0; 1792 } 1793 1794 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1795 { 1796 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1797 1798 /* Every FID has an associated VID, so walking the VTU 1799 * will discover the full set of FIDs in use. 1800 */ 1801 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1802 } 1803 1804 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1805 { 1806 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1807 int err; 1808 1809 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1810 if (err) 1811 return err; 1812 1813 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1814 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1815 return -ENOSPC; 1816 1817 /* Clear the database */ 1818 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1819 } 1820 1821 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1822 struct mv88e6xxx_stu_entry *entry) 1823 { 1824 if (!chip->info->ops->stu_loadpurge) 1825 return -EOPNOTSUPP; 1826 1827 return chip->info->ops->stu_loadpurge(chip, entry); 1828 } 1829 1830 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1831 { 1832 struct mv88e6xxx_stu_entry stu = { 1833 .valid = true, 1834 .sid = 0 1835 }; 1836 1837 if (!mv88e6xxx_has_stu(chip)) 1838 return 0; 1839 1840 /* Make sure that SID 0 is always valid. This is used by VTU 1841 * entries that do not make use of the STU, e.g. when creating 1842 * a VLAN upper on a port that is also part of a VLAN 1843 * filtering bridge. 1844 */ 1845 return mv88e6xxx_stu_loadpurge(chip, &stu); 1846 } 1847 1848 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1849 { 1850 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1851 struct mv88e6xxx_mst *mst; 1852 1853 __set_bit(0, busy); 1854 1855 list_for_each_entry(mst, &chip->msts, node) 1856 __set_bit(mst->stu.sid, busy); 1857 1858 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1859 1860 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1861 } 1862 1863 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1864 { 1865 struct mv88e6xxx_mst *mst, *tmp; 1866 int err; 1867 1868 if (!sid) 1869 return 0; 1870 1871 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1872 if (mst->stu.sid != sid) 1873 continue; 1874 1875 if (!refcount_dec_and_test(&mst->refcnt)) 1876 return 0; 1877 1878 mst->stu.valid = false; 1879 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1880 if (err) { 1881 refcount_set(&mst->refcnt, 1); 1882 return err; 1883 } 1884 1885 list_del(&mst->node); 1886 kfree(mst); 1887 return 0; 1888 } 1889 1890 return -ENOENT; 1891 } 1892 1893 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1894 u16 msti, u8 *sid) 1895 { 1896 struct mv88e6xxx_mst *mst; 1897 int err, i; 1898 1899 if (!mv88e6xxx_has_stu(chip)) { 1900 err = -EOPNOTSUPP; 1901 goto err; 1902 } 1903 1904 if (!msti) { 1905 *sid = 0; 1906 return 0; 1907 } 1908 1909 list_for_each_entry(mst, &chip->msts, node) { 1910 if (mst->br == br && mst->msti == msti) { 1911 refcount_inc(&mst->refcnt); 1912 *sid = mst->stu.sid; 1913 return 0; 1914 } 1915 } 1916 1917 err = mv88e6xxx_sid_get(chip, sid); 1918 if (err) 1919 goto err; 1920 1921 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1922 if (!mst) { 1923 err = -ENOMEM; 1924 goto err; 1925 } 1926 1927 INIT_LIST_HEAD(&mst->node); 1928 refcount_set(&mst->refcnt, 1); 1929 mst->br = br; 1930 mst->msti = msti; 1931 mst->stu.valid = true; 1932 mst->stu.sid = *sid; 1933 1934 /* The bridge starts out all ports in the disabled state. But 1935 * a STU state of disabled means to go by the port-global 1936 * state. So we set all user port's initial state to blocking, 1937 * to match the bridge's behavior. 1938 */ 1939 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1940 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1941 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1942 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1943 1944 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1945 if (err) 1946 goto err_free; 1947 1948 list_add_tail(&mst->node, &chip->msts); 1949 return 0; 1950 1951 err_free: 1952 kfree(mst); 1953 err: 1954 return err; 1955 } 1956 1957 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1958 const struct switchdev_mst_state *st) 1959 { 1960 struct dsa_port *dp = dsa_to_port(ds, port); 1961 struct mv88e6xxx_chip *chip = ds->priv; 1962 struct mv88e6xxx_mst *mst; 1963 u8 state; 1964 int err; 1965 1966 if (!mv88e6xxx_has_stu(chip)) 1967 return -EOPNOTSUPP; 1968 1969 switch (st->state) { 1970 case BR_STATE_DISABLED: 1971 case BR_STATE_BLOCKING: 1972 case BR_STATE_LISTENING: 1973 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1974 break; 1975 case BR_STATE_LEARNING: 1976 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1977 break; 1978 case BR_STATE_FORWARDING: 1979 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1980 break; 1981 default: 1982 return -EINVAL; 1983 } 1984 1985 list_for_each_entry(mst, &chip->msts, node) { 1986 if (mst->br == dsa_port_bridge_dev_get(dp) && 1987 mst->msti == st->msti) { 1988 if (mst->stu.state[port] == state) 1989 return 0; 1990 1991 mst->stu.state[port] = state; 1992 mv88e6xxx_reg_lock(chip); 1993 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1994 mv88e6xxx_reg_unlock(chip); 1995 return err; 1996 } 1997 } 1998 1999 return -ENOENT; 2000 } 2001 2002 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2003 u16 vid) 2004 { 2005 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2006 struct mv88e6xxx_chip *chip = ds->priv; 2007 struct mv88e6xxx_vtu_entry vlan; 2008 int err; 2009 2010 /* DSA and CPU ports have to be members of multiple vlans */ 2011 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2012 return 0; 2013 2014 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2015 if (err) 2016 return err; 2017 2018 if (!vlan.valid) 2019 return 0; 2020 2021 dsa_switch_for_each_user_port(other_dp, ds) { 2022 struct net_device *other_br; 2023 2024 if (vlan.member[other_dp->index] == 2025 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2026 continue; 2027 2028 if (dsa_port_bridge_same(dp, other_dp)) 2029 break; /* same bridge, check next VLAN */ 2030 2031 other_br = dsa_port_bridge_dev_get(other_dp); 2032 if (!other_br) 2033 continue; 2034 2035 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2036 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2037 return -EOPNOTSUPP; 2038 } 2039 2040 return 0; 2041 } 2042 2043 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2044 { 2045 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2046 struct net_device *br = dsa_port_bridge_dev_get(dp); 2047 struct mv88e6xxx_port *p = &chip->ports[port]; 2048 u16 pvid = MV88E6XXX_VID_STANDALONE; 2049 bool drop_untagged = false; 2050 int err; 2051 2052 if (br) { 2053 if (br_vlan_enabled(br)) { 2054 pvid = p->bridge_pvid.vid; 2055 drop_untagged = !p->bridge_pvid.valid; 2056 } else { 2057 pvid = MV88E6XXX_VID_BRIDGED; 2058 } 2059 } 2060 2061 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2062 if (err) 2063 return err; 2064 2065 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2066 } 2067 2068 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2069 bool vlan_filtering, 2070 struct netlink_ext_ack *extack) 2071 { 2072 struct mv88e6xxx_chip *chip = ds->priv; 2073 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2074 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2075 int err; 2076 2077 if (!mv88e6xxx_max_vid(chip)) 2078 return -EOPNOTSUPP; 2079 2080 mv88e6xxx_reg_lock(chip); 2081 2082 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2083 if (err) 2084 goto unlock; 2085 2086 err = mv88e6xxx_port_commit_pvid(chip, port); 2087 if (err) 2088 goto unlock; 2089 2090 unlock: 2091 mv88e6xxx_reg_unlock(chip); 2092 2093 return err; 2094 } 2095 2096 static int 2097 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2098 const struct switchdev_obj_port_vlan *vlan) 2099 { 2100 struct mv88e6xxx_chip *chip = ds->priv; 2101 int err; 2102 2103 if (!mv88e6xxx_max_vid(chip)) 2104 return -EOPNOTSUPP; 2105 2106 /* If the requested port doesn't belong to the same bridge as the VLAN 2107 * members, do not support it (yet) and fallback to software VLAN. 2108 */ 2109 mv88e6xxx_reg_lock(chip); 2110 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2111 mv88e6xxx_reg_unlock(chip); 2112 2113 return err; 2114 } 2115 2116 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2117 const unsigned char *addr, u16 vid, 2118 u8 state) 2119 { 2120 struct mv88e6xxx_atu_entry entry; 2121 struct mv88e6xxx_vtu_entry vlan; 2122 u16 fid; 2123 int err; 2124 2125 /* Ports have two private address databases: one for when the port is 2126 * standalone and one for when the port is under a bridge and the 2127 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2128 * address database to remain 100% empty, so we never load an ATU entry 2129 * into a standalone port's database. Therefore, translate the null 2130 * VLAN ID into the port's database used for VLAN-unaware bridging. 2131 */ 2132 if (vid == 0) { 2133 fid = MV88E6XXX_FID_BRIDGED; 2134 } else { 2135 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2136 if (err) 2137 return err; 2138 2139 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2140 if (!vlan.valid) 2141 return -EOPNOTSUPP; 2142 2143 fid = vlan.fid; 2144 } 2145 2146 entry.state = 0; 2147 ether_addr_copy(entry.mac, addr); 2148 eth_addr_dec(entry.mac); 2149 2150 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2151 if (err) 2152 return err; 2153 2154 /* Initialize a fresh ATU entry if it isn't found */ 2155 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2156 memset(&entry, 0, sizeof(entry)); 2157 ether_addr_copy(entry.mac, addr); 2158 } 2159 2160 /* Purge the ATU entry only if no port is using it anymore */ 2161 if (!state) { 2162 entry.portvec &= ~BIT(port); 2163 if (!entry.portvec) 2164 entry.state = 0; 2165 } else { 2166 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2167 entry.portvec = BIT(port); 2168 else 2169 entry.portvec |= BIT(port); 2170 2171 entry.state = state; 2172 } 2173 2174 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2175 } 2176 2177 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2178 const struct mv88e6xxx_policy *policy) 2179 { 2180 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2181 enum mv88e6xxx_policy_action action = policy->action; 2182 const u8 *addr = policy->addr; 2183 u16 vid = policy->vid; 2184 u8 state; 2185 int err; 2186 int id; 2187 2188 if (!chip->info->ops->port_set_policy) 2189 return -EOPNOTSUPP; 2190 2191 switch (mapping) { 2192 case MV88E6XXX_POLICY_MAPPING_DA: 2193 case MV88E6XXX_POLICY_MAPPING_SA: 2194 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2195 state = 0; /* Dissociate the port and address */ 2196 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2197 is_multicast_ether_addr(addr)) 2198 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2199 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2200 is_unicast_ether_addr(addr)) 2201 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2202 else 2203 return -EOPNOTSUPP; 2204 2205 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2206 state); 2207 if (err) 2208 return err; 2209 break; 2210 default: 2211 return -EOPNOTSUPP; 2212 } 2213 2214 /* Skip the port's policy clearing if the mapping is still in use */ 2215 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2216 idr_for_each_entry(&chip->policies, policy, id) 2217 if (policy->port == port && 2218 policy->mapping == mapping && 2219 policy->action != action) 2220 return 0; 2221 2222 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2223 } 2224 2225 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2226 struct ethtool_rx_flow_spec *fs) 2227 { 2228 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2229 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2230 enum mv88e6xxx_policy_mapping mapping; 2231 enum mv88e6xxx_policy_action action; 2232 struct mv88e6xxx_policy *policy; 2233 u16 vid = 0; 2234 u8 *addr; 2235 int err; 2236 int id; 2237 2238 if (fs->location != RX_CLS_LOC_ANY) 2239 return -EINVAL; 2240 2241 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2242 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2243 else 2244 return -EOPNOTSUPP; 2245 2246 switch (fs->flow_type & ~FLOW_EXT) { 2247 case ETHER_FLOW: 2248 if (!is_zero_ether_addr(mac_mask->h_dest) && 2249 is_zero_ether_addr(mac_mask->h_source)) { 2250 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2251 addr = mac_entry->h_dest; 2252 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2253 !is_zero_ether_addr(mac_mask->h_source)) { 2254 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2255 addr = mac_entry->h_source; 2256 } else { 2257 /* Cannot support DA and SA mapping in the same rule */ 2258 return -EOPNOTSUPP; 2259 } 2260 break; 2261 default: 2262 return -EOPNOTSUPP; 2263 } 2264 2265 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2266 if (fs->m_ext.vlan_tci != htons(0xffff)) 2267 return -EOPNOTSUPP; 2268 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2269 } 2270 2271 idr_for_each_entry(&chip->policies, policy, id) { 2272 if (policy->port == port && policy->mapping == mapping && 2273 policy->action == action && policy->vid == vid && 2274 ether_addr_equal(policy->addr, addr)) 2275 return -EEXIST; 2276 } 2277 2278 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2279 if (!policy) 2280 return -ENOMEM; 2281 2282 fs->location = 0; 2283 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2284 GFP_KERNEL); 2285 if (err) { 2286 devm_kfree(chip->dev, policy); 2287 return err; 2288 } 2289 2290 memcpy(&policy->fs, fs, sizeof(*fs)); 2291 ether_addr_copy(policy->addr, addr); 2292 policy->mapping = mapping; 2293 policy->action = action; 2294 policy->port = port; 2295 policy->vid = vid; 2296 2297 err = mv88e6xxx_policy_apply(chip, port, policy); 2298 if (err) { 2299 idr_remove(&chip->policies, fs->location); 2300 devm_kfree(chip->dev, policy); 2301 return err; 2302 } 2303 2304 return 0; 2305 } 2306 2307 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2308 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2309 { 2310 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2311 struct mv88e6xxx_chip *chip = ds->priv; 2312 struct mv88e6xxx_policy *policy; 2313 int err; 2314 int id; 2315 2316 mv88e6xxx_reg_lock(chip); 2317 2318 switch (rxnfc->cmd) { 2319 case ETHTOOL_GRXCLSRLCNT: 2320 rxnfc->data = 0; 2321 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2322 rxnfc->rule_cnt = 0; 2323 idr_for_each_entry(&chip->policies, policy, id) 2324 if (policy->port == port) 2325 rxnfc->rule_cnt++; 2326 err = 0; 2327 break; 2328 case ETHTOOL_GRXCLSRULE: 2329 err = -ENOENT; 2330 policy = idr_find(&chip->policies, fs->location); 2331 if (policy) { 2332 memcpy(fs, &policy->fs, sizeof(*fs)); 2333 err = 0; 2334 } 2335 break; 2336 case ETHTOOL_GRXCLSRLALL: 2337 rxnfc->data = 0; 2338 rxnfc->rule_cnt = 0; 2339 idr_for_each_entry(&chip->policies, policy, id) 2340 if (policy->port == port) 2341 rule_locs[rxnfc->rule_cnt++] = id; 2342 err = 0; 2343 break; 2344 default: 2345 err = -EOPNOTSUPP; 2346 break; 2347 } 2348 2349 mv88e6xxx_reg_unlock(chip); 2350 2351 return err; 2352 } 2353 2354 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2355 struct ethtool_rxnfc *rxnfc) 2356 { 2357 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2358 struct mv88e6xxx_chip *chip = ds->priv; 2359 struct mv88e6xxx_policy *policy; 2360 int err; 2361 2362 mv88e6xxx_reg_lock(chip); 2363 2364 switch (rxnfc->cmd) { 2365 case ETHTOOL_SRXCLSRLINS: 2366 err = mv88e6xxx_policy_insert(chip, port, fs); 2367 break; 2368 case ETHTOOL_SRXCLSRLDEL: 2369 err = -ENOENT; 2370 policy = idr_remove(&chip->policies, fs->location); 2371 if (policy) { 2372 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2373 err = mv88e6xxx_policy_apply(chip, port, policy); 2374 devm_kfree(chip->dev, policy); 2375 } 2376 break; 2377 default: 2378 err = -EOPNOTSUPP; 2379 break; 2380 } 2381 2382 mv88e6xxx_reg_unlock(chip); 2383 2384 return err; 2385 } 2386 2387 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2388 u16 vid) 2389 { 2390 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2391 u8 broadcast[ETH_ALEN]; 2392 2393 eth_broadcast_addr(broadcast); 2394 2395 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2396 } 2397 2398 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2399 { 2400 int port; 2401 int err; 2402 2403 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2404 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2405 struct net_device *brport; 2406 2407 if (dsa_is_unused_port(chip->ds, port)) 2408 continue; 2409 2410 brport = dsa_port_to_bridge_port(dp); 2411 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2412 /* Skip bridged user ports where broadcast 2413 * flooding is disabled. 2414 */ 2415 continue; 2416 2417 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2418 if (err) 2419 return err; 2420 } 2421 2422 return 0; 2423 } 2424 2425 struct mv88e6xxx_port_broadcast_sync_ctx { 2426 int port; 2427 bool flood; 2428 }; 2429 2430 static int 2431 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2432 const struct mv88e6xxx_vtu_entry *vlan, 2433 void *_ctx) 2434 { 2435 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2436 u8 broadcast[ETH_ALEN]; 2437 u8 state; 2438 2439 if (ctx->flood) 2440 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2441 else 2442 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2443 2444 eth_broadcast_addr(broadcast); 2445 2446 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2447 vlan->vid, state); 2448 } 2449 2450 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2451 bool flood) 2452 { 2453 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2454 .port = port, 2455 .flood = flood, 2456 }; 2457 struct mv88e6xxx_vtu_entry vid0 = { 2458 .vid = 0, 2459 }; 2460 int err; 2461 2462 /* Update the port's private database... */ 2463 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2464 if (err) 2465 return err; 2466 2467 /* ...and the database for all VLANs. */ 2468 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2469 &ctx); 2470 } 2471 2472 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2473 u16 vid, u8 member, bool warn) 2474 { 2475 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2476 struct mv88e6xxx_vtu_entry vlan; 2477 int i, err; 2478 2479 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2480 if (err) 2481 return err; 2482 2483 if (!vlan.valid) { 2484 memset(&vlan, 0, sizeof(vlan)); 2485 2486 if (vid == MV88E6XXX_VID_STANDALONE) 2487 vlan.policy = true; 2488 2489 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2490 if (err) 2491 return err; 2492 2493 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2494 if (i == port) 2495 vlan.member[i] = member; 2496 else 2497 vlan.member[i] = non_member; 2498 2499 vlan.vid = vid; 2500 vlan.valid = true; 2501 2502 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2503 if (err) 2504 return err; 2505 2506 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2507 if (err) 2508 return err; 2509 } else if (vlan.member[port] != member) { 2510 vlan.member[port] = member; 2511 2512 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2513 if (err) 2514 return err; 2515 } else if (warn) { 2516 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2517 port, vid); 2518 } 2519 2520 return 0; 2521 } 2522 2523 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2524 const struct switchdev_obj_port_vlan *vlan, 2525 struct netlink_ext_ack *extack) 2526 { 2527 struct mv88e6xxx_chip *chip = ds->priv; 2528 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2529 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2530 struct mv88e6xxx_port *p = &chip->ports[port]; 2531 bool warn; 2532 u8 member; 2533 int err; 2534 2535 if (!vlan->vid) 2536 return 0; 2537 2538 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2539 if (err) 2540 return err; 2541 2542 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2543 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2544 else if (untagged) 2545 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2546 else 2547 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2548 2549 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2550 * and then the CPU port. Do not warn for duplicates for the CPU port. 2551 */ 2552 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2553 2554 mv88e6xxx_reg_lock(chip); 2555 2556 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2557 if (err) { 2558 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2559 vlan->vid, untagged ? 'u' : 't'); 2560 goto out; 2561 } 2562 2563 if (pvid) { 2564 p->bridge_pvid.vid = vlan->vid; 2565 p->bridge_pvid.valid = true; 2566 2567 err = mv88e6xxx_port_commit_pvid(chip, port); 2568 if (err) 2569 goto out; 2570 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2571 /* The old pvid was reinstalled as a non-pvid VLAN */ 2572 p->bridge_pvid.valid = false; 2573 2574 err = mv88e6xxx_port_commit_pvid(chip, port); 2575 if (err) 2576 goto out; 2577 } 2578 2579 out: 2580 mv88e6xxx_reg_unlock(chip); 2581 2582 return err; 2583 } 2584 2585 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2586 int port, u16 vid) 2587 { 2588 struct mv88e6xxx_vtu_entry vlan; 2589 int i, err; 2590 2591 if (!vid) 2592 return 0; 2593 2594 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2595 if (err) 2596 return err; 2597 2598 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2599 * tell switchdev that this VLAN is likely handled in software. 2600 */ 2601 if (!vlan.valid || 2602 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2603 return -EOPNOTSUPP; 2604 2605 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2606 2607 /* keep the VLAN unless all ports are excluded */ 2608 vlan.valid = false; 2609 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2610 if (vlan.member[i] != 2611 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2612 vlan.valid = true; 2613 break; 2614 } 2615 } 2616 2617 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2618 if (err) 2619 return err; 2620 2621 if (!vlan.valid) { 2622 err = mv88e6xxx_mst_put(chip, vlan.sid); 2623 if (err) 2624 return err; 2625 } 2626 2627 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2628 } 2629 2630 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2631 const struct switchdev_obj_port_vlan *vlan) 2632 { 2633 struct mv88e6xxx_chip *chip = ds->priv; 2634 struct mv88e6xxx_port *p = &chip->ports[port]; 2635 int err = 0; 2636 u16 pvid; 2637 2638 if (!mv88e6xxx_max_vid(chip)) 2639 return -EOPNOTSUPP; 2640 2641 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2642 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2643 * switchdev workqueue to ensure that all FDB entries are deleted 2644 * before we remove the VLAN. 2645 */ 2646 dsa_flush_workqueue(); 2647 2648 mv88e6xxx_reg_lock(chip); 2649 2650 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2651 if (err) 2652 goto unlock; 2653 2654 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2655 if (err) 2656 goto unlock; 2657 2658 if (vlan->vid == pvid) { 2659 p->bridge_pvid.valid = false; 2660 2661 err = mv88e6xxx_port_commit_pvid(chip, port); 2662 if (err) 2663 goto unlock; 2664 } 2665 2666 unlock: 2667 mv88e6xxx_reg_unlock(chip); 2668 2669 return err; 2670 } 2671 2672 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2673 { 2674 struct mv88e6xxx_chip *chip = ds->priv; 2675 struct mv88e6xxx_vtu_entry vlan; 2676 int err; 2677 2678 mv88e6xxx_reg_lock(chip); 2679 2680 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2681 if (err) 2682 goto unlock; 2683 2684 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2685 2686 unlock: 2687 mv88e6xxx_reg_unlock(chip); 2688 2689 return err; 2690 } 2691 2692 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2693 struct dsa_bridge bridge, 2694 const struct switchdev_vlan_msti *msti) 2695 { 2696 struct mv88e6xxx_chip *chip = ds->priv; 2697 struct mv88e6xxx_vtu_entry vlan; 2698 u8 old_sid, new_sid; 2699 int err; 2700 2701 if (!mv88e6xxx_has_stu(chip)) 2702 return -EOPNOTSUPP; 2703 2704 mv88e6xxx_reg_lock(chip); 2705 2706 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2707 if (err) 2708 goto unlock; 2709 2710 if (!vlan.valid) { 2711 err = -EINVAL; 2712 goto unlock; 2713 } 2714 2715 old_sid = vlan.sid; 2716 2717 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2718 if (err) 2719 goto unlock; 2720 2721 if (new_sid != old_sid) { 2722 vlan.sid = new_sid; 2723 2724 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2725 if (err) { 2726 mv88e6xxx_mst_put(chip, new_sid); 2727 goto unlock; 2728 } 2729 } 2730 2731 err = mv88e6xxx_mst_put(chip, old_sid); 2732 2733 unlock: 2734 mv88e6xxx_reg_unlock(chip); 2735 return err; 2736 } 2737 2738 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2739 const unsigned char *addr, u16 vid, 2740 struct dsa_db db) 2741 { 2742 struct mv88e6xxx_chip *chip = ds->priv; 2743 int err; 2744 2745 mv88e6xxx_reg_lock(chip); 2746 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2747 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2748 mv88e6xxx_reg_unlock(chip); 2749 2750 return err; 2751 } 2752 2753 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2754 const unsigned char *addr, u16 vid, 2755 struct dsa_db db) 2756 { 2757 struct mv88e6xxx_chip *chip = ds->priv; 2758 int err; 2759 2760 mv88e6xxx_reg_lock(chip); 2761 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2762 mv88e6xxx_reg_unlock(chip); 2763 2764 return err; 2765 } 2766 2767 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2768 u16 fid, u16 vid, int port, 2769 dsa_fdb_dump_cb_t *cb, void *data) 2770 { 2771 struct mv88e6xxx_atu_entry addr; 2772 bool is_static; 2773 int err; 2774 2775 addr.state = 0; 2776 eth_broadcast_addr(addr.mac); 2777 2778 do { 2779 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2780 if (err) 2781 return err; 2782 2783 if (!addr.state) 2784 break; 2785 2786 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2787 continue; 2788 2789 if (!is_unicast_ether_addr(addr.mac)) 2790 continue; 2791 2792 is_static = (addr.state == 2793 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2794 err = cb(addr.mac, vid, is_static, data); 2795 if (err) 2796 return err; 2797 } while (!is_broadcast_ether_addr(addr.mac)); 2798 2799 return err; 2800 } 2801 2802 struct mv88e6xxx_port_db_dump_vlan_ctx { 2803 int port; 2804 dsa_fdb_dump_cb_t *cb; 2805 void *data; 2806 }; 2807 2808 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2809 const struct mv88e6xxx_vtu_entry *entry, 2810 void *_data) 2811 { 2812 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2813 2814 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2815 ctx->port, ctx->cb, ctx->data); 2816 } 2817 2818 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2819 dsa_fdb_dump_cb_t *cb, void *data) 2820 { 2821 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2822 .port = port, 2823 .cb = cb, 2824 .data = data, 2825 }; 2826 u16 fid; 2827 int err; 2828 2829 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2830 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2831 if (err) 2832 return err; 2833 2834 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2835 if (err) 2836 return err; 2837 2838 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2839 } 2840 2841 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2842 dsa_fdb_dump_cb_t *cb, void *data) 2843 { 2844 struct mv88e6xxx_chip *chip = ds->priv; 2845 int err; 2846 2847 mv88e6xxx_reg_lock(chip); 2848 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2849 mv88e6xxx_reg_unlock(chip); 2850 2851 return err; 2852 } 2853 2854 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2855 struct dsa_bridge bridge) 2856 { 2857 struct dsa_switch *ds = chip->ds; 2858 struct dsa_switch_tree *dst = ds->dst; 2859 struct dsa_port *dp; 2860 int err; 2861 2862 list_for_each_entry(dp, &dst->ports, list) { 2863 if (dsa_port_offloads_bridge(dp, &bridge)) { 2864 if (dp->ds == ds) { 2865 /* This is a local bridge group member, 2866 * remap its Port VLAN Map. 2867 */ 2868 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2869 if (err) 2870 return err; 2871 } else { 2872 /* This is an external bridge group member, 2873 * remap its cross-chip Port VLAN Table entry. 2874 */ 2875 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2876 dp->index); 2877 if (err) 2878 return err; 2879 } 2880 } 2881 } 2882 2883 return 0; 2884 } 2885 2886 /* Treat the software bridge as a virtual single-port switch behind the 2887 * CPU and map in the PVT. First dst->last_switch elements are taken by 2888 * physical switches, so start from beyond that range. 2889 */ 2890 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2891 unsigned int bridge_num) 2892 { 2893 u8 dev = bridge_num + ds->dst->last_switch; 2894 struct mv88e6xxx_chip *chip = ds->priv; 2895 2896 return mv88e6xxx_pvt_map(chip, dev, 0); 2897 } 2898 2899 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2900 struct dsa_bridge bridge, 2901 bool *tx_fwd_offload, 2902 struct netlink_ext_ack *extack) 2903 { 2904 struct mv88e6xxx_chip *chip = ds->priv; 2905 int err; 2906 2907 mv88e6xxx_reg_lock(chip); 2908 2909 err = mv88e6xxx_bridge_map(chip, bridge); 2910 if (err) 2911 goto unlock; 2912 2913 err = mv88e6xxx_port_set_map_da(chip, port, true); 2914 if (err) 2915 goto unlock; 2916 2917 err = mv88e6xxx_port_commit_pvid(chip, port); 2918 if (err) 2919 goto unlock; 2920 2921 if (mv88e6xxx_has_pvt(chip)) { 2922 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2923 if (err) 2924 goto unlock; 2925 2926 *tx_fwd_offload = true; 2927 } 2928 2929 unlock: 2930 mv88e6xxx_reg_unlock(chip); 2931 2932 return err; 2933 } 2934 2935 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2936 struct dsa_bridge bridge) 2937 { 2938 struct mv88e6xxx_chip *chip = ds->priv; 2939 int err; 2940 2941 mv88e6xxx_reg_lock(chip); 2942 2943 if (bridge.tx_fwd_offload && 2944 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2945 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2946 2947 if (mv88e6xxx_bridge_map(chip, bridge) || 2948 mv88e6xxx_port_vlan_map(chip, port)) 2949 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2950 2951 err = mv88e6xxx_port_set_map_da(chip, port, false); 2952 if (err) 2953 dev_err(ds->dev, 2954 "port %d failed to restore map-DA: %pe\n", 2955 port, ERR_PTR(err)); 2956 2957 err = mv88e6xxx_port_commit_pvid(chip, port); 2958 if (err) 2959 dev_err(ds->dev, 2960 "port %d failed to restore standalone pvid: %pe\n", 2961 port, ERR_PTR(err)); 2962 2963 mv88e6xxx_reg_unlock(chip); 2964 } 2965 2966 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2967 int tree_index, int sw_index, 2968 int port, struct dsa_bridge bridge, 2969 struct netlink_ext_ack *extack) 2970 { 2971 struct mv88e6xxx_chip *chip = ds->priv; 2972 int err; 2973 2974 if (tree_index != ds->dst->index) 2975 return 0; 2976 2977 mv88e6xxx_reg_lock(chip); 2978 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2979 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2980 mv88e6xxx_reg_unlock(chip); 2981 2982 return err; 2983 } 2984 2985 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2986 int tree_index, int sw_index, 2987 int port, struct dsa_bridge bridge) 2988 { 2989 struct mv88e6xxx_chip *chip = ds->priv; 2990 2991 if (tree_index != ds->dst->index) 2992 return; 2993 2994 mv88e6xxx_reg_lock(chip); 2995 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 2996 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2997 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2998 mv88e6xxx_reg_unlock(chip); 2999 } 3000 3001 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3002 { 3003 if (chip->info->ops->reset) 3004 return chip->info->ops->reset(chip); 3005 3006 return 0; 3007 } 3008 3009 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3010 { 3011 struct gpio_desc *gpiod = chip->reset; 3012 3013 /* If there is a GPIO connected to the reset pin, toggle it */ 3014 if (gpiod) { 3015 /* If the switch has just been reset and not yet completed 3016 * loading EEPROM, the reset may interrupt the I2C transaction 3017 * mid-byte, causing the first EEPROM read after the reset 3018 * from the wrong location resulting in the switch booting 3019 * to wrong mode and inoperable. 3020 */ 3021 if (chip->info->ops->get_eeprom) 3022 mv88e6xxx_g2_eeprom_wait(chip); 3023 3024 gpiod_set_value_cansleep(gpiod, 1); 3025 usleep_range(10000, 20000); 3026 gpiod_set_value_cansleep(gpiod, 0); 3027 usleep_range(10000, 20000); 3028 3029 if (chip->info->ops->get_eeprom) 3030 mv88e6xxx_g2_eeprom_wait(chip); 3031 } 3032 } 3033 3034 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3035 { 3036 int i, err; 3037 3038 /* Set all ports to the Disabled state */ 3039 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3040 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3041 if (err) 3042 return err; 3043 } 3044 3045 /* Wait for transmit queues to drain, 3046 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3047 */ 3048 usleep_range(2000, 4000); 3049 3050 return 0; 3051 } 3052 3053 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3054 { 3055 int err; 3056 3057 err = mv88e6xxx_disable_ports(chip); 3058 if (err) 3059 return err; 3060 3061 mv88e6xxx_hardware_reset(chip); 3062 3063 return mv88e6xxx_software_reset(chip); 3064 } 3065 3066 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3067 enum mv88e6xxx_frame_mode frame, 3068 enum mv88e6xxx_egress_mode egress, u16 etype) 3069 { 3070 int err; 3071 3072 if (!chip->info->ops->port_set_frame_mode) 3073 return -EOPNOTSUPP; 3074 3075 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3076 if (err) 3077 return err; 3078 3079 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3080 if (err) 3081 return err; 3082 3083 if (chip->info->ops->port_set_ether_type) 3084 return chip->info->ops->port_set_ether_type(chip, port, etype); 3085 3086 return 0; 3087 } 3088 3089 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3090 { 3091 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3092 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3093 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3094 } 3095 3096 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3097 { 3098 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3099 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3100 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3101 } 3102 3103 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3104 { 3105 return mv88e6xxx_set_port_mode(chip, port, 3106 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3107 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3108 ETH_P_EDSA); 3109 } 3110 3111 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3112 { 3113 if (dsa_is_dsa_port(chip->ds, port)) 3114 return mv88e6xxx_set_port_mode_dsa(chip, port); 3115 3116 if (dsa_is_user_port(chip->ds, port)) 3117 return mv88e6xxx_set_port_mode_normal(chip, port); 3118 3119 /* Setup CPU port mode depending on its supported tag format */ 3120 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3121 return mv88e6xxx_set_port_mode_dsa(chip, port); 3122 3123 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3124 return mv88e6xxx_set_port_mode_edsa(chip, port); 3125 3126 return -EINVAL; 3127 } 3128 3129 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3130 { 3131 bool message = dsa_is_dsa_port(chip->ds, port); 3132 3133 return mv88e6xxx_port_set_message_port(chip, port, message); 3134 } 3135 3136 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3137 { 3138 int err; 3139 3140 if (chip->info->ops->port_set_ucast_flood) { 3141 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3142 if (err) 3143 return err; 3144 } 3145 if (chip->info->ops->port_set_mcast_flood) { 3146 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3147 if (err) 3148 return err; 3149 } 3150 3151 return 0; 3152 } 3153 3154 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3155 enum mv88e6xxx_egress_direction direction, 3156 int port) 3157 { 3158 int err; 3159 3160 if (!chip->info->ops->set_egress_port) 3161 return -EOPNOTSUPP; 3162 3163 err = chip->info->ops->set_egress_port(chip, direction, port); 3164 if (err) 3165 return err; 3166 3167 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3168 chip->ingress_dest_port = port; 3169 else 3170 chip->egress_dest_port = port; 3171 3172 return 0; 3173 } 3174 3175 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3176 { 3177 struct dsa_switch *ds = chip->ds; 3178 int upstream_port; 3179 int err; 3180 3181 upstream_port = dsa_upstream_port(ds, port); 3182 if (chip->info->ops->port_set_upstream_port) { 3183 err = chip->info->ops->port_set_upstream_port(chip, port, 3184 upstream_port); 3185 if (err) 3186 return err; 3187 } 3188 3189 if (port == upstream_port) { 3190 if (chip->info->ops->set_cpu_port) { 3191 err = chip->info->ops->set_cpu_port(chip, 3192 upstream_port); 3193 if (err) 3194 return err; 3195 } 3196 3197 err = mv88e6xxx_set_egress_port(chip, 3198 MV88E6XXX_EGRESS_DIR_INGRESS, 3199 upstream_port); 3200 if (err && err != -EOPNOTSUPP) 3201 return err; 3202 3203 err = mv88e6xxx_set_egress_port(chip, 3204 MV88E6XXX_EGRESS_DIR_EGRESS, 3205 upstream_port); 3206 if (err && err != -EOPNOTSUPP) 3207 return err; 3208 } 3209 3210 return 0; 3211 } 3212 3213 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3214 { 3215 struct device_node *phy_handle = NULL; 3216 struct dsa_switch *ds = chip->ds; 3217 struct dsa_port *dp; 3218 int tx_amp; 3219 int err; 3220 u16 reg; 3221 3222 chip->ports[port].chip = chip; 3223 chip->ports[port].port = port; 3224 3225 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3226 SPEED_UNFORCED, DUPLEX_UNFORCED, 3227 PAUSE_ON, PHY_INTERFACE_MODE_NA); 3228 if (err) 3229 return err; 3230 3231 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3232 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3233 * tunneling, determine priority by looking at 802.1p and IP 3234 * priority fields (IP prio has precedence), and set STP state 3235 * to Forwarding. 3236 * 3237 * If this is the CPU link, use DSA or EDSA tagging depending 3238 * on which tagging mode was configured. 3239 * 3240 * If this is a link to another switch, use DSA tagging mode. 3241 * 3242 * If this is the upstream port for this switch, enable 3243 * forwarding of unknown unicasts and multicasts. 3244 */ 3245 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3246 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3247 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3248 * by a USER port to the CPU port to allow snooping. 3249 */ 3250 if (dsa_is_user_port(ds, port)) 3251 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3252 3253 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3254 if (err) 3255 return err; 3256 3257 err = mv88e6xxx_setup_port_mode(chip, port); 3258 if (err) 3259 return err; 3260 3261 err = mv88e6xxx_setup_egress_floods(chip, port); 3262 if (err) 3263 return err; 3264 3265 /* Port Control 2: don't force a good FCS, set the MTU size to 3266 * 10222 bytes, disable 802.1q tags checking, don't discard 3267 * tagged or untagged frames on this port, skip destination 3268 * address lookup on user ports, disable ARP mirroring and don't 3269 * send a copy of all transmitted/received frames on this port 3270 * to the CPU. 3271 */ 3272 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3273 if (err) 3274 return err; 3275 3276 err = mv88e6xxx_setup_upstream_port(chip, port); 3277 if (err) 3278 return err; 3279 3280 /* On chips that support it, set all downstream DSA ports' 3281 * VLAN policy to TRAP. In combination with loading 3282 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3283 * provides a better isolation barrier between standalone 3284 * ports, as the ATU is bypassed on any intermediate switches 3285 * between the incoming port and the CPU. 3286 */ 3287 if (dsa_is_downstream_port(ds, port) && 3288 chip->info->ops->port_set_policy) { 3289 err = chip->info->ops->port_set_policy(chip, port, 3290 MV88E6XXX_POLICY_MAPPING_VTU, 3291 MV88E6XXX_POLICY_ACTION_TRAP); 3292 if (err) 3293 return err; 3294 } 3295 3296 /* User ports start out in standalone mode and 802.1Q is 3297 * therefore disabled. On DSA ports, all valid VIDs are always 3298 * loaded in the VTU - therefore, enable 802.1Q in order to take 3299 * advantage of VLAN policy on chips that supports it. 3300 */ 3301 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3302 dsa_is_user_port(ds, port) ? 3303 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3304 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3305 if (err) 3306 return err; 3307 3308 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3309 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3310 * the first free FID. This will be used as the private PVID for 3311 * unbridged ports. Shared (DSA and CPU) ports must also be 3312 * members of this VID, in order to trap all frames assigned to 3313 * it to the CPU. 3314 */ 3315 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3316 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3317 false); 3318 if (err) 3319 return err; 3320 3321 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3322 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3323 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3324 * as the private PVID on ports under a VLAN-unaware bridge. 3325 * Shared (DSA and CPU) ports must also be members of it, to translate 3326 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3327 * relying on their port default FID. 3328 */ 3329 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3330 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3331 false); 3332 if (err) 3333 return err; 3334 3335 if (chip->info->ops->port_set_jumbo_size) { 3336 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3337 if (err) 3338 return err; 3339 } 3340 3341 /* Port Association Vector: disable automatic address learning 3342 * on all user ports since they start out in standalone 3343 * mode. When joining a bridge, learning will be configured to 3344 * match the bridge port settings. Enable learning on all 3345 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3346 * learning process. 3347 * 3348 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3349 * and RefreshLocked. I.e. setup standard automatic learning. 3350 */ 3351 if (dsa_is_user_port(ds, port)) 3352 reg = 0; 3353 else 3354 reg = 1 << port; 3355 3356 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3357 reg); 3358 if (err) 3359 return err; 3360 3361 /* Egress rate control 2: disable egress rate control. */ 3362 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3363 0x0000); 3364 if (err) 3365 return err; 3366 3367 if (chip->info->ops->port_pause_limit) { 3368 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3369 if (err) 3370 return err; 3371 } 3372 3373 if (chip->info->ops->port_disable_learn_limit) { 3374 err = chip->info->ops->port_disable_learn_limit(chip, port); 3375 if (err) 3376 return err; 3377 } 3378 3379 if (chip->info->ops->port_disable_pri_override) { 3380 err = chip->info->ops->port_disable_pri_override(chip, port); 3381 if (err) 3382 return err; 3383 } 3384 3385 if (chip->info->ops->port_tag_remap) { 3386 err = chip->info->ops->port_tag_remap(chip, port); 3387 if (err) 3388 return err; 3389 } 3390 3391 if (chip->info->ops->port_egress_rate_limiting) { 3392 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3393 if (err) 3394 return err; 3395 } 3396 3397 if (chip->info->ops->port_setup_message_port) { 3398 err = chip->info->ops->port_setup_message_port(chip, port); 3399 if (err) 3400 return err; 3401 } 3402 3403 if (chip->info->ops->serdes_set_tx_amplitude) { 3404 dp = dsa_to_port(ds, port); 3405 if (dp) 3406 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3407 3408 if (phy_handle && !of_property_read_u32(phy_handle, 3409 "tx-p2p-microvolt", 3410 &tx_amp)) 3411 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3412 port, tx_amp); 3413 if (phy_handle) { 3414 of_node_put(phy_handle); 3415 if (err) 3416 return err; 3417 } 3418 } 3419 3420 /* Port based VLAN map: give each port the same default address 3421 * database, and allow bidirectional communication between the 3422 * CPU and DSA port(s), and the other ports. 3423 */ 3424 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3425 if (err) 3426 return err; 3427 3428 err = mv88e6xxx_port_vlan_map(chip, port); 3429 if (err) 3430 return err; 3431 3432 /* Default VLAN ID and priority: don't set a default VLAN 3433 * ID, and set the default packet priority to zero. 3434 */ 3435 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3436 } 3437 3438 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3439 { 3440 struct mv88e6xxx_chip *chip = ds->priv; 3441 3442 if (chip->info->ops->port_set_jumbo_size) 3443 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3444 else if (chip->info->ops->set_max_frame_size) 3445 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3446 return ETH_DATA_LEN; 3447 } 3448 3449 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3450 { 3451 struct mv88e6xxx_chip *chip = ds->priv; 3452 int ret = 0; 3453 3454 /* For families where we don't know how to alter the MTU, 3455 * just accept any value up to ETH_DATA_LEN 3456 */ 3457 if (!chip->info->ops->port_set_jumbo_size && 3458 !chip->info->ops->set_max_frame_size) { 3459 if (new_mtu > ETH_DATA_LEN) 3460 return -EINVAL; 3461 3462 return 0; 3463 } 3464 3465 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3466 new_mtu += EDSA_HLEN; 3467 3468 mv88e6xxx_reg_lock(chip); 3469 if (chip->info->ops->port_set_jumbo_size) 3470 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3471 else if (chip->info->ops->set_max_frame_size) 3472 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3473 mv88e6xxx_reg_unlock(chip); 3474 3475 return ret; 3476 } 3477 3478 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3479 unsigned int ageing_time) 3480 { 3481 struct mv88e6xxx_chip *chip = ds->priv; 3482 int err; 3483 3484 mv88e6xxx_reg_lock(chip); 3485 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3486 mv88e6xxx_reg_unlock(chip); 3487 3488 return err; 3489 } 3490 3491 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3492 { 3493 int err; 3494 3495 /* Initialize the statistics unit */ 3496 if (chip->info->ops->stats_set_histogram) { 3497 err = chip->info->ops->stats_set_histogram(chip); 3498 if (err) 3499 return err; 3500 } 3501 3502 return mv88e6xxx_g1_stats_clear(chip); 3503 } 3504 3505 /* Check if the errata has already been applied. */ 3506 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3507 { 3508 int port; 3509 int err; 3510 u16 val; 3511 3512 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3513 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3514 if (err) { 3515 dev_err(chip->dev, 3516 "Error reading hidden register: %d\n", err); 3517 return false; 3518 } 3519 if (val != 0x01c0) 3520 return false; 3521 } 3522 3523 return true; 3524 } 3525 3526 /* The 6390 copper ports have an errata which require poking magic 3527 * values into undocumented hidden registers and then performing a 3528 * software reset. 3529 */ 3530 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3531 { 3532 int port; 3533 int err; 3534 3535 if (mv88e6390_setup_errata_applied(chip)) 3536 return 0; 3537 3538 /* Set the ports into blocking mode */ 3539 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3540 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3541 if (err) 3542 return err; 3543 } 3544 3545 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3546 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3547 if (err) 3548 return err; 3549 } 3550 3551 return mv88e6xxx_software_reset(chip); 3552 } 3553 3554 /* prod_id for switch families which do not have a PHY model number */ 3555 static const u16 family_prod_id_table[] = { 3556 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3557 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3558 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3559 }; 3560 3561 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3562 { 3563 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3564 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3565 u16 prod_id; 3566 u16 val; 3567 int err; 3568 3569 if (!chip->info->ops->phy_read) 3570 return -EOPNOTSUPP; 3571 3572 mv88e6xxx_reg_lock(chip); 3573 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3574 mv88e6xxx_reg_unlock(chip); 3575 3576 /* Some internal PHYs don't have a model number. */ 3577 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3578 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3579 prod_id = family_prod_id_table[chip->info->family]; 3580 if (prod_id) 3581 val |= prod_id >> 4; 3582 } 3583 3584 return err ? err : val; 3585 } 3586 3587 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3588 int reg) 3589 { 3590 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3591 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3592 u16 val; 3593 int err; 3594 3595 if (!chip->info->ops->phy_read_c45) 3596 return 0xffff; 3597 3598 mv88e6xxx_reg_lock(chip); 3599 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3600 mv88e6xxx_reg_unlock(chip); 3601 3602 return err ? err : val; 3603 } 3604 3605 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3606 { 3607 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3608 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3609 int err; 3610 3611 if (!chip->info->ops->phy_write) 3612 return -EOPNOTSUPP; 3613 3614 mv88e6xxx_reg_lock(chip); 3615 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3616 mv88e6xxx_reg_unlock(chip); 3617 3618 return err; 3619 } 3620 3621 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3622 int reg, u16 val) 3623 { 3624 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3625 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3626 int err; 3627 3628 if (!chip->info->ops->phy_write_c45) 3629 return -EOPNOTSUPP; 3630 3631 mv88e6xxx_reg_lock(chip); 3632 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3633 mv88e6xxx_reg_unlock(chip); 3634 3635 return err; 3636 } 3637 3638 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3639 struct device_node *np, 3640 bool external) 3641 { 3642 static int index; 3643 struct mv88e6xxx_mdio_bus *mdio_bus; 3644 struct mii_bus *bus; 3645 int err; 3646 3647 if (external) { 3648 mv88e6xxx_reg_lock(chip); 3649 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3650 mv88e6xxx_reg_unlock(chip); 3651 3652 if (err) 3653 return err; 3654 } 3655 3656 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3657 if (!bus) 3658 return -ENOMEM; 3659 3660 mdio_bus = bus->priv; 3661 mdio_bus->bus = bus; 3662 mdio_bus->chip = chip; 3663 INIT_LIST_HEAD(&mdio_bus->list); 3664 mdio_bus->external = external; 3665 3666 if (np) { 3667 bus->name = np->full_name; 3668 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3669 } else { 3670 bus->name = "mv88e6xxx SMI"; 3671 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3672 } 3673 3674 bus->read = mv88e6xxx_mdio_read; 3675 bus->write = mv88e6xxx_mdio_write; 3676 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3677 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3678 bus->parent = chip->dev; 3679 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3680 mv88e6xxx_num_ports(chip) - 1, 3681 chip->info->phy_base_addr); 3682 3683 if (!external) { 3684 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3685 if (err) 3686 goto out; 3687 } 3688 3689 err = of_mdiobus_register(bus, np); 3690 if (err) { 3691 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3692 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3693 goto out; 3694 } 3695 3696 if (external) 3697 list_add_tail(&mdio_bus->list, &chip->mdios); 3698 else 3699 list_add(&mdio_bus->list, &chip->mdios); 3700 3701 return 0; 3702 3703 out: 3704 mdiobus_free(bus); 3705 return err; 3706 } 3707 3708 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3709 3710 { 3711 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3712 struct mii_bus *bus; 3713 3714 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3715 bus = mdio_bus->bus; 3716 3717 if (!mdio_bus->external) 3718 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3719 3720 mdiobus_unregister(bus); 3721 mdiobus_free(bus); 3722 } 3723 } 3724 3725 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3726 { 3727 struct device_node *np = chip->dev->of_node; 3728 struct device_node *child; 3729 int err; 3730 3731 /* Always register one mdio bus for the internal/default mdio 3732 * bus. This maybe represented in the device tree, but is 3733 * optional. 3734 */ 3735 child = of_get_child_by_name(np, "mdio"); 3736 err = mv88e6xxx_mdio_register(chip, child, false); 3737 of_node_put(child); 3738 if (err) 3739 return err; 3740 3741 /* Walk the device tree, and see if there are any other nodes 3742 * which say they are compatible with the external mdio 3743 * bus. 3744 */ 3745 for_each_available_child_of_node(np, child) { 3746 if (of_device_is_compatible( 3747 child, "marvell,mv88e6xxx-mdio-external")) { 3748 err = mv88e6xxx_mdio_register(chip, child, true); 3749 if (err) { 3750 mv88e6xxx_mdios_unregister(chip); 3751 of_node_put(child); 3752 return err; 3753 } 3754 } 3755 } 3756 3757 return 0; 3758 } 3759 3760 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3761 { 3762 struct mv88e6xxx_chip *chip = ds->priv; 3763 3764 mv88e6xxx_teardown_devlink_params(ds); 3765 dsa_devlink_resources_unregister(ds); 3766 mv88e6xxx_teardown_devlink_regions_global(ds); 3767 mv88e6xxx_mdios_unregister(chip); 3768 } 3769 3770 static int mv88e6xxx_setup(struct dsa_switch *ds) 3771 { 3772 struct mv88e6xxx_chip *chip = ds->priv; 3773 u8 cmode; 3774 int err; 3775 int i; 3776 3777 err = mv88e6xxx_mdios_register(chip); 3778 if (err) 3779 return err; 3780 3781 chip->ds = ds; 3782 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3783 3784 /* Since virtual bridges are mapped in the PVT, the number we support 3785 * depends on the physical switch topology. We need to let DSA figure 3786 * that out and therefore we cannot set this at dsa_register_switch() 3787 * time. 3788 */ 3789 if (mv88e6xxx_has_pvt(chip)) 3790 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3791 ds->dst->last_switch - 1; 3792 3793 mv88e6xxx_reg_lock(chip); 3794 3795 if (chip->info->ops->setup_errata) { 3796 err = chip->info->ops->setup_errata(chip); 3797 if (err) 3798 goto unlock; 3799 } 3800 3801 /* Cache the cmode of each port. */ 3802 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3803 if (chip->info->ops->port_get_cmode) { 3804 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3805 if (err) 3806 goto unlock; 3807 3808 chip->ports[i].cmode = cmode; 3809 } 3810 } 3811 3812 err = mv88e6xxx_vtu_setup(chip); 3813 if (err) 3814 goto unlock; 3815 3816 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3817 * VTU, thereby also flushing the STU). 3818 */ 3819 err = mv88e6xxx_stu_setup(chip); 3820 if (err) 3821 goto unlock; 3822 3823 /* Setup Switch Port Registers */ 3824 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3825 if (dsa_is_unused_port(ds, i)) 3826 continue; 3827 3828 /* Prevent the use of an invalid port. */ 3829 if (mv88e6xxx_is_invalid_port(chip, i)) { 3830 dev_err(chip->dev, "port %d is invalid\n", i); 3831 err = -EINVAL; 3832 goto unlock; 3833 } 3834 3835 err = mv88e6xxx_setup_port(chip, i); 3836 if (err) 3837 goto unlock; 3838 } 3839 3840 err = mv88e6xxx_irl_setup(chip); 3841 if (err) 3842 goto unlock; 3843 3844 err = mv88e6xxx_mac_setup(chip); 3845 if (err) 3846 goto unlock; 3847 3848 err = mv88e6xxx_phy_setup(chip); 3849 if (err) 3850 goto unlock; 3851 3852 err = mv88e6xxx_pvt_setup(chip); 3853 if (err) 3854 goto unlock; 3855 3856 err = mv88e6xxx_atu_setup(chip); 3857 if (err) 3858 goto unlock; 3859 3860 err = mv88e6xxx_broadcast_setup(chip, 0); 3861 if (err) 3862 goto unlock; 3863 3864 err = mv88e6xxx_pot_setup(chip); 3865 if (err) 3866 goto unlock; 3867 3868 err = mv88e6xxx_rmu_setup(chip); 3869 if (err) 3870 goto unlock; 3871 3872 err = mv88e6xxx_rsvd2cpu_setup(chip); 3873 if (err) 3874 goto unlock; 3875 3876 err = mv88e6xxx_trunk_setup(chip); 3877 if (err) 3878 goto unlock; 3879 3880 err = mv88e6xxx_devmap_setup(chip); 3881 if (err) 3882 goto unlock; 3883 3884 err = mv88e6xxx_pri_setup(chip); 3885 if (err) 3886 goto unlock; 3887 3888 /* Setup PTP Hardware Clock and timestamping */ 3889 if (chip->info->ptp_support) { 3890 err = mv88e6xxx_ptp_setup(chip); 3891 if (err) 3892 goto unlock; 3893 3894 err = mv88e6xxx_hwtstamp_setup(chip); 3895 if (err) 3896 goto unlock; 3897 } 3898 3899 err = mv88e6xxx_stats_setup(chip); 3900 if (err) 3901 goto unlock; 3902 3903 unlock: 3904 mv88e6xxx_reg_unlock(chip); 3905 3906 if (err) 3907 goto out_mdios; 3908 3909 /* Have to be called without holding the register lock, since 3910 * they take the devlink lock, and we later take the locks in 3911 * the reverse order when getting/setting parameters or 3912 * resource occupancy. 3913 */ 3914 err = mv88e6xxx_setup_devlink_resources(ds); 3915 if (err) 3916 goto out_mdios; 3917 3918 err = mv88e6xxx_setup_devlink_params(ds); 3919 if (err) 3920 goto out_resources; 3921 3922 err = mv88e6xxx_setup_devlink_regions_global(ds); 3923 if (err) 3924 goto out_params; 3925 3926 return 0; 3927 3928 out_params: 3929 mv88e6xxx_teardown_devlink_params(ds); 3930 out_resources: 3931 dsa_devlink_resources_unregister(ds); 3932 out_mdios: 3933 mv88e6xxx_mdios_unregister(chip); 3934 3935 return err; 3936 } 3937 3938 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3939 { 3940 struct mv88e6xxx_chip *chip = ds->priv; 3941 int err; 3942 3943 if (chip->info->ops->pcs_ops && 3944 chip->info->ops->pcs_ops->pcs_init) { 3945 err = chip->info->ops->pcs_ops->pcs_init(chip, port); 3946 if (err) 3947 return err; 3948 } 3949 3950 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3951 } 3952 3953 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3954 { 3955 struct mv88e6xxx_chip *chip = ds->priv; 3956 3957 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3958 3959 if (chip->info->ops->pcs_ops && 3960 chip->info->ops->pcs_ops->pcs_teardown) 3961 chip->info->ops->pcs_ops->pcs_teardown(chip, port); 3962 } 3963 3964 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3965 { 3966 struct mv88e6xxx_chip *chip = ds->priv; 3967 3968 return chip->eeprom_len; 3969 } 3970 3971 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3972 struct ethtool_eeprom *eeprom, u8 *data) 3973 { 3974 struct mv88e6xxx_chip *chip = ds->priv; 3975 int err; 3976 3977 if (!chip->info->ops->get_eeprom) 3978 return -EOPNOTSUPP; 3979 3980 mv88e6xxx_reg_lock(chip); 3981 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3982 mv88e6xxx_reg_unlock(chip); 3983 3984 if (err) 3985 return err; 3986 3987 eeprom->magic = 0xc3ec4951; 3988 3989 return 0; 3990 } 3991 3992 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3993 struct ethtool_eeprom *eeprom, u8 *data) 3994 { 3995 struct mv88e6xxx_chip *chip = ds->priv; 3996 int err; 3997 3998 if (!chip->info->ops->set_eeprom) 3999 return -EOPNOTSUPP; 4000 4001 if (eeprom->magic != 0xc3ec4951) 4002 return -EINVAL; 4003 4004 mv88e6xxx_reg_lock(chip); 4005 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4006 mv88e6xxx_reg_unlock(chip); 4007 4008 return err; 4009 } 4010 4011 static const struct mv88e6xxx_ops mv88e6085_ops = { 4012 /* MV88E6XXX_FAMILY_6097 */ 4013 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4014 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4015 .irl_init_all = mv88e6352_g2_irl_init_all, 4016 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4017 .phy_read = mv88e6185_phy_ppu_read, 4018 .phy_write = mv88e6185_phy_ppu_write, 4019 .port_set_link = mv88e6xxx_port_set_link, 4020 .port_sync_link = mv88e6xxx_port_sync_link, 4021 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4022 .port_tag_remap = mv88e6095_port_tag_remap, 4023 .port_set_policy = mv88e6352_port_set_policy, 4024 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4025 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4026 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4027 .port_set_ether_type = mv88e6351_port_set_ether_type, 4028 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4029 .port_pause_limit = mv88e6097_port_pause_limit, 4030 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4031 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4032 .port_get_cmode = mv88e6185_port_get_cmode, 4033 .port_setup_message_port = mv88e6xxx_setup_message_port, 4034 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4035 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4036 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4037 .stats_get_strings = mv88e6095_stats_get_strings, 4038 .stats_get_stats = mv88e6095_stats_get_stats, 4039 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4040 .set_egress_port = mv88e6095_g1_set_egress_port, 4041 .watchdog_ops = &mv88e6097_watchdog_ops, 4042 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4043 .pot_clear = mv88e6xxx_g2_pot_clear, 4044 .ppu_enable = mv88e6185_g1_ppu_enable, 4045 .ppu_disable = mv88e6185_g1_ppu_disable, 4046 .reset = mv88e6185_g1_reset, 4047 .rmu_disable = mv88e6085_g1_rmu_disable, 4048 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4049 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4050 .stu_getnext = mv88e6352_g1_stu_getnext, 4051 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4052 .phylink_get_caps = mv88e6185_phylink_get_caps, 4053 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4054 }; 4055 4056 static const struct mv88e6xxx_ops mv88e6095_ops = { 4057 /* MV88E6XXX_FAMILY_6095 */ 4058 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4059 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4060 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4061 .phy_read = mv88e6185_phy_ppu_read, 4062 .phy_write = mv88e6185_phy_ppu_write, 4063 .port_set_link = mv88e6xxx_port_set_link, 4064 .port_sync_link = mv88e6185_port_sync_link, 4065 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4066 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4067 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4068 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4069 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4070 .port_get_cmode = mv88e6185_port_get_cmode, 4071 .port_setup_message_port = mv88e6xxx_setup_message_port, 4072 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4073 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4074 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4075 .stats_get_strings = mv88e6095_stats_get_strings, 4076 .stats_get_stats = mv88e6095_stats_get_stats, 4077 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4078 .ppu_enable = mv88e6185_g1_ppu_enable, 4079 .ppu_disable = mv88e6185_g1_ppu_disable, 4080 .reset = mv88e6185_g1_reset, 4081 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4082 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4083 .phylink_get_caps = mv88e6095_phylink_get_caps, 4084 .pcs_ops = &mv88e6185_pcs_ops, 4085 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4086 }; 4087 4088 static const struct mv88e6xxx_ops mv88e6097_ops = { 4089 /* MV88E6XXX_FAMILY_6097 */ 4090 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4091 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4092 .irl_init_all = mv88e6352_g2_irl_init_all, 4093 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4094 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4095 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4096 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4097 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4098 .port_set_link = mv88e6xxx_port_set_link, 4099 .port_sync_link = mv88e6185_port_sync_link, 4100 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4101 .port_tag_remap = mv88e6095_port_tag_remap, 4102 .port_set_policy = mv88e6352_port_set_policy, 4103 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4104 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4105 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4106 .port_set_ether_type = mv88e6351_port_set_ether_type, 4107 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4108 .port_pause_limit = mv88e6097_port_pause_limit, 4109 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4110 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4111 .port_get_cmode = mv88e6185_port_get_cmode, 4112 .port_setup_message_port = mv88e6xxx_setup_message_port, 4113 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4114 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4115 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4116 .stats_get_strings = mv88e6095_stats_get_strings, 4117 .stats_get_stats = mv88e6095_stats_get_stats, 4118 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4119 .set_egress_port = mv88e6095_g1_set_egress_port, 4120 .watchdog_ops = &mv88e6097_watchdog_ops, 4121 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4122 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4123 .pot_clear = mv88e6xxx_g2_pot_clear, 4124 .reset = mv88e6352_g1_reset, 4125 .rmu_disable = mv88e6085_g1_rmu_disable, 4126 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4127 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4128 .phylink_get_caps = mv88e6095_phylink_get_caps, 4129 .pcs_ops = &mv88e6185_pcs_ops, 4130 .stu_getnext = mv88e6352_g1_stu_getnext, 4131 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4132 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4133 }; 4134 4135 static const struct mv88e6xxx_ops mv88e6123_ops = { 4136 /* MV88E6XXX_FAMILY_6165 */ 4137 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4138 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4139 .irl_init_all = mv88e6352_g2_irl_init_all, 4140 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4141 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4142 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4143 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4144 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4145 .port_set_link = mv88e6xxx_port_set_link, 4146 .port_sync_link = mv88e6xxx_port_sync_link, 4147 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4148 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4149 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4150 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4151 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4152 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4153 .port_get_cmode = mv88e6185_port_get_cmode, 4154 .port_setup_message_port = mv88e6xxx_setup_message_port, 4155 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4156 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4157 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4158 .stats_get_strings = mv88e6095_stats_get_strings, 4159 .stats_get_stats = mv88e6095_stats_get_stats, 4160 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4161 .set_egress_port = mv88e6095_g1_set_egress_port, 4162 .watchdog_ops = &mv88e6097_watchdog_ops, 4163 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4164 .pot_clear = mv88e6xxx_g2_pot_clear, 4165 .reset = mv88e6352_g1_reset, 4166 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4167 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4168 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4169 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4170 .stu_getnext = mv88e6352_g1_stu_getnext, 4171 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4172 .phylink_get_caps = mv88e6185_phylink_get_caps, 4173 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4174 }; 4175 4176 static const struct mv88e6xxx_ops mv88e6131_ops = { 4177 /* MV88E6XXX_FAMILY_6185 */ 4178 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4179 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4180 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4181 .phy_read = mv88e6185_phy_ppu_read, 4182 .phy_write = mv88e6185_phy_ppu_write, 4183 .port_set_link = mv88e6xxx_port_set_link, 4184 .port_sync_link = mv88e6xxx_port_sync_link, 4185 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4186 .port_tag_remap = mv88e6095_port_tag_remap, 4187 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4188 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4189 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4190 .port_set_ether_type = mv88e6351_port_set_ether_type, 4191 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4192 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4193 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4194 .port_pause_limit = mv88e6097_port_pause_limit, 4195 .port_set_pause = mv88e6185_port_set_pause, 4196 .port_get_cmode = mv88e6185_port_get_cmode, 4197 .port_setup_message_port = mv88e6xxx_setup_message_port, 4198 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4199 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4200 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4201 .stats_get_strings = mv88e6095_stats_get_strings, 4202 .stats_get_stats = mv88e6095_stats_get_stats, 4203 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4204 .set_egress_port = mv88e6095_g1_set_egress_port, 4205 .watchdog_ops = &mv88e6097_watchdog_ops, 4206 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4207 .ppu_enable = mv88e6185_g1_ppu_enable, 4208 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4209 .ppu_disable = mv88e6185_g1_ppu_disable, 4210 .reset = mv88e6185_g1_reset, 4211 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4212 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4213 .phylink_get_caps = mv88e6185_phylink_get_caps, 4214 }; 4215 4216 static const struct mv88e6xxx_ops mv88e6141_ops = { 4217 /* MV88E6XXX_FAMILY_6341 */ 4218 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4219 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4220 .irl_init_all = mv88e6352_g2_irl_init_all, 4221 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4222 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4223 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4224 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4225 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4226 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4227 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4228 .port_set_link = mv88e6xxx_port_set_link, 4229 .port_sync_link = mv88e6xxx_port_sync_link, 4230 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4231 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4232 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4233 .port_tag_remap = mv88e6095_port_tag_remap, 4234 .port_set_policy = mv88e6352_port_set_policy, 4235 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4236 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4237 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4238 .port_set_ether_type = mv88e6351_port_set_ether_type, 4239 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4240 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4241 .port_pause_limit = mv88e6097_port_pause_limit, 4242 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4243 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4244 .port_get_cmode = mv88e6352_port_get_cmode, 4245 .port_set_cmode = mv88e6341_port_set_cmode, 4246 .port_setup_message_port = mv88e6xxx_setup_message_port, 4247 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4248 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4249 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4250 .stats_get_strings = mv88e6320_stats_get_strings, 4251 .stats_get_stats = mv88e6390_stats_get_stats, 4252 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4253 .set_egress_port = mv88e6390_g1_set_egress_port, 4254 .watchdog_ops = &mv88e6390_watchdog_ops, 4255 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4256 .pot_clear = mv88e6xxx_g2_pot_clear, 4257 .reset = mv88e6352_g1_reset, 4258 .rmu_disable = mv88e6390_g1_rmu_disable, 4259 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4260 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4261 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4262 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4263 .stu_getnext = mv88e6352_g1_stu_getnext, 4264 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4265 .serdes_get_lane = mv88e6341_serdes_get_lane, 4266 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4267 .gpio_ops = &mv88e6352_gpio_ops, 4268 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4269 .serdes_get_strings = mv88e6390_serdes_get_strings, 4270 .serdes_get_stats = mv88e6390_serdes_get_stats, 4271 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4272 .serdes_get_regs = mv88e6390_serdes_get_regs, 4273 .phylink_get_caps = mv88e6341_phylink_get_caps, 4274 .pcs_ops = &mv88e6390_pcs_ops, 4275 }; 4276 4277 static const struct mv88e6xxx_ops mv88e6161_ops = { 4278 /* MV88E6XXX_FAMILY_6165 */ 4279 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4280 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4281 .irl_init_all = mv88e6352_g2_irl_init_all, 4282 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4283 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4284 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4285 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4286 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4287 .port_set_link = mv88e6xxx_port_set_link, 4288 .port_sync_link = mv88e6xxx_port_sync_link, 4289 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4290 .port_tag_remap = mv88e6095_port_tag_remap, 4291 .port_set_policy = mv88e6352_port_set_policy, 4292 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4293 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4294 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4295 .port_set_ether_type = mv88e6351_port_set_ether_type, 4296 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4297 .port_pause_limit = mv88e6097_port_pause_limit, 4298 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4299 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4300 .port_get_cmode = mv88e6185_port_get_cmode, 4301 .port_setup_message_port = mv88e6xxx_setup_message_port, 4302 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4303 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4304 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4305 .stats_get_strings = mv88e6095_stats_get_strings, 4306 .stats_get_stats = mv88e6095_stats_get_stats, 4307 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4308 .set_egress_port = mv88e6095_g1_set_egress_port, 4309 .watchdog_ops = &mv88e6097_watchdog_ops, 4310 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4311 .pot_clear = mv88e6xxx_g2_pot_clear, 4312 .reset = mv88e6352_g1_reset, 4313 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4314 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4315 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4316 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4317 .stu_getnext = mv88e6352_g1_stu_getnext, 4318 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4319 .avb_ops = &mv88e6165_avb_ops, 4320 .ptp_ops = &mv88e6165_ptp_ops, 4321 .phylink_get_caps = mv88e6185_phylink_get_caps, 4322 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4323 }; 4324 4325 static const struct mv88e6xxx_ops mv88e6165_ops = { 4326 /* MV88E6XXX_FAMILY_6165 */ 4327 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4328 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4329 .irl_init_all = mv88e6352_g2_irl_init_all, 4330 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4331 .phy_read = mv88e6165_phy_read, 4332 .phy_write = mv88e6165_phy_write, 4333 .port_set_link = mv88e6xxx_port_set_link, 4334 .port_sync_link = mv88e6xxx_port_sync_link, 4335 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4336 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4337 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4338 .port_get_cmode = mv88e6185_port_get_cmode, 4339 .port_setup_message_port = mv88e6xxx_setup_message_port, 4340 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4341 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4342 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4343 .stats_get_strings = mv88e6095_stats_get_strings, 4344 .stats_get_stats = mv88e6095_stats_get_stats, 4345 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4346 .set_egress_port = mv88e6095_g1_set_egress_port, 4347 .watchdog_ops = &mv88e6097_watchdog_ops, 4348 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4349 .pot_clear = mv88e6xxx_g2_pot_clear, 4350 .reset = mv88e6352_g1_reset, 4351 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4352 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4353 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4354 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4355 .stu_getnext = mv88e6352_g1_stu_getnext, 4356 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4357 .avb_ops = &mv88e6165_avb_ops, 4358 .ptp_ops = &mv88e6165_ptp_ops, 4359 .phylink_get_caps = mv88e6185_phylink_get_caps, 4360 }; 4361 4362 static const struct mv88e6xxx_ops mv88e6171_ops = { 4363 /* MV88E6XXX_FAMILY_6351 */ 4364 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4365 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4366 .irl_init_all = mv88e6352_g2_irl_init_all, 4367 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4368 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4369 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4370 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4371 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4372 .port_set_link = mv88e6xxx_port_set_link, 4373 .port_sync_link = mv88e6xxx_port_sync_link, 4374 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4375 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4376 .port_tag_remap = mv88e6095_port_tag_remap, 4377 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4378 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4379 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4380 .port_set_ether_type = mv88e6351_port_set_ether_type, 4381 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4382 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4383 .port_pause_limit = mv88e6097_port_pause_limit, 4384 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4385 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4386 .port_get_cmode = mv88e6352_port_get_cmode, 4387 .port_setup_message_port = mv88e6xxx_setup_message_port, 4388 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4389 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4390 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4391 .stats_get_strings = mv88e6095_stats_get_strings, 4392 .stats_get_stats = mv88e6095_stats_get_stats, 4393 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4394 .set_egress_port = mv88e6095_g1_set_egress_port, 4395 .watchdog_ops = &mv88e6097_watchdog_ops, 4396 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4397 .pot_clear = mv88e6xxx_g2_pot_clear, 4398 .reset = mv88e6352_g1_reset, 4399 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4400 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4401 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4402 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4403 .stu_getnext = mv88e6352_g1_stu_getnext, 4404 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4405 .phylink_get_caps = mv88e6351_phylink_get_caps, 4406 }; 4407 4408 static const struct mv88e6xxx_ops mv88e6172_ops = { 4409 /* MV88E6XXX_FAMILY_6352 */ 4410 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4411 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4412 .irl_init_all = mv88e6352_g2_irl_init_all, 4413 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4414 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4415 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4416 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4417 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4418 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4419 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4420 .port_set_link = mv88e6xxx_port_set_link, 4421 .port_sync_link = mv88e6xxx_port_sync_link, 4422 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4423 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4424 .port_tag_remap = mv88e6095_port_tag_remap, 4425 .port_set_policy = mv88e6352_port_set_policy, 4426 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4427 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4428 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4429 .port_set_ether_type = mv88e6351_port_set_ether_type, 4430 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4431 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4432 .port_pause_limit = mv88e6097_port_pause_limit, 4433 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4434 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4435 .port_get_cmode = mv88e6352_port_get_cmode, 4436 .port_setup_message_port = mv88e6xxx_setup_message_port, 4437 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4438 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4439 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4440 .stats_get_strings = mv88e6095_stats_get_strings, 4441 .stats_get_stats = mv88e6095_stats_get_stats, 4442 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4443 .set_egress_port = mv88e6095_g1_set_egress_port, 4444 .watchdog_ops = &mv88e6097_watchdog_ops, 4445 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4446 .pot_clear = mv88e6xxx_g2_pot_clear, 4447 .reset = mv88e6352_g1_reset, 4448 .rmu_disable = mv88e6352_g1_rmu_disable, 4449 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4450 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4451 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4452 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4453 .stu_getnext = mv88e6352_g1_stu_getnext, 4454 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4455 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4456 .serdes_get_regs = mv88e6352_serdes_get_regs, 4457 .gpio_ops = &mv88e6352_gpio_ops, 4458 .phylink_get_caps = mv88e6352_phylink_get_caps, 4459 .pcs_ops = &mv88e6352_pcs_ops, 4460 }; 4461 4462 static const struct mv88e6xxx_ops mv88e6175_ops = { 4463 /* MV88E6XXX_FAMILY_6351 */ 4464 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4465 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4466 .irl_init_all = mv88e6352_g2_irl_init_all, 4467 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4468 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4469 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4470 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4471 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4472 .port_set_link = mv88e6xxx_port_set_link, 4473 .port_sync_link = mv88e6xxx_port_sync_link, 4474 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4475 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4476 .port_tag_remap = mv88e6095_port_tag_remap, 4477 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4478 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4479 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4480 .port_set_ether_type = mv88e6351_port_set_ether_type, 4481 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4482 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4483 .port_pause_limit = mv88e6097_port_pause_limit, 4484 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4485 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4486 .port_get_cmode = mv88e6352_port_get_cmode, 4487 .port_setup_message_port = mv88e6xxx_setup_message_port, 4488 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4489 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4490 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4491 .stats_get_strings = mv88e6095_stats_get_strings, 4492 .stats_get_stats = mv88e6095_stats_get_stats, 4493 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4494 .set_egress_port = mv88e6095_g1_set_egress_port, 4495 .watchdog_ops = &mv88e6097_watchdog_ops, 4496 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4497 .pot_clear = mv88e6xxx_g2_pot_clear, 4498 .reset = mv88e6352_g1_reset, 4499 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4500 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4501 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4502 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4503 .stu_getnext = mv88e6352_g1_stu_getnext, 4504 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4505 .phylink_get_caps = mv88e6351_phylink_get_caps, 4506 }; 4507 4508 static const struct mv88e6xxx_ops mv88e6176_ops = { 4509 /* MV88E6XXX_FAMILY_6352 */ 4510 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4511 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4512 .irl_init_all = mv88e6352_g2_irl_init_all, 4513 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4514 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4515 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4516 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4517 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4518 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4519 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4520 .port_set_link = mv88e6xxx_port_set_link, 4521 .port_sync_link = mv88e6xxx_port_sync_link, 4522 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4523 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4524 .port_tag_remap = mv88e6095_port_tag_remap, 4525 .port_set_policy = mv88e6352_port_set_policy, 4526 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4527 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4528 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4529 .port_set_ether_type = mv88e6351_port_set_ether_type, 4530 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4531 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4532 .port_pause_limit = mv88e6097_port_pause_limit, 4533 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4534 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4535 .port_get_cmode = mv88e6352_port_get_cmode, 4536 .port_setup_message_port = mv88e6xxx_setup_message_port, 4537 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4538 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4539 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4540 .stats_get_strings = mv88e6095_stats_get_strings, 4541 .stats_get_stats = mv88e6095_stats_get_stats, 4542 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4543 .set_egress_port = mv88e6095_g1_set_egress_port, 4544 .watchdog_ops = &mv88e6097_watchdog_ops, 4545 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4546 .pot_clear = mv88e6xxx_g2_pot_clear, 4547 .reset = mv88e6352_g1_reset, 4548 .rmu_disable = mv88e6352_g1_rmu_disable, 4549 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4550 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4551 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4552 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4553 .stu_getnext = mv88e6352_g1_stu_getnext, 4554 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4555 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4556 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4557 .serdes_get_regs = mv88e6352_serdes_get_regs, 4558 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4559 .gpio_ops = &mv88e6352_gpio_ops, 4560 .phylink_get_caps = mv88e6352_phylink_get_caps, 4561 .pcs_ops = &mv88e6352_pcs_ops, 4562 }; 4563 4564 static const struct mv88e6xxx_ops mv88e6185_ops = { 4565 /* MV88E6XXX_FAMILY_6185 */ 4566 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4567 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4568 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4569 .phy_read = mv88e6185_phy_ppu_read, 4570 .phy_write = mv88e6185_phy_ppu_write, 4571 .port_set_link = mv88e6xxx_port_set_link, 4572 .port_sync_link = mv88e6185_port_sync_link, 4573 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4574 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4575 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4576 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4577 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4578 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4579 .port_set_pause = mv88e6185_port_set_pause, 4580 .port_get_cmode = mv88e6185_port_get_cmode, 4581 .port_setup_message_port = mv88e6xxx_setup_message_port, 4582 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4583 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4584 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4585 .stats_get_strings = mv88e6095_stats_get_strings, 4586 .stats_get_stats = mv88e6095_stats_get_stats, 4587 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4588 .set_egress_port = mv88e6095_g1_set_egress_port, 4589 .watchdog_ops = &mv88e6097_watchdog_ops, 4590 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4591 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4592 .ppu_enable = mv88e6185_g1_ppu_enable, 4593 .ppu_disable = mv88e6185_g1_ppu_disable, 4594 .reset = mv88e6185_g1_reset, 4595 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4596 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4597 .phylink_get_caps = mv88e6185_phylink_get_caps, 4598 .pcs_ops = &mv88e6185_pcs_ops, 4599 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4600 }; 4601 4602 static const struct mv88e6xxx_ops mv88e6190_ops = { 4603 /* MV88E6XXX_FAMILY_6390 */ 4604 .setup_errata = mv88e6390_setup_errata, 4605 .irl_init_all = mv88e6390_g2_irl_init_all, 4606 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4607 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4608 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4609 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4610 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4611 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4612 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4613 .port_set_link = mv88e6xxx_port_set_link, 4614 .port_sync_link = mv88e6xxx_port_sync_link, 4615 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4616 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4617 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4618 .port_tag_remap = mv88e6390_port_tag_remap, 4619 .port_set_policy = mv88e6352_port_set_policy, 4620 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4621 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4622 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4623 .port_set_ether_type = mv88e6351_port_set_ether_type, 4624 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4625 .port_pause_limit = mv88e6390_port_pause_limit, 4626 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4627 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4628 .port_get_cmode = mv88e6352_port_get_cmode, 4629 .port_set_cmode = mv88e6390_port_set_cmode, 4630 .port_setup_message_port = mv88e6xxx_setup_message_port, 4631 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4632 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4633 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4634 .stats_get_strings = mv88e6320_stats_get_strings, 4635 .stats_get_stats = mv88e6390_stats_get_stats, 4636 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4637 .set_egress_port = mv88e6390_g1_set_egress_port, 4638 .watchdog_ops = &mv88e6390_watchdog_ops, 4639 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4640 .pot_clear = mv88e6xxx_g2_pot_clear, 4641 .reset = mv88e6352_g1_reset, 4642 .rmu_disable = mv88e6390_g1_rmu_disable, 4643 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4644 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4645 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4646 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4647 .stu_getnext = mv88e6390_g1_stu_getnext, 4648 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4649 .serdes_get_lane = mv88e6390_serdes_get_lane, 4650 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4651 .serdes_get_strings = mv88e6390_serdes_get_strings, 4652 .serdes_get_stats = mv88e6390_serdes_get_stats, 4653 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4654 .serdes_get_regs = mv88e6390_serdes_get_regs, 4655 .gpio_ops = &mv88e6352_gpio_ops, 4656 .phylink_get_caps = mv88e6390_phylink_get_caps, 4657 .pcs_ops = &mv88e6390_pcs_ops, 4658 }; 4659 4660 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4661 /* MV88E6XXX_FAMILY_6390 */ 4662 .setup_errata = mv88e6390_setup_errata, 4663 .irl_init_all = mv88e6390_g2_irl_init_all, 4664 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4665 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4666 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4667 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4668 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4669 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4670 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4671 .port_set_link = mv88e6xxx_port_set_link, 4672 .port_sync_link = mv88e6xxx_port_sync_link, 4673 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4674 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4675 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4676 .port_tag_remap = mv88e6390_port_tag_remap, 4677 .port_set_policy = mv88e6352_port_set_policy, 4678 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4679 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4680 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4681 .port_set_ether_type = mv88e6351_port_set_ether_type, 4682 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4683 .port_pause_limit = mv88e6390_port_pause_limit, 4684 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4685 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4686 .port_get_cmode = mv88e6352_port_get_cmode, 4687 .port_set_cmode = mv88e6390x_port_set_cmode, 4688 .port_setup_message_port = mv88e6xxx_setup_message_port, 4689 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4690 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4691 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4692 .stats_get_strings = mv88e6320_stats_get_strings, 4693 .stats_get_stats = mv88e6390_stats_get_stats, 4694 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4695 .set_egress_port = mv88e6390_g1_set_egress_port, 4696 .watchdog_ops = &mv88e6390_watchdog_ops, 4697 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4698 .pot_clear = mv88e6xxx_g2_pot_clear, 4699 .reset = mv88e6352_g1_reset, 4700 .rmu_disable = mv88e6390_g1_rmu_disable, 4701 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4702 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4703 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4704 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4705 .stu_getnext = mv88e6390_g1_stu_getnext, 4706 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4707 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4708 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4709 .serdes_get_strings = mv88e6390_serdes_get_strings, 4710 .serdes_get_stats = mv88e6390_serdes_get_stats, 4711 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4712 .serdes_get_regs = mv88e6390_serdes_get_regs, 4713 .gpio_ops = &mv88e6352_gpio_ops, 4714 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4715 .pcs_ops = &mv88e6390_pcs_ops, 4716 }; 4717 4718 static const struct mv88e6xxx_ops mv88e6191_ops = { 4719 /* MV88E6XXX_FAMILY_6390 */ 4720 .setup_errata = mv88e6390_setup_errata, 4721 .irl_init_all = mv88e6390_g2_irl_init_all, 4722 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4723 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4724 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4725 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4726 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4727 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4728 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4729 .port_set_link = mv88e6xxx_port_set_link, 4730 .port_sync_link = mv88e6xxx_port_sync_link, 4731 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4732 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4733 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4734 .port_tag_remap = mv88e6390_port_tag_remap, 4735 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4736 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4737 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4738 .port_set_ether_type = mv88e6351_port_set_ether_type, 4739 .port_pause_limit = mv88e6390_port_pause_limit, 4740 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4741 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4742 .port_get_cmode = mv88e6352_port_get_cmode, 4743 .port_set_cmode = mv88e6390_port_set_cmode, 4744 .port_setup_message_port = mv88e6xxx_setup_message_port, 4745 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4746 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4747 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4748 .stats_get_strings = mv88e6320_stats_get_strings, 4749 .stats_get_stats = mv88e6390_stats_get_stats, 4750 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4751 .set_egress_port = mv88e6390_g1_set_egress_port, 4752 .watchdog_ops = &mv88e6390_watchdog_ops, 4753 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4754 .pot_clear = mv88e6xxx_g2_pot_clear, 4755 .reset = mv88e6352_g1_reset, 4756 .rmu_disable = mv88e6390_g1_rmu_disable, 4757 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4758 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4759 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4760 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4761 .stu_getnext = mv88e6390_g1_stu_getnext, 4762 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4763 .serdes_get_lane = mv88e6390_serdes_get_lane, 4764 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4765 .serdes_get_strings = mv88e6390_serdes_get_strings, 4766 .serdes_get_stats = mv88e6390_serdes_get_stats, 4767 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4768 .serdes_get_regs = mv88e6390_serdes_get_regs, 4769 .avb_ops = &mv88e6390_avb_ops, 4770 .ptp_ops = &mv88e6352_ptp_ops, 4771 .phylink_get_caps = mv88e6390_phylink_get_caps, 4772 .pcs_ops = &mv88e6390_pcs_ops, 4773 }; 4774 4775 static const struct mv88e6xxx_ops mv88e6240_ops = { 4776 /* MV88E6XXX_FAMILY_6352 */ 4777 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4778 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4779 .irl_init_all = mv88e6352_g2_irl_init_all, 4780 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4781 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4782 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4783 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4784 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4785 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4786 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4787 .port_set_link = mv88e6xxx_port_set_link, 4788 .port_sync_link = mv88e6xxx_port_sync_link, 4789 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4790 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4791 .port_tag_remap = mv88e6095_port_tag_remap, 4792 .port_set_policy = mv88e6352_port_set_policy, 4793 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4794 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4795 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4796 .port_set_ether_type = mv88e6351_port_set_ether_type, 4797 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4798 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4799 .port_pause_limit = mv88e6097_port_pause_limit, 4800 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4801 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4802 .port_get_cmode = mv88e6352_port_get_cmode, 4803 .port_setup_message_port = mv88e6xxx_setup_message_port, 4804 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4805 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4806 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4807 .stats_get_strings = mv88e6095_stats_get_strings, 4808 .stats_get_stats = mv88e6095_stats_get_stats, 4809 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4810 .set_egress_port = mv88e6095_g1_set_egress_port, 4811 .watchdog_ops = &mv88e6097_watchdog_ops, 4812 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4813 .pot_clear = mv88e6xxx_g2_pot_clear, 4814 .reset = mv88e6352_g1_reset, 4815 .rmu_disable = mv88e6352_g1_rmu_disable, 4816 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4817 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4818 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4819 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4820 .stu_getnext = mv88e6352_g1_stu_getnext, 4821 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4822 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4823 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4824 .serdes_get_regs = mv88e6352_serdes_get_regs, 4825 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4826 .gpio_ops = &mv88e6352_gpio_ops, 4827 .avb_ops = &mv88e6352_avb_ops, 4828 .ptp_ops = &mv88e6352_ptp_ops, 4829 .phylink_get_caps = mv88e6352_phylink_get_caps, 4830 .pcs_ops = &mv88e6352_pcs_ops, 4831 }; 4832 4833 static const struct mv88e6xxx_ops mv88e6250_ops = { 4834 /* MV88E6XXX_FAMILY_6250 */ 4835 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4836 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4837 .irl_init_all = mv88e6352_g2_irl_init_all, 4838 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4839 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4840 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4841 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4842 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4843 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4844 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4845 .port_set_link = mv88e6xxx_port_set_link, 4846 .port_sync_link = mv88e6xxx_port_sync_link, 4847 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4848 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4849 .port_tag_remap = mv88e6095_port_tag_remap, 4850 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4851 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4852 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4853 .port_set_ether_type = mv88e6351_port_set_ether_type, 4854 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4855 .port_pause_limit = mv88e6097_port_pause_limit, 4856 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4857 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4858 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4859 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4860 .stats_get_strings = mv88e6250_stats_get_strings, 4861 .stats_get_stats = mv88e6250_stats_get_stats, 4862 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4863 .set_egress_port = mv88e6095_g1_set_egress_port, 4864 .watchdog_ops = &mv88e6250_watchdog_ops, 4865 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4866 .pot_clear = mv88e6xxx_g2_pot_clear, 4867 .reset = mv88e6250_g1_reset, 4868 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4869 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4870 .avb_ops = &mv88e6352_avb_ops, 4871 .ptp_ops = &mv88e6250_ptp_ops, 4872 .phylink_get_caps = mv88e6250_phylink_get_caps, 4873 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4874 }; 4875 4876 static const struct mv88e6xxx_ops mv88e6290_ops = { 4877 /* MV88E6XXX_FAMILY_6390 */ 4878 .setup_errata = mv88e6390_setup_errata, 4879 .irl_init_all = mv88e6390_g2_irl_init_all, 4880 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4881 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4882 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4883 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4884 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4885 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4886 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4887 .port_set_link = mv88e6xxx_port_set_link, 4888 .port_sync_link = mv88e6xxx_port_sync_link, 4889 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4890 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4891 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4892 .port_tag_remap = mv88e6390_port_tag_remap, 4893 .port_set_policy = mv88e6352_port_set_policy, 4894 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4895 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4896 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4897 .port_set_ether_type = mv88e6351_port_set_ether_type, 4898 .port_pause_limit = mv88e6390_port_pause_limit, 4899 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4900 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4901 .port_get_cmode = mv88e6352_port_get_cmode, 4902 .port_set_cmode = mv88e6390_port_set_cmode, 4903 .port_setup_message_port = mv88e6xxx_setup_message_port, 4904 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4905 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4906 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4907 .stats_get_strings = mv88e6320_stats_get_strings, 4908 .stats_get_stats = mv88e6390_stats_get_stats, 4909 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4910 .set_egress_port = mv88e6390_g1_set_egress_port, 4911 .watchdog_ops = &mv88e6390_watchdog_ops, 4912 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4913 .pot_clear = mv88e6xxx_g2_pot_clear, 4914 .reset = mv88e6352_g1_reset, 4915 .rmu_disable = mv88e6390_g1_rmu_disable, 4916 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4917 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4918 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4919 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4920 .stu_getnext = mv88e6390_g1_stu_getnext, 4921 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4922 .serdes_get_lane = mv88e6390_serdes_get_lane, 4923 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4924 .serdes_get_strings = mv88e6390_serdes_get_strings, 4925 .serdes_get_stats = mv88e6390_serdes_get_stats, 4926 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4927 .serdes_get_regs = mv88e6390_serdes_get_regs, 4928 .gpio_ops = &mv88e6352_gpio_ops, 4929 .avb_ops = &mv88e6390_avb_ops, 4930 .ptp_ops = &mv88e6390_ptp_ops, 4931 .phylink_get_caps = mv88e6390_phylink_get_caps, 4932 .pcs_ops = &mv88e6390_pcs_ops, 4933 }; 4934 4935 static const struct mv88e6xxx_ops mv88e6320_ops = { 4936 /* MV88E6XXX_FAMILY_6320 */ 4937 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4938 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4939 .irl_init_all = mv88e6352_g2_irl_init_all, 4940 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4941 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4942 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4943 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4944 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4945 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4946 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4947 .port_set_link = mv88e6xxx_port_set_link, 4948 .port_sync_link = mv88e6xxx_port_sync_link, 4949 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 4950 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4951 .port_tag_remap = mv88e6095_port_tag_remap, 4952 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4953 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4954 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4955 .port_set_ether_type = mv88e6351_port_set_ether_type, 4956 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4957 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4958 .port_pause_limit = mv88e6097_port_pause_limit, 4959 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4960 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4961 .port_get_cmode = mv88e6352_port_get_cmode, 4962 .port_setup_message_port = mv88e6xxx_setup_message_port, 4963 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4964 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4965 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4966 .stats_get_strings = mv88e6320_stats_get_strings, 4967 .stats_get_stats = mv88e6320_stats_get_stats, 4968 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4969 .set_egress_port = mv88e6095_g1_set_egress_port, 4970 .watchdog_ops = &mv88e6390_watchdog_ops, 4971 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4972 .pot_clear = mv88e6xxx_g2_pot_clear, 4973 .reset = mv88e6352_g1_reset, 4974 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4975 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4976 .gpio_ops = &mv88e6352_gpio_ops, 4977 .avb_ops = &mv88e6352_avb_ops, 4978 .ptp_ops = &mv88e6352_ptp_ops, 4979 .phylink_get_caps = mv88e6185_phylink_get_caps, 4980 }; 4981 4982 static const struct mv88e6xxx_ops mv88e6321_ops = { 4983 /* MV88E6XXX_FAMILY_6320 */ 4984 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4985 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4986 .irl_init_all = mv88e6352_g2_irl_init_all, 4987 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4988 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4989 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4990 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4991 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4992 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4993 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4994 .port_set_link = mv88e6xxx_port_set_link, 4995 .port_sync_link = mv88e6xxx_port_sync_link, 4996 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 4997 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4998 .port_tag_remap = mv88e6095_port_tag_remap, 4999 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5000 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5001 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5002 .port_set_ether_type = mv88e6351_port_set_ether_type, 5003 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5004 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5005 .port_pause_limit = mv88e6097_port_pause_limit, 5006 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5007 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5008 .port_get_cmode = mv88e6352_port_get_cmode, 5009 .port_setup_message_port = mv88e6xxx_setup_message_port, 5010 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5011 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5012 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5013 .stats_get_strings = mv88e6320_stats_get_strings, 5014 .stats_get_stats = mv88e6320_stats_get_stats, 5015 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5016 .set_egress_port = mv88e6095_g1_set_egress_port, 5017 .watchdog_ops = &mv88e6390_watchdog_ops, 5018 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5019 .reset = mv88e6352_g1_reset, 5020 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5021 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5022 .gpio_ops = &mv88e6352_gpio_ops, 5023 .avb_ops = &mv88e6352_avb_ops, 5024 .ptp_ops = &mv88e6352_ptp_ops, 5025 .phylink_get_caps = mv88e6185_phylink_get_caps, 5026 }; 5027 5028 static const struct mv88e6xxx_ops mv88e6341_ops = { 5029 /* MV88E6XXX_FAMILY_6341 */ 5030 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5031 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5032 .irl_init_all = mv88e6352_g2_irl_init_all, 5033 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5034 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5035 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5036 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5037 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5038 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5039 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5040 .port_set_link = mv88e6xxx_port_set_link, 5041 .port_sync_link = mv88e6xxx_port_sync_link, 5042 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5043 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5044 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5045 .port_tag_remap = mv88e6095_port_tag_remap, 5046 .port_set_policy = mv88e6352_port_set_policy, 5047 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5048 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5049 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5050 .port_set_ether_type = mv88e6351_port_set_ether_type, 5051 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5052 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5053 .port_pause_limit = mv88e6097_port_pause_limit, 5054 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5055 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5056 .port_get_cmode = mv88e6352_port_get_cmode, 5057 .port_set_cmode = mv88e6341_port_set_cmode, 5058 .port_setup_message_port = mv88e6xxx_setup_message_port, 5059 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5060 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5061 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5062 .stats_get_strings = mv88e6320_stats_get_strings, 5063 .stats_get_stats = mv88e6390_stats_get_stats, 5064 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5065 .set_egress_port = mv88e6390_g1_set_egress_port, 5066 .watchdog_ops = &mv88e6390_watchdog_ops, 5067 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5068 .pot_clear = mv88e6xxx_g2_pot_clear, 5069 .reset = mv88e6352_g1_reset, 5070 .rmu_disable = mv88e6390_g1_rmu_disable, 5071 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5072 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5073 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5074 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5075 .stu_getnext = mv88e6352_g1_stu_getnext, 5076 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5077 .serdes_get_lane = mv88e6341_serdes_get_lane, 5078 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5079 .gpio_ops = &mv88e6352_gpio_ops, 5080 .avb_ops = &mv88e6390_avb_ops, 5081 .ptp_ops = &mv88e6352_ptp_ops, 5082 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5083 .serdes_get_strings = mv88e6390_serdes_get_strings, 5084 .serdes_get_stats = mv88e6390_serdes_get_stats, 5085 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5086 .serdes_get_regs = mv88e6390_serdes_get_regs, 5087 .phylink_get_caps = mv88e6341_phylink_get_caps, 5088 .pcs_ops = &mv88e6390_pcs_ops, 5089 }; 5090 5091 static const struct mv88e6xxx_ops mv88e6350_ops = { 5092 /* MV88E6XXX_FAMILY_6351 */ 5093 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5094 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5095 .irl_init_all = mv88e6352_g2_irl_init_all, 5096 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5097 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5098 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5099 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5100 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5101 .port_set_link = mv88e6xxx_port_set_link, 5102 .port_sync_link = mv88e6xxx_port_sync_link, 5103 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5104 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5105 .port_tag_remap = mv88e6095_port_tag_remap, 5106 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5107 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5108 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5109 .port_set_ether_type = mv88e6351_port_set_ether_type, 5110 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5111 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5112 .port_pause_limit = mv88e6097_port_pause_limit, 5113 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5114 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5115 .port_get_cmode = mv88e6352_port_get_cmode, 5116 .port_setup_message_port = mv88e6xxx_setup_message_port, 5117 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5118 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5119 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5120 .stats_get_strings = mv88e6095_stats_get_strings, 5121 .stats_get_stats = mv88e6095_stats_get_stats, 5122 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5123 .set_egress_port = mv88e6095_g1_set_egress_port, 5124 .watchdog_ops = &mv88e6097_watchdog_ops, 5125 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5126 .pot_clear = mv88e6xxx_g2_pot_clear, 5127 .reset = mv88e6352_g1_reset, 5128 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5129 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5130 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5131 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5132 .stu_getnext = mv88e6352_g1_stu_getnext, 5133 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5134 .phylink_get_caps = mv88e6351_phylink_get_caps, 5135 }; 5136 5137 static const struct mv88e6xxx_ops mv88e6351_ops = { 5138 /* MV88E6XXX_FAMILY_6351 */ 5139 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5140 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5141 .irl_init_all = mv88e6352_g2_irl_init_all, 5142 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5143 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5144 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5145 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5146 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5147 .port_set_link = mv88e6xxx_port_set_link, 5148 .port_sync_link = mv88e6xxx_port_sync_link, 5149 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5150 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5151 .port_tag_remap = mv88e6095_port_tag_remap, 5152 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5153 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5154 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5155 .port_set_ether_type = mv88e6351_port_set_ether_type, 5156 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5157 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5158 .port_pause_limit = mv88e6097_port_pause_limit, 5159 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5160 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5161 .port_get_cmode = mv88e6352_port_get_cmode, 5162 .port_setup_message_port = mv88e6xxx_setup_message_port, 5163 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5164 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5165 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5166 .stats_get_strings = mv88e6095_stats_get_strings, 5167 .stats_get_stats = mv88e6095_stats_get_stats, 5168 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5169 .set_egress_port = mv88e6095_g1_set_egress_port, 5170 .watchdog_ops = &mv88e6097_watchdog_ops, 5171 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5172 .pot_clear = mv88e6xxx_g2_pot_clear, 5173 .reset = mv88e6352_g1_reset, 5174 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5175 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5176 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5177 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5178 .stu_getnext = mv88e6352_g1_stu_getnext, 5179 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5180 .avb_ops = &mv88e6352_avb_ops, 5181 .ptp_ops = &mv88e6352_ptp_ops, 5182 .phylink_get_caps = mv88e6351_phylink_get_caps, 5183 }; 5184 5185 static const struct mv88e6xxx_ops mv88e6352_ops = { 5186 /* MV88E6XXX_FAMILY_6352 */ 5187 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5188 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5189 .irl_init_all = mv88e6352_g2_irl_init_all, 5190 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5191 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5192 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5193 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5194 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5195 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5196 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5197 .port_set_link = mv88e6xxx_port_set_link, 5198 .port_sync_link = mv88e6xxx_port_sync_link, 5199 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5200 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5201 .port_tag_remap = mv88e6095_port_tag_remap, 5202 .port_set_policy = mv88e6352_port_set_policy, 5203 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5204 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5205 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5206 .port_set_ether_type = mv88e6351_port_set_ether_type, 5207 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5208 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5209 .port_pause_limit = mv88e6097_port_pause_limit, 5210 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5211 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5212 .port_get_cmode = mv88e6352_port_get_cmode, 5213 .port_setup_message_port = mv88e6xxx_setup_message_port, 5214 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5215 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5216 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5217 .stats_get_strings = mv88e6095_stats_get_strings, 5218 .stats_get_stats = mv88e6095_stats_get_stats, 5219 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5220 .set_egress_port = mv88e6095_g1_set_egress_port, 5221 .watchdog_ops = &mv88e6097_watchdog_ops, 5222 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5223 .pot_clear = mv88e6xxx_g2_pot_clear, 5224 .reset = mv88e6352_g1_reset, 5225 .rmu_disable = mv88e6352_g1_rmu_disable, 5226 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5227 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5228 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5229 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5230 .stu_getnext = mv88e6352_g1_stu_getnext, 5231 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5232 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5233 .gpio_ops = &mv88e6352_gpio_ops, 5234 .avb_ops = &mv88e6352_avb_ops, 5235 .ptp_ops = &mv88e6352_ptp_ops, 5236 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5237 .serdes_get_strings = mv88e6352_serdes_get_strings, 5238 .serdes_get_stats = mv88e6352_serdes_get_stats, 5239 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5240 .serdes_get_regs = mv88e6352_serdes_get_regs, 5241 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5242 .phylink_get_caps = mv88e6352_phylink_get_caps, 5243 .pcs_ops = &mv88e6352_pcs_ops, 5244 }; 5245 5246 static const struct mv88e6xxx_ops mv88e6390_ops = { 5247 /* MV88E6XXX_FAMILY_6390 */ 5248 .setup_errata = mv88e6390_setup_errata, 5249 .irl_init_all = mv88e6390_g2_irl_init_all, 5250 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5251 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5252 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5253 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5254 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5255 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5256 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5257 .port_set_link = mv88e6xxx_port_set_link, 5258 .port_sync_link = mv88e6xxx_port_sync_link, 5259 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5260 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5261 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5262 .port_tag_remap = mv88e6390_port_tag_remap, 5263 .port_set_policy = mv88e6352_port_set_policy, 5264 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5265 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5266 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5267 .port_set_ether_type = mv88e6351_port_set_ether_type, 5268 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5269 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5270 .port_pause_limit = mv88e6390_port_pause_limit, 5271 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5272 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5273 .port_get_cmode = mv88e6352_port_get_cmode, 5274 .port_set_cmode = mv88e6390_port_set_cmode, 5275 .port_setup_message_port = mv88e6xxx_setup_message_port, 5276 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5277 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5278 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5279 .stats_get_strings = mv88e6320_stats_get_strings, 5280 .stats_get_stats = mv88e6390_stats_get_stats, 5281 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5282 .set_egress_port = mv88e6390_g1_set_egress_port, 5283 .watchdog_ops = &mv88e6390_watchdog_ops, 5284 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5285 .pot_clear = mv88e6xxx_g2_pot_clear, 5286 .reset = mv88e6352_g1_reset, 5287 .rmu_disable = mv88e6390_g1_rmu_disable, 5288 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5289 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5290 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5291 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5292 .stu_getnext = mv88e6390_g1_stu_getnext, 5293 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5294 .serdes_get_lane = mv88e6390_serdes_get_lane, 5295 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5296 .gpio_ops = &mv88e6352_gpio_ops, 5297 .avb_ops = &mv88e6390_avb_ops, 5298 .ptp_ops = &mv88e6390_ptp_ops, 5299 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5300 .serdes_get_strings = mv88e6390_serdes_get_strings, 5301 .serdes_get_stats = mv88e6390_serdes_get_stats, 5302 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5303 .serdes_get_regs = mv88e6390_serdes_get_regs, 5304 .phylink_get_caps = mv88e6390_phylink_get_caps, 5305 .pcs_ops = &mv88e6390_pcs_ops, 5306 }; 5307 5308 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5309 /* MV88E6XXX_FAMILY_6390 */ 5310 .setup_errata = mv88e6390_setup_errata, 5311 .irl_init_all = mv88e6390_g2_irl_init_all, 5312 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5313 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5314 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5315 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5316 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5317 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5318 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5319 .port_set_link = mv88e6xxx_port_set_link, 5320 .port_sync_link = mv88e6xxx_port_sync_link, 5321 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5322 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5323 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5324 .port_tag_remap = mv88e6390_port_tag_remap, 5325 .port_set_policy = mv88e6352_port_set_policy, 5326 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5327 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5328 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5329 .port_set_ether_type = mv88e6351_port_set_ether_type, 5330 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5331 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5332 .port_pause_limit = mv88e6390_port_pause_limit, 5333 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5334 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5335 .port_get_cmode = mv88e6352_port_get_cmode, 5336 .port_set_cmode = mv88e6390x_port_set_cmode, 5337 .port_setup_message_port = mv88e6xxx_setup_message_port, 5338 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5339 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5340 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5341 .stats_get_strings = mv88e6320_stats_get_strings, 5342 .stats_get_stats = mv88e6390_stats_get_stats, 5343 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5344 .set_egress_port = mv88e6390_g1_set_egress_port, 5345 .watchdog_ops = &mv88e6390_watchdog_ops, 5346 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5347 .pot_clear = mv88e6xxx_g2_pot_clear, 5348 .reset = mv88e6352_g1_reset, 5349 .rmu_disable = mv88e6390_g1_rmu_disable, 5350 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5351 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5352 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5353 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5354 .stu_getnext = mv88e6390_g1_stu_getnext, 5355 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5356 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5357 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5358 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5359 .serdes_get_strings = mv88e6390_serdes_get_strings, 5360 .serdes_get_stats = mv88e6390_serdes_get_stats, 5361 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5362 .serdes_get_regs = mv88e6390_serdes_get_regs, 5363 .gpio_ops = &mv88e6352_gpio_ops, 5364 .avb_ops = &mv88e6390_avb_ops, 5365 .ptp_ops = &mv88e6390_ptp_ops, 5366 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5367 .pcs_ops = &mv88e6390_pcs_ops, 5368 }; 5369 5370 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5371 /* MV88E6XXX_FAMILY_6393 */ 5372 .irl_init_all = mv88e6390_g2_irl_init_all, 5373 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5374 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5375 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5376 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5377 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5378 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5379 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5380 .port_set_link = mv88e6xxx_port_set_link, 5381 .port_sync_link = mv88e6xxx_port_sync_link, 5382 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5383 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5384 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5385 .port_tag_remap = mv88e6390_port_tag_remap, 5386 .port_set_policy = mv88e6393x_port_set_policy, 5387 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5388 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5389 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5390 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5391 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5392 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5393 .port_pause_limit = mv88e6390_port_pause_limit, 5394 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5395 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5396 .port_get_cmode = mv88e6352_port_get_cmode, 5397 .port_set_cmode = mv88e6393x_port_set_cmode, 5398 .port_setup_message_port = mv88e6xxx_setup_message_port, 5399 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5400 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5401 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5402 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5403 .stats_get_strings = mv88e6320_stats_get_strings, 5404 .stats_get_stats = mv88e6390_stats_get_stats, 5405 /* .set_cpu_port is missing because this family does not support a global 5406 * CPU port, only per port CPU port which is set via 5407 * .port_set_upstream_port method. 5408 */ 5409 .set_egress_port = mv88e6393x_set_egress_port, 5410 .watchdog_ops = &mv88e6393x_watchdog_ops, 5411 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5412 .pot_clear = mv88e6xxx_g2_pot_clear, 5413 .reset = mv88e6352_g1_reset, 5414 .rmu_disable = mv88e6390_g1_rmu_disable, 5415 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5416 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5417 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5418 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5419 .stu_getnext = mv88e6390_g1_stu_getnext, 5420 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5421 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5422 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5423 /* TODO: serdes stats */ 5424 .gpio_ops = &mv88e6352_gpio_ops, 5425 .avb_ops = &mv88e6390_avb_ops, 5426 .ptp_ops = &mv88e6352_ptp_ops, 5427 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5428 .pcs_ops = &mv88e6393x_pcs_ops, 5429 }; 5430 5431 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5432 [MV88E6020] = { 5433 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5434 .family = MV88E6XXX_FAMILY_6250, 5435 .name = "Marvell 88E6020", 5436 .num_databases = 64, 5437 /* Ports 2-4 are not routed to pins 5438 * => usable ports 0, 1, 5, 6 5439 */ 5440 .num_ports = 7, 5441 .num_internal_phys = 2, 5442 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5443 .max_vid = 4095, 5444 .port_base_addr = 0x8, 5445 .phy_base_addr = 0x0, 5446 .global1_addr = 0xf, 5447 .global2_addr = 0x7, 5448 .age_time_coeff = 15000, 5449 .g1_irqs = 9, 5450 .g2_irqs = 5, 5451 .atu_move_port_mask = 0xf, 5452 .dual_chip = true, 5453 .ops = &mv88e6250_ops, 5454 }, 5455 5456 [MV88E6071] = { 5457 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5458 .family = MV88E6XXX_FAMILY_6250, 5459 .name = "Marvell 88E6071", 5460 .num_databases = 64, 5461 .num_ports = 7, 5462 .num_internal_phys = 5, 5463 .max_vid = 4095, 5464 .port_base_addr = 0x08, 5465 .phy_base_addr = 0x00, 5466 .global1_addr = 0x0f, 5467 .global2_addr = 0x07, 5468 .age_time_coeff = 15000, 5469 .g1_irqs = 9, 5470 .g2_irqs = 5, 5471 .atu_move_port_mask = 0xf, 5472 .dual_chip = true, 5473 .ops = &mv88e6250_ops, 5474 }, 5475 5476 [MV88E6085] = { 5477 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5478 .family = MV88E6XXX_FAMILY_6097, 5479 .name = "Marvell 88E6085", 5480 .num_databases = 4096, 5481 .num_macs = 8192, 5482 .num_ports = 10, 5483 .num_internal_phys = 5, 5484 .max_vid = 4095, 5485 .max_sid = 63, 5486 .port_base_addr = 0x10, 5487 .phy_base_addr = 0x0, 5488 .global1_addr = 0x1b, 5489 .global2_addr = 0x1c, 5490 .age_time_coeff = 15000, 5491 .g1_irqs = 8, 5492 .g2_irqs = 10, 5493 .atu_move_port_mask = 0xf, 5494 .pvt = true, 5495 .multi_chip = true, 5496 .ops = &mv88e6085_ops, 5497 }, 5498 5499 [MV88E6095] = { 5500 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5501 .family = MV88E6XXX_FAMILY_6095, 5502 .name = "Marvell 88E6095/88E6095F", 5503 .num_databases = 256, 5504 .num_macs = 8192, 5505 .num_ports = 11, 5506 .num_internal_phys = 0, 5507 .max_vid = 4095, 5508 .port_base_addr = 0x10, 5509 .phy_base_addr = 0x0, 5510 .global1_addr = 0x1b, 5511 .global2_addr = 0x1c, 5512 .age_time_coeff = 15000, 5513 .g1_irqs = 8, 5514 .atu_move_port_mask = 0xf, 5515 .multi_chip = true, 5516 .ops = &mv88e6095_ops, 5517 }, 5518 5519 [MV88E6097] = { 5520 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5521 .family = MV88E6XXX_FAMILY_6097, 5522 .name = "Marvell 88E6097/88E6097F", 5523 .num_databases = 4096, 5524 .num_macs = 8192, 5525 .num_ports = 11, 5526 .num_internal_phys = 8, 5527 .max_vid = 4095, 5528 .max_sid = 63, 5529 .port_base_addr = 0x10, 5530 .phy_base_addr = 0x0, 5531 .global1_addr = 0x1b, 5532 .global2_addr = 0x1c, 5533 .age_time_coeff = 15000, 5534 .g1_irqs = 8, 5535 .g2_irqs = 10, 5536 .atu_move_port_mask = 0xf, 5537 .pvt = true, 5538 .multi_chip = true, 5539 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5540 .ops = &mv88e6097_ops, 5541 }, 5542 5543 [MV88E6123] = { 5544 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5545 .family = MV88E6XXX_FAMILY_6165, 5546 .name = "Marvell 88E6123", 5547 .num_databases = 4096, 5548 .num_macs = 1024, 5549 .num_ports = 3, 5550 .num_internal_phys = 5, 5551 .max_vid = 4095, 5552 .max_sid = 63, 5553 .port_base_addr = 0x10, 5554 .phy_base_addr = 0x0, 5555 .global1_addr = 0x1b, 5556 .global2_addr = 0x1c, 5557 .age_time_coeff = 15000, 5558 .g1_irqs = 9, 5559 .g2_irqs = 10, 5560 .atu_move_port_mask = 0xf, 5561 .pvt = true, 5562 .multi_chip = true, 5563 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5564 .ops = &mv88e6123_ops, 5565 }, 5566 5567 [MV88E6131] = { 5568 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5569 .family = MV88E6XXX_FAMILY_6185, 5570 .name = "Marvell 88E6131", 5571 .num_databases = 256, 5572 .num_macs = 8192, 5573 .num_ports = 8, 5574 .num_internal_phys = 0, 5575 .max_vid = 4095, 5576 .port_base_addr = 0x10, 5577 .phy_base_addr = 0x0, 5578 .global1_addr = 0x1b, 5579 .global2_addr = 0x1c, 5580 .age_time_coeff = 15000, 5581 .g1_irqs = 9, 5582 .atu_move_port_mask = 0xf, 5583 .multi_chip = true, 5584 .ops = &mv88e6131_ops, 5585 }, 5586 5587 [MV88E6141] = { 5588 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5589 .family = MV88E6XXX_FAMILY_6341, 5590 .name = "Marvell 88E6141", 5591 .num_databases = 4096, 5592 .num_macs = 2048, 5593 .num_ports = 6, 5594 .num_internal_phys = 5, 5595 .num_gpio = 11, 5596 .max_vid = 4095, 5597 .max_sid = 63, 5598 .port_base_addr = 0x10, 5599 .phy_base_addr = 0x10, 5600 .global1_addr = 0x1b, 5601 .global2_addr = 0x1c, 5602 .age_time_coeff = 3750, 5603 .atu_move_port_mask = 0x1f, 5604 .g1_irqs = 9, 5605 .g2_irqs = 10, 5606 .pvt = true, 5607 .multi_chip = true, 5608 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5609 .ops = &mv88e6141_ops, 5610 }, 5611 5612 [MV88E6161] = { 5613 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5614 .family = MV88E6XXX_FAMILY_6165, 5615 .name = "Marvell 88E6161", 5616 .num_databases = 4096, 5617 .num_macs = 1024, 5618 .num_ports = 6, 5619 .num_internal_phys = 5, 5620 .max_vid = 4095, 5621 .max_sid = 63, 5622 .port_base_addr = 0x10, 5623 .phy_base_addr = 0x0, 5624 .global1_addr = 0x1b, 5625 .global2_addr = 0x1c, 5626 .age_time_coeff = 15000, 5627 .g1_irqs = 9, 5628 .g2_irqs = 10, 5629 .atu_move_port_mask = 0xf, 5630 .pvt = true, 5631 .multi_chip = true, 5632 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5633 .ptp_support = true, 5634 .ops = &mv88e6161_ops, 5635 }, 5636 5637 [MV88E6165] = { 5638 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5639 .family = MV88E6XXX_FAMILY_6165, 5640 .name = "Marvell 88E6165", 5641 .num_databases = 4096, 5642 .num_macs = 8192, 5643 .num_ports = 6, 5644 .num_internal_phys = 0, 5645 .max_vid = 4095, 5646 .max_sid = 63, 5647 .port_base_addr = 0x10, 5648 .phy_base_addr = 0x0, 5649 .global1_addr = 0x1b, 5650 .global2_addr = 0x1c, 5651 .age_time_coeff = 15000, 5652 .g1_irqs = 9, 5653 .g2_irqs = 10, 5654 .atu_move_port_mask = 0xf, 5655 .pvt = true, 5656 .multi_chip = true, 5657 .ptp_support = true, 5658 .ops = &mv88e6165_ops, 5659 }, 5660 5661 [MV88E6171] = { 5662 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5663 .family = MV88E6XXX_FAMILY_6351, 5664 .name = "Marvell 88E6171", 5665 .num_databases = 4096, 5666 .num_macs = 8192, 5667 .num_ports = 7, 5668 .num_internal_phys = 5, 5669 .max_vid = 4095, 5670 .max_sid = 63, 5671 .port_base_addr = 0x10, 5672 .phy_base_addr = 0x0, 5673 .global1_addr = 0x1b, 5674 .global2_addr = 0x1c, 5675 .age_time_coeff = 15000, 5676 .g1_irqs = 9, 5677 .g2_irqs = 10, 5678 .atu_move_port_mask = 0xf, 5679 .pvt = true, 5680 .multi_chip = true, 5681 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5682 .ops = &mv88e6171_ops, 5683 }, 5684 5685 [MV88E6172] = { 5686 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5687 .family = MV88E6XXX_FAMILY_6352, 5688 .name = "Marvell 88E6172", 5689 .num_databases = 4096, 5690 .num_macs = 8192, 5691 .num_ports = 7, 5692 .num_internal_phys = 5, 5693 .num_gpio = 15, 5694 .max_vid = 4095, 5695 .max_sid = 63, 5696 .port_base_addr = 0x10, 5697 .phy_base_addr = 0x0, 5698 .global1_addr = 0x1b, 5699 .global2_addr = 0x1c, 5700 .age_time_coeff = 15000, 5701 .g1_irqs = 9, 5702 .g2_irqs = 10, 5703 .atu_move_port_mask = 0xf, 5704 .pvt = true, 5705 .multi_chip = true, 5706 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5707 .ops = &mv88e6172_ops, 5708 }, 5709 5710 [MV88E6175] = { 5711 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5712 .family = MV88E6XXX_FAMILY_6351, 5713 .name = "Marvell 88E6175", 5714 .num_databases = 4096, 5715 .num_macs = 8192, 5716 .num_ports = 7, 5717 .num_internal_phys = 5, 5718 .max_vid = 4095, 5719 .max_sid = 63, 5720 .port_base_addr = 0x10, 5721 .phy_base_addr = 0x0, 5722 .global1_addr = 0x1b, 5723 .global2_addr = 0x1c, 5724 .age_time_coeff = 15000, 5725 .g1_irqs = 9, 5726 .g2_irqs = 10, 5727 .atu_move_port_mask = 0xf, 5728 .pvt = true, 5729 .multi_chip = true, 5730 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5731 .ops = &mv88e6175_ops, 5732 }, 5733 5734 [MV88E6176] = { 5735 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5736 .family = MV88E6XXX_FAMILY_6352, 5737 .name = "Marvell 88E6176", 5738 .num_databases = 4096, 5739 .num_macs = 8192, 5740 .num_ports = 7, 5741 .num_internal_phys = 5, 5742 .num_gpio = 15, 5743 .max_vid = 4095, 5744 .max_sid = 63, 5745 .port_base_addr = 0x10, 5746 .phy_base_addr = 0x0, 5747 .global1_addr = 0x1b, 5748 .global2_addr = 0x1c, 5749 .age_time_coeff = 15000, 5750 .g1_irqs = 9, 5751 .g2_irqs = 10, 5752 .atu_move_port_mask = 0xf, 5753 .pvt = true, 5754 .multi_chip = true, 5755 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5756 .ops = &mv88e6176_ops, 5757 }, 5758 5759 [MV88E6185] = { 5760 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5761 .family = MV88E6XXX_FAMILY_6185, 5762 .name = "Marvell 88E6185", 5763 .num_databases = 256, 5764 .num_macs = 8192, 5765 .num_ports = 10, 5766 .num_internal_phys = 0, 5767 .max_vid = 4095, 5768 .port_base_addr = 0x10, 5769 .phy_base_addr = 0x0, 5770 .global1_addr = 0x1b, 5771 .global2_addr = 0x1c, 5772 .age_time_coeff = 15000, 5773 .g1_irqs = 8, 5774 .atu_move_port_mask = 0xf, 5775 .multi_chip = true, 5776 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5777 .ops = &mv88e6185_ops, 5778 }, 5779 5780 [MV88E6190] = { 5781 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5782 .family = MV88E6XXX_FAMILY_6390, 5783 .name = "Marvell 88E6190", 5784 .num_databases = 4096, 5785 .num_macs = 16384, 5786 .num_ports = 11, /* 10 + Z80 */ 5787 .num_internal_phys = 9, 5788 .num_gpio = 16, 5789 .max_vid = 8191, 5790 .max_sid = 63, 5791 .port_base_addr = 0x0, 5792 .phy_base_addr = 0x0, 5793 .global1_addr = 0x1b, 5794 .global2_addr = 0x1c, 5795 .age_time_coeff = 3750, 5796 .g1_irqs = 9, 5797 .g2_irqs = 14, 5798 .pvt = true, 5799 .multi_chip = true, 5800 .atu_move_port_mask = 0x1f, 5801 .ops = &mv88e6190_ops, 5802 }, 5803 5804 [MV88E6190X] = { 5805 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5806 .family = MV88E6XXX_FAMILY_6390, 5807 .name = "Marvell 88E6190X", 5808 .num_databases = 4096, 5809 .num_macs = 16384, 5810 .num_ports = 11, /* 10 + Z80 */ 5811 .num_internal_phys = 9, 5812 .num_gpio = 16, 5813 .max_vid = 8191, 5814 .max_sid = 63, 5815 .port_base_addr = 0x0, 5816 .phy_base_addr = 0x0, 5817 .global1_addr = 0x1b, 5818 .global2_addr = 0x1c, 5819 .age_time_coeff = 3750, 5820 .g1_irqs = 9, 5821 .g2_irqs = 14, 5822 .atu_move_port_mask = 0x1f, 5823 .pvt = true, 5824 .multi_chip = true, 5825 .ops = &mv88e6190x_ops, 5826 }, 5827 5828 [MV88E6191] = { 5829 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5830 .family = MV88E6XXX_FAMILY_6390, 5831 .name = "Marvell 88E6191", 5832 .num_databases = 4096, 5833 .num_macs = 16384, 5834 .num_ports = 11, /* 10 + Z80 */ 5835 .num_internal_phys = 9, 5836 .max_vid = 8191, 5837 .max_sid = 63, 5838 .port_base_addr = 0x0, 5839 .phy_base_addr = 0x0, 5840 .global1_addr = 0x1b, 5841 .global2_addr = 0x1c, 5842 .age_time_coeff = 3750, 5843 .g1_irqs = 9, 5844 .g2_irqs = 14, 5845 .atu_move_port_mask = 0x1f, 5846 .pvt = true, 5847 .multi_chip = true, 5848 .ptp_support = true, 5849 .ops = &mv88e6191_ops, 5850 }, 5851 5852 [MV88E6191X] = { 5853 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5854 .family = MV88E6XXX_FAMILY_6393, 5855 .name = "Marvell 88E6191X", 5856 .num_databases = 4096, 5857 .num_ports = 11, /* 10 + Z80 */ 5858 .num_internal_phys = 8, 5859 .internal_phys_offset = 1, 5860 .max_vid = 8191, 5861 .max_sid = 63, 5862 .port_base_addr = 0x0, 5863 .phy_base_addr = 0x0, 5864 .global1_addr = 0x1b, 5865 .global2_addr = 0x1c, 5866 .age_time_coeff = 3750, 5867 .g1_irqs = 10, 5868 .g2_irqs = 14, 5869 .atu_move_port_mask = 0x1f, 5870 .pvt = true, 5871 .multi_chip = true, 5872 .ptp_support = true, 5873 .ops = &mv88e6393x_ops, 5874 }, 5875 5876 [MV88E6193X] = { 5877 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5878 .family = MV88E6XXX_FAMILY_6393, 5879 .name = "Marvell 88E6193X", 5880 .num_databases = 4096, 5881 .num_ports = 11, /* 10 + Z80 */ 5882 .num_internal_phys = 8, 5883 .internal_phys_offset = 1, 5884 .max_vid = 8191, 5885 .max_sid = 63, 5886 .port_base_addr = 0x0, 5887 .phy_base_addr = 0x0, 5888 .global1_addr = 0x1b, 5889 .global2_addr = 0x1c, 5890 .age_time_coeff = 3750, 5891 .g1_irqs = 10, 5892 .g2_irqs = 14, 5893 .atu_move_port_mask = 0x1f, 5894 .pvt = true, 5895 .multi_chip = true, 5896 .ptp_support = true, 5897 .ops = &mv88e6393x_ops, 5898 }, 5899 5900 [MV88E6220] = { 5901 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5902 .family = MV88E6XXX_FAMILY_6250, 5903 .name = "Marvell 88E6220", 5904 .num_databases = 64, 5905 5906 /* Ports 2-4 are not routed to pins 5907 * => usable ports 0, 1, 5, 6 5908 */ 5909 .num_ports = 7, 5910 .num_internal_phys = 2, 5911 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5912 .max_vid = 4095, 5913 .port_base_addr = 0x08, 5914 .phy_base_addr = 0x00, 5915 .global1_addr = 0x0f, 5916 .global2_addr = 0x07, 5917 .age_time_coeff = 15000, 5918 .g1_irqs = 9, 5919 .g2_irqs = 10, 5920 .atu_move_port_mask = 0xf, 5921 .dual_chip = true, 5922 .ptp_support = true, 5923 .ops = &mv88e6250_ops, 5924 }, 5925 5926 [MV88E6240] = { 5927 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5928 .family = MV88E6XXX_FAMILY_6352, 5929 .name = "Marvell 88E6240", 5930 .num_databases = 4096, 5931 .num_macs = 8192, 5932 .num_ports = 7, 5933 .num_internal_phys = 5, 5934 .num_gpio = 15, 5935 .max_vid = 4095, 5936 .max_sid = 63, 5937 .port_base_addr = 0x10, 5938 .phy_base_addr = 0x0, 5939 .global1_addr = 0x1b, 5940 .global2_addr = 0x1c, 5941 .age_time_coeff = 15000, 5942 .g1_irqs = 9, 5943 .g2_irqs = 10, 5944 .atu_move_port_mask = 0xf, 5945 .pvt = true, 5946 .multi_chip = true, 5947 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5948 .ptp_support = true, 5949 .ops = &mv88e6240_ops, 5950 }, 5951 5952 [MV88E6250] = { 5953 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5954 .family = MV88E6XXX_FAMILY_6250, 5955 .name = "Marvell 88E6250", 5956 .num_databases = 64, 5957 .num_ports = 7, 5958 .num_internal_phys = 5, 5959 .max_vid = 4095, 5960 .port_base_addr = 0x08, 5961 .phy_base_addr = 0x00, 5962 .global1_addr = 0x0f, 5963 .global2_addr = 0x07, 5964 .age_time_coeff = 15000, 5965 .g1_irqs = 9, 5966 .g2_irqs = 10, 5967 .atu_move_port_mask = 0xf, 5968 .dual_chip = true, 5969 .ptp_support = true, 5970 .ops = &mv88e6250_ops, 5971 }, 5972 5973 [MV88E6290] = { 5974 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5975 .family = MV88E6XXX_FAMILY_6390, 5976 .name = "Marvell 88E6290", 5977 .num_databases = 4096, 5978 .num_ports = 11, /* 10 + Z80 */ 5979 .num_internal_phys = 9, 5980 .num_gpio = 16, 5981 .max_vid = 8191, 5982 .max_sid = 63, 5983 .port_base_addr = 0x0, 5984 .phy_base_addr = 0x0, 5985 .global1_addr = 0x1b, 5986 .global2_addr = 0x1c, 5987 .age_time_coeff = 3750, 5988 .g1_irqs = 9, 5989 .g2_irqs = 14, 5990 .atu_move_port_mask = 0x1f, 5991 .pvt = true, 5992 .multi_chip = true, 5993 .ptp_support = true, 5994 .ops = &mv88e6290_ops, 5995 }, 5996 5997 [MV88E6320] = { 5998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5999 .family = MV88E6XXX_FAMILY_6320, 6000 .name = "Marvell 88E6320", 6001 .num_databases = 4096, 6002 .num_macs = 8192, 6003 .num_ports = 7, 6004 .num_internal_phys = 5, 6005 .num_gpio = 15, 6006 .max_vid = 4095, 6007 .port_base_addr = 0x10, 6008 .phy_base_addr = 0x0, 6009 .global1_addr = 0x1b, 6010 .global2_addr = 0x1c, 6011 .age_time_coeff = 15000, 6012 .g1_irqs = 8, 6013 .g2_irqs = 10, 6014 .atu_move_port_mask = 0xf, 6015 .pvt = true, 6016 .multi_chip = true, 6017 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6018 .ptp_support = true, 6019 .ops = &mv88e6320_ops, 6020 }, 6021 6022 [MV88E6321] = { 6023 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6024 .family = MV88E6XXX_FAMILY_6320, 6025 .name = "Marvell 88E6321", 6026 .num_databases = 4096, 6027 .num_macs = 8192, 6028 .num_ports = 7, 6029 .num_internal_phys = 5, 6030 .num_gpio = 15, 6031 .max_vid = 4095, 6032 .port_base_addr = 0x10, 6033 .phy_base_addr = 0x0, 6034 .global1_addr = 0x1b, 6035 .global2_addr = 0x1c, 6036 .age_time_coeff = 15000, 6037 .g1_irqs = 8, 6038 .g2_irqs = 10, 6039 .atu_move_port_mask = 0xf, 6040 .multi_chip = true, 6041 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6042 .ptp_support = true, 6043 .ops = &mv88e6321_ops, 6044 }, 6045 6046 [MV88E6341] = { 6047 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6048 .family = MV88E6XXX_FAMILY_6341, 6049 .name = "Marvell 88E6341", 6050 .num_databases = 4096, 6051 .num_macs = 2048, 6052 .num_internal_phys = 5, 6053 .num_ports = 6, 6054 .num_gpio = 11, 6055 .max_vid = 4095, 6056 .max_sid = 63, 6057 .port_base_addr = 0x10, 6058 .phy_base_addr = 0x10, 6059 .global1_addr = 0x1b, 6060 .global2_addr = 0x1c, 6061 .age_time_coeff = 3750, 6062 .atu_move_port_mask = 0x1f, 6063 .g1_irqs = 9, 6064 .g2_irqs = 10, 6065 .pvt = true, 6066 .multi_chip = true, 6067 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6068 .ptp_support = true, 6069 .ops = &mv88e6341_ops, 6070 }, 6071 6072 [MV88E6350] = { 6073 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6074 .family = MV88E6XXX_FAMILY_6351, 6075 .name = "Marvell 88E6350", 6076 .num_databases = 4096, 6077 .num_macs = 8192, 6078 .num_ports = 7, 6079 .num_internal_phys = 5, 6080 .max_vid = 4095, 6081 .max_sid = 63, 6082 .port_base_addr = 0x10, 6083 .phy_base_addr = 0x0, 6084 .global1_addr = 0x1b, 6085 .global2_addr = 0x1c, 6086 .age_time_coeff = 15000, 6087 .g1_irqs = 9, 6088 .g2_irqs = 10, 6089 .atu_move_port_mask = 0xf, 6090 .pvt = true, 6091 .multi_chip = true, 6092 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6093 .ops = &mv88e6350_ops, 6094 }, 6095 6096 [MV88E6351] = { 6097 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6098 .family = MV88E6XXX_FAMILY_6351, 6099 .name = "Marvell 88E6351", 6100 .num_databases = 4096, 6101 .num_macs = 8192, 6102 .num_ports = 7, 6103 .num_internal_phys = 5, 6104 .max_vid = 4095, 6105 .max_sid = 63, 6106 .port_base_addr = 0x10, 6107 .phy_base_addr = 0x0, 6108 .global1_addr = 0x1b, 6109 .global2_addr = 0x1c, 6110 .age_time_coeff = 15000, 6111 .g1_irqs = 9, 6112 .g2_irqs = 10, 6113 .atu_move_port_mask = 0xf, 6114 .pvt = true, 6115 .multi_chip = true, 6116 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6117 .ops = &mv88e6351_ops, 6118 }, 6119 6120 [MV88E6352] = { 6121 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6122 .family = MV88E6XXX_FAMILY_6352, 6123 .name = "Marvell 88E6352", 6124 .num_databases = 4096, 6125 .num_macs = 8192, 6126 .num_ports = 7, 6127 .num_internal_phys = 5, 6128 .num_gpio = 15, 6129 .max_vid = 4095, 6130 .max_sid = 63, 6131 .port_base_addr = 0x10, 6132 .phy_base_addr = 0x0, 6133 .global1_addr = 0x1b, 6134 .global2_addr = 0x1c, 6135 .age_time_coeff = 15000, 6136 .g1_irqs = 9, 6137 .g2_irqs = 10, 6138 .atu_move_port_mask = 0xf, 6139 .pvt = true, 6140 .multi_chip = true, 6141 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6142 .ptp_support = true, 6143 .ops = &mv88e6352_ops, 6144 }, 6145 [MV88E6361] = { 6146 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6147 .family = MV88E6XXX_FAMILY_6393, 6148 .name = "Marvell 88E6361", 6149 .num_databases = 4096, 6150 .num_macs = 16384, 6151 .num_ports = 11, 6152 /* Ports 1, 2 and 8 are not routed */ 6153 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6154 .num_internal_phys = 5, 6155 .internal_phys_offset = 3, 6156 .max_vid = 4095, 6157 .max_sid = 63, 6158 .port_base_addr = 0x0, 6159 .phy_base_addr = 0x0, 6160 .global1_addr = 0x1b, 6161 .global2_addr = 0x1c, 6162 .age_time_coeff = 3750, 6163 .g1_irqs = 10, 6164 .g2_irqs = 14, 6165 .atu_move_port_mask = 0x1f, 6166 .pvt = true, 6167 .multi_chip = true, 6168 .ptp_support = true, 6169 .ops = &mv88e6393x_ops, 6170 }, 6171 [MV88E6390] = { 6172 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6173 .family = MV88E6XXX_FAMILY_6390, 6174 .name = "Marvell 88E6390", 6175 .num_databases = 4096, 6176 .num_macs = 16384, 6177 .num_ports = 11, /* 10 + Z80 */ 6178 .num_internal_phys = 9, 6179 .num_gpio = 16, 6180 .max_vid = 8191, 6181 .max_sid = 63, 6182 .port_base_addr = 0x0, 6183 .phy_base_addr = 0x0, 6184 .global1_addr = 0x1b, 6185 .global2_addr = 0x1c, 6186 .age_time_coeff = 3750, 6187 .g1_irqs = 9, 6188 .g2_irqs = 14, 6189 .atu_move_port_mask = 0x1f, 6190 .pvt = true, 6191 .multi_chip = true, 6192 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6193 .ptp_support = true, 6194 .ops = &mv88e6390_ops, 6195 }, 6196 [MV88E6390X] = { 6197 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6198 .family = MV88E6XXX_FAMILY_6390, 6199 .name = "Marvell 88E6390X", 6200 .num_databases = 4096, 6201 .num_macs = 16384, 6202 .num_ports = 11, /* 10 + Z80 */ 6203 .num_internal_phys = 9, 6204 .num_gpio = 16, 6205 .max_vid = 8191, 6206 .max_sid = 63, 6207 .port_base_addr = 0x0, 6208 .phy_base_addr = 0x0, 6209 .global1_addr = 0x1b, 6210 .global2_addr = 0x1c, 6211 .age_time_coeff = 3750, 6212 .g1_irqs = 9, 6213 .g2_irqs = 14, 6214 .atu_move_port_mask = 0x1f, 6215 .pvt = true, 6216 .multi_chip = true, 6217 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6218 .ptp_support = true, 6219 .ops = &mv88e6390x_ops, 6220 }, 6221 6222 [MV88E6393X] = { 6223 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6224 .family = MV88E6XXX_FAMILY_6393, 6225 .name = "Marvell 88E6393X", 6226 .num_databases = 4096, 6227 .num_ports = 11, /* 10 + Z80 */ 6228 .num_internal_phys = 8, 6229 .internal_phys_offset = 1, 6230 .max_vid = 8191, 6231 .max_sid = 63, 6232 .port_base_addr = 0x0, 6233 .phy_base_addr = 0x0, 6234 .global1_addr = 0x1b, 6235 .global2_addr = 0x1c, 6236 .age_time_coeff = 3750, 6237 .g1_irqs = 10, 6238 .g2_irqs = 14, 6239 .atu_move_port_mask = 0x1f, 6240 .pvt = true, 6241 .multi_chip = true, 6242 .ptp_support = true, 6243 .ops = &mv88e6393x_ops, 6244 }, 6245 }; 6246 6247 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6248 { 6249 int i; 6250 6251 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6252 if (mv88e6xxx_table[i].prod_num == prod_num) 6253 return &mv88e6xxx_table[i]; 6254 6255 return NULL; 6256 } 6257 6258 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6259 { 6260 const struct mv88e6xxx_info *info; 6261 unsigned int prod_num, rev; 6262 u16 id; 6263 int err; 6264 6265 mv88e6xxx_reg_lock(chip); 6266 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6267 mv88e6xxx_reg_unlock(chip); 6268 if (err) 6269 return err; 6270 6271 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6272 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6273 6274 info = mv88e6xxx_lookup_info(prod_num); 6275 if (!info) 6276 return -ENODEV; 6277 6278 /* Update the compatible info with the probed one */ 6279 chip->info = info; 6280 6281 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6282 chip->info->prod_num, chip->info->name, rev); 6283 6284 return 0; 6285 } 6286 6287 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6288 struct mdio_device *mdiodev) 6289 { 6290 int err; 6291 6292 /* dual_chip takes precedence over single/multi-chip modes */ 6293 if (chip->info->dual_chip) 6294 return -EINVAL; 6295 6296 /* If the mdio addr is 16 indicating the first port address of a switch 6297 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6298 * configured in single chip addressing mode. Setup the smi access as 6299 * single chip addressing mode and attempt to detect the model of the 6300 * switch, if this fails the device is not configured in single chip 6301 * addressing mode. 6302 */ 6303 if (mdiodev->addr != 16) 6304 return -EINVAL; 6305 6306 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6307 if (err) 6308 return err; 6309 6310 return mv88e6xxx_detect(chip); 6311 } 6312 6313 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6314 { 6315 struct mv88e6xxx_chip *chip; 6316 6317 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6318 if (!chip) 6319 return NULL; 6320 6321 chip->dev = dev; 6322 6323 mutex_init(&chip->reg_lock); 6324 INIT_LIST_HEAD(&chip->mdios); 6325 idr_init(&chip->policies); 6326 INIT_LIST_HEAD(&chip->msts); 6327 6328 return chip; 6329 } 6330 6331 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6332 int port, 6333 enum dsa_tag_protocol m) 6334 { 6335 struct mv88e6xxx_chip *chip = ds->priv; 6336 6337 return chip->tag_protocol; 6338 } 6339 6340 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6341 enum dsa_tag_protocol proto) 6342 { 6343 struct mv88e6xxx_chip *chip = ds->priv; 6344 enum dsa_tag_protocol old_protocol; 6345 struct dsa_port *cpu_dp; 6346 int err; 6347 6348 switch (proto) { 6349 case DSA_TAG_PROTO_EDSA: 6350 switch (chip->info->edsa_support) { 6351 case MV88E6XXX_EDSA_UNSUPPORTED: 6352 return -EPROTONOSUPPORT; 6353 case MV88E6XXX_EDSA_UNDOCUMENTED: 6354 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6355 fallthrough; 6356 case MV88E6XXX_EDSA_SUPPORTED: 6357 break; 6358 } 6359 break; 6360 case DSA_TAG_PROTO_DSA: 6361 break; 6362 default: 6363 return -EPROTONOSUPPORT; 6364 } 6365 6366 old_protocol = chip->tag_protocol; 6367 chip->tag_protocol = proto; 6368 6369 mv88e6xxx_reg_lock(chip); 6370 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6371 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6372 if (err) { 6373 mv88e6xxx_reg_unlock(chip); 6374 goto unwind; 6375 } 6376 } 6377 mv88e6xxx_reg_unlock(chip); 6378 6379 return 0; 6380 6381 unwind: 6382 chip->tag_protocol = old_protocol; 6383 6384 mv88e6xxx_reg_lock(chip); 6385 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6386 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6387 mv88e6xxx_reg_unlock(chip); 6388 6389 return err; 6390 } 6391 6392 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6393 const struct switchdev_obj_port_mdb *mdb, 6394 struct dsa_db db) 6395 { 6396 struct mv88e6xxx_chip *chip = ds->priv; 6397 int err; 6398 6399 mv88e6xxx_reg_lock(chip); 6400 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6401 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6402 mv88e6xxx_reg_unlock(chip); 6403 6404 return err; 6405 } 6406 6407 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6408 const struct switchdev_obj_port_mdb *mdb, 6409 struct dsa_db db) 6410 { 6411 struct mv88e6xxx_chip *chip = ds->priv; 6412 int err; 6413 6414 mv88e6xxx_reg_lock(chip); 6415 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6416 mv88e6xxx_reg_unlock(chip); 6417 6418 return err; 6419 } 6420 6421 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6422 struct dsa_mall_mirror_tc_entry *mirror, 6423 bool ingress, 6424 struct netlink_ext_ack *extack) 6425 { 6426 enum mv88e6xxx_egress_direction direction = ingress ? 6427 MV88E6XXX_EGRESS_DIR_INGRESS : 6428 MV88E6XXX_EGRESS_DIR_EGRESS; 6429 struct mv88e6xxx_chip *chip = ds->priv; 6430 bool other_mirrors = false; 6431 int i; 6432 int err; 6433 6434 mutex_lock(&chip->reg_lock); 6435 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6436 mirror->to_local_port) { 6437 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6438 other_mirrors |= ingress ? 6439 chip->ports[i].mirror_ingress : 6440 chip->ports[i].mirror_egress; 6441 6442 /* Can't change egress port when other mirror is active */ 6443 if (other_mirrors) { 6444 err = -EBUSY; 6445 goto out; 6446 } 6447 6448 err = mv88e6xxx_set_egress_port(chip, direction, 6449 mirror->to_local_port); 6450 if (err) 6451 goto out; 6452 } 6453 6454 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6455 out: 6456 mutex_unlock(&chip->reg_lock); 6457 6458 return err; 6459 } 6460 6461 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6462 struct dsa_mall_mirror_tc_entry *mirror) 6463 { 6464 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6465 MV88E6XXX_EGRESS_DIR_INGRESS : 6466 MV88E6XXX_EGRESS_DIR_EGRESS; 6467 struct mv88e6xxx_chip *chip = ds->priv; 6468 bool other_mirrors = false; 6469 int i; 6470 6471 mutex_lock(&chip->reg_lock); 6472 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6473 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6474 6475 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6476 other_mirrors |= mirror->ingress ? 6477 chip->ports[i].mirror_ingress : 6478 chip->ports[i].mirror_egress; 6479 6480 /* Reset egress port when no other mirror is active */ 6481 if (!other_mirrors) { 6482 if (mv88e6xxx_set_egress_port(chip, direction, 6483 dsa_upstream_port(ds, port))) 6484 dev_err(ds->dev, "failed to set egress port\n"); 6485 } 6486 6487 mutex_unlock(&chip->reg_lock); 6488 } 6489 6490 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6491 struct switchdev_brport_flags flags, 6492 struct netlink_ext_ack *extack) 6493 { 6494 struct mv88e6xxx_chip *chip = ds->priv; 6495 const struct mv88e6xxx_ops *ops; 6496 6497 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6498 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6499 return -EINVAL; 6500 6501 ops = chip->info->ops; 6502 6503 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6504 return -EINVAL; 6505 6506 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6507 return -EINVAL; 6508 6509 return 0; 6510 } 6511 6512 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6513 struct switchdev_brport_flags flags, 6514 struct netlink_ext_ack *extack) 6515 { 6516 struct mv88e6xxx_chip *chip = ds->priv; 6517 int err = 0; 6518 6519 mv88e6xxx_reg_lock(chip); 6520 6521 if (flags.mask & BR_LEARNING) { 6522 bool learning = !!(flags.val & BR_LEARNING); 6523 u16 pav = learning ? (1 << port) : 0; 6524 6525 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6526 if (err) 6527 goto out; 6528 } 6529 6530 if (flags.mask & BR_FLOOD) { 6531 bool unicast = !!(flags.val & BR_FLOOD); 6532 6533 err = chip->info->ops->port_set_ucast_flood(chip, port, 6534 unicast); 6535 if (err) 6536 goto out; 6537 } 6538 6539 if (flags.mask & BR_MCAST_FLOOD) { 6540 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6541 6542 err = chip->info->ops->port_set_mcast_flood(chip, port, 6543 multicast); 6544 if (err) 6545 goto out; 6546 } 6547 6548 if (flags.mask & BR_BCAST_FLOOD) { 6549 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6550 6551 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6552 if (err) 6553 goto out; 6554 } 6555 6556 if (flags.mask & BR_PORT_MAB) { 6557 bool mab = !!(flags.val & BR_PORT_MAB); 6558 6559 mv88e6xxx_port_set_mab(chip, port, mab); 6560 } 6561 6562 if (flags.mask & BR_PORT_LOCKED) { 6563 bool locked = !!(flags.val & BR_PORT_LOCKED); 6564 6565 err = mv88e6xxx_port_set_lock(chip, port, locked); 6566 if (err) 6567 goto out; 6568 } 6569 out: 6570 mv88e6xxx_reg_unlock(chip); 6571 6572 return err; 6573 } 6574 6575 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6576 struct dsa_lag lag, 6577 struct netdev_lag_upper_info *info, 6578 struct netlink_ext_ack *extack) 6579 { 6580 struct mv88e6xxx_chip *chip = ds->priv; 6581 struct dsa_port *dp; 6582 int members = 0; 6583 6584 if (!mv88e6xxx_has_lag(chip)) { 6585 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6586 return false; 6587 } 6588 6589 if (!lag.id) 6590 return false; 6591 6592 dsa_lag_foreach_port(dp, ds->dst, &lag) 6593 /* Includes the port joining the LAG */ 6594 members++; 6595 6596 if (members > 8) { 6597 NL_SET_ERR_MSG_MOD(extack, 6598 "Cannot offload more than 8 LAG ports"); 6599 return false; 6600 } 6601 6602 /* We could potentially relax this to include active 6603 * backup in the future. 6604 */ 6605 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6606 NL_SET_ERR_MSG_MOD(extack, 6607 "Can only offload LAG using hash TX type"); 6608 return false; 6609 } 6610 6611 /* Ideally we would also validate that the hash type matches 6612 * the hardware. Alas, this is always set to unknown on team 6613 * interfaces. 6614 */ 6615 return true; 6616 } 6617 6618 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6619 { 6620 struct mv88e6xxx_chip *chip = ds->priv; 6621 struct dsa_port *dp; 6622 u16 map = 0; 6623 int id; 6624 6625 /* DSA LAG IDs are one-based, hardware is zero-based */ 6626 id = lag.id - 1; 6627 6628 /* Build the map of all ports to distribute flows destined for 6629 * this LAG. This can be either a local user port, or a DSA 6630 * port if the LAG port is on a remote chip. 6631 */ 6632 dsa_lag_foreach_port(dp, ds->dst, &lag) 6633 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6634 6635 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6636 } 6637 6638 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6639 /* Row number corresponds to the number of active members in a 6640 * LAG. Each column states which of the eight hash buckets are 6641 * mapped to the column:th port in the LAG. 6642 * 6643 * Example: In a LAG with three active ports, the second port 6644 * ([2][1]) would be selected for traffic mapped to buckets 6645 * 3,4,5 (0x38). 6646 */ 6647 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6648 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6649 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6650 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6651 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6652 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6653 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6654 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6655 }; 6656 6657 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6658 int num_tx, int nth) 6659 { 6660 u8 active = 0; 6661 int i; 6662 6663 num_tx = num_tx <= 8 ? num_tx : 8; 6664 if (nth < num_tx) 6665 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6666 6667 for (i = 0; i < 8; i++) { 6668 if (BIT(i) & active) 6669 mask[i] |= BIT(port); 6670 } 6671 } 6672 6673 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6674 { 6675 struct mv88e6xxx_chip *chip = ds->priv; 6676 unsigned int id, num_tx; 6677 struct dsa_port *dp; 6678 struct dsa_lag *lag; 6679 int i, err, nth; 6680 u16 mask[8]; 6681 u16 ivec; 6682 6683 /* Assume no port is a member of any LAG. */ 6684 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6685 6686 /* Disable all masks for ports that _are_ members of a LAG. */ 6687 dsa_switch_for_each_port(dp, ds) { 6688 if (!dp->lag) 6689 continue; 6690 6691 ivec &= ~BIT(dp->index); 6692 } 6693 6694 for (i = 0; i < 8; i++) 6695 mask[i] = ivec; 6696 6697 /* Enable the correct subset of masks for all LAG ports that 6698 * are in the Tx set. 6699 */ 6700 dsa_lags_foreach_id(id, ds->dst) { 6701 lag = dsa_lag_by_id(ds->dst, id); 6702 if (!lag) 6703 continue; 6704 6705 num_tx = 0; 6706 dsa_lag_foreach_port(dp, ds->dst, lag) { 6707 if (dp->lag_tx_enabled) 6708 num_tx++; 6709 } 6710 6711 if (!num_tx) 6712 continue; 6713 6714 nth = 0; 6715 dsa_lag_foreach_port(dp, ds->dst, lag) { 6716 if (!dp->lag_tx_enabled) 6717 continue; 6718 6719 if (dp->ds == ds) 6720 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6721 num_tx, nth); 6722 6723 nth++; 6724 } 6725 } 6726 6727 for (i = 0; i < 8; i++) { 6728 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6729 if (err) 6730 return err; 6731 } 6732 6733 return 0; 6734 } 6735 6736 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6737 struct dsa_lag lag) 6738 { 6739 int err; 6740 6741 err = mv88e6xxx_lag_sync_masks(ds); 6742 6743 if (!err) 6744 err = mv88e6xxx_lag_sync_map(ds, lag); 6745 6746 return err; 6747 } 6748 6749 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6750 { 6751 struct mv88e6xxx_chip *chip = ds->priv; 6752 int err; 6753 6754 mv88e6xxx_reg_lock(chip); 6755 err = mv88e6xxx_lag_sync_masks(ds); 6756 mv88e6xxx_reg_unlock(chip); 6757 return err; 6758 } 6759 6760 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6761 struct dsa_lag lag, 6762 struct netdev_lag_upper_info *info, 6763 struct netlink_ext_ack *extack) 6764 { 6765 struct mv88e6xxx_chip *chip = ds->priv; 6766 int err, id; 6767 6768 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6769 return -EOPNOTSUPP; 6770 6771 /* DSA LAG IDs are one-based */ 6772 id = lag.id - 1; 6773 6774 mv88e6xxx_reg_lock(chip); 6775 6776 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6777 if (err) 6778 goto err_unlock; 6779 6780 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6781 if (err) 6782 goto err_clear_trunk; 6783 6784 mv88e6xxx_reg_unlock(chip); 6785 return 0; 6786 6787 err_clear_trunk: 6788 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6789 err_unlock: 6790 mv88e6xxx_reg_unlock(chip); 6791 return err; 6792 } 6793 6794 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6795 struct dsa_lag lag) 6796 { 6797 struct mv88e6xxx_chip *chip = ds->priv; 6798 int err_sync, err_trunk; 6799 6800 mv88e6xxx_reg_lock(chip); 6801 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6802 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6803 mv88e6xxx_reg_unlock(chip); 6804 return err_sync ? : err_trunk; 6805 } 6806 6807 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6808 int port) 6809 { 6810 struct mv88e6xxx_chip *chip = ds->priv; 6811 int err; 6812 6813 mv88e6xxx_reg_lock(chip); 6814 err = mv88e6xxx_lag_sync_masks(ds); 6815 mv88e6xxx_reg_unlock(chip); 6816 return err; 6817 } 6818 6819 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6820 int port, struct dsa_lag lag, 6821 struct netdev_lag_upper_info *info, 6822 struct netlink_ext_ack *extack) 6823 { 6824 struct mv88e6xxx_chip *chip = ds->priv; 6825 int err; 6826 6827 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 6828 return -EOPNOTSUPP; 6829 6830 mv88e6xxx_reg_lock(chip); 6831 6832 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6833 if (err) 6834 goto unlock; 6835 6836 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6837 6838 unlock: 6839 mv88e6xxx_reg_unlock(chip); 6840 return err; 6841 } 6842 6843 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6844 int port, struct dsa_lag lag) 6845 { 6846 struct mv88e6xxx_chip *chip = ds->priv; 6847 int err_sync, err_pvt; 6848 6849 mv88e6xxx_reg_lock(chip); 6850 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6851 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6852 mv88e6xxx_reg_unlock(chip); 6853 return err_sync ? : err_pvt; 6854 } 6855 6856 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6857 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6858 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6859 .setup = mv88e6xxx_setup, 6860 .teardown = mv88e6xxx_teardown, 6861 .port_setup = mv88e6xxx_port_setup, 6862 .port_teardown = mv88e6xxx_port_teardown, 6863 .phylink_get_caps = mv88e6xxx_get_caps, 6864 .phylink_mac_select_pcs = mv88e6xxx_mac_select_pcs, 6865 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 6866 .phylink_mac_config = mv88e6xxx_mac_config, 6867 .phylink_mac_finish = mv88e6xxx_mac_finish, 6868 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6869 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6870 .get_strings = mv88e6xxx_get_strings, 6871 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6872 .get_sset_count = mv88e6xxx_get_sset_count, 6873 .port_max_mtu = mv88e6xxx_get_max_mtu, 6874 .port_change_mtu = mv88e6xxx_change_mtu, 6875 .get_mac_eee = mv88e6xxx_get_mac_eee, 6876 .set_mac_eee = mv88e6xxx_set_mac_eee, 6877 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6878 .get_eeprom = mv88e6xxx_get_eeprom, 6879 .set_eeprom = mv88e6xxx_set_eeprom, 6880 .get_regs_len = mv88e6xxx_get_regs_len, 6881 .get_regs = mv88e6xxx_get_regs, 6882 .get_rxnfc = mv88e6xxx_get_rxnfc, 6883 .set_rxnfc = mv88e6xxx_set_rxnfc, 6884 .set_ageing_time = mv88e6xxx_set_ageing_time, 6885 .port_bridge_join = mv88e6xxx_port_bridge_join, 6886 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6887 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6888 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6889 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6890 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 6891 .port_fast_age = mv88e6xxx_port_fast_age, 6892 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 6893 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6894 .port_vlan_add = mv88e6xxx_port_vlan_add, 6895 .port_vlan_del = mv88e6xxx_port_vlan_del, 6896 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 6897 .port_fdb_add = mv88e6xxx_port_fdb_add, 6898 .port_fdb_del = mv88e6xxx_port_fdb_del, 6899 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6900 .port_mdb_add = mv88e6xxx_port_mdb_add, 6901 .port_mdb_del = mv88e6xxx_port_mdb_del, 6902 .port_mirror_add = mv88e6xxx_port_mirror_add, 6903 .port_mirror_del = mv88e6xxx_port_mirror_del, 6904 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6905 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6906 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6907 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6908 .port_txtstamp = mv88e6xxx_port_txtstamp, 6909 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6910 .get_ts_info = mv88e6xxx_get_ts_info, 6911 .devlink_param_get = mv88e6xxx_devlink_param_get, 6912 .devlink_param_set = mv88e6xxx_devlink_param_set, 6913 .devlink_info_get = mv88e6xxx_devlink_info_get, 6914 .port_lag_change = mv88e6xxx_port_lag_change, 6915 .port_lag_join = mv88e6xxx_port_lag_join, 6916 .port_lag_leave = mv88e6xxx_port_lag_leave, 6917 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6918 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6919 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6920 }; 6921 6922 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6923 { 6924 struct device *dev = chip->dev; 6925 struct dsa_switch *ds; 6926 6927 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6928 if (!ds) 6929 return -ENOMEM; 6930 6931 ds->dev = dev; 6932 ds->num_ports = mv88e6xxx_num_ports(chip); 6933 ds->priv = chip; 6934 ds->dev = dev; 6935 ds->ops = &mv88e6xxx_switch_ops; 6936 ds->ageing_time_min = chip->info->age_time_coeff; 6937 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6938 6939 /* Some chips support up to 32, but that requires enabling the 6940 * 5-bit port mode, which we do not support. 640k^W16 ought to 6941 * be enough for anyone. 6942 */ 6943 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6944 6945 dev_set_drvdata(dev, ds); 6946 6947 return dsa_register_switch(ds); 6948 } 6949 6950 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6951 { 6952 dsa_unregister_switch(chip->ds); 6953 } 6954 6955 static const void *pdata_device_get_match_data(struct device *dev) 6956 { 6957 const struct of_device_id *matches = dev->driver->of_match_table; 6958 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6959 6960 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6961 matches++) { 6962 if (!strcmp(pdata->compatible, matches->compatible)) 6963 return matches->data; 6964 } 6965 return NULL; 6966 } 6967 6968 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6969 * would be lost after a power cycle so prevent it to be suspended. 6970 */ 6971 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6972 { 6973 return -EOPNOTSUPP; 6974 } 6975 6976 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6977 { 6978 return 0; 6979 } 6980 6981 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6982 6983 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6984 { 6985 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6986 const struct mv88e6xxx_info *compat_info = NULL; 6987 struct device *dev = &mdiodev->dev; 6988 struct device_node *np = dev->of_node; 6989 struct mv88e6xxx_chip *chip; 6990 int port; 6991 int err; 6992 6993 if (!np && !pdata) 6994 return -EINVAL; 6995 6996 if (np) 6997 compat_info = of_device_get_match_data(dev); 6998 6999 if (pdata) { 7000 compat_info = pdata_device_get_match_data(dev); 7001 7002 if (!pdata->netdev) 7003 return -EINVAL; 7004 7005 for (port = 0; port < DSA_MAX_PORTS; port++) { 7006 if (!(pdata->enabled_ports & (1 << port))) 7007 continue; 7008 if (strcmp(pdata->cd.port_names[port], "cpu")) 7009 continue; 7010 pdata->cd.netdev[port] = &pdata->netdev->dev; 7011 break; 7012 } 7013 } 7014 7015 if (!compat_info) 7016 return -EINVAL; 7017 7018 chip = mv88e6xxx_alloc_chip(dev); 7019 if (!chip) { 7020 err = -ENOMEM; 7021 goto out; 7022 } 7023 7024 chip->info = compat_info; 7025 7026 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7027 if (IS_ERR(chip->reset)) { 7028 err = PTR_ERR(chip->reset); 7029 goto out; 7030 } 7031 if (chip->reset) 7032 usleep_range(10000, 20000); 7033 7034 /* Detect if the device is configured in single chip addressing mode, 7035 * otherwise continue with address specific smi init/detection. 7036 */ 7037 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7038 if (err) { 7039 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7040 if (err) 7041 goto out; 7042 7043 err = mv88e6xxx_detect(chip); 7044 if (err) 7045 goto out; 7046 } 7047 7048 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7049 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7050 else 7051 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7052 7053 mv88e6xxx_phy_init(chip); 7054 7055 if (chip->info->ops->get_eeprom) { 7056 if (np) 7057 of_property_read_u32(np, "eeprom-length", 7058 &chip->eeprom_len); 7059 else 7060 chip->eeprom_len = pdata->eeprom_len; 7061 } 7062 7063 mv88e6xxx_reg_lock(chip); 7064 err = mv88e6xxx_switch_reset(chip); 7065 mv88e6xxx_reg_unlock(chip); 7066 if (err) 7067 goto out; 7068 7069 if (np) { 7070 chip->irq = of_irq_get(np, 0); 7071 if (chip->irq == -EPROBE_DEFER) { 7072 err = chip->irq; 7073 goto out; 7074 } 7075 } 7076 7077 if (pdata) 7078 chip->irq = pdata->irq; 7079 7080 /* Has to be performed before the MDIO bus is created, because 7081 * the PHYs will link their interrupts to these interrupt 7082 * controllers 7083 */ 7084 mv88e6xxx_reg_lock(chip); 7085 if (chip->irq > 0) 7086 err = mv88e6xxx_g1_irq_setup(chip); 7087 else 7088 err = mv88e6xxx_irq_poll_setup(chip); 7089 mv88e6xxx_reg_unlock(chip); 7090 7091 if (err) 7092 goto out; 7093 7094 if (chip->info->g2_irqs > 0) { 7095 err = mv88e6xxx_g2_irq_setup(chip); 7096 if (err) 7097 goto out_g1_irq; 7098 } 7099 7100 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7101 if (err) 7102 goto out_g2_irq; 7103 7104 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7105 if (err) 7106 goto out_g1_atu_prob_irq; 7107 7108 err = mv88e6xxx_register_switch(chip); 7109 if (err) 7110 goto out_g1_vtu_prob_irq; 7111 7112 return 0; 7113 7114 out_g1_vtu_prob_irq: 7115 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7116 out_g1_atu_prob_irq: 7117 mv88e6xxx_g1_atu_prob_irq_free(chip); 7118 out_g2_irq: 7119 if (chip->info->g2_irqs > 0) 7120 mv88e6xxx_g2_irq_free(chip); 7121 out_g1_irq: 7122 if (chip->irq > 0) 7123 mv88e6xxx_g1_irq_free(chip); 7124 else 7125 mv88e6xxx_irq_poll_free(chip); 7126 out: 7127 if (pdata) 7128 dev_put(pdata->netdev); 7129 7130 return err; 7131 } 7132 7133 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7134 { 7135 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7136 struct mv88e6xxx_chip *chip; 7137 7138 if (!ds) 7139 return; 7140 7141 chip = ds->priv; 7142 7143 if (chip->info->ptp_support) { 7144 mv88e6xxx_hwtstamp_free(chip); 7145 mv88e6xxx_ptp_free(chip); 7146 } 7147 7148 mv88e6xxx_phy_destroy(chip); 7149 mv88e6xxx_unregister_switch(chip); 7150 7151 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7152 mv88e6xxx_g1_atu_prob_irq_free(chip); 7153 7154 if (chip->info->g2_irqs > 0) 7155 mv88e6xxx_g2_irq_free(chip); 7156 7157 if (chip->irq > 0) 7158 mv88e6xxx_g1_irq_free(chip); 7159 else 7160 mv88e6xxx_irq_poll_free(chip); 7161 } 7162 7163 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7164 { 7165 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7166 7167 if (!ds) 7168 return; 7169 7170 dsa_switch_shutdown(ds); 7171 7172 dev_set_drvdata(&mdiodev->dev, NULL); 7173 } 7174 7175 static const struct of_device_id mv88e6xxx_of_match[] = { 7176 { 7177 .compatible = "marvell,mv88e6085", 7178 .data = &mv88e6xxx_table[MV88E6085], 7179 }, 7180 { 7181 .compatible = "marvell,mv88e6190", 7182 .data = &mv88e6xxx_table[MV88E6190], 7183 }, 7184 { 7185 .compatible = "marvell,mv88e6250", 7186 .data = &mv88e6xxx_table[MV88E6250], 7187 }, 7188 { /* sentinel */ }, 7189 }; 7190 7191 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7192 7193 static struct mdio_driver mv88e6xxx_driver = { 7194 .probe = mv88e6xxx_probe, 7195 .remove = mv88e6xxx_remove, 7196 .shutdown = mv88e6xxx_shutdown, 7197 .mdiodrv.driver = { 7198 .name = "mv88e6085", 7199 .of_match_table = mv88e6xxx_of_match, 7200 .pm = &mv88e6xxx_pm_ops, 7201 }, 7202 }; 7203 7204 mdio_module_driver(mv88e6xxx_driver); 7205 7206 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7207 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7208 MODULE_LICENSE("GPL"); 7209