1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 const unsigned long timeout = jiffies + msecs_to_jiffies(50); 90 u16 data; 91 int err; 92 int i; 93 94 /* There's no bus specific operation to wait for a mask. Even 95 * if the initial poll takes longer than 50ms, always do at 96 * least one more attempt. 97 */ 98 for (i = 0; time_before(jiffies, timeout) || (i < 2); i++) { 99 err = mv88e6xxx_read(chip, addr, reg, &data); 100 if (err) 101 return err; 102 103 if ((data & mask) == val) 104 return 0; 105 106 if (i < 2) 107 cpu_relax(); 108 else 109 usleep_range(1000, 2000); 110 } 111 112 dev_err(chip->dev, "Timeout while waiting for switch\n"); 113 return -ETIMEDOUT; 114 } 115 116 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 117 int bit, int val) 118 { 119 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 120 val ? BIT(bit) : 0x0000); 121 } 122 123 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 124 { 125 struct mv88e6xxx_mdio_bus *mdio_bus; 126 127 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 128 list); 129 if (!mdio_bus) 130 return NULL; 131 132 return mdio_bus->bus; 133 } 134 135 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 136 { 137 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 138 unsigned int n = d->hwirq; 139 140 chip->g1_irq.masked |= (1 << n); 141 } 142 143 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 144 { 145 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 146 unsigned int n = d->hwirq; 147 148 chip->g1_irq.masked &= ~(1 << n); 149 } 150 151 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 152 { 153 unsigned int nhandled = 0; 154 unsigned int sub_irq; 155 unsigned int n; 156 u16 reg; 157 u16 ctl1; 158 int err; 159 160 mv88e6xxx_reg_lock(chip); 161 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 162 mv88e6xxx_reg_unlock(chip); 163 164 if (err) 165 goto out; 166 167 do { 168 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 169 if (reg & (1 << n)) { 170 sub_irq = irq_find_mapping(chip->g1_irq.domain, 171 n); 172 handle_nested_irq(sub_irq); 173 ++nhandled; 174 } 175 } 176 177 mv88e6xxx_reg_lock(chip); 178 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 179 if (err) 180 goto unlock; 181 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 182 unlock: 183 mv88e6xxx_reg_unlock(chip); 184 if (err) 185 goto out; 186 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 187 } while (reg & ctl1); 188 189 out: 190 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 191 } 192 193 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 194 { 195 struct mv88e6xxx_chip *chip = dev_id; 196 197 return mv88e6xxx_g1_irq_thread_work(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 204 mv88e6xxx_reg_lock(chip); 205 } 206 207 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 208 { 209 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 210 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 211 u16 reg; 212 int err; 213 214 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 215 if (err) 216 goto out; 217 218 reg &= ~mask; 219 reg |= (~chip->g1_irq.masked & mask); 220 221 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 222 if (err) 223 goto out; 224 225 out: 226 mv88e6xxx_reg_unlock(chip); 227 } 228 229 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 230 .name = "mv88e6xxx-g1", 231 .irq_mask = mv88e6xxx_g1_irq_mask, 232 .irq_unmask = mv88e6xxx_g1_irq_unmask, 233 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 234 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 235 }; 236 237 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 238 unsigned int irq, 239 irq_hw_number_t hwirq) 240 { 241 struct mv88e6xxx_chip *chip = d->host_data; 242 243 irq_set_chip_data(irq, d->host_data); 244 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 245 irq_set_noprobe(irq); 246 247 return 0; 248 } 249 250 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 251 .map = mv88e6xxx_g1_irq_domain_map, 252 .xlate = irq_domain_xlate_twocell, 253 }; 254 255 /* To be called with reg_lock held */ 256 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 257 { 258 int irq, virq; 259 u16 mask; 260 261 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 262 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 263 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 264 265 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 266 virq = irq_find_mapping(chip->g1_irq.domain, irq); 267 irq_dispose_mapping(virq); 268 } 269 270 irq_domain_remove(chip->g1_irq.domain); 271 } 272 273 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 274 { 275 /* 276 * free_irq must be called without reg_lock taken because the irq 277 * handler takes this lock, too. 278 */ 279 free_irq(chip->irq, chip); 280 281 mv88e6xxx_reg_lock(chip); 282 mv88e6xxx_g1_irq_free_common(chip); 283 mv88e6xxx_reg_unlock(chip); 284 } 285 286 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 287 { 288 int err, irq, virq; 289 u16 reg, mask; 290 291 chip->g1_irq.nirqs = chip->info->g1_irqs; 292 chip->g1_irq.domain = irq_domain_add_simple( 293 NULL, chip->g1_irq.nirqs, 0, 294 &mv88e6xxx_g1_irq_domain_ops, chip); 295 if (!chip->g1_irq.domain) 296 return -ENOMEM; 297 298 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 299 irq_create_mapping(chip->g1_irq.domain, irq); 300 301 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 302 chip->g1_irq.masked = ~0; 303 304 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 305 if (err) 306 goto out_mapping; 307 308 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 309 310 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 311 if (err) 312 goto out_disable; 313 314 /* Reading the interrupt status clears (most of) them */ 315 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 316 if (err) 317 goto out_disable; 318 319 return 0; 320 321 out_disable: 322 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 323 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 324 325 out_mapping: 326 for (irq = 0; irq < 16; irq++) { 327 virq = irq_find_mapping(chip->g1_irq.domain, irq); 328 irq_dispose_mapping(virq); 329 } 330 331 irq_domain_remove(chip->g1_irq.domain); 332 333 return err; 334 } 335 336 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 337 { 338 static struct lock_class_key lock_key; 339 static struct lock_class_key request_key; 340 int err; 341 342 err = mv88e6xxx_g1_irq_setup_common(chip); 343 if (err) 344 return err; 345 346 /* These lock classes tells lockdep that global 1 irqs are in 347 * a different category than their parent GPIO, so it won't 348 * report false recursion. 349 */ 350 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 351 352 snprintf(chip->irq_name, sizeof(chip->irq_name), 353 "mv88e6xxx-%s", dev_name(chip->dev)); 354 355 mv88e6xxx_reg_unlock(chip); 356 err = request_threaded_irq(chip->irq, NULL, 357 mv88e6xxx_g1_irq_thread_fn, 358 IRQF_ONESHOT | IRQF_SHARED, 359 chip->irq_name, chip); 360 mv88e6xxx_reg_lock(chip); 361 if (err) 362 mv88e6xxx_g1_irq_free_common(chip); 363 364 return err; 365 } 366 367 static void mv88e6xxx_irq_poll(struct kthread_work *work) 368 { 369 struct mv88e6xxx_chip *chip = container_of(work, 370 struct mv88e6xxx_chip, 371 irq_poll_work.work); 372 mv88e6xxx_g1_irq_thread_work(chip); 373 374 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 375 msecs_to_jiffies(100)); 376 } 377 378 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 379 { 380 int err; 381 382 err = mv88e6xxx_g1_irq_setup_common(chip); 383 if (err) 384 return err; 385 386 kthread_init_delayed_work(&chip->irq_poll_work, 387 mv88e6xxx_irq_poll); 388 389 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 390 if (IS_ERR(chip->kworker)) 391 return PTR_ERR(chip->kworker); 392 393 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 394 msecs_to_jiffies(100)); 395 396 return 0; 397 } 398 399 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 400 { 401 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 402 kthread_destroy_worker(chip->kworker); 403 404 mv88e6xxx_reg_lock(chip); 405 mv88e6xxx_g1_irq_free_common(chip); 406 mv88e6xxx_reg_unlock(chip); 407 } 408 409 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 410 int port, phy_interface_t interface) 411 { 412 int err; 413 414 if (chip->info->ops->port_set_rgmii_delay) { 415 err = chip->info->ops->port_set_rgmii_delay(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 if (chip->info->ops->port_set_cmode) { 422 err = chip->info->ops->port_set_cmode(chip, port, 423 interface); 424 if (err && err != -EOPNOTSUPP) 425 return err; 426 } 427 428 return 0; 429 } 430 431 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 432 int link, int speed, int duplex, int pause, 433 phy_interface_t mode) 434 { 435 int err; 436 437 if (!chip->info->ops->port_set_link) 438 return 0; 439 440 /* Port's MAC control must not be changed unless the link is down */ 441 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 442 if (err) 443 return err; 444 445 if (chip->info->ops->port_set_speed_duplex) { 446 err = chip->info->ops->port_set_speed_duplex(chip, port, 447 speed, duplex); 448 if (err && err != -EOPNOTSUPP) 449 goto restore_link; 450 } 451 452 if (chip->info->ops->port_set_pause) { 453 err = chip->info->ops->port_set_pause(chip, port, pause); 454 if (err) 455 goto restore_link; 456 } 457 458 err = mv88e6xxx_port_config_interface(chip, port, mode); 459 restore_link: 460 if (chip->info->ops->port_set_link(chip, port, link)) 461 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 462 463 return err; 464 } 465 466 static int mv88e6xxx_phy_is_internal(struct mv88e6xxx_chip *chip, int port) 467 { 468 return port >= chip->info->internal_phys_offset && 469 port < chip->info->num_internal_phys + 470 chip->info->internal_phys_offset; 471 } 472 473 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 474 { 475 u16 reg; 476 int err; 477 478 /* The 88e6250 family does not have the PHY detect bit. Instead, 479 * report whether the port is internal. 480 */ 481 if (chip->info->family == MV88E6XXX_FAMILY_6250) 482 return mv88e6xxx_phy_is_internal(chip, port); 483 484 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 485 if (err) { 486 dev_err(chip->dev, 487 "p%d: %s: failed to read port status\n", 488 port, __func__); 489 return err; 490 } 491 492 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 493 } 494 495 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 496 struct phylink_link_state *state) 497 { 498 struct mv88e6xxx_chip *chip = ds->priv; 499 int lane; 500 int err; 501 502 mv88e6xxx_reg_lock(chip); 503 lane = mv88e6xxx_serdes_get_lane(chip, port); 504 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 505 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 506 state); 507 else 508 err = -EOPNOTSUPP; 509 mv88e6xxx_reg_unlock(chip); 510 511 return err; 512 } 513 514 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 515 unsigned int mode, 516 phy_interface_t interface, 517 const unsigned long *advertise) 518 { 519 const struct mv88e6xxx_ops *ops = chip->info->ops; 520 int lane; 521 522 if (ops->serdes_pcs_config) { 523 lane = mv88e6xxx_serdes_get_lane(chip, port); 524 if (lane >= 0) 525 return ops->serdes_pcs_config(chip, port, lane, mode, 526 interface, advertise); 527 } 528 529 return 0; 530 } 531 532 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 533 { 534 struct mv88e6xxx_chip *chip = ds->priv; 535 const struct mv88e6xxx_ops *ops; 536 int err = 0; 537 int lane; 538 539 ops = chip->info->ops; 540 541 if (ops->serdes_pcs_an_restart) { 542 mv88e6xxx_reg_lock(chip); 543 lane = mv88e6xxx_serdes_get_lane(chip, port); 544 if (lane >= 0) 545 err = ops->serdes_pcs_an_restart(chip, port, lane); 546 mv88e6xxx_reg_unlock(chip); 547 548 if (err) 549 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 550 } 551 } 552 553 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 554 unsigned int mode, 555 int speed, int duplex) 556 { 557 const struct mv88e6xxx_ops *ops = chip->info->ops; 558 int lane; 559 560 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 561 lane = mv88e6xxx_serdes_get_lane(chip, port); 562 if (lane >= 0) 563 return ops->serdes_pcs_link_up(chip, port, lane, 564 speed, duplex); 565 } 566 567 return 0; 568 } 569 570 static const u8 mv88e6185_phy_interface_modes[] = { 571 [MV88E6185_PORT_STS_CMODE_GMII_FD] = PHY_INTERFACE_MODE_GMII, 572 [MV88E6185_PORT_STS_CMODE_MII_100_FD_PS] = PHY_INTERFACE_MODE_MII, 573 [MV88E6185_PORT_STS_CMODE_MII_100] = PHY_INTERFACE_MODE_MII, 574 [MV88E6185_PORT_STS_CMODE_MII_10] = PHY_INTERFACE_MODE_MII, 575 [MV88E6185_PORT_STS_CMODE_SERDES] = PHY_INTERFACE_MODE_1000BASEX, 576 [MV88E6185_PORT_STS_CMODE_1000BASE_X] = PHY_INTERFACE_MODE_1000BASEX, 577 [MV88E6185_PORT_STS_CMODE_PHY] = PHY_INTERFACE_MODE_SGMII, 578 }; 579 580 static void mv88e6095_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 581 struct phylink_config *config) 582 { 583 u8 cmode = chip->ports[port].cmode; 584 585 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 586 587 if (mv88e6xxx_phy_is_internal(chip, port)) { 588 __set_bit(PHY_INTERFACE_MODE_MII, config->supported_interfaces); 589 } else { 590 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 591 mv88e6185_phy_interface_modes[cmode]) 592 __set_bit(mv88e6185_phy_interface_modes[cmode], 593 config->supported_interfaces); 594 595 config->mac_capabilities |= MAC_1000FD; 596 } 597 } 598 599 static void mv88e6185_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 600 struct phylink_config *config) 601 { 602 u8 cmode = chip->ports[port].cmode; 603 604 if (cmode < ARRAY_SIZE(mv88e6185_phy_interface_modes) && 605 mv88e6185_phy_interface_modes[cmode]) 606 __set_bit(mv88e6185_phy_interface_modes[cmode], 607 config->supported_interfaces); 608 609 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 610 MAC_1000FD; 611 } 612 613 static const u8 mv88e6xxx_phy_interface_modes[] = { 614 [MV88E6XXX_PORT_STS_CMODE_MII_PHY] = PHY_INTERFACE_MODE_REVMII, 615 [MV88E6XXX_PORT_STS_CMODE_MII] = PHY_INTERFACE_MODE_MII, 616 [MV88E6XXX_PORT_STS_CMODE_GMII] = PHY_INTERFACE_MODE_GMII, 617 [MV88E6XXX_PORT_STS_CMODE_RMII_PHY] = PHY_INTERFACE_MODE_REVRMII, 618 [MV88E6XXX_PORT_STS_CMODE_RMII] = PHY_INTERFACE_MODE_RMII, 619 [MV88E6XXX_PORT_STS_CMODE_100BASEX] = PHY_INTERFACE_MODE_100BASEX, 620 [MV88E6XXX_PORT_STS_CMODE_1000BASEX] = PHY_INTERFACE_MODE_1000BASEX, 621 [MV88E6XXX_PORT_STS_CMODE_SGMII] = PHY_INTERFACE_MODE_SGMII, 622 /* higher interface modes are not needed here, since ports supporting 623 * them are writable, and so the supported interfaces are filled in the 624 * corresponding .phylink_set_interfaces() implementation below 625 */ 626 }; 627 628 static void mv88e6xxx_translate_cmode(u8 cmode, unsigned long *supported) 629 { 630 if (cmode < ARRAY_SIZE(mv88e6xxx_phy_interface_modes) && 631 mv88e6xxx_phy_interface_modes[cmode]) 632 __set_bit(mv88e6xxx_phy_interface_modes[cmode], supported); 633 else if (cmode == MV88E6XXX_PORT_STS_CMODE_RGMII) 634 phy_interface_set_rgmii(supported); 635 } 636 637 static void mv88e6250_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 638 struct phylink_config *config) 639 { 640 unsigned long *supported = config->supported_interfaces; 641 642 /* Translate the default cmode */ 643 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 644 645 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100; 646 } 647 648 static int mv88e6352_get_port4_serdes_cmode(struct mv88e6xxx_chip *chip) 649 { 650 u16 reg, val; 651 int err; 652 653 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, ®); 654 if (err) 655 return err; 656 657 /* If PHY_DETECT is zero, then we are not in auto-media mode */ 658 if (!(reg & MV88E6XXX_PORT_STS_PHY_DETECT)) 659 return 0xf; 660 661 val = reg & ~MV88E6XXX_PORT_STS_PHY_DETECT; 662 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, val); 663 if (err) 664 return err; 665 666 err = mv88e6xxx_port_read(chip, 4, MV88E6XXX_PORT_STS, &val); 667 if (err) 668 return err; 669 670 /* Restore PHY_DETECT value */ 671 err = mv88e6xxx_port_write(chip, 4, MV88E6XXX_PORT_STS, reg); 672 if (err) 673 return err; 674 675 return val & MV88E6XXX_PORT_STS_CMODE_MASK; 676 } 677 678 static void mv88e6352_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 679 struct phylink_config *config) 680 { 681 unsigned long *supported = config->supported_interfaces; 682 int err, cmode; 683 684 /* Translate the default cmode */ 685 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 686 687 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 688 MAC_1000FD; 689 690 /* Port 4 supports automedia if the serdes is associated with it. */ 691 if (port == 4) { 692 err = mv88e6352_g2_scratch_port_has_serdes(chip, port); 693 if (err < 0) 694 dev_err(chip->dev, "p%d: failed to read scratch\n", 695 port); 696 if (err <= 0) 697 return; 698 699 cmode = mv88e6352_get_port4_serdes_cmode(chip); 700 if (cmode < 0) 701 dev_err(chip->dev, "p%d: failed to read serdes cmode\n", 702 port); 703 else 704 mv88e6xxx_translate_cmode(cmode, supported); 705 } 706 } 707 708 static void mv88e6341_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 709 struct phylink_config *config) 710 { 711 unsigned long *supported = config->supported_interfaces; 712 713 /* Translate the default cmode */ 714 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 715 716 /* No ethtool bits for 200Mbps */ 717 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 718 MAC_1000FD; 719 720 /* The C_Mode field is programmable on port 5 */ 721 if (port == 5) { 722 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 723 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 724 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 725 726 config->mac_capabilities |= MAC_2500FD; 727 } 728 } 729 730 static void mv88e6390_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 731 struct phylink_config *config) 732 { 733 unsigned long *supported = config->supported_interfaces; 734 735 /* Translate the default cmode */ 736 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 737 738 /* No ethtool bits for 200Mbps */ 739 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 740 MAC_1000FD; 741 742 /* The C_Mode field is programmable on ports 9 and 10 */ 743 if (port == 9 || port == 10) { 744 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 745 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 746 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 747 748 config->mac_capabilities |= MAC_2500FD; 749 } 750 } 751 752 static void mv88e6390x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 753 struct phylink_config *config) 754 { 755 unsigned long *supported = config->supported_interfaces; 756 757 mv88e6390_phylink_get_caps(chip, port, config); 758 759 /* For the 6x90X, ports 2-7 can be in automedia mode. 760 * (Note that 6x90 doesn't support RXAUI nor XAUI). 761 * 762 * Port 2 can also support 1000BASE-X in automedia mode if port 9 is 763 * configured for 1000BASE-X, SGMII or 2500BASE-X. 764 * Port 3-4 can also support 1000BASE-X in automedia mode if port 9 is 765 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 766 * 767 * Port 5 can also support 1000BASE-X in automedia mode if port 10 is 768 * configured for 1000BASE-X, SGMII or 2500BASE-X. 769 * Port 6-7 can also support 1000BASE-X in automedia mode if port 10 is 770 * configured for RXAUI, 1000BASE-X, SGMII or 2500BASE-X. 771 * 772 * For now, be permissive (as the old code was) and allow 1000BASE-X 773 * on ports 2..7. 774 */ 775 if (port >= 2 && port <= 7) 776 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 777 778 /* The C_Mode field can also be programmed for 10G speeds */ 779 if (port == 9 || port == 10) { 780 __set_bit(PHY_INTERFACE_MODE_XAUI, supported); 781 __set_bit(PHY_INTERFACE_MODE_RXAUI, supported); 782 783 config->mac_capabilities |= MAC_10000FD; 784 } 785 } 786 787 static void mv88e6393x_phylink_get_caps(struct mv88e6xxx_chip *chip, int port, 788 struct phylink_config *config) 789 { 790 unsigned long *supported = config->supported_interfaces; 791 bool is_6191x = 792 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 793 bool is_6361 = 794 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6361; 795 796 mv88e6xxx_translate_cmode(chip->ports[port].cmode, supported); 797 798 config->mac_capabilities = MAC_SYM_PAUSE | MAC_10 | MAC_100 | 799 MAC_1000FD; 800 801 /* The C_Mode field can be programmed for ports 0, 9 and 10 */ 802 if (port == 0 || port == 9 || port == 10) { 803 __set_bit(PHY_INTERFACE_MODE_SGMII, supported); 804 __set_bit(PHY_INTERFACE_MODE_1000BASEX, supported); 805 806 /* 6191X supports >1G modes only on port 10 */ 807 if (!is_6191x || port == 10) { 808 __set_bit(PHY_INTERFACE_MODE_2500BASEX, supported); 809 config->mac_capabilities |= MAC_2500FD; 810 811 /* 6361 only supports up to 2500BaseX */ 812 if (!is_6361) { 813 __set_bit(PHY_INTERFACE_MODE_5GBASER, supported); 814 __set_bit(PHY_INTERFACE_MODE_10GBASER, supported); 815 __set_bit(PHY_INTERFACE_MODE_USXGMII, supported); 816 config->mac_capabilities |= MAC_5000FD | 817 MAC_10000FD; 818 } 819 } 820 } 821 822 if (port == 0) { 823 __set_bit(PHY_INTERFACE_MODE_RMII, supported); 824 __set_bit(PHY_INTERFACE_MODE_RGMII, supported); 825 __set_bit(PHY_INTERFACE_MODE_RGMII_ID, supported); 826 __set_bit(PHY_INTERFACE_MODE_RGMII_RXID, supported); 827 __set_bit(PHY_INTERFACE_MODE_RGMII_TXID, supported); 828 } 829 } 830 831 static void mv88e6xxx_get_caps(struct dsa_switch *ds, int port, 832 struct phylink_config *config) 833 { 834 struct mv88e6xxx_chip *chip = ds->priv; 835 836 mv88e6xxx_reg_lock(chip); 837 chip->info->ops->phylink_get_caps(chip, port, config); 838 mv88e6xxx_reg_unlock(chip); 839 840 if (mv88e6xxx_phy_is_internal(chip, port)) { 841 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 842 config->supported_interfaces); 843 /* Internal ports with no phy-mode need GMII for PHYLIB */ 844 __set_bit(PHY_INTERFACE_MODE_GMII, 845 config->supported_interfaces); 846 } 847 } 848 849 static int mv88e6xxx_mac_prepare(struct dsa_switch *ds, int port, 850 unsigned int mode, phy_interface_t interface) 851 { 852 struct mv88e6xxx_chip *chip = ds->priv; 853 int err = 0; 854 855 /* In inband mode, the link may come up at any time while the link 856 * is not forced down. Force the link down while we reconfigure the 857 * interface mode. 858 */ 859 if (mode == MLO_AN_INBAND && 860 chip->ports[port].interface != interface && 861 chip->info->ops->port_set_link) { 862 mv88e6xxx_reg_lock(chip); 863 err = chip->info->ops->port_set_link(chip, port, 864 LINK_FORCED_DOWN); 865 mv88e6xxx_reg_unlock(chip); 866 } 867 868 return err; 869 } 870 871 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 872 unsigned int mode, 873 const struct phylink_link_state *state) 874 { 875 struct mv88e6xxx_chip *chip = ds->priv; 876 int err = 0; 877 878 mv88e6xxx_reg_lock(chip); 879 880 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(chip, port)) { 881 err = mv88e6xxx_port_config_interface(chip, port, 882 state->interface); 883 if (err && err != -EOPNOTSUPP) 884 goto err_unlock; 885 886 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 887 state->interface, 888 state->advertising); 889 /* FIXME: we should restart negotiation if something changed - 890 * which is something we get if we convert to using phylinks 891 * PCS operations. 892 */ 893 if (err > 0) 894 err = 0; 895 } 896 897 err_unlock: 898 mv88e6xxx_reg_unlock(chip); 899 900 if (err && err != -EOPNOTSUPP) 901 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 902 } 903 904 static int mv88e6xxx_mac_finish(struct dsa_switch *ds, int port, 905 unsigned int mode, phy_interface_t interface) 906 { 907 struct mv88e6xxx_chip *chip = ds->priv; 908 int err = 0; 909 910 /* Undo the forced down state above after completing configuration 911 * irrespective of its state on entry, which allows the link to come 912 * up in the in-band case where there is no separate SERDES. Also 913 * ensure that the link can come up if the PPU is in use and we are 914 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 915 */ 916 mv88e6xxx_reg_lock(chip); 917 918 if (chip->info->ops->port_set_link && 919 ((mode == MLO_AN_INBAND && 920 chip->ports[port].interface != interface) || 921 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 922 err = chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 923 924 mv88e6xxx_reg_unlock(chip); 925 926 chip->ports[port].interface = interface; 927 928 return err; 929 } 930 931 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 932 unsigned int mode, 933 phy_interface_t interface) 934 { 935 struct mv88e6xxx_chip *chip = ds->priv; 936 const struct mv88e6xxx_ops *ops; 937 int err = 0; 938 939 ops = chip->info->ops; 940 941 mv88e6xxx_reg_lock(chip); 942 /* Force the link down if we know the port may not be automatically 943 * updated by the switch or if we are using fixed-link mode. 944 */ 945 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 946 mode == MLO_AN_FIXED) && ops->port_sync_link) 947 err = ops->port_sync_link(chip, port, mode, false); 948 949 if (!err && ops->port_set_speed_duplex) 950 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 951 DUPLEX_UNFORCED); 952 mv88e6xxx_reg_unlock(chip); 953 954 if (err) 955 dev_err(chip->dev, 956 "p%d: failed to force MAC link down\n", port); 957 } 958 959 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 960 unsigned int mode, phy_interface_t interface, 961 struct phy_device *phydev, 962 int speed, int duplex, 963 bool tx_pause, bool rx_pause) 964 { 965 struct mv88e6xxx_chip *chip = ds->priv; 966 const struct mv88e6xxx_ops *ops; 967 int err = 0; 968 969 ops = chip->info->ops; 970 971 mv88e6xxx_reg_lock(chip); 972 /* Configure and force the link up if we know that the port may not 973 * automatically updated by the switch or if we are using fixed-link 974 * mode. 975 */ 976 if (!mv88e6xxx_port_ppu_updates(chip, port) || 977 mode == MLO_AN_FIXED) { 978 /* FIXME: for an automedia port, should we force the link 979 * down here - what if the link comes up due to "other" media 980 * while we're bringing the port up, how is the exclusivity 981 * handled in the Marvell hardware? E.g. port 2 on 88E6390 982 * shared between internal PHY and Serdes. 983 */ 984 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 985 duplex); 986 if (err) 987 goto error; 988 989 if (ops->port_set_speed_duplex) { 990 err = ops->port_set_speed_duplex(chip, port, 991 speed, duplex); 992 if (err && err != -EOPNOTSUPP) 993 goto error; 994 } 995 996 if (ops->port_sync_link) 997 err = ops->port_sync_link(chip, port, mode, true); 998 } 999 error: 1000 mv88e6xxx_reg_unlock(chip); 1001 1002 if (err && err != -EOPNOTSUPP) 1003 dev_err(ds->dev, 1004 "p%d: failed to configure MAC link up\n", port); 1005 } 1006 1007 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 1008 { 1009 if (!chip->info->ops->stats_snapshot) 1010 return -EOPNOTSUPP; 1011 1012 return chip->info->ops->stats_snapshot(chip, port); 1013 } 1014 1015 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 1016 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 1017 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 1018 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 1019 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 1020 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 1021 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 1022 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 1023 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 1024 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 1025 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 1026 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 1027 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 1028 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 1029 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 1030 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 1031 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 1032 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 1033 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 1034 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 1035 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 1036 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 1037 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 1038 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 1039 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 1040 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 1041 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 1042 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 1043 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 1044 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 1045 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 1046 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 1047 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 1048 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 1049 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 1050 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 1051 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 1052 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 1053 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 1054 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 1055 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 1056 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 1057 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 1058 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 1059 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 1060 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 1061 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 1062 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 1063 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 1064 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 1065 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 1066 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 1067 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 1068 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 1069 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 1070 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 1071 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 1072 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 1073 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 1074 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 1075 }; 1076 1077 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 1078 struct mv88e6xxx_hw_stat *s, 1079 int port, u16 bank1_select, 1080 u16 histogram) 1081 { 1082 u32 low; 1083 u32 high = 0; 1084 u16 reg = 0; 1085 int err; 1086 u64 value; 1087 1088 switch (s->type) { 1089 case STATS_TYPE_PORT: 1090 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 1091 if (err) 1092 return U64_MAX; 1093 1094 low = reg; 1095 if (s->size == 4) { 1096 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 1097 if (err) 1098 return U64_MAX; 1099 low |= ((u32)reg) << 16; 1100 } 1101 break; 1102 case STATS_TYPE_BANK1: 1103 reg = bank1_select; 1104 fallthrough; 1105 case STATS_TYPE_BANK0: 1106 reg |= s->reg | histogram; 1107 mv88e6xxx_g1_stats_read(chip, reg, &low); 1108 if (s->size == 8) 1109 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 1110 break; 1111 default: 1112 return U64_MAX; 1113 } 1114 value = (((u64)high) << 32) | low; 1115 return value; 1116 } 1117 1118 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 1119 uint8_t *data, int types) 1120 { 1121 struct mv88e6xxx_hw_stat *stat; 1122 int i, j; 1123 1124 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1125 stat = &mv88e6xxx_hw_stats[i]; 1126 if (stat->type & types) { 1127 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 1128 ETH_GSTRING_LEN); 1129 j++; 1130 } 1131 } 1132 1133 return j; 1134 } 1135 1136 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 1137 uint8_t *data) 1138 { 1139 return mv88e6xxx_stats_get_strings(chip, data, 1140 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 1141 } 1142 1143 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 1144 uint8_t *data) 1145 { 1146 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 1147 } 1148 1149 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 1150 uint8_t *data) 1151 { 1152 return mv88e6xxx_stats_get_strings(chip, data, 1153 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 1154 } 1155 1156 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 1157 "atu_member_violation", 1158 "atu_miss_violation", 1159 "atu_full_violation", 1160 "vtu_member_violation", 1161 "vtu_miss_violation", 1162 }; 1163 1164 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 1165 { 1166 unsigned int i; 1167 1168 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 1169 strscpy(data + i * ETH_GSTRING_LEN, 1170 mv88e6xxx_atu_vtu_stats_strings[i], 1171 ETH_GSTRING_LEN); 1172 } 1173 1174 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 1175 u32 stringset, uint8_t *data) 1176 { 1177 struct mv88e6xxx_chip *chip = ds->priv; 1178 int count = 0; 1179 1180 if (stringset != ETH_SS_STATS) 1181 return; 1182 1183 mv88e6xxx_reg_lock(chip); 1184 1185 if (chip->info->ops->stats_get_strings) 1186 count = chip->info->ops->stats_get_strings(chip, data); 1187 1188 if (chip->info->ops->serdes_get_strings) { 1189 data += count * ETH_GSTRING_LEN; 1190 count = chip->info->ops->serdes_get_strings(chip, port, data); 1191 } 1192 1193 data += count * ETH_GSTRING_LEN; 1194 mv88e6xxx_atu_vtu_get_strings(data); 1195 1196 mv88e6xxx_reg_unlock(chip); 1197 } 1198 1199 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1200 int types) 1201 { 1202 struct mv88e6xxx_hw_stat *stat; 1203 int i, j; 1204 1205 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1206 stat = &mv88e6xxx_hw_stats[i]; 1207 if (stat->type & types) 1208 j++; 1209 } 1210 return j; 1211 } 1212 1213 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1214 { 1215 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1216 STATS_TYPE_PORT); 1217 } 1218 1219 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1220 { 1221 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1222 } 1223 1224 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1225 { 1226 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1227 STATS_TYPE_BANK1); 1228 } 1229 1230 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1231 { 1232 struct mv88e6xxx_chip *chip = ds->priv; 1233 int serdes_count = 0; 1234 int count = 0; 1235 1236 if (sset != ETH_SS_STATS) 1237 return 0; 1238 1239 mv88e6xxx_reg_lock(chip); 1240 if (chip->info->ops->stats_get_sset_count) 1241 count = chip->info->ops->stats_get_sset_count(chip); 1242 if (count < 0) 1243 goto out; 1244 1245 if (chip->info->ops->serdes_get_sset_count) 1246 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1247 port); 1248 if (serdes_count < 0) { 1249 count = serdes_count; 1250 goto out; 1251 } 1252 count += serdes_count; 1253 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1254 1255 out: 1256 mv88e6xxx_reg_unlock(chip); 1257 1258 return count; 1259 } 1260 1261 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1262 uint64_t *data, int types, 1263 u16 bank1_select, u16 histogram) 1264 { 1265 struct mv88e6xxx_hw_stat *stat; 1266 int i, j; 1267 1268 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1269 stat = &mv88e6xxx_hw_stats[i]; 1270 if (stat->type & types) { 1271 mv88e6xxx_reg_lock(chip); 1272 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1273 bank1_select, 1274 histogram); 1275 mv88e6xxx_reg_unlock(chip); 1276 1277 j++; 1278 } 1279 } 1280 return j; 1281 } 1282 1283 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1284 uint64_t *data) 1285 { 1286 return mv88e6xxx_stats_get_stats(chip, port, data, 1287 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1288 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1289 } 1290 1291 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1292 uint64_t *data) 1293 { 1294 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1295 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1296 } 1297 1298 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1299 uint64_t *data) 1300 { 1301 return mv88e6xxx_stats_get_stats(chip, port, data, 1302 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1303 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1304 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1305 } 1306 1307 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1308 uint64_t *data) 1309 { 1310 return mv88e6xxx_stats_get_stats(chip, port, data, 1311 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1312 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1313 0); 1314 } 1315 1316 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1317 uint64_t *data) 1318 { 1319 *data++ = chip->ports[port].atu_member_violation; 1320 *data++ = chip->ports[port].atu_miss_violation; 1321 *data++ = chip->ports[port].atu_full_violation; 1322 *data++ = chip->ports[port].vtu_member_violation; 1323 *data++ = chip->ports[port].vtu_miss_violation; 1324 } 1325 1326 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1327 uint64_t *data) 1328 { 1329 int count = 0; 1330 1331 if (chip->info->ops->stats_get_stats) 1332 count = chip->info->ops->stats_get_stats(chip, port, data); 1333 1334 mv88e6xxx_reg_lock(chip); 1335 if (chip->info->ops->serdes_get_stats) { 1336 data += count; 1337 count = chip->info->ops->serdes_get_stats(chip, port, data); 1338 } 1339 data += count; 1340 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1341 mv88e6xxx_reg_unlock(chip); 1342 } 1343 1344 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1345 uint64_t *data) 1346 { 1347 struct mv88e6xxx_chip *chip = ds->priv; 1348 int ret; 1349 1350 mv88e6xxx_reg_lock(chip); 1351 1352 ret = mv88e6xxx_stats_snapshot(chip, port); 1353 mv88e6xxx_reg_unlock(chip); 1354 1355 if (ret < 0) 1356 return; 1357 1358 mv88e6xxx_get_stats(chip, port, data); 1359 1360 } 1361 1362 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1363 { 1364 struct mv88e6xxx_chip *chip = ds->priv; 1365 int len; 1366 1367 len = 32 * sizeof(u16); 1368 if (chip->info->ops->serdes_get_regs_len) 1369 len += chip->info->ops->serdes_get_regs_len(chip, port); 1370 1371 return len; 1372 } 1373 1374 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1375 struct ethtool_regs *regs, void *_p) 1376 { 1377 struct mv88e6xxx_chip *chip = ds->priv; 1378 int err; 1379 u16 reg; 1380 u16 *p = _p; 1381 int i; 1382 1383 regs->version = chip->info->prod_num; 1384 1385 memset(p, 0xff, 32 * sizeof(u16)); 1386 1387 mv88e6xxx_reg_lock(chip); 1388 1389 for (i = 0; i < 32; i++) { 1390 1391 err = mv88e6xxx_port_read(chip, port, i, ®); 1392 if (!err) 1393 p[i] = reg; 1394 } 1395 1396 if (chip->info->ops->serdes_get_regs) 1397 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1398 1399 mv88e6xxx_reg_unlock(chip); 1400 } 1401 1402 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1403 struct ethtool_eee *e) 1404 { 1405 /* Nothing to do on the port's MAC */ 1406 return 0; 1407 } 1408 1409 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1410 struct ethtool_eee *e) 1411 { 1412 /* Nothing to do on the port's MAC */ 1413 return 0; 1414 } 1415 1416 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1417 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1418 { 1419 struct dsa_switch *ds = chip->ds; 1420 struct dsa_switch_tree *dst = ds->dst; 1421 struct dsa_port *dp, *other_dp; 1422 bool found = false; 1423 u16 pvlan; 1424 1425 /* dev is a physical switch */ 1426 if (dev <= dst->last_switch) { 1427 list_for_each_entry(dp, &dst->ports, list) { 1428 if (dp->ds->index == dev && dp->index == port) { 1429 /* dp might be a DSA link or a user port, so it 1430 * might or might not have a bridge. 1431 * Use the "found" variable for both cases. 1432 */ 1433 found = true; 1434 break; 1435 } 1436 } 1437 /* dev is a virtual bridge */ 1438 } else { 1439 list_for_each_entry(dp, &dst->ports, list) { 1440 unsigned int bridge_num = dsa_port_bridge_num_get(dp); 1441 1442 if (!bridge_num) 1443 continue; 1444 1445 if (bridge_num + dst->last_switch != dev) 1446 continue; 1447 1448 found = true; 1449 break; 1450 } 1451 } 1452 1453 /* Prevent frames from unknown switch or virtual bridge */ 1454 if (!found) 1455 return 0; 1456 1457 /* Frames from DSA links and CPU ports can egress any local port */ 1458 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1459 return mv88e6xxx_port_mask(chip); 1460 1461 pvlan = 0; 1462 1463 /* Frames from standalone user ports can only egress on the 1464 * upstream port. 1465 */ 1466 if (!dsa_port_bridge_dev_get(dp)) 1467 return BIT(dsa_switch_upstream_port(ds)); 1468 1469 /* Frames from bridged user ports can egress any local DSA 1470 * links and CPU ports, as well as any local member of their 1471 * bridge group. 1472 */ 1473 dsa_switch_for_each_port(other_dp, ds) 1474 if (other_dp->type == DSA_PORT_TYPE_CPU || 1475 other_dp->type == DSA_PORT_TYPE_DSA || 1476 dsa_port_bridge_same(dp, other_dp)) 1477 pvlan |= BIT(other_dp->index); 1478 1479 return pvlan; 1480 } 1481 1482 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1483 { 1484 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1485 1486 /* prevent frames from going back out of the port they came in on */ 1487 output_ports &= ~BIT(port); 1488 1489 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1490 } 1491 1492 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1493 u8 state) 1494 { 1495 struct mv88e6xxx_chip *chip = ds->priv; 1496 int err; 1497 1498 mv88e6xxx_reg_lock(chip); 1499 err = mv88e6xxx_port_set_state(chip, port, state); 1500 mv88e6xxx_reg_unlock(chip); 1501 1502 if (err) 1503 dev_err(ds->dev, "p%d: failed to update state\n", port); 1504 } 1505 1506 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1507 { 1508 int err; 1509 1510 if (chip->info->ops->ieee_pri_map) { 1511 err = chip->info->ops->ieee_pri_map(chip); 1512 if (err) 1513 return err; 1514 } 1515 1516 if (chip->info->ops->ip_pri_map) { 1517 err = chip->info->ops->ip_pri_map(chip); 1518 if (err) 1519 return err; 1520 } 1521 1522 return 0; 1523 } 1524 1525 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1526 { 1527 struct dsa_switch *ds = chip->ds; 1528 int target, port; 1529 int err; 1530 1531 if (!chip->info->global2_addr) 1532 return 0; 1533 1534 /* Initialize the routing port to the 32 possible target devices */ 1535 for (target = 0; target < 32; target++) { 1536 port = dsa_routing_port(ds, target); 1537 if (port == ds->num_ports) 1538 port = 0x1f; 1539 1540 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1541 if (err) 1542 return err; 1543 } 1544 1545 if (chip->info->ops->set_cascade_port) { 1546 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1547 err = chip->info->ops->set_cascade_port(chip, port); 1548 if (err) 1549 return err; 1550 } 1551 1552 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1553 if (err) 1554 return err; 1555 1556 return 0; 1557 } 1558 1559 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1560 { 1561 /* Clear all trunk masks and mapping */ 1562 if (chip->info->global2_addr) 1563 return mv88e6xxx_g2_trunk_clear(chip); 1564 1565 return 0; 1566 } 1567 1568 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1569 { 1570 if (chip->info->ops->rmu_disable) 1571 return chip->info->ops->rmu_disable(chip); 1572 1573 return 0; 1574 } 1575 1576 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1577 { 1578 if (chip->info->ops->pot_clear) 1579 return chip->info->ops->pot_clear(chip); 1580 1581 return 0; 1582 } 1583 1584 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1585 { 1586 if (chip->info->ops->mgmt_rsvd2cpu) 1587 return chip->info->ops->mgmt_rsvd2cpu(chip); 1588 1589 return 0; 1590 } 1591 1592 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1593 { 1594 int err; 1595 1596 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1597 if (err) 1598 return err; 1599 1600 /* The chips that have a "learn2all" bit in Global1, ATU 1601 * Control are precisely those whose port registers have a 1602 * Message Port bit in Port Control 1 and hence implement 1603 * ->port_setup_message_port. 1604 */ 1605 if (chip->info->ops->port_setup_message_port) { 1606 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1607 if (err) 1608 return err; 1609 } 1610 1611 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1612 } 1613 1614 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1615 { 1616 int port; 1617 int err; 1618 1619 if (!chip->info->ops->irl_init_all) 1620 return 0; 1621 1622 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1623 /* Disable ingress rate limiting by resetting all per port 1624 * ingress rate limit resources to their initial state. 1625 */ 1626 err = chip->info->ops->irl_init_all(chip, port); 1627 if (err) 1628 return err; 1629 } 1630 1631 return 0; 1632 } 1633 1634 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1635 { 1636 if (chip->info->ops->set_switch_mac) { 1637 u8 addr[ETH_ALEN]; 1638 1639 eth_random_addr(addr); 1640 1641 return chip->info->ops->set_switch_mac(chip, addr); 1642 } 1643 1644 return 0; 1645 } 1646 1647 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1648 { 1649 struct dsa_switch_tree *dst = chip->ds->dst; 1650 struct dsa_switch *ds; 1651 struct dsa_port *dp; 1652 u16 pvlan = 0; 1653 1654 if (!mv88e6xxx_has_pvt(chip)) 1655 return 0; 1656 1657 /* Skip the local source device, which uses in-chip port VLAN */ 1658 if (dev != chip->ds->index) { 1659 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1660 1661 ds = dsa_switch_find(dst->index, dev); 1662 dp = ds ? dsa_to_port(ds, port) : NULL; 1663 if (dp && dp->lag) { 1664 /* As the PVT is used to limit flooding of 1665 * FORWARD frames, which use the LAG ID as the 1666 * source port, we must translate dev/port to 1667 * the special "LAG device" in the PVT, using 1668 * the LAG ID (one-based) as the port number 1669 * (zero-based). 1670 */ 1671 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1672 port = dsa_port_lag_id_get(dp) - 1; 1673 } 1674 } 1675 1676 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1677 } 1678 1679 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1680 { 1681 int dev, port; 1682 int err; 1683 1684 if (!mv88e6xxx_has_pvt(chip)) 1685 return 0; 1686 1687 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1688 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1689 */ 1690 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1691 if (err) 1692 return err; 1693 1694 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1695 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1696 err = mv88e6xxx_pvt_map(chip, dev, port); 1697 if (err) 1698 return err; 1699 } 1700 } 1701 1702 return 0; 1703 } 1704 1705 static int mv88e6xxx_port_fast_age_fid(struct mv88e6xxx_chip *chip, int port, 1706 u16 fid) 1707 { 1708 if (dsa_to_port(chip->ds, port)->lag) 1709 /* Hardware is incapable of fast-aging a LAG through a 1710 * regular ATU move operation. Until we have something 1711 * more fancy in place this is a no-op. 1712 */ 1713 return -EOPNOTSUPP; 1714 1715 return mv88e6xxx_g1_atu_remove(chip, fid, port, false); 1716 } 1717 1718 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1719 { 1720 struct mv88e6xxx_chip *chip = ds->priv; 1721 int err; 1722 1723 mv88e6xxx_reg_lock(chip); 1724 err = mv88e6xxx_port_fast_age_fid(chip, port, 0); 1725 mv88e6xxx_reg_unlock(chip); 1726 1727 if (err) 1728 dev_err(chip->ds->dev, "p%d: failed to flush ATU: %d\n", 1729 port, err); 1730 } 1731 1732 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1733 { 1734 if (!mv88e6xxx_max_vid(chip)) 1735 return 0; 1736 1737 return mv88e6xxx_g1_vtu_flush(chip); 1738 } 1739 1740 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1741 struct mv88e6xxx_vtu_entry *entry) 1742 { 1743 int err; 1744 1745 if (!chip->info->ops->vtu_getnext) 1746 return -EOPNOTSUPP; 1747 1748 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1749 entry->valid = false; 1750 1751 err = chip->info->ops->vtu_getnext(chip, entry); 1752 1753 if (entry->vid != vid) 1754 entry->valid = false; 1755 1756 return err; 1757 } 1758 1759 int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1760 int (*cb)(struct mv88e6xxx_chip *chip, 1761 const struct mv88e6xxx_vtu_entry *entry, 1762 void *priv), 1763 void *priv) 1764 { 1765 struct mv88e6xxx_vtu_entry entry = { 1766 .vid = mv88e6xxx_max_vid(chip), 1767 .valid = false, 1768 }; 1769 int err; 1770 1771 if (!chip->info->ops->vtu_getnext) 1772 return -EOPNOTSUPP; 1773 1774 do { 1775 err = chip->info->ops->vtu_getnext(chip, &entry); 1776 if (err) 1777 return err; 1778 1779 if (!entry.valid) 1780 break; 1781 1782 err = cb(chip, &entry, priv); 1783 if (err) 1784 return err; 1785 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1786 1787 return 0; 1788 } 1789 1790 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1791 struct mv88e6xxx_vtu_entry *entry) 1792 { 1793 if (!chip->info->ops->vtu_loadpurge) 1794 return -EOPNOTSUPP; 1795 1796 return chip->info->ops->vtu_loadpurge(chip, entry); 1797 } 1798 1799 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1800 const struct mv88e6xxx_vtu_entry *entry, 1801 void *_fid_bitmap) 1802 { 1803 unsigned long *fid_bitmap = _fid_bitmap; 1804 1805 set_bit(entry->fid, fid_bitmap); 1806 return 0; 1807 } 1808 1809 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1810 { 1811 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1812 1813 /* Every FID has an associated VID, so walking the VTU 1814 * will discover the full set of FIDs in use. 1815 */ 1816 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1817 } 1818 1819 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1820 { 1821 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1822 int err; 1823 1824 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1825 if (err) 1826 return err; 1827 1828 *fid = find_first_zero_bit(fid_bitmap, MV88E6XXX_N_FID); 1829 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1830 return -ENOSPC; 1831 1832 /* Clear the database */ 1833 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1834 } 1835 1836 static int mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1837 struct mv88e6xxx_stu_entry *entry) 1838 { 1839 if (!chip->info->ops->stu_loadpurge) 1840 return -EOPNOTSUPP; 1841 1842 return chip->info->ops->stu_loadpurge(chip, entry); 1843 } 1844 1845 static int mv88e6xxx_stu_setup(struct mv88e6xxx_chip *chip) 1846 { 1847 struct mv88e6xxx_stu_entry stu = { 1848 .valid = true, 1849 .sid = 0 1850 }; 1851 1852 if (!mv88e6xxx_has_stu(chip)) 1853 return 0; 1854 1855 /* Make sure that SID 0 is always valid. This is used by VTU 1856 * entries that do not make use of the STU, e.g. when creating 1857 * a VLAN upper on a port that is also part of a VLAN 1858 * filtering bridge. 1859 */ 1860 return mv88e6xxx_stu_loadpurge(chip, &stu); 1861 } 1862 1863 static int mv88e6xxx_sid_get(struct mv88e6xxx_chip *chip, u8 *sid) 1864 { 1865 DECLARE_BITMAP(busy, MV88E6XXX_N_SID) = { 0 }; 1866 struct mv88e6xxx_mst *mst; 1867 1868 __set_bit(0, busy); 1869 1870 list_for_each_entry(mst, &chip->msts, node) 1871 __set_bit(mst->stu.sid, busy); 1872 1873 *sid = find_first_zero_bit(busy, MV88E6XXX_N_SID); 1874 1875 return (*sid >= mv88e6xxx_max_sid(chip)) ? -ENOSPC : 0; 1876 } 1877 1878 static int mv88e6xxx_mst_put(struct mv88e6xxx_chip *chip, u8 sid) 1879 { 1880 struct mv88e6xxx_mst *mst, *tmp; 1881 int err; 1882 1883 if (!sid) 1884 return 0; 1885 1886 list_for_each_entry_safe(mst, tmp, &chip->msts, node) { 1887 if (mst->stu.sid != sid) 1888 continue; 1889 1890 if (!refcount_dec_and_test(&mst->refcnt)) 1891 return 0; 1892 1893 mst->stu.valid = false; 1894 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1895 if (err) { 1896 refcount_set(&mst->refcnt, 1); 1897 return err; 1898 } 1899 1900 list_del(&mst->node); 1901 kfree(mst); 1902 return 0; 1903 } 1904 1905 return -ENOENT; 1906 } 1907 1908 static int mv88e6xxx_mst_get(struct mv88e6xxx_chip *chip, struct net_device *br, 1909 u16 msti, u8 *sid) 1910 { 1911 struct mv88e6xxx_mst *mst; 1912 int err, i; 1913 1914 if (!mv88e6xxx_has_stu(chip)) { 1915 err = -EOPNOTSUPP; 1916 goto err; 1917 } 1918 1919 if (!msti) { 1920 *sid = 0; 1921 return 0; 1922 } 1923 1924 list_for_each_entry(mst, &chip->msts, node) { 1925 if (mst->br == br && mst->msti == msti) { 1926 refcount_inc(&mst->refcnt); 1927 *sid = mst->stu.sid; 1928 return 0; 1929 } 1930 } 1931 1932 err = mv88e6xxx_sid_get(chip, sid); 1933 if (err) 1934 goto err; 1935 1936 mst = kzalloc(sizeof(*mst), GFP_KERNEL); 1937 if (!mst) { 1938 err = -ENOMEM; 1939 goto err; 1940 } 1941 1942 INIT_LIST_HEAD(&mst->node); 1943 refcount_set(&mst->refcnt, 1); 1944 mst->br = br; 1945 mst->msti = msti; 1946 mst->stu.valid = true; 1947 mst->stu.sid = *sid; 1948 1949 /* The bridge starts out all ports in the disabled state. But 1950 * a STU state of disabled means to go by the port-global 1951 * state. So we set all user port's initial state to blocking, 1952 * to match the bridge's behavior. 1953 */ 1954 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 1955 mst->stu.state[i] = dsa_is_user_port(chip->ds, i) ? 1956 MV88E6XXX_PORT_CTL0_STATE_BLOCKING : 1957 MV88E6XXX_PORT_CTL0_STATE_DISABLED; 1958 1959 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 1960 if (err) 1961 goto err_free; 1962 1963 list_add_tail(&mst->node, &chip->msts); 1964 return 0; 1965 1966 err_free: 1967 kfree(mst); 1968 err: 1969 return err; 1970 } 1971 1972 static int mv88e6xxx_port_mst_state_set(struct dsa_switch *ds, int port, 1973 const struct switchdev_mst_state *st) 1974 { 1975 struct dsa_port *dp = dsa_to_port(ds, port); 1976 struct mv88e6xxx_chip *chip = ds->priv; 1977 struct mv88e6xxx_mst *mst; 1978 u8 state; 1979 int err; 1980 1981 if (!mv88e6xxx_has_stu(chip)) 1982 return -EOPNOTSUPP; 1983 1984 switch (st->state) { 1985 case BR_STATE_DISABLED: 1986 case BR_STATE_BLOCKING: 1987 case BR_STATE_LISTENING: 1988 state = MV88E6XXX_PORT_CTL0_STATE_BLOCKING; 1989 break; 1990 case BR_STATE_LEARNING: 1991 state = MV88E6XXX_PORT_CTL0_STATE_LEARNING; 1992 break; 1993 case BR_STATE_FORWARDING: 1994 state = MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 1995 break; 1996 default: 1997 return -EINVAL; 1998 } 1999 2000 list_for_each_entry(mst, &chip->msts, node) { 2001 if (mst->br == dsa_port_bridge_dev_get(dp) && 2002 mst->msti == st->msti) { 2003 if (mst->stu.state[port] == state) 2004 return 0; 2005 2006 mst->stu.state[port] = state; 2007 mv88e6xxx_reg_lock(chip); 2008 err = mv88e6xxx_stu_loadpurge(chip, &mst->stu); 2009 mv88e6xxx_reg_unlock(chip); 2010 return err; 2011 } 2012 } 2013 2014 return -ENOENT; 2015 } 2016 2017 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 2018 u16 vid) 2019 { 2020 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 2021 struct mv88e6xxx_chip *chip = ds->priv; 2022 struct mv88e6xxx_vtu_entry vlan; 2023 int err; 2024 2025 /* DSA and CPU ports have to be members of multiple vlans */ 2026 if (dsa_port_is_dsa(dp) || dsa_port_is_cpu(dp)) 2027 return 0; 2028 2029 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2030 if (err) 2031 return err; 2032 2033 if (!vlan.valid) 2034 return 0; 2035 2036 dsa_switch_for_each_user_port(other_dp, ds) { 2037 struct net_device *other_br; 2038 2039 if (vlan.member[other_dp->index] == 2040 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2041 continue; 2042 2043 if (dsa_port_bridge_same(dp, other_dp)) 2044 break; /* same bridge, check next VLAN */ 2045 2046 other_br = dsa_port_bridge_dev_get(other_dp); 2047 if (!other_br) 2048 continue; 2049 2050 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 2051 port, vlan.vid, other_dp->index, netdev_name(other_br)); 2052 return -EOPNOTSUPP; 2053 } 2054 2055 return 0; 2056 } 2057 2058 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 2059 { 2060 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2061 struct net_device *br = dsa_port_bridge_dev_get(dp); 2062 struct mv88e6xxx_port *p = &chip->ports[port]; 2063 u16 pvid = MV88E6XXX_VID_STANDALONE; 2064 bool drop_untagged = false; 2065 int err; 2066 2067 if (br) { 2068 if (br_vlan_enabled(br)) { 2069 pvid = p->bridge_pvid.vid; 2070 drop_untagged = !p->bridge_pvid.valid; 2071 } else { 2072 pvid = MV88E6XXX_VID_BRIDGED; 2073 } 2074 } 2075 2076 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 2077 if (err) 2078 return err; 2079 2080 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 2081 } 2082 2083 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 2084 bool vlan_filtering, 2085 struct netlink_ext_ack *extack) 2086 { 2087 struct mv88e6xxx_chip *chip = ds->priv; 2088 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 2089 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 2090 int err; 2091 2092 if (!mv88e6xxx_max_vid(chip)) 2093 return -EOPNOTSUPP; 2094 2095 mv88e6xxx_reg_lock(chip); 2096 2097 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 2098 if (err) 2099 goto unlock; 2100 2101 err = mv88e6xxx_port_commit_pvid(chip, port); 2102 if (err) 2103 goto unlock; 2104 2105 unlock: 2106 mv88e6xxx_reg_unlock(chip); 2107 2108 return err; 2109 } 2110 2111 static int 2112 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 2113 const struct switchdev_obj_port_vlan *vlan) 2114 { 2115 struct mv88e6xxx_chip *chip = ds->priv; 2116 int err; 2117 2118 if (!mv88e6xxx_max_vid(chip)) 2119 return -EOPNOTSUPP; 2120 2121 /* If the requested port doesn't belong to the same bridge as the VLAN 2122 * members, do not support it (yet) and fallback to software VLAN. 2123 */ 2124 mv88e6xxx_reg_lock(chip); 2125 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 2126 mv88e6xxx_reg_unlock(chip); 2127 2128 return err; 2129 } 2130 2131 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2132 const unsigned char *addr, u16 vid, 2133 u8 state) 2134 { 2135 struct mv88e6xxx_atu_entry entry; 2136 struct mv88e6xxx_vtu_entry vlan; 2137 u16 fid; 2138 int err; 2139 2140 /* Ports have two private address databases: one for when the port is 2141 * standalone and one for when the port is under a bridge and the 2142 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 2143 * address database to remain 100% empty, so we never load an ATU entry 2144 * into a standalone port's database. Therefore, translate the null 2145 * VLAN ID into the port's database used for VLAN-unaware bridging. 2146 */ 2147 if (vid == 0) { 2148 fid = MV88E6XXX_FID_BRIDGED; 2149 } else { 2150 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2151 if (err) 2152 return err; 2153 2154 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 2155 if (!vlan.valid) 2156 return -EOPNOTSUPP; 2157 2158 fid = vlan.fid; 2159 } 2160 2161 entry.state = 0; 2162 ether_addr_copy(entry.mac, addr); 2163 eth_addr_dec(entry.mac); 2164 2165 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 2166 if (err) 2167 return err; 2168 2169 /* Initialize a fresh ATU entry if it isn't found */ 2170 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 2171 memset(&entry, 0, sizeof(entry)); 2172 ether_addr_copy(entry.mac, addr); 2173 } 2174 2175 /* Purge the ATU entry only if no port is using it anymore */ 2176 if (!state) { 2177 entry.portvec &= ~BIT(port); 2178 if (!entry.portvec) 2179 entry.state = 0; 2180 } else { 2181 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 2182 entry.portvec = BIT(port); 2183 else 2184 entry.portvec |= BIT(port); 2185 2186 entry.state = state; 2187 } 2188 2189 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 2190 } 2191 2192 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 2193 const struct mv88e6xxx_policy *policy) 2194 { 2195 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 2196 enum mv88e6xxx_policy_action action = policy->action; 2197 const u8 *addr = policy->addr; 2198 u16 vid = policy->vid; 2199 u8 state; 2200 int err; 2201 int id; 2202 2203 if (!chip->info->ops->port_set_policy) 2204 return -EOPNOTSUPP; 2205 2206 switch (mapping) { 2207 case MV88E6XXX_POLICY_MAPPING_DA: 2208 case MV88E6XXX_POLICY_MAPPING_SA: 2209 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2210 state = 0; /* Dissociate the port and address */ 2211 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2212 is_multicast_ether_addr(addr)) 2213 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 2214 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 2215 is_unicast_ether_addr(addr)) 2216 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 2217 else 2218 return -EOPNOTSUPP; 2219 2220 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2221 state); 2222 if (err) 2223 return err; 2224 break; 2225 default: 2226 return -EOPNOTSUPP; 2227 } 2228 2229 /* Skip the port's policy clearing if the mapping is still in use */ 2230 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 2231 idr_for_each_entry(&chip->policies, policy, id) 2232 if (policy->port == port && 2233 policy->mapping == mapping && 2234 policy->action != action) 2235 return 0; 2236 2237 return chip->info->ops->port_set_policy(chip, port, mapping, action); 2238 } 2239 2240 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 2241 struct ethtool_rx_flow_spec *fs) 2242 { 2243 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 2244 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 2245 enum mv88e6xxx_policy_mapping mapping; 2246 enum mv88e6xxx_policy_action action; 2247 struct mv88e6xxx_policy *policy; 2248 u16 vid = 0; 2249 u8 *addr; 2250 int err; 2251 int id; 2252 2253 if (fs->location != RX_CLS_LOC_ANY) 2254 return -EINVAL; 2255 2256 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 2257 action = MV88E6XXX_POLICY_ACTION_DISCARD; 2258 else 2259 return -EOPNOTSUPP; 2260 2261 switch (fs->flow_type & ~FLOW_EXT) { 2262 case ETHER_FLOW: 2263 if (!is_zero_ether_addr(mac_mask->h_dest) && 2264 is_zero_ether_addr(mac_mask->h_source)) { 2265 mapping = MV88E6XXX_POLICY_MAPPING_DA; 2266 addr = mac_entry->h_dest; 2267 } else if (is_zero_ether_addr(mac_mask->h_dest) && 2268 !is_zero_ether_addr(mac_mask->h_source)) { 2269 mapping = MV88E6XXX_POLICY_MAPPING_SA; 2270 addr = mac_entry->h_source; 2271 } else { 2272 /* Cannot support DA and SA mapping in the same rule */ 2273 return -EOPNOTSUPP; 2274 } 2275 break; 2276 default: 2277 return -EOPNOTSUPP; 2278 } 2279 2280 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 2281 if (fs->m_ext.vlan_tci != htons(0xffff)) 2282 return -EOPNOTSUPP; 2283 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 2284 } 2285 2286 idr_for_each_entry(&chip->policies, policy, id) { 2287 if (policy->port == port && policy->mapping == mapping && 2288 policy->action == action && policy->vid == vid && 2289 ether_addr_equal(policy->addr, addr)) 2290 return -EEXIST; 2291 } 2292 2293 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 2294 if (!policy) 2295 return -ENOMEM; 2296 2297 fs->location = 0; 2298 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 2299 GFP_KERNEL); 2300 if (err) { 2301 devm_kfree(chip->dev, policy); 2302 return err; 2303 } 2304 2305 memcpy(&policy->fs, fs, sizeof(*fs)); 2306 ether_addr_copy(policy->addr, addr); 2307 policy->mapping = mapping; 2308 policy->action = action; 2309 policy->port = port; 2310 policy->vid = vid; 2311 2312 err = mv88e6xxx_policy_apply(chip, port, policy); 2313 if (err) { 2314 idr_remove(&chip->policies, fs->location); 2315 devm_kfree(chip->dev, policy); 2316 return err; 2317 } 2318 2319 return 0; 2320 } 2321 2322 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 2323 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 2324 { 2325 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2326 struct mv88e6xxx_chip *chip = ds->priv; 2327 struct mv88e6xxx_policy *policy; 2328 int err; 2329 int id; 2330 2331 mv88e6xxx_reg_lock(chip); 2332 2333 switch (rxnfc->cmd) { 2334 case ETHTOOL_GRXCLSRLCNT: 2335 rxnfc->data = 0; 2336 rxnfc->data |= RX_CLS_LOC_SPECIAL; 2337 rxnfc->rule_cnt = 0; 2338 idr_for_each_entry(&chip->policies, policy, id) 2339 if (policy->port == port) 2340 rxnfc->rule_cnt++; 2341 err = 0; 2342 break; 2343 case ETHTOOL_GRXCLSRULE: 2344 err = -ENOENT; 2345 policy = idr_find(&chip->policies, fs->location); 2346 if (policy) { 2347 memcpy(fs, &policy->fs, sizeof(*fs)); 2348 err = 0; 2349 } 2350 break; 2351 case ETHTOOL_GRXCLSRLALL: 2352 rxnfc->data = 0; 2353 rxnfc->rule_cnt = 0; 2354 idr_for_each_entry(&chip->policies, policy, id) 2355 if (policy->port == port) 2356 rule_locs[rxnfc->rule_cnt++] = id; 2357 err = 0; 2358 break; 2359 default: 2360 err = -EOPNOTSUPP; 2361 break; 2362 } 2363 2364 mv88e6xxx_reg_unlock(chip); 2365 2366 return err; 2367 } 2368 2369 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2370 struct ethtool_rxnfc *rxnfc) 2371 { 2372 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2373 struct mv88e6xxx_chip *chip = ds->priv; 2374 struct mv88e6xxx_policy *policy; 2375 int err; 2376 2377 mv88e6xxx_reg_lock(chip); 2378 2379 switch (rxnfc->cmd) { 2380 case ETHTOOL_SRXCLSRLINS: 2381 err = mv88e6xxx_policy_insert(chip, port, fs); 2382 break; 2383 case ETHTOOL_SRXCLSRLDEL: 2384 err = -ENOENT; 2385 policy = idr_remove(&chip->policies, fs->location); 2386 if (policy) { 2387 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2388 err = mv88e6xxx_policy_apply(chip, port, policy); 2389 devm_kfree(chip->dev, policy); 2390 } 2391 break; 2392 default: 2393 err = -EOPNOTSUPP; 2394 break; 2395 } 2396 2397 mv88e6xxx_reg_unlock(chip); 2398 2399 return err; 2400 } 2401 2402 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2403 u16 vid) 2404 { 2405 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2406 u8 broadcast[ETH_ALEN]; 2407 2408 eth_broadcast_addr(broadcast); 2409 2410 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2411 } 2412 2413 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2414 { 2415 int port; 2416 int err; 2417 2418 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2419 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2420 struct net_device *brport; 2421 2422 if (dsa_is_unused_port(chip->ds, port)) 2423 continue; 2424 2425 brport = dsa_port_to_bridge_port(dp); 2426 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2427 /* Skip bridged user ports where broadcast 2428 * flooding is disabled. 2429 */ 2430 continue; 2431 2432 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2433 if (err) 2434 return err; 2435 } 2436 2437 return 0; 2438 } 2439 2440 struct mv88e6xxx_port_broadcast_sync_ctx { 2441 int port; 2442 bool flood; 2443 }; 2444 2445 static int 2446 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2447 const struct mv88e6xxx_vtu_entry *vlan, 2448 void *_ctx) 2449 { 2450 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2451 u8 broadcast[ETH_ALEN]; 2452 u8 state; 2453 2454 if (ctx->flood) 2455 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2456 else 2457 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2458 2459 eth_broadcast_addr(broadcast); 2460 2461 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2462 vlan->vid, state); 2463 } 2464 2465 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2466 bool flood) 2467 { 2468 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2469 .port = port, 2470 .flood = flood, 2471 }; 2472 struct mv88e6xxx_vtu_entry vid0 = { 2473 .vid = 0, 2474 }; 2475 int err; 2476 2477 /* Update the port's private database... */ 2478 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2479 if (err) 2480 return err; 2481 2482 /* ...and the database for all VLANs. */ 2483 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2484 &ctx); 2485 } 2486 2487 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2488 u16 vid, u8 member, bool warn) 2489 { 2490 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2491 struct mv88e6xxx_vtu_entry vlan; 2492 int i, err; 2493 2494 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2495 if (err) 2496 return err; 2497 2498 if (!vlan.valid) { 2499 memset(&vlan, 0, sizeof(vlan)); 2500 2501 if (vid == MV88E6XXX_VID_STANDALONE) 2502 vlan.policy = true; 2503 2504 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2505 if (err) 2506 return err; 2507 2508 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2509 if (i == port) 2510 vlan.member[i] = member; 2511 else 2512 vlan.member[i] = non_member; 2513 2514 vlan.vid = vid; 2515 vlan.valid = true; 2516 2517 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2518 if (err) 2519 return err; 2520 2521 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2522 if (err) 2523 return err; 2524 } else if (vlan.member[port] != member) { 2525 vlan.member[port] = member; 2526 2527 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2528 if (err) 2529 return err; 2530 } else if (warn) { 2531 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2532 port, vid); 2533 } 2534 2535 return 0; 2536 } 2537 2538 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2539 const struct switchdev_obj_port_vlan *vlan, 2540 struct netlink_ext_ack *extack) 2541 { 2542 struct mv88e6xxx_chip *chip = ds->priv; 2543 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2544 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2545 struct mv88e6xxx_port *p = &chip->ports[port]; 2546 bool warn; 2547 u8 member; 2548 int err; 2549 2550 if (!vlan->vid) 2551 return 0; 2552 2553 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2554 if (err) 2555 return err; 2556 2557 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2558 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2559 else if (untagged) 2560 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2561 else 2562 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2563 2564 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2565 * and then the CPU port. Do not warn for duplicates for the CPU port. 2566 */ 2567 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2568 2569 mv88e6xxx_reg_lock(chip); 2570 2571 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2572 if (err) { 2573 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2574 vlan->vid, untagged ? 'u' : 't'); 2575 goto out; 2576 } 2577 2578 if (pvid) { 2579 p->bridge_pvid.vid = vlan->vid; 2580 p->bridge_pvid.valid = true; 2581 2582 err = mv88e6xxx_port_commit_pvid(chip, port); 2583 if (err) 2584 goto out; 2585 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2586 /* The old pvid was reinstalled as a non-pvid VLAN */ 2587 p->bridge_pvid.valid = false; 2588 2589 err = mv88e6xxx_port_commit_pvid(chip, port); 2590 if (err) 2591 goto out; 2592 } 2593 2594 out: 2595 mv88e6xxx_reg_unlock(chip); 2596 2597 return err; 2598 } 2599 2600 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2601 int port, u16 vid) 2602 { 2603 struct mv88e6xxx_vtu_entry vlan; 2604 int i, err; 2605 2606 if (!vid) 2607 return 0; 2608 2609 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2610 if (err) 2611 return err; 2612 2613 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2614 * tell switchdev that this VLAN is likely handled in software. 2615 */ 2616 if (!vlan.valid || 2617 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2618 return -EOPNOTSUPP; 2619 2620 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2621 2622 /* keep the VLAN unless all ports are excluded */ 2623 vlan.valid = false; 2624 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2625 if (vlan.member[i] != 2626 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2627 vlan.valid = true; 2628 break; 2629 } 2630 } 2631 2632 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2633 if (err) 2634 return err; 2635 2636 if (!vlan.valid) { 2637 err = mv88e6xxx_mst_put(chip, vlan.sid); 2638 if (err) 2639 return err; 2640 } 2641 2642 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2643 } 2644 2645 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2646 const struct switchdev_obj_port_vlan *vlan) 2647 { 2648 struct mv88e6xxx_chip *chip = ds->priv; 2649 struct mv88e6xxx_port *p = &chip->ports[port]; 2650 int err = 0; 2651 u16 pvid; 2652 2653 if (!mv88e6xxx_max_vid(chip)) 2654 return -EOPNOTSUPP; 2655 2656 /* The ATU removal procedure needs the FID to be mapped in the VTU, 2657 * but FDB deletion runs concurrently with VLAN deletion. Flush the DSA 2658 * switchdev workqueue to ensure that all FDB entries are deleted 2659 * before we remove the VLAN. 2660 */ 2661 dsa_flush_workqueue(); 2662 2663 mv88e6xxx_reg_lock(chip); 2664 2665 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2666 if (err) 2667 goto unlock; 2668 2669 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2670 if (err) 2671 goto unlock; 2672 2673 if (vlan->vid == pvid) { 2674 p->bridge_pvid.valid = false; 2675 2676 err = mv88e6xxx_port_commit_pvid(chip, port); 2677 if (err) 2678 goto unlock; 2679 } 2680 2681 unlock: 2682 mv88e6xxx_reg_unlock(chip); 2683 2684 return err; 2685 } 2686 2687 static int mv88e6xxx_port_vlan_fast_age(struct dsa_switch *ds, int port, u16 vid) 2688 { 2689 struct mv88e6xxx_chip *chip = ds->priv; 2690 struct mv88e6xxx_vtu_entry vlan; 2691 int err; 2692 2693 mv88e6xxx_reg_lock(chip); 2694 2695 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2696 if (err) 2697 goto unlock; 2698 2699 err = mv88e6xxx_port_fast_age_fid(chip, port, vlan.fid); 2700 2701 unlock: 2702 mv88e6xxx_reg_unlock(chip); 2703 2704 return err; 2705 } 2706 2707 static int mv88e6xxx_vlan_msti_set(struct dsa_switch *ds, 2708 struct dsa_bridge bridge, 2709 const struct switchdev_vlan_msti *msti) 2710 { 2711 struct mv88e6xxx_chip *chip = ds->priv; 2712 struct mv88e6xxx_vtu_entry vlan; 2713 u8 old_sid, new_sid; 2714 int err; 2715 2716 if (!mv88e6xxx_has_stu(chip)) 2717 return -EOPNOTSUPP; 2718 2719 mv88e6xxx_reg_lock(chip); 2720 2721 err = mv88e6xxx_vtu_get(chip, msti->vid, &vlan); 2722 if (err) 2723 goto unlock; 2724 2725 if (!vlan.valid) { 2726 err = -EINVAL; 2727 goto unlock; 2728 } 2729 2730 old_sid = vlan.sid; 2731 2732 err = mv88e6xxx_mst_get(chip, bridge.dev, msti->msti, &new_sid); 2733 if (err) 2734 goto unlock; 2735 2736 if (new_sid != old_sid) { 2737 vlan.sid = new_sid; 2738 2739 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2740 if (err) { 2741 mv88e6xxx_mst_put(chip, new_sid); 2742 goto unlock; 2743 } 2744 } 2745 2746 err = mv88e6xxx_mst_put(chip, old_sid); 2747 2748 unlock: 2749 mv88e6xxx_reg_unlock(chip); 2750 return err; 2751 } 2752 2753 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2754 const unsigned char *addr, u16 vid, 2755 struct dsa_db db) 2756 { 2757 struct mv88e6xxx_chip *chip = ds->priv; 2758 int err; 2759 2760 mv88e6xxx_reg_lock(chip); 2761 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2762 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2763 mv88e6xxx_reg_unlock(chip); 2764 2765 return err; 2766 } 2767 2768 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2769 const unsigned char *addr, u16 vid, 2770 struct dsa_db db) 2771 { 2772 struct mv88e6xxx_chip *chip = ds->priv; 2773 int err; 2774 2775 mv88e6xxx_reg_lock(chip); 2776 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2777 mv88e6xxx_reg_unlock(chip); 2778 2779 return err; 2780 } 2781 2782 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2783 u16 fid, u16 vid, int port, 2784 dsa_fdb_dump_cb_t *cb, void *data) 2785 { 2786 struct mv88e6xxx_atu_entry addr; 2787 bool is_static; 2788 int err; 2789 2790 addr.state = 0; 2791 eth_broadcast_addr(addr.mac); 2792 2793 do { 2794 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2795 if (err) 2796 return err; 2797 2798 if (!addr.state) 2799 break; 2800 2801 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2802 continue; 2803 2804 if (!is_unicast_ether_addr(addr.mac)) 2805 continue; 2806 2807 is_static = (addr.state == 2808 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2809 err = cb(addr.mac, vid, is_static, data); 2810 if (err) 2811 return err; 2812 } while (!is_broadcast_ether_addr(addr.mac)); 2813 2814 return err; 2815 } 2816 2817 struct mv88e6xxx_port_db_dump_vlan_ctx { 2818 int port; 2819 dsa_fdb_dump_cb_t *cb; 2820 void *data; 2821 }; 2822 2823 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2824 const struct mv88e6xxx_vtu_entry *entry, 2825 void *_data) 2826 { 2827 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2828 2829 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2830 ctx->port, ctx->cb, ctx->data); 2831 } 2832 2833 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2834 dsa_fdb_dump_cb_t *cb, void *data) 2835 { 2836 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2837 .port = port, 2838 .cb = cb, 2839 .data = data, 2840 }; 2841 u16 fid; 2842 int err; 2843 2844 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2845 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2846 if (err) 2847 return err; 2848 2849 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2850 if (err) 2851 return err; 2852 2853 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2854 } 2855 2856 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2857 dsa_fdb_dump_cb_t *cb, void *data) 2858 { 2859 struct mv88e6xxx_chip *chip = ds->priv; 2860 int err; 2861 2862 mv88e6xxx_reg_lock(chip); 2863 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2864 mv88e6xxx_reg_unlock(chip); 2865 2866 return err; 2867 } 2868 2869 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2870 struct dsa_bridge bridge) 2871 { 2872 struct dsa_switch *ds = chip->ds; 2873 struct dsa_switch_tree *dst = ds->dst; 2874 struct dsa_port *dp; 2875 int err; 2876 2877 list_for_each_entry(dp, &dst->ports, list) { 2878 if (dsa_port_offloads_bridge(dp, &bridge)) { 2879 if (dp->ds == ds) { 2880 /* This is a local bridge group member, 2881 * remap its Port VLAN Map. 2882 */ 2883 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2884 if (err) 2885 return err; 2886 } else { 2887 /* This is an external bridge group member, 2888 * remap its cross-chip Port VLAN Table entry. 2889 */ 2890 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2891 dp->index); 2892 if (err) 2893 return err; 2894 } 2895 } 2896 } 2897 2898 return 0; 2899 } 2900 2901 /* Treat the software bridge as a virtual single-port switch behind the 2902 * CPU and map in the PVT. First dst->last_switch elements are taken by 2903 * physical switches, so start from beyond that range. 2904 */ 2905 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2906 unsigned int bridge_num) 2907 { 2908 u8 dev = bridge_num + ds->dst->last_switch; 2909 struct mv88e6xxx_chip *chip = ds->priv; 2910 2911 return mv88e6xxx_pvt_map(chip, dev, 0); 2912 } 2913 2914 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2915 struct dsa_bridge bridge, 2916 bool *tx_fwd_offload, 2917 struct netlink_ext_ack *extack) 2918 { 2919 struct mv88e6xxx_chip *chip = ds->priv; 2920 int err; 2921 2922 mv88e6xxx_reg_lock(chip); 2923 2924 err = mv88e6xxx_bridge_map(chip, bridge); 2925 if (err) 2926 goto unlock; 2927 2928 err = mv88e6xxx_port_set_map_da(chip, port, true); 2929 if (err) 2930 goto unlock; 2931 2932 err = mv88e6xxx_port_commit_pvid(chip, port); 2933 if (err) 2934 goto unlock; 2935 2936 if (mv88e6xxx_has_pvt(chip)) { 2937 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2938 if (err) 2939 goto unlock; 2940 2941 *tx_fwd_offload = true; 2942 } 2943 2944 unlock: 2945 mv88e6xxx_reg_unlock(chip); 2946 2947 return err; 2948 } 2949 2950 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2951 struct dsa_bridge bridge) 2952 { 2953 struct mv88e6xxx_chip *chip = ds->priv; 2954 int err; 2955 2956 mv88e6xxx_reg_lock(chip); 2957 2958 if (bridge.tx_fwd_offload && 2959 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 2960 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2961 2962 if (mv88e6xxx_bridge_map(chip, bridge) || 2963 mv88e6xxx_port_vlan_map(chip, port)) 2964 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2965 2966 err = mv88e6xxx_port_set_map_da(chip, port, false); 2967 if (err) 2968 dev_err(ds->dev, 2969 "port %d failed to restore map-DA: %pe\n", 2970 port, ERR_PTR(err)); 2971 2972 err = mv88e6xxx_port_commit_pvid(chip, port); 2973 if (err) 2974 dev_err(ds->dev, 2975 "port %d failed to restore standalone pvid: %pe\n", 2976 port, ERR_PTR(err)); 2977 2978 mv88e6xxx_reg_unlock(chip); 2979 } 2980 2981 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2982 int tree_index, int sw_index, 2983 int port, struct dsa_bridge bridge, 2984 struct netlink_ext_ack *extack) 2985 { 2986 struct mv88e6xxx_chip *chip = ds->priv; 2987 int err; 2988 2989 if (tree_index != ds->dst->index) 2990 return 0; 2991 2992 mv88e6xxx_reg_lock(chip); 2993 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2994 err = err ? : mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num); 2995 mv88e6xxx_reg_unlock(chip); 2996 2997 return err; 2998 } 2999 3000 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 3001 int tree_index, int sw_index, 3002 int port, struct dsa_bridge bridge) 3003 { 3004 struct mv88e6xxx_chip *chip = ds->priv; 3005 3006 if (tree_index != ds->dst->index) 3007 return; 3008 3009 mv88e6xxx_reg_lock(chip); 3010 if (mv88e6xxx_pvt_map(chip, sw_index, port) || 3011 mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge.num)) 3012 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 3013 mv88e6xxx_reg_unlock(chip); 3014 } 3015 3016 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 3017 { 3018 if (chip->info->ops->reset) 3019 return chip->info->ops->reset(chip); 3020 3021 return 0; 3022 } 3023 3024 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 3025 { 3026 struct gpio_desc *gpiod = chip->reset; 3027 3028 /* If there is a GPIO connected to the reset pin, toggle it */ 3029 if (gpiod) { 3030 gpiod_set_value_cansleep(gpiod, 1); 3031 usleep_range(10000, 20000); 3032 gpiod_set_value_cansleep(gpiod, 0); 3033 usleep_range(10000, 20000); 3034 3035 mv88e6xxx_g1_wait_eeprom_done(chip); 3036 } 3037 } 3038 3039 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 3040 { 3041 int i, err; 3042 3043 /* Set all ports to the Disabled state */ 3044 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3045 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 3046 if (err) 3047 return err; 3048 } 3049 3050 /* Wait for transmit queues to drain, 3051 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 3052 */ 3053 usleep_range(2000, 4000); 3054 3055 return 0; 3056 } 3057 3058 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 3059 { 3060 int err; 3061 3062 err = mv88e6xxx_disable_ports(chip); 3063 if (err) 3064 return err; 3065 3066 mv88e6xxx_hardware_reset(chip); 3067 3068 return mv88e6xxx_software_reset(chip); 3069 } 3070 3071 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 3072 enum mv88e6xxx_frame_mode frame, 3073 enum mv88e6xxx_egress_mode egress, u16 etype) 3074 { 3075 int err; 3076 3077 if (!chip->info->ops->port_set_frame_mode) 3078 return -EOPNOTSUPP; 3079 3080 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 3081 if (err) 3082 return err; 3083 3084 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 3085 if (err) 3086 return err; 3087 3088 if (chip->info->ops->port_set_ether_type) 3089 return chip->info->ops->port_set_ether_type(chip, port, etype); 3090 3091 return 0; 3092 } 3093 3094 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 3095 { 3096 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 3097 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3098 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3099 } 3100 3101 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 3102 { 3103 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 3104 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 3105 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 3106 } 3107 3108 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 3109 { 3110 return mv88e6xxx_set_port_mode(chip, port, 3111 MV88E6XXX_FRAME_MODE_ETHERTYPE, 3112 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 3113 ETH_P_EDSA); 3114 } 3115 3116 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 3117 { 3118 if (dsa_is_dsa_port(chip->ds, port)) 3119 return mv88e6xxx_set_port_mode_dsa(chip, port); 3120 3121 if (dsa_is_user_port(chip->ds, port)) 3122 return mv88e6xxx_set_port_mode_normal(chip, port); 3123 3124 /* Setup CPU port mode depending on its supported tag format */ 3125 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 3126 return mv88e6xxx_set_port_mode_dsa(chip, port); 3127 3128 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 3129 return mv88e6xxx_set_port_mode_edsa(chip, port); 3130 3131 return -EINVAL; 3132 } 3133 3134 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 3135 { 3136 bool message = dsa_is_dsa_port(chip->ds, port); 3137 3138 return mv88e6xxx_port_set_message_port(chip, port, message); 3139 } 3140 3141 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 3142 { 3143 int err; 3144 3145 if (chip->info->ops->port_set_ucast_flood) { 3146 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 3147 if (err) 3148 return err; 3149 } 3150 if (chip->info->ops->port_set_mcast_flood) { 3151 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 3152 if (err) 3153 return err; 3154 } 3155 3156 return 0; 3157 } 3158 3159 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 3160 { 3161 struct mv88e6xxx_port *mvp = dev_id; 3162 struct mv88e6xxx_chip *chip = mvp->chip; 3163 irqreturn_t ret = IRQ_NONE; 3164 int port = mvp->port; 3165 int lane; 3166 3167 mv88e6xxx_reg_lock(chip); 3168 lane = mv88e6xxx_serdes_get_lane(chip, port); 3169 if (lane >= 0) 3170 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 3171 mv88e6xxx_reg_unlock(chip); 3172 3173 return ret; 3174 } 3175 3176 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 3177 int lane) 3178 { 3179 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3180 unsigned int irq; 3181 int err; 3182 3183 /* Nothing to request if this SERDES port has no IRQ */ 3184 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 3185 if (!irq) 3186 return 0; 3187 3188 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 3189 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 3190 3191 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 3192 mv88e6xxx_reg_unlock(chip); 3193 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 3194 IRQF_ONESHOT, dev_id->serdes_irq_name, 3195 dev_id); 3196 mv88e6xxx_reg_lock(chip); 3197 if (err) 3198 return err; 3199 3200 dev_id->serdes_irq = irq; 3201 3202 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 3203 } 3204 3205 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 3206 int lane) 3207 { 3208 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 3209 unsigned int irq = dev_id->serdes_irq; 3210 int err; 3211 3212 /* Nothing to free if no IRQ has been requested */ 3213 if (!irq) 3214 return 0; 3215 3216 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 3217 3218 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 3219 mv88e6xxx_reg_unlock(chip); 3220 free_irq(irq, dev_id); 3221 mv88e6xxx_reg_lock(chip); 3222 3223 dev_id->serdes_irq = 0; 3224 3225 return err; 3226 } 3227 3228 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 3229 bool on) 3230 { 3231 int lane; 3232 int err; 3233 3234 lane = mv88e6xxx_serdes_get_lane(chip, port); 3235 if (lane < 0) 3236 return 0; 3237 3238 if (on) { 3239 err = mv88e6xxx_serdes_power_up(chip, port, lane); 3240 if (err) 3241 return err; 3242 3243 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 3244 } else { 3245 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 3246 if (err) 3247 return err; 3248 3249 err = mv88e6xxx_serdes_power_down(chip, port, lane); 3250 } 3251 3252 return err; 3253 } 3254 3255 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 3256 enum mv88e6xxx_egress_direction direction, 3257 int port) 3258 { 3259 int err; 3260 3261 if (!chip->info->ops->set_egress_port) 3262 return -EOPNOTSUPP; 3263 3264 err = chip->info->ops->set_egress_port(chip, direction, port); 3265 if (err) 3266 return err; 3267 3268 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 3269 chip->ingress_dest_port = port; 3270 else 3271 chip->egress_dest_port = port; 3272 3273 return 0; 3274 } 3275 3276 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 3277 { 3278 struct dsa_switch *ds = chip->ds; 3279 int upstream_port; 3280 int err; 3281 3282 upstream_port = dsa_upstream_port(ds, port); 3283 if (chip->info->ops->port_set_upstream_port) { 3284 err = chip->info->ops->port_set_upstream_port(chip, port, 3285 upstream_port); 3286 if (err) 3287 return err; 3288 } 3289 3290 if (port == upstream_port) { 3291 if (chip->info->ops->set_cpu_port) { 3292 err = chip->info->ops->set_cpu_port(chip, 3293 upstream_port); 3294 if (err) 3295 return err; 3296 } 3297 3298 err = mv88e6xxx_set_egress_port(chip, 3299 MV88E6XXX_EGRESS_DIR_INGRESS, 3300 upstream_port); 3301 if (err && err != -EOPNOTSUPP) 3302 return err; 3303 3304 err = mv88e6xxx_set_egress_port(chip, 3305 MV88E6XXX_EGRESS_DIR_EGRESS, 3306 upstream_port); 3307 if (err && err != -EOPNOTSUPP) 3308 return err; 3309 } 3310 3311 return 0; 3312 } 3313 3314 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 3315 { 3316 struct device_node *phy_handle = NULL; 3317 struct dsa_switch *ds = chip->ds; 3318 phy_interface_t mode; 3319 struct dsa_port *dp; 3320 int tx_amp, speed; 3321 int err; 3322 u16 reg; 3323 3324 chip->ports[port].chip = chip; 3325 chip->ports[port].port = port; 3326 3327 dp = dsa_to_port(ds, port); 3328 3329 /* MAC Forcing register: don't force link, speed, duplex or flow control 3330 * state to any particular values on physical ports, but force the CPU 3331 * port and all DSA ports to their maximum bandwidth and full duplex. 3332 */ 3333 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 3334 struct phylink_config pl_config = {}; 3335 unsigned long caps; 3336 3337 chip->info->ops->phylink_get_caps(chip, port, &pl_config); 3338 3339 caps = pl_config.mac_capabilities; 3340 3341 if (chip->info->ops->port_max_speed_mode) 3342 mode = chip->info->ops->port_max_speed_mode(chip, port); 3343 else 3344 mode = PHY_INTERFACE_MODE_NA; 3345 3346 if (caps & MAC_10000FD) 3347 speed = SPEED_10000; 3348 else if (caps & MAC_5000FD) 3349 speed = SPEED_5000; 3350 else if (caps & MAC_2500FD) 3351 speed = SPEED_2500; 3352 else if (caps & MAC_1000) 3353 speed = SPEED_1000; 3354 else if (caps & MAC_100) 3355 speed = SPEED_100; 3356 else 3357 speed = SPEED_10; 3358 3359 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 3360 speed, DUPLEX_FULL, 3361 PAUSE_OFF, mode); 3362 } else { 3363 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 3364 SPEED_UNFORCED, DUPLEX_UNFORCED, 3365 PAUSE_ON, 3366 PHY_INTERFACE_MODE_NA); 3367 } 3368 if (err) 3369 return err; 3370 3371 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 3372 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 3373 * tunneling, determine priority by looking at 802.1p and IP 3374 * priority fields (IP prio has precedence), and set STP state 3375 * to Forwarding. 3376 * 3377 * If this is the CPU link, use DSA or EDSA tagging depending 3378 * on which tagging mode was configured. 3379 * 3380 * If this is a link to another switch, use DSA tagging mode. 3381 * 3382 * If this is the upstream port for this switch, enable 3383 * forwarding of unknown unicasts and multicasts. 3384 */ 3385 reg = MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 3386 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 3387 /* Forward any IPv4 IGMP or IPv6 MLD frames received 3388 * by a USER port to the CPU port to allow snooping. 3389 */ 3390 if (dsa_is_user_port(ds, port)) 3391 reg |= MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP; 3392 3393 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 3394 if (err) 3395 return err; 3396 3397 err = mv88e6xxx_setup_port_mode(chip, port); 3398 if (err) 3399 return err; 3400 3401 err = mv88e6xxx_setup_egress_floods(chip, port); 3402 if (err) 3403 return err; 3404 3405 /* Port Control 2: don't force a good FCS, set the MTU size to 3406 * 10222 bytes, disable 802.1q tags checking, don't discard 3407 * tagged or untagged frames on this port, skip destination 3408 * address lookup on user ports, disable ARP mirroring and don't 3409 * send a copy of all transmitted/received frames on this port 3410 * to the CPU. 3411 */ 3412 err = mv88e6xxx_port_set_map_da(chip, port, !dsa_is_user_port(ds, port)); 3413 if (err) 3414 return err; 3415 3416 err = mv88e6xxx_setup_upstream_port(chip, port); 3417 if (err) 3418 return err; 3419 3420 /* On chips that support it, set all downstream DSA ports' 3421 * VLAN policy to TRAP. In combination with loading 3422 * MV88E6XXX_VID_STANDALONE as a policy entry in the VTU, this 3423 * provides a better isolation barrier between standalone 3424 * ports, as the ATU is bypassed on any intermediate switches 3425 * between the incoming port and the CPU. 3426 */ 3427 if (dsa_is_downstream_port(ds, port) && 3428 chip->info->ops->port_set_policy) { 3429 err = chip->info->ops->port_set_policy(chip, port, 3430 MV88E6XXX_POLICY_MAPPING_VTU, 3431 MV88E6XXX_POLICY_ACTION_TRAP); 3432 if (err) 3433 return err; 3434 } 3435 3436 /* User ports start out in standalone mode and 802.1Q is 3437 * therefore disabled. On DSA ports, all valid VIDs are always 3438 * loaded in the VTU - therefore, enable 802.1Q in order to take 3439 * advantage of VLAN policy on chips that supports it. 3440 */ 3441 err = mv88e6xxx_port_set_8021q_mode(chip, port, 3442 dsa_is_user_port(ds, port) ? 3443 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED : 3444 MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE); 3445 if (err) 3446 return err; 3447 3448 /* Bind MV88E6XXX_VID_STANDALONE to MV88E6XXX_FID_STANDALONE by 3449 * virtue of the fact that mv88e6xxx_atu_new() will pick it as 3450 * the first free FID. This will be used as the private PVID for 3451 * unbridged ports. Shared (DSA and CPU) ports must also be 3452 * members of this VID, in order to trap all frames assigned to 3453 * it to the CPU. 3454 */ 3455 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_STANDALONE, 3456 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3457 false); 3458 if (err) 3459 return err; 3460 3461 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 3462 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 3463 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 3464 * as the private PVID on ports under a VLAN-unaware bridge. 3465 * Shared (DSA and CPU) ports must also be members of it, to translate 3466 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 3467 * relying on their port default FID. 3468 */ 3469 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 3470 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED, 3471 false); 3472 if (err) 3473 return err; 3474 3475 if (chip->info->ops->port_set_jumbo_size) { 3476 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 3477 if (err) 3478 return err; 3479 } 3480 3481 /* Port Association Vector: disable automatic address learning 3482 * on all user ports since they start out in standalone 3483 * mode. When joining a bridge, learning will be configured to 3484 * match the bridge port settings. Enable learning on all 3485 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 3486 * learning process. 3487 * 3488 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 3489 * and RefreshLocked. I.e. setup standard automatic learning. 3490 */ 3491 if (dsa_is_user_port(ds, port)) 3492 reg = 0; 3493 else 3494 reg = 1 << port; 3495 3496 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 3497 reg); 3498 if (err) 3499 return err; 3500 3501 /* Egress rate control 2: disable egress rate control. */ 3502 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 3503 0x0000); 3504 if (err) 3505 return err; 3506 3507 if (chip->info->ops->port_pause_limit) { 3508 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 3509 if (err) 3510 return err; 3511 } 3512 3513 if (chip->info->ops->port_disable_learn_limit) { 3514 err = chip->info->ops->port_disable_learn_limit(chip, port); 3515 if (err) 3516 return err; 3517 } 3518 3519 if (chip->info->ops->port_disable_pri_override) { 3520 err = chip->info->ops->port_disable_pri_override(chip, port); 3521 if (err) 3522 return err; 3523 } 3524 3525 if (chip->info->ops->port_tag_remap) { 3526 err = chip->info->ops->port_tag_remap(chip, port); 3527 if (err) 3528 return err; 3529 } 3530 3531 if (chip->info->ops->port_egress_rate_limiting) { 3532 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3533 if (err) 3534 return err; 3535 } 3536 3537 if (chip->info->ops->port_setup_message_port) { 3538 err = chip->info->ops->port_setup_message_port(chip, port); 3539 if (err) 3540 return err; 3541 } 3542 3543 if (chip->info->ops->serdes_set_tx_amplitude) { 3544 if (dp) 3545 phy_handle = of_parse_phandle(dp->dn, "phy-handle", 0); 3546 3547 if (phy_handle && !of_property_read_u32(phy_handle, 3548 "tx-p2p-microvolt", 3549 &tx_amp)) 3550 err = chip->info->ops->serdes_set_tx_amplitude(chip, 3551 port, tx_amp); 3552 if (phy_handle) { 3553 of_node_put(phy_handle); 3554 if (err) 3555 return err; 3556 } 3557 } 3558 3559 /* Port based VLAN map: give each port the same default address 3560 * database, and allow bidirectional communication between the 3561 * CPU and DSA port(s), and the other ports. 3562 */ 3563 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3564 if (err) 3565 return err; 3566 3567 err = mv88e6xxx_port_vlan_map(chip, port); 3568 if (err) 3569 return err; 3570 3571 /* Default VLAN ID and priority: don't set a default VLAN 3572 * ID, and set the default packet priority to zero. 3573 */ 3574 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3575 } 3576 3577 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3578 { 3579 struct mv88e6xxx_chip *chip = ds->priv; 3580 3581 if (chip->info->ops->port_set_jumbo_size) 3582 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3583 else if (chip->info->ops->set_max_frame_size) 3584 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3585 return ETH_DATA_LEN; 3586 } 3587 3588 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3589 { 3590 struct mv88e6xxx_chip *chip = ds->priv; 3591 int ret = 0; 3592 3593 /* For families where we don't know how to alter the MTU, 3594 * just accept any value up to ETH_DATA_LEN 3595 */ 3596 if (!chip->info->ops->port_set_jumbo_size && 3597 !chip->info->ops->set_max_frame_size) { 3598 if (new_mtu > ETH_DATA_LEN) 3599 return -EINVAL; 3600 3601 return 0; 3602 } 3603 3604 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3605 new_mtu += EDSA_HLEN; 3606 3607 mv88e6xxx_reg_lock(chip); 3608 if (chip->info->ops->port_set_jumbo_size) 3609 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3610 else if (chip->info->ops->set_max_frame_size) 3611 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3612 mv88e6xxx_reg_unlock(chip); 3613 3614 return ret; 3615 } 3616 3617 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3618 struct phy_device *phydev) 3619 { 3620 struct mv88e6xxx_chip *chip = ds->priv; 3621 int err; 3622 3623 mv88e6xxx_reg_lock(chip); 3624 err = mv88e6xxx_serdes_power(chip, port, true); 3625 mv88e6xxx_reg_unlock(chip); 3626 3627 return err; 3628 } 3629 3630 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3631 { 3632 struct mv88e6xxx_chip *chip = ds->priv; 3633 3634 mv88e6xxx_reg_lock(chip); 3635 if (mv88e6xxx_serdes_power(chip, port, false)) 3636 dev_err(chip->dev, "failed to power off SERDES\n"); 3637 mv88e6xxx_reg_unlock(chip); 3638 } 3639 3640 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3641 unsigned int ageing_time) 3642 { 3643 struct mv88e6xxx_chip *chip = ds->priv; 3644 int err; 3645 3646 mv88e6xxx_reg_lock(chip); 3647 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3648 mv88e6xxx_reg_unlock(chip); 3649 3650 return err; 3651 } 3652 3653 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3654 { 3655 int err; 3656 3657 /* Initialize the statistics unit */ 3658 if (chip->info->ops->stats_set_histogram) { 3659 err = chip->info->ops->stats_set_histogram(chip); 3660 if (err) 3661 return err; 3662 } 3663 3664 return mv88e6xxx_g1_stats_clear(chip); 3665 } 3666 3667 /* Check if the errata has already been applied. */ 3668 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3669 { 3670 int port; 3671 int err; 3672 u16 val; 3673 3674 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3675 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3676 if (err) { 3677 dev_err(chip->dev, 3678 "Error reading hidden register: %d\n", err); 3679 return false; 3680 } 3681 if (val != 0x01c0) 3682 return false; 3683 } 3684 3685 return true; 3686 } 3687 3688 /* The 6390 copper ports have an errata which require poking magic 3689 * values into undocumented hidden registers and then performing a 3690 * software reset. 3691 */ 3692 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3693 { 3694 int port; 3695 int err; 3696 3697 if (mv88e6390_setup_errata_applied(chip)) 3698 return 0; 3699 3700 /* Set the ports into blocking mode */ 3701 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3702 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3703 if (err) 3704 return err; 3705 } 3706 3707 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3708 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3709 if (err) 3710 return err; 3711 } 3712 3713 return mv88e6xxx_software_reset(chip); 3714 } 3715 3716 /* prod_id for switch families which do not have a PHY model number */ 3717 static const u16 family_prod_id_table[] = { 3718 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3719 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3720 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3721 }; 3722 3723 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3724 { 3725 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3726 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3727 u16 prod_id; 3728 u16 val; 3729 int err; 3730 3731 if (!chip->info->ops->phy_read) 3732 return -EOPNOTSUPP; 3733 3734 mv88e6xxx_reg_lock(chip); 3735 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3736 mv88e6xxx_reg_unlock(chip); 3737 3738 /* Some internal PHYs don't have a model number. */ 3739 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3740 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3741 prod_id = family_prod_id_table[chip->info->family]; 3742 if (prod_id) 3743 val |= prod_id >> 4; 3744 } 3745 3746 return err ? err : val; 3747 } 3748 3749 static int mv88e6xxx_mdio_read_c45(struct mii_bus *bus, int phy, int devad, 3750 int reg) 3751 { 3752 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3753 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3754 u16 val; 3755 int err; 3756 3757 if (!chip->info->ops->phy_read_c45) 3758 return -EOPNOTSUPP; 3759 3760 mv88e6xxx_reg_lock(chip); 3761 err = chip->info->ops->phy_read_c45(chip, bus, phy, devad, reg, &val); 3762 mv88e6xxx_reg_unlock(chip); 3763 3764 return err ? err : val; 3765 } 3766 3767 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3768 { 3769 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3770 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3771 int err; 3772 3773 if (!chip->info->ops->phy_write) 3774 return -EOPNOTSUPP; 3775 3776 mv88e6xxx_reg_lock(chip); 3777 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3778 mv88e6xxx_reg_unlock(chip); 3779 3780 return err; 3781 } 3782 3783 static int mv88e6xxx_mdio_write_c45(struct mii_bus *bus, int phy, int devad, 3784 int reg, u16 val) 3785 { 3786 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3787 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3788 int err; 3789 3790 if (!chip->info->ops->phy_write_c45) 3791 return -EOPNOTSUPP; 3792 3793 mv88e6xxx_reg_lock(chip); 3794 err = chip->info->ops->phy_write_c45(chip, bus, phy, devad, reg, val); 3795 mv88e6xxx_reg_unlock(chip); 3796 3797 return err; 3798 } 3799 3800 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3801 struct device_node *np, 3802 bool external) 3803 { 3804 static int index; 3805 struct mv88e6xxx_mdio_bus *mdio_bus; 3806 struct mii_bus *bus; 3807 int err; 3808 3809 if (external) { 3810 mv88e6xxx_reg_lock(chip); 3811 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3812 mv88e6xxx_reg_unlock(chip); 3813 3814 if (err) 3815 return err; 3816 } 3817 3818 bus = mdiobus_alloc_size(sizeof(*mdio_bus)); 3819 if (!bus) 3820 return -ENOMEM; 3821 3822 mdio_bus = bus->priv; 3823 mdio_bus->bus = bus; 3824 mdio_bus->chip = chip; 3825 INIT_LIST_HEAD(&mdio_bus->list); 3826 mdio_bus->external = external; 3827 3828 if (np) { 3829 bus->name = np->full_name; 3830 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3831 } else { 3832 bus->name = "mv88e6xxx SMI"; 3833 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3834 } 3835 3836 bus->read = mv88e6xxx_mdio_read; 3837 bus->write = mv88e6xxx_mdio_write; 3838 bus->read_c45 = mv88e6xxx_mdio_read_c45; 3839 bus->write_c45 = mv88e6xxx_mdio_write_c45; 3840 bus->parent = chip->dev; 3841 bus->phy_mask = ~GENMASK(chip->info->phy_base_addr + 3842 mv88e6xxx_num_ports(chip) - 1, 3843 chip->info->phy_base_addr); 3844 3845 if (!external) { 3846 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3847 if (err) 3848 goto out; 3849 } 3850 3851 err = of_mdiobus_register(bus, np); 3852 if (err) { 3853 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3854 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3855 goto out; 3856 } 3857 3858 if (external) 3859 list_add_tail(&mdio_bus->list, &chip->mdios); 3860 else 3861 list_add(&mdio_bus->list, &chip->mdios); 3862 3863 return 0; 3864 3865 out: 3866 mdiobus_free(bus); 3867 return err; 3868 } 3869 3870 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3871 3872 { 3873 struct mv88e6xxx_mdio_bus *mdio_bus, *p; 3874 struct mii_bus *bus; 3875 3876 list_for_each_entry_safe(mdio_bus, p, &chip->mdios, list) { 3877 bus = mdio_bus->bus; 3878 3879 if (!mdio_bus->external) 3880 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3881 3882 mdiobus_unregister(bus); 3883 mdiobus_free(bus); 3884 } 3885 } 3886 3887 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip) 3888 { 3889 struct device_node *np = chip->dev->of_node; 3890 struct device_node *child; 3891 int err; 3892 3893 /* Always register one mdio bus for the internal/default mdio 3894 * bus. This maybe represented in the device tree, but is 3895 * optional. 3896 */ 3897 child = of_get_child_by_name(np, "mdio"); 3898 err = mv88e6xxx_mdio_register(chip, child, false); 3899 of_node_put(child); 3900 if (err) 3901 return err; 3902 3903 /* Walk the device tree, and see if there are any other nodes 3904 * which say they are compatible with the external mdio 3905 * bus. 3906 */ 3907 for_each_available_child_of_node(np, child) { 3908 if (of_device_is_compatible( 3909 child, "marvell,mv88e6xxx-mdio-external")) { 3910 err = mv88e6xxx_mdio_register(chip, child, true); 3911 if (err) { 3912 mv88e6xxx_mdios_unregister(chip); 3913 of_node_put(child); 3914 return err; 3915 } 3916 } 3917 } 3918 3919 return 0; 3920 } 3921 3922 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3923 { 3924 struct mv88e6xxx_chip *chip = ds->priv; 3925 3926 mv88e6xxx_teardown_devlink_params(ds); 3927 dsa_devlink_resources_unregister(ds); 3928 mv88e6xxx_teardown_devlink_regions_global(ds); 3929 mv88e6xxx_mdios_unregister(chip); 3930 } 3931 3932 static int mv88e6xxx_setup(struct dsa_switch *ds) 3933 { 3934 struct mv88e6xxx_chip *chip = ds->priv; 3935 u8 cmode; 3936 int err; 3937 int i; 3938 3939 err = mv88e6xxx_mdios_register(chip); 3940 if (err) 3941 return err; 3942 3943 chip->ds = ds; 3944 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3945 3946 /* Since virtual bridges are mapped in the PVT, the number we support 3947 * depends on the physical switch topology. We need to let DSA figure 3948 * that out and therefore we cannot set this at dsa_register_switch() 3949 * time. 3950 */ 3951 if (mv88e6xxx_has_pvt(chip)) 3952 ds->max_num_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3953 ds->dst->last_switch - 1; 3954 3955 mv88e6xxx_reg_lock(chip); 3956 3957 if (chip->info->ops->setup_errata) { 3958 err = chip->info->ops->setup_errata(chip); 3959 if (err) 3960 goto unlock; 3961 } 3962 3963 /* Cache the cmode of each port. */ 3964 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3965 if (chip->info->ops->port_get_cmode) { 3966 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3967 if (err) 3968 goto unlock; 3969 3970 chip->ports[i].cmode = cmode; 3971 } 3972 } 3973 3974 err = mv88e6xxx_vtu_setup(chip); 3975 if (err) 3976 goto unlock; 3977 3978 /* Must be called after mv88e6xxx_vtu_setup (which flushes the 3979 * VTU, thereby also flushing the STU). 3980 */ 3981 err = mv88e6xxx_stu_setup(chip); 3982 if (err) 3983 goto unlock; 3984 3985 /* Setup Switch Port Registers */ 3986 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3987 if (dsa_is_unused_port(ds, i)) 3988 continue; 3989 3990 /* Prevent the use of an invalid port. */ 3991 if (mv88e6xxx_is_invalid_port(chip, i)) { 3992 dev_err(chip->dev, "port %d is invalid\n", i); 3993 err = -EINVAL; 3994 goto unlock; 3995 } 3996 3997 err = mv88e6xxx_setup_port(chip, i); 3998 if (err) 3999 goto unlock; 4000 } 4001 4002 err = mv88e6xxx_irl_setup(chip); 4003 if (err) 4004 goto unlock; 4005 4006 err = mv88e6xxx_mac_setup(chip); 4007 if (err) 4008 goto unlock; 4009 4010 err = mv88e6xxx_phy_setup(chip); 4011 if (err) 4012 goto unlock; 4013 4014 err = mv88e6xxx_pvt_setup(chip); 4015 if (err) 4016 goto unlock; 4017 4018 err = mv88e6xxx_atu_setup(chip); 4019 if (err) 4020 goto unlock; 4021 4022 err = mv88e6xxx_broadcast_setup(chip, 0); 4023 if (err) 4024 goto unlock; 4025 4026 err = mv88e6xxx_pot_setup(chip); 4027 if (err) 4028 goto unlock; 4029 4030 err = mv88e6xxx_rmu_setup(chip); 4031 if (err) 4032 goto unlock; 4033 4034 err = mv88e6xxx_rsvd2cpu_setup(chip); 4035 if (err) 4036 goto unlock; 4037 4038 err = mv88e6xxx_trunk_setup(chip); 4039 if (err) 4040 goto unlock; 4041 4042 err = mv88e6xxx_devmap_setup(chip); 4043 if (err) 4044 goto unlock; 4045 4046 err = mv88e6xxx_pri_setup(chip); 4047 if (err) 4048 goto unlock; 4049 4050 /* Setup PTP Hardware Clock and timestamping */ 4051 if (chip->info->ptp_support) { 4052 err = mv88e6xxx_ptp_setup(chip); 4053 if (err) 4054 goto unlock; 4055 4056 err = mv88e6xxx_hwtstamp_setup(chip); 4057 if (err) 4058 goto unlock; 4059 } 4060 4061 err = mv88e6xxx_stats_setup(chip); 4062 if (err) 4063 goto unlock; 4064 4065 unlock: 4066 mv88e6xxx_reg_unlock(chip); 4067 4068 if (err) 4069 goto out_mdios; 4070 4071 /* Have to be called without holding the register lock, since 4072 * they take the devlink lock, and we later take the locks in 4073 * the reverse order when getting/setting parameters or 4074 * resource occupancy. 4075 */ 4076 err = mv88e6xxx_setup_devlink_resources(ds); 4077 if (err) 4078 goto out_mdios; 4079 4080 err = mv88e6xxx_setup_devlink_params(ds); 4081 if (err) 4082 goto out_resources; 4083 4084 err = mv88e6xxx_setup_devlink_regions_global(ds); 4085 if (err) 4086 goto out_params; 4087 4088 return 0; 4089 4090 out_params: 4091 mv88e6xxx_teardown_devlink_params(ds); 4092 out_resources: 4093 dsa_devlink_resources_unregister(ds); 4094 out_mdios: 4095 mv88e6xxx_mdios_unregister(chip); 4096 4097 return err; 4098 } 4099 4100 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 4101 { 4102 return mv88e6xxx_setup_devlink_regions_port(ds, port); 4103 } 4104 4105 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 4106 { 4107 mv88e6xxx_teardown_devlink_regions_port(ds, port); 4108 } 4109 4110 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 4111 { 4112 struct mv88e6xxx_chip *chip = ds->priv; 4113 4114 return chip->eeprom_len; 4115 } 4116 4117 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 4118 struct ethtool_eeprom *eeprom, u8 *data) 4119 { 4120 struct mv88e6xxx_chip *chip = ds->priv; 4121 int err; 4122 4123 if (!chip->info->ops->get_eeprom) 4124 return -EOPNOTSUPP; 4125 4126 mv88e6xxx_reg_lock(chip); 4127 err = chip->info->ops->get_eeprom(chip, eeprom, data); 4128 mv88e6xxx_reg_unlock(chip); 4129 4130 if (err) 4131 return err; 4132 4133 eeprom->magic = 0xc3ec4951; 4134 4135 return 0; 4136 } 4137 4138 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 4139 struct ethtool_eeprom *eeprom, u8 *data) 4140 { 4141 struct mv88e6xxx_chip *chip = ds->priv; 4142 int err; 4143 4144 if (!chip->info->ops->set_eeprom) 4145 return -EOPNOTSUPP; 4146 4147 if (eeprom->magic != 0xc3ec4951) 4148 return -EINVAL; 4149 4150 mv88e6xxx_reg_lock(chip); 4151 err = chip->info->ops->set_eeprom(chip, eeprom, data); 4152 mv88e6xxx_reg_unlock(chip); 4153 4154 return err; 4155 } 4156 4157 static const struct mv88e6xxx_ops mv88e6085_ops = { 4158 /* MV88E6XXX_FAMILY_6097 */ 4159 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4160 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4161 .irl_init_all = mv88e6352_g2_irl_init_all, 4162 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4163 .phy_read = mv88e6185_phy_ppu_read, 4164 .phy_write = mv88e6185_phy_ppu_write, 4165 .port_set_link = mv88e6xxx_port_set_link, 4166 .port_sync_link = mv88e6xxx_port_sync_link, 4167 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4168 .port_tag_remap = mv88e6095_port_tag_remap, 4169 .port_set_policy = mv88e6352_port_set_policy, 4170 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4171 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4172 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4173 .port_set_ether_type = mv88e6351_port_set_ether_type, 4174 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4175 .port_pause_limit = mv88e6097_port_pause_limit, 4176 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4177 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4178 .port_get_cmode = mv88e6185_port_get_cmode, 4179 .port_setup_message_port = mv88e6xxx_setup_message_port, 4180 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4181 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4182 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4183 .stats_get_strings = mv88e6095_stats_get_strings, 4184 .stats_get_stats = mv88e6095_stats_get_stats, 4185 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4186 .set_egress_port = mv88e6095_g1_set_egress_port, 4187 .watchdog_ops = &mv88e6097_watchdog_ops, 4188 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4189 .pot_clear = mv88e6xxx_g2_pot_clear, 4190 .ppu_enable = mv88e6185_g1_ppu_enable, 4191 .ppu_disable = mv88e6185_g1_ppu_disable, 4192 .reset = mv88e6185_g1_reset, 4193 .rmu_disable = mv88e6085_g1_rmu_disable, 4194 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4195 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4196 .stu_getnext = mv88e6352_g1_stu_getnext, 4197 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4198 .phylink_get_caps = mv88e6185_phylink_get_caps, 4199 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4200 }; 4201 4202 static const struct mv88e6xxx_ops mv88e6095_ops = { 4203 /* MV88E6XXX_FAMILY_6095 */ 4204 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4205 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4206 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4207 .phy_read = mv88e6185_phy_ppu_read, 4208 .phy_write = mv88e6185_phy_ppu_write, 4209 .port_set_link = mv88e6xxx_port_set_link, 4210 .port_sync_link = mv88e6185_port_sync_link, 4211 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4212 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4213 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4214 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4215 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4216 .port_get_cmode = mv88e6185_port_get_cmode, 4217 .port_setup_message_port = mv88e6xxx_setup_message_port, 4218 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4219 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4220 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4221 .stats_get_strings = mv88e6095_stats_get_strings, 4222 .stats_get_stats = mv88e6095_stats_get_stats, 4223 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4224 .serdes_power = mv88e6185_serdes_power, 4225 .serdes_get_lane = mv88e6185_serdes_get_lane, 4226 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4227 .ppu_enable = mv88e6185_g1_ppu_enable, 4228 .ppu_disable = mv88e6185_g1_ppu_disable, 4229 .reset = mv88e6185_g1_reset, 4230 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4231 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4232 .phylink_get_caps = mv88e6095_phylink_get_caps, 4233 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4234 }; 4235 4236 static const struct mv88e6xxx_ops mv88e6097_ops = { 4237 /* MV88E6XXX_FAMILY_6097 */ 4238 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4239 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4240 .irl_init_all = mv88e6352_g2_irl_init_all, 4241 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4242 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4243 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4244 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4245 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4246 .port_set_link = mv88e6xxx_port_set_link, 4247 .port_sync_link = mv88e6185_port_sync_link, 4248 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4249 .port_tag_remap = mv88e6095_port_tag_remap, 4250 .port_set_policy = mv88e6352_port_set_policy, 4251 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4252 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4253 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4254 .port_set_ether_type = mv88e6351_port_set_ether_type, 4255 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4256 .port_pause_limit = mv88e6097_port_pause_limit, 4257 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4258 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4259 .port_get_cmode = mv88e6185_port_get_cmode, 4260 .port_setup_message_port = mv88e6xxx_setup_message_port, 4261 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4262 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4263 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4264 .stats_get_strings = mv88e6095_stats_get_strings, 4265 .stats_get_stats = mv88e6095_stats_get_stats, 4266 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4267 .set_egress_port = mv88e6095_g1_set_egress_port, 4268 .watchdog_ops = &mv88e6097_watchdog_ops, 4269 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4270 .serdes_power = mv88e6185_serdes_power, 4271 .serdes_get_lane = mv88e6185_serdes_get_lane, 4272 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4273 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4274 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 4275 .serdes_irq_status = mv88e6097_serdes_irq_status, 4276 .pot_clear = mv88e6xxx_g2_pot_clear, 4277 .reset = mv88e6352_g1_reset, 4278 .rmu_disable = mv88e6085_g1_rmu_disable, 4279 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4280 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4281 .phylink_get_caps = mv88e6095_phylink_get_caps, 4282 .stu_getnext = mv88e6352_g1_stu_getnext, 4283 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4284 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4285 }; 4286 4287 static const struct mv88e6xxx_ops mv88e6123_ops = { 4288 /* MV88E6XXX_FAMILY_6165 */ 4289 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4290 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4291 .irl_init_all = mv88e6352_g2_irl_init_all, 4292 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4293 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4294 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4295 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4296 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4297 .port_set_link = mv88e6xxx_port_set_link, 4298 .port_sync_link = mv88e6xxx_port_sync_link, 4299 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4300 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4301 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4302 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4303 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4304 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4305 .port_get_cmode = mv88e6185_port_get_cmode, 4306 .port_setup_message_port = mv88e6xxx_setup_message_port, 4307 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4308 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4309 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4310 .stats_get_strings = mv88e6095_stats_get_strings, 4311 .stats_get_stats = mv88e6095_stats_get_stats, 4312 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4313 .set_egress_port = mv88e6095_g1_set_egress_port, 4314 .watchdog_ops = &mv88e6097_watchdog_ops, 4315 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4316 .pot_clear = mv88e6xxx_g2_pot_clear, 4317 .reset = mv88e6352_g1_reset, 4318 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4319 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4320 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4321 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4322 .stu_getnext = mv88e6352_g1_stu_getnext, 4323 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4324 .phylink_get_caps = mv88e6185_phylink_get_caps, 4325 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4326 }; 4327 4328 static const struct mv88e6xxx_ops mv88e6131_ops = { 4329 /* MV88E6XXX_FAMILY_6185 */ 4330 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4331 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4332 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4333 .phy_read = mv88e6185_phy_ppu_read, 4334 .phy_write = mv88e6185_phy_ppu_write, 4335 .port_set_link = mv88e6xxx_port_set_link, 4336 .port_sync_link = mv88e6xxx_port_sync_link, 4337 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4338 .port_tag_remap = mv88e6095_port_tag_remap, 4339 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4340 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4341 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4342 .port_set_ether_type = mv88e6351_port_set_ether_type, 4343 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4344 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4345 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4346 .port_pause_limit = mv88e6097_port_pause_limit, 4347 .port_set_pause = mv88e6185_port_set_pause, 4348 .port_get_cmode = mv88e6185_port_get_cmode, 4349 .port_setup_message_port = mv88e6xxx_setup_message_port, 4350 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4351 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4352 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4353 .stats_get_strings = mv88e6095_stats_get_strings, 4354 .stats_get_stats = mv88e6095_stats_get_stats, 4355 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4356 .set_egress_port = mv88e6095_g1_set_egress_port, 4357 .watchdog_ops = &mv88e6097_watchdog_ops, 4358 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4359 .ppu_enable = mv88e6185_g1_ppu_enable, 4360 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4361 .ppu_disable = mv88e6185_g1_ppu_disable, 4362 .reset = mv88e6185_g1_reset, 4363 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4364 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4365 .phylink_get_caps = mv88e6185_phylink_get_caps, 4366 }; 4367 4368 static const struct mv88e6xxx_ops mv88e6141_ops = { 4369 /* MV88E6XXX_FAMILY_6341 */ 4370 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4371 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4372 .irl_init_all = mv88e6352_g2_irl_init_all, 4373 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4374 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4375 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4376 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4377 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4378 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4379 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4380 .port_set_link = mv88e6xxx_port_set_link, 4381 .port_sync_link = mv88e6xxx_port_sync_link, 4382 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4383 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4384 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4385 .port_tag_remap = mv88e6095_port_tag_remap, 4386 .port_set_policy = mv88e6352_port_set_policy, 4387 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4388 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4389 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4390 .port_set_ether_type = mv88e6351_port_set_ether_type, 4391 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4392 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4393 .port_pause_limit = mv88e6097_port_pause_limit, 4394 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4395 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4396 .port_get_cmode = mv88e6352_port_get_cmode, 4397 .port_set_cmode = mv88e6341_port_set_cmode, 4398 .port_setup_message_port = mv88e6xxx_setup_message_port, 4399 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4400 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4401 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4402 .stats_get_strings = mv88e6320_stats_get_strings, 4403 .stats_get_stats = mv88e6390_stats_get_stats, 4404 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4405 .set_egress_port = mv88e6390_g1_set_egress_port, 4406 .watchdog_ops = &mv88e6390_watchdog_ops, 4407 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4408 .pot_clear = mv88e6xxx_g2_pot_clear, 4409 .reset = mv88e6352_g1_reset, 4410 .rmu_disable = mv88e6390_g1_rmu_disable, 4411 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4412 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4413 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4414 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4415 .stu_getnext = mv88e6352_g1_stu_getnext, 4416 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4417 .serdes_power = mv88e6390_serdes_power, 4418 .serdes_get_lane = mv88e6341_serdes_get_lane, 4419 /* Check status register pause & lpa register */ 4420 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4421 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4422 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4423 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4424 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4425 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4426 .serdes_irq_status = mv88e6390_serdes_irq_status, 4427 .gpio_ops = &mv88e6352_gpio_ops, 4428 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4429 .serdes_get_strings = mv88e6390_serdes_get_strings, 4430 .serdes_get_stats = mv88e6390_serdes_get_stats, 4431 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4432 .serdes_get_regs = mv88e6390_serdes_get_regs, 4433 .phylink_get_caps = mv88e6341_phylink_get_caps, 4434 }; 4435 4436 static const struct mv88e6xxx_ops mv88e6161_ops = { 4437 /* MV88E6XXX_FAMILY_6165 */ 4438 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4439 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4440 .irl_init_all = mv88e6352_g2_irl_init_all, 4441 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4442 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4443 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4444 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4445 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4446 .port_set_link = mv88e6xxx_port_set_link, 4447 .port_sync_link = mv88e6xxx_port_sync_link, 4448 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4449 .port_tag_remap = mv88e6095_port_tag_remap, 4450 .port_set_policy = mv88e6352_port_set_policy, 4451 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4452 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4453 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4454 .port_set_ether_type = mv88e6351_port_set_ether_type, 4455 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4456 .port_pause_limit = mv88e6097_port_pause_limit, 4457 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4458 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4459 .port_get_cmode = mv88e6185_port_get_cmode, 4460 .port_setup_message_port = mv88e6xxx_setup_message_port, 4461 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4462 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4463 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4464 .stats_get_strings = mv88e6095_stats_get_strings, 4465 .stats_get_stats = mv88e6095_stats_get_stats, 4466 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4467 .set_egress_port = mv88e6095_g1_set_egress_port, 4468 .watchdog_ops = &mv88e6097_watchdog_ops, 4469 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4470 .pot_clear = mv88e6xxx_g2_pot_clear, 4471 .reset = mv88e6352_g1_reset, 4472 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4473 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4474 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4475 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4476 .stu_getnext = mv88e6352_g1_stu_getnext, 4477 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4478 .avb_ops = &mv88e6165_avb_ops, 4479 .ptp_ops = &mv88e6165_ptp_ops, 4480 .phylink_get_caps = mv88e6185_phylink_get_caps, 4481 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4482 }; 4483 4484 static const struct mv88e6xxx_ops mv88e6165_ops = { 4485 /* MV88E6XXX_FAMILY_6165 */ 4486 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4487 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4488 .irl_init_all = mv88e6352_g2_irl_init_all, 4489 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4490 .phy_read = mv88e6165_phy_read, 4491 .phy_write = mv88e6165_phy_write, 4492 .port_set_link = mv88e6xxx_port_set_link, 4493 .port_sync_link = mv88e6xxx_port_sync_link, 4494 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4495 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4496 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4497 .port_get_cmode = mv88e6185_port_get_cmode, 4498 .port_setup_message_port = mv88e6xxx_setup_message_port, 4499 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4500 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4501 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4502 .stats_get_strings = mv88e6095_stats_get_strings, 4503 .stats_get_stats = mv88e6095_stats_get_stats, 4504 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4505 .set_egress_port = mv88e6095_g1_set_egress_port, 4506 .watchdog_ops = &mv88e6097_watchdog_ops, 4507 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4508 .pot_clear = mv88e6xxx_g2_pot_clear, 4509 .reset = mv88e6352_g1_reset, 4510 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4511 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4512 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4513 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4514 .stu_getnext = mv88e6352_g1_stu_getnext, 4515 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4516 .avb_ops = &mv88e6165_avb_ops, 4517 .ptp_ops = &mv88e6165_ptp_ops, 4518 .phylink_get_caps = mv88e6185_phylink_get_caps, 4519 }; 4520 4521 static const struct mv88e6xxx_ops mv88e6171_ops = { 4522 /* MV88E6XXX_FAMILY_6351 */ 4523 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4524 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4525 .irl_init_all = mv88e6352_g2_irl_init_all, 4526 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4527 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4528 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4529 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4530 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4531 .port_set_link = mv88e6xxx_port_set_link, 4532 .port_sync_link = mv88e6xxx_port_sync_link, 4533 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4534 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4535 .port_tag_remap = mv88e6095_port_tag_remap, 4536 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4537 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4538 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4539 .port_set_ether_type = mv88e6351_port_set_ether_type, 4540 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4541 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4542 .port_pause_limit = mv88e6097_port_pause_limit, 4543 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4544 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4545 .port_get_cmode = mv88e6352_port_get_cmode, 4546 .port_setup_message_port = mv88e6xxx_setup_message_port, 4547 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4548 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4549 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4550 .stats_get_strings = mv88e6095_stats_get_strings, 4551 .stats_get_stats = mv88e6095_stats_get_stats, 4552 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4553 .set_egress_port = mv88e6095_g1_set_egress_port, 4554 .watchdog_ops = &mv88e6097_watchdog_ops, 4555 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4556 .pot_clear = mv88e6xxx_g2_pot_clear, 4557 .reset = mv88e6352_g1_reset, 4558 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4559 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4560 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4561 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4562 .stu_getnext = mv88e6352_g1_stu_getnext, 4563 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4564 .phylink_get_caps = mv88e6185_phylink_get_caps, 4565 }; 4566 4567 static const struct mv88e6xxx_ops mv88e6172_ops = { 4568 /* MV88E6XXX_FAMILY_6352 */ 4569 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4570 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4571 .irl_init_all = mv88e6352_g2_irl_init_all, 4572 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4573 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4574 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4575 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4576 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4577 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4578 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4579 .port_set_link = mv88e6xxx_port_set_link, 4580 .port_sync_link = mv88e6xxx_port_sync_link, 4581 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4582 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4583 .port_tag_remap = mv88e6095_port_tag_remap, 4584 .port_set_policy = mv88e6352_port_set_policy, 4585 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4586 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4587 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4588 .port_set_ether_type = mv88e6351_port_set_ether_type, 4589 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4590 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4591 .port_pause_limit = mv88e6097_port_pause_limit, 4592 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4593 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4594 .port_get_cmode = mv88e6352_port_get_cmode, 4595 .port_setup_message_port = mv88e6xxx_setup_message_port, 4596 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4597 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4598 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4599 .stats_get_strings = mv88e6095_stats_get_strings, 4600 .stats_get_stats = mv88e6095_stats_get_stats, 4601 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4602 .set_egress_port = mv88e6095_g1_set_egress_port, 4603 .watchdog_ops = &mv88e6097_watchdog_ops, 4604 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4605 .pot_clear = mv88e6xxx_g2_pot_clear, 4606 .reset = mv88e6352_g1_reset, 4607 .rmu_disable = mv88e6352_g1_rmu_disable, 4608 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4609 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4610 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4611 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4612 .stu_getnext = mv88e6352_g1_stu_getnext, 4613 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4614 .serdes_get_lane = mv88e6352_serdes_get_lane, 4615 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4616 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4617 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4618 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4619 .serdes_power = mv88e6352_serdes_power, 4620 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4621 .serdes_get_regs = mv88e6352_serdes_get_regs, 4622 .gpio_ops = &mv88e6352_gpio_ops, 4623 .phylink_get_caps = mv88e6352_phylink_get_caps, 4624 }; 4625 4626 static const struct mv88e6xxx_ops mv88e6175_ops = { 4627 /* MV88E6XXX_FAMILY_6351 */ 4628 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4629 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4630 .irl_init_all = mv88e6352_g2_irl_init_all, 4631 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4632 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4633 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4634 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4635 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4636 .port_set_link = mv88e6xxx_port_set_link, 4637 .port_sync_link = mv88e6xxx_port_sync_link, 4638 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4639 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4640 .port_tag_remap = mv88e6095_port_tag_remap, 4641 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4642 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4643 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4644 .port_set_ether_type = mv88e6351_port_set_ether_type, 4645 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4646 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4647 .port_pause_limit = mv88e6097_port_pause_limit, 4648 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4649 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4650 .port_get_cmode = mv88e6352_port_get_cmode, 4651 .port_setup_message_port = mv88e6xxx_setup_message_port, 4652 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4653 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4654 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4655 .stats_get_strings = mv88e6095_stats_get_strings, 4656 .stats_get_stats = mv88e6095_stats_get_stats, 4657 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4658 .set_egress_port = mv88e6095_g1_set_egress_port, 4659 .watchdog_ops = &mv88e6097_watchdog_ops, 4660 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4661 .pot_clear = mv88e6xxx_g2_pot_clear, 4662 .reset = mv88e6352_g1_reset, 4663 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4664 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4665 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4666 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4667 .stu_getnext = mv88e6352_g1_stu_getnext, 4668 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4669 .phylink_get_caps = mv88e6185_phylink_get_caps, 4670 }; 4671 4672 static const struct mv88e6xxx_ops mv88e6176_ops = { 4673 /* MV88E6XXX_FAMILY_6352 */ 4674 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4675 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4676 .irl_init_all = mv88e6352_g2_irl_init_all, 4677 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4678 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4679 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4680 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4681 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4682 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4683 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4684 .port_set_link = mv88e6xxx_port_set_link, 4685 .port_sync_link = mv88e6xxx_port_sync_link, 4686 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4687 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4688 .port_tag_remap = mv88e6095_port_tag_remap, 4689 .port_set_policy = mv88e6352_port_set_policy, 4690 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4691 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4692 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4693 .port_set_ether_type = mv88e6351_port_set_ether_type, 4694 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4695 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4696 .port_pause_limit = mv88e6097_port_pause_limit, 4697 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4698 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4699 .port_get_cmode = mv88e6352_port_get_cmode, 4700 .port_setup_message_port = mv88e6xxx_setup_message_port, 4701 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4702 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4703 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4704 .stats_get_strings = mv88e6095_stats_get_strings, 4705 .stats_get_stats = mv88e6095_stats_get_stats, 4706 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4707 .set_egress_port = mv88e6095_g1_set_egress_port, 4708 .watchdog_ops = &mv88e6097_watchdog_ops, 4709 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4710 .pot_clear = mv88e6xxx_g2_pot_clear, 4711 .reset = mv88e6352_g1_reset, 4712 .rmu_disable = mv88e6352_g1_rmu_disable, 4713 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4714 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4715 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4716 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4717 .stu_getnext = mv88e6352_g1_stu_getnext, 4718 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 4719 .serdes_get_lane = mv88e6352_serdes_get_lane, 4720 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4721 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4722 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4723 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4724 .serdes_power = mv88e6352_serdes_power, 4725 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4726 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4727 .serdes_irq_status = mv88e6352_serdes_irq_status, 4728 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4729 .serdes_get_regs = mv88e6352_serdes_get_regs, 4730 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 4731 .gpio_ops = &mv88e6352_gpio_ops, 4732 .phylink_get_caps = mv88e6352_phylink_get_caps, 4733 }; 4734 4735 static const struct mv88e6xxx_ops mv88e6185_ops = { 4736 /* MV88E6XXX_FAMILY_6185 */ 4737 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4738 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4739 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4740 .phy_read = mv88e6185_phy_ppu_read, 4741 .phy_write = mv88e6185_phy_ppu_write, 4742 .port_set_link = mv88e6xxx_port_set_link, 4743 .port_sync_link = mv88e6185_port_sync_link, 4744 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4745 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4746 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4747 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4748 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4749 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4750 .port_set_pause = mv88e6185_port_set_pause, 4751 .port_get_cmode = mv88e6185_port_get_cmode, 4752 .port_setup_message_port = mv88e6xxx_setup_message_port, 4753 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4754 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4755 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4756 .stats_get_strings = mv88e6095_stats_get_strings, 4757 .stats_get_stats = mv88e6095_stats_get_stats, 4758 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4759 .set_egress_port = mv88e6095_g1_set_egress_port, 4760 .watchdog_ops = &mv88e6097_watchdog_ops, 4761 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4762 .serdes_power = mv88e6185_serdes_power, 4763 .serdes_get_lane = mv88e6185_serdes_get_lane, 4764 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4765 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4766 .ppu_enable = mv88e6185_g1_ppu_enable, 4767 .ppu_disable = mv88e6185_g1_ppu_disable, 4768 .reset = mv88e6185_g1_reset, 4769 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4770 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4771 .phylink_get_caps = mv88e6185_phylink_get_caps, 4772 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4773 }; 4774 4775 static const struct mv88e6xxx_ops mv88e6190_ops = { 4776 /* MV88E6XXX_FAMILY_6390 */ 4777 .setup_errata = mv88e6390_setup_errata, 4778 .irl_init_all = mv88e6390_g2_irl_init_all, 4779 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4780 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4781 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4782 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4783 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4784 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4785 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4786 .port_set_link = mv88e6xxx_port_set_link, 4787 .port_sync_link = mv88e6xxx_port_sync_link, 4788 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4789 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4790 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4791 .port_tag_remap = mv88e6390_port_tag_remap, 4792 .port_set_policy = mv88e6352_port_set_policy, 4793 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4794 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4795 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4796 .port_set_ether_type = mv88e6351_port_set_ether_type, 4797 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4798 .port_pause_limit = mv88e6390_port_pause_limit, 4799 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4800 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4801 .port_get_cmode = mv88e6352_port_get_cmode, 4802 .port_set_cmode = mv88e6390_port_set_cmode, 4803 .port_setup_message_port = mv88e6xxx_setup_message_port, 4804 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4805 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4806 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4807 .stats_get_strings = mv88e6320_stats_get_strings, 4808 .stats_get_stats = mv88e6390_stats_get_stats, 4809 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4810 .set_egress_port = mv88e6390_g1_set_egress_port, 4811 .watchdog_ops = &mv88e6390_watchdog_ops, 4812 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4813 .pot_clear = mv88e6xxx_g2_pot_clear, 4814 .reset = mv88e6352_g1_reset, 4815 .rmu_disable = mv88e6390_g1_rmu_disable, 4816 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4817 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4818 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4819 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4820 .stu_getnext = mv88e6390_g1_stu_getnext, 4821 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4822 .serdes_power = mv88e6390_serdes_power, 4823 .serdes_get_lane = mv88e6390_serdes_get_lane, 4824 /* Check status register pause & lpa register */ 4825 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4826 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4827 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4828 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4829 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4830 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4831 .serdes_irq_status = mv88e6390_serdes_irq_status, 4832 .serdes_get_strings = mv88e6390_serdes_get_strings, 4833 .serdes_get_stats = mv88e6390_serdes_get_stats, 4834 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4835 .serdes_get_regs = mv88e6390_serdes_get_regs, 4836 .gpio_ops = &mv88e6352_gpio_ops, 4837 .phylink_get_caps = mv88e6390_phylink_get_caps, 4838 }; 4839 4840 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4841 /* MV88E6XXX_FAMILY_6390 */ 4842 .setup_errata = mv88e6390_setup_errata, 4843 .irl_init_all = mv88e6390_g2_irl_init_all, 4844 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4845 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4846 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4847 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4848 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4849 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4850 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4851 .port_set_link = mv88e6xxx_port_set_link, 4852 .port_sync_link = mv88e6xxx_port_sync_link, 4853 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4854 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4855 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4856 .port_tag_remap = mv88e6390_port_tag_remap, 4857 .port_set_policy = mv88e6352_port_set_policy, 4858 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4859 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4860 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4861 .port_set_ether_type = mv88e6351_port_set_ether_type, 4862 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4863 .port_pause_limit = mv88e6390_port_pause_limit, 4864 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4865 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4866 .port_get_cmode = mv88e6352_port_get_cmode, 4867 .port_set_cmode = mv88e6390x_port_set_cmode, 4868 .port_setup_message_port = mv88e6xxx_setup_message_port, 4869 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4870 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4871 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4872 .stats_get_strings = mv88e6320_stats_get_strings, 4873 .stats_get_stats = mv88e6390_stats_get_stats, 4874 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4875 .set_egress_port = mv88e6390_g1_set_egress_port, 4876 .watchdog_ops = &mv88e6390_watchdog_ops, 4877 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4878 .pot_clear = mv88e6xxx_g2_pot_clear, 4879 .reset = mv88e6352_g1_reset, 4880 .rmu_disable = mv88e6390_g1_rmu_disable, 4881 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4882 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4883 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4884 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4885 .stu_getnext = mv88e6390_g1_stu_getnext, 4886 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4887 .serdes_power = mv88e6390_serdes_power, 4888 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4889 /* Check status register pause & lpa register */ 4890 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4891 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4892 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4893 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4894 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4895 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4896 .serdes_irq_status = mv88e6390_serdes_irq_status, 4897 .serdes_get_strings = mv88e6390_serdes_get_strings, 4898 .serdes_get_stats = mv88e6390_serdes_get_stats, 4899 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4900 .serdes_get_regs = mv88e6390_serdes_get_regs, 4901 .gpio_ops = &mv88e6352_gpio_ops, 4902 .phylink_get_caps = mv88e6390x_phylink_get_caps, 4903 }; 4904 4905 static const struct mv88e6xxx_ops mv88e6191_ops = { 4906 /* MV88E6XXX_FAMILY_6390 */ 4907 .setup_errata = mv88e6390_setup_errata, 4908 .irl_init_all = mv88e6390_g2_irl_init_all, 4909 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4910 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4911 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4912 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4913 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4914 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4915 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4916 .port_set_link = mv88e6xxx_port_set_link, 4917 .port_sync_link = mv88e6xxx_port_sync_link, 4918 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4919 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4920 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4921 .port_tag_remap = mv88e6390_port_tag_remap, 4922 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4923 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4924 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4925 .port_set_ether_type = mv88e6351_port_set_ether_type, 4926 .port_pause_limit = mv88e6390_port_pause_limit, 4927 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4928 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4929 .port_get_cmode = mv88e6352_port_get_cmode, 4930 .port_set_cmode = mv88e6390_port_set_cmode, 4931 .port_setup_message_port = mv88e6xxx_setup_message_port, 4932 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4933 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4934 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4935 .stats_get_strings = mv88e6320_stats_get_strings, 4936 .stats_get_stats = mv88e6390_stats_get_stats, 4937 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4938 .set_egress_port = mv88e6390_g1_set_egress_port, 4939 .watchdog_ops = &mv88e6390_watchdog_ops, 4940 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4941 .pot_clear = mv88e6xxx_g2_pot_clear, 4942 .reset = mv88e6352_g1_reset, 4943 .rmu_disable = mv88e6390_g1_rmu_disable, 4944 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4945 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4946 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4947 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4948 .stu_getnext = mv88e6390_g1_stu_getnext, 4949 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 4950 .serdes_power = mv88e6390_serdes_power, 4951 .serdes_get_lane = mv88e6390_serdes_get_lane, 4952 /* Check status register pause & lpa register */ 4953 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4954 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4955 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4956 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4957 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4958 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4959 .serdes_irq_status = mv88e6390_serdes_irq_status, 4960 .serdes_get_strings = mv88e6390_serdes_get_strings, 4961 .serdes_get_stats = mv88e6390_serdes_get_stats, 4962 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4963 .serdes_get_regs = mv88e6390_serdes_get_regs, 4964 .avb_ops = &mv88e6390_avb_ops, 4965 .ptp_ops = &mv88e6352_ptp_ops, 4966 .phylink_get_caps = mv88e6390_phylink_get_caps, 4967 }; 4968 4969 static const struct mv88e6xxx_ops mv88e6240_ops = { 4970 /* MV88E6XXX_FAMILY_6352 */ 4971 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4972 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4973 .irl_init_all = mv88e6352_g2_irl_init_all, 4974 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4975 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4976 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4977 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 4978 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 4979 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 4980 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 4981 .port_set_link = mv88e6xxx_port_set_link, 4982 .port_sync_link = mv88e6xxx_port_sync_link, 4983 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4984 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4985 .port_tag_remap = mv88e6095_port_tag_remap, 4986 .port_set_policy = mv88e6352_port_set_policy, 4987 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4988 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4989 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4990 .port_set_ether_type = mv88e6351_port_set_ether_type, 4991 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4992 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4993 .port_pause_limit = mv88e6097_port_pause_limit, 4994 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4995 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4996 .port_get_cmode = mv88e6352_port_get_cmode, 4997 .port_setup_message_port = mv88e6xxx_setup_message_port, 4998 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4999 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5000 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5001 .stats_get_strings = mv88e6095_stats_get_strings, 5002 .stats_get_stats = mv88e6095_stats_get_stats, 5003 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5004 .set_egress_port = mv88e6095_g1_set_egress_port, 5005 .watchdog_ops = &mv88e6097_watchdog_ops, 5006 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5007 .pot_clear = mv88e6xxx_g2_pot_clear, 5008 .reset = mv88e6352_g1_reset, 5009 .rmu_disable = mv88e6352_g1_rmu_disable, 5010 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5011 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5012 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5013 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5014 .stu_getnext = mv88e6352_g1_stu_getnext, 5015 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5016 .serdes_get_lane = mv88e6352_serdes_get_lane, 5017 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5018 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5019 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5020 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5021 .serdes_power = mv88e6352_serdes_power, 5022 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5023 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5024 .serdes_irq_status = mv88e6352_serdes_irq_status, 5025 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5026 .serdes_get_regs = mv88e6352_serdes_get_regs, 5027 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5028 .gpio_ops = &mv88e6352_gpio_ops, 5029 .avb_ops = &mv88e6352_avb_ops, 5030 .ptp_ops = &mv88e6352_ptp_ops, 5031 .phylink_get_caps = mv88e6352_phylink_get_caps, 5032 }; 5033 5034 static const struct mv88e6xxx_ops mv88e6250_ops = { 5035 /* MV88E6XXX_FAMILY_6250 */ 5036 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 5037 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5038 .irl_init_all = mv88e6352_g2_irl_init_all, 5039 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5040 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5041 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5042 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5043 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5044 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5045 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5046 .port_set_link = mv88e6xxx_port_set_link, 5047 .port_sync_link = mv88e6xxx_port_sync_link, 5048 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5049 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 5050 .port_tag_remap = mv88e6095_port_tag_remap, 5051 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5052 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5053 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5054 .port_set_ether_type = mv88e6351_port_set_ether_type, 5055 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5056 .port_pause_limit = mv88e6097_port_pause_limit, 5057 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5058 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5059 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5060 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 5061 .stats_get_strings = mv88e6250_stats_get_strings, 5062 .stats_get_stats = mv88e6250_stats_get_stats, 5063 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5064 .set_egress_port = mv88e6095_g1_set_egress_port, 5065 .watchdog_ops = &mv88e6250_watchdog_ops, 5066 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5067 .pot_clear = mv88e6xxx_g2_pot_clear, 5068 .reset = mv88e6250_g1_reset, 5069 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5070 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5071 .avb_ops = &mv88e6352_avb_ops, 5072 .ptp_ops = &mv88e6250_ptp_ops, 5073 .phylink_get_caps = mv88e6250_phylink_get_caps, 5074 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 5075 }; 5076 5077 static const struct mv88e6xxx_ops mv88e6290_ops = { 5078 /* MV88E6XXX_FAMILY_6390 */ 5079 .setup_errata = mv88e6390_setup_errata, 5080 .irl_init_all = mv88e6390_g2_irl_init_all, 5081 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5082 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5083 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5084 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5085 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5086 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5087 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5088 .port_set_link = mv88e6xxx_port_set_link, 5089 .port_sync_link = mv88e6xxx_port_sync_link, 5090 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5091 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5092 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5093 .port_tag_remap = mv88e6390_port_tag_remap, 5094 .port_set_policy = mv88e6352_port_set_policy, 5095 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5096 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5097 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5098 .port_set_ether_type = mv88e6351_port_set_ether_type, 5099 .port_pause_limit = mv88e6390_port_pause_limit, 5100 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5101 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5102 .port_get_cmode = mv88e6352_port_get_cmode, 5103 .port_set_cmode = mv88e6390_port_set_cmode, 5104 .port_setup_message_port = mv88e6xxx_setup_message_port, 5105 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5106 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5107 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5108 .stats_get_strings = mv88e6320_stats_get_strings, 5109 .stats_get_stats = mv88e6390_stats_get_stats, 5110 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5111 .set_egress_port = mv88e6390_g1_set_egress_port, 5112 .watchdog_ops = &mv88e6390_watchdog_ops, 5113 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5114 .pot_clear = mv88e6xxx_g2_pot_clear, 5115 .reset = mv88e6352_g1_reset, 5116 .rmu_disable = mv88e6390_g1_rmu_disable, 5117 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5118 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5119 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5120 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5121 .stu_getnext = mv88e6390_g1_stu_getnext, 5122 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5123 .serdes_power = mv88e6390_serdes_power, 5124 .serdes_get_lane = mv88e6390_serdes_get_lane, 5125 /* Check status register pause & lpa register */ 5126 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5127 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5128 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5129 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5130 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5131 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5132 .serdes_irq_status = mv88e6390_serdes_irq_status, 5133 .serdes_get_strings = mv88e6390_serdes_get_strings, 5134 .serdes_get_stats = mv88e6390_serdes_get_stats, 5135 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5136 .serdes_get_regs = mv88e6390_serdes_get_regs, 5137 .gpio_ops = &mv88e6352_gpio_ops, 5138 .avb_ops = &mv88e6390_avb_ops, 5139 .ptp_ops = &mv88e6390_ptp_ops, 5140 .phylink_get_caps = mv88e6390_phylink_get_caps, 5141 }; 5142 5143 static const struct mv88e6xxx_ops mv88e6320_ops = { 5144 /* MV88E6XXX_FAMILY_6320 */ 5145 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5146 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5147 .irl_init_all = mv88e6352_g2_irl_init_all, 5148 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5149 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5150 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5151 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5152 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5153 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5154 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5155 .port_set_link = mv88e6xxx_port_set_link, 5156 .port_sync_link = mv88e6xxx_port_sync_link, 5157 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5158 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5159 .port_tag_remap = mv88e6095_port_tag_remap, 5160 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5161 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5162 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5163 .port_set_ether_type = mv88e6351_port_set_ether_type, 5164 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5165 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5166 .port_pause_limit = mv88e6097_port_pause_limit, 5167 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5168 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5169 .port_get_cmode = mv88e6352_port_get_cmode, 5170 .port_setup_message_port = mv88e6xxx_setup_message_port, 5171 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5172 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5173 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5174 .stats_get_strings = mv88e6320_stats_get_strings, 5175 .stats_get_stats = mv88e6320_stats_get_stats, 5176 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5177 .set_egress_port = mv88e6095_g1_set_egress_port, 5178 .watchdog_ops = &mv88e6390_watchdog_ops, 5179 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5180 .pot_clear = mv88e6xxx_g2_pot_clear, 5181 .reset = mv88e6352_g1_reset, 5182 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5183 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5184 .gpio_ops = &mv88e6352_gpio_ops, 5185 .avb_ops = &mv88e6352_avb_ops, 5186 .ptp_ops = &mv88e6352_ptp_ops, 5187 .phylink_get_caps = mv88e6185_phylink_get_caps, 5188 }; 5189 5190 static const struct mv88e6xxx_ops mv88e6321_ops = { 5191 /* MV88E6XXX_FAMILY_6320 */ 5192 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5193 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5194 .irl_init_all = mv88e6352_g2_irl_init_all, 5195 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5196 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5197 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5198 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5199 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5200 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5201 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5202 .port_set_link = mv88e6xxx_port_set_link, 5203 .port_sync_link = mv88e6xxx_port_sync_link, 5204 .port_set_rgmii_delay = mv88e6320_port_set_rgmii_delay, 5205 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5206 .port_tag_remap = mv88e6095_port_tag_remap, 5207 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5208 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5209 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5210 .port_set_ether_type = mv88e6351_port_set_ether_type, 5211 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5212 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5213 .port_pause_limit = mv88e6097_port_pause_limit, 5214 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5215 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5216 .port_get_cmode = mv88e6352_port_get_cmode, 5217 .port_setup_message_port = mv88e6xxx_setup_message_port, 5218 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5219 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5220 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5221 .stats_get_strings = mv88e6320_stats_get_strings, 5222 .stats_get_stats = mv88e6320_stats_get_stats, 5223 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5224 .set_egress_port = mv88e6095_g1_set_egress_port, 5225 .watchdog_ops = &mv88e6390_watchdog_ops, 5226 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5227 .reset = mv88e6352_g1_reset, 5228 .vtu_getnext = mv88e6185_g1_vtu_getnext, 5229 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 5230 .gpio_ops = &mv88e6352_gpio_ops, 5231 .avb_ops = &mv88e6352_avb_ops, 5232 .ptp_ops = &mv88e6352_ptp_ops, 5233 .phylink_get_caps = mv88e6185_phylink_get_caps, 5234 }; 5235 5236 static const struct mv88e6xxx_ops mv88e6341_ops = { 5237 /* MV88E6XXX_FAMILY_6341 */ 5238 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5239 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5240 .irl_init_all = mv88e6352_g2_irl_init_all, 5241 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5242 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5243 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5244 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5245 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5246 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5247 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5248 .port_set_link = mv88e6xxx_port_set_link, 5249 .port_sync_link = mv88e6xxx_port_sync_link, 5250 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5251 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 5252 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 5253 .port_tag_remap = mv88e6095_port_tag_remap, 5254 .port_set_policy = mv88e6352_port_set_policy, 5255 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5256 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5257 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5258 .port_set_ether_type = mv88e6351_port_set_ether_type, 5259 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5260 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5261 .port_pause_limit = mv88e6097_port_pause_limit, 5262 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5263 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5264 .port_get_cmode = mv88e6352_port_get_cmode, 5265 .port_set_cmode = mv88e6341_port_set_cmode, 5266 .port_setup_message_port = mv88e6xxx_setup_message_port, 5267 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5268 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5269 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5270 .stats_get_strings = mv88e6320_stats_get_strings, 5271 .stats_get_stats = mv88e6390_stats_get_stats, 5272 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5273 .set_egress_port = mv88e6390_g1_set_egress_port, 5274 .watchdog_ops = &mv88e6390_watchdog_ops, 5275 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5276 .pot_clear = mv88e6xxx_g2_pot_clear, 5277 .reset = mv88e6352_g1_reset, 5278 .rmu_disable = mv88e6390_g1_rmu_disable, 5279 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5280 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5281 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5282 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5283 .stu_getnext = mv88e6352_g1_stu_getnext, 5284 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5285 .serdes_power = mv88e6390_serdes_power, 5286 .serdes_get_lane = mv88e6341_serdes_get_lane, 5287 /* Check status register pause & lpa register */ 5288 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5289 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5290 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5291 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5292 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5293 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5294 .serdes_irq_status = mv88e6390_serdes_irq_status, 5295 .gpio_ops = &mv88e6352_gpio_ops, 5296 .avb_ops = &mv88e6390_avb_ops, 5297 .ptp_ops = &mv88e6352_ptp_ops, 5298 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5299 .serdes_get_strings = mv88e6390_serdes_get_strings, 5300 .serdes_get_stats = mv88e6390_serdes_get_stats, 5301 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5302 .serdes_get_regs = mv88e6390_serdes_get_regs, 5303 .phylink_get_caps = mv88e6341_phylink_get_caps, 5304 }; 5305 5306 static const struct mv88e6xxx_ops mv88e6350_ops = { 5307 /* MV88E6XXX_FAMILY_6351 */ 5308 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5309 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5310 .irl_init_all = mv88e6352_g2_irl_init_all, 5311 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5312 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5313 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5314 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5315 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5316 .port_set_link = mv88e6xxx_port_set_link, 5317 .port_sync_link = mv88e6xxx_port_sync_link, 5318 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5319 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5320 .port_tag_remap = mv88e6095_port_tag_remap, 5321 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5322 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5323 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5324 .port_set_ether_type = mv88e6351_port_set_ether_type, 5325 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5326 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5327 .port_pause_limit = mv88e6097_port_pause_limit, 5328 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5329 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5330 .port_get_cmode = mv88e6352_port_get_cmode, 5331 .port_setup_message_port = mv88e6xxx_setup_message_port, 5332 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5333 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5334 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5335 .stats_get_strings = mv88e6095_stats_get_strings, 5336 .stats_get_stats = mv88e6095_stats_get_stats, 5337 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5338 .set_egress_port = mv88e6095_g1_set_egress_port, 5339 .watchdog_ops = &mv88e6097_watchdog_ops, 5340 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5341 .pot_clear = mv88e6xxx_g2_pot_clear, 5342 .reset = mv88e6352_g1_reset, 5343 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5344 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5345 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5346 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5347 .stu_getnext = mv88e6352_g1_stu_getnext, 5348 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5349 .phylink_get_caps = mv88e6185_phylink_get_caps, 5350 }; 5351 5352 static const struct mv88e6xxx_ops mv88e6351_ops = { 5353 /* MV88E6XXX_FAMILY_6351 */ 5354 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5355 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5356 .irl_init_all = mv88e6352_g2_irl_init_all, 5357 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5358 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5359 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5360 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5361 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5362 .port_set_link = mv88e6xxx_port_set_link, 5363 .port_sync_link = mv88e6xxx_port_sync_link, 5364 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5365 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 5366 .port_tag_remap = mv88e6095_port_tag_remap, 5367 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5368 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5369 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5370 .port_set_ether_type = mv88e6351_port_set_ether_type, 5371 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5372 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5373 .port_pause_limit = mv88e6097_port_pause_limit, 5374 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5375 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5376 .port_get_cmode = mv88e6352_port_get_cmode, 5377 .port_setup_message_port = mv88e6xxx_setup_message_port, 5378 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5379 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5380 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5381 .stats_get_strings = mv88e6095_stats_get_strings, 5382 .stats_get_stats = mv88e6095_stats_get_stats, 5383 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5384 .set_egress_port = mv88e6095_g1_set_egress_port, 5385 .watchdog_ops = &mv88e6097_watchdog_ops, 5386 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5387 .pot_clear = mv88e6xxx_g2_pot_clear, 5388 .reset = mv88e6352_g1_reset, 5389 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5390 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5391 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5392 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5393 .stu_getnext = mv88e6352_g1_stu_getnext, 5394 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5395 .avb_ops = &mv88e6352_avb_ops, 5396 .ptp_ops = &mv88e6352_ptp_ops, 5397 .phylink_get_caps = mv88e6185_phylink_get_caps, 5398 }; 5399 5400 static const struct mv88e6xxx_ops mv88e6352_ops = { 5401 /* MV88E6XXX_FAMILY_6352 */ 5402 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 5403 .ip_pri_map = mv88e6085_g1_ip_pri_map, 5404 .irl_init_all = mv88e6352_g2_irl_init_all, 5405 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 5406 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 5407 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5408 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5409 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5410 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5411 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5412 .port_set_link = mv88e6xxx_port_set_link, 5413 .port_sync_link = mv88e6xxx_port_sync_link, 5414 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 5415 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 5416 .port_tag_remap = mv88e6095_port_tag_remap, 5417 .port_set_policy = mv88e6352_port_set_policy, 5418 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5419 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5420 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5421 .port_set_ether_type = mv88e6351_port_set_ether_type, 5422 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5423 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5424 .port_pause_limit = mv88e6097_port_pause_limit, 5425 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5426 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5427 .port_get_cmode = mv88e6352_port_get_cmode, 5428 .port_setup_message_port = mv88e6xxx_setup_message_port, 5429 .stats_snapshot = mv88e6320_g1_stats_snapshot, 5430 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 5431 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 5432 .stats_get_strings = mv88e6095_stats_get_strings, 5433 .stats_get_stats = mv88e6095_stats_get_stats, 5434 .set_cpu_port = mv88e6095_g1_set_cpu_port, 5435 .set_egress_port = mv88e6095_g1_set_egress_port, 5436 .watchdog_ops = &mv88e6097_watchdog_ops, 5437 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 5438 .pot_clear = mv88e6xxx_g2_pot_clear, 5439 .reset = mv88e6352_g1_reset, 5440 .rmu_disable = mv88e6352_g1_rmu_disable, 5441 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5442 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5443 .vtu_getnext = mv88e6352_g1_vtu_getnext, 5444 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 5445 .stu_getnext = mv88e6352_g1_stu_getnext, 5446 .stu_loadpurge = mv88e6352_g1_stu_loadpurge, 5447 .serdes_get_lane = mv88e6352_serdes_get_lane, 5448 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 5449 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 5450 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 5451 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 5452 .serdes_power = mv88e6352_serdes_power, 5453 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 5454 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 5455 .serdes_irq_status = mv88e6352_serdes_irq_status, 5456 .gpio_ops = &mv88e6352_gpio_ops, 5457 .avb_ops = &mv88e6352_avb_ops, 5458 .ptp_ops = &mv88e6352_ptp_ops, 5459 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 5460 .serdes_get_strings = mv88e6352_serdes_get_strings, 5461 .serdes_get_stats = mv88e6352_serdes_get_stats, 5462 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 5463 .serdes_get_regs = mv88e6352_serdes_get_regs, 5464 .serdes_set_tx_amplitude = mv88e6352_serdes_set_tx_amplitude, 5465 .phylink_get_caps = mv88e6352_phylink_get_caps, 5466 }; 5467 5468 static const struct mv88e6xxx_ops mv88e6390_ops = { 5469 /* MV88E6XXX_FAMILY_6390 */ 5470 .setup_errata = mv88e6390_setup_errata, 5471 .irl_init_all = mv88e6390_g2_irl_init_all, 5472 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5473 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5474 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5475 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5476 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5477 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5478 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5479 .port_set_link = mv88e6xxx_port_set_link, 5480 .port_sync_link = mv88e6xxx_port_sync_link, 5481 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5482 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 5483 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 5484 .port_tag_remap = mv88e6390_port_tag_remap, 5485 .port_set_policy = mv88e6352_port_set_policy, 5486 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5487 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5488 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5489 .port_set_ether_type = mv88e6351_port_set_ether_type, 5490 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5491 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5492 .port_pause_limit = mv88e6390_port_pause_limit, 5493 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5494 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5495 .port_get_cmode = mv88e6352_port_get_cmode, 5496 .port_set_cmode = mv88e6390_port_set_cmode, 5497 .port_setup_message_port = mv88e6xxx_setup_message_port, 5498 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5499 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5500 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5501 .stats_get_strings = mv88e6320_stats_get_strings, 5502 .stats_get_stats = mv88e6390_stats_get_stats, 5503 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5504 .set_egress_port = mv88e6390_g1_set_egress_port, 5505 .watchdog_ops = &mv88e6390_watchdog_ops, 5506 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5507 .pot_clear = mv88e6xxx_g2_pot_clear, 5508 .reset = mv88e6352_g1_reset, 5509 .rmu_disable = mv88e6390_g1_rmu_disable, 5510 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5511 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5512 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5513 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5514 .stu_getnext = mv88e6390_g1_stu_getnext, 5515 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5516 .serdes_power = mv88e6390_serdes_power, 5517 .serdes_get_lane = mv88e6390_serdes_get_lane, 5518 /* Check status register pause & lpa register */ 5519 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5520 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5521 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5522 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5523 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5524 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5525 .serdes_irq_status = mv88e6390_serdes_irq_status, 5526 .gpio_ops = &mv88e6352_gpio_ops, 5527 .avb_ops = &mv88e6390_avb_ops, 5528 .ptp_ops = &mv88e6390_ptp_ops, 5529 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5530 .serdes_get_strings = mv88e6390_serdes_get_strings, 5531 .serdes_get_stats = mv88e6390_serdes_get_stats, 5532 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5533 .serdes_get_regs = mv88e6390_serdes_get_regs, 5534 .phylink_get_caps = mv88e6390_phylink_get_caps, 5535 }; 5536 5537 static const struct mv88e6xxx_ops mv88e6390x_ops = { 5538 /* MV88E6XXX_FAMILY_6390 */ 5539 .setup_errata = mv88e6390_setup_errata, 5540 .irl_init_all = mv88e6390_g2_irl_init_all, 5541 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5542 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5543 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5544 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5545 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5546 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5547 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5548 .port_set_link = mv88e6xxx_port_set_link, 5549 .port_sync_link = mv88e6xxx_port_sync_link, 5550 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5551 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 5552 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 5553 .port_tag_remap = mv88e6390_port_tag_remap, 5554 .port_set_policy = mv88e6352_port_set_policy, 5555 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5556 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5557 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5558 .port_set_ether_type = mv88e6351_port_set_ether_type, 5559 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5560 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5561 .port_pause_limit = mv88e6390_port_pause_limit, 5562 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5563 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5564 .port_get_cmode = mv88e6352_port_get_cmode, 5565 .port_set_cmode = mv88e6390x_port_set_cmode, 5566 .port_setup_message_port = mv88e6xxx_setup_message_port, 5567 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5568 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5569 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5570 .stats_get_strings = mv88e6320_stats_get_strings, 5571 .stats_get_stats = mv88e6390_stats_get_stats, 5572 .set_cpu_port = mv88e6390_g1_set_cpu_port, 5573 .set_egress_port = mv88e6390_g1_set_egress_port, 5574 .watchdog_ops = &mv88e6390_watchdog_ops, 5575 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 5576 .pot_clear = mv88e6xxx_g2_pot_clear, 5577 .reset = mv88e6352_g1_reset, 5578 .rmu_disable = mv88e6390_g1_rmu_disable, 5579 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5580 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5581 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5582 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5583 .stu_getnext = mv88e6390_g1_stu_getnext, 5584 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5585 .serdes_power = mv88e6390_serdes_power, 5586 .serdes_get_lane = mv88e6390x_serdes_get_lane, 5587 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 5588 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5589 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5590 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5591 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5592 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 5593 .serdes_irq_status = mv88e6390_serdes_irq_status, 5594 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 5595 .serdes_get_strings = mv88e6390_serdes_get_strings, 5596 .serdes_get_stats = mv88e6390_serdes_get_stats, 5597 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 5598 .serdes_get_regs = mv88e6390_serdes_get_regs, 5599 .gpio_ops = &mv88e6352_gpio_ops, 5600 .avb_ops = &mv88e6390_avb_ops, 5601 .ptp_ops = &mv88e6390_ptp_ops, 5602 .phylink_get_caps = mv88e6390x_phylink_get_caps, 5603 }; 5604 5605 static const struct mv88e6xxx_ops mv88e6393x_ops = { 5606 /* MV88E6XXX_FAMILY_6393 */ 5607 .setup_errata = mv88e6393x_serdes_setup_errata, 5608 .irl_init_all = mv88e6390_g2_irl_init_all, 5609 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 5610 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 5611 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 5612 .phy_read = mv88e6xxx_g2_smi_phy_read_c22, 5613 .phy_write = mv88e6xxx_g2_smi_phy_write_c22, 5614 .phy_read_c45 = mv88e6xxx_g2_smi_phy_read_c45, 5615 .phy_write_c45 = mv88e6xxx_g2_smi_phy_write_c45, 5616 .port_set_link = mv88e6xxx_port_set_link, 5617 .port_sync_link = mv88e6xxx_port_sync_link, 5618 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 5619 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 5620 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 5621 .port_tag_remap = mv88e6390_port_tag_remap, 5622 .port_set_policy = mv88e6393x_port_set_policy, 5623 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 5624 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 5625 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 5626 .port_set_ether_type = mv88e6393x_port_set_ether_type, 5627 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 5628 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 5629 .port_pause_limit = mv88e6390_port_pause_limit, 5630 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 5631 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 5632 .port_get_cmode = mv88e6352_port_get_cmode, 5633 .port_set_cmode = mv88e6393x_port_set_cmode, 5634 .port_setup_message_port = mv88e6xxx_setup_message_port, 5635 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 5636 .stats_snapshot = mv88e6390_g1_stats_snapshot, 5637 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 5638 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 5639 .stats_get_strings = mv88e6320_stats_get_strings, 5640 .stats_get_stats = mv88e6390_stats_get_stats, 5641 /* .set_cpu_port is missing because this family does not support a global 5642 * CPU port, only per port CPU port which is set via 5643 * .port_set_upstream_port method. 5644 */ 5645 .set_egress_port = mv88e6393x_set_egress_port, 5646 .watchdog_ops = &mv88e6393x_watchdog_ops, 5647 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 5648 .pot_clear = mv88e6xxx_g2_pot_clear, 5649 .reset = mv88e6352_g1_reset, 5650 .rmu_disable = mv88e6390_g1_rmu_disable, 5651 .atu_get_hash = mv88e6165_g1_atu_get_hash, 5652 .atu_set_hash = mv88e6165_g1_atu_set_hash, 5653 .vtu_getnext = mv88e6390_g1_vtu_getnext, 5654 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 5655 .stu_getnext = mv88e6390_g1_stu_getnext, 5656 .stu_loadpurge = mv88e6390_g1_stu_loadpurge, 5657 .serdes_power = mv88e6393x_serdes_power, 5658 .serdes_get_lane = mv88e6393x_serdes_get_lane, 5659 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 5660 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 5661 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 5662 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 5663 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 5664 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 5665 .serdes_irq_status = mv88e6393x_serdes_irq_status, 5666 /* TODO: serdes stats */ 5667 .gpio_ops = &mv88e6352_gpio_ops, 5668 .avb_ops = &mv88e6390_avb_ops, 5669 .ptp_ops = &mv88e6352_ptp_ops, 5670 .phylink_get_caps = mv88e6393x_phylink_get_caps, 5671 }; 5672 5673 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 5674 [MV88E6020] = { 5675 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6020, 5676 .family = MV88E6XXX_FAMILY_6250, 5677 .name = "Marvell 88E6020", 5678 .num_databases = 64, 5679 .num_ports = 4, 5680 .num_internal_phys = 2, 5681 .max_vid = 4095, 5682 .port_base_addr = 0x8, 5683 .phy_base_addr = 0x0, 5684 .global1_addr = 0xf, 5685 .global2_addr = 0x7, 5686 .age_time_coeff = 15000, 5687 .g1_irqs = 9, 5688 .g2_irqs = 5, 5689 .atu_move_port_mask = 0xf, 5690 .dual_chip = true, 5691 .ops = &mv88e6250_ops, 5692 }, 5693 5694 [MV88E6071] = { 5695 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6071, 5696 .family = MV88E6XXX_FAMILY_6250, 5697 .name = "Marvell 88E6071", 5698 .num_databases = 64, 5699 .num_ports = 7, 5700 .num_internal_phys = 5, 5701 .max_vid = 4095, 5702 .port_base_addr = 0x08, 5703 .phy_base_addr = 0x00, 5704 .global1_addr = 0x0f, 5705 .global2_addr = 0x07, 5706 .age_time_coeff = 15000, 5707 .g1_irqs = 9, 5708 .g2_irqs = 5, 5709 .atu_move_port_mask = 0xf, 5710 .dual_chip = true, 5711 .ops = &mv88e6250_ops, 5712 }, 5713 5714 [MV88E6085] = { 5715 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 5716 .family = MV88E6XXX_FAMILY_6097, 5717 .name = "Marvell 88E6085", 5718 .num_databases = 4096, 5719 .num_macs = 8192, 5720 .num_ports = 10, 5721 .num_internal_phys = 5, 5722 .max_vid = 4095, 5723 .max_sid = 63, 5724 .port_base_addr = 0x10, 5725 .phy_base_addr = 0x0, 5726 .global1_addr = 0x1b, 5727 .global2_addr = 0x1c, 5728 .age_time_coeff = 15000, 5729 .g1_irqs = 8, 5730 .g2_irqs = 10, 5731 .atu_move_port_mask = 0xf, 5732 .pvt = true, 5733 .multi_chip = true, 5734 .ops = &mv88e6085_ops, 5735 }, 5736 5737 [MV88E6095] = { 5738 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 5739 .family = MV88E6XXX_FAMILY_6095, 5740 .name = "Marvell 88E6095/88E6095F", 5741 .num_databases = 256, 5742 .num_macs = 8192, 5743 .num_ports = 11, 5744 .num_internal_phys = 0, 5745 .max_vid = 4095, 5746 .port_base_addr = 0x10, 5747 .phy_base_addr = 0x0, 5748 .global1_addr = 0x1b, 5749 .global2_addr = 0x1c, 5750 .age_time_coeff = 15000, 5751 .g1_irqs = 8, 5752 .atu_move_port_mask = 0xf, 5753 .multi_chip = true, 5754 .ops = &mv88e6095_ops, 5755 }, 5756 5757 [MV88E6097] = { 5758 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5759 .family = MV88E6XXX_FAMILY_6097, 5760 .name = "Marvell 88E6097/88E6097F", 5761 .num_databases = 4096, 5762 .num_macs = 8192, 5763 .num_ports = 11, 5764 .num_internal_phys = 8, 5765 .max_vid = 4095, 5766 .max_sid = 63, 5767 .port_base_addr = 0x10, 5768 .phy_base_addr = 0x0, 5769 .global1_addr = 0x1b, 5770 .global2_addr = 0x1c, 5771 .age_time_coeff = 15000, 5772 .g1_irqs = 8, 5773 .g2_irqs = 10, 5774 .atu_move_port_mask = 0xf, 5775 .pvt = true, 5776 .multi_chip = true, 5777 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5778 .ops = &mv88e6097_ops, 5779 }, 5780 5781 [MV88E6123] = { 5782 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5783 .family = MV88E6XXX_FAMILY_6165, 5784 .name = "Marvell 88E6123", 5785 .num_databases = 4096, 5786 .num_macs = 1024, 5787 .num_ports = 3, 5788 .num_internal_phys = 5, 5789 .max_vid = 4095, 5790 .max_sid = 63, 5791 .port_base_addr = 0x10, 5792 .phy_base_addr = 0x0, 5793 .global1_addr = 0x1b, 5794 .global2_addr = 0x1c, 5795 .age_time_coeff = 15000, 5796 .g1_irqs = 9, 5797 .g2_irqs = 10, 5798 .atu_move_port_mask = 0xf, 5799 .pvt = true, 5800 .multi_chip = true, 5801 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5802 .ops = &mv88e6123_ops, 5803 }, 5804 5805 [MV88E6131] = { 5806 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5807 .family = MV88E6XXX_FAMILY_6185, 5808 .name = "Marvell 88E6131", 5809 .num_databases = 256, 5810 .num_macs = 8192, 5811 .num_ports = 8, 5812 .num_internal_phys = 0, 5813 .max_vid = 4095, 5814 .port_base_addr = 0x10, 5815 .phy_base_addr = 0x0, 5816 .global1_addr = 0x1b, 5817 .global2_addr = 0x1c, 5818 .age_time_coeff = 15000, 5819 .g1_irqs = 9, 5820 .atu_move_port_mask = 0xf, 5821 .multi_chip = true, 5822 .ops = &mv88e6131_ops, 5823 }, 5824 5825 [MV88E6141] = { 5826 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5827 .family = MV88E6XXX_FAMILY_6341, 5828 .name = "Marvell 88E6141", 5829 .num_databases = 4096, 5830 .num_macs = 2048, 5831 .num_ports = 6, 5832 .num_internal_phys = 5, 5833 .num_gpio = 11, 5834 .max_vid = 4095, 5835 .max_sid = 63, 5836 .port_base_addr = 0x10, 5837 .phy_base_addr = 0x10, 5838 .global1_addr = 0x1b, 5839 .global2_addr = 0x1c, 5840 .age_time_coeff = 3750, 5841 .atu_move_port_mask = 0x1f, 5842 .g1_irqs = 9, 5843 .g2_irqs = 10, 5844 .pvt = true, 5845 .multi_chip = true, 5846 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5847 .ops = &mv88e6141_ops, 5848 }, 5849 5850 [MV88E6161] = { 5851 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5852 .family = MV88E6XXX_FAMILY_6165, 5853 .name = "Marvell 88E6161", 5854 .num_databases = 4096, 5855 .num_macs = 1024, 5856 .num_ports = 6, 5857 .num_internal_phys = 5, 5858 .max_vid = 4095, 5859 .max_sid = 63, 5860 .port_base_addr = 0x10, 5861 .phy_base_addr = 0x0, 5862 .global1_addr = 0x1b, 5863 .global2_addr = 0x1c, 5864 .age_time_coeff = 15000, 5865 .g1_irqs = 9, 5866 .g2_irqs = 10, 5867 .atu_move_port_mask = 0xf, 5868 .pvt = true, 5869 .multi_chip = true, 5870 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5871 .ptp_support = true, 5872 .ops = &mv88e6161_ops, 5873 }, 5874 5875 [MV88E6165] = { 5876 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5877 .family = MV88E6XXX_FAMILY_6165, 5878 .name = "Marvell 88E6165", 5879 .num_databases = 4096, 5880 .num_macs = 8192, 5881 .num_ports = 6, 5882 .num_internal_phys = 0, 5883 .max_vid = 4095, 5884 .max_sid = 63, 5885 .port_base_addr = 0x10, 5886 .phy_base_addr = 0x0, 5887 .global1_addr = 0x1b, 5888 .global2_addr = 0x1c, 5889 .age_time_coeff = 15000, 5890 .g1_irqs = 9, 5891 .g2_irqs = 10, 5892 .atu_move_port_mask = 0xf, 5893 .pvt = true, 5894 .multi_chip = true, 5895 .ptp_support = true, 5896 .ops = &mv88e6165_ops, 5897 }, 5898 5899 [MV88E6171] = { 5900 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5901 .family = MV88E6XXX_FAMILY_6351, 5902 .name = "Marvell 88E6171", 5903 .num_databases = 4096, 5904 .num_macs = 8192, 5905 .num_ports = 7, 5906 .num_internal_phys = 5, 5907 .max_vid = 4095, 5908 .max_sid = 63, 5909 .port_base_addr = 0x10, 5910 .phy_base_addr = 0x0, 5911 .global1_addr = 0x1b, 5912 .global2_addr = 0x1c, 5913 .age_time_coeff = 15000, 5914 .g1_irqs = 9, 5915 .g2_irqs = 10, 5916 .atu_move_port_mask = 0xf, 5917 .pvt = true, 5918 .multi_chip = true, 5919 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5920 .ops = &mv88e6171_ops, 5921 }, 5922 5923 [MV88E6172] = { 5924 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5925 .family = MV88E6XXX_FAMILY_6352, 5926 .name = "Marvell 88E6172", 5927 .num_databases = 4096, 5928 .num_macs = 8192, 5929 .num_ports = 7, 5930 .num_internal_phys = 5, 5931 .num_gpio = 15, 5932 .max_vid = 4095, 5933 .max_sid = 63, 5934 .port_base_addr = 0x10, 5935 .phy_base_addr = 0x0, 5936 .global1_addr = 0x1b, 5937 .global2_addr = 0x1c, 5938 .age_time_coeff = 15000, 5939 .g1_irqs = 9, 5940 .g2_irqs = 10, 5941 .atu_move_port_mask = 0xf, 5942 .pvt = true, 5943 .multi_chip = true, 5944 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5945 .ops = &mv88e6172_ops, 5946 }, 5947 5948 [MV88E6175] = { 5949 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5950 .family = MV88E6XXX_FAMILY_6351, 5951 .name = "Marvell 88E6175", 5952 .num_databases = 4096, 5953 .num_macs = 8192, 5954 .num_ports = 7, 5955 .num_internal_phys = 5, 5956 .max_vid = 4095, 5957 .max_sid = 63, 5958 .port_base_addr = 0x10, 5959 .phy_base_addr = 0x0, 5960 .global1_addr = 0x1b, 5961 .global2_addr = 0x1c, 5962 .age_time_coeff = 15000, 5963 .g1_irqs = 9, 5964 .g2_irqs = 10, 5965 .atu_move_port_mask = 0xf, 5966 .pvt = true, 5967 .multi_chip = true, 5968 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5969 .ops = &mv88e6175_ops, 5970 }, 5971 5972 [MV88E6176] = { 5973 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5974 .family = MV88E6XXX_FAMILY_6352, 5975 .name = "Marvell 88E6176", 5976 .num_databases = 4096, 5977 .num_macs = 8192, 5978 .num_ports = 7, 5979 .num_internal_phys = 5, 5980 .num_gpio = 15, 5981 .max_vid = 4095, 5982 .max_sid = 63, 5983 .port_base_addr = 0x10, 5984 .phy_base_addr = 0x0, 5985 .global1_addr = 0x1b, 5986 .global2_addr = 0x1c, 5987 .age_time_coeff = 15000, 5988 .g1_irqs = 9, 5989 .g2_irqs = 10, 5990 .atu_move_port_mask = 0xf, 5991 .pvt = true, 5992 .multi_chip = true, 5993 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5994 .ops = &mv88e6176_ops, 5995 }, 5996 5997 [MV88E6185] = { 5998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5999 .family = MV88E6XXX_FAMILY_6185, 6000 .name = "Marvell 88E6185", 6001 .num_databases = 256, 6002 .num_macs = 8192, 6003 .num_ports = 10, 6004 .num_internal_phys = 0, 6005 .max_vid = 4095, 6006 .port_base_addr = 0x10, 6007 .phy_base_addr = 0x0, 6008 .global1_addr = 0x1b, 6009 .global2_addr = 0x1c, 6010 .age_time_coeff = 15000, 6011 .g1_irqs = 8, 6012 .atu_move_port_mask = 0xf, 6013 .multi_chip = true, 6014 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6015 .ops = &mv88e6185_ops, 6016 }, 6017 6018 [MV88E6190] = { 6019 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 6020 .family = MV88E6XXX_FAMILY_6390, 6021 .name = "Marvell 88E6190", 6022 .num_databases = 4096, 6023 .num_macs = 16384, 6024 .num_ports = 11, /* 10 + Z80 */ 6025 .num_internal_phys = 9, 6026 .num_gpio = 16, 6027 .max_vid = 8191, 6028 .max_sid = 63, 6029 .port_base_addr = 0x0, 6030 .phy_base_addr = 0x0, 6031 .global1_addr = 0x1b, 6032 .global2_addr = 0x1c, 6033 .age_time_coeff = 3750, 6034 .g1_irqs = 9, 6035 .g2_irqs = 14, 6036 .pvt = true, 6037 .multi_chip = true, 6038 .atu_move_port_mask = 0x1f, 6039 .ops = &mv88e6190_ops, 6040 }, 6041 6042 [MV88E6190X] = { 6043 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 6044 .family = MV88E6XXX_FAMILY_6390, 6045 .name = "Marvell 88E6190X", 6046 .num_databases = 4096, 6047 .num_macs = 16384, 6048 .num_ports = 11, /* 10 + Z80 */ 6049 .num_internal_phys = 9, 6050 .num_gpio = 16, 6051 .max_vid = 8191, 6052 .max_sid = 63, 6053 .port_base_addr = 0x0, 6054 .phy_base_addr = 0x0, 6055 .global1_addr = 0x1b, 6056 .global2_addr = 0x1c, 6057 .age_time_coeff = 3750, 6058 .g1_irqs = 9, 6059 .g2_irqs = 14, 6060 .atu_move_port_mask = 0x1f, 6061 .pvt = true, 6062 .multi_chip = true, 6063 .ops = &mv88e6190x_ops, 6064 }, 6065 6066 [MV88E6191] = { 6067 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 6068 .family = MV88E6XXX_FAMILY_6390, 6069 .name = "Marvell 88E6191", 6070 .num_databases = 4096, 6071 .num_macs = 16384, 6072 .num_ports = 11, /* 10 + Z80 */ 6073 .num_internal_phys = 9, 6074 .max_vid = 8191, 6075 .max_sid = 63, 6076 .port_base_addr = 0x0, 6077 .phy_base_addr = 0x0, 6078 .global1_addr = 0x1b, 6079 .global2_addr = 0x1c, 6080 .age_time_coeff = 3750, 6081 .g1_irqs = 9, 6082 .g2_irqs = 14, 6083 .atu_move_port_mask = 0x1f, 6084 .pvt = true, 6085 .multi_chip = true, 6086 .ptp_support = true, 6087 .ops = &mv88e6191_ops, 6088 }, 6089 6090 [MV88E6191X] = { 6091 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 6092 .family = MV88E6XXX_FAMILY_6393, 6093 .name = "Marvell 88E6191X", 6094 .num_databases = 4096, 6095 .num_ports = 11, /* 10 + Z80 */ 6096 .num_internal_phys = 8, 6097 .internal_phys_offset = 1, 6098 .max_vid = 8191, 6099 .max_sid = 63, 6100 .port_base_addr = 0x0, 6101 .phy_base_addr = 0x0, 6102 .global1_addr = 0x1b, 6103 .global2_addr = 0x1c, 6104 .age_time_coeff = 3750, 6105 .g1_irqs = 10, 6106 .g2_irqs = 14, 6107 .atu_move_port_mask = 0x1f, 6108 .pvt = true, 6109 .multi_chip = true, 6110 .ptp_support = true, 6111 .ops = &mv88e6393x_ops, 6112 }, 6113 6114 [MV88E6193X] = { 6115 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 6116 .family = MV88E6XXX_FAMILY_6393, 6117 .name = "Marvell 88E6193X", 6118 .num_databases = 4096, 6119 .num_ports = 11, /* 10 + Z80 */ 6120 .num_internal_phys = 8, 6121 .internal_phys_offset = 1, 6122 .max_vid = 8191, 6123 .max_sid = 63, 6124 .port_base_addr = 0x0, 6125 .phy_base_addr = 0x0, 6126 .global1_addr = 0x1b, 6127 .global2_addr = 0x1c, 6128 .age_time_coeff = 3750, 6129 .g1_irqs = 10, 6130 .g2_irqs = 14, 6131 .atu_move_port_mask = 0x1f, 6132 .pvt = true, 6133 .multi_chip = true, 6134 .ptp_support = true, 6135 .ops = &mv88e6393x_ops, 6136 }, 6137 6138 [MV88E6220] = { 6139 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 6140 .family = MV88E6XXX_FAMILY_6250, 6141 .name = "Marvell 88E6220", 6142 .num_databases = 64, 6143 6144 /* Ports 2-4 are not routed to pins 6145 * => usable ports 0, 1, 5, 6 6146 */ 6147 .num_ports = 7, 6148 .num_internal_phys = 2, 6149 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 6150 .max_vid = 4095, 6151 .port_base_addr = 0x08, 6152 .phy_base_addr = 0x00, 6153 .global1_addr = 0x0f, 6154 .global2_addr = 0x07, 6155 .age_time_coeff = 15000, 6156 .g1_irqs = 9, 6157 .g2_irqs = 10, 6158 .atu_move_port_mask = 0xf, 6159 .dual_chip = true, 6160 .ptp_support = true, 6161 .ops = &mv88e6250_ops, 6162 }, 6163 6164 [MV88E6240] = { 6165 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 6166 .family = MV88E6XXX_FAMILY_6352, 6167 .name = "Marvell 88E6240", 6168 .num_databases = 4096, 6169 .num_macs = 8192, 6170 .num_ports = 7, 6171 .num_internal_phys = 5, 6172 .num_gpio = 15, 6173 .max_vid = 4095, 6174 .max_sid = 63, 6175 .port_base_addr = 0x10, 6176 .phy_base_addr = 0x0, 6177 .global1_addr = 0x1b, 6178 .global2_addr = 0x1c, 6179 .age_time_coeff = 15000, 6180 .g1_irqs = 9, 6181 .g2_irqs = 10, 6182 .atu_move_port_mask = 0xf, 6183 .pvt = true, 6184 .multi_chip = true, 6185 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6186 .ptp_support = true, 6187 .ops = &mv88e6240_ops, 6188 }, 6189 6190 [MV88E6250] = { 6191 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 6192 .family = MV88E6XXX_FAMILY_6250, 6193 .name = "Marvell 88E6250", 6194 .num_databases = 64, 6195 .num_ports = 7, 6196 .num_internal_phys = 5, 6197 .max_vid = 4095, 6198 .port_base_addr = 0x08, 6199 .phy_base_addr = 0x00, 6200 .global1_addr = 0x0f, 6201 .global2_addr = 0x07, 6202 .age_time_coeff = 15000, 6203 .g1_irqs = 9, 6204 .g2_irqs = 10, 6205 .atu_move_port_mask = 0xf, 6206 .dual_chip = true, 6207 .ptp_support = true, 6208 .ops = &mv88e6250_ops, 6209 }, 6210 6211 [MV88E6290] = { 6212 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 6213 .family = MV88E6XXX_FAMILY_6390, 6214 .name = "Marvell 88E6290", 6215 .num_databases = 4096, 6216 .num_ports = 11, /* 10 + Z80 */ 6217 .num_internal_phys = 9, 6218 .num_gpio = 16, 6219 .max_vid = 8191, 6220 .max_sid = 63, 6221 .port_base_addr = 0x0, 6222 .phy_base_addr = 0x0, 6223 .global1_addr = 0x1b, 6224 .global2_addr = 0x1c, 6225 .age_time_coeff = 3750, 6226 .g1_irqs = 9, 6227 .g2_irqs = 14, 6228 .atu_move_port_mask = 0x1f, 6229 .pvt = true, 6230 .multi_chip = true, 6231 .ptp_support = true, 6232 .ops = &mv88e6290_ops, 6233 }, 6234 6235 [MV88E6320] = { 6236 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 6237 .family = MV88E6XXX_FAMILY_6320, 6238 .name = "Marvell 88E6320", 6239 .num_databases = 4096, 6240 .num_macs = 8192, 6241 .num_ports = 7, 6242 .num_internal_phys = 5, 6243 .num_gpio = 15, 6244 .max_vid = 4095, 6245 .port_base_addr = 0x10, 6246 .phy_base_addr = 0x0, 6247 .global1_addr = 0x1b, 6248 .global2_addr = 0x1c, 6249 .age_time_coeff = 15000, 6250 .g1_irqs = 8, 6251 .g2_irqs = 10, 6252 .atu_move_port_mask = 0xf, 6253 .pvt = true, 6254 .multi_chip = true, 6255 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6256 .ptp_support = true, 6257 .ops = &mv88e6320_ops, 6258 }, 6259 6260 [MV88E6321] = { 6261 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 6262 .family = MV88E6XXX_FAMILY_6320, 6263 .name = "Marvell 88E6321", 6264 .num_databases = 4096, 6265 .num_macs = 8192, 6266 .num_ports = 7, 6267 .num_internal_phys = 5, 6268 .num_gpio = 15, 6269 .max_vid = 4095, 6270 .port_base_addr = 0x10, 6271 .phy_base_addr = 0x0, 6272 .global1_addr = 0x1b, 6273 .global2_addr = 0x1c, 6274 .age_time_coeff = 15000, 6275 .g1_irqs = 8, 6276 .g2_irqs = 10, 6277 .atu_move_port_mask = 0xf, 6278 .multi_chip = true, 6279 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6280 .ptp_support = true, 6281 .ops = &mv88e6321_ops, 6282 }, 6283 6284 [MV88E6341] = { 6285 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 6286 .family = MV88E6XXX_FAMILY_6341, 6287 .name = "Marvell 88E6341", 6288 .num_databases = 4096, 6289 .num_macs = 2048, 6290 .num_internal_phys = 5, 6291 .num_ports = 6, 6292 .num_gpio = 11, 6293 .max_vid = 4095, 6294 .max_sid = 63, 6295 .port_base_addr = 0x10, 6296 .phy_base_addr = 0x10, 6297 .global1_addr = 0x1b, 6298 .global2_addr = 0x1c, 6299 .age_time_coeff = 3750, 6300 .atu_move_port_mask = 0x1f, 6301 .g1_irqs = 9, 6302 .g2_irqs = 10, 6303 .pvt = true, 6304 .multi_chip = true, 6305 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6306 .ptp_support = true, 6307 .ops = &mv88e6341_ops, 6308 }, 6309 6310 [MV88E6350] = { 6311 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 6312 .family = MV88E6XXX_FAMILY_6351, 6313 .name = "Marvell 88E6350", 6314 .num_databases = 4096, 6315 .num_macs = 8192, 6316 .num_ports = 7, 6317 .num_internal_phys = 5, 6318 .max_vid = 4095, 6319 .max_sid = 63, 6320 .port_base_addr = 0x10, 6321 .phy_base_addr = 0x0, 6322 .global1_addr = 0x1b, 6323 .global2_addr = 0x1c, 6324 .age_time_coeff = 15000, 6325 .g1_irqs = 9, 6326 .g2_irqs = 10, 6327 .atu_move_port_mask = 0xf, 6328 .pvt = true, 6329 .multi_chip = true, 6330 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6331 .ops = &mv88e6350_ops, 6332 }, 6333 6334 [MV88E6351] = { 6335 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 6336 .family = MV88E6XXX_FAMILY_6351, 6337 .name = "Marvell 88E6351", 6338 .num_databases = 4096, 6339 .num_macs = 8192, 6340 .num_ports = 7, 6341 .num_internal_phys = 5, 6342 .max_vid = 4095, 6343 .max_sid = 63, 6344 .port_base_addr = 0x10, 6345 .phy_base_addr = 0x0, 6346 .global1_addr = 0x1b, 6347 .global2_addr = 0x1c, 6348 .age_time_coeff = 15000, 6349 .g1_irqs = 9, 6350 .g2_irqs = 10, 6351 .atu_move_port_mask = 0xf, 6352 .pvt = true, 6353 .multi_chip = true, 6354 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6355 .ops = &mv88e6351_ops, 6356 }, 6357 6358 [MV88E6352] = { 6359 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 6360 .family = MV88E6XXX_FAMILY_6352, 6361 .name = "Marvell 88E6352", 6362 .num_databases = 4096, 6363 .num_macs = 8192, 6364 .num_ports = 7, 6365 .num_internal_phys = 5, 6366 .num_gpio = 15, 6367 .max_vid = 4095, 6368 .max_sid = 63, 6369 .port_base_addr = 0x10, 6370 .phy_base_addr = 0x0, 6371 .global1_addr = 0x1b, 6372 .global2_addr = 0x1c, 6373 .age_time_coeff = 15000, 6374 .g1_irqs = 9, 6375 .g2_irqs = 10, 6376 .atu_move_port_mask = 0xf, 6377 .pvt = true, 6378 .multi_chip = true, 6379 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 6380 .ptp_support = true, 6381 .ops = &mv88e6352_ops, 6382 }, 6383 [MV88E6361] = { 6384 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6361, 6385 .family = MV88E6XXX_FAMILY_6393, 6386 .name = "Marvell 88E6361", 6387 .num_databases = 4096, 6388 .num_macs = 16384, 6389 .num_ports = 11, 6390 /* Ports 1, 2 and 8 are not routed */ 6391 .invalid_port_mask = BIT(1) | BIT(2) | BIT(8), 6392 .num_internal_phys = 5, 6393 .internal_phys_offset = 3, 6394 .max_vid = 4095, 6395 .max_sid = 63, 6396 .port_base_addr = 0x0, 6397 .phy_base_addr = 0x0, 6398 .global1_addr = 0x1b, 6399 .global2_addr = 0x1c, 6400 .age_time_coeff = 3750, 6401 .g1_irqs = 10, 6402 .g2_irqs = 14, 6403 .atu_move_port_mask = 0x1f, 6404 .pvt = true, 6405 .multi_chip = true, 6406 .ptp_support = true, 6407 .ops = &mv88e6393x_ops, 6408 }, 6409 [MV88E6390] = { 6410 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 6411 .family = MV88E6XXX_FAMILY_6390, 6412 .name = "Marvell 88E6390", 6413 .num_databases = 4096, 6414 .num_macs = 16384, 6415 .num_ports = 11, /* 10 + Z80 */ 6416 .num_internal_phys = 9, 6417 .num_gpio = 16, 6418 .max_vid = 8191, 6419 .max_sid = 63, 6420 .port_base_addr = 0x0, 6421 .phy_base_addr = 0x0, 6422 .global1_addr = 0x1b, 6423 .global2_addr = 0x1c, 6424 .age_time_coeff = 3750, 6425 .g1_irqs = 9, 6426 .g2_irqs = 14, 6427 .atu_move_port_mask = 0x1f, 6428 .pvt = true, 6429 .multi_chip = true, 6430 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6431 .ptp_support = true, 6432 .ops = &mv88e6390_ops, 6433 }, 6434 [MV88E6390X] = { 6435 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 6436 .family = MV88E6XXX_FAMILY_6390, 6437 .name = "Marvell 88E6390X", 6438 .num_databases = 4096, 6439 .num_macs = 16384, 6440 .num_ports = 11, /* 10 + Z80 */ 6441 .num_internal_phys = 9, 6442 .num_gpio = 16, 6443 .max_vid = 8191, 6444 .max_sid = 63, 6445 .port_base_addr = 0x0, 6446 .phy_base_addr = 0x0, 6447 .global1_addr = 0x1b, 6448 .global2_addr = 0x1c, 6449 .age_time_coeff = 3750, 6450 .g1_irqs = 9, 6451 .g2_irqs = 14, 6452 .atu_move_port_mask = 0x1f, 6453 .pvt = true, 6454 .multi_chip = true, 6455 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 6456 .ptp_support = true, 6457 .ops = &mv88e6390x_ops, 6458 }, 6459 6460 [MV88E6393X] = { 6461 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 6462 .family = MV88E6XXX_FAMILY_6393, 6463 .name = "Marvell 88E6393X", 6464 .num_databases = 4096, 6465 .num_ports = 11, /* 10 + Z80 */ 6466 .num_internal_phys = 8, 6467 .internal_phys_offset = 1, 6468 .max_vid = 8191, 6469 .max_sid = 63, 6470 .port_base_addr = 0x0, 6471 .phy_base_addr = 0x0, 6472 .global1_addr = 0x1b, 6473 .global2_addr = 0x1c, 6474 .age_time_coeff = 3750, 6475 .g1_irqs = 10, 6476 .g2_irqs = 14, 6477 .atu_move_port_mask = 0x1f, 6478 .pvt = true, 6479 .multi_chip = true, 6480 .ptp_support = true, 6481 .ops = &mv88e6393x_ops, 6482 }, 6483 }; 6484 6485 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 6486 { 6487 int i; 6488 6489 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 6490 if (mv88e6xxx_table[i].prod_num == prod_num) 6491 return &mv88e6xxx_table[i]; 6492 6493 return NULL; 6494 } 6495 6496 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 6497 { 6498 const struct mv88e6xxx_info *info; 6499 unsigned int prod_num, rev; 6500 u16 id; 6501 int err; 6502 6503 mv88e6xxx_reg_lock(chip); 6504 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 6505 mv88e6xxx_reg_unlock(chip); 6506 if (err) 6507 return err; 6508 6509 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 6510 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 6511 6512 info = mv88e6xxx_lookup_info(prod_num); 6513 if (!info) 6514 return -ENODEV; 6515 6516 /* Update the compatible info with the probed one */ 6517 chip->info = info; 6518 6519 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 6520 chip->info->prod_num, chip->info->name, rev); 6521 6522 return 0; 6523 } 6524 6525 static int mv88e6xxx_single_chip_detect(struct mv88e6xxx_chip *chip, 6526 struct mdio_device *mdiodev) 6527 { 6528 int err; 6529 6530 /* dual_chip takes precedence over single/multi-chip modes */ 6531 if (chip->info->dual_chip) 6532 return -EINVAL; 6533 6534 /* If the mdio addr is 16 indicating the first port address of a switch 6535 * (e.g. mv88e6*41) in single chip addressing mode the device may be 6536 * configured in single chip addressing mode. Setup the smi access as 6537 * single chip addressing mode and attempt to detect the model of the 6538 * switch, if this fails the device is not configured in single chip 6539 * addressing mode. 6540 */ 6541 if (mdiodev->addr != 16) 6542 return -EINVAL; 6543 6544 err = mv88e6xxx_smi_init(chip, mdiodev->bus, 0); 6545 if (err) 6546 return err; 6547 6548 return mv88e6xxx_detect(chip); 6549 } 6550 6551 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 6552 { 6553 struct mv88e6xxx_chip *chip; 6554 6555 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 6556 if (!chip) 6557 return NULL; 6558 6559 chip->dev = dev; 6560 6561 mutex_init(&chip->reg_lock); 6562 INIT_LIST_HEAD(&chip->mdios); 6563 idr_init(&chip->policies); 6564 INIT_LIST_HEAD(&chip->msts); 6565 6566 return chip; 6567 } 6568 6569 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 6570 int port, 6571 enum dsa_tag_protocol m) 6572 { 6573 struct mv88e6xxx_chip *chip = ds->priv; 6574 6575 return chip->tag_protocol; 6576 } 6577 6578 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, 6579 enum dsa_tag_protocol proto) 6580 { 6581 struct mv88e6xxx_chip *chip = ds->priv; 6582 enum dsa_tag_protocol old_protocol; 6583 struct dsa_port *cpu_dp; 6584 int err; 6585 6586 switch (proto) { 6587 case DSA_TAG_PROTO_EDSA: 6588 switch (chip->info->edsa_support) { 6589 case MV88E6XXX_EDSA_UNSUPPORTED: 6590 return -EPROTONOSUPPORT; 6591 case MV88E6XXX_EDSA_UNDOCUMENTED: 6592 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 6593 fallthrough; 6594 case MV88E6XXX_EDSA_SUPPORTED: 6595 break; 6596 } 6597 break; 6598 case DSA_TAG_PROTO_DSA: 6599 break; 6600 default: 6601 return -EPROTONOSUPPORT; 6602 } 6603 6604 old_protocol = chip->tag_protocol; 6605 chip->tag_protocol = proto; 6606 6607 mv88e6xxx_reg_lock(chip); 6608 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 6609 err = mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6610 if (err) { 6611 mv88e6xxx_reg_unlock(chip); 6612 goto unwind; 6613 } 6614 } 6615 mv88e6xxx_reg_unlock(chip); 6616 6617 return 0; 6618 6619 unwind: 6620 chip->tag_protocol = old_protocol; 6621 6622 mv88e6xxx_reg_lock(chip); 6623 dsa_switch_for_each_cpu_port_continue_reverse(cpu_dp, ds) 6624 mv88e6xxx_setup_port_mode(chip, cpu_dp->index); 6625 mv88e6xxx_reg_unlock(chip); 6626 6627 return err; 6628 } 6629 6630 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 6631 const struct switchdev_obj_port_mdb *mdb, 6632 struct dsa_db db) 6633 { 6634 struct mv88e6xxx_chip *chip = ds->priv; 6635 int err; 6636 6637 mv88e6xxx_reg_lock(chip); 6638 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 6639 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 6640 mv88e6xxx_reg_unlock(chip); 6641 6642 return err; 6643 } 6644 6645 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 6646 const struct switchdev_obj_port_mdb *mdb, 6647 struct dsa_db db) 6648 { 6649 struct mv88e6xxx_chip *chip = ds->priv; 6650 int err; 6651 6652 mv88e6xxx_reg_lock(chip); 6653 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 6654 mv88e6xxx_reg_unlock(chip); 6655 6656 return err; 6657 } 6658 6659 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 6660 struct dsa_mall_mirror_tc_entry *mirror, 6661 bool ingress, 6662 struct netlink_ext_ack *extack) 6663 { 6664 enum mv88e6xxx_egress_direction direction = ingress ? 6665 MV88E6XXX_EGRESS_DIR_INGRESS : 6666 MV88E6XXX_EGRESS_DIR_EGRESS; 6667 struct mv88e6xxx_chip *chip = ds->priv; 6668 bool other_mirrors = false; 6669 int i; 6670 int err; 6671 6672 mutex_lock(&chip->reg_lock); 6673 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 6674 mirror->to_local_port) { 6675 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6676 other_mirrors |= ingress ? 6677 chip->ports[i].mirror_ingress : 6678 chip->ports[i].mirror_egress; 6679 6680 /* Can't change egress port when other mirror is active */ 6681 if (other_mirrors) { 6682 err = -EBUSY; 6683 goto out; 6684 } 6685 6686 err = mv88e6xxx_set_egress_port(chip, direction, 6687 mirror->to_local_port); 6688 if (err) 6689 goto out; 6690 } 6691 6692 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 6693 out: 6694 mutex_unlock(&chip->reg_lock); 6695 6696 return err; 6697 } 6698 6699 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 6700 struct dsa_mall_mirror_tc_entry *mirror) 6701 { 6702 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 6703 MV88E6XXX_EGRESS_DIR_INGRESS : 6704 MV88E6XXX_EGRESS_DIR_EGRESS; 6705 struct mv88e6xxx_chip *chip = ds->priv; 6706 bool other_mirrors = false; 6707 int i; 6708 6709 mutex_lock(&chip->reg_lock); 6710 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 6711 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 6712 6713 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 6714 other_mirrors |= mirror->ingress ? 6715 chip->ports[i].mirror_ingress : 6716 chip->ports[i].mirror_egress; 6717 6718 /* Reset egress port when no other mirror is active */ 6719 if (!other_mirrors) { 6720 if (mv88e6xxx_set_egress_port(chip, direction, 6721 dsa_upstream_port(ds, port))) 6722 dev_err(ds->dev, "failed to set egress port\n"); 6723 } 6724 6725 mutex_unlock(&chip->reg_lock); 6726 } 6727 6728 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 6729 struct switchdev_brport_flags flags, 6730 struct netlink_ext_ack *extack) 6731 { 6732 struct mv88e6xxx_chip *chip = ds->priv; 6733 const struct mv88e6xxx_ops *ops; 6734 6735 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 6736 BR_BCAST_FLOOD | BR_PORT_LOCKED | BR_PORT_MAB)) 6737 return -EINVAL; 6738 6739 ops = chip->info->ops; 6740 6741 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 6742 return -EINVAL; 6743 6744 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 6745 return -EINVAL; 6746 6747 return 0; 6748 } 6749 6750 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 6751 struct switchdev_brport_flags flags, 6752 struct netlink_ext_ack *extack) 6753 { 6754 struct mv88e6xxx_chip *chip = ds->priv; 6755 int err = 0; 6756 6757 mv88e6xxx_reg_lock(chip); 6758 6759 if (flags.mask & BR_LEARNING) { 6760 bool learning = !!(flags.val & BR_LEARNING); 6761 u16 pav = learning ? (1 << port) : 0; 6762 6763 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 6764 if (err) 6765 goto out; 6766 } 6767 6768 if (flags.mask & BR_FLOOD) { 6769 bool unicast = !!(flags.val & BR_FLOOD); 6770 6771 err = chip->info->ops->port_set_ucast_flood(chip, port, 6772 unicast); 6773 if (err) 6774 goto out; 6775 } 6776 6777 if (flags.mask & BR_MCAST_FLOOD) { 6778 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 6779 6780 err = chip->info->ops->port_set_mcast_flood(chip, port, 6781 multicast); 6782 if (err) 6783 goto out; 6784 } 6785 6786 if (flags.mask & BR_BCAST_FLOOD) { 6787 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 6788 6789 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 6790 if (err) 6791 goto out; 6792 } 6793 6794 if (flags.mask & BR_PORT_MAB) { 6795 bool mab = !!(flags.val & BR_PORT_MAB); 6796 6797 mv88e6xxx_port_set_mab(chip, port, mab); 6798 } 6799 6800 if (flags.mask & BR_PORT_LOCKED) { 6801 bool locked = !!(flags.val & BR_PORT_LOCKED); 6802 6803 err = mv88e6xxx_port_set_lock(chip, port, locked); 6804 if (err) 6805 goto out; 6806 } 6807 out: 6808 mv88e6xxx_reg_unlock(chip); 6809 6810 return err; 6811 } 6812 6813 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 6814 struct dsa_lag lag, 6815 struct netdev_lag_upper_info *info, 6816 struct netlink_ext_ack *extack) 6817 { 6818 struct mv88e6xxx_chip *chip = ds->priv; 6819 struct dsa_port *dp; 6820 int members = 0; 6821 6822 if (!mv88e6xxx_has_lag(chip)) { 6823 NL_SET_ERR_MSG_MOD(extack, "Chip does not support LAG offload"); 6824 return false; 6825 } 6826 6827 if (!lag.id) 6828 return false; 6829 6830 dsa_lag_foreach_port(dp, ds->dst, &lag) 6831 /* Includes the port joining the LAG */ 6832 members++; 6833 6834 if (members > 8) { 6835 NL_SET_ERR_MSG_MOD(extack, 6836 "Cannot offload more than 8 LAG ports"); 6837 return false; 6838 } 6839 6840 /* We could potentially relax this to include active 6841 * backup in the future. 6842 */ 6843 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) { 6844 NL_SET_ERR_MSG_MOD(extack, 6845 "Can only offload LAG using hash TX type"); 6846 return false; 6847 } 6848 6849 /* Ideally we would also validate that the hash type matches 6850 * the hardware. Alas, this is always set to unknown on team 6851 * interfaces. 6852 */ 6853 return true; 6854 } 6855 6856 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct dsa_lag lag) 6857 { 6858 struct mv88e6xxx_chip *chip = ds->priv; 6859 struct dsa_port *dp; 6860 u16 map = 0; 6861 int id; 6862 6863 /* DSA LAG IDs are one-based, hardware is zero-based */ 6864 id = lag.id - 1; 6865 6866 /* Build the map of all ports to distribute flows destined for 6867 * this LAG. This can be either a local user port, or a DSA 6868 * port if the LAG port is on a remote chip. 6869 */ 6870 dsa_lag_foreach_port(dp, ds->dst, &lag) 6871 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6872 6873 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6874 } 6875 6876 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6877 /* Row number corresponds to the number of active members in a 6878 * LAG. Each column states which of the eight hash buckets are 6879 * mapped to the column:th port in the LAG. 6880 * 6881 * Example: In a LAG with three active ports, the second port 6882 * ([2][1]) would be selected for traffic mapped to buckets 6883 * 3,4,5 (0x38). 6884 */ 6885 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6886 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6887 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6888 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6889 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6890 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6891 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6892 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6893 }; 6894 6895 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6896 int num_tx, int nth) 6897 { 6898 u8 active = 0; 6899 int i; 6900 6901 num_tx = num_tx <= 8 ? num_tx : 8; 6902 if (nth < num_tx) 6903 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6904 6905 for (i = 0; i < 8; i++) { 6906 if (BIT(i) & active) 6907 mask[i] |= BIT(port); 6908 } 6909 } 6910 6911 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6912 { 6913 struct mv88e6xxx_chip *chip = ds->priv; 6914 unsigned int id, num_tx; 6915 struct dsa_port *dp; 6916 struct dsa_lag *lag; 6917 int i, err, nth; 6918 u16 mask[8]; 6919 u16 ivec; 6920 6921 /* Assume no port is a member of any LAG. */ 6922 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6923 6924 /* Disable all masks for ports that _are_ members of a LAG. */ 6925 dsa_switch_for_each_port(dp, ds) { 6926 if (!dp->lag) 6927 continue; 6928 6929 ivec &= ~BIT(dp->index); 6930 } 6931 6932 for (i = 0; i < 8; i++) 6933 mask[i] = ivec; 6934 6935 /* Enable the correct subset of masks for all LAG ports that 6936 * are in the Tx set. 6937 */ 6938 dsa_lags_foreach_id(id, ds->dst) { 6939 lag = dsa_lag_by_id(ds->dst, id); 6940 if (!lag) 6941 continue; 6942 6943 num_tx = 0; 6944 dsa_lag_foreach_port(dp, ds->dst, lag) { 6945 if (dp->lag_tx_enabled) 6946 num_tx++; 6947 } 6948 6949 if (!num_tx) 6950 continue; 6951 6952 nth = 0; 6953 dsa_lag_foreach_port(dp, ds->dst, lag) { 6954 if (!dp->lag_tx_enabled) 6955 continue; 6956 6957 if (dp->ds == ds) 6958 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6959 num_tx, nth); 6960 6961 nth++; 6962 } 6963 } 6964 6965 for (i = 0; i < 8; i++) { 6966 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6967 if (err) 6968 return err; 6969 } 6970 6971 return 0; 6972 } 6973 6974 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6975 struct dsa_lag lag) 6976 { 6977 int err; 6978 6979 err = mv88e6xxx_lag_sync_masks(ds); 6980 6981 if (!err) 6982 err = mv88e6xxx_lag_sync_map(ds, lag); 6983 6984 return err; 6985 } 6986 6987 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6988 { 6989 struct mv88e6xxx_chip *chip = ds->priv; 6990 int err; 6991 6992 mv88e6xxx_reg_lock(chip); 6993 err = mv88e6xxx_lag_sync_masks(ds); 6994 mv88e6xxx_reg_unlock(chip); 6995 return err; 6996 } 6997 6998 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6999 struct dsa_lag lag, 7000 struct netdev_lag_upper_info *info, 7001 struct netlink_ext_ack *extack) 7002 { 7003 struct mv88e6xxx_chip *chip = ds->priv; 7004 int err, id; 7005 7006 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7007 return -EOPNOTSUPP; 7008 7009 /* DSA LAG IDs are one-based */ 7010 id = lag.id - 1; 7011 7012 mv88e6xxx_reg_lock(chip); 7013 7014 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 7015 if (err) 7016 goto err_unlock; 7017 7018 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7019 if (err) 7020 goto err_clear_trunk; 7021 7022 mv88e6xxx_reg_unlock(chip); 7023 return 0; 7024 7025 err_clear_trunk: 7026 mv88e6xxx_port_set_trunk(chip, port, false, 0); 7027 err_unlock: 7028 mv88e6xxx_reg_unlock(chip); 7029 return err; 7030 } 7031 7032 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 7033 struct dsa_lag lag) 7034 { 7035 struct mv88e6xxx_chip *chip = ds->priv; 7036 int err_sync, err_trunk; 7037 7038 mv88e6xxx_reg_lock(chip); 7039 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7040 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 7041 mv88e6xxx_reg_unlock(chip); 7042 return err_sync ? : err_trunk; 7043 } 7044 7045 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 7046 int port) 7047 { 7048 struct mv88e6xxx_chip *chip = ds->priv; 7049 int err; 7050 7051 mv88e6xxx_reg_lock(chip); 7052 err = mv88e6xxx_lag_sync_masks(ds); 7053 mv88e6xxx_reg_unlock(chip); 7054 return err; 7055 } 7056 7057 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 7058 int port, struct dsa_lag lag, 7059 struct netdev_lag_upper_info *info, 7060 struct netlink_ext_ack *extack) 7061 { 7062 struct mv88e6xxx_chip *chip = ds->priv; 7063 int err; 7064 7065 if (!mv88e6xxx_lag_can_offload(ds, lag, info, extack)) 7066 return -EOPNOTSUPP; 7067 7068 mv88e6xxx_reg_lock(chip); 7069 7070 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 7071 if (err) 7072 goto unlock; 7073 7074 err = mv88e6xxx_pvt_map(chip, sw_index, port); 7075 7076 unlock: 7077 mv88e6xxx_reg_unlock(chip); 7078 return err; 7079 } 7080 7081 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 7082 int port, struct dsa_lag lag) 7083 { 7084 struct mv88e6xxx_chip *chip = ds->priv; 7085 int err_sync, err_pvt; 7086 7087 mv88e6xxx_reg_lock(chip); 7088 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 7089 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 7090 mv88e6xxx_reg_unlock(chip); 7091 return err_sync ? : err_pvt; 7092 } 7093 7094 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 7095 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 7096 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 7097 .setup = mv88e6xxx_setup, 7098 .teardown = mv88e6xxx_teardown, 7099 .port_setup = mv88e6xxx_port_setup, 7100 .port_teardown = mv88e6xxx_port_teardown, 7101 .phylink_get_caps = mv88e6xxx_get_caps, 7102 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 7103 .phylink_mac_prepare = mv88e6xxx_mac_prepare, 7104 .phylink_mac_config = mv88e6xxx_mac_config, 7105 .phylink_mac_finish = mv88e6xxx_mac_finish, 7106 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 7107 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 7108 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 7109 .get_strings = mv88e6xxx_get_strings, 7110 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 7111 .get_sset_count = mv88e6xxx_get_sset_count, 7112 .port_enable = mv88e6xxx_port_enable, 7113 .port_disable = mv88e6xxx_port_disable, 7114 .port_max_mtu = mv88e6xxx_get_max_mtu, 7115 .port_change_mtu = mv88e6xxx_change_mtu, 7116 .get_mac_eee = mv88e6xxx_get_mac_eee, 7117 .set_mac_eee = mv88e6xxx_set_mac_eee, 7118 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 7119 .get_eeprom = mv88e6xxx_get_eeprom, 7120 .set_eeprom = mv88e6xxx_set_eeprom, 7121 .get_regs_len = mv88e6xxx_get_regs_len, 7122 .get_regs = mv88e6xxx_get_regs, 7123 .get_rxnfc = mv88e6xxx_get_rxnfc, 7124 .set_rxnfc = mv88e6xxx_set_rxnfc, 7125 .set_ageing_time = mv88e6xxx_set_ageing_time, 7126 .port_bridge_join = mv88e6xxx_port_bridge_join, 7127 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 7128 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 7129 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 7130 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 7131 .port_mst_state_set = mv88e6xxx_port_mst_state_set, 7132 .port_fast_age = mv88e6xxx_port_fast_age, 7133 .port_vlan_fast_age = mv88e6xxx_port_vlan_fast_age, 7134 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 7135 .port_vlan_add = mv88e6xxx_port_vlan_add, 7136 .port_vlan_del = mv88e6xxx_port_vlan_del, 7137 .vlan_msti_set = mv88e6xxx_vlan_msti_set, 7138 .port_fdb_add = mv88e6xxx_port_fdb_add, 7139 .port_fdb_del = mv88e6xxx_port_fdb_del, 7140 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 7141 .port_mdb_add = mv88e6xxx_port_mdb_add, 7142 .port_mdb_del = mv88e6xxx_port_mdb_del, 7143 .port_mirror_add = mv88e6xxx_port_mirror_add, 7144 .port_mirror_del = mv88e6xxx_port_mirror_del, 7145 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 7146 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 7147 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 7148 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 7149 .port_txtstamp = mv88e6xxx_port_txtstamp, 7150 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 7151 .get_ts_info = mv88e6xxx_get_ts_info, 7152 .devlink_param_get = mv88e6xxx_devlink_param_get, 7153 .devlink_param_set = mv88e6xxx_devlink_param_set, 7154 .devlink_info_get = mv88e6xxx_devlink_info_get, 7155 .port_lag_change = mv88e6xxx_port_lag_change, 7156 .port_lag_join = mv88e6xxx_port_lag_join, 7157 .port_lag_leave = mv88e6xxx_port_lag_leave, 7158 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 7159 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 7160 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 7161 }; 7162 7163 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 7164 { 7165 struct device *dev = chip->dev; 7166 struct dsa_switch *ds; 7167 7168 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 7169 if (!ds) 7170 return -ENOMEM; 7171 7172 ds->dev = dev; 7173 ds->num_ports = mv88e6xxx_num_ports(chip); 7174 ds->priv = chip; 7175 ds->dev = dev; 7176 ds->ops = &mv88e6xxx_switch_ops; 7177 ds->ageing_time_min = chip->info->age_time_coeff; 7178 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 7179 7180 /* Some chips support up to 32, but that requires enabling the 7181 * 5-bit port mode, which we do not support. 640k^W16 ought to 7182 * be enough for anyone. 7183 */ 7184 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 7185 7186 dev_set_drvdata(dev, ds); 7187 7188 return dsa_register_switch(ds); 7189 } 7190 7191 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 7192 { 7193 dsa_unregister_switch(chip->ds); 7194 } 7195 7196 static const void *pdata_device_get_match_data(struct device *dev) 7197 { 7198 const struct of_device_id *matches = dev->driver->of_match_table; 7199 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 7200 7201 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 7202 matches++) { 7203 if (!strcmp(pdata->compatible, matches->compatible)) 7204 return matches->data; 7205 } 7206 return NULL; 7207 } 7208 7209 /* There is no suspend to RAM support at DSA level yet, the switch configuration 7210 * would be lost after a power cycle so prevent it to be suspended. 7211 */ 7212 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 7213 { 7214 return -EOPNOTSUPP; 7215 } 7216 7217 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 7218 { 7219 return 0; 7220 } 7221 7222 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 7223 7224 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 7225 { 7226 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 7227 const struct mv88e6xxx_info *compat_info = NULL; 7228 struct device *dev = &mdiodev->dev; 7229 struct device_node *np = dev->of_node; 7230 struct mv88e6xxx_chip *chip; 7231 int port; 7232 int err; 7233 7234 if (!np && !pdata) 7235 return -EINVAL; 7236 7237 if (np) 7238 compat_info = of_device_get_match_data(dev); 7239 7240 if (pdata) { 7241 compat_info = pdata_device_get_match_data(dev); 7242 7243 if (!pdata->netdev) 7244 return -EINVAL; 7245 7246 for (port = 0; port < DSA_MAX_PORTS; port++) { 7247 if (!(pdata->enabled_ports & (1 << port))) 7248 continue; 7249 if (strcmp(pdata->cd.port_names[port], "cpu")) 7250 continue; 7251 pdata->cd.netdev[port] = &pdata->netdev->dev; 7252 break; 7253 } 7254 } 7255 7256 if (!compat_info) 7257 return -EINVAL; 7258 7259 chip = mv88e6xxx_alloc_chip(dev); 7260 if (!chip) { 7261 err = -ENOMEM; 7262 goto out; 7263 } 7264 7265 chip->info = compat_info; 7266 7267 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 7268 if (IS_ERR(chip->reset)) { 7269 err = PTR_ERR(chip->reset); 7270 goto out; 7271 } 7272 if (chip->reset) 7273 usleep_range(10000, 20000); 7274 7275 /* Detect if the device is configured in single chip addressing mode, 7276 * otherwise continue with address specific smi init/detection. 7277 */ 7278 err = mv88e6xxx_single_chip_detect(chip, mdiodev); 7279 if (err) { 7280 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 7281 if (err) 7282 goto out; 7283 7284 err = mv88e6xxx_detect(chip); 7285 if (err) 7286 goto out; 7287 } 7288 7289 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 7290 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 7291 else 7292 chip->tag_protocol = DSA_TAG_PROTO_DSA; 7293 7294 mv88e6xxx_phy_init(chip); 7295 7296 if (chip->info->ops->get_eeprom) { 7297 if (np) 7298 of_property_read_u32(np, "eeprom-length", 7299 &chip->eeprom_len); 7300 else 7301 chip->eeprom_len = pdata->eeprom_len; 7302 } 7303 7304 mv88e6xxx_reg_lock(chip); 7305 err = mv88e6xxx_switch_reset(chip); 7306 mv88e6xxx_reg_unlock(chip); 7307 if (err) 7308 goto out; 7309 7310 if (np) { 7311 chip->irq = of_irq_get(np, 0); 7312 if (chip->irq == -EPROBE_DEFER) { 7313 err = chip->irq; 7314 goto out; 7315 } 7316 } 7317 7318 if (pdata) 7319 chip->irq = pdata->irq; 7320 7321 /* Has to be performed before the MDIO bus is created, because 7322 * the PHYs will link their interrupts to these interrupt 7323 * controllers 7324 */ 7325 mv88e6xxx_reg_lock(chip); 7326 if (chip->irq > 0) 7327 err = mv88e6xxx_g1_irq_setup(chip); 7328 else 7329 err = mv88e6xxx_irq_poll_setup(chip); 7330 mv88e6xxx_reg_unlock(chip); 7331 7332 if (err) 7333 goto out; 7334 7335 if (chip->info->g2_irqs > 0) { 7336 err = mv88e6xxx_g2_irq_setup(chip); 7337 if (err) 7338 goto out_g1_irq; 7339 } 7340 7341 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 7342 if (err) 7343 goto out_g2_irq; 7344 7345 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 7346 if (err) 7347 goto out_g1_atu_prob_irq; 7348 7349 err = mv88e6xxx_register_switch(chip); 7350 if (err) 7351 goto out_g1_vtu_prob_irq; 7352 7353 return 0; 7354 7355 out_g1_vtu_prob_irq: 7356 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7357 out_g1_atu_prob_irq: 7358 mv88e6xxx_g1_atu_prob_irq_free(chip); 7359 out_g2_irq: 7360 if (chip->info->g2_irqs > 0) 7361 mv88e6xxx_g2_irq_free(chip); 7362 out_g1_irq: 7363 if (chip->irq > 0) 7364 mv88e6xxx_g1_irq_free(chip); 7365 else 7366 mv88e6xxx_irq_poll_free(chip); 7367 out: 7368 if (pdata) 7369 dev_put(pdata->netdev); 7370 7371 return err; 7372 } 7373 7374 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 7375 { 7376 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7377 struct mv88e6xxx_chip *chip; 7378 7379 if (!ds) 7380 return; 7381 7382 chip = ds->priv; 7383 7384 if (chip->info->ptp_support) { 7385 mv88e6xxx_hwtstamp_free(chip); 7386 mv88e6xxx_ptp_free(chip); 7387 } 7388 7389 mv88e6xxx_phy_destroy(chip); 7390 mv88e6xxx_unregister_switch(chip); 7391 7392 mv88e6xxx_g1_vtu_prob_irq_free(chip); 7393 mv88e6xxx_g1_atu_prob_irq_free(chip); 7394 7395 if (chip->info->g2_irqs > 0) 7396 mv88e6xxx_g2_irq_free(chip); 7397 7398 if (chip->irq > 0) 7399 mv88e6xxx_g1_irq_free(chip); 7400 else 7401 mv88e6xxx_irq_poll_free(chip); 7402 } 7403 7404 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 7405 { 7406 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 7407 7408 if (!ds) 7409 return; 7410 7411 dsa_switch_shutdown(ds); 7412 7413 dev_set_drvdata(&mdiodev->dev, NULL); 7414 } 7415 7416 static const struct of_device_id mv88e6xxx_of_match[] = { 7417 { 7418 .compatible = "marvell,mv88e6085", 7419 .data = &mv88e6xxx_table[MV88E6085], 7420 }, 7421 { 7422 .compatible = "marvell,mv88e6190", 7423 .data = &mv88e6xxx_table[MV88E6190], 7424 }, 7425 { 7426 .compatible = "marvell,mv88e6250", 7427 .data = &mv88e6xxx_table[MV88E6250], 7428 }, 7429 { /* sentinel */ }, 7430 }; 7431 7432 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 7433 7434 static struct mdio_driver mv88e6xxx_driver = { 7435 .probe = mv88e6xxx_probe, 7436 .remove = mv88e6xxx_remove, 7437 .shutdown = mv88e6xxx_shutdown, 7438 .mdiodrv.driver = { 7439 .name = "mv88e6085", 7440 .of_match_table = mv88e6xxx_of_match, 7441 .pm = &mv88e6xxx_pm_ops, 7442 }, 7443 }; 7444 7445 mdio_module_driver(mv88e6xxx_driver); 7446 7447 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 7448 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 7449 MODULE_LICENSE("GPL"); 7450