1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Marvell 88e6xxx Ethernet switch single-chip support 4 * 5 * Copyright (c) 2008 Marvell Semiconductor 6 * 7 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 8 * 9 * Copyright (c) 2016-2017 Savoir-faire Linux Inc. 10 * Vivien Didelot <vivien.didelot@savoirfairelinux.com> 11 */ 12 13 #include <linux/bitfield.h> 14 #include <linux/delay.h> 15 #include <linux/dsa/mv88e6xxx.h> 16 #include <linux/etherdevice.h> 17 #include <linux/ethtool.h> 18 #include <linux/if_bridge.h> 19 #include <linux/interrupt.h> 20 #include <linux/irq.h> 21 #include <linux/irqdomain.h> 22 #include <linux/jiffies.h> 23 #include <linux/list.h> 24 #include <linux/mdio.h> 25 #include <linux/module.h> 26 #include <linux/of_device.h> 27 #include <linux/of_irq.h> 28 #include <linux/of_mdio.h> 29 #include <linux/platform_data/mv88e6xxx.h> 30 #include <linux/netdevice.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/phylink.h> 33 #include <net/dsa.h> 34 35 #include "chip.h" 36 #include "devlink.h" 37 #include "global1.h" 38 #include "global2.h" 39 #include "hwtstamp.h" 40 #include "phy.h" 41 #include "port.h" 42 #include "ptp.h" 43 #include "serdes.h" 44 #include "smi.h" 45 46 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 47 { 48 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 49 dev_err(chip->dev, "Switch registers lock not held!\n"); 50 dump_stack(); 51 } 52 } 53 54 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 55 { 56 int err; 57 58 assert_reg_lock(chip); 59 60 err = mv88e6xxx_smi_read(chip, addr, reg, val); 61 if (err) 62 return err; 63 64 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 65 addr, reg, *val); 66 67 return 0; 68 } 69 70 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 71 { 72 int err; 73 74 assert_reg_lock(chip); 75 76 err = mv88e6xxx_smi_write(chip, addr, reg, val); 77 if (err) 78 return err; 79 80 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 81 addr, reg, val); 82 83 return 0; 84 } 85 86 int mv88e6xxx_wait_mask(struct mv88e6xxx_chip *chip, int addr, int reg, 87 u16 mask, u16 val) 88 { 89 u16 data; 90 int err; 91 int i; 92 93 /* There's no bus specific operation to wait for a mask */ 94 for (i = 0; i < 16; i++) { 95 err = mv88e6xxx_read(chip, addr, reg, &data); 96 if (err) 97 return err; 98 99 if ((data & mask) == val) 100 return 0; 101 102 usleep_range(1000, 2000); 103 } 104 105 dev_err(chip->dev, "Timeout while waiting for switch\n"); 106 return -ETIMEDOUT; 107 } 108 109 int mv88e6xxx_wait_bit(struct mv88e6xxx_chip *chip, int addr, int reg, 110 int bit, int val) 111 { 112 return mv88e6xxx_wait_mask(chip, addr, reg, BIT(bit), 113 val ? BIT(bit) : 0x0000); 114 } 115 116 struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 117 { 118 struct mv88e6xxx_mdio_bus *mdio_bus; 119 120 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 121 list); 122 if (!mdio_bus) 123 return NULL; 124 125 return mdio_bus->bus; 126 } 127 128 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 129 { 130 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 131 unsigned int n = d->hwirq; 132 133 chip->g1_irq.masked |= (1 << n); 134 } 135 136 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 137 { 138 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 139 unsigned int n = d->hwirq; 140 141 chip->g1_irq.masked &= ~(1 << n); 142 } 143 144 static irqreturn_t mv88e6xxx_g1_irq_thread_work(struct mv88e6xxx_chip *chip) 145 { 146 unsigned int nhandled = 0; 147 unsigned int sub_irq; 148 unsigned int n; 149 u16 reg; 150 u16 ctl1; 151 int err; 152 153 mv88e6xxx_reg_lock(chip); 154 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 155 mv88e6xxx_reg_unlock(chip); 156 157 if (err) 158 goto out; 159 160 do { 161 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 162 if (reg & (1 << n)) { 163 sub_irq = irq_find_mapping(chip->g1_irq.domain, 164 n); 165 handle_nested_irq(sub_irq); 166 ++nhandled; 167 } 168 } 169 170 mv88e6xxx_reg_lock(chip); 171 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &ctl1); 172 if (err) 173 goto unlock; 174 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 175 unlock: 176 mv88e6xxx_reg_unlock(chip); 177 if (err) 178 goto out; 179 ctl1 &= GENMASK(chip->g1_irq.nirqs, 0); 180 } while (reg & ctl1); 181 182 out: 183 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 184 } 185 186 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 187 { 188 struct mv88e6xxx_chip *chip = dev_id; 189 190 return mv88e6xxx_g1_irq_thread_work(chip); 191 } 192 193 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 194 { 195 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 196 197 mv88e6xxx_reg_lock(chip); 198 } 199 200 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 201 { 202 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 203 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 204 u16 reg; 205 int err; 206 207 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, ®); 208 if (err) 209 goto out; 210 211 reg &= ~mask; 212 reg |= (~chip->g1_irq.masked & mask); 213 214 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, reg); 215 if (err) 216 goto out; 217 218 out: 219 mv88e6xxx_reg_unlock(chip); 220 } 221 222 static const struct irq_chip mv88e6xxx_g1_irq_chip = { 223 .name = "mv88e6xxx-g1", 224 .irq_mask = mv88e6xxx_g1_irq_mask, 225 .irq_unmask = mv88e6xxx_g1_irq_unmask, 226 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 227 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 228 }; 229 230 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 231 unsigned int irq, 232 irq_hw_number_t hwirq) 233 { 234 struct mv88e6xxx_chip *chip = d->host_data; 235 236 irq_set_chip_data(irq, d->host_data); 237 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 238 irq_set_noprobe(irq); 239 240 return 0; 241 } 242 243 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 244 .map = mv88e6xxx_g1_irq_domain_map, 245 .xlate = irq_domain_xlate_twocell, 246 }; 247 248 /* To be called with reg_lock held */ 249 static void mv88e6xxx_g1_irq_free_common(struct mv88e6xxx_chip *chip) 250 { 251 int irq, virq; 252 u16 mask; 253 254 mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 255 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 256 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 257 258 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 259 virq = irq_find_mapping(chip->g1_irq.domain, irq); 260 irq_dispose_mapping(virq); 261 } 262 263 irq_domain_remove(chip->g1_irq.domain); 264 } 265 266 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 267 { 268 /* 269 * free_irq must be called without reg_lock taken because the irq 270 * handler takes this lock, too. 271 */ 272 free_irq(chip->irq, chip); 273 274 mv88e6xxx_reg_lock(chip); 275 mv88e6xxx_g1_irq_free_common(chip); 276 mv88e6xxx_reg_unlock(chip); 277 } 278 279 static int mv88e6xxx_g1_irq_setup_common(struct mv88e6xxx_chip *chip) 280 { 281 int err, irq, virq; 282 u16 reg, mask; 283 284 chip->g1_irq.nirqs = chip->info->g1_irqs; 285 chip->g1_irq.domain = irq_domain_add_simple( 286 NULL, chip->g1_irq.nirqs, 0, 287 &mv88e6xxx_g1_irq_domain_ops, chip); 288 if (!chip->g1_irq.domain) 289 return -ENOMEM; 290 291 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 292 irq_create_mapping(chip->g1_irq.domain, irq); 293 294 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 295 chip->g1_irq.masked = ~0; 296 297 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_CTL1, &mask); 298 if (err) 299 goto out_mapping; 300 301 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 302 303 err = mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 304 if (err) 305 goto out_disable; 306 307 /* Reading the interrupt status clears (most of) them */ 308 err = mv88e6xxx_g1_read(chip, MV88E6XXX_G1_STS, ®); 309 if (err) 310 goto out_disable; 311 312 return 0; 313 314 out_disable: 315 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 316 mv88e6xxx_g1_write(chip, MV88E6XXX_G1_CTL1, mask); 317 318 out_mapping: 319 for (irq = 0; irq < 16; irq++) { 320 virq = irq_find_mapping(chip->g1_irq.domain, irq); 321 irq_dispose_mapping(virq); 322 } 323 324 irq_domain_remove(chip->g1_irq.domain); 325 326 return err; 327 } 328 329 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 330 { 331 static struct lock_class_key lock_key; 332 static struct lock_class_key request_key; 333 int err; 334 335 err = mv88e6xxx_g1_irq_setup_common(chip); 336 if (err) 337 return err; 338 339 /* These lock classes tells lockdep that global 1 irqs are in 340 * a different category than their parent GPIO, so it won't 341 * report false recursion. 342 */ 343 irq_set_lockdep_class(chip->irq, &lock_key, &request_key); 344 345 snprintf(chip->irq_name, sizeof(chip->irq_name), 346 "mv88e6xxx-%s", dev_name(chip->dev)); 347 348 mv88e6xxx_reg_unlock(chip); 349 err = request_threaded_irq(chip->irq, NULL, 350 mv88e6xxx_g1_irq_thread_fn, 351 IRQF_ONESHOT | IRQF_SHARED, 352 chip->irq_name, chip); 353 mv88e6xxx_reg_lock(chip); 354 if (err) 355 mv88e6xxx_g1_irq_free_common(chip); 356 357 return err; 358 } 359 360 static void mv88e6xxx_irq_poll(struct kthread_work *work) 361 { 362 struct mv88e6xxx_chip *chip = container_of(work, 363 struct mv88e6xxx_chip, 364 irq_poll_work.work); 365 mv88e6xxx_g1_irq_thread_work(chip); 366 367 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 368 msecs_to_jiffies(100)); 369 } 370 371 static int mv88e6xxx_irq_poll_setup(struct mv88e6xxx_chip *chip) 372 { 373 int err; 374 375 err = mv88e6xxx_g1_irq_setup_common(chip); 376 if (err) 377 return err; 378 379 kthread_init_delayed_work(&chip->irq_poll_work, 380 mv88e6xxx_irq_poll); 381 382 chip->kworker = kthread_create_worker(0, "%s", dev_name(chip->dev)); 383 if (IS_ERR(chip->kworker)) 384 return PTR_ERR(chip->kworker); 385 386 kthread_queue_delayed_work(chip->kworker, &chip->irq_poll_work, 387 msecs_to_jiffies(100)); 388 389 return 0; 390 } 391 392 static void mv88e6xxx_irq_poll_free(struct mv88e6xxx_chip *chip) 393 { 394 kthread_cancel_delayed_work_sync(&chip->irq_poll_work); 395 kthread_destroy_worker(chip->kworker); 396 397 mv88e6xxx_reg_lock(chip); 398 mv88e6xxx_g1_irq_free_common(chip); 399 mv88e6xxx_reg_unlock(chip); 400 } 401 402 static int mv88e6xxx_port_config_interface(struct mv88e6xxx_chip *chip, 403 int port, phy_interface_t interface) 404 { 405 int err; 406 407 if (chip->info->ops->port_set_rgmii_delay) { 408 err = chip->info->ops->port_set_rgmii_delay(chip, port, 409 interface); 410 if (err && err != -EOPNOTSUPP) 411 return err; 412 } 413 414 if (chip->info->ops->port_set_cmode) { 415 err = chip->info->ops->port_set_cmode(chip, port, 416 interface); 417 if (err && err != -EOPNOTSUPP) 418 return err; 419 } 420 421 return 0; 422 } 423 424 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 425 int link, int speed, int duplex, int pause, 426 phy_interface_t mode) 427 { 428 int err; 429 430 if (!chip->info->ops->port_set_link) 431 return 0; 432 433 /* Port's MAC control must not be changed unless the link is down */ 434 err = chip->info->ops->port_set_link(chip, port, LINK_FORCED_DOWN); 435 if (err) 436 return err; 437 438 if (chip->info->ops->port_set_speed_duplex) { 439 err = chip->info->ops->port_set_speed_duplex(chip, port, 440 speed, duplex); 441 if (err && err != -EOPNOTSUPP) 442 goto restore_link; 443 } 444 445 if (speed == SPEED_MAX && chip->info->ops->port_max_speed_mode) 446 mode = chip->info->ops->port_max_speed_mode(port); 447 448 if (chip->info->ops->port_set_pause) { 449 err = chip->info->ops->port_set_pause(chip, port, pause); 450 if (err) 451 goto restore_link; 452 } 453 454 err = mv88e6xxx_port_config_interface(chip, port, mode); 455 restore_link: 456 if (chip->info->ops->port_set_link(chip, port, link)) 457 dev_err(chip->dev, "p%d: failed to restore MAC's link\n", port); 458 459 return err; 460 } 461 462 static int mv88e6xxx_phy_is_internal(struct dsa_switch *ds, int port) 463 { 464 struct mv88e6xxx_chip *chip = ds->priv; 465 466 return port < chip->info->num_internal_phys; 467 } 468 469 static int mv88e6xxx_port_ppu_updates(struct mv88e6xxx_chip *chip, int port) 470 { 471 u16 reg; 472 int err; 473 474 /* The 88e6250 family does not have the PHY detect bit. Instead, 475 * report whether the port is internal. 476 */ 477 if (chip->info->family == MV88E6XXX_FAMILY_6250) 478 return port < chip->info->num_internal_phys; 479 480 err = mv88e6xxx_port_read(chip, port, MV88E6XXX_PORT_STS, ®); 481 if (err) { 482 dev_err(chip->dev, 483 "p%d: %s: failed to read port status\n", 484 port, __func__); 485 return err; 486 } 487 488 return !!(reg & MV88E6XXX_PORT_STS_PHY_DETECT); 489 } 490 491 static int mv88e6xxx_serdes_pcs_get_state(struct dsa_switch *ds, int port, 492 struct phylink_link_state *state) 493 { 494 struct mv88e6xxx_chip *chip = ds->priv; 495 int lane; 496 int err; 497 498 mv88e6xxx_reg_lock(chip); 499 lane = mv88e6xxx_serdes_get_lane(chip, port); 500 if (lane >= 0 && chip->info->ops->serdes_pcs_get_state) 501 err = chip->info->ops->serdes_pcs_get_state(chip, port, lane, 502 state); 503 else 504 err = -EOPNOTSUPP; 505 mv88e6xxx_reg_unlock(chip); 506 507 return err; 508 } 509 510 static int mv88e6xxx_serdes_pcs_config(struct mv88e6xxx_chip *chip, int port, 511 unsigned int mode, 512 phy_interface_t interface, 513 const unsigned long *advertise) 514 { 515 const struct mv88e6xxx_ops *ops = chip->info->ops; 516 int lane; 517 518 if (ops->serdes_pcs_config) { 519 lane = mv88e6xxx_serdes_get_lane(chip, port); 520 if (lane >= 0) 521 return ops->serdes_pcs_config(chip, port, lane, mode, 522 interface, advertise); 523 } 524 525 return 0; 526 } 527 528 static void mv88e6xxx_serdes_pcs_an_restart(struct dsa_switch *ds, int port) 529 { 530 struct mv88e6xxx_chip *chip = ds->priv; 531 const struct mv88e6xxx_ops *ops; 532 int err = 0; 533 int lane; 534 535 ops = chip->info->ops; 536 537 if (ops->serdes_pcs_an_restart) { 538 mv88e6xxx_reg_lock(chip); 539 lane = mv88e6xxx_serdes_get_lane(chip, port); 540 if (lane >= 0) 541 err = ops->serdes_pcs_an_restart(chip, port, lane); 542 mv88e6xxx_reg_unlock(chip); 543 544 if (err) 545 dev_err(ds->dev, "p%d: failed to restart AN\n", port); 546 } 547 } 548 549 static int mv88e6xxx_serdes_pcs_link_up(struct mv88e6xxx_chip *chip, int port, 550 unsigned int mode, 551 int speed, int duplex) 552 { 553 const struct mv88e6xxx_ops *ops = chip->info->ops; 554 int lane; 555 556 if (!phylink_autoneg_inband(mode) && ops->serdes_pcs_link_up) { 557 lane = mv88e6xxx_serdes_get_lane(chip, port); 558 if (lane >= 0) 559 return ops->serdes_pcs_link_up(chip, port, lane, 560 speed, duplex); 561 } 562 563 return 0; 564 } 565 566 static void mv88e6065_phylink_validate(struct mv88e6xxx_chip *chip, int port, 567 unsigned long *mask, 568 struct phylink_link_state *state) 569 { 570 if (!phy_interface_mode_is_8023z(state->interface)) { 571 /* 10M and 100M are only supported in non-802.3z mode */ 572 phylink_set(mask, 10baseT_Half); 573 phylink_set(mask, 10baseT_Full); 574 phylink_set(mask, 100baseT_Half); 575 phylink_set(mask, 100baseT_Full); 576 } 577 } 578 579 static void mv88e6185_phylink_validate(struct mv88e6xxx_chip *chip, int port, 580 unsigned long *mask, 581 struct phylink_link_state *state) 582 { 583 /* FIXME: if the port is in 1000Base-X mode, then it only supports 584 * 1000M FD speeds. In this case, CMODE will indicate 5. 585 */ 586 phylink_set(mask, 1000baseT_Full); 587 phylink_set(mask, 1000baseX_Full); 588 589 mv88e6065_phylink_validate(chip, port, mask, state); 590 } 591 592 static void mv88e6341_phylink_validate(struct mv88e6xxx_chip *chip, int port, 593 unsigned long *mask, 594 struct phylink_link_state *state) 595 { 596 if (port >= 5) 597 phylink_set(mask, 2500baseX_Full); 598 599 /* No ethtool bits for 200Mbps */ 600 phylink_set(mask, 1000baseT_Full); 601 phylink_set(mask, 1000baseX_Full); 602 603 mv88e6065_phylink_validate(chip, port, mask, state); 604 } 605 606 static void mv88e6352_phylink_validate(struct mv88e6xxx_chip *chip, int port, 607 unsigned long *mask, 608 struct phylink_link_state *state) 609 { 610 /* No ethtool bits for 200Mbps */ 611 phylink_set(mask, 1000baseT_Full); 612 phylink_set(mask, 1000baseX_Full); 613 614 mv88e6065_phylink_validate(chip, port, mask, state); 615 } 616 617 static void mv88e6390_phylink_validate(struct mv88e6xxx_chip *chip, int port, 618 unsigned long *mask, 619 struct phylink_link_state *state) 620 { 621 if (port >= 9) { 622 phylink_set(mask, 2500baseX_Full); 623 phylink_set(mask, 2500baseT_Full); 624 } 625 626 /* No ethtool bits for 200Mbps */ 627 phylink_set(mask, 1000baseT_Full); 628 phylink_set(mask, 1000baseX_Full); 629 630 mv88e6065_phylink_validate(chip, port, mask, state); 631 } 632 633 static void mv88e6390x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 634 unsigned long *mask, 635 struct phylink_link_state *state) 636 { 637 if (port >= 9) { 638 phylink_set(mask, 10000baseT_Full); 639 phylink_set(mask, 10000baseKR_Full); 640 } 641 642 mv88e6390_phylink_validate(chip, port, mask, state); 643 } 644 645 static void mv88e6393x_phylink_validate(struct mv88e6xxx_chip *chip, int port, 646 unsigned long *mask, 647 struct phylink_link_state *state) 648 { 649 bool is_6191x = 650 chip->info->prod_num == MV88E6XXX_PORT_SWITCH_ID_PROD_6191X; 651 652 if (((port == 0 || port == 9) && !is_6191x) || port == 10) { 653 phylink_set(mask, 10000baseT_Full); 654 phylink_set(mask, 10000baseKR_Full); 655 phylink_set(mask, 10000baseCR_Full); 656 phylink_set(mask, 10000baseSR_Full); 657 phylink_set(mask, 10000baseLR_Full); 658 phylink_set(mask, 10000baseLRM_Full); 659 phylink_set(mask, 10000baseER_Full); 660 phylink_set(mask, 5000baseT_Full); 661 phylink_set(mask, 2500baseX_Full); 662 phylink_set(mask, 2500baseT_Full); 663 } 664 665 phylink_set(mask, 1000baseT_Full); 666 phylink_set(mask, 1000baseX_Full); 667 668 mv88e6065_phylink_validate(chip, port, mask, state); 669 } 670 671 static void mv88e6xxx_validate(struct dsa_switch *ds, int port, 672 unsigned long *supported, 673 struct phylink_link_state *state) 674 { 675 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 676 struct mv88e6xxx_chip *chip = ds->priv; 677 678 /* Allow all the expected bits */ 679 phylink_set(mask, Autoneg); 680 phylink_set(mask, Pause); 681 phylink_set_port_modes(mask); 682 683 if (chip->info->ops->phylink_validate) 684 chip->info->ops->phylink_validate(chip, port, mask, state); 685 686 linkmode_and(supported, supported, mask); 687 linkmode_and(state->advertising, state->advertising, mask); 688 689 /* We can only operate at 2500BaseX or 1000BaseX. If requested 690 * to advertise both, only report advertising at 2500BaseX. 691 */ 692 phylink_helper_basex_speed(state); 693 } 694 695 static void mv88e6xxx_mac_config(struct dsa_switch *ds, int port, 696 unsigned int mode, 697 const struct phylink_link_state *state) 698 { 699 struct mv88e6xxx_chip *chip = ds->priv; 700 struct mv88e6xxx_port *p; 701 int err = 0; 702 703 p = &chip->ports[port]; 704 705 mv88e6xxx_reg_lock(chip); 706 707 if (mode != MLO_AN_PHY || !mv88e6xxx_phy_is_internal(ds, port)) { 708 /* In inband mode, the link may come up at any time while the 709 * link is not forced down. Force the link down while we 710 * reconfigure the interface mode. 711 */ 712 if (mode == MLO_AN_INBAND && 713 p->interface != state->interface && 714 chip->info->ops->port_set_link) 715 chip->info->ops->port_set_link(chip, port, 716 LINK_FORCED_DOWN); 717 718 err = mv88e6xxx_port_config_interface(chip, port, 719 state->interface); 720 if (err && err != -EOPNOTSUPP) 721 goto err_unlock; 722 723 err = mv88e6xxx_serdes_pcs_config(chip, port, mode, 724 state->interface, 725 state->advertising); 726 /* FIXME: we should restart negotiation if something changed - 727 * which is something we get if we convert to using phylinks 728 * PCS operations. 729 */ 730 if (err > 0) 731 err = 0; 732 } 733 734 /* Undo the forced down state above after completing configuration 735 * irrespective of its state on entry, which allows the link to come 736 * up in the in-band case where there is no separate SERDES. Also 737 * ensure that the link can come up if the PPU is in use and we are 738 * in PHY mode (we treat the PPU as an effective in-band mechanism.) 739 */ 740 if (chip->info->ops->port_set_link && 741 ((mode == MLO_AN_INBAND && p->interface != state->interface) || 742 (mode == MLO_AN_PHY && mv88e6xxx_port_ppu_updates(chip, port)))) 743 chip->info->ops->port_set_link(chip, port, LINK_UNFORCED); 744 745 p->interface = state->interface; 746 747 err_unlock: 748 mv88e6xxx_reg_unlock(chip); 749 750 if (err && err != -EOPNOTSUPP) 751 dev_err(ds->dev, "p%d: failed to configure MAC/PCS\n", port); 752 } 753 754 static void mv88e6xxx_mac_link_down(struct dsa_switch *ds, int port, 755 unsigned int mode, 756 phy_interface_t interface) 757 { 758 struct mv88e6xxx_chip *chip = ds->priv; 759 const struct mv88e6xxx_ops *ops; 760 int err = 0; 761 762 ops = chip->info->ops; 763 764 mv88e6xxx_reg_lock(chip); 765 /* Force the link down if we know the port may not be automatically 766 * updated by the switch or if we are using fixed-link mode. 767 */ 768 if ((!mv88e6xxx_port_ppu_updates(chip, port) || 769 mode == MLO_AN_FIXED) && ops->port_sync_link) 770 err = ops->port_sync_link(chip, port, mode, false); 771 772 if (!err && ops->port_set_speed_duplex) 773 err = ops->port_set_speed_duplex(chip, port, SPEED_UNFORCED, 774 DUPLEX_UNFORCED); 775 mv88e6xxx_reg_unlock(chip); 776 777 if (err) 778 dev_err(chip->dev, 779 "p%d: failed to force MAC link down\n", port); 780 } 781 782 static void mv88e6xxx_mac_link_up(struct dsa_switch *ds, int port, 783 unsigned int mode, phy_interface_t interface, 784 struct phy_device *phydev, 785 int speed, int duplex, 786 bool tx_pause, bool rx_pause) 787 { 788 struct mv88e6xxx_chip *chip = ds->priv; 789 const struct mv88e6xxx_ops *ops; 790 int err = 0; 791 792 ops = chip->info->ops; 793 794 mv88e6xxx_reg_lock(chip); 795 /* Configure and force the link up if we know that the port may not 796 * automatically updated by the switch or if we are using fixed-link 797 * mode. 798 */ 799 if (!mv88e6xxx_port_ppu_updates(chip, port) || 800 mode == MLO_AN_FIXED) { 801 /* FIXME: for an automedia port, should we force the link 802 * down here - what if the link comes up due to "other" media 803 * while we're bringing the port up, how is the exclusivity 804 * handled in the Marvell hardware? E.g. port 2 on 88E6390 805 * shared between internal PHY and Serdes. 806 */ 807 err = mv88e6xxx_serdes_pcs_link_up(chip, port, mode, speed, 808 duplex); 809 if (err) 810 goto error; 811 812 if (ops->port_set_speed_duplex) { 813 err = ops->port_set_speed_duplex(chip, port, 814 speed, duplex); 815 if (err && err != -EOPNOTSUPP) 816 goto error; 817 } 818 819 if (ops->port_sync_link) 820 err = ops->port_sync_link(chip, port, mode, true); 821 } 822 error: 823 mv88e6xxx_reg_unlock(chip); 824 825 if (err && err != -EOPNOTSUPP) 826 dev_err(ds->dev, 827 "p%d: failed to configure MAC link up\n", port); 828 } 829 830 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 831 { 832 if (!chip->info->ops->stats_snapshot) 833 return -EOPNOTSUPP; 834 835 return chip->info->ops->stats_snapshot(chip, port); 836 } 837 838 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 839 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 840 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 841 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 842 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 843 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 844 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 845 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 846 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 847 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 848 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 849 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 850 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 851 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 852 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 853 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 854 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 855 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 856 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 857 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 858 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 859 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 860 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 861 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 862 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 863 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 864 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 865 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 866 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 867 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 868 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 869 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 870 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 871 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 872 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 873 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 874 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 875 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 876 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 877 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 878 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 879 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 880 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 881 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 882 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 883 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 884 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 885 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 886 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 887 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 888 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 889 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 890 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 891 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 892 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 893 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 894 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 895 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 896 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 897 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 898 }; 899 900 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 901 struct mv88e6xxx_hw_stat *s, 902 int port, u16 bank1_select, 903 u16 histogram) 904 { 905 u32 low; 906 u32 high = 0; 907 u16 reg = 0; 908 int err; 909 u64 value; 910 911 switch (s->type) { 912 case STATS_TYPE_PORT: 913 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 914 if (err) 915 return U64_MAX; 916 917 low = reg; 918 if (s->size == 4) { 919 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 920 if (err) 921 return U64_MAX; 922 low |= ((u32)reg) << 16; 923 } 924 break; 925 case STATS_TYPE_BANK1: 926 reg = bank1_select; 927 fallthrough; 928 case STATS_TYPE_BANK0: 929 reg |= s->reg | histogram; 930 mv88e6xxx_g1_stats_read(chip, reg, &low); 931 if (s->size == 8) 932 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 933 break; 934 default: 935 return U64_MAX; 936 } 937 value = (((u64)high) << 32) | low; 938 return value; 939 } 940 941 static int mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 942 uint8_t *data, int types) 943 { 944 struct mv88e6xxx_hw_stat *stat; 945 int i, j; 946 947 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 948 stat = &mv88e6xxx_hw_stats[i]; 949 if (stat->type & types) { 950 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 951 ETH_GSTRING_LEN); 952 j++; 953 } 954 } 955 956 return j; 957 } 958 959 static int mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 960 uint8_t *data) 961 { 962 return mv88e6xxx_stats_get_strings(chip, data, 963 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 964 } 965 966 static int mv88e6250_stats_get_strings(struct mv88e6xxx_chip *chip, 967 uint8_t *data) 968 { 969 return mv88e6xxx_stats_get_strings(chip, data, STATS_TYPE_BANK0); 970 } 971 972 static int mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 973 uint8_t *data) 974 { 975 return mv88e6xxx_stats_get_strings(chip, data, 976 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 977 } 978 979 static const uint8_t *mv88e6xxx_atu_vtu_stats_strings[] = { 980 "atu_member_violation", 981 "atu_miss_violation", 982 "atu_full_violation", 983 "vtu_member_violation", 984 "vtu_miss_violation", 985 }; 986 987 static void mv88e6xxx_atu_vtu_get_strings(uint8_t *data) 988 { 989 unsigned int i; 990 991 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); i++) 992 strlcpy(data + i * ETH_GSTRING_LEN, 993 mv88e6xxx_atu_vtu_stats_strings[i], 994 ETH_GSTRING_LEN); 995 } 996 997 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 998 u32 stringset, uint8_t *data) 999 { 1000 struct mv88e6xxx_chip *chip = ds->priv; 1001 int count = 0; 1002 1003 if (stringset != ETH_SS_STATS) 1004 return; 1005 1006 mv88e6xxx_reg_lock(chip); 1007 1008 if (chip->info->ops->stats_get_strings) 1009 count = chip->info->ops->stats_get_strings(chip, data); 1010 1011 if (chip->info->ops->serdes_get_strings) { 1012 data += count * ETH_GSTRING_LEN; 1013 count = chip->info->ops->serdes_get_strings(chip, port, data); 1014 } 1015 1016 data += count * ETH_GSTRING_LEN; 1017 mv88e6xxx_atu_vtu_get_strings(data); 1018 1019 mv88e6xxx_reg_unlock(chip); 1020 } 1021 1022 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 1023 int types) 1024 { 1025 struct mv88e6xxx_hw_stat *stat; 1026 int i, j; 1027 1028 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1029 stat = &mv88e6xxx_hw_stats[i]; 1030 if (stat->type & types) 1031 j++; 1032 } 1033 return j; 1034 } 1035 1036 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1037 { 1038 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1039 STATS_TYPE_PORT); 1040 } 1041 1042 static int mv88e6250_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1043 { 1044 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0); 1045 } 1046 1047 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 1048 { 1049 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 1050 STATS_TYPE_BANK1); 1051 } 1052 1053 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds, int port, int sset) 1054 { 1055 struct mv88e6xxx_chip *chip = ds->priv; 1056 int serdes_count = 0; 1057 int count = 0; 1058 1059 if (sset != ETH_SS_STATS) 1060 return 0; 1061 1062 mv88e6xxx_reg_lock(chip); 1063 if (chip->info->ops->stats_get_sset_count) 1064 count = chip->info->ops->stats_get_sset_count(chip); 1065 if (count < 0) 1066 goto out; 1067 1068 if (chip->info->ops->serdes_get_sset_count) 1069 serdes_count = chip->info->ops->serdes_get_sset_count(chip, 1070 port); 1071 if (serdes_count < 0) { 1072 count = serdes_count; 1073 goto out; 1074 } 1075 count += serdes_count; 1076 count += ARRAY_SIZE(mv88e6xxx_atu_vtu_stats_strings); 1077 1078 out: 1079 mv88e6xxx_reg_unlock(chip); 1080 1081 return count; 1082 } 1083 1084 static int mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1085 uint64_t *data, int types, 1086 u16 bank1_select, u16 histogram) 1087 { 1088 struct mv88e6xxx_hw_stat *stat; 1089 int i, j; 1090 1091 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 1092 stat = &mv88e6xxx_hw_stats[i]; 1093 if (stat->type & types) { 1094 mv88e6xxx_reg_lock(chip); 1095 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 1096 bank1_select, 1097 histogram); 1098 mv88e6xxx_reg_unlock(chip); 1099 1100 j++; 1101 } 1102 } 1103 return j; 1104 } 1105 1106 static int mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1107 uint64_t *data) 1108 { 1109 return mv88e6xxx_stats_get_stats(chip, port, data, 1110 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 1111 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1112 } 1113 1114 static int mv88e6250_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1115 uint64_t *data) 1116 { 1117 return mv88e6xxx_stats_get_stats(chip, port, data, STATS_TYPE_BANK0, 1118 0, MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1119 } 1120 1121 static int mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1122 uint64_t *data) 1123 { 1124 return mv88e6xxx_stats_get_stats(chip, port, data, 1125 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1126 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_9, 1127 MV88E6XXX_G1_STATS_OP_HIST_RX_TX); 1128 } 1129 1130 static int mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 1131 uint64_t *data) 1132 { 1133 return mv88e6xxx_stats_get_stats(chip, port, data, 1134 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1135 MV88E6XXX_G1_STATS_OP_BANK_1_BIT_10, 1136 0); 1137 } 1138 1139 static void mv88e6xxx_atu_vtu_get_stats(struct mv88e6xxx_chip *chip, int port, 1140 uint64_t *data) 1141 { 1142 *data++ = chip->ports[port].atu_member_violation; 1143 *data++ = chip->ports[port].atu_miss_violation; 1144 *data++ = chip->ports[port].atu_full_violation; 1145 *data++ = chip->ports[port].vtu_member_violation; 1146 *data++ = chip->ports[port].vtu_miss_violation; 1147 } 1148 1149 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1150 uint64_t *data) 1151 { 1152 int count = 0; 1153 1154 if (chip->info->ops->stats_get_stats) 1155 count = chip->info->ops->stats_get_stats(chip, port, data); 1156 1157 mv88e6xxx_reg_lock(chip); 1158 if (chip->info->ops->serdes_get_stats) { 1159 data += count; 1160 count = chip->info->ops->serdes_get_stats(chip, port, data); 1161 } 1162 data += count; 1163 mv88e6xxx_atu_vtu_get_stats(chip, port, data); 1164 mv88e6xxx_reg_unlock(chip); 1165 } 1166 1167 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1168 uint64_t *data) 1169 { 1170 struct mv88e6xxx_chip *chip = ds->priv; 1171 int ret; 1172 1173 mv88e6xxx_reg_lock(chip); 1174 1175 ret = mv88e6xxx_stats_snapshot(chip, port); 1176 mv88e6xxx_reg_unlock(chip); 1177 1178 if (ret < 0) 1179 return; 1180 1181 mv88e6xxx_get_stats(chip, port, data); 1182 1183 } 1184 1185 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1186 { 1187 struct mv88e6xxx_chip *chip = ds->priv; 1188 int len; 1189 1190 len = 32 * sizeof(u16); 1191 if (chip->info->ops->serdes_get_regs_len) 1192 len += chip->info->ops->serdes_get_regs_len(chip, port); 1193 1194 return len; 1195 } 1196 1197 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1198 struct ethtool_regs *regs, void *_p) 1199 { 1200 struct mv88e6xxx_chip *chip = ds->priv; 1201 int err; 1202 u16 reg; 1203 u16 *p = _p; 1204 int i; 1205 1206 regs->version = chip->info->prod_num; 1207 1208 memset(p, 0xff, 32 * sizeof(u16)); 1209 1210 mv88e6xxx_reg_lock(chip); 1211 1212 for (i = 0; i < 32; i++) { 1213 1214 err = mv88e6xxx_port_read(chip, port, i, ®); 1215 if (!err) 1216 p[i] = reg; 1217 } 1218 1219 if (chip->info->ops->serdes_get_regs) 1220 chip->info->ops->serdes_get_regs(chip, port, &p[i]); 1221 1222 mv88e6xxx_reg_unlock(chip); 1223 } 1224 1225 static int mv88e6xxx_get_mac_eee(struct dsa_switch *ds, int port, 1226 struct ethtool_eee *e) 1227 { 1228 /* Nothing to do on the port's MAC */ 1229 return 0; 1230 } 1231 1232 static int mv88e6xxx_set_mac_eee(struct dsa_switch *ds, int port, 1233 struct ethtool_eee *e) 1234 { 1235 /* Nothing to do on the port's MAC */ 1236 return 0; 1237 } 1238 1239 /* Mask of the local ports allowed to receive frames from a given fabric port */ 1240 static u16 mv88e6xxx_port_vlan(struct mv88e6xxx_chip *chip, int dev, int port) 1241 { 1242 struct dsa_switch *ds = chip->ds; 1243 struct dsa_switch_tree *dst = ds->dst; 1244 struct net_device *br; 1245 struct dsa_port *dp; 1246 bool found = false; 1247 u16 pvlan; 1248 1249 /* dev is a physical switch */ 1250 if (dev <= dst->last_switch) { 1251 list_for_each_entry(dp, &dst->ports, list) { 1252 if (dp->ds->index == dev && dp->index == port) { 1253 /* dp might be a DSA link or a user port, so it 1254 * might or might not have a bridge_dev 1255 * pointer. Use the "found" variable for both 1256 * cases. 1257 */ 1258 br = dp->bridge_dev; 1259 found = true; 1260 break; 1261 } 1262 } 1263 /* dev is a virtual bridge */ 1264 } else { 1265 list_for_each_entry(dp, &dst->ports, list) { 1266 if (dp->bridge_num < 0) 1267 continue; 1268 1269 if (dp->bridge_num + 1 + dst->last_switch != dev) 1270 continue; 1271 1272 br = dp->bridge_dev; 1273 found = true; 1274 break; 1275 } 1276 } 1277 1278 /* Prevent frames from unknown switch or virtual bridge */ 1279 if (!found) 1280 return 0; 1281 1282 /* Frames from DSA links and CPU ports can egress any local port */ 1283 if (dp->type == DSA_PORT_TYPE_CPU || dp->type == DSA_PORT_TYPE_DSA) 1284 return mv88e6xxx_port_mask(chip); 1285 1286 pvlan = 0; 1287 1288 /* Frames from user ports can egress any local DSA links and CPU ports, 1289 * as well as any local member of their bridge group. 1290 */ 1291 list_for_each_entry(dp, &dst->ports, list) 1292 if (dp->ds == ds && 1293 (dp->type == DSA_PORT_TYPE_CPU || 1294 dp->type == DSA_PORT_TYPE_DSA || 1295 (br && dp->bridge_dev == br))) 1296 pvlan |= BIT(dp->index); 1297 1298 return pvlan; 1299 } 1300 1301 static int mv88e6xxx_port_vlan_map(struct mv88e6xxx_chip *chip, int port) 1302 { 1303 u16 output_ports = mv88e6xxx_port_vlan(chip, chip->ds->index, port); 1304 1305 /* prevent frames from going back out of the port they came in on */ 1306 output_ports &= ~BIT(port); 1307 1308 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1309 } 1310 1311 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1312 u8 state) 1313 { 1314 struct mv88e6xxx_chip *chip = ds->priv; 1315 int err; 1316 1317 mv88e6xxx_reg_lock(chip); 1318 err = mv88e6xxx_port_set_state(chip, port, state); 1319 mv88e6xxx_reg_unlock(chip); 1320 1321 if (err) 1322 dev_err(ds->dev, "p%d: failed to update state\n", port); 1323 } 1324 1325 static int mv88e6xxx_pri_setup(struct mv88e6xxx_chip *chip) 1326 { 1327 int err; 1328 1329 if (chip->info->ops->ieee_pri_map) { 1330 err = chip->info->ops->ieee_pri_map(chip); 1331 if (err) 1332 return err; 1333 } 1334 1335 if (chip->info->ops->ip_pri_map) { 1336 err = chip->info->ops->ip_pri_map(chip); 1337 if (err) 1338 return err; 1339 } 1340 1341 return 0; 1342 } 1343 1344 static int mv88e6xxx_devmap_setup(struct mv88e6xxx_chip *chip) 1345 { 1346 struct dsa_switch *ds = chip->ds; 1347 int target, port; 1348 int err; 1349 1350 if (!chip->info->global2_addr) 1351 return 0; 1352 1353 /* Initialize the routing port to the 32 possible target devices */ 1354 for (target = 0; target < 32; target++) { 1355 port = dsa_routing_port(ds, target); 1356 if (port == ds->num_ports) 1357 port = 0x1f; 1358 1359 err = mv88e6xxx_g2_device_mapping_write(chip, target, port); 1360 if (err) 1361 return err; 1362 } 1363 1364 if (chip->info->ops->set_cascade_port) { 1365 port = MV88E6XXX_CASCADE_PORT_MULTIPLE; 1366 err = chip->info->ops->set_cascade_port(chip, port); 1367 if (err) 1368 return err; 1369 } 1370 1371 err = mv88e6xxx_g1_set_device_number(chip, chip->ds->index); 1372 if (err) 1373 return err; 1374 1375 return 0; 1376 } 1377 1378 static int mv88e6xxx_trunk_setup(struct mv88e6xxx_chip *chip) 1379 { 1380 /* Clear all trunk masks and mapping */ 1381 if (chip->info->global2_addr) 1382 return mv88e6xxx_g2_trunk_clear(chip); 1383 1384 return 0; 1385 } 1386 1387 static int mv88e6xxx_rmu_setup(struct mv88e6xxx_chip *chip) 1388 { 1389 if (chip->info->ops->rmu_disable) 1390 return chip->info->ops->rmu_disable(chip); 1391 1392 return 0; 1393 } 1394 1395 static int mv88e6xxx_pot_setup(struct mv88e6xxx_chip *chip) 1396 { 1397 if (chip->info->ops->pot_clear) 1398 return chip->info->ops->pot_clear(chip); 1399 1400 return 0; 1401 } 1402 1403 static int mv88e6xxx_rsvd2cpu_setup(struct mv88e6xxx_chip *chip) 1404 { 1405 if (chip->info->ops->mgmt_rsvd2cpu) 1406 return chip->info->ops->mgmt_rsvd2cpu(chip); 1407 1408 return 0; 1409 } 1410 1411 static int mv88e6xxx_atu_setup(struct mv88e6xxx_chip *chip) 1412 { 1413 int err; 1414 1415 err = mv88e6xxx_g1_atu_flush(chip, 0, true); 1416 if (err) 1417 return err; 1418 1419 /* The chips that have a "learn2all" bit in Global1, ATU 1420 * Control are precisely those whose port registers have a 1421 * Message Port bit in Port Control 1 and hence implement 1422 * ->port_setup_message_port. 1423 */ 1424 if (chip->info->ops->port_setup_message_port) { 1425 err = mv88e6xxx_g1_atu_set_learn2all(chip, true); 1426 if (err) 1427 return err; 1428 } 1429 1430 return mv88e6xxx_g1_atu_set_age_time(chip, 300000); 1431 } 1432 1433 static int mv88e6xxx_irl_setup(struct mv88e6xxx_chip *chip) 1434 { 1435 int port; 1436 int err; 1437 1438 if (!chip->info->ops->irl_init_all) 1439 return 0; 1440 1441 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 1442 /* Disable ingress rate limiting by resetting all per port 1443 * ingress rate limit resources to their initial state. 1444 */ 1445 err = chip->info->ops->irl_init_all(chip, port); 1446 if (err) 1447 return err; 1448 } 1449 1450 return 0; 1451 } 1452 1453 static int mv88e6xxx_mac_setup(struct mv88e6xxx_chip *chip) 1454 { 1455 if (chip->info->ops->set_switch_mac) { 1456 u8 addr[ETH_ALEN]; 1457 1458 eth_random_addr(addr); 1459 1460 return chip->info->ops->set_switch_mac(chip, addr); 1461 } 1462 1463 return 0; 1464 } 1465 1466 static int mv88e6xxx_pvt_map(struct mv88e6xxx_chip *chip, int dev, int port) 1467 { 1468 struct dsa_switch_tree *dst = chip->ds->dst; 1469 struct dsa_switch *ds; 1470 struct dsa_port *dp; 1471 u16 pvlan = 0; 1472 1473 if (!mv88e6xxx_has_pvt(chip)) 1474 return 0; 1475 1476 /* Skip the local source device, which uses in-chip port VLAN */ 1477 if (dev != chip->ds->index) { 1478 pvlan = mv88e6xxx_port_vlan(chip, dev, port); 1479 1480 ds = dsa_switch_find(dst->index, dev); 1481 dp = ds ? dsa_to_port(ds, port) : NULL; 1482 if (dp && dp->lag_dev) { 1483 /* As the PVT is used to limit flooding of 1484 * FORWARD frames, which use the LAG ID as the 1485 * source port, we must translate dev/port to 1486 * the special "LAG device" in the PVT, using 1487 * the LAG ID as the port number. 1488 */ 1489 dev = MV88E6XXX_G2_PVT_ADDR_DEV_TRUNK; 1490 port = dsa_lag_id(dst, dp->lag_dev); 1491 } 1492 } 1493 1494 return mv88e6xxx_g2_pvt_write(chip, dev, port, pvlan); 1495 } 1496 1497 static int mv88e6xxx_pvt_setup(struct mv88e6xxx_chip *chip) 1498 { 1499 int dev, port; 1500 int err; 1501 1502 if (!mv88e6xxx_has_pvt(chip)) 1503 return 0; 1504 1505 /* Clear 5 Bit Port for usage with Marvell Link Street devices: 1506 * use 4 bits for the Src_Port/Src_Trunk and 5 bits for the Src_Dev. 1507 */ 1508 err = mv88e6xxx_g2_misc_4_bit_port(chip); 1509 if (err) 1510 return err; 1511 1512 for (dev = 0; dev < MV88E6XXX_MAX_PVT_SWITCHES; ++dev) { 1513 for (port = 0; port < MV88E6XXX_MAX_PVT_PORTS; ++port) { 1514 err = mv88e6xxx_pvt_map(chip, dev, port); 1515 if (err) 1516 return err; 1517 } 1518 } 1519 1520 return 0; 1521 } 1522 1523 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1524 { 1525 struct mv88e6xxx_chip *chip = ds->priv; 1526 int err; 1527 1528 if (dsa_to_port(ds, port)->lag_dev) 1529 /* Hardware is incapable of fast-aging a LAG through a 1530 * regular ATU move operation. Until we have something 1531 * more fancy in place this is a no-op. 1532 */ 1533 return; 1534 1535 mv88e6xxx_reg_lock(chip); 1536 err = mv88e6xxx_g1_atu_remove(chip, 0, port, false); 1537 mv88e6xxx_reg_unlock(chip); 1538 1539 if (err) 1540 dev_err(ds->dev, "p%d: failed to flush ATU\n", port); 1541 } 1542 1543 static int mv88e6xxx_vtu_setup(struct mv88e6xxx_chip *chip) 1544 { 1545 if (!mv88e6xxx_max_vid(chip)) 1546 return 0; 1547 1548 return mv88e6xxx_g1_vtu_flush(chip); 1549 } 1550 1551 static int mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1552 struct mv88e6xxx_vtu_entry *entry) 1553 { 1554 int err; 1555 1556 if (!chip->info->ops->vtu_getnext) 1557 return -EOPNOTSUPP; 1558 1559 entry->vid = vid ? vid - 1 : mv88e6xxx_max_vid(chip); 1560 entry->valid = false; 1561 1562 err = chip->info->ops->vtu_getnext(chip, entry); 1563 1564 if (entry->vid != vid) 1565 entry->valid = false; 1566 1567 return err; 1568 } 1569 1570 static int mv88e6xxx_vtu_walk(struct mv88e6xxx_chip *chip, 1571 int (*cb)(struct mv88e6xxx_chip *chip, 1572 const struct mv88e6xxx_vtu_entry *entry, 1573 void *priv), 1574 void *priv) 1575 { 1576 struct mv88e6xxx_vtu_entry entry = { 1577 .vid = mv88e6xxx_max_vid(chip), 1578 .valid = false, 1579 }; 1580 int err; 1581 1582 if (!chip->info->ops->vtu_getnext) 1583 return -EOPNOTSUPP; 1584 1585 do { 1586 err = chip->info->ops->vtu_getnext(chip, &entry); 1587 if (err) 1588 return err; 1589 1590 if (!entry.valid) 1591 break; 1592 1593 err = cb(chip, &entry, priv); 1594 if (err) 1595 return err; 1596 } while (entry.vid < mv88e6xxx_max_vid(chip)); 1597 1598 return 0; 1599 } 1600 1601 static int mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1602 struct mv88e6xxx_vtu_entry *entry) 1603 { 1604 if (!chip->info->ops->vtu_loadpurge) 1605 return -EOPNOTSUPP; 1606 1607 return chip->info->ops->vtu_loadpurge(chip, entry); 1608 } 1609 1610 static int mv88e6xxx_fid_map_vlan(struct mv88e6xxx_chip *chip, 1611 const struct mv88e6xxx_vtu_entry *entry, 1612 void *_fid_bitmap) 1613 { 1614 unsigned long *fid_bitmap = _fid_bitmap; 1615 1616 set_bit(entry->fid, fid_bitmap); 1617 return 0; 1618 } 1619 1620 int mv88e6xxx_fid_map(struct mv88e6xxx_chip *chip, unsigned long *fid_bitmap) 1621 { 1622 int i, err; 1623 u16 fid; 1624 1625 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1626 1627 /* Set every FID bit used by the (un)bridged ports */ 1628 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1629 err = mv88e6xxx_port_get_fid(chip, i, &fid); 1630 if (err) 1631 return err; 1632 1633 set_bit(fid, fid_bitmap); 1634 } 1635 1636 /* Set every FID bit used by the VLAN entries */ 1637 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_fid_map_vlan, fid_bitmap); 1638 } 1639 1640 static int mv88e6xxx_atu_new(struct mv88e6xxx_chip *chip, u16 *fid) 1641 { 1642 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1643 int err; 1644 1645 err = mv88e6xxx_fid_map(chip, fid_bitmap); 1646 if (err) 1647 return err; 1648 1649 /* The reset value 0x000 is used to indicate that multiple address 1650 * databases are not needed. Return the next positive available. 1651 */ 1652 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1653 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1654 return -ENOSPC; 1655 1656 /* Clear the database */ 1657 return mv88e6xxx_g1_atu_flush(chip, *fid, true); 1658 } 1659 1660 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1661 u16 vid) 1662 { 1663 struct mv88e6xxx_chip *chip = ds->priv; 1664 struct mv88e6xxx_vtu_entry vlan; 1665 int i, err; 1666 1667 /* DSA and CPU ports have to be members of multiple vlans */ 1668 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 1669 return 0; 1670 1671 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1672 if (err) 1673 return err; 1674 1675 if (!vlan.valid) 1676 return 0; 1677 1678 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1679 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1680 continue; 1681 1682 if (!dsa_to_port(ds, i)->slave) 1683 continue; 1684 1685 if (vlan.member[i] == 1686 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1687 continue; 1688 1689 if (dsa_to_port(ds, i)->bridge_dev == 1690 dsa_to_port(ds, port)->bridge_dev) 1691 break; /* same bridge, check next VLAN */ 1692 1693 if (!dsa_to_port(ds, i)->bridge_dev) 1694 continue; 1695 1696 dev_err(ds->dev, "p%d: hw VLAN %d already used by port %d in %s\n", 1697 port, vlan.vid, i, 1698 netdev_name(dsa_to_port(ds, i)->bridge_dev)); 1699 return -EOPNOTSUPP; 1700 } 1701 1702 return 0; 1703 } 1704 1705 static int mv88e6xxx_port_commit_pvid(struct mv88e6xxx_chip *chip, int port) 1706 { 1707 struct dsa_port *dp = dsa_to_port(chip->ds, port); 1708 struct mv88e6xxx_port *p = &chip->ports[port]; 1709 u16 pvid = MV88E6XXX_VID_STANDALONE; 1710 bool drop_untagged = false; 1711 int err; 1712 1713 if (dp->bridge_dev) { 1714 if (br_vlan_enabled(dp->bridge_dev)) { 1715 pvid = p->bridge_pvid.vid; 1716 drop_untagged = !p->bridge_pvid.valid; 1717 } else { 1718 pvid = MV88E6XXX_VID_BRIDGED; 1719 } 1720 } 1721 1722 err = mv88e6xxx_port_set_pvid(chip, port, pvid); 1723 if (err) 1724 return err; 1725 1726 return mv88e6xxx_port_drop_untagged(chip, port, drop_untagged); 1727 } 1728 1729 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1730 bool vlan_filtering, 1731 struct netlink_ext_ack *extack) 1732 { 1733 struct mv88e6xxx_chip *chip = ds->priv; 1734 u16 mode = vlan_filtering ? MV88E6XXX_PORT_CTL2_8021Q_MODE_SECURE : 1735 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED; 1736 int err; 1737 1738 if (!mv88e6xxx_max_vid(chip)) 1739 return -EOPNOTSUPP; 1740 1741 mv88e6xxx_reg_lock(chip); 1742 1743 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1744 if (err) 1745 goto unlock; 1746 1747 err = mv88e6xxx_port_commit_pvid(chip, port); 1748 if (err) 1749 goto unlock; 1750 1751 unlock: 1752 mv88e6xxx_reg_unlock(chip); 1753 1754 return err; 1755 } 1756 1757 static int 1758 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1759 const struct switchdev_obj_port_vlan *vlan) 1760 { 1761 struct mv88e6xxx_chip *chip = ds->priv; 1762 int err; 1763 1764 if (!mv88e6xxx_max_vid(chip)) 1765 return -EOPNOTSUPP; 1766 1767 /* If the requested port doesn't belong to the same bridge as the VLAN 1768 * members, do not support it (yet) and fallback to software VLAN. 1769 */ 1770 mv88e6xxx_reg_lock(chip); 1771 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid); 1772 mv88e6xxx_reg_unlock(chip); 1773 1774 return err; 1775 } 1776 1777 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 1778 const unsigned char *addr, u16 vid, 1779 u8 state) 1780 { 1781 struct mv88e6xxx_atu_entry entry; 1782 struct mv88e6xxx_vtu_entry vlan; 1783 u16 fid; 1784 int err; 1785 1786 /* Ports have two private address databases: one for when the port is 1787 * standalone and one for when the port is under a bridge and the 1788 * 802.1Q mode is disabled. When the port is standalone, DSA wants its 1789 * address database to remain 100% empty, so we never load an ATU entry 1790 * into a standalone port's database. Therefore, translate the null 1791 * VLAN ID into the port's database used for VLAN-unaware bridging. 1792 */ 1793 if (vid == 0) { 1794 fid = MV88E6XXX_FID_BRIDGED; 1795 } else { 1796 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 1797 if (err) 1798 return err; 1799 1800 /* switchdev expects -EOPNOTSUPP to honor software VLANs */ 1801 if (!vlan.valid) 1802 return -EOPNOTSUPP; 1803 1804 fid = vlan.fid; 1805 } 1806 1807 entry.state = 0; 1808 ether_addr_copy(entry.mac, addr); 1809 eth_addr_dec(entry.mac); 1810 1811 err = mv88e6xxx_g1_atu_getnext(chip, fid, &entry); 1812 if (err) 1813 return err; 1814 1815 /* Initialize a fresh ATU entry if it isn't found */ 1816 if (!entry.state || !ether_addr_equal(entry.mac, addr)) { 1817 memset(&entry, 0, sizeof(entry)); 1818 ether_addr_copy(entry.mac, addr); 1819 } 1820 1821 /* Purge the ATU entry only if no port is using it anymore */ 1822 if (!state) { 1823 entry.portvec &= ~BIT(port); 1824 if (!entry.portvec) 1825 entry.state = 0; 1826 } else { 1827 if (state == MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC) 1828 entry.portvec = BIT(port); 1829 else 1830 entry.portvec |= BIT(port); 1831 1832 entry.state = state; 1833 } 1834 1835 return mv88e6xxx_g1_atu_loadpurge(chip, fid, &entry); 1836 } 1837 1838 static int mv88e6xxx_policy_apply(struct mv88e6xxx_chip *chip, int port, 1839 const struct mv88e6xxx_policy *policy) 1840 { 1841 enum mv88e6xxx_policy_mapping mapping = policy->mapping; 1842 enum mv88e6xxx_policy_action action = policy->action; 1843 const u8 *addr = policy->addr; 1844 u16 vid = policy->vid; 1845 u8 state; 1846 int err; 1847 int id; 1848 1849 if (!chip->info->ops->port_set_policy) 1850 return -EOPNOTSUPP; 1851 1852 switch (mapping) { 1853 case MV88E6XXX_POLICY_MAPPING_DA: 1854 case MV88E6XXX_POLICY_MAPPING_SA: 1855 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1856 state = 0; /* Dissociate the port and address */ 1857 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1858 is_multicast_ether_addr(addr)) 1859 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC_POLICY; 1860 else if (action == MV88E6XXX_POLICY_ACTION_DISCARD && 1861 is_unicast_ether_addr(addr)) 1862 state = MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC_POLICY; 1863 else 1864 return -EOPNOTSUPP; 1865 1866 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 1867 state); 1868 if (err) 1869 return err; 1870 break; 1871 default: 1872 return -EOPNOTSUPP; 1873 } 1874 1875 /* Skip the port's policy clearing if the mapping is still in use */ 1876 if (action == MV88E6XXX_POLICY_ACTION_NORMAL) 1877 idr_for_each_entry(&chip->policies, policy, id) 1878 if (policy->port == port && 1879 policy->mapping == mapping && 1880 policy->action != action) 1881 return 0; 1882 1883 return chip->info->ops->port_set_policy(chip, port, mapping, action); 1884 } 1885 1886 static int mv88e6xxx_policy_insert(struct mv88e6xxx_chip *chip, int port, 1887 struct ethtool_rx_flow_spec *fs) 1888 { 1889 struct ethhdr *mac_entry = &fs->h_u.ether_spec; 1890 struct ethhdr *mac_mask = &fs->m_u.ether_spec; 1891 enum mv88e6xxx_policy_mapping mapping; 1892 enum mv88e6xxx_policy_action action; 1893 struct mv88e6xxx_policy *policy; 1894 u16 vid = 0; 1895 u8 *addr; 1896 int err; 1897 int id; 1898 1899 if (fs->location != RX_CLS_LOC_ANY) 1900 return -EINVAL; 1901 1902 if (fs->ring_cookie == RX_CLS_FLOW_DISC) 1903 action = MV88E6XXX_POLICY_ACTION_DISCARD; 1904 else 1905 return -EOPNOTSUPP; 1906 1907 switch (fs->flow_type & ~FLOW_EXT) { 1908 case ETHER_FLOW: 1909 if (!is_zero_ether_addr(mac_mask->h_dest) && 1910 is_zero_ether_addr(mac_mask->h_source)) { 1911 mapping = MV88E6XXX_POLICY_MAPPING_DA; 1912 addr = mac_entry->h_dest; 1913 } else if (is_zero_ether_addr(mac_mask->h_dest) && 1914 !is_zero_ether_addr(mac_mask->h_source)) { 1915 mapping = MV88E6XXX_POLICY_MAPPING_SA; 1916 addr = mac_entry->h_source; 1917 } else { 1918 /* Cannot support DA and SA mapping in the same rule */ 1919 return -EOPNOTSUPP; 1920 } 1921 break; 1922 default: 1923 return -EOPNOTSUPP; 1924 } 1925 1926 if ((fs->flow_type & FLOW_EXT) && fs->m_ext.vlan_tci) { 1927 if (fs->m_ext.vlan_tci != htons(0xffff)) 1928 return -EOPNOTSUPP; 1929 vid = be16_to_cpu(fs->h_ext.vlan_tci) & VLAN_VID_MASK; 1930 } 1931 1932 idr_for_each_entry(&chip->policies, policy, id) { 1933 if (policy->port == port && policy->mapping == mapping && 1934 policy->action == action && policy->vid == vid && 1935 ether_addr_equal(policy->addr, addr)) 1936 return -EEXIST; 1937 } 1938 1939 policy = devm_kzalloc(chip->dev, sizeof(*policy), GFP_KERNEL); 1940 if (!policy) 1941 return -ENOMEM; 1942 1943 fs->location = 0; 1944 err = idr_alloc_u32(&chip->policies, policy, &fs->location, 0xffffffff, 1945 GFP_KERNEL); 1946 if (err) { 1947 devm_kfree(chip->dev, policy); 1948 return err; 1949 } 1950 1951 memcpy(&policy->fs, fs, sizeof(*fs)); 1952 ether_addr_copy(policy->addr, addr); 1953 policy->mapping = mapping; 1954 policy->action = action; 1955 policy->port = port; 1956 policy->vid = vid; 1957 1958 err = mv88e6xxx_policy_apply(chip, port, policy); 1959 if (err) { 1960 idr_remove(&chip->policies, fs->location); 1961 devm_kfree(chip->dev, policy); 1962 return err; 1963 } 1964 1965 return 0; 1966 } 1967 1968 static int mv88e6xxx_get_rxnfc(struct dsa_switch *ds, int port, 1969 struct ethtool_rxnfc *rxnfc, u32 *rule_locs) 1970 { 1971 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 1972 struct mv88e6xxx_chip *chip = ds->priv; 1973 struct mv88e6xxx_policy *policy; 1974 int err; 1975 int id; 1976 1977 mv88e6xxx_reg_lock(chip); 1978 1979 switch (rxnfc->cmd) { 1980 case ETHTOOL_GRXCLSRLCNT: 1981 rxnfc->data = 0; 1982 rxnfc->data |= RX_CLS_LOC_SPECIAL; 1983 rxnfc->rule_cnt = 0; 1984 idr_for_each_entry(&chip->policies, policy, id) 1985 if (policy->port == port) 1986 rxnfc->rule_cnt++; 1987 err = 0; 1988 break; 1989 case ETHTOOL_GRXCLSRULE: 1990 err = -ENOENT; 1991 policy = idr_find(&chip->policies, fs->location); 1992 if (policy) { 1993 memcpy(fs, &policy->fs, sizeof(*fs)); 1994 err = 0; 1995 } 1996 break; 1997 case ETHTOOL_GRXCLSRLALL: 1998 rxnfc->data = 0; 1999 rxnfc->rule_cnt = 0; 2000 idr_for_each_entry(&chip->policies, policy, id) 2001 if (policy->port == port) 2002 rule_locs[rxnfc->rule_cnt++] = id; 2003 err = 0; 2004 break; 2005 default: 2006 err = -EOPNOTSUPP; 2007 break; 2008 } 2009 2010 mv88e6xxx_reg_unlock(chip); 2011 2012 return err; 2013 } 2014 2015 static int mv88e6xxx_set_rxnfc(struct dsa_switch *ds, int port, 2016 struct ethtool_rxnfc *rxnfc) 2017 { 2018 struct ethtool_rx_flow_spec *fs = &rxnfc->fs; 2019 struct mv88e6xxx_chip *chip = ds->priv; 2020 struct mv88e6xxx_policy *policy; 2021 int err; 2022 2023 mv88e6xxx_reg_lock(chip); 2024 2025 switch (rxnfc->cmd) { 2026 case ETHTOOL_SRXCLSRLINS: 2027 err = mv88e6xxx_policy_insert(chip, port, fs); 2028 break; 2029 case ETHTOOL_SRXCLSRLDEL: 2030 err = -ENOENT; 2031 policy = idr_remove(&chip->policies, fs->location); 2032 if (policy) { 2033 policy->action = MV88E6XXX_POLICY_ACTION_NORMAL; 2034 err = mv88e6xxx_policy_apply(chip, port, policy); 2035 devm_kfree(chip->dev, policy); 2036 } 2037 break; 2038 default: 2039 err = -EOPNOTSUPP; 2040 break; 2041 } 2042 2043 mv88e6xxx_reg_unlock(chip); 2044 2045 return err; 2046 } 2047 2048 static int mv88e6xxx_port_add_broadcast(struct mv88e6xxx_chip *chip, int port, 2049 u16 vid) 2050 { 2051 u8 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2052 u8 broadcast[ETH_ALEN]; 2053 2054 eth_broadcast_addr(broadcast); 2055 2056 return mv88e6xxx_port_db_load_purge(chip, port, broadcast, vid, state); 2057 } 2058 2059 static int mv88e6xxx_broadcast_setup(struct mv88e6xxx_chip *chip, u16 vid) 2060 { 2061 int port; 2062 int err; 2063 2064 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 2065 struct dsa_port *dp = dsa_to_port(chip->ds, port); 2066 struct net_device *brport; 2067 2068 if (dsa_is_unused_port(chip->ds, port)) 2069 continue; 2070 2071 brport = dsa_port_to_bridge_port(dp); 2072 if (brport && !br_port_flag_is_set(brport, BR_BCAST_FLOOD)) 2073 /* Skip bridged user ports where broadcast 2074 * flooding is disabled. 2075 */ 2076 continue; 2077 2078 err = mv88e6xxx_port_add_broadcast(chip, port, vid); 2079 if (err) 2080 return err; 2081 } 2082 2083 return 0; 2084 } 2085 2086 struct mv88e6xxx_port_broadcast_sync_ctx { 2087 int port; 2088 bool flood; 2089 }; 2090 2091 static int 2092 mv88e6xxx_port_broadcast_sync_vlan(struct mv88e6xxx_chip *chip, 2093 const struct mv88e6xxx_vtu_entry *vlan, 2094 void *_ctx) 2095 { 2096 struct mv88e6xxx_port_broadcast_sync_ctx *ctx = _ctx; 2097 u8 broadcast[ETH_ALEN]; 2098 u8 state; 2099 2100 if (ctx->flood) 2101 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC; 2102 else 2103 state = MV88E6XXX_G1_ATU_DATA_STATE_MC_UNUSED; 2104 2105 eth_broadcast_addr(broadcast); 2106 2107 return mv88e6xxx_port_db_load_purge(chip, ctx->port, broadcast, 2108 vlan->vid, state); 2109 } 2110 2111 static int mv88e6xxx_port_broadcast_sync(struct mv88e6xxx_chip *chip, int port, 2112 bool flood) 2113 { 2114 struct mv88e6xxx_port_broadcast_sync_ctx ctx = { 2115 .port = port, 2116 .flood = flood, 2117 }; 2118 struct mv88e6xxx_vtu_entry vid0 = { 2119 .vid = 0, 2120 }; 2121 int err; 2122 2123 /* Update the port's private database... */ 2124 err = mv88e6xxx_port_broadcast_sync_vlan(chip, &vid0, &ctx); 2125 if (err) 2126 return err; 2127 2128 /* ...and the database for all VLANs. */ 2129 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_broadcast_sync_vlan, 2130 &ctx); 2131 } 2132 2133 static int mv88e6xxx_port_vlan_join(struct mv88e6xxx_chip *chip, int port, 2134 u16 vid, u8 member, bool warn) 2135 { 2136 const u8 non_member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2137 struct mv88e6xxx_vtu_entry vlan; 2138 int i, err; 2139 2140 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2141 if (err) 2142 return err; 2143 2144 if (!vlan.valid) { 2145 memset(&vlan, 0, sizeof(vlan)); 2146 2147 err = mv88e6xxx_atu_new(chip, &vlan.fid); 2148 if (err) 2149 return err; 2150 2151 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2152 if (i == port) 2153 vlan.member[i] = member; 2154 else 2155 vlan.member[i] = non_member; 2156 2157 vlan.vid = vid; 2158 vlan.valid = true; 2159 2160 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2161 if (err) 2162 return err; 2163 2164 err = mv88e6xxx_broadcast_setup(chip, vlan.vid); 2165 if (err) 2166 return err; 2167 } else if (vlan.member[port] != member) { 2168 vlan.member[port] = member; 2169 2170 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2171 if (err) 2172 return err; 2173 } else if (warn) { 2174 dev_info(chip->dev, "p%d: already a member of VLAN %d\n", 2175 port, vid); 2176 } 2177 2178 return 0; 2179 } 2180 2181 static int mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 2182 const struct switchdev_obj_port_vlan *vlan, 2183 struct netlink_ext_ack *extack) 2184 { 2185 struct mv88e6xxx_chip *chip = ds->priv; 2186 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 2187 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 2188 struct mv88e6xxx_port *p = &chip->ports[port]; 2189 bool warn; 2190 u8 member; 2191 int err; 2192 2193 if (!vlan->vid) 2194 return 0; 2195 2196 err = mv88e6xxx_port_vlan_prepare(ds, port, vlan); 2197 if (err) 2198 return err; 2199 2200 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 2201 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNMODIFIED; 2202 else if (untagged) 2203 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED; 2204 else 2205 member = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_TAGGED; 2206 2207 /* net/dsa/slave.c will call dsa_port_vlan_add() for the affected port 2208 * and then the CPU port. Do not warn for duplicates for the CPU port. 2209 */ 2210 warn = !dsa_is_cpu_port(ds, port) && !dsa_is_dsa_port(ds, port); 2211 2212 mv88e6xxx_reg_lock(chip); 2213 2214 err = mv88e6xxx_port_vlan_join(chip, port, vlan->vid, member, warn); 2215 if (err) { 2216 dev_err(ds->dev, "p%d: failed to add VLAN %d%c\n", port, 2217 vlan->vid, untagged ? 'u' : 't'); 2218 goto out; 2219 } 2220 2221 if (pvid) { 2222 p->bridge_pvid.vid = vlan->vid; 2223 p->bridge_pvid.valid = true; 2224 2225 err = mv88e6xxx_port_commit_pvid(chip, port); 2226 if (err) 2227 goto out; 2228 } else if (vlan->vid && p->bridge_pvid.vid == vlan->vid) { 2229 /* The old pvid was reinstalled as a non-pvid VLAN */ 2230 p->bridge_pvid.valid = false; 2231 2232 err = mv88e6xxx_port_commit_pvid(chip, port); 2233 if (err) 2234 goto out; 2235 } 2236 2237 out: 2238 mv88e6xxx_reg_unlock(chip); 2239 2240 return err; 2241 } 2242 2243 static int mv88e6xxx_port_vlan_leave(struct mv88e6xxx_chip *chip, 2244 int port, u16 vid) 2245 { 2246 struct mv88e6xxx_vtu_entry vlan; 2247 int i, err; 2248 2249 if (!vid) 2250 return 0; 2251 2252 err = mv88e6xxx_vtu_get(chip, vid, &vlan); 2253 if (err) 2254 return err; 2255 2256 /* If the VLAN doesn't exist in hardware or the port isn't a member, 2257 * tell switchdev that this VLAN is likely handled in software. 2258 */ 2259 if (!vlan.valid || 2260 vlan.member[port] == MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) 2261 return -EOPNOTSUPP; 2262 2263 vlan.member[port] = MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER; 2264 2265 /* keep the VLAN unless all ports are excluded */ 2266 vlan.valid = false; 2267 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2268 if (vlan.member[i] != 2269 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 2270 vlan.valid = true; 2271 break; 2272 } 2273 } 2274 2275 err = mv88e6xxx_vtu_loadpurge(chip, &vlan); 2276 if (err) 2277 return err; 2278 2279 return mv88e6xxx_g1_atu_remove(chip, vlan.fid, port, false); 2280 } 2281 2282 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 2283 const struct switchdev_obj_port_vlan *vlan) 2284 { 2285 struct mv88e6xxx_chip *chip = ds->priv; 2286 struct mv88e6xxx_port *p = &chip->ports[port]; 2287 int err = 0; 2288 u16 pvid; 2289 2290 if (!mv88e6xxx_max_vid(chip)) 2291 return -EOPNOTSUPP; 2292 2293 mv88e6xxx_reg_lock(chip); 2294 2295 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 2296 if (err) 2297 goto unlock; 2298 2299 err = mv88e6xxx_port_vlan_leave(chip, port, vlan->vid); 2300 if (err) 2301 goto unlock; 2302 2303 if (vlan->vid == pvid) { 2304 p->bridge_pvid.valid = false; 2305 2306 err = mv88e6xxx_port_commit_pvid(chip, port); 2307 if (err) 2308 goto unlock; 2309 } 2310 2311 unlock: 2312 mv88e6xxx_reg_unlock(chip); 2313 2314 return err; 2315 } 2316 2317 static int mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2318 const unsigned char *addr, u16 vid) 2319 { 2320 struct mv88e6xxx_chip *chip = ds->priv; 2321 int err; 2322 2323 mv88e6xxx_reg_lock(chip); 2324 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 2325 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2326 mv88e6xxx_reg_unlock(chip); 2327 2328 return err; 2329 } 2330 2331 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2332 const unsigned char *addr, u16 vid) 2333 { 2334 struct mv88e6xxx_chip *chip = ds->priv; 2335 int err; 2336 2337 mv88e6xxx_reg_lock(chip); 2338 err = mv88e6xxx_port_db_load_purge(chip, port, addr, vid, 0); 2339 mv88e6xxx_reg_unlock(chip); 2340 2341 return err; 2342 } 2343 2344 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2345 u16 fid, u16 vid, int port, 2346 dsa_fdb_dump_cb_t *cb, void *data) 2347 { 2348 struct mv88e6xxx_atu_entry addr; 2349 bool is_static; 2350 int err; 2351 2352 addr.state = 0; 2353 eth_broadcast_addr(addr.mac); 2354 2355 do { 2356 err = mv88e6xxx_g1_atu_getnext(chip, fid, &addr); 2357 if (err) 2358 return err; 2359 2360 if (!addr.state) 2361 break; 2362 2363 if (addr.trunk || (addr.portvec & BIT(port)) == 0) 2364 continue; 2365 2366 if (!is_unicast_ether_addr(addr.mac)) 2367 continue; 2368 2369 is_static = (addr.state == 2370 MV88E6XXX_G1_ATU_DATA_STATE_UC_STATIC); 2371 err = cb(addr.mac, vid, is_static, data); 2372 if (err) 2373 return err; 2374 } while (!is_broadcast_ether_addr(addr.mac)); 2375 2376 return err; 2377 } 2378 2379 struct mv88e6xxx_port_db_dump_vlan_ctx { 2380 int port; 2381 dsa_fdb_dump_cb_t *cb; 2382 void *data; 2383 }; 2384 2385 static int mv88e6xxx_port_db_dump_vlan(struct mv88e6xxx_chip *chip, 2386 const struct mv88e6xxx_vtu_entry *entry, 2387 void *_data) 2388 { 2389 struct mv88e6xxx_port_db_dump_vlan_ctx *ctx = _data; 2390 2391 return mv88e6xxx_port_db_dump_fid(chip, entry->fid, entry->vid, 2392 ctx->port, ctx->cb, ctx->data); 2393 } 2394 2395 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2396 dsa_fdb_dump_cb_t *cb, void *data) 2397 { 2398 struct mv88e6xxx_port_db_dump_vlan_ctx ctx = { 2399 .port = port, 2400 .cb = cb, 2401 .data = data, 2402 }; 2403 u16 fid; 2404 int err; 2405 2406 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2407 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2408 if (err) 2409 return err; 2410 2411 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, cb, data); 2412 if (err) 2413 return err; 2414 2415 return mv88e6xxx_vtu_walk(chip, mv88e6xxx_port_db_dump_vlan, &ctx); 2416 } 2417 2418 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2419 dsa_fdb_dump_cb_t *cb, void *data) 2420 { 2421 struct mv88e6xxx_chip *chip = ds->priv; 2422 int err; 2423 2424 mv88e6xxx_reg_lock(chip); 2425 err = mv88e6xxx_port_db_dump(chip, port, cb, data); 2426 mv88e6xxx_reg_unlock(chip); 2427 2428 return err; 2429 } 2430 2431 static int mv88e6xxx_bridge_map(struct mv88e6xxx_chip *chip, 2432 struct net_device *br) 2433 { 2434 struct dsa_switch *ds = chip->ds; 2435 struct dsa_switch_tree *dst = ds->dst; 2436 struct dsa_port *dp; 2437 int err; 2438 2439 list_for_each_entry(dp, &dst->ports, list) { 2440 if (dp->bridge_dev == br) { 2441 if (dp->ds == ds) { 2442 /* This is a local bridge group member, 2443 * remap its Port VLAN Map. 2444 */ 2445 err = mv88e6xxx_port_vlan_map(chip, dp->index); 2446 if (err) 2447 return err; 2448 } else { 2449 /* This is an external bridge group member, 2450 * remap its cross-chip Port VLAN Table entry. 2451 */ 2452 err = mv88e6xxx_pvt_map(chip, dp->ds->index, 2453 dp->index); 2454 if (err) 2455 return err; 2456 } 2457 } 2458 } 2459 2460 return 0; 2461 } 2462 2463 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2464 struct net_device *br) 2465 { 2466 struct mv88e6xxx_chip *chip = ds->priv; 2467 int err; 2468 2469 mv88e6xxx_reg_lock(chip); 2470 2471 err = mv88e6xxx_bridge_map(chip, br); 2472 if (err) 2473 goto unlock; 2474 2475 err = mv88e6xxx_port_commit_pvid(chip, port); 2476 if (err) 2477 goto unlock; 2478 2479 unlock: 2480 mv88e6xxx_reg_unlock(chip); 2481 2482 return err; 2483 } 2484 2485 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2486 struct net_device *br) 2487 { 2488 struct mv88e6xxx_chip *chip = ds->priv; 2489 int err; 2490 2491 mv88e6xxx_reg_lock(chip); 2492 2493 if (mv88e6xxx_bridge_map(chip, br) || 2494 mv88e6xxx_port_vlan_map(chip, port)) 2495 dev_err(ds->dev, "failed to remap in-chip Port VLAN\n"); 2496 2497 err = mv88e6xxx_port_commit_pvid(chip, port); 2498 if (err) 2499 dev_err(ds->dev, 2500 "port %d failed to restore standalone pvid: %pe\n", 2501 port, ERR_PTR(err)); 2502 2503 mv88e6xxx_reg_unlock(chip); 2504 } 2505 2506 static int mv88e6xxx_crosschip_bridge_join(struct dsa_switch *ds, 2507 int tree_index, int sw_index, 2508 int port, struct net_device *br) 2509 { 2510 struct mv88e6xxx_chip *chip = ds->priv; 2511 int err; 2512 2513 if (tree_index != ds->dst->index) 2514 return 0; 2515 2516 mv88e6xxx_reg_lock(chip); 2517 err = mv88e6xxx_pvt_map(chip, sw_index, port); 2518 mv88e6xxx_reg_unlock(chip); 2519 2520 return err; 2521 } 2522 2523 static void mv88e6xxx_crosschip_bridge_leave(struct dsa_switch *ds, 2524 int tree_index, int sw_index, 2525 int port, struct net_device *br) 2526 { 2527 struct mv88e6xxx_chip *chip = ds->priv; 2528 2529 if (tree_index != ds->dst->index) 2530 return; 2531 2532 mv88e6xxx_reg_lock(chip); 2533 if (mv88e6xxx_pvt_map(chip, sw_index, port)) 2534 dev_err(ds->dev, "failed to remap cross-chip Port VLAN\n"); 2535 mv88e6xxx_reg_unlock(chip); 2536 } 2537 2538 /* Treat the software bridge as a virtual single-port switch behind the 2539 * CPU and map in the PVT. First dst->last_switch elements are taken by 2540 * physical switches, so start from beyond that range. 2541 */ 2542 static int mv88e6xxx_map_virtual_bridge_to_pvt(struct dsa_switch *ds, 2543 int bridge_num) 2544 { 2545 u8 dev = bridge_num + ds->dst->last_switch + 1; 2546 struct mv88e6xxx_chip *chip = ds->priv; 2547 int err; 2548 2549 mv88e6xxx_reg_lock(chip); 2550 err = mv88e6xxx_pvt_map(chip, dev, 0); 2551 mv88e6xxx_reg_unlock(chip); 2552 2553 return err; 2554 } 2555 2556 static int mv88e6xxx_bridge_tx_fwd_offload(struct dsa_switch *ds, int port, 2557 struct net_device *br, 2558 int bridge_num) 2559 { 2560 return mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2561 } 2562 2563 static void mv88e6xxx_bridge_tx_fwd_unoffload(struct dsa_switch *ds, int port, 2564 struct net_device *br, 2565 int bridge_num) 2566 { 2567 int err; 2568 2569 err = mv88e6xxx_map_virtual_bridge_to_pvt(ds, bridge_num); 2570 if (err) { 2571 dev_err(ds->dev, "failed to remap cross-chip Port VLAN: %pe\n", 2572 ERR_PTR(err)); 2573 } 2574 } 2575 2576 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2577 { 2578 if (chip->info->ops->reset) 2579 return chip->info->ops->reset(chip); 2580 2581 return 0; 2582 } 2583 2584 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2585 { 2586 struct gpio_desc *gpiod = chip->reset; 2587 2588 /* If there is a GPIO connected to the reset pin, toggle it */ 2589 if (gpiod) { 2590 gpiod_set_value_cansleep(gpiod, 1); 2591 usleep_range(10000, 20000); 2592 gpiod_set_value_cansleep(gpiod, 0); 2593 usleep_range(10000, 20000); 2594 2595 mv88e6xxx_g1_wait_eeprom_done(chip); 2596 } 2597 } 2598 2599 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2600 { 2601 int i, err; 2602 2603 /* Set all ports to the Disabled state */ 2604 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2605 err = mv88e6xxx_port_set_state(chip, i, BR_STATE_DISABLED); 2606 if (err) 2607 return err; 2608 } 2609 2610 /* Wait for transmit queues to drain, 2611 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2612 */ 2613 usleep_range(2000, 4000); 2614 2615 return 0; 2616 } 2617 2618 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2619 { 2620 int err; 2621 2622 err = mv88e6xxx_disable_ports(chip); 2623 if (err) 2624 return err; 2625 2626 mv88e6xxx_hardware_reset(chip); 2627 2628 return mv88e6xxx_software_reset(chip); 2629 } 2630 2631 static int mv88e6xxx_set_port_mode(struct mv88e6xxx_chip *chip, int port, 2632 enum mv88e6xxx_frame_mode frame, 2633 enum mv88e6xxx_egress_mode egress, u16 etype) 2634 { 2635 int err; 2636 2637 if (!chip->info->ops->port_set_frame_mode) 2638 return -EOPNOTSUPP; 2639 2640 err = mv88e6xxx_port_set_egress_mode(chip, port, egress); 2641 if (err) 2642 return err; 2643 2644 err = chip->info->ops->port_set_frame_mode(chip, port, frame); 2645 if (err) 2646 return err; 2647 2648 if (chip->info->ops->port_set_ether_type) 2649 return chip->info->ops->port_set_ether_type(chip, port, etype); 2650 2651 return 0; 2652 } 2653 2654 static int mv88e6xxx_set_port_mode_normal(struct mv88e6xxx_chip *chip, int port) 2655 { 2656 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_NORMAL, 2657 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2658 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2659 } 2660 2661 static int mv88e6xxx_set_port_mode_dsa(struct mv88e6xxx_chip *chip, int port) 2662 { 2663 return mv88e6xxx_set_port_mode(chip, port, MV88E6XXX_FRAME_MODE_DSA, 2664 MV88E6XXX_EGRESS_MODE_UNMODIFIED, 2665 MV88E6XXX_PORT_ETH_TYPE_DEFAULT); 2666 } 2667 2668 static int mv88e6xxx_set_port_mode_edsa(struct mv88e6xxx_chip *chip, int port) 2669 { 2670 return mv88e6xxx_set_port_mode(chip, port, 2671 MV88E6XXX_FRAME_MODE_ETHERTYPE, 2672 MV88E6XXX_EGRESS_MODE_ETHERTYPE, 2673 ETH_P_EDSA); 2674 } 2675 2676 static int mv88e6xxx_setup_port_mode(struct mv88e6xxx_chip *chip, int port) 2677 { 2678 if (dsa_is_dsa_port(chip->ds, port)) 2679 return mv88e6xxx_set_port_mode_dsa(chip, port); 2680 2681 if (dsa_is_user_port(chip->ds, port)) 2682 return mv88e6xxx_set_port_mode_normal(chip, port); 2683 2684 /* Setup CPU port mode depending on its supported tag format */ 2685 if (chip->tag_protocol == DSA_TAG_PROTO_DSA) 2686 return mv88e6xxx_set_port_mode_dsa(chip, port); 2687 2688 if (chip->tag_protocol == DSA_TAG_PROTO_EDSA) 2689 return mv88e6xxx_set_port_mode_edsa(chip, port); 2690 2691 return -EINVAL; 2692 } 2693 2694 static int mv88e6xxx_setup_message_port(struct mv88e6xxx_chip *chip, int port) 2695 { 2696 bool message = dsa_is_dsa_port(chip->ds, port); 2697 2698 return mv88e6xxx_port_set_message_port(chip, port, message); 2699 } 2700 2701 static int mv88e6xxx_setup_egress_floods(struct mv88e6xxx_chip *chip, int port) 2702 { 2703 int err; 2704 2705 if (chip->info->ops->port_set_ucast_flood) { 2706 err = chip->info->ops->port_set_ucast_flood(chip, port, true); 2707 if (err) 2708 return err; 2709 } 2710 if (chip->info->ops->port_set_mcast_flood) { 2711 err = chip->info->ops->port_set_mcast_flood(chip, port, true); 2712 if (err) 2713 return err; 2714 } 2715 2716 return 0; 2717 } 2718 2719 static irqreturn_t mv88e6xxx_serdes_irq_thread_fn(int irq, void *dev_id) 2720 { 2721 struct mv88e6xxx_port *mvp = dev_id; 2722 struct mv88e6xxx_chip *chip = mvp->chip; 2723 irqreturn_t ret = IRQ_NONE; 2724 int port = mvp->port; 2725 int lane; 2726 2727 mv88e6xxx_reg_lock(chip); 2728 lane = mv88e6xxx_serdes_get_lane(chip, port); 2729 if (lane >= 0) 2730 ret = mv88e6xxx_serdes_irq_status(chip, port, lane); 2731 mv88e6xxx_reg_unlock(chip); 2732 2733 return ret; 2734 } 2735 2736 static int mv88e6xxx_serdes_irq_request(struct mv88e6xxx_chip *chip, int port, 2737 int lane) 2738 { 2739 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2740 unsigned int irq; 2741 int err; 2742 2743 /* Nothing to request if this SERDES port has no IRQ */ 2744 irq = mv88e6xxx_serdes_irq_mapping(chip, port); 2745 if (!irq) 2746 return 0; 2747 2748 snprintf(dev_id->serdes_irq_name, sizeof(dev_id->serdes_irq_name), 2749 "mv88e6xxx-%s-serdes-%d", dev_name(chip->dev), port); 2750 2751 /* Requesting the IRQ will trigger IRQ callbacks, so release the lock */ 2752 mv88e6xxx_reg_unlock(chip); 2753 err = request_threaded_irq(irq, NULL, mv88e6xxx_serdes_irq_thread_fn, 2754 IRQF_ONESHOT, dev_id->serdes_irq_name, 2755 dev_id); 2756 mv88e6xxx_reg_lock(chip); 2757 if (err) 2758 return err; 2759 2760 dev_id->serdes_irq = irq; 2761 2762 return mv88e6xxx_serdes_irq_enable(chip, port, lane); 2763 } 2764 2765 static int mv88e6xxx_serdes_irq_free(struct mv88e6xxx_chip *chip, int port, 2766 int lane) 2767 { 2768 struct mv88e6xxx_port *dev_id = &chip->ports[port]; 2769 unsigned int irq = dev_id->serdes_irq; 2770 int err; 2771 2772 /* Nothing to free if no IRQ has been requested */ 2773 if (!irq) 2774 return 0; 2775 2776 err = mv88e6xxx_serdes_irq_disable(chip, port, lane); 2777 2778 /* Freeing the IRQ will trigger IRQ callbacks, so release the lock */ 2779 mv88e6xxx_reg_unlock(chip); 2780 free_irq(irq, dev_id); 2781 mv88e6xxx_reg_lock(chip); 2782 2783 dev_id->serdes_irq = 0; 2784 2785 return err; 2786 } 2787 2788 static int mv88e6xxx_serdes_power(struct mv88e6xxx_chip *chip, int port, 2789 bool on) 2790 { 2791 int lane; 2792 int err; 2793 2794 lane = mv88e6xxx_serdes_get_lane(chip, port); 2795 if (lane < 0) 2796 return 0; 2797 2798 if (on) { 2799 err = mv88e6xxx_serdes_power_up(chip, port, lane); 2800 if (err) 2801 return err; 2802 2803 err = mv88e6xxx_serdes_irq_request(chip, port, lane); 2804 } else { 2805 err = mv88e6xxx_serdes_irq_free(chip, port, lane); 2806 if (err) 2807 return err; 2808 2809 err = mv88e6xxx_serdes_power_down(chip, port, lane); 2810 } 2811 2812 return err; 2813 } 2814 2815 static int mv88e6xxx_set_egress_port(struct mv88e6xxx_chip *chip, 2816 enum mv88e6xxx_egress_direction direction, 2817 int port) 2818 { 2819 int err; 2820 2821 if (!chip->info->ops->set_egress_port) 2822 return -EOPNOTSUPP; 2823 2824 err = chip->info->ops->set_egress_port(chip, direction, port); 2825 if (err) 2826 return err; 2827 2828 if (direction == MV88E6XXX_EGRESS_DIR_INGRESS) 2829 chip->ingress_dest_port = port; 2830 else 2831 chip->egress_dest_port = port; 2832 2833 return 0; 2834 } 2835 2836 static int mv88e6xxx_setup_upstream_port(struct mv88e6xxx_chip *chip, int port) 2837 { 2838 struct dsa_switch *ds = chip->ds; 2839 int upstream_port; 2840 int err; 2841 2842 upstream_port = dsa_upstream_port(ds, port); 2843 if (chip->info->ops->port_set_upstream_port) { 2844 err = chip->info->ops->port_set_upstream_port(chip, port, 2845 upstream_port); 2846 if (err) 2847 return err; 2848 } 2849 2850 if (port == upstream_port) { 2851 if (chip->info->ops->set_cpu_port) { 2852 err = chip->info->ops->set_cpu_port(chip, 2853 upstream_port); 2854 if (err) 2855 return err; 2856 } 2857 2858 err = mv88e6xxx_set_egress_port(chip, 2859 MV88E6XXX_EGRESS_DIR_INGRESS, 2860 upstream_port); 2861 if (err && err != -EOPNOTSUPP) 2862 return err; 2863 2864 err = mv88e6xxx_set_egress_port(chip, 2865 MV88E6XXX_EGRESS_DIR_EGRESS, 2866 upstream_port); 2867 if (err && err != -EOPNOTSUPP) 2868 return err; 2869 } 2870 2871 return 0; 2872 } 2873 2874 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2875 { 2876 struct dsa_switch *ds = chip->ds; 2877 int err; 2878 u16 reg; 2879 2880 chip->ports[port].chip = chip; 2881 chip->ports[port].port = port; 2882 2883 /* MAC Forcing register: don't force link, speed, duplex or flow control 2884 * state to any particular values on physical ports, but force the CPU 2885 * port and all DSA ports to their maximum bandwidth and full duplex. 2886 */ 2887 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2888 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2889 SPEED_MAX, DUPLEX_FULL, 2890 PAUSE_OFF, 2891 PHY_INTERFACE_MODE_NA); 2892 else 2893 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2894 SPEED_UNFORCED, DUPLEX_UNFORCED, 2895 PAUSE_ON, 2896 PHY_INTERFACE_MODE_NA); 2897 if (err) 2898 return err; 2899 2900 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2901 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2902 * tunneling, determine priority by looking at 802.1p and IP 2903 * priority fields (IP prio has precedence), and set STP state 2904 * to Forwarding. 2905 * 2906 * If this is the CPU link, use DSA or EDSA tagging depending 2907 * on which tagging mode was configured. 2908 * 2909 * If this is a link to another switch, use DSA tagging mode. 2910 * 2911 * If this is the upstream port for this switch, enable 2912 * forwarding of unknown unicasts and multicasts. 2913 */ 2914 reg = MV88E6XXX_PORT_CTL0_IGMP_MLD_SNOOP | 2915 MV88E6185_PORT_CTL0_USE_TAG | MV88E6185_PORT_CTL0_USE_IP | 2916 MV88E6XXX_PORT_CTL0_STATE_FORWARDING; 2917 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_CTL0, reg); 2918 if (err) 2919 return err; 2920 2921 err = mv88e6xxx_setup_port_mode(chip, port); 2922 if (err) 2923 return err; 2924 2925 err = mv88e6xxx_setup_egress_floods(chip, port); 2926 if (err) 2927 return err; 2928 2929 /* Port Control 2: don't force a good FCS, set the MTU size to 2930 * 10222 bytes, disable 802.1q tags checking, don't discard tagged or 2931 * untagged frames on this port, do a destination address lookup on all 2932 * received packets as usual, disable ARP mirroring and don't send a 2933 * copy of all transmitted/received frames on this port to the CPU. 2934 */ 2935 err = mv88e6xxx_port_set_map_da(chip, port); 2936 if (err) 2937 return err; 2938 2939 err = mv88e6xxx_setup_upstream_port(chip, port); 2940 if (err) 2941 return err; 2942 2943 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2944 MV88E6XXX_PORT_CTL2_8021Q_MODE_DISABLED); 2945 if (err) 2946 return err; 2947 2948 /* Associate MV88E6XXX_VID_BRIDGED with MV88E6XXX_FID_BRIDGED in the 2949 * ATU by virtue of the fact that mv88e6xxx_atu_new() will pick it as 2950 * the first free FID after MV88E6XXX_FID_STANDALONE. This will be used 2951 * as the private PVID on ports under a VLAN-unaware bridge. 2952 * Shared (DSA and CPU) ports must also be members of it, to translate 2953 * the VID from the DSA tag into MV88E6XXX_FID_BRIDGED, instead of 2954 * relying on their port default FID. 2955 */ 2956 err = mv88e6xxx_port_vlan_join(chip, port, MV88E6XXX_VID_BRIDGED, 2957 MV88E6XXX_G1_VTU_DATA_MEMBER_TAG_UNTAGGED, 2958 false); 2959 if (err) 2960 return err; 2961 2962 if (chip->info->ops->port_set_jumbo_size) { 2963 err = chip->info->ops->port_set_jumbo_size(chip, port, 10218); 2964 if (err) 2965 return err; 2966 } 2967 2968 /* Port Association Vector: disable automatic address learning 2969 * on all user ports since they start out in standalone 2970 * mode. When joining a bridge, learning will be configured to 2971 * match the bridge port settings. Enable learning on all 2972 * DSA/CPU ports. NOTE: FROM_CPU frames always bypass the 2973 * learning process. 2974 * 2975 * Disable HoldAt1, IntOnAgeOut, LockedPort, IgnoreWrongData, 2976 * and RefreshLocked. I.e. setup standard automatic learning. 2977 */ 2978 if (dsa_is_user_port(ds, port)) 2979 reg = 0; 2980 else 2981 reg = 1 << port; 2982 2983 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_ASSOC_VECTOR, 2984 reg); 2985 if (err) 2986 return err; 2987 2988 /* Egress rate control 2: disable egress rate control. */ 2989 err = mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_EGRESS_RATE_CTL2, 2990 0x0000); 2991 if (err) 2992 return err; 2993 2994 if (chip->info->ops->port_pause_limit) { 2995 err = chip->info->ops->port_pause_limit(chip, port, 0, 0); 2996 if (err) 2997 return err; 2998 } 2999 3000 if (chip->info->ops->port_disable_learn_limit) { 3001 err = chip->info->ops->port_disable_learn_limit(chip, port); 3002 if (err) 3003 return err; 3004 } 3005 3006 if (chip->info->ops->port_disable_pri_override) { 3007 err = chip->info->ops->port_disable_pri_override(chip, port); 3008 if (err) 3009 return err; 3010 } 3011 3012 if (chip->info->ops->port_tag_remap) { 3013 err = chip->info->ops->port_tag_remap(chip, port); 3014 if (err) 3015 return err; 3016 } 3017 3018 if (chip->info->ops->port_egress_rate_limiting) { 3019 err = chip->info->ops->port_egress_rate_limiting(chip, port); 3020 if (err) 3021 return err; 3022 } 3023 3024 if (chip->info->ops->port_setup_message_port) { 3025 err = chip->info->ops->port_setup_message_port(chip, port); 3026 if (err) 3027 return err; 3028 } 3029 3030 /* Port based VLAN map: give each port the same default address 3031 * database, and allow bidirectional communication between the 3032 * CPU and DSA port(s), and the other ports. 3033 */ 3034 err = mv88e6xxx_port_set_fid(chip, port, MV88E6XXX_FID_STANDALONE); 3035 if (err) 3036 return err; 3037 3038 err = mv88e6xxx_port_vlan_map(chip, port); 3039 if (err) 3040 return err; 3041 3042 /* Default VLAN ID and priority: don't set a default VLAN 3043 * ID, and set the default packet priority to zero. 3044 */ 3045 return mv88e6xxx_port_write(chip, port, MV88E6XXX_PORT_DEFAULT_VLAN, 0); 3046 } 3047 3048 static int mv88e6xxx_get_max_mtu(struct dsa_switch *ds, int port) 3049 { 3050 struct mv88e6xxx_chip *chip = ds->priv; 3051 3052 if (chip->info->ops->port_set_jumbo_size) 3053 return 10240 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3054 else if (chip->info->ops->set_max_frame_size) 3055 return 1632 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3056 return 1522 - VLAN_ETH_HLEN - EDSA_HLEN - ETH_FCS_LEN; 3057 } 3058 3059 static int mv88e6xxx_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 3060 { 3061 struct mv88e6xxx_chip *chip = ds->priv; 3062 int ret = 0; 3063 3064 if (dsa_is_dsa_port(ds, port) || dsa_is_cpu_port(ds, port)) 3065 new_mtu += EDSA_HLEN; 3066 3067 mv88e6xxx_reg_lock(chip); 3068 if (chip->info->ops->port_set_jumbo_size) 3069 ret = chip->info->ops->port_set_jumbo_size(chip, port, new_mtu); 3070 else if (chip->info->ops->set_max_frame_size) 3071 ret = chip->info->ops->set_max_frame_size(chip, new_mtu); 3072 else 3073 if (new_mtu > 1522) 3074 ret = -EINVAL; 3075 mv88e6xxx_reg_unlock(chip); 3076 3077 return ret; 3078 } 3079 3080 static int mv88e6xxx_port_enable(struct dsa_switch *ds, int port, 3081 struct phy_device *phydev) 3082 { 3083 struct mv88e6xxx_chip *chip = ds->priv; 3084 int err; 3085 3086 mv88e6xxx_reg_lock(chip); 3087 err = mv88e6xxx_serdes_power(chip, port, true); 3088 mv88e6xxx_reg_unlock(chip); 3089 3090 return err; 3091 } 3092 3093 static void mv88e6xxx_port_disable(struct dsa_switch *ds, int port) 3094 { 3095 struct mv88e6xxx_chip *chip = ds->priv; 3096 3097 mv88e6xxx_reg_lock(chip); 3098 if (mv88e6xxx_serdes_power(chip, port, false)) 3099 dev_err(chip->dev, "failed to power off SERDES\n"); 3100 mv88e6xxx_reg_unlock(chip); 3101 } 3102 3103 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 3104 unsigned int ageing_time) 3105 { 3106 struct mv88e6xxx_chip *chip = ds->priv; 3107 int err; 3108 3109 mv88e6xxx_reg_lock(chip); 3110 err = mv88e6xxx_g1_atu_set_age_time(chip, ageing_time); 3111 mv88e6xxx_reg_unlock(chip); 3112 3113 return err; 3114 } 3115 3116 static int mv88e6xxx_stats_setup(struct mv88e6xxx_chip *chip) 3117 { 3118 int err; 3119 3120 /* Initialize the statistics unit */ 3121 if (chip->info->ops->stats_set_histogram) { 3122 err = chip->info->ops->stats_set_histogram(chip); 3123 if (err) 3124 return err; 3125 } 3126 3127 return mv88e6xxx_g1_stats_clear(chip); 3128 } 3129 3130 /* Check if the errata has already been applied. */ 3131 static bool mv88e6390_setup_errata_applied(struct mv88e6xxx_chip *chip) 3132 { 3133 int port; 3134 int err; 3135 u16 val; 3136 3137 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3138 err = mv88e6xxx_port_hidden_read(chip, 0xf, port, 0, &val); 3139 if (err) { 3140 dev_err(chip->dev, 3141 "Error reading hidden register: %d\n", err); 3142 return false; 3143 } 3144 if (val != 0x01c0) 3145 return false; 3146 } 3147 3148 return true; 3149 } 3150 3151 /* The 6390 copper ports have an errata which require poking magic 3152 * values into undocumented hidden registers and then performing a 3153 * software reset. 3154 */ 3155 static int mv88e6390_setup_errata(struct mv88e6xxx_chip *chip) 3156 { 3157 int port; 3158 int err; 3159 3160 if (mv88e6390_setup_errata_applied(chip)) 3161 return 0; 3162 3163 /* Set the ports into blocking mode */ 3164 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3165 err = mv88e6xxx_port_set_state(chip, port, BR_STATE_DISABLED); 3166 if (err) 3167 return err; 3168 } 3169 3170 for (port = 0; port < mv88e6xxx_num_ports(chip); port++) { 3171 err = mv88e6xxx_port_hidden_write(chip, 0xf, port, 0, 0x01c0); 3172 if (err) 3173 return err; 3174 } 3175 3176 return mv88e6xxx_software_reset(chip); 3177 } 3178 3179 static void mv88e6xxx_teardown(struct dsa_switch *ds) 3180 { 3181 mv88e6xxx_teardown_devlink_params(ds); 3182 dsa_devlink_resources_unregister(ds); 3183 mv88e6xxx_teardown_devlink_regions_global(ds); 3184 } 3185 3186 static int mv88e6xxx_setup(struct dsa_switch *ds) 3187 { 3188 struct mv88e6xxx_chip *chip = ds->priv; 3189 u8 cmode; 3190 int err; 3191 int i; 3192 3193 chip->ds = ds; 3194 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 3195 3196 /* Since virtual bridges are mapped in the PVT, the number we support 3197 * depends on the physical switch topology. We need to let DSA figure 3198 * that out and therefore we cannot set this at dsa_register_switch() 3199 * time. 3200 */ 3201 if (mv88e6xxx_has_pvt(chip)) 3202 ds->num_fwd_offloading_bridges = MV88E6XXX_MAX_PVT_SWITCHES - 3203 ds->dst->last_switch - 1; 3204 3205 mv88e6xxx_reg_lock(chip); 3206 3207 if (chip->info->ops->setup_errata) { 3208 err = chip->info->ops->setup_errata(chip); 3209 if (err) 3210 goto unlock; 3211 } 3212 3213 /* Cache the cmode of each port. */ 3214 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3215 if (chip->info->ops->port_get_cmode) { 3216 err = chip->info->ops->port_get_cmode(chip, i, &cmode); 3217 if (err) 3218 goto unlock; 3219 3220 chip->ports[i].cmode = cmode; 3221 } 3222 } 3223 3224 err = mv88e6xxx_vtu_setup(chip); 3225 if (err) 3226 goto unlock; 3227 3228 /* Setup Switch Port Registers */ 3229 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 3230 if (dsa_is_unused_port(ds, i)) 3231 continue; 3232 3233 /* Prevent the use of an invalid port. */ 3234 if (mv88e6xxx_is_invalid_port(chip, i)) { 3235 dev_err(chip->dev, "port %d is invalid\n", i); 3236 err = -EINVAL; 3237 goto unlock; 3238 } 3239 3240 err = mv88e6xxx_setup_port(chip, i); 3241 if (err) 3242 goto unlock; 3243 } 3244 3245 err = mv88e6xxx_irl_setup(chip); 3246 if (err) 3247 goto unlock; 3248 3249 err = mv88e6xxx_mac_setup(chip); 3250 if (err) 3251 goto unlock; 3252 3253 err = mv88e6xxx_phy_setup(chip); 3254 if (err) 3255 goto unlock; 3256 3257 err = mv88e6xxx_pvt_setup(chip); 3258 if (err) 3259 goto unlock; 3260 3261 err = mv88e6xxx_atu_setup(chip); 3262 if (err) 3263 goto unlock; 3264 3265 err = mv88e6xxx_broadcast_setup(chip, 0); 3266 if (err) 3267 goto unlock; 3268 3269 err = mv88e6xxx_pot_setup(chip); 3270 if (err) 3271 goto unlock; 3272 3273 err = mv88e6xxx_rmu_setup(chip); 3274 if (err) 3275 goto unlock; 3276 3277 err = mv88e6xxx_rsvd2cpu_setup(chip); 3278 if (err) 3279 goto unlock; 3280 3281 err = mv88e6xxx_trunk_setup(chip); 3282 if (err) 3283 goto unlock; 3284 3285 err = mv88e6xxx_devmap_setup(chip); 3286 if (err) 3287 goto unlock; 3288 3289 err = mv88e6xxx_pri_setup(chip); 3290 if (err) 3291 goto unlock; 3292 3293 /* Setup PTP Hardware Clock and timestamping */ 3294 if (chip->info->ptp_support) { 3295 err = mv88e6xxx_ptp_setup(chip); 3296 if (err) 3297 goto unlock; 3298 3299 err = mv88e6xxx_hwtstamp_setup(chip); 3300 if (err) 3301 goto unlock; 3302 } 3303 3304 err = mv88e6xxx_stats_setup(chip); 3305 if (err) 3306 goto unlock; 3307 3308 unlock: 3309 mv88e6xxx_reg_unlock(chip); 3310 3311 if (err) 3312 return err; 3313 3314 /* Have to be called without holding the register lock, since 3315 * they take the devlink lock, and we later take the locks in 3316 * the reverse order when getting/setting parameters or 3317 * resource occupancy. 3318 */ 3319 err = mv88e6xxx_setup_devlink_resources(ds); 3320 if (err) 3321 return err; 3322 3323 err = mv88e6xxx_setup_devlink_params(ds); 3324 if (err) 3325 goto out_resources; 3326 3327 err = mv88e6xxx_setup_devlink_regions_global(ds); 3328 if (err) 3329 goto out_params; 3330 3331 return 0; 3332 3333 out_params: 3334 mv88e6xxx_teardown_devlink_params(ds); 3335 out_resources: 3336 dsa_devlink_resources_unregister(ds); 3337 3338 return err; 3339 } 3340 3341 static int mv88e6xxx_port_setup(struct dsa_switch *ds, int port) 3342 { 3343 return mv88e6xxx_setup_devlink_regions_port(ds, port); 3344 } 3345 3346 static void mv88e6xxx_port_teardown(struct dsa_switch *ds, int port) 3347 { 3348 mv88e6xxx_teardown_devlink_regions_port(ds, port); 3349 } 3350 3351 /* prod_id for switch families which do not have a PHY model number */ 3352 static const u16 family_prod_id_table[] = { 3353 [MV88E6XXX_FAMILY_6341] = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 3354 [MV88E6XXX_FAMILY_6390] = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 3355 [MV88E6XXX_FAMILY_6393] = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 3356 }; 3357 3358 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 3359 { 3360 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3361 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3362 u16 prod_id; 3363 u16 val; 3364 int err; 3365 3366 if (!chip->info->ops->phy_read) 3367 return -EOPNOTSUPP; 3368 3369 mv88e6xxx_reg_lock(chip); 3370 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 3371 mv88e6xxx_reg_unlock(chip); 3372 3373 /* Some internal PHYs don't have a model number. */ 3374 if (reg == MII_PHYSID2 && !(val & 0x3f0) && 3375 chip->info->family < ARRAY_SIZE(family_prod_id_table)) { 3376 prod_id = family_prod_id_table[chip->info->family]; 3377 if (prod_id) 3378 val |= prod_id >> 4; 3379 } 3380 3381 return err ? err : val; 3382 } 3383 3384 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 3385 { 3386 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 3387 struct mv88e6xxx_chip *chip = mdio_bus->chip; 3388 int err; 3389 3390 if (!chip->info->ops->phy_write) 3391 return -EOPNOTSUPP; 3392 3393 mv88e6xxx_reg_lock(chip); 3394 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 3395 mv88e6xxx_reg_unlock(chip); 3396 3397 return err; 3398 } 3399 3400 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 3401 struct device_node *np, 3402 bool external) 3403 { 3404 static int index; 3405 struct mv88e6xxx_mdio_bus *mdio_bus; 3406 struct mii_bus *bus; 3407 int err; 3408 3409 if (external) { 3410 mv88e6xxx_reg_lock(chip); 3411 err = mv88e6xxx_g2_scratch_gpio_set_smi(chip, true); 3412 mv88e6xxx_reg_unlock(chip); 3413 3414 if (err) 3415 return err; 3416 } 3417 3418 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 3419 if (!bus) 3420 return -ENOMEM; 3421 3422 mdio_bus = bus->priv; 3423 mdio_bus->bus = bus; 3424 mdio_bus->chip = chip; 3425 INIT_LIST_HEAD(&mdio_bus->list); 3426 mdio_bus->external = external; 3427 3428 if (np) { 3429 bus->name = np->full_name; 3430 snprintf(bus->id, MII_BUS_ID_SIZE, "%pOF", np); 3431 } else { 3432 bus->name = "mv88e6xxx SMI"; 3433 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 3434 } 3435 3436 bus->read = mv88e6xxx_mdio_read; 3437 bus->write = mv88e6xxx_mdio_write; 3438 bus->parent = chip->dev; 3439 3440 if (!external) { 3441 err = mv88e6xxx_g2_irq_mdio_setup(chip, bus); 3442 if (err) 3443 return err; 3444 } 3445 3446 err = of_mdiobus_register(bus, np); 3447 if (err) { 3448 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 3449 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3450 return err; 3451 } 3452 3453 if (external) 3454 list_add_tail(&mdio_bus->list, &chip->mdios); 3455 else 3456 list_add(&mdio_bus->list, &chip->mdios); 3457 3458 return 0; 3459 } 3460 3461 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3462 3463 { 3464 struct mv88e6xxx_mdio_bus *mdio_bus; 3465 struct mii_bus *bus; 3466 3467 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3468 bus = mdio_bus->bus; 3469 3470 if (!mdio_bus->external) 3471 mv88e6xxx_g2_irq_mdio_free(chip, bus); 3472 3473 mdiobus_unregister(bus); 3474 } 3475 } 3476 3477 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3478 struct device_node *np) 3479 { 3480 struct device_node *child; 3481 int err; 3482 3483 /* Always register one mdio bus for the internal/default mdio 3484 * bus. This maybe represented in the device tree, but is 3485 * optional. 3486 */ 3487 child = of_get_child_by_name(np, "mdio"); 3488 err = mv88e6xxx_mdio_register(chip, child, false); 3489 if (err) 3490 return err; 3491 3492 /* Walk the device tree, and see if there are any other nodes 3493 * which say they are compatible with the external mdio 3494 * bus. 3495 */ 3496 for_each_available_child_of_node(np, child) { 3497 if (of_device_is_compatible( 3498 child, "marvell,mv88e6xxx-mdio-external")) { 3499 err = mv88e6xxx_mdio_register(chip, child, true); 3500 if (err) { 3501 mv88e6xxx_mdios_unregister(chip); 3502 of_node_put(child); 3503 return err; 3504 } 3505 } 3506 } 3507 3508 return 0; 3509 } 3510 3511 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3512 { 3513 struct mv88e6xxx_chip *chip = ds->priv; 3514 3515 return chip->eeprom_len; 3516 } 3517 3518 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3519 struct ethtool_eeprom *eeprom, u8 *data) 3520 { 3521 struct mv88e6xxx_chip *chip = ds->priv; 3522 int err; 3523 3524 if (!chip->info->ops->get_eeprom) 3525 return -EOPNOTSUPP; 3526 3527 mv88e6xxx_reg_lock(chip); 3528 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3529 mv88e6xxx_reg_unlock(chip); 3530 3531 if (err) 3532 return err; 3533 3534 eeprom->magic = 0xc3ec4951; 3535 3536 return 0; 3537 } 3538 3539 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3540 struct ethtool_eeprom *eeprom, u8 *data) 3541 { 3542 struct mv88e6xxx_chip *chip = ds->priv; 3543 int err; 3544 3545 if (!chip->info->ops->set_eeprom) 3546 return -EOPNOTSUPP; 3547 3548 if (eeprom->magic != 0xc3ec4951) 3549 return -EINVAL; 3550 3551 mv88e6xxx_reg_lock(chip); 3552 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3553 mv88e6xxx_reg_unlock(chip); 3554 3555 return err; 3556 } 3557 3558 static const struct mv88e6xxx_ops mv88e6085_ops = { 3559 /* MV88E6XXX_FAMILY_6097 */ 3560 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3561 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3562 .irl_init_all = mv88e6352_g2_irl_init_all, 3563 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3564 .phy_read = mv88e6185_phy_ppu_read, 3565 .phy_write = mv88e6185_phy_ppu_write, 3566 .port_set_link = mv88e6xxx_port_set_link, 3567 .port_sync_link = mv88e6xxx_port_sync_link, 3568 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3569 .port_tag_remap = mv88e6095_port_tag_remap, 3570 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3571 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3572 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3573 .port_set_ether_type = mv88e6351_port_set_ether_type, 3574 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3575 .port_pause_limit = mv88e6097_port_pause_limit, 3576 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3577 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3578 .port_get_cmode = mv88e6185_port_get_cmode, 3579 .port_setup_message_port = mv88e6xxx_setup_message_port, 3580 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3581 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3582 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3583 .stats_get_strings = mv88e6095_stats_get_strings, 3584 .stats_get_stats = mv88e6095_stats_get_stats, 3585 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3586 .set_egress_port = mv88e6095_g1_set_egress_port, 3587 .watchdog_ops = &mv88e6097_watchdog_ops, 3588 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3589 .pot_clear = mv88e6xxx_g2_pot_clear, 3590 .ppu_enable = mv88e6185_g1_ppu_enable, 3591 .ppu_disable = mv88e6185_g1_ppu_disable, 3592 .reset = mv88e6185_g1_reset, 3593 .rmu_disable = mv88e6085_g1_rmu_disable, 3594 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3595 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3596 .phylink_validate = mv88e6185_phylink_validate, 3597 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3598 }; 3599 3600 static const struct mv88e6xxx_ops mv88e6095_ops = { 3601 /* MV88E6XXX_FAMILY_6095 */ 3602 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3603 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3604 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3605 .phy_read = mv88e6185_phy_ppu_read, 3606 .phy_write = mv88e6185_phy_ppu_write, 3607 .port_set_link = mv88e6xxx_port_set_link, 3608 .port_sync_link = mv88e6185_port_sync_link, 3609 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3610 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3611 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3612 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3613 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3614 .port_get_cmode = mv88e6185_port_get_cmode, 3615 .port_setup_message_port = mv88e6xxx_setup_message_port, 3616 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3617 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3618 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3619 .stats_get_strings = mv88e6095_stats_get_strings, 3620 .stats_get_stats = mv88e6095_stats_get_stats, 3621 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3622 .serdes_power = mv88e6185_serdes_power, 3623 .serdes_get_lane = mv88e6185_serdes_get_lane, 3624 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3625 .ppu_enable = mv88e6185_g1_ppu_enable, 3626 .ppu_disable = mv88e6185_g1_ppu_disable, 3627 .reset = mv88e6185_g1_reset, 3628 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3629 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3630 .phylink_validate = mv88e6185_phylink_validate, 3631 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3632 }; 3633 3634 static const struct mv88e6xxx_ops mv88e6097_ops = { 3635 /* MV88E6XXX_FAMILY_6097 */ 3636 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3637 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3638 .irl_init_all = mv88e6352_g2_irl_init_all, 3639 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3640 .phy_read = mv88e6xxx_g2_smi_phy_read, 3641 .phy_write = mv88e6xxx_g2_smi_phy_write, 3642 .port_set_link = mv88e6xxx_port_set_link, 3643 .port_sync_link = mv88e6185_port_sync_link, 3644 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3645 .port_tag_remap = mv88e6095_port_tag_remap, 3646 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3647 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3648 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3649 .port_set_ether_type = mv88e6351_port_set_ether_type, 3650 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3651 .port_pause_limit = mv88e6097_port_pause_limit, 3652 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3653 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3654 .port_get_cmode = mv88e6185_port_get_cmode, 3655 .port_setup_message_port = mv88e6xxx_setup_message_port, 3656 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3657 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3658 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3659 .stats_get_strings = mv88e6095_stats_get_strings, 3660 .stats_get_stats = mv88e6095_stats_get_stats, 3661 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3662 .set_egress_port = mv88e6095_g1_set_egress_port, 3663 .watchdog_ops = &mv88e6097_watchdog_ops, 3664 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3665 .serdes_power = mv88e6185_serdes_power, 3666 .serdes_get_lane = mv88e6185_serdes_get_lane, 3667 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 3668 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3669 .serdes_irq_enable = mv88e6097_serdes_irq_enable, 3670 .serdes_irq_status = mv88e6097_serdes_irq_status, 3671 .pot_clear = mv88e6xxx_g2_pot_clear, 3672 .reset = mv88e6352_g1_reset, 3673 .rmu_disable = mv88e6085_g1_rmu_disable, 3674 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3675 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3676 .phylink_validate = mv88e6185_phylink_validate, 3677 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3678 }; 3679 3680 static const struct mv88e6xxx_ops mv88e6123_ops = { 3681 /* MV88E6XXX_FAMILY_6165 */ 3682 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3683 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3684 .irl_init_all = mv88e6352_g2_irl_init_all, 3685 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3686 .phy_read = mv88e6xxx_g2_smi_phy_read, 3687 .phy_write = mv88e6xxx_g2_smi_phy_write, 3688 .port_set_link = mv88e6xxx_port_set_link, 3689 .port_sync_link = mv88e6xxx_port_sync_link, 3690 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3691 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3692 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3693 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3694 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3695 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3696 .port_get_cmode = mv88e6185_port_get_cmode, 3697 .port_setup_message_port = mv88e6xxx_setup_message_port, 3698 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3699 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3700 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3701 .stats_get_strings = mv88e6095_stats_get_strings, 3702 .stats_get_stats = mv88e6095_stats_get_stats, 3703 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3704 .set_egress_port = mv88e6095_g1_set_egress_port, 3705 .watchdog_ops = &mv88e6097_watchdog_ops, 3706 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3707 .pot_clear = mv88e6xxx_g2_pot_clear, 3708 .reset = mv88e6352_g1_reset, 3709 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3710 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3711 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3712 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3713 .phylink_validate = mv88e6185_phylink_validate, 3714 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3715 }; 3716 3717 static const struct mv88e6xxx_ops mv88e6131_ops = { 3718 /* MV88E6XXX_FAMILY_6185 */ 3719 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3720 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3721 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3722 .phy_read = mv88e6185_phy_ppu_read, 3723 .phy_write = mv88e6185_phy_ppu_write, 3724 .port_set_link = mv88e6xxx_port_set_link, 3725 .port_sync_link = mv88e6xxx_port_sync_link, 3726 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3727 .port_tag_remap = mv88e6095_port_tag_remap, 3728 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3729 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 3730 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 3731 .port_set_ether_type = mv88e6351_port_set_ether_type, 3732 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3733 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3734 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3735 .port_pause_limit = mv88e6097_port_pause_limit, 3736 .port_set_pause = mv88e6185_port_set_pause, 3737 .port_get_cmode = mv88e6185_port_get_cmode, 3738 .port_setup_message_port = mv88e6xxx_setup_message_port, 3739 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3740 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3741 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3742 .stats_get_strings = mv88e6095_stats_get_strings, 3743 .stats_get_stats = mv88e6095_stats_get_stats, 3744 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3745 .set_egress_port = mv88e6095_g1_set_egress_port, 3746 .watchdog_ops = &mv88e6097_watchdog_ops, 3747 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 3748 .ppu_enable = mv88e6185_g1_ppu_enable, 3749 .set_cascade_port = mv88e6185_g1_set_cascade_port, 3750 .ppu_disable = mv88e6185_g1_ppu_disable, 3751 .reset = mv88e6185_g1_reset, 3752 .vtu_getnext = mv88e6185_g1_vtu_getnext, 3753 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 3754 .phylink_validate = mv88e6185_phylink_validate, 3755 }; 3756 3757 static const struct mv88e6xxx_ops mv88e6141_ops = { 3758 /* MV88E6XXX_FAMILY_6341 */ 3759 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3760 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3761 .irl_init_all = mv88e6352_g2_irl_init_all, 3762 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3763 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3764 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3765 .phy_read = mv88e6xxx_g2_smi_phy_read, 3766 .phy_write = mv88e6xxx_g2_smi_phy_write, 3767 .port_set_link = mv88e6xxx_port_set_link, 3768 .port_sync_link = mv88e6xxx_port_sync_link, 3769 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3770 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 3771 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 3772 .port_tag_remap = mv88e6095_port_tag_remap, 3773 .port_set_policy = mv88e6352_port_set_policy, 3774 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3775 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3776 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3777 .port_set_ether_type = mv88e6351_port_set_ether_type, 3778 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3779 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3780 .port_pause_limit = mv88e6097_port_pause_limit, 3781 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3782 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3783 .port_get_cmode = mv88e6352_port_get_cmode, 3784 .port_set_cmode = mv88e6341_port_set_cmode, 3785 .port_setup_message_port = mv88e6xxx_setup_message_port, 3786 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3787 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3788 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3789 .stats_get_strings = mv88e6320_stats_get_strings, 3790 .stats_get_stats = mv88e6390_stats_get_stats, 3791 .set_cpu_port = mv88e6390_g1_set_cpu_port, 3792 .set_egress_port = mv88e6390_g1_set_egress_port, 3793 .watchdog_ops = &mv88e6390_watchdog_ops, 3794 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3795 .pot_clear = mv88e6xxx_g2_pot_clear, 3796 .reset = mv88e6352_g1_reset, 3797 .rmu_disable = mv88e6390_g1_rmu_disable, 3798 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3799 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3800 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3801 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3802 .serdes_power = mv88e6390_serdes_power, 3803 .serdes_get_lane = mv88e6341_serdes_get_lane, 3804 /* Check status register pause & lpa register */ 3805 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 3806 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 3807 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 3808 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 3809 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 3810 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 3811 .serdes_irq_status = mv88e6390_serdes_irq_status, 3812 .gpio_ops = &mv88e6352_gpio_ops, 3813 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 3814 .serdes_get_strings = mv88e6390_serdes_get_strings, 3815 .serdes_get_stats = mv88e6390_serdes_get_stats, 3816 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 3817 .serdes_get_regs = mv88e6390_serdes_get_regs, 3818 .phylink_validate = mv88e6341_phylink_validate, 3819 }; 3820 3821 static const struct mv88e6xxx_ops mv88e6161_ops = { 3822 /* MV88E6XXX_FAMILY_6165 */ 3823 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3824 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3825 .irl_init_all = mv88e6352_g2_irl_init_all, 3826 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3827 .phy_read = mv88e6xxx_g2_smi_phy_read, 3828 .phy_write = mv88e6xxx_g2_smi_phy_write, 3829 .port_set_link = mv88e6xxx_port_set_link, 3830 .port_sync_link = mv88e6xxx_port_sync_link, 3831 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3832 .port_tag_remap = mv88e6095_port_tag_remap, 3833 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3834 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3835 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3836 .port_set_ether_type = mv88e6351_port_set_ether_type, 3837 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3838 .port_pause_limit = mv88e6097_port_pause_limit, 3839 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3840 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3841 .port_get_cmode = mv88e6185_port_get_cmode, 3842 .port_setup_message_port = mv88e6xxx_setup_message_port, 3843 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3844 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3845 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3846 .stats_get_strings = mv88e6095_stats_get_strings, 3847 .stats_get_stats = mv88e6095_stats_get_stats, 3848 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3849 .set_egress_port = mv88e6095_g1_set_egress_port, 3850 .watchdog_ops = &mv88e6097_watchdog_ops, 3851 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3852 .pot_clear = mv88e6xxx_g2_pot_clear, 3853 .reset = mv88e6352_g1_reset, 3854 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3855 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3856 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3857 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3858 .avb_ops = &mv88e6165_avb_ops, 3859 .ptp_ops = &mv88e6165_ptp_ops, 3860 .phylink_validate = mv88e6185_phylink_validate, 3861 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 3862 }; 3863 3864 static const struct mv88e6xxx_ops mv88e6165_ops = { 3865 /* MV88E6XXX_FAMILY_6165 */ 3866 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3867 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3868 .irl_init_all = mv88e6352_g2_irl_init_all, 3869 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3870 .phy_read = mv88e6165_phy_read, 3871 .phy_write = mv88e6165_phy_write, 3872 .port_set_link = mv88e6xxx_port_set_link, 3873 .port_sync_link = mv88e6xxx_port_sync_link, 3874 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3875 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3876 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3877 .port_get_cmode = mv88e6185_port_get_cmode, 3878 .port_setup_message_port = mv88e6xxx_setup_message_port, 3879 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3880 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3881 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3882 .stats_get_strings = mv88e6095_stats_get_strings, 3883 .stats_get_stats = mv88e6095_stats_get_stats, 3884 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3885 .set_egress_port = mv88e6095_g1_set_egress_port, 3886 .watchdog_ops = &mv88e6097_watchdog_ops, 3887 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3888 .pot_clear = mv88e6xxx_g2_pot_clear, 3889 .reset = mv88e6352_g1_reset, 3890 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3891 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3892 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3893 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3894 .avb_ops = &mv88e6165_avb_ops, 3895 .ptp_ops = &mv88e6165_ptp_ops, 3896 .phylink_validate = mv88e6185_phylink_validate, 3897 }; 3898 3899 static const struct mv88e6xxx_ops mv88e6171_ops = { 3900 /* MV88E6XXX_FAMILY_6351 */ 3901 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3902 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3903 .irl_init_all = mv88e6352_g2_irl_init_all, 3904 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3905 .phy_read = mv88e6xxx_g2_smi_phy_read, 3906 .phy_write = mv88e6xxx_g2_smi_phy_write, 3907 .port_set_link = mv88e6xxx_port_set_link, 3908 .port_sync_link = mv88e6xxx_port_sync_link, 3909 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3910 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 3911 .port_tag_remap = mv88e6095_port_tag_remap, 3912 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3913 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3914 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3915 .port_set_ether_type = mv88e6351_port_set_ether_type, 3916 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3917 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3918 .port_pause_limit = mv88e6097_port_pause_limit, 3919 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3920 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3921 .port_get_cmode = mv88e6352_port_get_cmode, 3922 .port_setup_message_port = mv88e6xxx_setup_message_port, 3923 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3924 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3925 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3926 .stats_get_strings = mv88e6095_stats_get_strings, 3927 .stats_get_stats = mv88e6095_stats_get_stats, 3928 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3929 .set_egress_port = mv88e6095_g1_set_egress_port, 3930 .watchdog_ops = &mv88e6097_watchdog_ops, 3931 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3932 .pot_clear = mv88e6xxx_g2_pot_clear, 3933 .reset = mv88e6352_g1_reset, 3934 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3935 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3936 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3937 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3938 .phylink_validate = mv88e6185_phylink_validate, 3939 }; 3940 3941 static const struct mv88e6xxx_ops mv88e6172_ops = { 3942 /* MV88E6XXX_FAMILY_6352 */ 3943 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3944 .ip_pri_map = mv88e6085_g1_ip_pri_map, 3945 .irl_init_all = mv88e6352_g2_irl_init_all, 3946 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3947 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3948 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3949 .phy_read = mv88e6xxx_g2_smi_phy_read, 3950 .phy_write = mv88e6xxx_g2_smi_phy_write, 3951 .port_set_link = mv88e6xxx_port_set_link, 3952 .port_sync_link = mv88e6xxx_port_sync_link, 3953 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3954 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 3955 .port_tag_remap = mv88e6095_port_tag_remap, 3956 .port_set_policy = mv88e6352_port_set_policy, 3957 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3958 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 3959 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 3960 .port_set_ether_type = mv88e6351_port_set_ether_type, 3961 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 3962 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3963 .port_pause_limit = mv88e6097_port_pause_limit, 3964 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 3965 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 3966 .port_get_cmode = mv88e6352_port_get_cmode, 3967 .port_setup_message_port = mv88e6xxx_setup_message_port, 3968 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3969 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 3970 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3971 .stats_get_strings = mv88e6095_stats_get_strings, 3972 .stats_get_stats = mv88e6095_stats_get_stats, 3973 .set_cpu_port = mv88e6095_g1_set_cpu_port, 3974 .set_egress_port = mv88e6095_g1_set_egress_port, 3975 .watchdog_ops = &mv88e6097_watchdog_ops, 3976 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 3977 .pot_clear = mv88e6xxx_g2_pot_clear, 3978 .reset = mv88e6352_g1_reset, 3979 .rmu_disable = mv88e6352_g1_rmu_disable, 3980 .atu_get_hash = mv88e6165_g1_atu_get_hash, 3981 .atu_set_hash = mv88e6165_g1_atu_set_hash, 3982 .vtu_getnext = mv88e6352_g1_vtu_getnext, 3983 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 3984 .serdes_get_lane = mv88e6352_serdes_get_lane, 3985 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 3986 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 3987 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 3988 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 3989 .serdes_power = mv88e6352_serdes_power, 3990 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 3991 .serdes_get_regs = mv88e6352_serdes_get_regs, 3992 .gpio_ops = &mv88e6352_gpio_ops, 3993 .phylink_validate = mv88e6352_phylink_validate, 3994 }; 3995 3996 static const struct mv88e6xxx_ops mv88e6175_ops = { 3997 /* MV88E6XXX_FAMILY_6351 */ 3998 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 3999 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4000 .irl_init_all = mv88e6352_g2_irl_init_all, 4001 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4002 .phy_read = mv88e6xxx_g2_smi_phy_read, 4003 .phy_write = mv88e6xxx_g2_smi_phy_write, 4004 .port_set_link = mv88e6xxx_port_set_link, 4005 .port_sync_link = mv88e6xxx_port_sync_link, 4006 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4007 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4008 .port_tag_remap = mv88e6095_port_tag_remap, 4009 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4010 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4011 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4012 .port_set_ether_type = mv88e6351_port_set_ether_type, 4013 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4014 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4015 .port_pause_limit = mv88e6097_port_pause_limit, 4016 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4017 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4018 .port_get_cmode = mv88e6352_port_get_cmode, 4019 .port_setup_message_port = mv88e6xxx_setup_message_port, 4020 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4021 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4022 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4023 .stats_get_strings = mv88e6095_stats_get_strings, 4024 .stats_get_stats = mv88e6095_stats_get_stats, 4025 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4026 .set_egress_port = mv88e6095_g1_set_egress_port, 4027 .watchdog_ops = &mv88e6097_watchdog_ops, 4028 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4029 .pot_clear = mv88e6xxx_g2_pot_clear, 4030 .reset = mv88e6352_g1_reset, 4031 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4032 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4033 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4034 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4035 .phylink_validate = mv88e6185_phylink_validate, 4036 }; 4037 4038 static const struct mv88e6xxx_ops mv88e6176_ops = { 4039 /* MV88E6XXX_FAMILY_6352 */ 4040 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4041 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4042 .irl_init_all = mv88e6352_g2_irl_init_all, 4043 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4044 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4045 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4046 .phy_read = mv88e6xxx_g2_smi_phy_read, 4047 .phy_write = mv88e6xxx_g2_smi_phy_write, 4048 .port_set_link = mv88e6xxx_port_set_link, 4049 .port_sync_link = mv88e6xxx_port_sync_link, 4050 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4051 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4052 .port_tag_remap = mv88e6095_port_tag_remap, 4053 .port_set_policy = mv88e6352_port_set_policy, 4054 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4055 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4056 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4057 .port_set_ether_type = mv88e6351_port_set_ether_type, 4058 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4059 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4060 .port_pause_limit = mv88e6097_port_pause_limit, 4061 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4062 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4063 .port_get_cmode = mv88e6352_port_get_cmode, 4064 .port_setup_message_port = mv88e6xxx_setup_message_port, 4065 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4066 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4067 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4068 .stats_get_strings = mv88e6095_stats_get_strings, 4069 .stats_get_stats = mv88e6095_stats_get_stats, 4070 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4071 .set_egress_port = mv88e6095_g1_set_egress_port, 4072 .watchdog_ops = &mv88e6097_watchdog_ops, 4073 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4074 .pot_clear = mv88e6xxx_g2_pot_clear, 4075 .reset = mv88e6352_g1_reset, 4076 .rmu_disable = mv88e6352_g1_rmu_disable, 4077 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4078 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4079 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4080 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4081 .serdes_get_lane = mv88e6352_serdes_get_lane, 4082 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4083 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4084 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4085 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4086 .serdes_power = mv88e6352_serdes_power, 4087 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4088 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4089 .serdes_irq_status = mv88e6352_serdes_irq_status, 4090 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4091 .serdes_get_regs = mv88e6352_serdes_get_regs, 4092 .gpio_ops = &mv88e6352_gpio_ops, 4093 .phylink_validate = mv88e6352_phylink_validate, 4094 }; 4095 4096 static const struct mv88e6xxx_ops mv88e6185_ops = { 4097 /* MV88E6XXX_FAMILY_6185 */ 4098 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4099 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4100 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 4101 .phy_read = mv88e6185_phy_ppu_read, 4102 .phy_write = mv88e6185_phy_ppu_write, 4103 .port_set_link = mv88e6xxx_port_set_link, 4104 .port_sync_link = mv88e6185_port_sync_link, 4105 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4106 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 4107 .port_set_ucast_flood = mv88e6185_port_set_forward_unknown, 4108 .port_set_mcast_flood = mv88e6185_port_set_default_forward, 4109 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 4110 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 4111 .port_set_pause = mv88e6185_port_set_pause, 4112 .port_get_cmode = mv88e6185_port_get_cmode, 4113 .port_setup_message_port = mv88e6xxx_setup_message_port, 4114 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 4115 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4116 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4117 .stats_get_strings = mv88e6095_stats_get_strings, 4118 .stats_get_stats = mv88e6095_stats_get_stats, 4119 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4120 .set_egress_port = mv88e6095_g1_set_egress_port, 4121 .watchdog_ops = &mv88e6097_watchdog_ops, 4122 .mgmt_rsvd2cpu = mv88e6185_g2_mgmt_rsvd2cpu, 4123 .serdes_power = mv88e6185_serdes_power, 4124 .serdes_get_lane = mv88e6185_serdes_get_lane, 4125 .serdes_pcs_get_state = mv88e6185_serdes_pcs_get_state, 4126 .set_cascade_port = mv88e6185_g1_set_cascade_port, 4127 .ppu_enable = mv88e6185_g1_ppu_enable, 4128 .ppu_disable = mv88e6185_g1_ppu_disable, 4129 .reset = mv88e6185_g1_reset, 4130 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4131 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4132 .phylink_validate = mv88e6185_phylink_validate, 4133 .set_max_frame_size = mv88e6185_g1_set_max_frame_size, 4134 }; 4135 4136 static const struct mv88e6xxx_ops mv88e6190_ops = { 4137 /* MV88E6XXX_FAMILY_6390 */ 4138 .setup_errata = mv88e6390_setup_errata, 4139 .irl_init_all = mv88e6390_g2_irl_init_all, 4140 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4141 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4142 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4143 .phy_read = mv88e6xxx_g2_smi_phy_read, 4144 .phy_write = mv88e6xxx_g2_smi_phy_write, 4145 .port_set_link = mv88e6xxx_port_set_link, 4146 .port_sync_link = mv88e6xxx_port_sync_link, 4147 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4148 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4149 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4150 .port_tag_remap = mv88e6390_port_tag_remap, 4151 .port_set_policy = mv88e6352_port_set_policy, 4152 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4153 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4154 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4155 .port_set_ether_type = mv88e6351_port_set_ether_type, 4156 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4157 .port_pause_limit = mv88e6390_port_pause_limit, 4158 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4159 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4160 .port_get_cmode = mv88e6352_port_get_cmode, 4161 .port_set_cmode = mv88e6390_port_set_cmode, 4162 .port_setup_message_port = mv88e6xxx_setup_message_port, 4163 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4164 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4165 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4166 .stats_get_strings = mv88e6320_stats_get_strings, 4167 .stats_get_stats = mv88e6390_stats_get_stats, 4168 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4169 .set_egress_port = mv88e6390_g1_set_egress_port, 4170 .watchdog_ops = &mv88e6390_watchdog_ops, 4171 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4172 .pot_clear = mv88e6xxx_g2_pot_clear, 4173 .reset = mv88e6352_g1_reset, 4174 .rmu_disable = mv88e6390_g1_rmu_disable, 4175 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4176 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4177 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4178 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4179 .serdes_power = mv88e6390_serdes_power, 4180 .serdes_get_lane = mv88e6390_serdes_get_lane, 4181 /* Check status register pause & lpa register */ 4182 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4183 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4184 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4185 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4186 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4187 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4188 .serdes_irq_status = mv88e6390_serdes_irq_status, 4189 .serdes_get_strings = mv88e6390_serdes_get_strings, 4190 .serdes_get_stats = mv88e6390_serdes_get_stats, 4191 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4192 .serdes_get_regs = mv88e6390_serdes_get_regs, 4193 .gpio_ops = &mv88e6352_gpio_ops, 4194 .phylink_validate = mv88e6390_phylink_validate, 4195 }; 4196 4197 static const struct mv88e6xxx_ops mv88e6190x_ops = { 4198 /* MV88E6XXX_FAMILY_6390 */ 4199 .setup_errata = mv88e6390_setup_errata, 4200 .irl_init_all = mv88e6390_g2_irl_init_all, 4201 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4202 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4203 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4204 .phy_read = mv88e6xxx_g2_smi_phy_read, 4205 .phy_write = mv88e6xxx_g2_smi_phy_write, 4206 .port_set_link = mv88e6xxx_port_set_link, 4207 .port_sync_link = mv88e6xxx_port_sync_link, 4208 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4209 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4210 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4211 .port_tag_remap = mv88e6390_port_tag_remap, 4212 .port_set_policy = mv88e6352_port_set_policy, 4213 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4214 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4215 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4216 .port_set_ether_type = mv88e6351_port_set_ether_type, 4217 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4218 .port_pause_limit = mv88e6390_port_pause_limit, 4219 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4220 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4221 .port_get_cmode = mv88e6352_port_get_cmode, 4222 .port_set_cmode = mv88e6390x_port_set_cmode, 4223 .port_setup_message_port = mv88e6xxx_setup_message_port, 4224 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4225 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4226 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4227 .stats_get_strings = mv88e6320_stats_get_strings, 4228 .stats_get_stats = mv88e6390_stats_get_stats, 4229 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4230 .set_egress_port = mv88e6390_g1_set_egress_port, 4231 .watchdog_ops = &mv88e6390_watchdog_ops, 4232 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4233 .pot_clear = mv88e6xxx_g2_pot_clear, 4234 .reset = mv88e6352_g1_reset, 4235 .rmu_disable = mv88e6390_g1_rmu_disable, 4236 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4237 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4238 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4239 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4240 .serdes_power = mv88e6390_serdes_power, 4241 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4242 /* Check status register pause & lpa register */ 4243 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4244 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4245 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4246 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4247 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4248 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4249 .serdes_irq_status = mv88e6390_serdes_irq_status, 4250 .serdes_get_strings = mv88e6390_serdes_get_strings, 4251 .serdes_get_stats = mv88e6390_serdes_get_stats, 4252 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4253 .serdes_get_regs = mv88e6390_serdes_get_regs, 4254 .gpio_ops = &mv88e6352_gpio_ops, 4255 .phylink_validate = mv88e6390x_phylink_validate, 4256 }; 4257 4258 static const struct mv88e6xxx_ops mv88e6191_ops = { 4259 /* MV88E6XXX_FAMILY_6390 */ 4260 .setup_errata = mv88e6390_setup_errata, 4261 .irl_init_all = mv88e6390_g2_irl_init_all, 4262 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4263 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4264 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4265 .phy_read = mv88e6xxx_g2_smi_phy_read, 4266 .phy_write = mv88e6xxx_g2_smi_phy_write, 4267 .port_set_link = mv88e6xxx_port_set_link, 4268 .port_sync_link = mv88e6xxx_port_sync_link, 4269 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4270 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4271 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4272 .port_tag_remap = mv88e6390_port_tag_remap, 4273 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4274 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4275 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4276 .port_set_ether_type = mv88e6351_port_set_ether_type, 4277 .port_pause_limit = mv88e6390_port_pause_limit, 4278 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4279 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4280 .port_get_cmode = mv88e6352_port_get_cmode, 4281 .port_set_cmode = mv88e6390_port_set_cmode, 4282 .port_setup_message_port = mv88e6xxx_setup_message_port, 4283 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4284 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4285 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4286 .stats_get_strings = mv88e6320_stats_get_strings, 4287 .stats_get_stats = mv88e6390_stats_get_stats, 4288 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4289 .set_egress_port = mv88e6390_g1_set_egress_port, 4290 .watchdog_ops = &mv88e6390_watchdog_ops, 4291 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4292 .pot_clear = mv88e6xxx_g2_pot_clear, 4293 .reset = mv88e6352_g1_reset, 4294 .rmu_disable = mv88e6390_g1_rmu_disable, 4295 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4296 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4297 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4298 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4299 .serdes_power = mv88e6390_serdes_power, 4300 .serdes_get_lane = mv88e6390_serdes_get_lane, 4301 /* Check status register pause & lpa register */ 4302 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4303 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4304 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4305 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4306 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4307 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4308 .serdes_irq_status = mv88e6390_serdes_irq_status, 4309 .serdes_get_strings = mv88e6390_serdes_get_strings, 4310 .serdes_get_stats = mv88e6390_serdes_get_stats, 4311 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4312 .serdes_get_regs = mv88e6390_serdes_get_regs, 4313 .avb_ops = &mv88e6390_avb_ops, 4314 .ptp_ops = &mv88e6352_ptp_ops, 4315 .phylink_validate = mv88e6390_phylink_validate, 4316 }; 4317 4318 static const struct mv88e6xxx_ops mv88e6240_ops = { 4319 /* MV88E6XXX_FAMILY_6352 */ 4320 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4321 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4322 .irl_init_all = mv88e6352_g2_irl_init_all, 4323 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4324 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4325 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4326 .phy_read = mv88e6xxx_g2_smi_phy_read, 4327 .phy_write = mv88e6xxx_g2_smi_phy_write, 4328 .port_set_link = mv88e6xxx_port_set_link, 4329 .port_sync_link = mv88e6xxx_port_sync_link, 4330 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4331 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4332 .port_tag_remap = mv88e6095_port_tag_remap, 4333 .port_set_policy = mv88e6352_port_set_policy, 4334 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4335 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4336 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4337 .port_set_ether_type = mv88e6351_port_set_ether_type, 4338 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4339 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4340 .port_pause_limit = mv88e6097_port_pause_limit, 4341 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4342 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4343 .port_get_cmode = mv88e6352_port_get_cmode, 4344 .port_setup_message_port = mv88e6xxx_setup_message_port, 4345 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4346 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4347 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4348 .stats_get_strings = mv88e6095_stats_get_strings, 4349 .stats_get_stats = mv88e6095_stats_get_stats, 4350 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4351 .set_egress_port = mv88e6095_g1_set_egress_port, 4352 .watchdog_ops = &mv88e6097_watchdog_ops, 4353 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4354 .pot_clear = mv88e6xxx_g2_pot_clear, 4355 .reset = mv88e6352_g1_reset, 4356 .rmu_disable = mv88e6352_g1_rmu_disable, 4357 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4358 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4359 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4360 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4361 .serdes_get_lane = mv88e6352_serdes_get_lane, 4362 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4363 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4364 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4365 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4366 .serdes_power = mv88e6352_serdes_power, 4367 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4368 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4369 .serdes_irq_status = mv88e6352_serdes_irq_status, 4370 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4371 .serdes_get_regs = mv88e6352_serdes_get_regs, 4372 .gpio_ops = &mv88e6352_gpio_ops, 4373 .avb_ops = &mv88e6352_avb_ops, 4374 .ptp_ops = &mv88e6352_ptp_ops, 4375 .phylink_validate = mv88e6352_phylink_validate, 4376 }; 4377 4378 static const struct mv88e6xxx_ops mv88e6250_ops = { 4379 /* MV88E6XXX_FAMILY_6250 */ 4380 .ieee_pri_map = mv88e6250_g1_ieee_pri_map, 4381 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4382 .irl_init_all = mv88e6352_g2_irl_init_all, 4383 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4384 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4385 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4386 .phy_read = mv88e6xxx_g2_smi_phy_read, 4387 .phy_write = mv88e6xxx_g2_smi_phy_write, 4388 .port_set_link = mv88e6xxx_port_set_link, 4389 .port_sync_link = mv88e6xxx_port_sync_link, 4390 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4391 .port_set_speed_duplex = mv88e6250_port_set_speed_duplex, 4392 .port_tag_remap = mv88e6095_port_tag_remap, 4393 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4394 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4395 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4396 .port_set_ether_type = mv88e6351_port_set_ether_type, 4397 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4398 .port_pause_limit = mv88e6097_port_pause_limit, 4399 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4400 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4401 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4402 .stats_get_sset_count = mv88e6250_stats_get_sset_count, 4403 .stats_get_strings = mv88e6250_stats_get_strings, 4404 .stats_get_stats = mv88e6250_stats_get_stats, 4405 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4406 .set_egress_port = mv88e6095_g1_set_egress_port, 4407 .watchdog_ops = &mv88e6250_watchdog_ops, 4408 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4409 .pot_clear = mv88e6xxx_g2_pot_clear, 4410 .reset = mv88e6250_g1_reset, 4411 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4412 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4413 .avb_ops = &mv88e6352_avb_ops, 4414 .ptp_ops = &mv88e6250_ptp_ops, 4415 .phylink_validate = mv88e6065_phylink_validate, 4416 }; 4417 4418 static const struct mv88e6xxx_ops mv88e6290_ops = { 4419 /* MV88E6XXX_FAMILY_6390 */ 4420 .setup_errata = mv88e6390_setup_errata, 4421 .irl_init_all = mv88e6390_g2_irl_init_all, 4422 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4423 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4424 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4425 .phy_read = mv88e6xxx_g2_smi_phy_read, 4426 .phy_write = mv88e6xxx_g2_smi_phy_write, 4427 .port_set_link = mv88e6xxx_port_set_link, 4428 .port_sync_link = mv88e6xxx_port_sync_link, 4429 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4430 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4431 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4432 .port_tag_remap = mv88e6390_port_tag_remap, 4433 .port_set_policy = mv88e6352_port_set_policy, 4434 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4435 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4436 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4437 .port_set_ether_type = mv88e6351_port_set_ether_type, 4438 .port_pause_limit = mv88e6390_port_pause_limit, 4439 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4440 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4441 .port_get_cmode = mv88e6352_port_get_cmode, 4442 .port_set_cmode = mv88e6390_port_set_cmode, 4443 .port_setup_message_port = mv88e6xxx_setup_message_port, 4444 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4445 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4446 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4447 .stats_get_strings = mv88e6320_stats_get_strings, 4448 .stats_get_stats = mv88e6390_stats_get_stats, 4449 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4450 .set_egress_port = mv88e6390_g1_set_egress_port, 4451 .watchdog_ops = &mv88e6390_watchdog_ops, 4452 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4453 .pot_clear = mv88e6xxx_g2_pot_clear, 4454 .reset = mv88e6352_g1_reset, 4455 .rmu_disable = mv88e6390_g1_rmu_disable, 4456 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4457 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4458 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4459 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4460 .serdes_power = mv88e6390_serdes_power, 4461 .serdes_get_lane = mv88e6390_serdes_get_lane, 4462 /* Check status register pause & lpa register */ 4463 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4464 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4465 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4466 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4467 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4468 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4469 .serdes_irq_status = mv88e6390_serdes_irq_status, 4470 .serdes_get_strings = mv88e6390_serdes_get_strings, 4471 .serdes_get_stats = mv88e6390_serdes_get_stats, 4472 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4473 .serdes_get_regs = mv88e6390_serdes_get_regs, 4474 .gpio_ops = &mv88e6352_gpio_ops, 4475 .avb_ops = &mv88e6390_avb_ops, 4476 .ptp_ops = &mv88e6352_ptp_ops, 4477 .phylink_validate = mv88e6390_phylink_validate, 4478 }; 4479 4480 static const struct mv88e6xxx_ops mv88e6320_ops = { 4481 /* MV88E6XXX_FAMILY_6320 */ 4482 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4483 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4484 .irl_init_all = mv88e6352_g2_irl_init_all, 4485 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4486 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4487 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4488 .phy_read = mv88e6xxx_g2_smi_phy_read, 4489 .phy_write = mv88e6xxx_g2_smi_phy_write, 4490 .port_set_link = mv88e6xxx_port_set_link, 4491 .port_sync_link = mv88e6xxx_port_sync_link, 4492 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4493 .port_tag_remap = mv88e6095_port_tag_remap, 4494 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4495 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4496 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4497 .port_set_ether_type = mv88e6351_port_set_ether_type, 4498 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4499 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4500 .port_pause_limit = mv88e6097_port_pause_limit, 4501 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4502 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4503 .port_get_cmode = mv88e6352_port_get_cmode, 4504 .port_setup_message_port = mv88e6xxx_setup_message_port, 4505 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4506 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4507 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4508 .stats_get_strings = mv88e6320_stats_get_strings, 4509 .stats_get_stats = mv88e6320_stats_get_stats, 4510 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4511 .set_egress_port = mv88e6095_g1_set_egress_port, 4512 .watchdog_ops = &mv88e6390_watchdog_ops, 4513 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4514 .pot_clear = mv88e6xxx_g2_pot_clear, 4515 .reset = mv88e6352_g1_reset, 4516 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4517 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4518 .gpio_ops = &mv88e6352_gpio_ops, 4519 .avb_ops = &mv88e6352_avb_ops, 4520 .ptp_ops = &mv88e6352_ptp_ops, 4521 .phylink_validate = mv88e6185_phylink_validate, 4522 }; 4523 4524 static const struct mv88e6xxx_ops mv88e6321_ops = { 4525 /* MV88E6XXX_FAMILY_6320 */ 4526 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4527 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4528 .irl_init_all = mv88e6352_g2_irl_init_all, 4529 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4530 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4531 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4532 .phy_read = mv88e6xxx_g2_smi_phy_read, 4533 .phy_write = mv88e6xxx_g2_smi_phy_write, 4534 .port_set_link = mv88e6xxx_port_set_link, 4535 .port_sync_link = mv88e6xxx_port_sync_link, 4536 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4537 .port_tag_remap = mv88e6095_port_tag_remap, 4538 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4539 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4540 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4541 .port_set_ether_type = mv88e6351_port_set_ether_type, 4542 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4543 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4544 .port_pause_limit = mv88e6097_port_pause_limit, 4545 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4546 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4547 .port_get_cmode = mv88e6352_port_get_cmode, 4548 .port_setup_message_port = mv88e6xxx_setup_message_port, 4549 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4550 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4551 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4552 .stats_get_strings = mv88e6320_stats_get_strings, 4553 .stats_get_stats = mv88e6320_stats_get_stats, 4554 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4555 .set_egress_port = mv88e6095_g1_set_egress_port, 4556 .watchdog_ops = &mv88e6390_watchdog_ops, 4557 .reset = mv88e6352_g1_reset, 4558 .vtu_getnext = mv88e6185_g1_vtu_getnext, 4559 .vtu_loadpurge = mv88e6185_g1_vtu_loadpurge, 4560 .gpio_ops = &mv88e6352_gpio_ops, 4561 .avb_ops = &mv88e6352_avb_ops, 4562 .ptp_ops = &mv88e6352_ptp_ops, 4563 .phylink_validate = mv88e6185_phylink_validate, 4564 }; 4565 4566 static const struct mv88e6xxx_ops mv88e6341_ops = { 4567 /* MV88E6XXX_FAMILY_6341 */ 4568 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4569 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4570 .irl_init_all = mv88e6352_g2_irl_init_all, 4571 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4572 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4573 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4574 .phy_read = mv88e6xxx_g2_smi_phy_read, 4575 .phy_write = mv88e6xxx_g2_smi_phy_write, 4576 .port_set_link = mv88e6xxx_port_set_link, 4577 .port_sync_link = mv88e6xxx_port_sync_link, 4578 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4579 .port_set_speed_duplex = mv88e6341_port_set_speed_duplex, 4580 .port_max_speed_mode = mv88e6341_port_max_speed_mode, 4581 .port_tag_remap = mv88e6095_port_tag_remap, 4582 .port_set_policy = mv88e6352_port_set_policy, 4583 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4584 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4585 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4586 .port_set_ether_type = mv88e6351_port_set_ether_type, 4587 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4588 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4589 .port_pause_limit = mv88e6097_port_pause_limit, 4590 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4591 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4592 .port_get_cmode = mv88e6352_port_get_cmode, 4593 .port_set_cmode = mv88e6341_port_set_cmode, 4594 .port_setup_message_port = mv88e6xxx_setup_message_port, 4595 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4596 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4597 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4598 .stats_get_strings = mv88e6320_stats_get_strings, 4599 .stats_get_stats = mv88e6390_stats_get_stats, 4600 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4601 .set_egress_port = mv88e6390_g1_set_egress_port, 4602 .watchdog_ops = &mv88e6390_watchdog_ops, 4603 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4604 .pot_clear = mv88e6xxx_g2_pot_clear, 4605 .reset = mv88e6352_g1_reset, 4606 .rmu_disable = mv88e6390_g1_rmu_disable, 4607 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4608 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4609 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4610 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4611 .serdes_power = mv88e6390_serdes_power, 4612 .serdes_get_lane = mv88e6341_serdes_get_lane, 4613 /* Check status register pause & lpa register */ 4614 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4615 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4616 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4617 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4618 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4619 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4620 .serdes_irq_status = mv88e6390_serdes_irq_status, 4621 .gpio_ops = &mv88e6352_gpio_ops, 4622 .avb_ops = &mv88e6390_avb_ops, 4623 .ptp_ops = &mv88e6352_ptp_ops, 4624 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4625 .serdes_get_strings = mv88e6390_serdes_get_strings, 4626 .serdes_get_stats = mv88e6390_serdes_get_stats, 4627 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4628 .serdes_get_regs = mv88e6390_serdes_get_regs, 4629 .phylink_validate = mv88e6341_phylink_validate, 4630 }; 4631 4632 static const struct mv88e6xxx_ops mv88e6350_ops = { 4633 /* MV88E6XXX_FAMILY_6351 */ 4634 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4635 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4636 .irl_init_all = mv88e6352_g2_irl_init_all, 4637 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4638 .phy_read = mv88e6xxx_g2_smi_phy_read, 4639 .phy_write = mv88e6xxx_g2_smi_phy_write, 4640 .port_set_link = mv88e6xxx_port_set_link, 4641 .port_sync_link = mv88e6xxx_port_sync_link, 4642 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4643 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4644 .port_tag_remap = mv88e6095_port_tag_remap, 4645 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4646 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4647 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4648 .port_set_ether_type = mv88e6351_port_set_ether_type, 4649 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4650 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4651 .port_pause_limit = mv88e6097_port_pause_limit, 4652 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4653 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4654 .port_get_cmode = mv88e6352_port_get_cmode, 4655 .port_setup_message_port = mv88e6xxx_setup_message_port, 4656 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4657 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4658 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4659 .stats_get_strings = mv88e6095_stats_get_strings, 4660 .stats_get_stats = mv88e6095_stats_get_stats, 4661 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4662 .set_egress_port = mv88e6095_g1_set_egress_port, 4663 .watchdog_ops = &mv88e6097_watchdog_ops, 4664 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4665 .pot_clear = mv88e6xxx_g2_pot_clear, 4666 .reset = mv88e6352_g1_reset, 4667 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4668 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4669 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4670 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4671 .phylink_validate = mv88e6185_phylink_validate, 4672 }; 4673 4674 static const struct mv88e6xxx_ops mv88e6351_ops = { 4675 /* MV88E6XXX_FAMILY_6351 */ 4676 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4677 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4678 .irl_init_all = mv88e6352_g2_irl_init_all, 4679 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4680 .phy_read = mv88e6xxx_g2_smi_phy_read, 4681 .phy_write = mv88e6xxx_g2_smi_phy_write, 4682 .port_set_link = mv88e6xxx_port_set_link, 4683 .port_sync_link = mv88e6xxx_port_sync_link, 4684 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4685 .port_set_speed_duplex = mv88e6185_port_set_speed_duplex, 4686 .port_tag_remap = mv88e6095_port_tag_remap, 4687 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4688 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4689 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4690 .port_set_ether_type = mv88e6351_port_set_ether_type, 4691 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4692 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4693 .port_pause_limit = mv88e6097_port_pause_limit, 4694 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4695 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4696 .port_get_cmode = mv88e6352_port_get_cmode, 4697 .port_setup_message_port = mv88e6xxx_setup_message_port, 4698 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4699 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4700 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4701 .stats_get_strings = mv88e6095_stats_get_strings, 4702 .stats_get_stats = mv88e6095_stats_get_stats, 4703 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4704 .set_egress_port = mv88e6095_g1_set_egress_port, 4705 .watchdog_ops = &mv88e6097_watchdog_ops, 4706 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4707 .pot_clear = mv88e6xxx_g2_pot_clear, 4708 .reset = mv88e6352_g1_reset, 4709 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4710 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4711 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4712 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4713 .avb_ops = &mv88e6352_avb_ops, 4714 .ptp_ops = &mv88e6352_ptp_ops, 4715 .phylink_validate = mv88e6185_phylink_validate, 4716 }; 4717 4718 static const struct mv88e6xxx_ops mv88e6352_ops = { 4719 /* MV88E6XXX_FAMILY_6352 */ 4720 .ieee_pri_map = mv88e6085_g1_ieee_pri_map, 4721 .ip_pri_map = mv88e6085_g1_ip_pri_map, 4722 .irl_init_all = mv88e6352_g2_irl_init_all, 4723 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 4724 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 4725 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4726 .phy_read = mv88e6xxx_g2_smi_phy_read, 4727 .phy_write = mv88e6xxx_g2_smi_phy_write, 4728 .port_set_link = mv88e6xxx_port_set_link, 4729 .port_sync_link = mv88e6xxx_port_sync_link, 4730 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 4731 .port_set_speed_duplex = mv88e6352_port_set_speed_duplex, 4732 .port_tag_remap = mv88e6095_port_tag_remap, 4733 .port_set_policy = mv88e6352_port_set_policy, 4734 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4735 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4736 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4737 .port_set_ether_type = mv88e6351_port_set_ether_type, 4738 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4739 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4740 .port_pause_limit = mv88e6097_port_pause_limit, 4741 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4742 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4743 .port_get_cmode = mv88e6352_port_get_cmode, 4744 .port_setup_message_port = mv88e6xxx_setup_message_port, 4745 .stats_snapshot = mv88e6320_g1_stats_snapshot, 4746 .stats_set_histogram = mv88e6095_g1_stats_set_histogram, 4747 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 4748 .stats_get_strings = mv88e6095_stats_get_strings, 4749 .stats_get_stats = mv88e6095_stats_get_stats, 4750 .set_cpu_port = mv88e6095_g1_set_cpu_port, 4751 .set_egress_port = mv88e6095_g1_set_egress_port, 4752 .watchdog_ops = &mv88e6097_watchdog_ops, 4753 .mgmt_rsvd2cpu = mv88e6352_g2_mgmt_rsvd2cpu, 4754 .pot_clear = mv88e6xxx_g2_pot_clear, 4755 .reset = mv88e6352_g1_reset, 4756 .rmu_disable = mv88e6352_g1_rmu_disable, 4757 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4758 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4759 .vtu_getnext = mv88e6352_g1_vtu_getnext, 4760 .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge, 4761 .serdes_get_lane = mv88e6352_serdes_get_lane, 4762 .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state, 4763 .serdes_pcs_config = mv88e6352_serdes_pcs_config, 4764 .serdes_pcs_an_restart = mv88e6352_serdes_pcs_an_restart, 4765 .serdes_pcs_link_up = mv88e6352_serdes_pcs_link_up, 4766 .serdes_power = mv88e6352_serdes_power, 4767 .serdes_irq_mapping = mv88e6352_serdes_irq_mapping, 4768 .serdes_irq_enable = mv88e6352_serdes_irq_enable, 4769 .serdes_irq_status = mv88e6352_serdes_irq_status, 4770 .gpio_ops = &mv88e6352_gpio_ops, 4771 .avb_ops = &mv88e6352_avb_ops, 4772 .ptp_ops = &mv88e6352_ptp_ops, 4773 .serdes_get_sset_count = mv88e6352_serdes_get_sset_count, 4774 .serdes_get_strings = mv88e6352_serdes_get_strings, 4775 .serdes_get_stats = mv88e6352_serdes_get_stats, 4776 .serdes_get_regs_len = mv88e6352_serdes_get_regs_len, 4777 .serdes_get_regs = mv88e6352_serdes_get_regs, 4778 .phylink_validate = mv88e6352_phylink_validate, 4779 }; 4780 4781 static const struct mv88e6xxx_ops mv88e6390_ops = { 4782 /* MV88E6XXX_FAMILY_6390 */ 4783 .setup_errata = mv88e6390_setup_errata, 4784 .irl_init_all = mv88e6390_g2_irl_init_all, 4785 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4786 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4787 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4788 .phy_read = mv88e6xxx_g2_smi_phy_read, 4789 .phy_write = mv88e6xxx_g2_smi_phy_write, 4790 .port_set_link = mv88e6xxx_port_set_link, 4791 .port_sync_link = mv88e6xxx_port_sync_link, 4792 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4793 .port_set_speed_duplex = mv88e6390_port_set_speed_duplex, 4794 .port_max_speed_mode = mv88e6390_port_max_speed_mode, 4795 .port_tag_remap = mv88e6390_port_tag_remap, 4796 .port_set_policy = mv88e6352_port_set_policy, 4797 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4798 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4799 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4800 .port_set_ether_type = mv88e6351_port_set_ether_type, 4801 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4802 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4803 .port_pause_limit = mv88e6390_port_pause_limit, 4804 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4805 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4806 .port_get_cmode = mv88e6352_port_get_cmode, 4807 .port_set_cmode = mv88e6390_port_set_cmode, 4808 .port_setup_message_port = mv88e6xxx_setup_message_port, 4809 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4810 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4811 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4812 .stats_get_strings = mv88e6320_stats_get_strings, 4813 .stats_get_stats = mv88e6390_stats_get_stats, 4814 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4815 .set_egress_port = mv88e6390_g1_set_egress_port, 4816 .watchdog_ops = &mv88e6390_watchdog_ops, 4817 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4818 .pot_clear = mv88e6xxx_g2_pot_clear, 4819 .reset = mv88e6352_g1_reset, 4820 .rmu_disable = mv88e6390_g1_rmu_disable, 4821 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4822 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4823 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4824 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4825 .serdes_power = mv88e6390_serdes_power, 4826 .serdes_get_lane = mv88e6390_serdes_get_lane, 4827 /* Check status register pause & lpa register */ 4828 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4829 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4830 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4831 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4832 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4833 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4834 .serdes_irq_status = mv88e6390_serdes_irq_status, 4835 .gpio_ops = &mv88e6352_gpio_ops, 4836 .avb_ops = &mv88e6390_avb_ops, 4837 .ptp_ops = &mv88e6352_ptp_ops, 4838 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4839 .serdes_get_strings = mv88e6390_serdes_get_strings, 4840 .serdes_get_stats = mv88e6390_serdes_get_stats, 4841 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4842 .serdes_get_regs = mv88e6390_serdes_get_regs, 4843 .phylink_validate = mv88e6390_phylink_validate, 4844 }; 4845 4846 static const struct mv88e6xxx_ops mv88e6390x_ops = { 4847 /* MV88E6XXX_FAMILY_6390 */ 4848 .setup_errata = mv88e6390_setup_errata, 4849 .irl_init_all = mv88e6390_g2_irl_init_all, 4850 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4851 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4852 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4853 .phy_read = mv88e6xxx_g2_smi_phy_read, 4854 .phy_write = mv88e6xxx_g2_smi_phy_write, 4855 .port_set_link = mv88e6xxx_port_set_link, 4856 .port_sync_link = mv88e6xxx_port_sync_link, 4857 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4858 .port_set_speed_duplex = mv88e6390x_port_set_speed_duplex, 4859 .port_max_speed_mode = mv88e6390x_port_max_speed_mode, 4860 .port_tag_remap = mv88e6390_port_tag_remap, 4861 .port_set_policy = mv88e6352_port_set_policy, 4862 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4863 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4864 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4865 .port_set_ether_type = mv88e6351_port_set_ether_type, 4866 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4867 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4868 .port_pause_limit = mv88e6390_port_pause_limit, 4869 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4870 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4871 .port_get_cmode = mv88e6352_port_get_cmode, 4872 .port_set_cmode = mv88e6390x_port_set_cmode, 4873 .port_setup_message_port = mv88e6xxx_setup_message_port, 4874 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4875 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4876 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4877 .stats_get_strings = mv88e6320_stats_get_strings, 4878 .stats_get_stats = mv88e6390_stats_get_stats, 4879 .set_cpu_port = mv88e6390_g1_set_cpu_port, 4880 .set_egress_port = mv88e6390_g1_set_egress_port, 4881 .watchdog_ops = &mv88e6390_watchdog_ops, 4882 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 4883 .pot_clear = mv88e6xxx_g2_pot_clear, 4884 .reset = mv88e6352_g1_reset, 4885 .rmu_disable = mv88e6390_g1_rmu_disable, 4886 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4887 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4888 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4889 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4890 .serdes_power = mv88e6390_serdes_power, 4891 .serdes_get_lane = mv88e6390x_serdes_get_lane, 4892 .serdes_pcs_get_state = mv88e6390_serdes_pcs_get_state, 4893 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4894 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4895 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4896 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4897 .serdes_irq_enable = mv88e6390_serdes_irq_enable, 4898 .serdes_irq_status = mv88e6390_serdes_irq_status, 4899 .serdes_get_sset_count = mv88e6390_serdes_get_sset_count, 4900 .serdes_get_strings = mv88e6390_serdes_get_strings, 4901 .serdes_get_stats = mv88e6390_serdes_get_stats, 4902 .serdes_get_regs_len = mv88e6390_serdes_get_regs_len, 4903 .serdes_get_regs = mv88e6390_serdes_get_regs, 4904 .gpio_ops = &mv88e6352_gpio_ops, 4905 .avb_ops = &mv88e6390_avb_ops, 4906 .ptp_ops = &mv88e6352_ptp_ops, 4907 .phylink_validate = mv88e6390x_phylink_validate, 4908 }; 4909 4910 static const struct mv88e6xxx_ops mv88e6393x_ops = { 4911 /* MV88E6XXX_FAMILY_6393 */ 4912 .setup_errata = mv88e6393x_serdes_setup_errata, 4913 .irl_init_all = mv88e6390_g2_irl_init_all, 4914 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 4915 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 4916 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 4917 .phy_read = mv88e6xxx_g2_smi_phy_read, 4918 .phy_write = mv88e6xxx_g2_smi_phy_write, 4919 .port_set_link = mv88e6xxx_port_set_link, 4920 .port_sync_link = mv88e6xxx_port_sync_link, 4921 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 4922 .port_set_speed_duplex = mv88e6393x_port_set_speed_duplex, 4923 .port_max_speed_mode = mv88e6393x_port_max_speed_mode, 4924 .port_tag_remap = mv88e6390_port_tag_remap, 4925 .port_set_policy = mv88e6393x_port_set_policy, 4926 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 4927 .port_set_ucast_flood = mv88e6352_port_set_ucast_flood, 4928 .port_set_mcast_flood = mv88e6352_port_set_mcast_flood, 4929 .port_set_ether_type = mv88e6393x_port_set_ether_type, 4930 .port_set_jumbo_size = mv88e6165_port_set_jumbo_size, 4931 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 4932 .port_pause_limit = mv88e6390_port_pause_limit, 4933 .port_disable_learn_limit = mv88e6xxx_port_disable_learn_limit, 4934 .port_disable_pri_override = mv88e6xxx_port_disable_pri_override, 4935 .port_get_cmode = mv88e6352_port_get_cmode, 4936 .port_set_cmode = mv88e6393x_port_set_cmode, 4937 .port_setup_message_port = mv88e6xxx_setup_message_port, 4938 .port_set_upstream_port = mv88e6393x_port_set_upstream_port, 4939 .stats_snapshot = mv88e6390_g1_stats_snapshot, 4940 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 4941 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 4942 .stats_get_strings = mv88e6320_stats_get_strings, 4943 .stats_get_stats = mv88e6390_stats_get_stats, 4944 /* .set_cpu_port is missing because this family does not support a global 4945 * CPU port, only per port CPU port which is set via 4946 * .port_set_upstream_port method. 4947 */ 4948 .set_egress_port = mv88e6393x_set_egress_port, 4949 .watchdog_ops = &mv88e6390_watchdog_ops, 4950 .mgmt_rsvd2cpu = mv88e6393x_port_mgmt_rsvd2cpu, 4951 .pot_clear = mv88e6xxx_g2_pot_clear, 4952 .reset = mv88e6352_g1_reset, 4953 .rmu_disable = mv88e6390_g1_rmu_disable, 4954 .atu_get_hash = mv88e6165_g1_atu_get_hash, 4955 .atu_set_hash = mv88e6165_g1_atu_set_hash, 4956 .vtu_getnext = mv88e6390_g1_vtu_getnext, 4957 .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge, 4958 .serdes_power = mv88e6393x_serdes_power, 4959 .serdes_get_lane = mv88e6393x_serdes_get_lane, 4960 .serdes_pcs_get_state = mv88e6393x_serdes_pcs_get_state, 4961 .serdes_pcs_config = mv88e6390_serdes_pcs_config, 4962 .serdes_pcs_an_restart = mv88e6390_serdes_pcs_an_restart, 4963 .serdes_pcs_link_up = mv88e6390_serdes_pcs_link_up, 4964 .serdes_irq_mapping = mv88e6390_serdes_irq_mapping, 4965 .serdes_irq_enable = mv88e6393x_serdes_irq_enable, 4966 .serdes_irq_status = mv88e6393x_serdes_irq_status, 4967 /* TODO: serdes stats */ 4968 .gpio_ops = &mv88e6352_gpio_ops, 4969 .avb_ops = &mv88e6390_avb_ops, 4970 .ptp_ops = &mv88e6352_ptp_ops, 4971 .phylink_validate = mv88e6393x_phylink_validate, 4972 }; 4973 4974 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 4975 [MV88E6085] = { 4976 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6085, 4977 .family = MV88E6XXX_FAMILY_6097, 4978 .name = "Marvell 88E6085", 4979 .num_databases = 4096, 4980 .num_macs = 8192, 4981 .num_ports = 10, 4982 .num_internal_phys = 5, 4983 .max_vid = 4095, 4984 .port_base_addr = 0x10, 4985 .phy_base_addr = 0x0, 4986 .global1_addr = 0x1b, 4987 .global2_addr = 0x1c, 4988 .age_time_coeff = 15000, 4989 .g1_irqs = 8, 4990 .g2_irqs = 10, 4991 .atu_move_port_mask = 0xf, 4992 .pvt = true, 4993 .multi_chip = true, 4994 .ops = &mv88e6085_ops, 4995 }, 4996 4997 [MV88E6095] = { 4998 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6095, 4999 .family = MV88E6XXX_FAMILY_6095, 5000 .name = "Marvell 88E6095/88E6095F", 5001 .num_databases = 256, 5002 .num_macs = 8192, 5003 .num_ports = 11, 5004 .num_internal_phys = 0, 5005 .max_vid = 4095, 5006 .port_base_addr = 0x10, 5007 .phy_base_addr = 0x0, 5008 .global1_addr = 0x1b, 5009 .global2_addr = 0x1c, 5010 .age_time_coeff = 15000, 5011 .g1_irqs = 8, 5012 .atu_move_port_mask = 0xf, 5013 .multi_chip = true, 5014 .ops = &mv88e6095_ops, 5015 }, 5016 5017 [MV88E6097] = { 5018 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6097, 5019 .family = MV88E6XXX_FAMILY_6097, 5020 .name = "Marvell 88E6097/88E6097F", 5021 .num_databases = 4096, 5022 .num_macs = 8192, 5023 .num_ports = 11, 5024 .num_internal_phys = 8, 5025 .max_vid = 4095, 5026 .port_base_addr = 0x10, 5027 .phy_base_addr = 0x0, 5028 .global1_addr = 0x1b, 5029 .global2_addr = 0x1c, 5030 .age_time_coeff = 15000, 5031 .g1_irqs = 8, 5032 .g2_irqs = 10, 5033 .atu_move_port_mask = 0xf, 5034 .pvt = true, 5035 .multi_chip = true, 5036 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5037 .ops = &mv88e6097_ops, 5038 }, 5039 5040 [MV88E6123] = { 5041 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6123, 5042 .family = MV88E6XXX_FAMILY_6165, 5043 .name = "Marvell 88E6123", 5044 .num_databases = 4096, 5045 .num_macs = 1024, 5046 .num_ports = 3, 5047 .num_internal_phys = 5, 5048 .max_vid = 4095, 5049 .port_base_addr = 0x10, 5050 .phy_base_addr = 0x0, 5051 .global1_addr = 0x1b, 5052 .global2_addr = 0x1c, 5053 .age_time_coeff = 15000, 5054 .g1_irqs = 9, 5055 .g2_irqs = 10, 5056 .atu_move_port_mask = 0xf, 5057 .pvt = true, 5058 .multi_chip = true, 5059 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5060 .ops = &mv88e6123_ops, 5061 }, 5062 5063 [MV88E6131] = { 5064 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6131, 5065 .family = MV88E6XXX_FAMILY_6185, 5066 .name = "Marvell 88E6131", 5067 .num_databases = 256, 5068 .num_macs = 8192, 5069 .num_ports = 8, 5070 .num_internal_phys = 0, 5071 .max_vid = 4095, 5072 .port_base_addr = 0x10, 5073 .phy_base_addr = 0x0, 5074 .global1_addr = 0x1b, 5075 .global2_addr = 0x1c, 5076 .age_time_coeff = 15000, 5077 .g1_irqs = 9, 5078 .atu_move_port_mask = 0xf, 5079 .multi_chip = true, 5080 .ops = &mv88e6131_ops, 5081 }, 5082 5083 [MV88E6141] = { 5084 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6141, 5085 .family = MV88E6XXX_FAMILY_6341, 5086 .name = "Marvell 88E6141", 5087 .num_databases = 4096, 5088 .num_macs = 2048, 5089 .num_ports = 6, 5090 .num_internal_phys = 5, 5091 .num_gpio = 11, 5092 .max_vid = 4095, 5093 .port_base_addr = 0x10, 5094 .phy_base_addr = 0x10, 5095 .global1_addr = 0x1b, 5096 .global2_addr = 0x1c, 5097 .age_time_coeff = 3750, 5098 .atu_move_port_mask = 0x1f, 5099 .g1_irqs = 9, 5100 .g2_irqs = 10, 5101 .pvt = true, 5102 .multi_chip = true, 5103 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5104 .ops = &mv88e6141_ops, 5105 }, 5106 5107 [MV88E6161] = { 5108 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6161, 5109 .family = MV88E6XXX_FAMILY_6165, 5110 .name = "Marvell 88E6161", 5111 .num_databases = 4096, 5112 .num_macs = 1024, 5113 .num_ports = 6, 5114 .num_internal_phys = 5, 5115 .max_vid = 4095, 5116 .port_base_addr = 0x10, 5117 .phy_base_addr = 0x0, 5118 .global1_addr = 0x1b, 5119 .global2_addr = 0x1c, 5120 .age_time_coeff = 15000, 5121 .g1_irqs = 9, 5122 .g2_irqs = 10, 5123 .atu_move_port_mask = 0xf, 5124 .pvt = true, 5125 .multi_chip = true, 5126 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5127 .ptp_support = true, 5128 .ops = &mv88e6161_ops, 5129 }, 5130 5131 [MV88E6165] = { 5132 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6165, 5133 .family = MV88E6XXX_FAMILY_6165, 5134 .name = "Marvell 88E6165", 5135 .num_databases = 4096, 5136 .num_macs = 8192, 5137 .num_ports = 6, 5138 .num_internal_phys = 0, 5139 .max_vid = 4095, 5140 .port_base_addr = 0x10, 5141 .phy_base_addr = 0x0, 5142 .global1_addr = 0x1b, 5143 .global2_addr = 0x1c, 5144 .age_time_coeff = 15000, 5145 .g1_irqs = 9, 5146 .g2_irqs = 10, 5147 .atu_move_port_mask = 0xf, 5148 .pvt = true, 5149 .multi_chip = true, 5150 .ptp_support = true, 5151 .ops = &mv88e6165_ops, 5152 }, 5153 5154 [MV88E6171] = { 5155 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6171, 5156 .family = MV88E6XXX_FAMILY_6351, 5157 .name = "Marvell 88E6171", 5158 .num_databases = 4096, 5159 .num_macs = 8192, 5160 .num_ports = 7, 5161 .num_internal_phys = 5, 5162 .max_vid = 4095, 5163 .port_base_addr = 0x10, 5164 .phy_base_addr = 0x0, 5165 .global1_addr = 0x1b, 5166 .global2_addr = 0x1c, 5167 .age_time_coeff = 15000, 5168 .g1_irqs = 9, 5169 .g2_irqs = 10, 5170 .atu_move_port_mask = 0xf, 5171 .pvt = true, 5172 .multi_chip = true, 5173 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5174 .ops = &mv88e6171_ops, 5175 }, 5176 5177 [MV88E6172] = { 5178 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6172, 5179 .family = MV88E6XXX_FAMILY_6352, 5180 .name = "Marvell 88E6172", 5181 .num_databases = 4096, 5182 .num_macs = 8192, 5183 .num_ports = 7, 5184 .num_internal_phys = 5, 5185 .num_gpio = 15, 5186 .max_vid = 4095, 5187 .port_base_addr = 0x10, 5188 .phy_base_addr = 0x0, 5189 .global1_addr = 0x1b, 5190 .global2_addr = 0x1c, 5191 .age_time_coeff = 15000, 5192 .g1_irqs = 9, 5193 .g2_irqs = 10, 5194 .atu_move_port_mask = 0xf, 5195 .pvt = true, 5196 .multi_chip = true, 5197 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5198 .ops = &mv88e6172_ops, 5199 }, 5200 5201 [MV88E6175] = { 5202 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6175, 5203 .family = MV88E6XXX_FAMILY_6351, 5204 .name = "Marvell 88E6175", 5205 .num_databases = 4096, 5206 .num_macs = 8192, 5207 .num_ports = 7, 5208 .num_internal_phys = 5, 5209 .max_vid = 4095, 5210 .port_base_addr = 0x10, 5211 .phy_base_addr = 0x0, 5212 .global1_addr = 0x1b, 5213 .global2_addr = 0x1c, 5214 .age_time_coeff = 15000, 5215 .g1_irqs = 9, 5216 .g2_irqs = 10, 5217 .atu_move_port_mask = 0xf, 5218 .pvt = true, 5219 .multi_chip = true, 5220 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5221 .ops = &mv88e6175_ops, 5222 }, 5223 5224 [MV88E6176] = { 5225 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6176, 5226 .family = MV88E6XXX_FAMILY_6352, 5227 .name = "Marvell 88E6176", 5228 .num_databases = 4096, 5229 .num_macs = 8192, 5230 .num_ports = 7, 5231 .num_internal_phys = 5, 5232 .num_gpio = 15, 5233 .max_vid = 4095, 5234 .port_base_addr = 0x10, 5235 .phy_base_addr = 0x0, 5236 .global1_addr = 0x1b, 5237 .global2_addr = 0x1c, 5238 .age_time_coeff = 15000, 5239 .g1_irqs = 9, 5240 .g2_irqs = 10, 5241 .atu_move_port_mask = 0xf, 5242 .pvt = true, 5243 .multi_chip = true, 5244 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5245 .ops = &mv88e6176_ops, 5246 }, 5247 5248 [MV88E6185] = { 5249 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6185, 5250 .family = MV88E6XXX_FAMILY_6185, 5251 .name = "Marvell 88E6185", 5252 .num_databases = 256, 5253 .num_macs = 8192, 5254 .num_ports = 10, 5255 .num_internal_phys = 0, 5256 .max_vid = 4095, 5257 .port_base_addr = 0x10, 5258 .phy_base_addr = 0x0, 5259 .global1_addr = 0x1b, 5260 .global2_addr = 0x1c, 5261 .age_time_coeff = 15000, 5262 .g1_irqs = 8, 5263 .atu_move_port_mask = 0xf, 5264 .multi_chip = true, 5265 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5266 .ops = &mv88e6185_ops, 5267 }, 5268 5269 [MV88E6190] = { 5270 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190, 5271 .family = MV88E6XXX_FAMILY_6390, 5272 .name = "Marvell 88E6190", 5273 .num_databases = 4096, 5274 .num_macs = 16384, 5275 .num_ports = 11, /* 10 + Z80 */ 5276 .num_internal_phys = 9, 5277 .num_gpio = 16, 5278 .max_vid = 8191, 5279 .port_base_addr = 0x0, 5280 .phy_base_addr = 0x0, 5281 .global1_addr = 0x1b, 5282 .global2_addr = 0x1c, 5283 .age_time_coeff = 3750, 5284 .g1_irqs = 9, 5285 .g2_irqs = 14, 5286 .pvt = true, 5287 .multi_chip = true, 5288 .atu_move_port_mask = 0x1f, 5289 .ops = &mv88e6190_ops, 5290 }, 5291 5292 [MV88E6190X] = { 5293 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6190X, 5294 .family = MV88E6XXX_FAMILY_6390, 5295 .name = "Marvell 88E6190X", 5296 .num_databases = 4096, 5297 .num_macs = 16384, 5298 .num_ports = 11, /* 10 + Z80 */ 5299 .num_internal_phys = 9, 5300 .num_gpio = 16, 5301 .max_vid = 8191, 5302 .port_base_addr = 0x0, 5303 .phy_base_addr = 0x0, 5304 .global1_addr = 0x1b, 5305 .global2_addr = 0x1c, 5306 .age_time_coeff = 3750, 5307 .g1_irqs = 9, 5308 .g2_irqs = 14, 5309 .atu_move_port_mask = 0x1f, 5310 .pvt = true, 5311 .multi_chip = true, 5312 .ops = &mv88e6190x_ops, 5313 }, 5314 5315 [MV88E6191] = { 5316 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191, 5317 .family = MV88E6XXX_FAMILY_6390, 5318 .name = "Marvell 88E6191", 5319 .num_databases = 4096, 5320 .num_macs = 16384, 5321 .num_ports = 11, /* 10 + Z80 */ 5322 .num_internal_phys = 9, 5323 .max_vid = 8191, 5324 .port_base_addr = 0x0, 5325 .phy_base_addr = 0x0, 5326 .global1_addr = 0x1b, 5327 .global2_addr = 0x1c, 5328 .age_time_coeff = 3750, 5329 .g1_irqs = 9, 5330 .g2_irqs = 14, 5331 .atu_move_port_mask = 0x1f, 5332 .pvt = true, 5333 .multi_chip = true, 5334 .ptp_support = true, 5335 .ops = &mv88e6191_ops, 5336 }, 5337 5338 [MV88E6191X] = { 5339 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6191X, 5340 .family = MV88E6XXX_FAMILY_6393, 5341 .name = "Marvell 88E6191X", 5342 .num_databases = 4096, 5343 .num_ports = 11, /* 10 + Z80 */ 5344 .num_internal_phys = 9, 5345 .max_vid = 8191, 5346 .port_base_addr = 0x0, 5347 .phy_base_addr = 0x0, 5348 .global1_addr = 0x1b, 5349 .global2_addr = 0x1c, 5350 .age_time_coeff = 3750, 5351 .g1_irqs = 10, 5352 .g2_irqs = 14, 5353 .atu_move_port_mask = 0x1f, 5354 .pvt = true, 5355 .multi_chip = true, 5356 .ptp_support = true, 5357 .ops = &mv88e6393x_ops, 5358 }, 5359 5360 [MV88E6193X] = { 5361 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6193X, 5362 .family = MV88E6XXX_FAMILY_6393, 5363 .name = "Marvell 88E6193X", 5364 .num_databases = 4096, 5365 .num_ports = 11, /* 10 + Z80 */ 5366 .num_internal_phys = 9, 5367 .max_vid = 8191, 5368 .port_base_addr = 0x0, 5369 .phy_base_addr = 0x0, 5370 .global1_addr = 0x1b, 5371 .global2_addr = 0x1c, 5372 .age_time_coeff = 3750, 5373 .g1_irqs = 10, 5374 .g2_irqs = 14, 5375 .atu_move_port_mask = 0x1f, 5376 .pvt = true, 5377 .multi_chip = true, 5378 .ptp_support = true, 5379 .ops = &mv88e6393x_ops, 5380 }, 5381 5382 [MV88E6220] = { 5383 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6220, 5384 .family = MV88E6XXX_FAMILY_6250, 5385 .name = "Marvell 88E6220", 5386 .num_databases = 64, 5387 5388 /* Ports 2-4 are not routed to pins 5389 * => usable ports 0, 1, 5, 6 5390 */ 5391 .num_ports = 7, 5392 .num_internal_phys = 2, 5393 .invalid_port_mask = BIT(2) | BIT(3) | BIT(4), 5394 .max_vid = 4095, 5395 .port_base_addr = 0x08, 5396 .phy_base_addr = 0x00, 5397 .global1_addr = 0x0f, 5398 .global2_addr = 0x07, 5399 .age_time_coeff = 15000, 5400 .g1_irqs = 9, 5401 .g2_irqs = 10, 5402 .atu_move_port_mask = 0xf, 5403 .dual_chip = true, 5404 .ptp_support = true, 5405 .ops = &mv88e6250_ops, 5406 }, 5407 5408 [MV88E6240] = { 5409 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6240, 5410 .family = MV88E6XXX_FAMILY_6352, 5411 .name = "Marvell 88E6240", 5412 .num_databases = 4096, 5413 .num_macs = 8192, 5414 .num_ports = 7, 5415 .num_internal_phys = 5, 5416 .num_gpio = 15, 5417 .max_vid = 4095, 5418 .port_base_addr = 0x10, 5419 .phy_base_addr = 0x0, 5420 .global1_addr = 0x1b, 5421 .global2_addr = 0x1c, 5422 .age_time_coeff = 15000, 5423 .g1_irqs = 9, 5424 .g2_irqs = 10, 5425 .atu_move_port_mask = 0xf, 5426 .pvt = true, 5427 .multi_chip = true, 5428 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5429 .ptp_support = true, 5430 .ops = &mv88e6240_ops, 5431 }, 5432 5433 [MV88E6250] = { 5434 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6250, 5435 .family = MV88E6XXX_FAMILY_6250, 5436 .name = "Marvell 88E6250", 5437 .num_databases = 64, 5438 .num_ports = 7, 5439 .num_internal_phys = 5, 5440 .max_vid = 4095, 5441 .port_base_addr = 0x08, 5442 .phy_base_addr = 0x00, 5443 .global1_addr = 0x0f, 5444 .global2_addr = 0x07, 5445 .age_time_coeff = 15000, 5446 .g1_irqs = 9, 5447 .g2_irqs = 10, 5448 .atu_move_port_mask = 0xf, 5449 .dual_chip = true, 5450 .ptp_support = true, 5451 .ops = &mv88e6250_ops, 5452 }, 5453 5454 [MV88E6290] = { 5455 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6290, 5456 .family = MV88E6XXX_FAMILY_6390, 5457 .name = "Marvell 88E6290", 5458 .num_databases = 4096, 5459 .num_ports = 11, /* 10 + Z80 */ 5460 .num_internal_phys = 9, 5461 .num_gpio = 16, 5462 .max_vid = 8191, 5463 .port_base_addr = 0x0, 5464 .phy_base_addr = 0x0, 5465 .global1_addr = 0x1b, 5466 .global2_addr = 0x1c, 5467 .age_time_coeff = 3750, 5468 .g1_irqs = 9, 5469 .g2_irqs = 14, 5470 .atu_move_port_mask = 0x1f, 5471 .pvt = true, 5472 .multi_chip = true, 5473 .ptp_support = true, 5474 .ops = &mv88e6290_ops, 5475 }, 5476 5477 [MV88E6320] = { 5478 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6320, 5479 .family = MV88E6XXX_FAMILY_6320, 5480 .name = "Marvell 88E6320", 5481 .num_databases = 4096, 5482 .num_macs = 8192, 5483 .num_ports = 7, 5484 .num_internal_phys = 5, 5485 .num_gpio = 15, 5486 .max_vid = 4095, 5487 .port_base_addr = 0x10, 5488 .phy_base_addr = 0x0, 5489 .global1_addr = 0x1b, 5490 .global2_addr = 0x1c, 5491 .age_time_coeff = 15000, 5492 .g1_irqs = 8, 5493 .g2_irqs = 10, 5494 .atu_move_port_mask = 0xf, 5495 .pvt = true, 5496 .multi_chip = true, 5497 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5498 .ptp_support = true, 5499 .ops = &mv88e6320_ops, 5500 }, 5501 5502 [MV88E6321] = { 5503 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6321, 5504 .family = MV88E6XXX_FAMILY_6320, 5505 .name = "Marvell 88E6321", 5506 .num_databases = 4096, 5507 .num_macs = 8192, 5508 .num_ports = 7, 5509 .num_internal_phys = 5, 5510 .num_gpio = 15, 5511 .max_vid = 4095, 5512 .port_base_addr = 0x10, 5513 .phy_base_addr = 0x0, 5514 .global1_addr = 0x1b, 5515 .global2_addr = 0x1c, 5516 .age_time_coeff = 15000, 5517 .g1_irqs = 8, 5518 .g2_irqs = 10, 5519 .atu_move_port_mask = 0xf, 5520 .multi_chip = true, 5521 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5522 .ptp_support = true, 5523 .ops = &mv88e6321_ops, 5524 }, 5525 5526 [MV88E6341] = { 5527 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6341, 5528 .family = MV88E6XXX_FAMILY_6341, 5529 .name = "Marvell 88E6341", 5530 .num_databases = 4096, 5531 .num_macs = 2048, 5532 .num_internal_phys = 5, 5533 .num_ports = 6, 5534 .num_gpio = 11, 5535 .max_vid = 4095, 5536 .port_base_addr = 0x10, 5537 .phy_base_addr = 0x10, 5538 .global1_addr = 0x1b, 5539 .global2_addr = 0x1c, 5540 .age_time_coeff = 3750, 5541 .atu_move_port_mask = 0x1f, 5542 .g1_irqs = 9, 5543 .g2_irqs = 10, 5544 .pvt = true, 5545 .multi_chip = true, 5546 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5547 .ptp_support = true, 5548 .ops = &mv88e6341_ops, 5549 }, 5550 5551 [MV88E6350] = { 5552 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6350, 5553 .family = MV88E6XXX_FAMILY_6351, 5554 .name = "Marvell 88E6350", 5555 .num_databases = 4096, 5556 .num_macs = 8192, 5557 .num_ports = 7, 5558 .num_internal_phys = 5, 5559 .max_vid = 4095, 5560 .port_base_addr = 0x10, 5561 .phy_base_addr = 0x0, 5562 .global1_addr = 0x1b, 5563 .global2_addr = 0x1c, 5564 .age_time_coeff = 15000, 5565 .g1_irqs = 9, 5566 .g2_irqs = 10, 5567 .atu_move_port_mask = 0xf, 5568 .pvt = true, 5569 .multi_chip = true, 5570 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5571 .ops = &mv88e6350_ops, 5572 }, 5573 5574 [MV88E6351] = { 5575 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6351, 5576 .family = MV88E6XXX_FAMILY_6351, 5577 .name = "Marvell 88E6351", 5578 .num_databases = 4096, 5579 .num_macs = 8192, 5580 .num_ports = 7, 5581 .num_internal_phys = 5, 5582 .max_vid = 4095, 5583 .port_base_addr = 0x10, 5584 .phy_base_addr = 0x0, 5585 .global1_addr = 0x1b, 5586 .global2_addr = 0x1c, 5587 .age_time_coeff = 15000, 5588 .g1_irqs = 9, 5589 .g2_irqs = 10, 5590 .atu_move_port_mask = 0xf, 5591 .pvt = true, 5592 .multi_chip = true, 5593 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5594 .ops = &mv88e6351_ops, 5595 }, 5596 5597 [MV88E6352] = { 5598 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6352, 5599 .family = MV88E6XXX_FAMILY_6352, 5600 .name = "Marvell 88E6352", 5601 .num_databases = 4096, 5602 .num_macs = 8192, 5603 .num_ports = 7, 5604 .num_internal_phys = 5, 5605 .num_gpio = 15, 5606 .max_vid = 4095, 5607 .port_base_addr = 0x10, 5608 .phy_base_addr = 0x0, 5609 .global1_addr = 0x1b, 5610 .global2_addr = 0x1c, 5611 .age_time_coeff = 15000, 5612 .g1_irqs = 9, 5613 .g2_irqs = 10, 5614 .atu_move_port_mask = 0xf, 5615 .pvt = true, 5616 .multi_chip = true, 5617 .edsa_support = MV88E6XXX_EDSA_SUPPORTED, 5618 .ptp_support = true, 5619 .ops = &mv88e6352_ops, 5620 }, 5621 [MV88E6390] = { 5622 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390, 5623 .family = MV88E6XXX_FAMILY_6390, 5624 .name = "Marvell 88E6390", 5625 .num_databases = 4096, 5626 .num_macs = 16384, 5627 .num_ports = 11, /* 10 + Z80 */ 5628 .num_internal_phys = 9, 5629 .num_gpio = 16, 5630 .max_vid = 8191, 5631 .port_base_addr = 0x0, 5632 .phy_base_addr = 0x0, 5633 .global1_addr = 0x1b, 5634 .global2_addr = 0x1c, 5635 .age_time_coeff = 3750, 5636 .g1_irqs = 9, 5637 .g2_irqs = 14, 5638 .atu_move_port_mask = 0x1f, 5639 .pvt = true, 5640 .multi_chip = true, 5641 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5642 .ptp_support = true, 5643 .ops = &mv88e6390_ops, 5644 }, 5645 [MV88E6390X] = { 5646 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6390X, 5647 .family = MV88E6XXX_FAMILY_6390, 5648 .name = "Marvell 88E6390X", 5649 .num_databases = 4096, 5650 .num_macs = 16384, 5651 .num_ports = 11, /* 10 + Z80 */ 5652 .num_internal_phys = 9, 5653 .num_gpio = 16, 5654 .max_vid = 8191, 5655 .port_base_addr = 0x0, 5656 .phy_base_addr = 0x0, 5657 .global1_addr = 0x1b, 5658 .global2_addr = 0x1c, 5659 .age_time_coeff = 3750, 5660 .g1_irqs = 9, 5661 .g2_irqs = 14, 5662 .atu_move_port_mask = 0x1f, 5663 .pvt = true, 5664 .multi_chip = true, 5665 .edsa_support = MV88E6XXX_EDSA_UNDOCUMENTED, 5666 .ptp_support = true, 5667 .ops = &mv88e6390x_ops, 5668 }, 5669 5670 [MV88E6393X] = { 5671 .prod_num = MV88E6XXX_PORT_SWITCH_ID_PROD_6393X, 5672 .family = MV88E6XXX_FAMILY_6393, 5673 .name = "Marvell 88E6393X", 5674 .num_databases = 4096, 5675 .num_ports = 11, /* 10 + Z80 */ 5676 .num_internal_phys = 9, 5677 .max_vid = 8191, 5678 .port_base_addr = 0x0, 5679 .phy_base_addr = 0x0, 5680 .global1_addr = 0x1b, 5681 .global2_addr = 0x1c, 5682 .age_time_coeff = 3750, 5683 .g1_irqs = 10, 5684 .g2_irqs = 14, 5685 .atu_move_port_mask = 0x1f, 5686 .pvt = true, 5687 .multi_chip = true, 5688 .ptp_support = true, 5689 .ops = &mv88e6393x_ops, 5690 }, 5691 }; 5692 5693 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 5694 { 5695 int i; 5696 5697 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 5698 if (mv88e6xxx_table[i].prod_num == prod_num) 5699 return &mv88e6xxx_table[i]; 5700 5701 return NULL; 5702 } 5703 5704 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 5705 { 5706 const struct mv88e6xxx_info *info; 5707 unsigned int prod_num, rev; 5708 u16 id; 5709 int err; 5710 5711 mv88e6xxx_reg_lock(chip); 5712 err = mv88e6xxx_port_read(chip, 0, MV88E6XXX_PORT_SWITCH_ID, &id); 5713 mv88e6xxx_reg_unlock(chip); 5714 if (err) 5715 return err; 5716 5717 prod_num = id & MV88E6XXX_PORT_SWITCH_ID_PROD_MASK; 5718 rev = id & MV88E6XXX_PORT_SWITCH_ID_REV_MASK; 5719 5720 info = mv88e6xxx_lookup_info(prod_num); 5721 if (!info) 5722 return -ENODEV; 5723 5724 /* Update the compatible info with the probed one */ 5725 chip->info = info; 5726 5727 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 5728 chip->info->prod_num, chip->info->name, rev); 5729 5730 return 0; 5731 } 5732 5733 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 5734 { 5735 struct mv88e6xxx_chip *chip; 5736 5737 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 5738 if (!chip) 5739 return NULL; 5740 5741 chip->dev = dev; 5742 5743 mutex_init(&chip->reg_lock); 5744 INIT_LIST_HEAD(&chip->mdios); 5745 idr_init(&chip->policies); 5746 5747 return chip; 5748 } 5749 5750 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds, 5751 int port, 5752 enum dsa_tag_protocol m) 5753 { 5754 struct mv88e6xxx_chip *chip = ds->priv; 5755 5756 return chip->tag_protocol; 5757 } 5758 5759 static int mv88e6xxx_change_tag_protocol(struct dsa_switch *ds, int port, 5760 enum dsa_tag_protocol proto) 5761 { 5762 struct mv88e6xxx_chip *chip = ds->priv; 5763 enum dsa_tag_protocol old_protocol; 5764 int err; 5765 5766 switch (proto) { 5767 case DSA_TAG_PROTO_EDSA: 5768 switch (chip->info->edsa_support) { 5769 case MV88E6XXX_EDSA_UNSUPPORTED: 5770 return -EPROTONOSUPPORT; 5771 case MV88E6XXX_EDSA_UNDOCUMENTED: 5772 dev_warn(chip->dev, "Relying on undocumented EDSA tagging behavior\n"); 5773 fallthrough; 5774 case MV88E6XXX_EDSA_SUPPORTED: 5775 break; 5776 } 5777 break; 5778 case DSA_TAG_PROTO_DSA: 5779 break; 5780 default: 5781 return -EPROTONOSUPPORT; 5782 } 5783 5784 old_protocol = chip->tag_protocol; 5785 chip->tag_protocol = proto; 5786 5787 mv88e6xxx_reg_lock(chip); 5788 err = mv88e6xxx_setup_port_mode(chip, port); 5789 mv88e6xxx_reg_unlock(chip); 5790 5791 if (err) 5792 chip->tag_protocol = old_protocol; 5793 5794 return err; 5795 } 5796 5797 static int mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 5798 const struct switchdev_obj_port_mdb *mdb) 5799 { 5800 struct mv88e6xxx_chip *chip = ds->priv; 5801 int err; 5802 5803 mv88e6xxx_reg_lock(chip); 5804 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 5805 MV88E6XXX_G1_ATU_DATA_STATE_MC_STATIC); 5806 mv88e6xxx_reg_unlock(chip); 5807 5808 return err; 5809 } 5810 5811 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 5812 const struct switchdev_obj_port_mdb *mdb) 5813 { 5814 struct mv88e6xxx_chip *chip = ds->priv; 5815 int err; 5816 5817 mv88e6xxx_reg_lock(chip); 5818 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 0); 5819 mv88e6xxx_reg_unlock(chip); 5820 5821 return err; 5822 } 5823 5824 static int mv88e6xxx_port_mirror_add(struct dsa_switch *ds, int port, 5825 struct dsa_mall_mirror_tc_entry *mirror, 5826 bool ingress) 5827 { 5828 enum mv88e6xxx_egress_direction direction = ingress ? 5829 MV88E6XXX_EGRESS_DIR_INGRESS : 5830 MV88E6XXX_EGRESS_DIR_EGRESS; 5831 struct mv88e6xxx_chip *chip = ds->priv; 5832 bool other_mirrors = false; 5833 int i; 5834 int err; 5835 5836 mutex_lock(&chip->reg_lock); 5837 if ((ingress ? chip->ingress_dest_port : chip->egress_dest_port) != 5838 mirror->to_local_port) { 5839 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5840 other_mirrors |= ingress ? 5841 chip->ports[i].mirror_ingress : 5842 chip->ports[i].mirror_egress; 5843 5844 /* Can't change egress port when other mirror is active */ 5845 if (other_mirrors) { 5846 err = -EBUSY; 5847 goto out; 5848 } 5849 5850 err = mv88e6xxx_set_egress_port(chip, direction, 5851 mirror->to_local_port); 5852 if (err) 5853 goto out; 5854 } 5855 5856 err = mv88e6xxx_port_set_mirror(chip, port, direction, true); 5857 out: 5858 mutex_unlock(&chip->reg_lock); 5859 5860 return err; 5861 } 5862 5863 static void mv88e6xxx_port_mirror_del(struct dsa_switch *ds, int port, 5864 struct dsa_mall_mirror_tc_entry *mirror) 5865 { 5866 enum mv88e6xxx_egress_direction direction = mirror->ingress ? 5867 MV88E6XXX_EGRESS_DIR_INGRESS : 5868 MV88E6XXX_EGRESS_DIR_EGRESS; 5869 struct mv88e6xxx_chip *chip = ds->priv; 5870 bool other_mirrors = false; 5871 int i; 5872 5873 mutex_lock(&chip->reg_lock); 5874 if (mv88e6xxx_port_set_mirror(chip, port, direction, false)) 5875 dev_err(ds->dev, "p%d: failed to disable mirroring\n", port); 5876 5877 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) 5878 other_mirrors |= mirror->ingress ? 5879 chip->ports[i].mirror_ingress : 5880 chip->ports[i].mirror_egress; 5881 5882 /* Reset egress port when no other mirror is active */ 5883 if (!other_mirrors) { 5884 if (mv88e6xxx_set_egress_port(chip, direction, 5885 dsa_upstream_port(ds, port))) 5886 dev_err(ds->dev, "failed to set egress port\n"); 5887 } 5888 5889 mutex_unlock(&chip->reg_lock); 5890 } 5891 5892 static int mv88e6xxx_port_pre_bridge_flags(struct dsa_switch *ds, int port, 5893 struct switchdev_brport_flags flags, 5894 struct netlink_ext_ack *extack) 5895 { 5896 struct mv88e6xxx_chip *chip = ds->priv; 5897 const struct mv88e6xxx_ops *ops; 5898 5899 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 5900 BR_BCAST_FLOOD)) 5901 return -EINVAL; 5902 5903 ops = chip->info->ops; 5904 5905 if ((flags.mask & BR_FLOOD) && !ops->port_set_ucast_flood) 5906 return -EINVAL; 5907 5908 if ((flags.mask & BR_MCAST_FLOOD) && !ops->port_set_mcast_flood) 5909 return -EINVAL; 5910 5911 return 0; 5912 } 5913 5914 static int mv88e6xxx_port_bridge_flags(struct dsa_switch *ds, int port, 5915 struct switchdev_brport_flags flags, 5916 struct netlink_ext_ack *extack) 5917 { 5918 struct mv88e6xxx_chip *chip = ds->priv; 5919 int err = -EOPNOTSUPP; 5920 5921 mv88e6xxx_reg_lock(chip); 5922 5923 if (flags.mask & BR_LEARNING) { 5924 bool learning = !!(flags.val & BR_LEARNING); 5925 u16 pav = learning ? (1 << port) : 0; 5926 5927 err = mv88e6xxx_port_set_assoc_vector(chip, port, pav); 5928 if (err) 5929 goto out; 5930 } 5931 5932 if (flags.mask & BR_FLOOD) { 5933 bool unicast = !!(flags.val & BR_FLOOD); 5934 5935 err = chip->info->ops->port_set_ucast_flood(chip, port, 5936 unicast); 5937 if (err) 5938 goto out; 5939 } 5940 5941 if (flags.mask & BR_MCAST_FLOOD) { 5942 bool multicast = !!(flags.val & BR_MCAST_FLOOD); 5943 5944 err = chip->info->ops->port_set_mcast_flood(chip, port, 5945 multicast); 5946 if (err) 5947 goto out; 5948 } 5949 5950 if (flags.mask & BR_BCAST_FLOOD) { 5951 bool broadcast = !!(flags.val & BR_BCAST_FLOOD); 5952 5953 err = mv88e6xxx_port_broadcast_sync(chip, port, broadcast); 5954 if (err) 5955 goto out; 5956 } 5957 5958 out: 5959 mv88e6xxx_reg_unlock(chip); 5960 5961 return err; 5962 } 5963 5964 static bool mv88e6xxx_lag_can_offload(struct dsa_switch *ds, 5965 struct net_device *lag, 5966 struct netdev_lag_upper_info *info) 5967 { 5968 struct mv88e6xxx_chip *chip = ds->priv; 5969 struct dsa_port *dp; 5970 int id, members = 0; 5971 5972 if (!mv88e6xxx_has_lag(chip)) 5973 return false; 5974 5975 id = dsa_lag_id(ds->dst, lag); 5976 if (id < 0 || id >= ds->num_lag_ids) 5977 return false; 5978 5979 dsa_lag_foreach_port(dp, ds->dst, lag) 5980 /* Includes the port joining the LAG */ 5981 members++; 5982 5983 if (members > 8) 5984 return false; 5985 5986 /* We could potentially relax this to include active 5987 * backup in the future. 5988 */ 5989 if (info->tx_type != NETDEV_LAG_TX_TYPE_HASH) 5990 return false; 5991 5992 /* Ideally we would also validate that the hash type matches 5993 * the hardware. Alas, this is always set to unknown on team 5994 * interfaces. 5995 */ 5996 return true; 5997 } 5998 5999 static int mv88e6xxx_lag_sync_map(struct dsa_switch *ds, struct net_device *lag) 6000 { 6001 struct mv88e6xxx_chip *chip = ds->priv; 6002 struct dsa_port *dp; 6003 u16 map = 0; 6004 int id; 6005 6006 id = dsa_lag_id(ds->dst, lag); 6007 6008 /* Build the map of all ports to distribute flows destined for 6009 * this LAG. This can be either a local user port, or a DSA 6010 * port if the LAG port is on a remote chip. 6011 */ 6012 dsa_lag_foreach_port(dp, ds->dst, lag) 6013 map |= BIT(dsa_towards_port(ds, dp->ds->index, dp->index)); 6014 6015 return mv88e6xxx_g2_trunk_mapping_write(chip, id, map); 6016 } 6017 6018 static const u8 mv88e6xxx_lag_mask_table[8][8] = { 6019 /* Row number corresponds to the number of active members in a 6020 * LAG. Each column states which of the eight hash buckets are 6021 * mapped to the column:th port in the LAG. 6022 * 6023 * Example: In a LAG with three active ports, the second port 6024 * ([2][1]) would be selected for traffic mapped to buckets 6025 * 3,4,5 (0x38). 6026 */ 6027 { 0xff, 0, 0, 0, 0, 0, 0, 0 }, 6028 { 0x0f, 0xf0, 0, 0, 0, 0, 0, 0 }, 6029 { 0x07, 0x38, 0xc0, 0, 0, 0, 0, 0 }, 6030 { 0x03, 0x0c, 0x30, 0xc0, 0, 0, 0, 0 }, 6031 { 0x03, 0x0c, 0x30, 0x40, 0x80, 0, 0, 0 }, 6032 { 0x03, 0x0c, 0x10, 0x20, 0x40, 0x80, 0, 0 }, 6033 { 0x03, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80, 0 }, 6034 { 0x01, 0x02, 0x04, 0x08, 0x10, 0x20, 0x40, 0x80 }, 6035 }; 6036 6037 static void mv88e6xxx_lag_set_port_mask(u16 *mask, int port, 6038 int num_tx, int nth) 6039 { 6040 u8 active = 0; 6041 int i; 6042 6043 num_tx = num_tx <= 8 ? num_tx : 8; 6044 if (nth < num_tx) 6045 active = mv88e6xxx_lag_mask_table[num_tx - 1][nth]; 6046 6047 for (i = 0; i < 8; i++) { 6048 if (BIT(i) & active) 6049 mask[i] |= BIT(port); 6050 } 6051 } 6052 6053 static int mv88e6xxx_lag_sync_masks(struct dsa_switch *ds) 6054 { 6055 struct mv88e6xxx_chip *chip = ds->priv; 6056 unsigned int id, num_tx; 6057 struct net_device *lag; 6058 struct dsa_port *dp; 6059 int i, err, nth; 6060 u16 mask[8]; 6061 u16 ivec; 6062 6063 /* Assume no port is a member of any LAG. */ 6064 ivec = BIT(mv88e6xxx_num_ports(chip)) - 1; 6065 6066 /* Disable all masks for ports that _are_ members of a LAG. */ 6067 list_for_each_entry(dp, &ds->dst->ports, list) { 6068 if (!dp->lag_dev || dp->ds != ds) 6069 continue; 6070 6071 ivec &= ~BIT(dp->index); 6072 } 6073 6074 for (i = 0; i < 8; i++) 6075 mask[i] = ivec; 6076 6077 /* Enable the correct subset of masks for all LAG ports that 6078 * are in the Tx set. 6079 */ 6080 dsa_lags_foreach_id(id, ds->dst) { 6081 lag = dsa_lag_dev(ds->dst, id); 6082 if (!lag) 6083 continue; 6084 6085 num_tx = 0; 6086 dsa_lag_foreach_port(dp, ds->dst, lag) { 6087 if (dp->lag_tx_enabled) 6088 num_tx++; 6089 } 6090 6091 if (!num_tx) 6092 continue; 6093 6094 nth = 0; 6095 dsa_lag_foreach_port(dp, ds->dst, lag) { 6096 if (!dp->lag_tx_enabled) 6097 continue; 6098 6099 if (dp->ds == ds) 6100 mv88e6xxx_lag_set_port_mask(mask, dp->index, 6101 num_tx, nth); 6102 6103 nth++; 6104 } 6105 } 6106 6107 for (i = 0; i < 8; i++) { 6108 err = mv88e6xxx_g2_trunk_mask_write(chip, i, true, mask[i]); 6109 if (err) 6110 return err; 6111 } 6112 6113 return 0; 6114 } 6115 6116 static int mv88e6xxx_lag_sync_masks_map(struct dsa_switch *ds, 6117 struct net_device *lag) 6118 { 6119 int err; 6120 6121 err = mv88e6xxx_lag_sync_masks(ds); 6122 6123 if (!err) 6124 err = mv88e6xxx_lag_sync_map(ds, lag); 6125 6126 return err; 6127 } 6128 6129 static int mv88e6xxx_port_lag_change(struct dsa_switch *ds, int port) 6130 { 6131 struct mv88e6xxx_chip *chip = ds->priv; 6132 int err; 6133 6134 mv88e6xxx_reg_lock(chip); 6135 err = mv88e6xxx_lag_sync_masks(ds); 6136 mv88e6xxx_reg_unlock(chip); 6137 return err; 6138 } 6139 6140 static int mv88e6xxx_port_lag_join(struct dsa_switch *ds, int port, 6141 struct net_device *lag, 6142 struct netdev_lag_upper_info *info) 6143 { 6144 struct mv88e6xxx_chip *chip = ds->priv; 6145 int err, id; 6146 6147 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6148 return -EOPNOTSUPP; 6149 6150 id = dsa_lag_id(ds->dst, lag); 6151 6152 mv88e6xxx_reg_lock(chip); 6153 6154 err = mv88e6xxx_port_set_trunk(chip, port, true, id); 6155 if (err) 6156 goto err_unlock; 6157 6158 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6159 if (err) 6160 goto err_clear_trunk; 6161 6162 mv88e6xxx_reg_unlock(chip); 6163 return 0; 6164 6165 err_clear_trunk: 6166 mv88e6xxx_port_set_trunk(chip, port, false, 0); 6167 err_unlock: 6168 mv88e6xxx_reg_unlock(chip); 6169 return err; 6170 } 6171 6172 static int mv88e6xxx_port_lag_leave(struct dsa_switch *ds, int port, 6173 struct net_device *lag) 6174 { 6175 struct mv88e6xxx_chip *chip = ds->priv; 6176 int err_sync, err_trunk; 6177 6178 mv88e6xxx_reg_lock(chip); 6179 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6180 err_trunk = mv88e6xxx_port_set_trunk(chip, port, false, 0); 6181 mv88e6xxx_reg_unlock(chip); 6182 return err_sync ? : err_trunk; 6183 } 6184 6185 static int mv88e6xxx_crosschip_lag_change(struct dsa_switch *ds, int sw_index, 6186 int port) 6187 { 6188 struct mv88e6xxx_chip *chip = ds->priv; 6189 int err; 6190 6191 mv88e6xxx_reg_lock(chip); 6192 err = mv88e6xxx_lag_sync_masks(ds); 6193 mv88e6xxx_reg_unlock(chip); 6194 return err; 6195 } 6196 6197 static int mv88e6xxx_crosschip_lag_join(struct dsa_switch *ds, int sw_index, 6198 int port, struct net_device *lag, 6199 struct netdev_lag_upper_info *info) 6200 { 6201 struct mv88e6xxx_chip *chip = ds->priv; 6202 int err; 6203 6204 if (!mv88e6xxx_lag_can_offload(ds, lag, info)) 6205 return -EOPNOTSUPP; 6206 6207 mv88e6xxx_reg_lock(chip); 6208 6209 err = mv88e6xxx_lag_sync_masks_map(ds, lag); 6210 if (err) 6211 goto unlock; 6212 6213 err = mv88e6xxx_pvt_map(chip, sw_index, port); 6214 6215 unlock: 6216 mv88e6xxx_reg_unlock(chip); 6217 return err; 6218 } 6219 6220 static int mv88e6xxx_crosschip_lag_leave(struct dsa_switch *ds, int sw_index, 6221 int port, struct net_device *lag) 6222 { 6223 struct mv88e6xxx_chip *chip = ds->priv; 6224 int err_sync, err_pvt; 6225 6226 mv88e6xxx_reg_lock(chip); 6227 err_sync = mv88e6xxx_lag_sync_masks_map(ds, lag); 6228 err_pvt = mv88e6xxx_pvt_map(chip, sw_index, port); 6229 mv88e6xxx_reg_unlock(chip); 6230 return err_sync ? : err_pvt; 6231 } 6232 6233 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 6234 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 6235 .change_tag_protocol = mv88e6xxx_change_tag_protocol, 6236 .setup = mv88e6xxx_setup, 6237 .teardown = mv88e6xxx_teardown, 6238 .port_setup = mv88e6xxx_port_setup, 6239 .port_teardown = mv88e6xxx_port_teardown, 6240 .phylink_validate = mv88e6xxx_validate, 6241 .phylink_mac_link_state = mv88e6xxx_serdes_pcs_get_state, 6242 .phylink_mac_config = mv88e6xxx_mac_config, 6243 .phylink_mac_an_restart = mv88e6xxx_serdes_pcs_an_restart, 6244 .phylink_mac_link_down = mv88e6xxx_mac_link_down, 6245 .phylink_mac_link_up = mv88e6xxx_mac_link_up, 6246 .get_strings = mv88e6xxx_get_strings, 6247 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 6248 .get_sset_count = mv88e6xxx_get_sset_count, 6249 .port_enable = mv88e6xxx_port_enable, 6250 .port_disable = mv88e6xxx_port_disable, 6251 .port_max_mtu = mv88e6xxx_get_max_mtu, 6252 .port_change_mtu = mv88e6xxx_change_mtu, 6253 .get_mac_eee = mv88e6xxx_get_mac_eee, 6254 .set_mac_eee = mv88e6xxx_set_mac_eee, 6255 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 6256 .get_eeprom = mv88e6xxx_get_eeprom, 6257 .set_eeprom = mv88e6xxx_set_eeprom, 6258 .get_regs_len = mv88e6xxx_get_regs_len, 6259 .get_regs = mv88e6xxx_get_regs, 6260 .get_rxnfc = mv88e6xxx_get_rxnfc, 6261 .set_rxnfc = mv88e6xxx_set_rxnfc, 6262 .set_ageing_time = mv88e6xxx_set_ageing_time, 6263 .port_bridge_join = mv88e6xxx_port_bridge_join, 6264 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 6265 .port_pre_bridge_flags = mv88e6xxx_port_pre_bridge_flags, 6266 .port_bridge_flags = mv88e6xxx_port_bridge_flags, 6267 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 6268 .port_fast_age = mv88e6xxx_port_fast_age, 6269 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 6270 .port_vlan_add = mv88e6xxx_port_vlan_add, 6271 .port_vlan_del = mv88e6xxx_port_vlan_del, 6272 .port_fdb_add = mv88e6xxx_port_fdb_add, 6273 .port_fdb_del = mv88e6xxx_port_fdb_del, 6274 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 6275 .port_mdb_add = mv88e6xxx_port_mdb_add, 6276 .port_mdb_del = mv88e6xxx_port_mdb_del, 6277 .port_mirror_add = mv88e6xxx_port_mirror_add, 6278 .port_mirror_del = mv88e6xxx_port_mirror_del, 6279 .crosschip_bridge_join = mv88e6xxx_crosschip_bridge_join, 6280 .crosschip_bridge_leave = mv88e6xxx_crosschip_bridge_leave, 6281 .port_hwtstamp_set = mv88e6xxx_port_hwtstamp_set, 6282 .port_hwtstamp_get = mv88e6xxx_port_hwtstamp_get, 6283 .port_txtstamp = mv88e6xxx_port_txtstamp, 6284 .port_rxtstamp = mv88e6xxx_port_rxtstamp, 6285 .get_ts_info = mv88e6xxx_get_ts_info, 6286 .devlink_param_get = mv88e6xxx_devlink_param_get, 6287 .devlink_param_set = mv88e6xxx_devlink_param_set, 6288 .devlink_info_get = mv88e6xxx_devlink_info_get, 6289 .port_lag_change = mv88e6xxx_port_lag_change, 6290 .port_lag_join = mv88e6xxx_port_lag_join, 6291 .port_lag_leave = mv88e6xxx_port_lag_leave, 6292 .crosschip_lag_change = mv88e6xxx_crosschip_lag_change, 6293 .crosschip_lag_join = mv88e6xxx_crosschip_lag_join, 6294 .crosschip_lag_leave = mv88e6xxx_crosschip_lag_leave, 6295 .port_bridge_tx_fwd_offload = mv88e6xxx_bridge_tx_fwd_offload, 6296 .port_bridge_tx_fwd_unoffload = mv88e6xxx_bridge_tx_fwd_unoffload, 6297 }; 6298 6299 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 6300 { 6301 struct device *dev = chip->dev; 6302 struct dsa_switch *ds; 6303 6304 ds = devm_kzalloc(dev, sizeof(*ds), GFP_KERNEL); 6305 if (!ds) 6306 return -ENOMEM; 6307 6308 ds->dev = dev; 6309 ds->num_ports = mv88e6xxx_num_ports(chip); 6310 ds->priv = chip; 6311 ds->dev = dev; 6312 ds->ops = &mv88e6xxx_switch_ops; 6313 ds->ageing_time_min = chip->info->age_time_coeff; 6314 ds->ageing_time_max = chip->info->age_time_coeff * U8_MAX; 6315 6316 /* Some chips support up to 32, but that requires enabling the 6317 * 5-bit port mode, which we do not support. 640k^W16 ought to 6318 * be enough for anyone. 6319 */ 6320 ds->num_lag_ids = mv88e6xxx_has_lag(chip) ? 16 : 0; 6321 6322 dev_set_drvdata(dev, ds); 6323 6324 return dsa_register_switch(ds); 6325 } 6326 6327 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 6328 { 6329 dsa_unregister_switch(chip->ds); 6330 } 6331 6332 static const void *pdata_device_get_match_data(struct device *dev) 6333 { 6334 const struct of_device_id *matches = dev->driver->of_match_table; 6335 const struct dsa_mv88e6xxx_pdata *pdata = dev->platform_data; 6336 6337 for (; matches->name[0] || matches->type[0] || matches->compatible[0]; 6338 matches++) { 6339 if (!strcmp(pdata->compatible, matches->compatible)) 6340 return matches->data; 6341 } 6342 return NULL; 6343 } 6344 6345 /* There is no suspend to RAM support at DSA level yet, the switch configuration 6346 * would be lost after a power cycle so prevent it to be suspended. 6347 */ 6348 static int __maybe_unused mv88e6xxx_suspend(struct device *dev) 6349 { 6350 return -EOPNOTSUPP; 6351 } 6352 6353 static int __maybe_unused mv88e6xxx_resume(struct device *dev) 6354 { 6355 return 0; 6356 } 6357 6358 static SIMPLE_DEV_PM_OPS(mv88e6xxx_pm_ops, mv88e6xxx_suspend, mv88e6xxx_resume); 6359 6360 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 6361 { 6362 struct dsa_mv88e6xxx_pdata *pdata = mdiodev->dev.platform_data; 6363 const struct mv88e6xxx_info *compat_info = NULL; 6364 struct device *dev = &mdiodev->dev; 6365 struct device_node *np = dev->of_node; 6366 struct mv88e6xxx_chip *chip; 6367 int port; 6368 int err; 6369 6370 if (!np && !pdata) 6371 return -EINVAL; 6372 6373 if (np) 6374 compat_info = of_device_get_match_data(dev); 6375 6376 if (pdata) { 6377 compat_info = pdata_device_get_match_data(dev); 6378 6379 if (!pdata->netdev) 6380 return -EINVAL; 6381 6382 for (port = 0; port < DSA_MAX_PORTS; port++) { 6383 if (!(pdata->enabled_ports & (1 << port))) 6384 continue; 6385 if (strcmp(pdata->cd.port_names[port], "cpu")) 6386 continue; 6387 pdata->cd.netdev[port] = &pdata->netdev->dev; 6388 break; 6389 } 6390 } 6391 6392 if (!compat_info) 6393 return -EINVAL; 6394 6395 chip = mv88e6xxx_alloc_chip(dev); 6396 if (!chip) { 6397 err = -ENOMEM; 6398 goto out; 6399 } 6400 6401 chip->info = compat_info; 6402 6403 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 6404 if (err) 6405 goto out; 6406 6407 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 6408 if (IS_ERR(chip->reset)) { 6409 err = PTR_ERR(chip->reset); 6410 goto out; 6411 } 6412 if (chip->reset) 6413 usleep_range(1000, 2000); 6414 6415 err = mv88e6xxx_detect(chip); 6416 if (err) 6417 goto out; 6418 6419 if (chip->info->edsa_support == MV88E6XXX_EDSA_SUPPORTED) 6420 chip->tag_protocol = DSA_TAG_PROTO_EDSA; 6421 else 6422 chip->tag_protocol = DSA_TAG_PROTO_DSA; 6423 6424 mv88e6xxx_phy_init(chip); 6425 6426 if (chip->info->ops->get_eeprom) { 6427 if (np) 6428 of_property_read_u32(np, "eeprom-length", 6429 &chip->eeprom_len); 6430 else 6431 chip->eeprom_len = pdata->eeprom_len; 6432 } 6433 6434 mv88e6xxx_reg_lock(chip); 6435 err = mv88e6xxx_switch_reset(chip); 6436 mv88e6xxx_reg_unlock(chip); 6437 if (err) 6438 goto out; 6439 6440 if (np) { 6441 chip->irq = of_irq_get(np, 0); 6442 if (chip->irq == -EPROBE_DEFER) { 6443 err = chip->irq; 6444 goto out; 6445 } 6446 } 6447 6448 if (pdata) 6449 chip->irq = pdata->irq; 6450 6451 /* Has to be performed before the MDIO bus is created, because 6452 * the PHYs will link their interrupts to these interrupt 6453 * controllers 6454 */ 6455 mv88e6xxx_reg_lock(chip); 6456 if (chip->irq > 0) 6457 err = mv88e6xxx_g1_irq_setup(chip); 6458 else 6459 err = mv88e6xxx_irq_poll_setup(chip); 6460 mv88e6xxx_reg_unlock(chip); 6461 6462 if (err) 6463 goto out; 6464 6465 if (chip->info->g2_irqs > 0) { 6466 err = mv88e6xxx_g2_irq_setup(chip); 6467 if (err) 6468 goto out_g1_irq; 6469 } 6470 6471 err = mv88e6xxx_g1_atu_prob_irq_setup(chip); 6472 if (err) 6473 goto out_g2_irq; 6474 6475 err = mv88e6xxx_g1_vtu_prob_irq_setup(chip); 6476 if (err) 6477 goto out_g1_atu_prob_irq; 6478 6479 err = mv88e6xxx_mdios_register(chip, np); 6480 if (err) 6481 goto out_g1_vtu_prob_irq; 6482 6483 err = mv88e6xxx_register_switch(chip); 6484 if (err) 6485 goto out_mdio; 6486 6487 return 0; 6488 6489 out_mdio: 6490 mv88e6xxx_mdios_unregister(chip); 6491 out_g1_vtu_prob_irq: 6492 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6493 out_g1_atu_prob_irq: 6494 mv88e6xxx_g1_atu_prob_irq_free(chip); 6495 out_g2_irq: 6496 if (chip->info->g2_irqs > 0) 6497 mv88e6xxx_g2_irq_free(chip); 6498 out_g1_irq: 6499 if (chip->irq > 0) 6500 mv88e6xxx_g1_irq_free(chip); 6501 else 6502 mv88e6xxx_irq_poll_free(chip); 6503 out: 6504 if (pdata) 6505 dev_put(pdata->netdev); 6506 6507 return err; 6508 } 6509 6510 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 6511 { 6512 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6513 struct mv88e6xxx_chip *chip; 6514 6515 if (!ds) 6516 return; 6517 6518 chip = ds->priv; 6519 6520 if (chip->info->ptp_support) { 6521 mv88e6xxx_hwtstamp_free(chip); 6522 mv88e6xxx_ptp_free(chip); 6523 } 6524 6525 mv88e6xxx_phy_destroy(chip); 6526 mv88e6xxx_unregister_switch(chip); 6527 mv88e6xxx_mdios_unregister(chip); 6528 6529 mv88e6xxx_g1_vtu_prob_irq_free(chip); 6530 mv88e6xxx_g1_atu_prob_irq_free(chip); 6531 6532 if (chip->info->g2_irqs > 0) 6533 mv88e6xxx_g2_irq_free(chip); 6534 6535 if (chip->irq > 0) 6536 mv88e6xxx_g1_irq_free(chip); 6537 else 6538 mv88e6xxx_irq_poll_free(chip); 6539 6540 dev_set_drvdata(&mdiodev->dev, NULL); 6541 } 6542 6543 static void mv88e6xxx_shutdown(struct mdio_device *mdiodev) 6544 { 6545 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 6546 6547 if (!ds) 6548 return; 6549 6550 dsa_switch_shutdown(ds); 6551 6552 dev_set_drvdata(&mdiodev->dev, NULL); 6553 } 6554 6555 static const struct of_device_id mv88e6xxx_of_match[] = { 6556 { 6557 .compatible = "marvell,mv88e6085", 6558 .data = &mv88e6xxx_table[MV88E6085], 6559 }, 6560 { 6561 .compatible = "marvell,mv88e6190", 6562 .data = &mv88e6xxx_table[MV88E6190], 6563 }, 6564 { 6565 .compatible = "marvell,mv88e6250", 6566 .data = &mv88e6xxx_table[MV88E6250], 6567 }, 6568 { /* sentinel */ }, 6569 }; 6570 6571 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 6572 6573 static struct mdio_driver mv88e6xxx_driver = { 6574 .probe = mv88e6xxx_probe, 6575 .remove = mv88e6xxx_remove, 6576 .shutdown = mv88e6xxx_shutdown, 6577 .mdiodrv.driver = { 6578 .name = "mv88e6085", 6579 .of_match_table = mv88e6xxx_of_match, 6580 .pm = &mv88e6xxx_pm_ops, 6581 }, 6582 }; 6583 6584 mdio_module_driver(mv88e6xxx_driver); 6585 6586 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 6587 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 6588 MODULE_LICENSE("GPL"); 6589