1 /* 2 * Marvell 88e6xxx Ethernet switch single-chip support 3 * 4 * Copyright (c) 2008 Marvell Semiconductor 5 * 6 * Copyright (c) 2015 CMC Electronics, Inc. 7 * Added support for VLAN Table Unit operations 8 * 9 * Copyright (c) 2016 Andrew Lunn <andrew@lunn.ch> 10 * 11 * This program is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include <linux/delay.h> 18 #include <linux/etherdevice.h> 19 #include <linux/ethtool.h> 20 #include <linux/if_bridge.h> 21 #include <linux/interrupt.h> 22 #include <linux/irq.h> 23 #include <linux/irqdomain.h> 24 #include <linux/jiffies.h> 25 #include <linux/list.h> 26 #include <linux/mdio.h> 27 #include <linux/module.h> 28 #include <linux/of_device.h> 29 #include <linux/of_irq.h> 30 #include <linux/of_mdio.h> 31 #include <linux/netdevice.h> 32 #include <linux/gpio/consumer.h> 33 #include <linux/phy.h> 34 #include <net/dsa.h> 35 #include <net/switchdev.h> 36 37 #include "mv88e6xxx.h" 38 #include "global1.h" 39 #include "global2.h" 40 #include "port.h" 41 42 static void assert_reg_lock(struct mv88e6xxx_chip *chip) 43 { 44 if (unlikely(!mutex_is_locked(&chip->reg_lock))) { 45 dev_err(chip->dev, "Switch registers lock not held!\n"); 46 dump_stack(); 47 } 48 } 49 50 /* The switch ADDR[4:1] configuration pins define the chip SMI device address 51 * (ADDR[0] is always zero, thus only even SMI addresses can be strapped). 52 * 53 * When ADDR is all zero, the chip uses Single-chip Addressing Mode, assuming it 54 * is the only device connected to the SMI master. In this mode it responds to 55 * all 32 possible SMI addresses, and thus maps directly the internal devices. 56 * 57 * When ADDR is non-zero, the chip uses Multi-chip Addressing Mode, allowing 58 * multiple devices to share the SMI interface. In this mode it responds to only 59 * 2 registers, used to indirectly access the internal SMI devices. 60 */ 61 62 static int mv88e6xxx_smi_read(struct mv88e6xxx_chip *chip, 63 int addr, int reg, u16 *val) 64 { 65 if (!chip->smi_ops) 66 return -EOPNOTSUPP; 67 68 return chip->smi_ops->read(chip, addr, reg, val); 69 } 70 71 static int mv88e6xxx_smi_write(struct mv88e6xxx_chip *chip, 72 int addr, int reg, u16 val) 73 { 74 if (!chip->smi_ops) 75 return -EOPNOTSUPP; 76 77 return chip->smi_ops->write(chip, addr, reg, val); 78 } 79 80 static int mv88e6xxx_smi_single_chip_read(struct mv88e6xxx_chip *chip, 81 int addr, int reg, u16 *val) 82 { 83 int ret; 84 85 ret = mdiobus_read_nested(chip->bus, addr, reg); 86 if (ret < 0) 87 return ret; 88 89 *val = ret & 0xffff; 90 91 return 0; 92 } 93 94 static int mv88e6xxx_smi_single_chip_write(struct mv88e6xxx_chip *chip, 95 int addr, int reg, u16 val) 96 { 97 int ret; 98 99 ret = mdiobus_write_nested(chip->bus, addr, reg, val); 100 if (ret < 0) 101 return ret; 102 103 return 0; 104 } 105 106 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_single_chip_ops = { 107 .read = mv88e6xxx_smi_single_chip_read, 108 .write = mv88e6xxx_smi_single_chip_write, 109 }; 110 111 static int mv88e6xxx_smi_multi_chip_wait(struct mv88e6xxx_chip *chip) 112 { 113 int ret; 114 int i; 115 116 for (i = 0; i < 16; i++) { 117 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_CMD); 118 if (ret < 0) 119 return ret; 120 121 if ((ret & SMI_CMD_BUSY) == 0) 122 return 0; 123 } 124 125 return -ETIMEDOUT; 126 } 127 128 static int mv88e6xxx_smi_multi_chip_read(struct mv88e6xxx_chip *chip, 129 int addr, int reg, u16 *val) 130 { 131 int ret; 132 133 /* Wait for the bus to become free. */ 134 ret = mv88e6xxx_smi_multi_chip_wait(chip); 135 if (ret < 0) 136 return ret; 137 138 /* Transmit the read command. */ 139 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 140 SMI_CMD_OP_22_READ | (addr << 5) | reg); 141 if (ret < 0) 142 return ret; 143 144 /* Wait for the read command to complete. */ 145 ret = mv88e6xxx_smi_multi_chip_wait(chip); 146 if (ret < 0) 147 return ret; 148 149 /* Read the data. */ 150 ret = mdiobus_read_nested(chip->bus, chip->sw_addr, SMI_DATA); 151 if (ret < 0) 152 return ret; 153 154 *val = ret & 0xffff; 155 156 return 0; 157 } 158 159 static int mv88e6xxx_smi_multi_chip_write(struct mv88e6xxx_chip *chip, 160 int addr, int reg, u16 val) 161 { 162 int ret; 163 164 /* Wait for the bus to become free. */ 165 ret = mv88e6xxx_smi_multi_chip_wait(chip); 166 if (ret < 0) 167 return ret; 168 169 /* Transmit the data to write. */ 170 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_DATA, val); 171 if (ret < 0) 172 return ret; 173 174 /* Transmit the write command. */ 175 ret = mdiobus_write_nested(chip->bus, chip->sw_addr, SMI_CMD, 176 SMI_CMD_OP_22_WRITE | (addr << 5) | reg); 177 if (ret < 0) 178 return ret; 179 180 /* Wait for the write command to complete. */ 181 ret = mv88e6xxx_smi_multi_chip_wait(chip); 182 if (ret < 0) 183 return ret; 184 185 return 0; 186 } 187 188 static const struct mv88e6xxx_bus_ops mv88e6xxx_smi_multi_chip_ops = { 189 .read = mv88e6xxx_smi_multi_chip_read, 190 .write = mv88e6xxx_smi_multi_chip_write, 191 }; 192 193 int mv88e6xxx_read(struct mv88e6xxx_chip *chip, int addr, int reg, u16 *val) 194 { 195 int err; 196 197 assert_reg_lock(chip); 198 199 err = mv88e6xxx_smi_read(chip, addr, reg, val); 200 if (err) 201 return err; 202 203 dev_dbg(chip->dev, "<- addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 204 addr, reg, *val); 205 206 return 0; 207 } 208 209 int mv88e6xxx_write(struct mv88e6xxx_chip *chip, int addr, int reg, u16 val) 210 { 211 int err; 212 213 assert_reg_lock(chip); 214 215 err = mv88e6xxx_smi_write(chip, addr, reg, val); 216 if (err) 217 return err; 218 219 dev_dbg(chip->dev, "-> addr: 0x%.2x reg: 0x%.2x val: 0x%.4x\n", 220 addr, reg, val); 221 222 return 0; 223 } 224 225 static int mv88e6165_phy_read(struct mv88e6xxx_chip *chip, 226 struct mii_bus *bus, 227 int addr, int reg, u16 *val) 228 { 229 return mv88e6xxx_read(chip, addr, reg, val); 230 } 231 232 static int mv88e6165_phy_write(struct mv88e6xxx_chip *chip, 233 struct mii_bus *bus, 234 int addr, int reg, u16 val) 235 { 236 return mv88e6xxx_write(chip, addr, reg, val); 237 } 238 239 static struct mii_bus *mv88e6xxx_default_mdio_bus(struct mv88e6xxx_chip *chip) 240 { 241 struct mv88e6xxx_mdio_bus *mdio_bus; 242 243 mdio_bus = list_first_entry(&chip->mdios, struct mv88e6xxx_mdio_bus, 244 list); 245 if (!mdio_bus) 246 return NULL; 247 248 return mdio_bus->bus; 249 } 250 251 static int mv88e6xxx_phy_read(struct mv88e6xxx_chip *chip, int phy, 252 int reg, u16 *val) 253 { 254 int addr = phy; /* PHY devices addresses start at 0x0 */ 255 struct mii_bus *bus; 256 257 bus = mv88e6xxx_default_mdio_bus(chip); 258 if (!bus) 259 return -EOPNOTSUPP; 260 261 if (!chip->info->ops->phy_read) 262 return -EOPNOTSUPP; 263 264 return chip->info->ops->phy_read(chip, bus, addr, reg, val); 265 } 266 267 static int mv88e6xxx_phy_write(struct mv88e6xxx_chip *chip, int phy, 268 int reg, u16 val) 269 { 270 int addr = phy; /* PHY devices addresses start at 0x0 */ 271 struct mii_bus *bus; 272 273 bus = mv88e6xxx_default_mdio_bus(chip); 274 if (!bus) 275 return -EOPNOTSUPP; 276 277 if (!chip->info->ops->phy_write) 278 return -EOPNOTSUPP; 279 280 return chip->info->ops->phy_write(chip, bus, addr, reg, val); 281 } 282 283 static int mv88e6xxx_phy_page_get(struct mv88e6xxx_chip *chip, int phy, u8 page) 284 { 285 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_PHY_PAGE)) 286 return -EOPNOTSUPP; 287 288 return mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 289 } 290 291 static void mv88e6xxx_phy_page_put(struct mv88e6xxx_chip *chip, int phy) 292 { 293 int err; 294 295 /* Restore PHY page Copper 0x0 for access via the registered MDIO bus */ 296 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, PHY_PAGE_COPPER); 297 if (unlikely(err)) { 298 dev_err(chip->dev, "failed to restore PHY %d page Copper (%d)\n", 299 phy, err); 300 } 301 } 302 303 static int mv88e6xxx_phy_page_read(struct mv88e6xxx_chip *chip, int phy, 304 u8 page, int reg, u16 *val) 305 { 306 int err; 307 308 /* There is no paging for registers 22 */ 309 if (reg == PHY_PAGE) 310 return -EINVAL; 311 312 err = mv88e6xxx_phy_page_get(chip, phy, page); 313 if (!err) { 314 err = mv88e6xxx_phy_read(chip, phy, reg, val); 315 mv88e6xxx_phy_page_put(chip, phy); 316 } 317 318 return err; 319 } 320 321 static int mv88e6xxx_phy_page_write(struct mv88e6xxx_chip *chip, int phy, 322 u8 page, int reg, u16 val) 323 { 324 int err; 325 326 /* There is no paging for registers 22 */ 327 if (reg == PHY_PAGE) 328 return -EINVAL; 329 330 err = mv88e6xxx_phy_page_get(chip, phy, page); 331 if (!err) { 332 err = mv88e6xxx_phy_write(chip, phy, PHY_PAGE, page); 333 mv88e6xxx_phy_page_put(chip, phy); 334 } 335 336 return err; 337 } 338 339 static int mv88e6xxx_serdes_read(struct mv88e6xxx_chip *chip, int reg, u16 *val) 340 { 341 return mv88e6xxx_phy_page_read(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 342 reg, val); 343 } 344 345 static int mv88e6xxx_serdes_write(struct mv88e6xxx_chip *chip, int reg, u16 val) 346 { 347 return mv88e6xxx_phy_page_write(chip, ADDR_SERDES, SERDES_PAGE_FIBER, 348 reg, val); 349 } 350 351 static void mv88e6xxx_g1_irq_mask(struct irq_data *d) 352 { 353 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 354 unsigned int n = d->hwirq; 355 356 chip->g1_irq.masked |= (1 << n); 357 } 358 359 static void mv88e6xxx_g1_irq_unmask(struct irq_data *d) 360 { 361 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 362 unsigned int n = d->hwirq; 363 364 chip->g1_irq.masked &= ~(1 << n); 365 } 366 367 static irqreturn_t mv88e6xxx_g1_irq_thread_fn(int irq, void *dev_id) 368 { 369 struct mv88e6xxx_chip *chip = dev_id; 370 unsigned int nhandled = 0; 371 unsigned int sub_irq; 372 unsigned int n; 373 u16 reg; 374 int err; 375 376 mutex_lock(&chip->reg_lock); 377 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 378 mutex_unlock(&chip->reg_lock); 379 380 if (err) 381 goto out; 382 383 for (n = 0; n < chip->g1_irq.nirqs; ++n) { 384 if (reg & (1 << n)) { 385 sub_irq = irq_find_mapping(chip->g1_irq.domain, n); 386 handle_nested_irq(sub_irq); 387 ++nhandled; 388 } 389 } 390 out: 391 return (nhandled > 0 ? IRQ_HANDLED : IRQ_NONE); 392 } 393 394 static void mv88e6xxx_g1_irq_bus_lock(struct irq_data *d) 395 { 396 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 397 398 mutex_lock(&chip->reg_lock); 399 } 400 401 static void mv88e6xxx_g1_irq_bus_sync_unlock(struct irq_data *d) 402 { 403 struct mv88e6xxx_chip *chip = irq_data_get_irq_chip_data(d); 404 u16 mask = GENMASK(chip->g1_irq.nirqs, 0); 405 u16 reg; 406 int err; 407 408 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, ®); 409 if (err) 410 goto out; 411 412 reg &= ~mask; 413 reg |= (~chip->g1_irq.masked & mask); 414 415 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, reg); 416 if (err) 417 goto out; 418 419 out: 420 mutex_unlock(&chip->reg_lock); 421 } 422 423 static struct irq_chip mv88e6xxx_g1_irq_chip = { 424 .name = "mv88e6xxx-g1", 425 .irq_mask = mv88e6xxx_g1_irq_mask, 426 .irq_unmask = mv88e6xxx_g1_irq_unmask, 427 .irq_bus_lock = mv88e6xxx_g1_irq_bus_lock, 428 .irq_bus_sync_unlock = mv88e6xxx_g1_irq_bus_sync_unlock, 429 }; 430 431 static int mv88e6xxx_g1_irq_domain_map(struct irq_domain *d, 432 unsigned int irq, 433 irq_hw_number_t hwirq) 434 { 435 struct mv88e6xxx_chip *chip = d->host_data; 436 437 irq_set_chip_data(irq, d->host_data); 438 irq_set_chip_and_handler(irq, &chip->g1_irq.chip, handle_level_irq); 439 irq_set_noprobe(irq); 440 441 return 0; 442 } 443 444 static const struct irq_domain_ops mv88e6xxx_g1_irq_domain_ops = { 445 .map = mv88e6xxx_g1_irq_domain_map, 446 .xlate = irq_domain_xlate_twocell, 447 }; 448 449 static void mv88e6xxx_g1_irq_free(struct mv88e6xxx_chip *chip) 450 { 451 int irq, virq; 452 u16 mask; 453 454 mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 455 mask |= GENMASK(chip->g1_irq.nirqs, 0); 456 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 457 458 free_irq(chip->irq, chip); 459 460 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) { 461 virq = irq_find_mapping(chip->g1_irq.domain, irq); 462 irq_dispose_mapping(virq); 463 } 464 465 irq_domain_remove(chip->g1_irq.domain); 466 } 467 468 static int mv88e6xxx_g1_irq_setup(struct mv88e6xxx_chip *chip) 469 { 470 int err, irq, virq; 471 u16 reg, mask; 472 473 chip->g1_irq.nirqs = chip->info->g1_irqs; 474 chip->g1_irq.domain = irq_domain_add_simple( 475 NULL, chip->g1_irq.nirqs, 0, 476 &mv88e6xxx_g1_irq_domain_ops, chip); 477 if (!chip->g1_irq.domain) 478 return -ENOMEM; 479 480 for (irq = 0; irq < chip->g1_irq.nirqs; irq++) 481 irq_create_mapping(chip->g1_irq.domain, irq); 482 483 chip->g1_irq.chip = mv88e6xxx_g1_irq_chip; 484 chip->g1_irq.masked = ~0; 485 486 err = mv88e6xxx_g1_read(chip, GLOBAL_CONTROL, &mask); 487 if (err) 488 goto out_mapping; 489 490 mask &= ~GENMASK(chip->g1_irq.nirqs, 0); 491 492 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 493 if (err) 494 goto out_disable; 495 496 /* Reading the interrupt status clears (most of) them */ 497 err = mv88e6xxx_g1_read(chip, GLOBAL_STATUS, ®); 498 if (err) 499 goto out_disable; 500 501 err = request_threaded_irq(chip->irq, NULL, 502 mv88e6xxx_g1_irq_thread_fn, 503 IRQF_ONESHOT | IRQF_TRIGGER_FALLING, 504 dev_name(chip->dev), chip); 505 if (err) 506 goto out_disable; 507 508 return 0; 509 510 out_disable: 511 mask |= GENMASK(chip->g1_irq.nirqs, 0); 512 mv88e6xxx_g1_write(chip, GLOBAL_CONTROL, mask); 513 514 out_mapping: 515 for (irq = 0; irq < 16; irq++) { 516 virq = irq_find_mapping(chip->g1_irq.domain, irq); 517 irq_dispose_mapping(virq); 518 } 519 520 irq_domain_remove(chip->g1_irq.domain); 521 522 return err; 523 } 524 525 int mv88e6xxx_wait(struct mv88e6xxx_chip *chip, int addr, int reg, u16 mask) 526 { 527 int i; 528 529 for (i = 0; i < 16; i++) { 530 u16 val; 531 int err; 532 533 err = mv88e6xxx_read(chip, addr, reg, &val); 534 if (err) 535 return err; 536 537 if (!(val & mask)) 538 return 0; 539 540 usleep_range(1000, 2000); 541 } 542 543 dev_err(chip->dev, "Timeout while waiting for switch\n"); 544 return -ETIMEDOUT; 545 } 546 547 /* Indirect write to single pointer-data register with an Update bit */ 548 int mv88e6xxx_update(struct mv88e6xxx_chip *chip, int addr, int reg, u16 update) 549 { 550 u16 val; 551 int err; 552 553 /* Wait until the previous operation is completed */ 554 err = mv88e6xxx_wait(chip, addr, reg, BIT(15)); 555 if (err) 556 return err; 557 558 /* Set the Update bit to trigger a write operation */ 559 val = BIT(15) | update; 560 561 return mv88e6xxx_write(chip, addr, reg, val); 562 } 563 564 static int mv88e6xxx_ppu_disable(struct mv88e6xxx_chip *chip) 565 { 566 if (!chip->info->ops->ppu_disable) 567 return 0; 568 569 return chip->info->ops->ppu_disable(chip); 570 } 571 572 static int mv88e6xxx_ppu_enable(struct mv88e6xxx_chip *chip) 573 { 574 if (!chip->info->ops->ppu_enable) 575 return 0; 576 577 return chip->info->ops->ppu_enable(chip); 578 } 579 580 static void mv88e6xxx_ppu_reenable_work(struct work_struct *ugly) 581 { 582 struct mv88e6xxx_chip *chip; 583 584 chip = container_of(ugly, struct mv88e6xxx_chip, ppu_work); 585 586 mutex_lock(&chip->reg_lock); 587 588 if (mutex_trylock(&chip->ppu_mutex)) { 589 if (mv88e6xxx_ppu_enable(chip) == 0) 590 chip->ppu_disabled = 0; 591 mutex_unlock(&chip->ppu_mutex); 592 } 593 594 mutex_unlock(&chip->reg_lock); 595 } 596 597 static void mv88e6xxx_ppu_reenable_timer(unsigned long _ps) 598 { 599 struct mv88e6xxx_chip *chip = (void *)_ps; 600 601 schedule_work(&chip->ppu_work); 602 } 603 604 static int mv88e6xxx_ppu_access_get(struct mv88e6xxx_chip *chip) 605 { 606 int ret; 607 608 mutex_lock(&chip->ppu_mutex); 609 610 /* If the PHY polling unit is enabled, disable it so that 611 * we can access the PHY registers. If it was already 612 * disabled, cancel the timer that is going to re-enable 613 * it. 614 */ 615 if (!chip->ppu_disabled) { 616 ret = mv88e6xxx_ppu_disable(chip); 617 if (ret < 0) { 618 mutex_unlock(&chip->ppu_mutex); 619 return ret; 620 } 621 chip->ppu_disabled = 1; 622 } else { 623 del_timer(&chip->ppu_timer); 624 ret = 0; 625 } 626 627 return ret; 628 } 629 630 static void mv88e6xxx_ppu_access_put(struct mv88e6xxx_chip *chip) 631 { 632 /* Schedule a timer to re-enable the PHY polling unit. */ 633 mod_timer(&chip->ppu_timer, jiffies + msecs_to_jiffies(10)); 634 mutex_unlock(&chip->ppu_mutex); 635 } 636 637 static void mv88e6xxx_ppu_state_init(struct mv88e6xxx_chip *chip) 638 { 639 mutex_init(&chip->ppu_mutex); 640 INIT_WORK(&chip->ppu_work, mv88e6xxx_ppu_reenable_work); 641 setup_timer(&chip->ppu_timer, mv88e6xxx_ppu_reenable_timer, 642 (unsigned long)chip); 643 } 644 645 static void mv88e6xxx_ppu_state_destroy(struct mv88e6xxx_chip *chip) 646 { 647 del_timer_sync(&chip->ppu_timer); 648 } 649 650 static int mv88e6xxx_phy_ppu_read(struct mv88e6xxx_chip *chip, 651 struct mii_bus *bus, 652 int addr, int reg, u16 *val) 653 { 654 int err; 655 656 err = mv88e6xxx_ppu_access_get(chip); 657 if (!err) { 658 err = mv88e6xxx_read(chip, addr, reg, val); 659 mv88e6xxx_ppu_access_put(chip); 660 } 661 662 return err; 663 } 664 665 static int mv88e6xxx_phy_ppu_write(struct mv88e6xxx_chip *chip, 666 struct mii_bus *bus, 667 int addr, int reg, u16 val) 668 { 669 int err; 670 671 err = mv88e6xxx_ppu_access_get(chip); 672 if (!err) { 673 err = mv88e6xxx_write(chip, addr, reg, val); 674 mv88e6xxx_ppu_access_put(chip); 675 } 676 677 return err; 678 } 679 680 static bool mv88e6xxx_6097_family(struct mv88e6xxx_chip *chip) 681 { 682 return chip->info->family == MV88E6XXX_FAMILY_6097; 683 } 684 685 static bool mv88e6xxx_6165_family(struct mv88e6xxx_chip *chip) 686 { 687 return chip->info->family == MV88E6XXX_FAMILY_6165; 688 } 689 690 static bool mv88e6xxx_6320_family(struct mv88e6xxx_chip *chip) 691 { 692 return chip->info->family == MV88E6XXX_FAMILY_6320; 693 } 694 695 static bool mv88e6xxx_6341_family(struct mv88e6xxx_chip *chip) 696 { 697 return chip->info->family == MV88E6XXX_FAMILY_6341; 698 } 699 700 static bool mv88e6xxx_6351_family(struct mv88e6xxx_chip *chip) 701 { 702 return chip->info->family == MV88E6XXX_FAMILY_6351; 703 } 704 705 static bool mv88e6xxx_6352_family(struct mv88e6xxx_chip *chip) 706 { 707 return chip->info->family == MV88E6XXX_FAMILY_6352; 708 } 709 710 static int mv88e6xxx_port_setup_mac(struct mv88e6xxx_chip *chip, int port, 711 int link, int speed, int duplex, 712 phy_interface_t mode) 713 { 714 int err; 715 716 if (!chip->info->ops->port_set_link) 717 return 0; 718 719 /* Port's MAC control must not be changed unless the link is down */ 720 err = chip->info->ops->port_set_link(chip, port, 0); 721 if (err) 722 return err; 723 724 if (chip->info->ops->port_set_speed) { 725 err = chip->info->ops->port_set_speed(chip, port, speed); 726 if (err && err != -EOPNOTSUPP) 727 goto restore_link; 728 } 729 730 if (chip->info->ops->port_set_duplex) { 731 err = chip->info->ops->port_set_duplex(chip, port, duplex); 732 if (err && err != -EOPNOTSUPP) 733 goto restore_link; 734 } 735 736 if (chip->info->ops->port_set_rgmii_delay) { 737 err = chip->info->ops->port_set_rgmii_delay(chip, port, mode); 738 if (err && err != -EOPNOTSUPP) 739 goto restore_link; 740 } 741 742 if (chip->info->ops->port_set_cmode) { 743 err = chip->info->ops->port_set_cmode(chip, port, mode); 744 if (err && err != -EOPNOTSUPP) 745 goto restore_link; 746 } 747 748 err = 0; 749 restore_link: 750 if (chip->info->ops->port_set_link(chip, port, link)) 751 netdev_err(chip->ds->ports[port].netdev, 752 "failed to restore MAC's link\n"); 753 754 return err; 755 } 756 757 /* We expect the switch to perform auto negotiation if there is a real 758 * phy. However, in the case of a fixed link phy, we force the port 759 * settings from the fixed link settings. 760 */ 761 static void mv88e6xxx_adjust_link(struct dsa_switch *ds, int port, 762 struct phy_device *phydev) 763 { 764 struct mv88e6xxx_chip *chip = ds->priv; 765 int err; 766 767 if (!phy_is_pseudo_fixed_link(phydev)) 768 return; 769 770 mutex_lock(&chip->reg_lock); 771 err = mv88e6xxx_port_setup_mac(chip, port, phydev->link, phydev->speed, 772 phydev->duplex, phydev->interface); 773 mutex_unlock(&chip->reg_lock); 774 775 if (err && err != -EOPNOTSUPP) 776 netdev_err(ds->ports[port].netdev, "failed to configure MAC\n"); 777 } 778 779 static int mv88e6xxx_stats_snapshot(struct mv88e6xxx_chip *chip, int port) 780 { 781 if (!chip->info->ops->stats_snapshot) 782 return -EOPNOTSUPP; 783 784 return chip->info->ops->stats_snapshot(chip, port); 785 } 786 787 static struct mv88e6xxx_hw_stat mv88e6xxx_hw_stats[] = { 788 { "in_good_octets", 8, 0x00, STATS_TYPE_BANK0, }, 789 { "in_bad_octets", 4, 0x02, STATS_TYPE_BANK0, }, 790 { "in_unicast", 4, 0x04, STATS_TYPE_BANK0, }, 791 { "in_broadcasts", 4, 0x06, STATS_TYPE_BANK0, }, 792 { "in_multicasts", 4, 0x07, STATS_TYPE_BANK0, }, 793 { "in_pause", 4, 0x16, STATS_TYPE_BANK0, }, 794 { "in_undersize", 4, 0x18, STATS_TYPE_BANK0, }, 795 { "in_fragments", 4, 0x19, STATS_TYPE_BANK0, }, 796 { "in_oversize", 4, 0x1a, STATS_TYPE_BANK0, }, 797 { "in_jabber", 4, 0x1b, STATS_TYPE_BANK0, }, 798 { "in_rx_error", 4, 0x1c, STATS_TYPE_BANK0, }, 799 { "in_fcs_error", 4, 0x1d, STATS_TYPE_BANK0, }, 800 { "out_octets", 8, 0x0e, STATS_TYPE_BANK0, }, 801 { "out_unicast", 4, 0x10, STATS_TYPE_BANK0, }, 802 { "out_broadcasts", 4, 0x13, STATS_TYPE_BANK0, }, 803 { "out_multicasts", 4, 0x12, STATS_TYPE_BANK0, }, 804 { "out_pause", 4, 0x15, STATS_TYPE_BANK0, }, 805 { "excessive", 4, 0x11, STATS_TYPE_BANK0, }, 806 { "collisions", 4, 0x1e, STATS_TYPE_BANK0, }, 807 { "deferred", 4, 0x05, STATS_TYPE_BANK0, }, 808 { "single", 4, 0x14, STATS_TYPE_BANK0, }, 809 { "multiple", 4, 0x17, STATS_TYPE_BANK0, }, 810 { "out_fcs_error", 4, 0x03, STATS_TYPE_BANK0, }, 811 { "late", 4, 0x1f, STATS_TYPE_BANK0, }, 812 { "hist_64bytes", 4, 0x08, STATS_TYPE_BANK0, }, 813 { "hist_65_127bytes", 4, 0x09, STATS_TYPE_BANK0, }, 814 { "hist_128_255bytes", 4, 0x0a, STATS_TYPE_BANK0, }, 815 { "hist_256_511bytes", 4, 0x0b, STATS_TYPE_BANK0, }, 816 { "hist_512_1023bytes", 4, 0x0c, STATS_TYPE_BANK0, }, 817 { "hist_1024_max_bytes", 4, 0x0d, STATS_TYPE_BANK0, }, 818 { "sw_in_discards", 4, 0x10, STATS_TYPE_PORT, }, 819 { "sw_in_filtered", 2, 0x12, STATS_TYPE_PORT, }, 820 { "sw_out_filtered", 2, 0x13, STATS_TYPE_PORT, }, 821 { "in_discards", 4, 0x00, STATS_TYPE_BANK1, }, 822 { "in_filtered", 4, 0x01, STATS_TYPE_BANK1, }, 823 { "in_accepted", 4, 0x02, STATS_TYPE_BANK1, }, 824 { "in_bad_accepted", 4, 0x03, STATS_TYPE_BANK1, }, 825 { "in_good_avb_class_a", 4, 0x04, STATS_TYPE_BANK1, }, 826 { "in_good_avb_class_b", 4, 0x05, STATS_TYPE_BANK1, }, 827 { "in_bad_avb_class_a", 4, 0x06, STATS_TYPE_BANK1, }, 828 { "in_bad_avb_class_b", 4, 0x07, STATS_TYPE_BANK1, }, 829 { "tcam_counter_0", 4, 0x08, STATS_TYPE_BANK1, }, 830 { "tcam_counter_1", 4, 0x09, STATS_TYPE_BANK1, }, 831 { "tcam_counter_2", 4, 0x0a, STATS_TYPE_BANK1, }, 832 { "tcam_counter_3", 4, 0x0b, STATS_TYPE_BANK1, }, 833 { "in_da_unknown", 4, 0x0e, STATS_TYPE_BANK1, }, 834 { "in_management", 4, 0x0f, STATS_TYPE_BANK1, }, 835 { "out_queue_0", 4, 0x10, STATS_TYPE_BANK1, }, 836 { "out_queue_1", 4, 0x11, STATS_TYPE_BANK1, }, 837 { "out_queue_2", 4, 0x12, STATS_TYPE_BANK1, }, 838 { "out_queue_3", 4, 0x13, STATS_TYPE_BANK1, }, 839 { "out_queue_4", 4, 0x14, STATS_TYPE_BANK1, }, 840 { "out_queue_5", 4, 0x15, STATS_TYPE_BANK1, }, 841 { "out_queue_6", 4, 0x16, STATS_TYPE_BANK1, }, 842 { "out_queue_7", 4, 0x17, STATS_TYPE_BANK1, }, 843 { "out_cut_through", 4, 0x18, STATS_TYPE_BANK1, }, 844 { "out_octets_a", 4, 0x1a, STATS_TYPE_BANK1, }, 845 { "out_octets_b", 4, 0x1b, STATS_TYPE_BANK1, }, 846 { "out_management", 4, 0x1f, STATS_TYPE_BANK1, }, 847 }; 848 849 static uint64_t _mv88e6xxx_get_ethtool_stat(struct mv88e6xxx_chip *chip, 850 struct mv88e6xxx_hw_stat *s, 851 int port, u16 bank1_select, 852 u16 histogram) 853 { 854 u32 low; 855 u32 high = 0; 856 u16 reg = 0; 857 int err; 858 u64 value; 859 860 switch (s->type) { 861 case STATS_TYPE_PORT: 862 err = mv88e6xxx_port_read(chip, port, s->reg, ®); 863 if (err) 864 return UINT64_MAX; 865 866 low = reg; 867 if (s->sizeof_stat == 4) { 868 err = mv88e6xxx_port_read(chip, port, s->reg + 1, ®); 869 if (err) 870 return UINT64_MAX; 871 high = reg; 872 } 873 break; 874 case STATS_TYPE_BANK1: 875 reg = bank1_select; 876 /* fall through */ 877 case STATS_TYPE_BANK0: 878 reg |= s->reg | histogram; 879 mv88e6xxx_g1_stats_read(chip, reg, &low); 880 if (s->sizeof_stat == 8) 881 mv88e6xxx_g1_stats_read(chip, reg + 1, &high); 882 } 883 value = (((u64)high) << 16) | low; 884 return value; 885 } 886 887 static void mv88e6xxx_stats_get_strings(struct mv88e6xxx_chip *chip, 888 uint8_t *data, int types) 889 { 890 struct mv88e6xxx_hw_stat *stat; 891 int i, j; 892 893 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 894 stat = &mv88e6xxx_hw_stats[i]; 895 if (stat->type & types) { 896 memcpy(data + j * ETH_GSTRING_LEN, stat->string, 897 ETH_GSTRING_LEN); 898 j++; 899 } 900 } 901 } 902 903 static void mv88e6095_stats_get_strings(struct mv88e6xxx_chip *chip, 904 uint8_t *data) 905 { 906 mv88e6xxx_stats_get_strings(chip, data, 907 STATS_TYPE_BANK0 | STATS_TYPE_PORT); 908 } 909 910 static void mv88e6320_stats_get_strings(struct mv88e6xxx_chip *chip, 911 uint8_t *data) 912 { 913 mv88e6xxx_stats_get_strings(chip, data, 914 STATS_TYPE_BANK0 | STATS_TYPE_BANK1); 915 } 916 917 static void mv88e6xxx_get_strings(struct dsa_switch *ds, int port, 918 uint8_t *data) 919 { 920 struct mv88e6xxx_chip *chip = ds->priv; 921 922 if (chip->info->ops->stats_get_strings) 923 chip->info->ops->stats_get_strings(chip, data); 924 } 925 926 static int mv88e6xxx_stats_get_sset_count(struct mv88e6xxx_chip *chip, 927 int types) 928 { 929 struct mv88e6xxx_hw_stat *stat; 930 int i, j; 931 932 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 933 stat = &mv88e6xxx_hw_stats[i]; 934 if (stat->type & types) 935 j++; 936 } 937 return j; 938 } 939 940 static int mv88e6095_stats_get_sset_count(struct mv88e6xxx_chip *chip) 941 { 942 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 943 STATS_TYPE_PORT); 944 } 945 946 static int mv88e6320_stats_get_sset_count(struct mv88e6xxx_chip *chip) 947 { 948 return mv88e6xxx_stats_get_sset_count(chip, STATS_TYPE_BANK0 | 949 STATS_TYPE_BANK1); 950 } 951 952 static int mv88e6xxx_get_sset_count(struct dsa_switch *ds) 953 { 954 struct mv88e6xxx_chip *chip = ds->priv; 955 956 if (chip->info->ops->stats_get_sset_count) 957 return chip->info->ops->stats_get_sset_count(chip); 958 959 return 0; 960 } 961 962 static void mv88e6xxx_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 963 uint64_t *data, int types, 964 u16 bank1_select, u16 histogram) 965 { 966 struct mv88e6xxx_hw_stat *stat; 967 int i, j; 968 969 for (i = 0, j = 0; i < ARRAY_SIZE(mv88e6xxx_hw_stats); i++) { 970 stat = &mv88e6xxx_hw_stats[i]; 971 if (stat->type & types) { 972 data[j] = _mv88e6xxx_get_ethtool_stat(chip, stat, port, 973 bank1_select, 974 histogram); 975 j++; 976 } 977 } 978 } 979 980 static void mv88e6095_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 981 uint64_t *data) 982 { 983 return mv88e6xxx_stats_get_stats(chip, port, data, 984 STATS_TYPE_BANK0 | STATS_TYPE_PORT, 985 0, GLOBAL_STATS_OP_HIST_RX_TX); 986 } 987 988 static void mv88e6320_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 989 uint64_t *data) 990 { 991 return mv88e6xxx_stats_get_stats(chip, port, data, 992 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 993 GLOBAL_STATS_OP_BANK_1_BIT_9, 994 GLOBAL_STATS_OP_HIST_RX_TX); 995 } 996 997 static void mv88e6390_stats_get_stats(struct mv88e6xxx_chip *chip, int port, 998 uint64_t *data) 999 { 1000 return mv88e6xxx_stats_get_stats(chip, port, data, 1001 STATS_TYPE_BANK0 | STATS_TYPE_BANK1, 1002 GLOBAL_STATS_OP_BANK_1_BIT_10, 0); 1003 } 1004 1005 static void mv88e6xxx_get_stats(struct mv88e6xxx_chip *chip, int port, 1006 uint64_t *data) 1007 { 1008 if (chip->info->ops->stats_get_stats) 1009 chip->info->ops->stats_get_stats(chip, port, data); 1010 } 1011 1012 static void mv88e6xxx_get_ethtool_stats(struct dsa_switch *ds, int port, 1013 uint64_t *data) 1014 { 1015 struct mv88e6xxx_chip *chip = ds->priv; 1016 int ret; 1017 1018 mutex_lock(&chip->reg_lock); 1019 1020 ret = mv88e6xxx_stats_snapshot(chip, port); 1021 if (ret < 0) { 1022 mutex_unlock(&chip->reg_lock); 1023 return; 1024 } 1025 1026 mv88e6xxx_get_stats(chip, port, data); 1027 1028 mutex_unlock(&chip->reg_lock); 1029 } 1030 1031 static int mv88e6xxx_stats_set_histogram(struct mv88e6xxx_chip *chip) 1032 { 1033 if (chip->info->ops->stats_set_histogram) 1034 return chip->info->ops->stats_set_histogram(chip); 1035 1036 return 0; 1037 } 1038 1039 static int mv88e6xxx_get_regs_len(struct dsa_switch *ds, int port) 1040 { 1041 return 32 * sizeof(u16); 1042 } 1043 1044 static void mv88e6xxx_get_regs(struct dsa_switch *ds, int port, 1045 struct ethtool_regs *regs, void *_p) 1046 { 1047 struct mv88e6xxx_chip *chip = ds->priv; 1048 int err; 1049 u16 reg; 1050 u16 *p = _p; 1051 int i; 1052 1053 regs->version = 0; 1054 1055 memset(p, 0xff, 32 * sizeof(u16)); 1056 1057 mutex_lock(&chip->reg_lock); 1058 1059 for (i = 0; i < 32; i++) { 1060 1061 err = mv88e6xxx_port_read(chip, port, i, ®); 1062 if (!err) 1063 p[i] = reg; 1064 } 1065 1066 mutex_unlock(&chip->reg_lock); 1067 } 1068 1069 static int _mv88e6xxx_atu_wait(struct mv88e6xxx_chip *chip) 1070 { 1071 return mv88e6xxx_g1_wait(chip, GLOBAL_ATU_OP, GLOBAL_ATU_OP_BUSY); 1072 } 1073 1074 static int mv88e6xxx_get_eee(struct dsa_switch *ds, int port, 1075 struct ethtool_eee *e) 1076 { 1077 struct mv88e6xxx_chip *chip = ds->priv; 1078 u16 reg; 1079 int err; 1080 1081 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1082 return -EOPNOTSUPP; 1083 1084 mutex_lock(&chip->reg_lock); 1085 1086 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1087 if (err) 1088 goto out; 1089 1090 e->eee_enabled = !!(reg & 0x0200); 1091 e->tx_lpi_enabled = !!(reg & 0x0100); 1092 1093 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 1094 if (err) 1095 goto out; 1096 1097 e->eee_active = !!(reg & PORT_STATUS_EEE); 1098 out: 1099 mutex_unlock(&chip->reg_lock); 1100 1101 return err; 1102 } 1103 1104 static int mv88e6xxx_set_eee(struct dsa_switch *ds, int port, 1105 struct phy_device *phydev, struct ethtool_eee *e) 1106 { 1107 struct mv88e6xxx_chip *chip = ds->priv; 1108 u16 reg; 1109 int err; 1110 1111 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_EEE)) 1112 return -EOPNOTSUPP; 1113 1114 mutex_lock(&chip->reg_lock); 1115 1116 err = mv88e6xxx_phy_read(chip, port, 16, ®); 1117 if (err) 1118 goto out; 1119 1120 reg &= ~0x0300; 1121 if (e->eee_enabled) 1122 reg |= 0x0200; 1123 if (e->tx_lpi_enabled) 1124 reg |= 0x0100; 1125 1126 err = mv88e6xxx_phy_write(chip, port, 16, reg); 1127 out: 1128 mutex_unlock(&chip->reg_lock); 1129 1130 return err; 1131 } 1132 1133 static int _mv88e6xxx_atu_cmd(struct mv88e6xxx_chip *chip, u16 fid, u16 cmd) 1134 { 1135 u16 val; 1136 int err; 1137 1138 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_ATU_FID)) { 1139 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_FID, fid); 1140 if (err) 1141 return err; 1142 } else if (mv88e6xxx_num_databases(chip) == 256) { 1143 /* ATU DBNum[7:4] are located in ATU Control 15:12 */ 1144 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 1145 if (err) 1146 return err; 1147 1148 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 1149 (val & 0xfff) | ((fid << 8) & 0xf000)); 1150 if (err) 1151 return err; 1152 1153 /* ATU DBNum[3:0] are located in ATU Operation 3:0 */ 1154 cmd |= fid & 0xf; 1155 } 1156 1157 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_OP, cmd); 1158 if (err) 1159 return err; 1160 1161 return _mv88e6xxx_atu_wait(chip); 1162 } 1163 1164 static int _mv88e6xxx_atu_data_write(struct mv88e6xxx_chip *chip, 1165 struct mv88e6xxx_atu_entry *entry) 1166 { 1167 u16 data = entry->state & GLOBAL_ATU_DATA_STATE_MASK; 1168 1169 if (entry->state != GLOBAL_ATU_DATA_STATE_UNUSED) { 1170 unsigned int mask, shift; 1171 1172 if (entry->trunk) { 1173 data |= GLOBAL_ATU_DATA_TRUNK; 1174 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 1175 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 1176 } else { 1177 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 1178 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 1179 } 1180 1181 data |= (entry->portv_trunkid << shift) & mask; 1182 } 1183 1184 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_DATA, data); 1185 } 1186 1187 static int _mv88e6xxx_atu_flush_move(struct mv88e6xxx_chip *chip, 1188 struct mv88e6xxx_atu_entry *entry, 1189 bool static_too) 1190 { 1191 int op; 1192 int err; 1193 1194 err = _mv88e6xxx_atu_wait(chip); 1195 if (err) 1196 return err; 1197 1198 err = _mv88e6xxx_atu_data_write(chip, entry); 1199 if (err) 1200 return err; 1201 1202 if (entry->fid) { 1203 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL_DB : 1204 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC_DB; 1205 } else { 1206 op = static_too ? GLOBAL_ATU_OP_FLUSH_MOVE_ALL : 1207 GLOBAL_ATU_OP_FLUSH_MOVE_NON_STATIC; 1208 } 1209 1210 return _mv88e6xxx_atu_cmd(chip, entry->fid, op); 1211 } 1212 1213 static int _mv88e6xxx_atu_flush(struct mv88e6xxx_chip *chip, 1214 u16 fid, bool static_too) 1215 { 1216 struct mv88e6xxx_atu_entry entry = { 1217 .fid = fid, 1218 .state = 0, /* EntryState bits must be 0 */ 1219 }; 1220 1221 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1222 } 1223 1224 static int _mv88e6xxx_atu_move(struct mv88e6xxx_chip *chip, u16 fid, 1225 int from_port, int to_port, bool static_too) 1226 { 1227 struct mv88e6xxx_atu_entry entry = { 1228 .trunk = false, 1229 .fid = fid, 1230 }; 1231 1232 /* EntryState bits must be 0xF */ 1233 entry.state = GLOBAL_ATU_DATA_STATE_MASK; 1234 1235 /* ToPort and FromPort are respectively in PortVec bits 7:4 and 3:0 */ 1236 entry.portv_trunkid = (to_port & 0x0f) << 4; 1237 entry.portv_trunkid |= from_port & 0x0f; 1238 1239 return _mv88e6xxx_atu_flush_move(chip, &entry, static_too); 1240 } 1241 1242 static int _mv88e6xxx_atu_remove(struct mv88e6xxx_chip *chip, u16 fid, 1243 int port, bool static_too) 1244 { 1245 /* Destination port 0xF means remove the entries */ 1246 return _mv88e6xxx_atu_move(chip, fid, port, 0x0f, static_too); 1247 } 1248 1249 static int _mv88e6xxx_port_based_vlan_map(struct mv88e6xxx_chip *chip, int port) 1250 { 1251 struct dsa_switch *ds = chip->ds; 1252 struct net_device *bridge = ds->ports[port].bridge_dev; 1253 u16 output_ports = 0; 1254 int i; 1255 1256 /* allow CPU port or DSA link(s) to send frames to every port */ 1257 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) { 1258 output_ports = ~0; 1259 } else { 1260 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1261 /* allow sending frames to every group member */ 1262 if (bridge && ds->ports[i].bridge_dev == bridge) 1263 output_ports |= BIT(i); 1264 1265 /* allow sending frames to CPU port and DSA link(s) */ 1266 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1267 output_ports |= BIT(i); 1268 } 1269 } 1270 1271 /* prevent frames from going back out of the port they came in on */ 1272 output_ports &= ~BIT(port); 1273 1274 return mv88e6xxx_port_set_vlan_map(chip, port, output_ports); 1275 } 1276 1277 static void mv88e6xxx_port_stp_state_set(struct dsa_switch *ds, int port, 1278 u8 state) 1279 { 1280 struct mv88e6xxx_chip *chip = ds->priv; 1281 int stp_state; 1282 int err; 1283 1284 switch (state) { 1285 case BR_STATE_DISABLED: 1286 stp_state = PORT_CONTROL_STATE_DISABLED; 1287 break; 1288 case BR_STATE_BLOCKING: 1289 case BR_STATE_LISTENING: 1290 stp_state = PORT_CONTROL_STATE_BLOCKING; 1291 break; 1292 case BR_STATE_LEARNING: 1293 stp_state = PORT_CONTROL_STATE_LEARNING; 1294 break; 1295 case BR_STATE_FORWARDING: 1296 default: 1297 stp_state = PORT_CONTROL_STATE_FORWARDING; 1298 break; 1299 } 1300 1301 mutex_lock(&chip->reg_lock); 1302 err = mv88e6xxx_port_set_state(chip, port, stp_state); 1303 mutex_unlock(&chip->reg_lock); 1304 1305 if (err) 1306 netdev_err(ds->ports[port].netdev, "failed to update state\n"); 1307 } 1308 1309 static void mv88e6xxx_port_fast_age(struct dsa_switch *ds, int port) 1310 { 1311 struct mv88e6xxx_chip *chip = ds->priv; 1312 int err; 1313 1314 mutex_lock(&chip->reg_lock); 1315 err = _mv88e6xxx_atu_remove(chip, 0, port, false); 1316 mutex_unlock(&chip->reg_lock); 1317 1318 if (err) 1319 netdev_err(ds->ports[port].netdev, "failed to flush ATU\n"); 1320 } 1321 1322 static int _mv88e6xxx_vtu_wait(struct mv88e6xxx_chip *chip) 1323 { 1324 return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY); 1325 } 1326 1327 static int _mv88e6xxx_vtu_cmd(struct mv88e6xxx_chip *chip, u16 op) 1328 { 1329 int err; 1330 1331 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op); 1332 if (err) 1333 return err; 1334 1335 return _mv88e6xxx_vtu_wait(chip); 1336 } 1337 1338 static int _mv88e6xxx_vtu_stu_flush(struct mv88e6xxx_chip *chip) 1339 { 1340 int ret; 1341 1342 ret = _mv88e6xxx_vtu_wait(chip); 1343 if (ret < 0) 1344 return ret; 1345 1346 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_FLUSH_ALL); 1347 } 1348 1349 static int _mv88e6xxx_vtu_stu_data_read(struct mv88e6xxx_chip *chip, 1350 struct mv88e6xxx_vtu_entry *entry, 1351 unsigned int nibble_offset) 1352 { 1353 u16 regs[3]; 1354 int i, err; 1355 1356 for (i = 0; i < 3; ++i) { 1357 u16 *reg = ®s[i]; 1358 1359 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1360 if (err) 1361 return err; 1362 } 1363 1364 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1365 unsigned int shift = (i % 4) * 4 + nibble_offset; 1366 u16 reg = regs[i / 4]; 1367 1368 entry->data[i] = (reg >> shift) & GLOBAL_VTU_STU_DATA_MASK; 1369 } 1370 1371 return 0; 1372 } 1373 1374 static int mv88e6xxx_vtu_data_read(struct mv88e6xxx_chip *chip, 1375 struct mv88e6xxx_vtu_entry *entry) 1376 { 1377 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 0); 1378 } 1379 1380 static int mv88e6xxx_stu_data_read(struct mv88e6xxx_chip *chip, 1381 struct mv88e6xxx_vtu_entry *entry) 1382 { 1383 return _mv88e6xxx_vtu_stu_data_read(chip, entry, 2); 1384 } 1385 1386 static int _mv88e6xxx_vtu_stu_data_write(struct mv88e6xxx_chip *chip, 1387 struct mv88e6xxx_vtu_entry *entry, 1388 unsigned int nibble_offset) 1389 { 1390 u16 regs[3] = { 0 }; 1391 int i, err; 1392 1393 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1394 unsigned int shift = (i % 4) * 4 + nibble_offset; 1395 u8 data = entry->data[i]; 1396 1397 regs[i / 4] |= (data & GLOBAL_VTU_STU_DATA_MASK) << shift; 1398 } 1399 1400 for (i = 0; i < 3; ++i) { 1401 u16 reg = regs[i]; 1402 1403 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg); 1404 if (err) 1405 return err; 1406 } 1407 1408 return 0; 1409 } 1410 1411 static int mv88e6xxx_vtu_data_write(struct mv88e6xxx_chip *chip, 1412 struct mv88e6xxx_vtu_entry *entry) 1413 { 1414 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 0); 1415 } 1416 1417 static int mv88e6xxx_stu_data_write(struct mv88e6xxx_chip *chip, 1418 struct mv88e6xxx_vtu_entry *entry) 1419 { 1420 return _mv88e6xxx_vtu_stu_data_write(chip, entry, 2); 1421 } 1422 1423 static int _mv88e6xxx_vtu_vid_write(struct mv88e6xxx_chip *chip, u16 vid) 1424 { 1425 return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, 1426 vid & GLOBAL_VTU_VID_MASK); 1427 } 1428 1429 static int _mv88e6xxx_vtu_getnext(struct mv88e6xxx_chip *chip, 1430 struct mv88e6xxx_vtu_entry *entry) 1431 { 1432 struct mv88e6xxx_vtu_entry next = { 0 }; 1433 u16 val; 1434 int err; 1435 1436 err = _mv88e6xxx_vtu_wait(chip); 1437 if (err) 1438 return err; 1439 1440 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_VTU_GET_NEXT); 1441 if (err) 1442 return err; 1443 1444 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1445 if (err) 1446 return err; 1447 1448 next.vid = val & GLOBAL_VTU_VID_MASK; 1449 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1450 1451 if (next.valid) { 1452 err = mv88e6xxx_vtu_data_read(chip, &next); 1453 if (err) 1454 return err; 1455 1456 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1457 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val); 1458 if (err) 1459 return err; 1460 1461 next.fid = val & GLOBAL_VTU_FID_MASK; 1462 } else if (mv88e6xxx_num_databases(chip) == 256) { 1463 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1464 * VTU DBNum[3:0] are located in VTU Operation 3:0 1465 */ 1466 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val); 1467 if (err) 1468 return err; 1469 1470 next.fid = (val & 0xf00) >> 4; 1471 next.fid |= val & 0xf; 1472 } 1473 1474 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1475 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1476 if (err) 1477 return err; 1478 1479 next.sid = val & GLOBAL_VTU_SID_MASK; 1480 } 1481 } 1482 1483 *entry = next; 1484 return 0; 1485 } 1486 1487 static int mv88e6xxx_port_vlan_dump(struct dsa_switch *ds, int port, 1488 struct switchdev_obj_port_vlan *vlan, 1489 int (*cb)(struct switchdev_obj *obj)) 1490 { 1491 struct mv88e6xxx_chip *chip = ds->priv; 1492 struct mv88e6xxx_vtu_entry next; 1493 u16 pvid; 1494 int err; 1495 1496 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1497 return -EOPNOTSUPP; 1498 1499 mutex_lock(&chip->reg_lock); 1500 1501 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1502 if (err) 1503 goto unlock; 1504 1505 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1506 if (err) 1507 goto unlock; 1508 1509 do { 1510 err = _mv88e6xxx_vtu_getnext(chip, &next); 1511 if (err) 1512 break; 1513 1514 if (!next.valid) 1515 break; 1516 1517 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1518 continue; 1519 1520 /* reinit and dump this VLAN obj */ 1521 vlan->vid_begin = next.vid; 1522 vlan->vid_end = next.vid; 1523 vlan->flags = 0; 1524 1525 if (next.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED) 1526 vlan->flags |= BRIDGE_VLAN_INFO_UNTAGGED; 1527 1528 if (next.vid == pvid) 1529 vlan->flags |= BRIDGE_VLAN_INFO_PVID; 1530 1531 err = cb(&vlan->obj); 1532 if (err) 1533 break; 1534 } while (next.vid < GLOBAL_VTU_VID_MASK); 1535 1536 unlock: 1537 mutex_unlock(&chip->reg_lock); 1538 1539 return err; 1540 } 1541 1542 static int _mv88e6xxx_vtu_loadpurge(struct mv88e6xxx_chip *chip, 1543 struct mv88e6xxx_vtu_entry *entry) 1544 { 1545 u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE; 1546 u16 reg = 0; 1547 int err; 1548 1549 err = _mv88e6xxx_vtu_wait(chip); 1550 if (err) 1551 return err; 1552 1553 if (!entry->valid) 1554 goto loadpurge; 1555 1556 /* Write port member tags */ 1557 err = mv88e6xxx_vtu_data_write(chip, entry); 1558 if (err) 1559 return err; 1560 1561 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_STU)) { 1562 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1563 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1564 if (err) 1565 return err; 1566 } 1567 1568 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G1_VTU_FID)) { 1569 reg = entry->fid & GLOBAL_VTU_FID_MASK; 1570 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, reg); 1571 if (err) 1572 return err; 1573 } else if (mv88e6xxx_num_databases(chip) == 256) { 1574 /* VTU DBNum[7:4] are located in VTU Operation 11:8, and 1575 * VTU DBNum[3:0] are located in VTU Operation 3:0 1576 */ 1577 op |= (entry->fid & 0xf0) << 8; 1578 op |= entry->fid & 0xf; 1579 } 1580 1581 reg = GLOBAL_VTU_VID_VALID; 1582 loadpurge: 1583 reg |= entry->vid & GLOBAL_VTU_VID_MASK; 1584 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1585 if (err) 1586 return err; 1587 1588 return _mv88e6xxx_vtu_cmd(chip, op); 1589 } 1590 1591 static int _mv88e6xxx_stu_getnext(struct mv88e6xxx_chip *chip, u8 sid, 1592 struct mv88e6xxx_vtu_entry *entry) 1593 { 1594 struct mv88e6xxx_vtu_entry next = { 0 }; 1595 u16 val; 1596 int err; 1597 1598 err = _mv88e6xxx_vtu_wait(chip); 1599 if (err) 1600 return err; 1601 1602 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, 1603 sid & GLOBAL_VTU_SID_MASK); 1604 if (err) 1605 return err; 1606 1607 err = _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_GET_NEXT); 1608 if (err) 1609 return err; 1610 1611 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val); 1612 if (err) 1613 return err; 1614 1615 next.sid = val & GLOBAL_VTU_SID_MASK; 1616 1617 err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val); 1618 if (err) 1619 return err; 1620 1621 next.valid = !!(val & GLOBAL_VTU_VID_VALID); 1622 1623 if (next.valid) { 1624 err = mv88e6xxx_stu_data_read(chip, &next); 1625 if (err) 1626 return err; 1627 } 1628 1629 *entry = next; 1630 return 0; 1631 } 1632 1633 static int _mv88e6xxx_stu_loadpurge(struct mv88e6xxx_chip *chip, 1634 struct mv88e6xxx_vtu_entry *entry) 1635 { 1636 u16 reg = 0; 1637 int err; 1638 1639 err = _mv88e6xxx_vtu_wait(chip); 1640 if (err) 1641 return err; 1642 1643 if (!entry->valid) 1644 goto loadpurge; 1645 1646 /* Write port states */ 1647 err = mv88e6xxx_stu_data_write(chip, entry); 1648 if (err) 1649 return err; 1650 1651 reg = GLOBAL_VTU_VID_VALID; 1652 loadpurge: 1653 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, reg); 1654 if (err) 1655 return err; 1656 1657 reg = entry->sid & GLOBAL_VTU_SID_MASK; 1658 err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, reg); 1659 if (err) 1660 return err; 1661 1662 return _mv88e6xxx_vtu_cmd(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE); 1663 } 1664 1665 static int _mv88e6xxx_fid_new(struct mv88e6xxx_chip *chip, u16 *fid) 1666 { 1667 DECLARE_BITMAP(fid_bitmap, MV88E6XXX_N_FID); 1668 struct mv88e6xxx_vtu_entry vlan; 1669 int i, err; 1670 1671 bitmap_zero(fid_bitmap, MV88E6XXX_N_FID); 1672 1673 /* Set every FID bit used by the (un)bridged ports */ 1674 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1675 err = mv88e6xxx_port_get_fid(chip, i, fid); 1676 if (err) 1677 return err; 1678 1679 set_bit(*fid, fid_bitmap); 1680 } 1681 1682 /* Set every FID bit used by the VLAN entries */ 1683 err = _mv88e6xxx_vtu_vid_write(chip, GLOBAL_VTU_VID_MASK); 1684 if (err) 1685 return err; 1686 1687 do { 1688 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1689 if (err) 1690 return err; 1691 1692 if (!vlan.valid) 1693 break; 1694 1695 set_bit(vlan.fid, fid_bitmap); 1696 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 1697 1698 /* The reset value 0x000 is used to indicate that multiple address 1699 * databases are not needed. Return the next positive available. 1700 */ 1701 *fid = find_next_zero_bit(fid_bitmap, MV88E6XXX_N_FID, 1); 1702 if (unlikely(*fid >= mv88e6xxx_num_databases(chip))) 1703 return -ENOSPC; 1704 1705 /* Clear the database */ 1706 return _mv88e6xxx_atu_flush(chip, *fid, true); 1707 } 1708 1709 static int _mv88e6xxx_vtu_new(struct mv88e6xxx_chip *chip, u16 vid, 1710 struct mv88e6xxx_vtu_entry *entry) 1711 { 1712 struct dsa_switch *ds = chip->ds; 1713 struct mv88e6xxx_vtu_entry vlan = { 1714 .valid = true, 1715 .vid = vid, 1716 }; 1717 int i, err; 1718 1719 err = _mv88e6xxx_fid_new(chip, &vlan.fid); 1720 if (err) 1721 return err; 1722 1723 /* exclude all ports except the CPU and DSA ports */ 1724 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 1725 vlan.data[i] = dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i) 1726 ? GLOBAL_VTU_DATA_MEMBER_TAG_UNMODIFIED 1727 : GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1728 1729 if (mv88e6xxx_6097_family(chip) || mv88e6xxx_6165_family(chip) || 1730 mv88e6xxx_6351_family(chip) || mv88e6xxx_6352_family(chip) || 1731 mv88e6xxx_6341_family(chip)) { 1732 struct mv88e6xxx_vtu_entry vstp; 1733 1734 /* Adding a VTU entry requires a valid STU entry. As VSTP is not 1735 * implemented, only one STU entry is needed to cover all VTU 1736 * entries. Thus, validate the SID 0. 1737 */ 1738 vlan.sid = 0; 1739 err = _mv88e6xxx_stu_getnext(chip, GLOBAL_VTU_SID_MASK, &vstp); 1740 if (err) 1741 return err; 1742 1743 if (vstp.sid != vlan.sid || !vstp.valid) { 1744 memset(&vstp, 0, sizeof(vstp)); 1745 vstp.valid = true; 1746 vstp.sid = vlan.sid; 1747 1748 err = _mv88e6xxx_stu_loadpurge(chip, &vstp); 1749 if (err) 1750 return err; 1751 } 1752 } 1753 1754 *entry = vlan; 1755 return 0; 1756 } 1757 1758 static int _mv88e6xxx_vtu_get(struct mv88e6xxx_chip *chip, u16 vid, 1759 struct mv88e6xxx_vtu_entry *entry, bool creat) 1760 { 1761 int err; 1762 1763 if (!vid) 1764 return -EINVAL; 1765 1766 err = _mv88e6xxx_vtu_vid_write(chip, vid - 1); 1767 if (err) 1768 return err; 1769 1770 err = _mv88e6xxx_vtu_getnext(chip, entry); 1771 if (err) 1772 return err; 1773 1774 if (entry->vid != vid || !entry->valid) { 1775 if (!creat) 1776 return -EOPNOTSUPP; 1777 /* -ENOENT would've been more appropriate, but switchdev expects 1778 * -EOPNOTSUPP to inform bridge about an eventual software VLAN. 1779 */ 1780 1781 err = _mv88e6xxx_vtu_new(chip, vid, entry); 1782 } 1783 1784 return err; 1785 } 1786 1787 static int mv88e6xxx_port_check_hw_vlan(struct dsa_switch *ds, int port, 1788 u16 vid_begin, u16 vid_end) 1789 { 1790 struct mv88e6xxx_chip *chip = ds->priv; 1791 struct mv88e6xxx_vtu_entry vlan; 1792 int i, err; 1793 1794 if (!vid_begin) 1795 return -EOPNOTSUPP; 1796 1797 mutex_lock(&chip->reg_lock); 1798 1799 err = _mv88e6xxx_vtu_vid_write(chip, vid_begin - 1); 1800 if (err) 1801 goto unlock; 1802 1803 do { 1804 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 1805 if (err) 1806 goto unlock; 1807 1808 if (!vlan.valid) 1809 break; 1810 1811 if (vlan.vid > vid_end) 1812 break; 1813 1814 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1815 if (dsa_is_dsa_port(ds, i) || dsa_is_cpu_port(ds, i)) 1816 continue; 1817 1818 if (!ds->ports[port].netdev) 1819 continue; 1820 1821 if (vlan.data[i] == 1822 GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1823 continue; 1824 1825 if (ds->ports[i].bridge_dev == 1826 ds->ports[port].bridge_dev) 1827 break; /* same bridge, check next VLAN */ 1828 1829 if (!ds->ports[i].bridge_dev) 1830 continue; 1831 1832 netdev_warn(ds->ports[port].netdev, 1833 "hardware VLAN %d already used by %s\n", 1834 vlan.vid, 1835 netdev_name(ds->ports[i].bridge_dev)); 1836 err = -EOPNOTSUPP; 1837 goto unlock; 1838 } 1839 } while (vlan.vid < vid_end); 1840 1841 unlock: 1842 mutex_unlock(&chip->reg_lock); 1843 1844 return err; 1845 } 1846 1847 static int mv88e6xxx_port_vlan_filtering(struct dsa_switch *ds, int port, 1848 bool vlan_filtering) 1849 { 1850 struct mv88e6xxx_chip *chip = ds->priv; 1851 u16 mode = vlan_filtering ? PORT_CONTROL_2_8021Q_SECURE : 1852 PORT_CONTROL_2_8021Q_DISABLED; 1853 int err; 1854 1855 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1856 return -EOPNOTSUPP; 1857 1858 mutex_lock(&chip->reg_lock); 1859 err = mv88e6xxx_port_set_8021q_mode(chip, port, mode); 1860 mutex_unlock(&chip->reg_lock); 1861 1862 return err; 1863 } 1864 1865 static int 1866 mv88e6xxx_port_vlan_prepare(struct dsa_switch *ds, int port, 1867 const struct switchdev_obj_port_vlan *vlan, 1868 struct switchdev_trans *trans) 1869 { 1870 struct mv88e6xxx_chip *chip = ds->priv; 1871 int err; 1872 1873 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1874 return -EOPNOTSUPP; 1875 1876 /* If the requested port doesn't belong to the same bridge as the VLAN 1877 * members, do not support it (yet) and fallback to software VLAN. 1878 */ 1879 err = mv88e6xxx_port_check_hw_vlan(ds, port, vlan->vid_begin, 1880 vlan->vid_end); 1881 if (err) 1882 return err; 1883 1884 /* We don't need any dynamic resource from the kernel (yet), 1885 * so skip the prepare phase. 1886 */ 1887 return 0; 1888 } 1889 1890 static int _mv88e6xxx_port_vlan_add(struct mv88e6xxx_chip *chip, int port, 1891 u16 vid, bool untagged) 1892 { 1893 struct mv88e6xxx_vtu_entry vlan; 1894 int err; 1895 1896 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, true); 1897 if (err) 1898 return err; 1899 1900 vlan.data[port] = untagged ? 1901 GLOBAL_VTU_DATA_MEMBER_TAG_UNTAGGED : 1902 GLOBAL_VTU_DATA_MEMBER_TAG_TAGGED; 1903 1904 return _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1905 } 1906 1907 static void mv88e6xxx_port_vlan_add(struct dsa_switch *ds, int port, 1908 const struct switchdev_obj_port_vlan *vlan, 1909 struct switchdev_trans *trans) 1910 { 1911 struct mv88e6xxx_chip *chip = ds->priv; 1912 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1913 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1914 u16 vid; 1915 1916 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1917 return; 1918 1919 mutex_lock(&chip->reg_lock); 1920 1921 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) 1922 if (_mv88e6xxx_port_vlan_add(chip, port, vid, untagged)) 1923 netdev_err(ds->ports[port].netdev, 1924 "failed to add VLAN %d%c\n", 1925 vid, untagged ? 'u' : 't'); 1926 1927 if (pvid && mv88e6xxx_port_set_pvid(chip, port, vlan->vid_end)) 1928 netdev_err(ds->ports[port].netdev, "failed to set PVID %d\n", 1929 vlan->vid_end); 1930 1931 mutex_unlock(&chip->reg_lock); 1932 } 1933 1934 static int _mv88e6xxx_port_vlan_del(struct mv88e6xxx_chip *chip, 1935 int port, u16 vid) 1936 { 1937 struct dsa_switch *ds = chip->ds; 1938 struct mv88e6xxx_vtu_entry vlan; 1939 int i, err; 1940 1941 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 1942 if (err) 1943 return err; 1944 1945 /* Tell switchdev if this VLAN is handled in software */ 1946 if (vlan.data[port] == GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) 1947 return -EOPNOTSUPP; 1948 1949 vlan.data[port] = GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER; 1950 1951 /* keep the VLAN unless all ports are excluded */ 1952 vlan.valid = false; 1953 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 1954 if (dsa_is_cpu_port(ds, i) || dsa_is_dsa_port(ds, i)) 1955 continue; 1956 1957 if (vlan.data[i] != GLOBAL_VTU_DATA_MEMBER_TAG_NON_MEMBER) { 1958 vlan.valid = true; 1959 break; 1960 } 1961 } 1962 1963 err = _mv88e6xxx_vtu_loadpurge(chip, &vlan); 1964 if (err) 1965 return err; 1966 1967 return _mv88e6xxx_atu_remove(chip, vlan.fid, port, false); 1968 } 1969 1970 static int mv88e6xxx_port_vlan_del(struct dsa_switch *ds, int port, 1971 const struct switchdev_obj_port_vlan *vlan) 1972 { 1973 struct mv88e6xxx_chip *chip = ds->priv; 1974 u16 pvid, vid; 1975 int err = 0; 1976 1977 if (!mv88e6xxx_has(chip, MV88E6XXX_FLAG_VTU)) 1978 return -EOPNOTSUPP; 1979 1980 mutex_lock(&chip->reg_lock); 1981 1982 err = mv88e6xxx_port_get_pvid(chip, port, &pvid); 1983 if (err) 1984 goto unlock; 1985 1986 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1987 err = _mv88e6xxx_port_vlan_del(chip, port, vid); 1988 if (err) 1989 goto unlock; 1990 1991 if (vid == pvid) { 1992 err = mv88e6xxx_port_set_pvid(chip, port, 0); 1993 if (err) 1994 goto unlock; 1995 } 1996 } 1997 1998 unlock: 1999 mutex_unlock(&chip->reg_lock); 2000 2001 return err; 2002 } 2003 2004 static int _mv88e6xxx_atu_mac_write(struct mv88e6xxx_chip *chip, 2005 const unsigned char *addr) 2006 { 2007 int i, err; 2008 2009 for (i = 0; i < 3; i++) { 2010 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_MAC_01 + i, 2011 (addr[i * 2] << 8) | addr[i * 2 + 1]); 2012 if (err) 2013 return err; 2014 } 2015 2016 return 0; 2017 } 2018 2019 static int _mv88e6xxx_atu_mac_read(struct mv88e6xxx_chip *chip, 2020 unsigned char *addr) 2021 { 2022 u16 val; 2023 int i, err; 2024 2025 for (i = 0; i < 3; i++) { 2026 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_MAC_01 + i, &val); 2027 if (err) 2028 return err; 2029 2030 addr[i * 2] = val >> 8; 2031 addr[i * 2 + 1] = val & 0xff; 2032 } 2033 2034 return 0; 2035 } 2036 2037 static int _mv88e6xxx_atu_load(struct mv88e6xxx_chip *chip, 2038 struct mv88e6xxx_atu_entry *entry) 2039 { 2040 int ret; 2041 2042 ret = _mv88e6xxx_atu_wait(chip); 2043 if (ret < 0) 2044 return ret; 2045 2046 ret = _mv88e6xxx_atu_mac_write(chip, entry->mac); 2047 if (ret < 0) 2048 return ret; 2049 2050 ret = _mv88e6xxx_atu_data_write(chip, entry); 2051 if (ret < 0) 2052 return ret; 2053 2054 return _mv88e6xxx_atu_cmd(chip, entry->fid, GLOBAL_ATU_OP_LOAD_DB); 2055 } 2056 2057 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2058 struct mv88e6xxx_atu_entry *entry); 2059 2060 static int mv88e6xxx_atu_get(struct mv88e6xxx_chip *chip, int fid, 2061 const u8 *addr, struct mv88e6xxx_atu_entry *entry) 2062 { 2063 struct mv88e6xxx_atu_entry next; 2064 int err; 2065 2066 memcpy(next.mac, addr, ETH_ALEN); 2067 eth_addr_dec(next.mac); 2068 2069 err = _mv88e6xxx_atu_mac_write(chip, next.mac); 2070 if (err) 2071 return err; 2072 2073 do { 2074 err = _mv88e6xxx_atu_getnext(chip, fid, &next); 2075 if (err) 2076 return err; 2077 2078 if (next.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2079 break; 2080 2081 if (ether_addr_equal(next.mac, addr)) { 2082 *entry = next; 2083 return 0; 2084 } 2085 } while (ether_addr_greater(addr, next.mac)); 2086 2087 memset(entry, 0, sizeof(*entry)); 2088 entry->fid = fid; 2089 ether_addr_copy(entry->mac, addr); 2090 2091 return 0; 2092 } 2093 2094 static int mv88e6xxx_port_db_load_purge(struct mv88e6xxx_chip *chip, int port, 2095 const unsigned char *addr, u16 vid, 2096 u8 state) 2097 { 2098 struct mv88e6xxx_vtu_entry vlan; 2099 struct mv88e6xxx_atu_entry entry; 2100 int err; 2101 2102 /* Null VLAN ID corresponds to the port private database */ 2103 if (vid == 0) 2104 err = mv88e6xxx_port_get_fid(chip, port, &vlan.fid); 2105 else 2106 err = _mv88e6xxx_vtu_get(chip, vid, &vlan, false); 2107 if (err) 2108 return err; 2109 2110 err = mv88e6xxx_atu_get(chip, vlan.fid, addr, &entry); 2111 if (err) 2112 return err; 2113 2114 /* Purge the ATU entry only if no port is using it anymore */ 2115 if (state == GLOBAL_ATU_DATA_STATE_UNUSED) { 2116 entry.portv_trunkid &= ~BIT(port); 2117 if (!entry.portv_trunkid) 2118 entry.state = GLOBAL_ATU_DATA_STATE_UNUSED; 2119 } else { 2120 entry.portv_trunkid |= BIT(port); 2121 entry.state = state; 2122 } 2123 2124 return _mv88e6xxx_atu_load(chip, &entry); 2125 } 2126 2127 static int mv88e6xxx_port_fdb_prepare(struct dsa_switch *ds, int port, 2128 const struct switchdev_obj_port_fdb *fdb, 2129 struct switchdev_trans *trans) 2130 { 2131 /* We don't need any dynamic resource from the kernel (yet), 2132 * so skip the prepare phase. 2133 */ 2134 return 0; 2135 } 2136 2137 static void mv88e6xxx_port_fdb_add(struct dsa_switch *ds, int port, 2138 const struct switchdev_obj_port_fdb *fdb, 2139 struct switchdev_trans *trans) 2140 { 2141 struct mv88e6xxx_chip *chip = ds->priv; 2142 2143 mutex_lock(&chip->reg_lock); 2144 if (mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2145 GLOBAL_ATU_DATA_STATE_UC_STATIC)) 2146 netdev_err(ds->ports[port].netdev, "failed to load unicast MAC address\n"); 2147 mutex_unlock(&chip->reg_lock); 2148 } 2149 2150 static int mv88e6xxx_port_fdb_del(struct dsa_switch *ds, int port, 2151 const struct switchdev_obj_port_fdb *fdb) 2152 { 2153 struct mv88e6xxx_chip *chip = ds->priv; 2154 int err; 2155 2156 mutex_lock(&chip->reg_lock); 2157 err = mv88e6xxx_port_db_load_purge(chip, port, fdb->addr, fdb->vid, 2158 GLOBAL_ATU_DATA_STATE_UNUSED); 2159 mutex_unlock(&chip->reg_lock); 2160 2161 return err; 2162 } 2163 2164 static int _mv88e6xxx_atu_getnext(struct mv88e6xxx_chip *chip, u16 fid, 2165 struct mv88e6xxx_atu_entry *entry) 2166 { 2167 struct mv88e6xxx_atu_entry next = { 0 }; 2168 u16 val; 2169 int err; 2170 2171 next.fid = fid; 2172 2173 err = _mv88e6xxx_atu_wait(chip); 2174 if (err) 2175 return err; 2176 2177 err = _mv88e6xxx_atu_cmd(chip, fid, GLOBAL_ATU_OP_GET_NEXT_DB); 2178 if (err) 2179 return err; 2180 2181 err = _mv88e6xxx_atu_mac_read(chip, next.mac); 2182 if (err) 2183 return err; 2184 2185 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_DATA, &val); 2186 if (err) 2187 return err; 2188 2189 next.state = val & GLOBAL_ATU_DATA_STATE_MASK; 2190 if (next.state != GLOBAL_ATU_DATA_STATE_UNUSED) { 2191 unsigned int mask, shift; 2192 2193 if (val & GLOBAL_ATU_DATA_TRUNK) { 2194 next.trunk = true; 2195 mask = GLOBAL_ATU_DATA_TRUNK_ID_MASK; 2196 shift = GLOBAL_ATU_DATA_TRUNK_ID_SHIFT; 2197 } else { 2198 next.trunk = false; 2199 mask = GLOBAL_ATU_DATA_PORT_VECTOR_MASK; 2200 shift = GLOBAL_ATU_DATA_PORT_VECTOR_SHIFT; 2201 } 2202 2203 next.portv_trunkid = (val & mask) >> shift; 2204 } 2205 2206 *entry = next; 2207 return 0; 2208 } 2209 2210 static int mv88e6xxx_port_db_dump_fid(struct mv88e6xxx_chip *chip, 2211 u16 fid, u16 vid, int port, 2212 struct switchdev_obj *obj, 2213 int (*cb)(struct switchdev_obj *obj)) 2214 { 2215 struct mv88e6xxx_atu_entry addr = { 2216 .mac = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }, 2217 }; 2218 int err; 2219 2220 err = _mv88e6xxx_atu_mac_write(chip, addr.mac); 2221 if (err) 2222 return err; 2223 2224 do { 2225 err = _mv88e6xxx_atu_getnext(chip, fid, &addr); 2226 if (err) 2227 return err; 2228 2229 if (addr.state == GLOBAL_ATU_DATA_STATE_UNUSED) 2230 break; 2231 2232 if (addr.trunk || (addr.portv_trunkid & BIT(port)) == 0) 2233 continue; 2234 2235 if (obj->id == SWITCHDEV_OBJ_ID_PORT_FDB) { 2236 struct switchdev_obj_port_fdb *fdb; 2237 2238 if (!is_unicast_ether_addr(addr.mac)) 2239 continue; 2240 2241 fdb = SWITCHDEV_OBJ_PORT_FDB(obj); 2242 fdb->vid = vid; 2243 ether_addr_copy(fdb->addr, addr.mac); 2244 if (addr.state == GLOBAL_ATU_DATA_STATE_UC_STATIC) 2245 fdb->ndm_state = NUD_NOARP; 2246 else 2247 fdb->ndm_state = NUD_REACHABLE; 2248 } else if (obj->id == SWITCHDEV_OBJ_ID_PORT_MDB) { 2249 struct switchdev_obj_port_mdb *mdb; 2250 2251 if (!is_multicast_ether_addr(addr.mac)) 2252 continue; 2253 2254 mdb = SWITCHDEV_OBJ_PORT_MDB(obj); 2255 mdb->vid = vid; 2256 ether_addr_copy(mdb->addr, addr.mac); 2257 } else { 2258 return -EOPNOTSUPP; 2259 } 2260 2261 err = cb(obj); 2262 if (err) 2263 return err; 2264 } while (!is_broadcast_ether_addr(addr.mac)); 2265 2266 return err; 2267 } 2268 2269 static int mv88e6xxx_port_db_dump(struct mv88e6xxx_chip *chip, int port, 2270 struct switchdev_obj *obj, 2271 int (*cb)(struct switchdev_obj *obj)) 2272 { 2273 struct mv88e6xxx_vtu_entry vlan = { 2274 .vid = GLOBAL_VTU_VID_MASK, /* all ones */ 2275 }; 2276 u16 fid; 2277 int err; 2278 2279 /* Dump port's default Filtering Information Database (VLAN ID 0) */ 2280 err = mv88e6xxx_port_get_fid(chip, port, &fid); 2281 if (err) 2282 return err; 2283 2284 err = mv88e6xxx_port_db_dump_fid(chip, fid, 0, port, obj, cb); 2285 if (err) 2286 return err; 2287 2288 /* Dump VLANs' Filtering Information Databases */ 2289 err = _mv88e6xxx_vtu_vid_write(chip, vlan.vid); 2290 if (err) 2291 return err; 2292 2293 do { 2294 err = _mv88e6xxx_vtu_getnext(chip, &vlan); 2295 if (err) 2296 return err; 2297 2298 if (!vlan.valid) 2299 break; 2300 2301 err = mv88e6xxx_port_db_dump_fid(chip, vlan.fid, vlan.vid, port, 2302 obj, cb); 2303 if (err) 2304 return err; 2305 } while (vlan.vid < GLOBAL_VTU_VID_MASK); 2306 2307 return err; 2308 } 2309 2310 static int mv88e6xxx_port_fdb_dump(struct dsa_switch *ds, int port, 2311 struct switchdev_obj_port_fdb *fdb, 2312 int (*cb)(struct switchdev_obj *obj)) 2313 { 2314 struct mv88e6xxx_chip *chip = ds->priv; 2315 int err; 2316 2317 mutex_lock(&chip->reg_lock); 2318 err = mv88e6xxx_port_db_dump(chip, port, &fdb->obj, cb); 2319 mutex_unlock(&chip->reg_lock); 2320 2321 return err; 2322 } 2323 2324 static int mv88e6xxx_port_bridge_join(struct dsa_switch *ds, int port, 2325 struct net_device *br) 2326 { 2327 struct mv88e6xxx_chip *chip = ds->priv; 2328 int i, err = 0; 2329 2330 mutex_lock(&chip->reg_lock); 2331 2332 /* Remap each port's VLANTable */ 2333 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) { 2334 if (ds->ports[i].bridge_dev == br) { 2335 err = _mv88e6xxx_port_based_vlan_map(chip, i); 2336 if (err) 2337 break; 2338 } 2339 } 2340 2341 mutex_unlock(&chip->reg_lock); 2342 2343 return err; 2344 } 2345 2346 static void mv88e6xxx_port_bridge_leave(struct dsa_switch *ds, int port, 2347 struct net_device *br) 2348 { 2349 struct mv88e6xxx_chip *chip = ds->priv; 2350 int i; 2351 2352 mutex_lock(&chip->reg_lock); 2353 2354 /* Remap each port's VLANTable */ 2355 for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) 2356 if (i == port || ds->ports[i].bridge_dev == br) 2357 if (_mv88e6xxx_port_based_vlan_map(chip, i)) 2358 netdev_warn(ds->ports[i].netdev, 2359 "failed to remap\n"); 2360 2361 mutex_unlock(&chip->reg_lock); 2362 } 2363 2364 static int mv88e6xxx_software_reset(struct mv88e6xxx_chip *chip) 2365 { 2366 if (chip->info->ops->reset) 2367 return chip->info->ops->reset(chip); 2368 2369 return 0; 2370 } 2371 2372 static void mv88e6xxx_hardware_reset(struct mv88e6xxx_chip *chip) 2373 { 2374 struct gpio_desc *gpiod = chip->reset; 2375 2376 /* If there is a GPIO connected to the reset pin, toggle it */ 2377 if (gpiod) { 2378 gpiod_set_value_cansleep(gpiod, 1); 2379 usleep_range(10000, 20000); 2380 gpiod_set_value_cansleep(gpiod, 0); 2381 usleep_range(10000, 20000); 2382 } 2383 } 2384 2385 static int mv88e6xxx_disable_ports(struct mv88e6xxx_chip *chip) 2386 { 2387 int i, err; 2388 2389 /* Set all ports to the Disabled state */ 2390 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2391 err = mv88e6xxx_port_set_state(chip, i, 2392 PORT_CONTROL_STATE_DISABLED); 2393 if (err) 2394 return err; 2395 } 2396 2397 /* Wait for transmit queues to drain, 2398 * i.e. 2ms for a maximum frame to be transmitted at 10 Mbps. 2399 */ 2400 usleep_range(2000, 4000); 2401 2402 return 0; 2403 } 2404 2405 static int mv88e6xxx_switch_reset(struct mv88e6xxx_chip *chip) 2406 { 2407 int err; 2408 2409 err = mv88e6xxx_disable_ports(chip); 2410 if (err) 2411 return err; 2412 2413 mv88e6xxx_hardware_reset(chip); 2414 2415 return mv88e6xxx_software_reset(chip); 2416 } 2417 2418 static int mv88e6xxx_serdes_power_on(struct mv88e6xxx_chip *chip) 2419 { 2420 u16 val; 2421 int err; 2422 2423 /* Clear Power Down bit */ 2424 err = mv88e6xxx_serdes_read(chip, MII_BMCR, &val); 2425 if (err) 2426 return err; 2427 2428 if (val & BMCR_PDOWN) { 2429 val &= ~BMCR_PDOWN; 2430 err = mv88e6xxx_serdes_write(chip, MII_BMCR, val); 2431 } 2432 2433 return err; 2434 } 2435 2436 static int mv88e6xxx_setup_port_dsa(struct mv88e6xxx_chip *chip, int port, 2437 int upstream_port) 2438 { 2439 int err; 2440 2441 err = chip->info->ops->port_set_frame_mode( 2442 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2443 if (err) 2444 return err; 2445 2446 return chip->info->ops->port_set_egress_unknowns( 2447 chip, port, port == upstream_port); 2448 } 2449 2450 static int mv88e6xxx_setup_port_cpu(struct mv88e6xxx_chip *chip, int port) 2451 { 2452 int err; 2453 2454 switch (chip->info->tag_protocol) { 2455 case DSA_TAG_PROTO_EDSA: 2456 err = chip->info->ops->port_set_frame_mode( 2457 chip, port, MV88E6XXX_FRAME_MODE_ETHERTYPE); 2458 if (err) 2459 return err; 2460 2461 err = mv88e6xxx_port_set_egress_mode( 2462 chip, port, PORT_CONTROL_EGRESS_ADD_TAG); 2463 if (err) 2464 return err; 2465 2466 if (chip->info->ops->port_set_ether_type) 2467 err = chip->info->ops->port_set_ether_type( 2468 chip, port, ETH_P_EDSA); 2469 break; 2470 2471 case DSA_TAG_PROTO_DSA: 2472 err = chip->info->ops->port_set_frame_mode( 2473 chip, port, MV88E6XXX_FRAME_MODE_DSA); 2474 if (err) 2475 return err; 2476 2477 err = mv88e6xxx_port_set_egress_mode( 2478 chip, port, PORT_CONTROL_EGRESS_UNMODIFIED); 2479 break; 2480 default: 2481 err = -EINVAL; 2482 } 2483 2484 if (err) 2485 return err; 2486 2487 return chip->info->ops->port_set_egress_unknowns(chip, port, true); 2488 } 2489 2490 static int mv88e6xxx_setup_port_normal(struct mv88e6xxx_chip *chip, int port) 2491 { 2492 int err; 2493 2494 err = chip->info->ops->port_set_frame_mode( 2495 chip, port, MV88E6XXX_FRAME_MODE_NORMAL); 2496 if (err) 2497 return err; 2498 2499 return chip->info->ops->port_set_egress_unknowns(chip, port, false); 2500 } 2501 2502 static int mv88e6xxx_setup_port(struct mv88e6xxx_chip *chip, int port) 2503 { 2504 struct dsa_switch *ds = chip->ds; 2505 int err; 2506 u16 reg; 2507 2508 /* MAC Forcing register: don't force link, speed, duplex or flow control 2509 * state to any particular values on physical ports, but force the CPU 2510 * port and all DSA ports to their maximum bandwidth and full duplex. 2511 */ 2512 if (dsa_is_cpu_port(ds, port) || dsa_is_dsa_port(ds, port)) 2513 err = mv88e6xxx_port_setup_mac(chip, port, LINK_FORCED_UP, 2514 SPEED_MAX, DUPLEX_FULL, 2515 PHY_INTERFACE_MODE_NA); 2516 else 2517 err = mv88e6xxx_port_setup_mac(chip, port, LINK_UNFORCED, 2518 SPEED_UNFORCED, DUPLEX_UNFORCED, 2519 PHY_INTERFACE_MODE_NA); 2520 if (err) 2521 return err; 2522 2523 /* Port Control: disable Drop-on-Unlock, disable Drop-on-Lock, 2524 * disable Header mode, enable IGMP/MLD snooping, disable VLAN 2525 * tunneling, determine priority by looking at 802.1p and IP 2526 * priority fields (IP prio has precedence), and set STP state 2527 * to Forwarding. 2528 * 2529 * If this is the CPU link, use DSA or EDSA tagging depending 2530 * on which tagging mode was configured. 2531 * 2532 * If this is a link to another switch, use DSA tagging mode. 2533 * 2534 * If this is the upstream port for this switch, enable 2535 * forwarding of unknown unicasts and multicasts. 2536 */ 2537 reg = PORT_CONTROL_IGMP_MLD_SNOOP | 2538 PORT_CONTROL_USE_TAG | PORT_CONTROL_USE_IP | 2539 PORT_CONTROL_STATE_FORWARDING; 2540 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL, reg); 2541 if (err) 2542 return err; 2543 2544 if (dsa_is_cpu_port(ds, port)) { 2545 err = mv88e6xxx_setup_port_cpu(chip, port); 2546 } else if (dsa_is_dsa_port(ds, port)) { 2547 err = mv88e6xxx_setup_port_dsa(chip, port, 2548 dsa_upstream_port(ds)); 2549 } else { 2550 err = mv88e6xxx_setup_port_normal(chip, port); 2551 } 2552 if (err) 2553 return err; 2554 2555 /* If this port is connected to a SerDes, make sure the SerDes is not 2556 * powered down. 2557 */ 2558 if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_SERDES)) { 2559 err = mv88e6xxx_port_read(chip, port, PORT_STATUS, ®); 2560 if (err) 2561 return err; 2562 reg &= PORT_STATUS_CMODE_MASK; 2563 if ((reg == PORT_STATUS_CMODE_100BASE_X) || 2564 (reg == PORT_STATUS_CMODE_1000BASE_X) || 2565 (reg == PORT_STATUS_CMODE_SGMII)) { 2566 err = mv88e6xxx_serdes_power_on(chip); 2567 if (err < 0) 2568 return err; 2569 } 2570 } 2571 2572 /* Port Control 2: don't force a good FCS, set the maximum frame size to 2573 * 10240 bytes, disable 802.1q tags checking, don't discard tagged or 2574 * untagged frames on this port, do a destination address lookup on all 2575 * received packets as usual, disable ARP mirroring and don't send a 2576 * copy of all transmitted/received frames on this port to the CPU. 2577 */ 2578 err = mv88e6xxx_port_set_map_da(chip, port); 2579 if (err) 2580 return err; 2581 2582 reg = 0; 2583 if (chip->info->ops->port_set_upstream_port) { 2584 err = chip->info->ops->port_set_upstream_port( 2585 chip, port, dsa_upstream_port(ds)); 2586 if (err) 2587 return err; 2588 } 2589 2590 err = mv88e6xxx_port_set_8021q_mode(chip, port, 2591 PORT_CONTROL_2_8021Q_DISABLED); 2592 if (err) 2593 return err; 2594 2595 if (chip->info->ops->port_jumbo_config) { 2596 err = chip->info->ops->port_jumbo_config(chip, port); 2597 if (err) 2598 return err; 2599 } 2600 2601 /* Port Association Vector: when learning source addresses 2602 * of packets, add the address to the address database using 2603 * a port bitmap that has only the bit for this port set and 2604 * the other bits clear. 2605 */ 2606 reg = 1 << port; 2607 /* Disable learning for CPU port */ 2608 if (dsa_is_cpu_port(ds, port)) 2609 reg = 0; 2610 2611 err = mv88e6xxx_port_write(chip, port, PORT_ASSOC_VECTOR, reg); 2612 if (err) 2613 return err; 2614 2615 /* Egress rate control 2: disable egress rate control. */ 2616 err = mv88e6xxx_port_write(chip, port, PORT_RATE_CONTROL_2, 0x0000); 2617 if (err) 2618 return err; 2619 2620 if (chip->info->ops->port_pause_config) { 2621 err = chip->info->ops->port_pause_config(chip, port); 2622 if (err) 2623 return err; 2624 } 2625 2626 if (mv88e6xxx_6352_family(chip) || mv88e6xxx_6351_family(chip) || 2627 mv88e6xxx_6165_family(chip) || mv88e6xxx_6097_family(chip) || 2628 mv88e6xxx_6320_family(chip) || mv88e6xxx_6341_family(chip)) { 2629 /* Port ATU control: disable limiting the number of 2630 * address database entries that this port is allowed 2631 * to use. 2632 */ 2633 err = mv88e6xxx_port_write(chip, port, PORT_ATU_CONTROL, 2634 0x0000); 2635 /* Priority Override: disable DA, SA and VTU priority 2636 * override. 2637 */ 2638 err = mv88e6xxx_port_write(chip, port, PORT_PRI_OVERRIDE, 2639 0x0000); 2640 if (err) 2641 return err; 2642 } 2643 2644 if (chip->info->ops->port_tag_remap) { 2645 err = chip->info->ops->port_tag_remap(chip, port); 2646 if (err) 2647 return err; 2648 } 2649 2650 if (chip->info->ops->port_egress_rate_limiting) { 2651 err = chip->info->ops->port_egress_rate_limiting(chip, port); 2652 if (err) 2653 return err; 2654 } 2655 2656 /* Port Control 1: disable trunking, disable sending 2657 * learning messages to this port. 2658 */ 2659 err = mv88e6xxx_port_write(chip, port, PORT_CONTROL_1, 0x0000); 2660 if (err) 2661 return err; 2662 2663 /* Port based VLAN map: give each port the same default address 2664 * database, and allow bidirectional communication between the 2665 * CPU and DSA port(s), and the other ports. 2666 */ 2667 err = mv88e6xxx_port_set_fid(chip, port, 0); 2668 if (err) 2669 return err; 2670 2671 err = _mv88e6xxx_port_based_vlan_map(chip, port); 2672 if (err) 2673 return err; 2674 2675 /* Default VLAN ID and priority: don't set a default VLAN 2676 * ID, and set the default packet priority to zero. 2677 */ 2678 return mv88e6xxx_port_write(chip, port, PORT_DEFAULT_VLAN, 0x0000); 2679 } 2680 2681 static int mv88e6xxx_g1_set_switch_mac(struct mv88e6xxx_chip *chip, u8 *addr) 2682 { 2683 int err; 2684 2685 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_01, (addr[0] << 8) | addr[1]); 2686 if (err) 2687 return err; 2688 2689 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_23, (addr[2] << 8) | addr[3]); 2690 if (err) 2691 return err; 2692 2693 err = mv88e6xxx_g1_write(chip, GLOBAL_MAC_45, (addr[4] << 8) | addr[5]); 2694 if (err) 2695 return err; 2696 2697 return 0; 2698 } 2699 2700 static int mv88e6xxx_g1_set_age_time(struct mv88e6xxx_chip *chip, 2701 unsigned int msecs) 2702 { 2703 const unsigned int coeff = chip->info->age_time_coeff; 2704 const unsigned int min = 0x01 * coeff; 2705 const unsigned int max = 0xff * coeff; 2706 u8 age_time; 2707 u16 val; 2708 int err; 2709 2710 if (msecs < min || msecs > max) 2711 return -ERANGE; 2712 2713 /* Round to nearest multiple of coeff */ 2714 age_time = (msecs + coeff / 2) / coeff; 2715 2716 err = mv88e6xxx_g1_read(chip, GLOBAL_ATU_CONTROL, &val); 2717 if (err) 2718 return err; 2719 2720 /* AgeTime is 11:4 bits */ 2721 val &= ~0xff0; 2722 val |= age_time << 4; 2723 2724 return mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, val); 2725 } 2726 2727 static int mv88e6xxx_set_ageing_time(struct dsa_switch *ds, 2728 unsigned int ageing_time) 2729 { 2730 struct mv88e6xxx_chip *chip = ds->priv; 2731 int err; 2732 2733 mutex_lock(&chip->reg_lock); 2734 err = mv88e6xxx_g1_set_age_time(chip, ageing_time); 2735 mutex_unlock(&chip->reg_lock); 2736 2737 return err; 2738 } 2739 2740 static int mv88e6xxx_g1_setup(struct mv88e6xxx_chip *chip) 2741 { 2742 struct dsa_switch *ds = chip->ds; 2743 u32 upstream_port = dsa_upstream_port(ds); 2744 int err; 2745 2746 /* Enable the PHY Polling Unit if present, don't discard any packets, 2747 * and mask all interrupt sources. 2748 */ 2749 err = mv88e6xxx_ppu_enable(chip); 2750 if (err) 2751 return err; 2752 2753 if (chip->info->ops->g1_set_cpu_port) { 2754 err = chip->info->ops->g1_set_cpu_port(chip, upstream_port); 2755 if (err) 2756 return err; 2757 } 2758 2759 if (chip->info->ops->g1_set_egress_port) { 2760 err = chip->info->ops->g1_set_egress_port(chip, upstream_port); 2761 if (err) 2762 return err; 2763 } 2764 2765 /* Disable remote management, and set the switch's DSA device number. */ 2766 err = mv88e6xxx_g1_write(chip, GLOBAL_CONTROL_2, 2767 GLOBAL_CONTROL_2_MULTIPLE_CASCADE | 2768 (ds->index & 0x1f)); 2769 if (err) 2770 return err; 2771 2772 /* Clear all the VTU and STU entries */ 2773 err = _mv88e6xxx_vtu_stu_flush(chip); 2774 if (err < 0) 2775 return err; 2776 2777 /* Set the default address aging time to 5 minutes, and 2778 * enable address learn messages to be sent to all message 2779 * ports. 2780 */ 2781 err = mv88e6xxx_g1_write(chip, GLOBAL_ATU_CONTROL, 2782 GLOBAL_ATU_CONTROL_LEARN2ALL); 2783 if (err) 2784 return err; 2785 2786 err = mv88e6xxx_g1_set_age_time(chip, 300000); 2787 if (err) 2788 return err; 2789 2790 /* Clear all ATU entries */ 2791 err = _mv88e6xxx_atu_flush(chip, 0, true); 2792 if (err) 2793 return err; 2794 2795 /* Configure the IP ToS mapping registers. */ 2796 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_0, 0x0000); 2797 if (err) 2798 return err; 2799 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_1, 0x0000); 2800 if (err) 2801 return err; 2802 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_2, 0x5555); 2803 if (err) 2804 return err; 2805 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_3, 0x5555); 2806 if (err) 2807 return err; 2808 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_4, 0xaaaa); 2809 if (err) 2810 return err; 2811 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_5, 0xaaaa); 2812 if (err) 2813 return err; 2814 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_6, 0xffff); 2815 if (err) 2816 return err; 2817 err = mv88e6xxx_g1_write(chip, GLOBAL_IP_PRI_7, 0xffff); 2818 if (err) 2819 return err; 2820 2821 /* Configure the IEEE 802.1p priority mapping register. */ 2822 err = mv88e6xxx_g1_write(chip, GLOBAL_IEEE_PRI, 0xfa41); 2823 if (err) 2824 return err; 2825 2826 /* Initialize the statistics unit */ 2827 err = mv88e6xxx_stats_set_histogram(chip); 2828 if (err) 2829 return err; 2830 2831 /* Clear the statistics counters for all ports */ 2832 err = mv88e6xxx_g1_write(chip, GLOBAL_STATS_OP, 2833 GLOBAL_STATS_OP_FLUSH_ALL); 2834 if (err) 2835 return err; 2836 2837 /* Wait for the flush to complete. */ 2838 err = mv88e6xxx_g1_stats_wait(chip); 2839 if (err) 2840 return err; 2841 2842 return 0; 2843 } 2844 2845 static int mv88e6xxx_setup(struct dsa_switch *ds) 2846 { 2847 struct mv88e6xxx_chip *chip = ds->priv; 2848 int err; 2849 int i; 2850 2851 chip->ds = ds; 2852 ds->slave_mii_bus = mv88e6xxx_default_mdio_bus(chip); 2853 2854 mutex_lock(&chip->reg_lock); 2855 2856 /* Setup Switch Port Registers */ 2857 for (i = 0; i < mv88e6xxx_num_ports(chip); i++) { 2858 err = mv88e6xxx_setup_port(chip, i); 2859 if (err) 2860 goto unlock; 2861 } 2862 2863 /* Setup Switch Global 1 Registers */ 2864 err = mv88e6xxx_g1_setup(chip); 2865 if (err) 2866 goto unlock; 2867 2868 /* Setup Switch Global 2 Registers */ 2869 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_GLOBAL2)) { 2870 err = mv88e6xxx_g2_setup(chip); 2871 if (err) 2872 goto unlock; 2873 } 2874 2875 /* Some generations have the configuration of sending reserved 2876 * management frames to the CPU in global2, others in 2877 * global1. Hence it does not fit the two setup functions 2878 * above. 2879 */ 2880 if (chip->info->ops->mgmt_rsvd2cpu) { 2881 err = chip->info->ops->mgmt_rsvd2cpu(chip); 2882 if (err) 2883 goto unlock; 2884 } 2885 2886 unlock: 2887 mutex_unlock(&chip->reg_lock); 2888 2889 return err; 2890 } 2891 2892 static int mv88e6xxx_set_addr(struct dsa_switch *ds, u8 *addr) 2893 { 2894 struct mv88e6xxx_chip *chip = ds->priv; 2895 int err; 2896 2897 if (!chip->info->ops->set_switch_mac) 2898 return -EOPNOTSUPP; 2899 2900 mutex_lock(&chip->reg_lock); 2901 err = chip->info->ops->set_switch_mac(chip, addr); 2902 mutex_unlock(&chip->reg_lock); 2903 2904 return err; 2905 } 2906 2907 static int mv88e6xxx_mdio_read(struct mii_bus *bus, int phy, int reg) 2908 { 2909 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2910 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2911 u16 val; 2912 int err; 2913 2914 if (!chip->info->ops->phy_read) 2915 return -EOPNOTSUPP; 2916 2917 mutex_lock(&chip->reg_lock); 2918 err = chip->info->ops->phy_read(chip, bus, phy, reg, &val); 2919 mutex_unlock(&chip->reg_lock); 2920 2921 if (reg == MII_PHYSID2) { 2922 /* Some internal PHYS don't have a model number. Use 2923 * the mv88e6390 family model number instead. 2924 */ 2925 if (!(val & 0x3f0)) 2926 val |= PORT_SWITCH_ID_PROD_NUM_6390; 2927 } 2928 2929 return err ? err : val; 2930 } 2931 2932 static int mv88e6xxx_mdio_write(struct mii_bus *bus, int phy, int reg, u16 val) 2933 { 2934 struct mv88e6xxx_mdio_bus *mdio_bus = bus->priv; 2935 struct mv88e6xxx_chip *chip = mdio_bus->chip; 2936 int err; 2937 2938 if (!chip->info->ops->phy_write) 2939 return -EOPNOTSUPP; 2940 2941 mutex_lock(&chip->reg_lock); 2942 err = chip->info->ops->phy_write(chip, bus, phy, reg, val); 2943 mutex_unlock(&chip->reg_lock); 2944 2945 return err; 2946 } 2947 2948 static int mv88e6xxx_mdio_register(struct mv88e6xxx_chip *chip, 2949 struct device_node *np, 2950 bool external) 2951 { 2952 static int index; 2953 struct mv88e6xxx_mdio_bus *mdio_bus; 2954 struct mii_bus *bus; 2955 int err; 2956 2957 bus = devm_mdiobus_alloc_size(chip->dev, sizeof(*mdio_bus)); 2958 if (!bus) 2959 return -ENOMEM; 2960 2961 mdio_bus = bus->priv; 2962 mdio_bus->bus = bus; 2963 mdio_bus->chip = chip; 2964 INIT_LIST_HEAD(&mdio_bus->list); 2965 mdio_bus->external = external; 2966 2967 if (np) { 2968 bus->name = np->full_name; 2969 snprintf(bus->id, MII_BUS_ID_SIZE, "%s", np->full_name); 2970 } else { 2971 bus->name = "mv88e6xxx SMI"; 2972 snprintf(bus->id, MII_BUS_ID_SIZE, "mv88e6xxx-%d", index++); 2973 } 2974 2975 bus->read = mv88e6xxx_mdio_read; 2976 bus->write = mv88e6xxx_mdio_write; 2977 bus->parent = chip->dev; 2978 2979 if (np) 2980 err = of_mdiobus_register(bus, np); 2981 else 2982 err = mdiobus_register(bus); 2983 if (err) { 2984 dev_err(chip->dev, "Cannot register MDIO bus (%d)\n", err); 2985 return err; 2986 } 2987 2988 if (external) 2989 list_add_tail(&mdio_bus->list, &chip->mdios); 2990 else 2991 list_add(&mdio_bus->list, &chip->mdios); 2992 2993 return 0; 2994 } 2995 2996 static const struct of_device_id mv88e6xxx_mdio_external_match[] = { 2997 { .compatible = "marvell,mv88e6xxx-mdio-external", 2998 .data = (void *)true }, 2999 { }, 3000 }; 3001 3002 static int mv88e6xxx_mdios_register(struct mv88e6xxx_chip *chip, 3003 struct device_node *np) 3004 { 3005 const struct of_device_id *match; 3006 struct device_node *child; 3007 int err; 3008 3009 /* Always register one mdio bus for the internal/default mdio 3010 * bus. This maybe represented in the device tree, but is 3011 * optional. 3012 */ 3013 child = of_get_child_by_name(np, "mdio"); 3014 err = mv88e6xxx_mdio_register(chip, child, false); 3015 if (err) 3016 return err; 3017 3018 /* Walk the device tree, and see if there are any other nodes 3019 * which say they are compatible with the external mdio 3020 * bus. 3021 */ 3022 for_each_available_child_of_node(np, child) { 3023 match = of_match_node(mv88e6xxx_mdio_external_match, child); 3024 if (match) { 3025 err = mv88e6xxx_mdio_register(chip, child, true); 3026 if (err) 3027 return err; 3028 } 3029 } 3030 3031 return 0; 3032 } 3033 3034 static void mv88e6xxx_mdios_unregister(struct mv88e6xxx_chip *chip) 3035 3036 { 3037 struct mv88e6xxx_mdio_bus *mdio_bus; 3038 struct mii_bus *bus; 3039 3040 list_for_each_entry(mdio_bus, &chip->mdios, list) { 3041 bus = mdio_bus->bus; 3042 3043 mdiobus_unregister(bus); 3044 } 3045 } 3046 3047 static int mv88e6xxx_get_eeprom_len(struct dsa_switch *ds) 3048 { 3049 struct mv88e6xxx_chip *chip = ds->priv; 3050 3051 return chip->eeprom_len; 3052 } 3053 3054 static int mv88e6xxx_get_eeprom(struct dsa_switch *ds, 3055 struct ethtool_eeprom *eeprom, u8 *data) 3056 { 3057 struct mv88e6xxx_chip *chip = ds->priv; 3058 int err; 3059 3060 if (!chip->info->ops->get_eeprom) 3061 return -EOPNOTSUPP; 3062 3063 mutex_lock(&chip->reg_lock); 3064 err = chip->info->ops->get_eeprom(chip, eeprom, data); 3065 mutex_unlock(&chip->reg_lock); 3066 3067 if (err) 3068 return err; 3069 3070 eeprom->magic = 0xc3ec4951; 3071 3072 return 0; 3073 } 3074 3075 static int mv88e6xxx_set_eeprom(struct dsa_switch *ds, 3076 struct ethtool_eeprom *eeprom, u8 *data) 3077 { 3078 struct mv88e6xxx_chip *chip = ds->priv; 3079 int err; 3080 3081 if (!chip->info->ops->set_eeprom) 3082 return -EOPNOTSUPP; 3083 3084 if (eeprom->magic != 0xc3ec4951) 3085 return -EINVAL; 3086 3087 mutex_lock(&chip->reg_lock); 3088 err = chip->info->ops->set_eeprom(chip, eeprom, data); 3089 mutex_unlock(&chip->reg_lock); 3090 3091 return err; 3092 } 3093 3094 static const struct mv88e6xxx_ops mv88e6085_ops = { 3095 /* MV88E6XXX_FAMILY_6097 */ 3096 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3097 .phy_read = mv88e6xxx_phy_ppu_read, 3098 .phy_write = mv88e6xxx_phy_ppu_write, 3099 .port_set_link = mv88e6xxx_port_set_link, 3100 .port_set_duplex = mv88e6xxx_port_set_duplex, 3101 .port_set_speed = mv88e6185_port_set_speed, 3102 .port_tag_remap = mv88e6095_port_tag_remap, 3103 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3104 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3105 .port_set_ether_type = mv88e6351_port_set_ether_type, 3106 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3107 .port_pause_config = mv88e6097_port_pause_config, 3108 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3109 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3110 .stats_get_strings = mv88e6095_stats_get_strings, 3111 .stats_get_stats = mv88e6095_stats_get_stats, 3112 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3113 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3114 .watchdog_ops = &mv88e6097_watchdog_ops, 3115 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3116 .ppu_enable = mv88e6185_g1_ppu_enable, 3117 .ppu_disable = mv88e6185_g1_ppu_disable, 3118 .reset = mv88e6185_g1_reset, 3119 }; 3120 3121 static const struct mv88e6xxx_ops mv88e6095_ops = { 3122 /* MV88E6XXX_FAMILY_6095 */ 3123 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3124 .phy_read = mv88e6xxx_phy_ppu_read, 3125 .phy_write = mv88e6xxx_phy_ppu_write, 3126 .port_set_link = mv88e6xxx_port_set_link, 3127 .port_set_duplex = mv88e6xxx_port_set_duplex, 3128 .port_set_speed = mv88e6185_port_set_speed, 3129 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3130 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns, 3131 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3132 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3133 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3134 .stats_get_strings = mv88e6095_stats_get_strings, 3135 .stats_get_stats = mv88e6095_stats_get_stats, 3136 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3137 .ppu_enable = mv88e6185_g1_ppu_enable, 3138 .ppu_disable = mv88e6185_g1_ppu_disable, 3139 .reset = mv88e6185_g1_reset, 3140 }; 3141 3142 static const struct mv88e6xxx_ops mv88e6097_ops = { 3143 /* MV88E6XXX_FAMILY_6097 */ 3144 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3145 .phy_read = mv88e6xxx_g2_smi_phy_read, 3146 .phy_write = mv88e6xxx_g2_smi_phy_write, 3147 .port_set_link = mv88e6xxx_port_set_link, 3148 .port_set_duplex = mv88e6xxx_port_set_duplex, 3149 .port_set_speed = mv88e6185_port_set_speed, 3150 .port_tag_remap = mv88e6095_port_tag_remap, 3151 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3152 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3153 .port_set_ether_type = mv88e6351_port_set_ether_type, 3154 .port_jumbo_config = mv88e6165_port_jumbo_config, 3155 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3156 .port_pause_config = mv88e6097_port_pause_config, 3157 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3158 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3159 .stats_get_strings = mv88e6095_stats_get_strings, 3160 .stats_get_stats = mv88e6095_stats_get_stats, 3161 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3162 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3163 .watchdog_ops = &mv88e6097_watchdog_ops, 3164 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3165 .reset = mv88e6352_g1_reset, 3166 }; 3167 3168 static const struct mv88e6xxx_ops mv88e6123_ops = { 3169 /* MV88E6XXX_FAMILY_6165 */ 3170 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3171 .phy_read = mv88e6165_phy_read, 3172 .phy_write = mv88e6165_phy_write, 3173 .port_set_link = mv88e6xxx_port_set_link, 3174 .port_set_duplex = mv88e6xxx_port_set_duplex, 3175 .port_set_speed = mv88e6185_port_set_speed, 3176 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3177 .port_set_egress_unknowns = mv88e6085_port_set_egress_unknowns, 3178 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3179 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3180 .stats_get_strings = mv88e6095_stats_get_strings, 3181 .stats_get_stats = mv88e6095_stats_get_stats, 3182 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3183 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3184 .watchdog_ops = &mv88e6097_watchdog_ops, 3185 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3186 .reset = mv88e6352_g1_reset, 3187 }; 3188 3189 static const struct mv88e6xxx_ops mv88e6131_ops = { 3190 /* MV88E6XXX_FAMILY_6185 */ 3191 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3192 .phy_read = mv88e6xxx_phy_ppu_read, 3193 .phy_write = mv88e6xxx_phy_ppu_write, 3194 .port_set_link = mv88e6xxx_port_set_link, 3195 .port_set_duplex = mv88e6xxx_port_set_duplex, 3196 .port_set_speed = mv88e6185_port_set_speed, 3197 .port_tag_remap = mv88e6095_port_tag_remap, 3198 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3199 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns, 3200 .port_set_ether_type = mv88e6351_port_set_ether_type, 3201 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3202 .port_jumbo_config = mv88e6165_port_jumbo_config, 3203 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3204 .port_pause_config = mv88e6097_port_pause_config, 3205 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3206 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3207 .stats_get_strings = mv88e6095_stats_get_strings, 3208 .stats_get_stats = mv88e6095_stats_get_stats, 3209 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3210 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3211 .watchdog_ops = &mv88e6097_watchdog_ops, 3212 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3213 .ppu_enable = mv88e6185_g1_ppu_enable, 3214 .ppu_disable = mv88e6185_g1_ppu_disable, 3215 .reset = mv88e6185_g1_reset, 3216 }; 3217 3218 static const struct mv88e6xxx_ops mv88e6161_ops = { 3219 /* MV88E6XXX_FAMILY_6165 */ 3220 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3221 .phy_read = mv88e6165_phy_read, 3222 .phy_write = mv88e6165_phy_write, 3223 .port_set_link = mv88e6xxx_port_set_link, 3224 .port_set_duplex = mv88e6xxx_port_set_duplex, 3225 .port_set_speed = mv88e6185_port_set_speed, 3226 .port_tag_remap = mv88e6095_port_tag_remap, 3227 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3228 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3229 .port_set_ether_type = mv88e6351_port_set_ether_type, 3230 .port_jumbo_config = mv88e6165_port_jumbo_config, 3231 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3232 .port_pause_config = mv88e6097_port_pause_config, 3233 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3234 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3235 .stats_get_strings = mv88e6095_stats_get_strings, 3236 .stats_get_stats = mv88e6095_stats_get_stats, 3237 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3238 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3239 .watchdog_ops = &mv88e6097_watchdog_ops, 3240 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3241 .reset = mv88e6352_g1_reset, 3242 }; 3243 3244 static const struct mv88e6xxx_ops mv88e6165_ops = { 3245 /* MV88E6XXX_FAMILY_6165 */ 3246 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3247 .phy_read = mv88e6165_phy_read, 3248 .phy_write = mv88e6165_phy_write, 3249 .port_set_link = mv88e6xxx_port_set_link, 3250 .port_set_duplex = mv88e6xxx_port_set_duplex, 3251 .port_set_speed = mv88e6185_port_set_speed, 3252 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3253 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3254 .stats_get_strings = mv88e6095_stats_get_strings, 3255 .stats_get_stats = mv88e6095_stats_get_stats, 3256 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3257 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3258 .watchdog_ops = &mv88e6097_watchdog_ops, 3259 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3260 .reset = mv88e6352_g1_reset, 3261 }; 3262 3263 static const struct mv88e6xxx_ops mv88e6171_ops = { 3264 /* MV88E6XXX_FAMILY_6351 */ 3265 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3266 .phy_read = mv88e6xxx_g2_smi_phy_read, 3267 .phy_write = mv88e6xxx_g2_smi_phy_write, 3268 .port_set_link = mv88e6xxx_port_set_link, 3269 .port_set_duplex = mv88e6xxx_port_set_duplex, 3270 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3271 .port_set_speed = mv88e6185_port_set_speed, 3272 .port_tag_remap = mv88e6095_port_tag_remap, 3273 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3274 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3275 .port_set_ether_type = mv88e6351_port_set_ether_type, 3276 .port_jumbo_config = mv88e6165_port_jumbo_config, 3277 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3278 .port_pause_config = mv88e6097_port_pause_config, 3279 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3280 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3281 .stats_get_strings = mv88e6095_stats_get_strings, 3282 .stats_get_stats = mv88e6095_stats_get_stats, 3283 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3284 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3285 .watchdog_ops = &mv88e6097_watchdog_ops, 3286 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3287 .reset = mv88e6352_g1_reset, 3288 }; 3289 3290 static const struct mv88e6xxx_ops mv88e6172_ops = { 3291 /* MV88E6XXX_FAMILY_6352 */ 3292 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3293 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3294 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3295 .phy_read = mv88e6xxx_g2_smi_phy_read, 3296 .phy_write = mv88e6xxx_g2_smi_phy_write, 3297 .port_set_link = mv88e6xxx_port_set_link, 3298 .port_set_duplex = mv88e6xxx_port_set_duplex, 3299 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3300 .port_set_speed = mv88e6352_port_set_speed, 3301 .port_tag_remap = mv88e6095_port_tag_remap, 3302 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3303 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3304 .port_set_ether_type = mv88e6351_port_set_ether_type, 3305 .port_jumbo_config = mv88e6165_port_jumbo_config, 3306 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3307 .port_pause_config = mv88e6097_port_pause_config, 3308 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3309 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3310 .stats_get_strings = mv88e6095_stats_get_strings, 3311 .stats_get_stats = mv88e6095_stats_get_stats, 3312 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3313 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3314 .watchdog_ops = &mv88e6097_watchdog_ops, 3315 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3316 .reset = mv88e6352_g1_reset, 3317 }; 3318 3319 static const struct mv88e6xxx_ops mv88e6175_ops = { 3320 /* MV88E6XXX_FAMILY_6351 */ 3321 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3322 .phy_read = mv88e6xxx_g2_smi_phy_read, 3323 .phy_write = mv88e6xxx_g2_smi_phy_write, 3324 .port_set_link = mv88e6xxx_port_set_link, 3325 .port_set_duplex = mv88e6xxx_port_set_duplex, 3326 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3327 .port_set_speed = mv88e6185_port_set_speed, 3328 .port_tag_remap = mv88e6095_port_tag_remap, 3329 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3330 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3331 .port_set_ether_type = mv88e6351_port_set_ether_type, 3332 .port_jumbo_config = mv88e6165_port_jumbo_config, 3333 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3334 .port_pause_config = mv88e6097_port_pause_config, 3335 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3336 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3337 .stats_get_strings = mv88e6095_stats_get_strings, 3338 .stats_get_stats = mv88e6095_stats_get_stats, 3339 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3340 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3341 .watchdog_ops = &mv88e6097_watchdog_ops, 3342 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3343 .reset = mv88e6352_g1_reset, 3344 }; 3345 3346 static const struct mv88e6xxx_ops mv88e6176_ops = { 3347 /* MV88E6XXX_FAMILY_6352 */ 3348 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3349 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3350 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3351 .phy_read = mv88e6xxx_g2_smi_phy_read, 3352 .phy_write = mv88e6xxx_g2_smi_phy_write, 3353 .port_set_link = mv88e6xxx_port_set_link, 3354 .port_set_duplex = mv88e6xxx_port_set_duplex, 3355 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3356 .port_set_speed = mv88e6352_port_set_speed, 3357 .port_tag_remap = mv88e6095_port_tag_remap, 3358 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3359 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3360 .port_set_ether_type = mv88e6351_port_set_ether_type, 3361 .port_jumbo_config = mv88e6165_port_jumbo_config, 3362 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3363 .port_pause_config = mv88e6097_port_pause_config, 3364 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3365 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3366 .stats_get_strings = mv88e6095_stats_get_strings, 3367 .stats_get_stats = mv88e6095_stats_get_stats, 3368 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3369 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3370 .watchdog_ops = &mv88e6097_watchdog_ops, 3371 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3372 .reset = mv88e6352_g1_reset, 3373 }; 3374 3375 static const struct mv88e6xxx_ops mv88e6185_ops = { 3376 /* MV88E6XXX_FAMILY_6185 */ 3377 .set_switch_mac = mv88e6xxx_g1_set_switch_mac, 3378 .phy_read = mv88e6xxx_phy_ppu_read, 3379 .phy_write = mv88e6xxx_phy_ppu_write, 3380 .port_set_link = mv88e6xxx_port_set_link, 3381 .port_set_duplex = mv88e6xxx_port_set_duplex, 3382 .port_set_speed = mv88e6185_port_set_speed, 3383 .port_set_frame_mode = mv88e6085_port_set_frame_mode, 3384 .port_set_egress_unknowns = mv88e6095_port_set_egress_unknowns, 3385 .port_egress_rate_limiting = mv88e6095_port_egress_rate_limiting, 3386 .port_set_upstream_port = mv88e6095_port_set_upstream_port, 3387 .stats_snapshot = mv88e6xxx_g1_stats_snapshot, 3388 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3389 .stats_get_strings = mv88e6095_stats_get_strings, 3390 .stats_get_stats = mv88e6095_stats_get_stats, 3391 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3392 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3393 .watchdog_ops = &mv88e6097_watchdog_ops, 3394 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3395 .ppu_enable = mv88e6185_g1_ppu_enable, 3396 .ppu_disable = mv88e6185_g1_ppu_disable, 3397 .reset = mv88e6185_g1_reset, 3398 }; 3399 3400 static const struct mv88e6xxx_ops mv88e6190_ops = { 3401 /* MV88E6XXX_FAMILY_6390 */ 3402 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3403 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3404 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3405 .phy_read = mv88e6xxx_g2_smi_phy_read, 3406 .phy_write = mv88e6xxx_g2_smi_phy_write, 3407 .port_set_link = mv88e6xxx_port_set_link, 3408 .port_set_duplex = mv88e6xxx_port_set_duplex, 3409 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3410 .port_set_speed = mv88e6390_port_set_speed, 3411 .port_tag_remap = mv88e6390_port_tag_remap, 3412 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3413 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3414 .port_set_ether_type = mv88e6351_port_set_ether_type, 3415 .port_pause_config = mv88e6390_port_pause_config, 3416 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3417 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3418 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3419 .stats_get_strings = mv88e6320_stats_get_strings, 3420 .stats_get_stats = mv88e6390_stats_get_stats, 3421 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3422 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3423 .watchdog_ops = &mv88e6390_watchdog_ops, 3424 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3425 .reset = mv88e6352_g1_reset, 3426 }; 3427 3428 static const struct mv88e6xxx_ops mv88e6190x_ops = { 3429 /* MV88E6XXX_FAMILY_6390 */ 3430 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3431 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3432 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3433 .phy_read = mv88e6xxx_g2_smi_phy_read, 3434 .phy_write = mv88e6xxx_g2_smi_phy_write, 3435 .port_set_link = mv88e6xxx_port_set_link, 3436 .port_set_duplex = mv88e6xxx_port_set_duplex, 3437 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3438 .port_set_speed = mv88e6390x_port_set_speed, 3439 .port_tag_remap = mv88e6390_port_tag_remap, 3440 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3441 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3442 .port_set_ether_type = mv88e6351_port_set_ether_type, 3443 .port_pause_config = mv88e6390_port_pause_config, 3444 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3445 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3446 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3447 .stats_get_strings = mv88e6320_stats_get_strings, 3448 .stats_get_stats = mv88e6390_stats_get_stats, 3449 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3450 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3451 .watchdog_ops = &mv88e6390_watchdog_ops, 3452 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3453 .reset = mv88e6352_g1_reset, 3454 }; 3455 3456 static const struct mv88e6xxx_ops mv88e6191_ops = { 3457 /* MV88E6XXX_FAMILY_6390 */ 3458 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3459 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3460 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3461 .phy_read = mv88e6xxx_g2_smi_phy_read, 3462 .phy_write = mv88e6xxx_g2_smi_phy_write, 3463 .port_set_link = mv88e6xxx_port_set_link, 3464 .port_set_duplex = mv88e6xxx_port_set_duplex, 3465 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3466 .port_set_speed = mv88e6390_port_set_speed, 3467 .port_tag_remap = mv88e6390_port_tag_remap, 3468 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3469 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3470 .port_set_ether_type = mv88e6351_port_set_ether_type, 3471 .port_pause_config = mv88e6390_port_pause_config, 3472 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3473 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3474 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3475 .stats_get_strings = mv88e6320_stats_get_strings, 3476 .stats_get_stats = mv88e6390_stats_get_stats, 3477 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3478 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3479 .watchdog_ops = &mv88e6390_watchdog_ops, 3480 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3481 .reset = mv88e6352_g1_reset, 3482 }; 3483 3484 static const struct mv88e6xxx_ops mv88e6240_ops = { 3485 /* MV88E6XXX_FAMILY_6352 */ 3486 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3487 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3488 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3489 .phy_read = mv88e6xxx_g2_smi_phy_read, 3490 .phy_write = mv88e6xxx_g2_smi_phy_write, 3491 .port_set_link = mv88e6xxx_port_set_link, 3492 .port_set_duplex = mv88e6xxx_port_set_duplex, 3493 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3494 .port_set_speed = mv88e6352_port_set_speed, 3495 .port_tag_remap = mv88e6095_port_tag_remap, 3496 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3497 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3498 .port_set_ether_type = mv88e6351_port_set_ether_type, 3499 .port_jumbo_config = mv88e6165_port_jumbo_config, 3500 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3501 .port_pause_config = mv88e6097_port_pause_config, 3502 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3503 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3504 .stats_get_strings = mv88e6095_stats_get_strings, 3505 .stats_get_stats = mv88e6095_stats_get_stats, 3506 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3507 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3508 .watchdog_ops = &mv88e6097_watchdog_ops, 3509 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3510 .reset = mv88e6352_g1_reset, 3511 }; 3512 3513 static const struct mv88e6xxx_ops mv88e6290_ops = { 3514 /* MV88E6XXX_FAMILY_6390 */ 3515 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3516 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3517 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3518 .phy_read = mv88e6xxx_g2_smi_phy_read, 3519 .phy_write = mv88e6xxx_g2_smi_phy_write, 3520 .port_set_link = mv88e6xxx_port_set_link, 3521 .port_set_duplex = mv88e6xxx_port_set_duplex, 3522 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3523 .port_set_speed = mv88e6390_port_set_speed, 3524 .port_tag_remap = mv88e6390_port_tag_remap, 3525 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3526 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3527 .port_set_ether_type = mv88e6351_port_set_ether_type, 3528 .port_pause_config = mv88e6390_port_pause_config, 3529 .port_set_cmode = mv88e6390x_port_set_cmode, 3530 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3531 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3532 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3533 .stats_get_strings = mv88e6320_stats_get_strings, 3534 .stats_get_stats = mv88e6390_stats_get_stats, 3535 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3536 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3537 .watchdog_ops = &mv88e6390_watchdog_ops, 3538 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3539 .reset = mv88e6352_g1_reset, 3540 }; 3541 3542 static const struct mv88e6xxx_ops mv88e6320_ops = { 3543 /* MV88E6XXX_FAMILY_6320 */ 3544 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3545 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3546 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3547 .phy_read = mv88e6xxx_g2_smi_phy_read, 3548 .phy_write = mv88e6xxx_g2_smi_phy_write, 3549 .port_set_link = mv88e6xxx_port_set_link, 3550 .port_set_duplex = mv88e6xxx_port_set_duplex, 3551 .port_set_speed = mv88e6185_port_set_speed, 3552 .port_tag_remap = mv88e6095_port_tag_remap, 3553 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3554 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3555 .port_set_ether_type = mv88e6351_port_set_ether_type, 3556 .port_jumbo_config = mv88e6165_port_jumbo_config, 3557 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3558 .port_pause_config = mv88e6097_port_pause_config, 3559 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3560 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3561 .stats_get_strings = mv88e6320_stats_get_strings, 3562 .stats_get_stats = mv88e6320_stats_get_stats, 3563 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3564 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3565 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3566 .reset = mv88e6352_g1_reset, 3567 }; 3568 3569 static const struct mv88e6xxx_ops mv88e6321_ops = { 3570 /* MV88E6XXX_FAMILY_6321 */ 3571 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3572 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3573 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3574 .phy_read = mv88e6xxx_g2_smi_phy_read, 3575 .phy_write = mv88e6xxx_g2_smi_phy_write, 3576 .port_set_link = mv88e6xxx_port_set_link, 3577 .port_set_duplex = mv88e6xxx_port_set_duplex, 3578 .port_set_speed = mv88e6185_port_set_speed, 3579 .port_tag_remap = mv88e6095_port_tag_remap, 3580 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3581 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3582 .port_set_ether_type = mv88e6351_port_set_ether_type, 3583 .port_jumbo_config = mv88e6165_port_jumbo_config, 3584 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3585 .port_pause_config = mv88e6097_port_pause_config, 3586 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3587 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3588 .stats_get_strings = mv88e6320_stats_get_strings, 3589 .stats_get_stats = mv88e6320_stats_get_stats, 3590 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3591 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3592 .reset = mv88e6352_g1_reset, 3593 }; 3594 3595 static const struct mv88e6xxx_ops mv88e6350_ops = { 3596 /* MV88E6XXX_FAMILY_6351 */ 3597 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3598 .phy_read = mv88e6xxx_g2_smi_phy_read, 3599 .phy_write = mv88e6xxx_g2_smi_phy_write, 3600 .port_set_link = mv88e6xxx_port_set_link, 3601 .port_set_duplex = mv88e6xxx_port_set_duplex, 3602 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3603 .port_set_speed = mv88e6185_port_set_speed, 3604 .port_tag_remap = mv88e6095_port_tag_remap, 3605 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3606 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3607 .port_set_ether_type = mv88e6351_port_set_ether_type, 3608 .port_jumbo_config = mv88e6165_port_jumbo_config, 3609 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3610 .port_pause_config = mv88e6097_port_pause_config, 3611 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3612 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3613 .stats_get_strings = mv88e6095_stats_get_strings, 3614 .stats_get_stats = mv88e6095_stats_get_stats, 3615 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3616 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3617 .watchdog_ops = &mv88e6097_watchdog_ops, 3618 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3619 .reset = mv88e6352_g1_reset, 3620 }; 3621 3622 static const struct mv88e6xxx_ops mv88e6351_ops = { 3623 /* MV88E6XXX_FAMILY_6351 */ 3624 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3625 .phy_read = mv88e6xxx_g2_smi_phy_read, 3626 .phy_write = mv88e6xxx_g2_smi_phy_write, 3627 .port_set_link = mv88e6xxx_port_set_link, 3628 .port_set_duplex = mv88e6xxx_port_set_duplex, 3629 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3630 .port_set_speed = mv88e6185_port_set_speed, 3631 .port_tag_remap = mv88e6095_port_tag_remap, 3632 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3633 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3634 .port_set_ether_type = mv88e6351_port_set_ether_type, 3635 .port_jumbo_config = mv88e6165_port_jumbo_config, 3636 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3637 .port_pause_config = mv88e6097_port_pause_config, 3638 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3639 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3640 .stats_get_strings = mv88e6095_stats_get_strings, 3641 .stats_get_stats = mv88e6095_stats_get_stats, 3642 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3643 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3644 .watchdog_ops = &mv88e6097_watchdog_ops, 3645 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3646 .reset = mv88e6352_g1_reset, 3647 }; 3648 3649 static const struct mv88e6xxx_ops mv88e6352_ops = { 3650 /* MV88E6XXX_FAMILY_6352 */ 3651 .get_eeprom = mv88e6xxx_g2_get_eeprom16, 3652 .set_eeprom = mv88e6xxx_g2_set_eeprom16, 3653 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3654 .phy_read = mv88e6xxx_g2_smi_phy_read, 3655 .phy_write = mv88e6xxx_g2_smi_phy_write, 3656 .port_set_link = mv88e6xxx_port_set_link, 3657 .port_set_duplex = mv88e6xxx_port_set_duplex, 3658 .port_set_rgmii_delay = mv88e6352_port_set_rgmii_delay, 3659 .port_set_speed = mv88e6352_port_set_speed, 3660 .port_tag_remap = mv88e6095_port_tag_remap, 3661 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3662 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3663 .port_set_ether_type = mv88e6351_port_set_ether_type, 3664 .port_jumbo_config = mv88e6165_port_jumbo_config, 3665 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3666 .port_pause_config = mv88e6097_port_pause_config, 3667 .stats_snapshot = mv88e6320_g1_stats_snapshot, 3668 .stats_get_sset_count = mv88e6095_stats_get_sset_count, 3669 .stats_get_strings = mv88e6095_stats_get_strings, 3670 .stats_get_stats = mv88e6095_stats_get_stats, 3671 .g1_set_cpu_port = mv88e6095_g1_set_cpu_port, 3672 .g1_set_egress_port = mv88e6095_g1_set_egress_port, 3673 .watchdog_ops = &mv88e6097_watchdog_ops, 3674 .mgmt_rsvd2cpu = mv88e6095_g2_mgmt_rsvd2cpu, 3675 .reset = mv88e6352_g1_reset, 3676 }; 3677 3678 static const struct mv88e6xxx_ops mv88e6141_ops = { 3679 /* MV88E6XXX_FAMILY_6341 */ 3680 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3681 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3682 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3683 .phy_read = mv88e6xxx_g2_smi_phy_read, 3684 .phy_write = mv88e6xxx_g2_smi_phy_write, 3685 .port_set_link = mv88e6xxx_port_set_link, 3686 .port_set_duplex = mv88e6xxx_port_set_duplex, 3687 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3688 .port_set_speed = mv88e6390_port_set_speed, 3689 .port_tag_remap = mv88e6095_port_tag_remap, 3690 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3691 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3692 .port_set_ether_type = mv88e6351_port_set_ether_type, 3693 .port_jumbo_config = mv88e6165_port_jumbo_config, 3694 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3695 .port_pause_config = mv88e6097_port_pause_config, 3696 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3697 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3698 .stats_get_strings = mv88e6320_stats_get_strings, 3699 .stats_get_stats = mv88e6390_stats_get_stats, 3700 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3701 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3702 .watchdog_ops = &mv88e6390_watchdog_ops, 3703 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3704 .reset = mv88e6352_g1_reset, 3705 }; 3706 3707 static const struct mv88e6xxx_ops mv88e6341_ops = { 3708 /* MV88E6XXX_FAMILY_6341 */ 3709 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3710 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3711 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3712 .phy_read = mv88e6xxx_g2_smi_phy_read, 3713 .phy_write = mv88e6xxx_g2_smi_phy_write, 3714 .port_set_link = mv88e6xxx_port_set_link, 3715 .port_set_duplex = mv88e6xxx_port_set_duplex, 3716 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3717 .port_set_speed = mv88e6390_port_set_speed, 3718 .port_tag_remap = mv88e6095_port_tag_remap, 3719 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3720 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3721 .port_set_ether_type = mv88e6351_port_set_ether_type, 3722 .port_jumbo_config = mv88e6165_port_jumbo_config, 3723 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3724 .port_pause_config = mv88e6097_port_pause_config, 3725 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3726 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3727 .stats_get_strings = mv88e6320_stats_get_strings, 3728 .stats_get_stats = mv88e6390_stats_get_stats, 3729 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3730 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3731 .watchdog_ops = &mv88e6390_watchdog_ops, 3732 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3733 .reset = mv88e6352_g1_reset, 3734 }; 3735 3736 static const struct mv88e6xxx_ops mv88e6390_ops = { 3737 /* MV88E6XXX_FAMILY_6390 */ 3738 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3739 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3740 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3741 .phy_read = mv88e6xxx_g2_smi_phy_read, 3742 .phy_write = mv88e6xxx_g2_smi_phy_write, 3743 .port_set_link = mv88e6xxx_port_set_link, 3744 .port_set_duplex = mv88e6xxx_port_set_duplex, 3745 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3746 .port_set_speed = mv88e6390_port_set_speed, 3747 .port_tag_remap = mv88e6390_port_tag_remap, 3748 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3749 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3750 .port_set_ether_type = mv88e6351_port_set_ether_type, 3751 .port_jumbo_config = mv88e6165_port_jumbo_config, 3752 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3753 .port_pause_config = mv88e6390_port_pause_config, 3754 .port_set_cmode = mv88e6390x_port_set_cmode, 3755 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3756 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3757 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3758 .stats_get_strings = mv88e6320_stats_get_strings, 3759 .stats_get_stats = mv88e6390_stats_get_stats, 3760 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3761 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3762 .watchdog_ops = &mv88e6390_watchdog_ops, 3763 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3764 .reset = mv88e6352_g1_reset, 3765 }; 3766 3767 static const struct mv88e6xxx_ops mv88e6390x_ops = { 3768 /* MV88E6XXX_FAMILY_6390 */ 3769 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3770 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3771 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3772 .phy_read = mv88e6xxx_g2_smi_phy_read, 3773 .phy_write = mv88e6xxx_g2_smi_phy_write, 3774 .port_set_link = mv88e6xxx_port_set_link, 3775 .port_set_duplex = mv88e6xxx_port_set_duplex, 3776 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3777 .port_set_speed = mv88e6390x_port_set_speed, 3778 .port_tag_remap = mv88e6390_port_tag_remap, 3779 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3780 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3781 .port_set_ether_type = mv88e6351_port_set_ether_type, 3782 .port_jumbo_config = mv88e6165_port_jumbo_config, 3783 .port_egress_rate_limiting = mv88e6097_port_egress_rate_limiting, 3784 .port_pause_config = mv88e6390_port_pause_config, 3785 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3786 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3787 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3788 .stats_get_strings = mv88e6320_stats_get_strings, 3789 .stats_get_stats = mv88e6390_stats_get_stats, 3790 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3791 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3792 .watchdog_ops = &mv88e6390_watchdog_ops, 3793 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3794 .reset = mv88e6352_g1_reset, 3795 }; 3796 3797 static const struct mv88e6xxx_ops mv88e6391_ops = { 3798 /* MV88E6XXX_FAMILY_6390 */ 3799 .get_eeprom = mv88e6xxx_g2_get_eeprom8, 3800 .set_eeprom = mv88e6xxx_g2_set_eeprom8, 3801 .set_switch_mac = mv88e6xxx_g2_set_switch_mac, 3802 .phy_read = mv88e6xxx_g2_smi_phy_read, 3803 .phy_write = mv88e6xxx_g2_smi_phy_write, 3804 .port_set_link = mv88e6xxx_port_set_link, 3805 .port_set_duplex = mv88e6xxx_port_set_duplex, 3806 .port_set_rgmii_delay = mv88e6390_port_set_rgmii_delay, 3807 .port_set_speed = mv88e6390_port_set_speed, 3808 .port_tag_remap = mv88e6390_port_tag_remap, 3809 .port_set_frame_mode = mv88e6351_port_set_frame_mode, 3810 .port_set_egress_unknowns = mv88e6351_port_set_egress_unknowns, 3811 .port_set_ether_type = mv88e6351_port_set_ether_type, 3812 .port_pause_config = mv88e6390_port_pause_config, 3813 .stats_snapshot = mv88e6390_g1_stats_snapshot, 3814 .stats_set_histogram = mv88e6390_g1_stats_set_histogram, 3815 .stats_get_sset_count = mv88e6320_stats_get_sset_count, 3816 .stats_get_strings = mv88e6320_stats_get_strings, 3817 .stats_get_stats = mv88e6390_stats_get_stats, 3818 .g1_set_cpu_port = mv88e6390_g1_set_cpu_port, 3819 .g1_set_egress_port = mv88e6390_g1_set_egress_port, 3820 .watchdog_ops = &mv88e6390_watchdog_ops, 3821 .mgmt_rsvd2cpu = mv88e6390_g1_mgmt_rsvd2cpu, 3822 .reset = mv88e6352_g1_reset, 3823 }; 3824 3825 static int mv88e6xxx_verify_madatory_ops(struct mv88e6xxx_chip *chip, 3826 const struct mv88e6xxx_ops *ops) 3827 { 3828 if (!ops->port_set_frame_mode) { 3829 dev_err(chip->dev, "Missing port_set_frame_mode"); 3830 return -EINVAL; 3831 } 3832 3833 if (!ops->port_set_egress_unknowns) { 3834 dev_err(chip->dev, "Missing port_set_egress_mode"); 3835 return -EINVAL; 3836 } 3837 3838 return 0; 3839 } 3840 3841 static const struct mv88e6xxx_info mv88e6xxx_table[] = { 3842 [MV88E6085] = { 3843 .prod_num = PORT_SWITCH_ID_PROD_NUM_6085, 3844 .family = MV88E6XXX_FAMILY_6097, 3845 .name = "Marvell 88E6085", 3846 .num_databases = 4096, 3847 .num_ports = 10, 3848 .port_base_addr = 0x10, 3849 .global1_addr = 0x1b, 3850 .age_time_coeff = 15000, 3851 .g1_irqs = 8, 3852 .tag_protocol = DSA_TAG_PROTO_DSA, 3853 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3854 .ops = &mv88e6085_ops, 3855 }, 3856 3857 [MV88E6095] = { 3858 .prod_num = PORT_SWITCH_ID_PROD_NUM_6095, 3859 .family = MV88E6XXX_FAMILY_6095, 3860 .name = "Marvell 88E6095/88E6095F", 3861 .num_databases = 256, 3862 .num_ports = 11, 3863 .port_base_addr = 0x10, 3864 .global1_addr = 0x1b, 3865 .age_time_coeff = 15000, 3866 .g1_irqs = 8, 3867 .tag_protocol = DSA_TAG_PROTO_DSA, 3868 .flags = MV88E6XXX_FLAGS_FAMILY_6095, 3869 .ops = &mv88e6095_ops, 3870 }, 3871 3872 [MV88E6097] = { 3873 .prod_num = PORT_SWITCH_ID_PROD_NUM_6097, 3874 .family = MV88E6XXX_FAMILY_6097, 3875 .name = "Marvell 88E6097/88E6097F", 3876 .num_databases = 4096, 3877 .num_ports = 11, 3878 .port_base_addr = 0x10, 3879 .global1_addr = 0x1b, 3880 .age_time_coeff = 15000, 3881 .g1_irqs = 8, 3882 .tag_protocol = DSA_TAG_PROTO_EDSA, 3883 .flags = MV88E6XXX_FLAGS_FAMILY_6097, 3884 .ops = &mv88e6097_ops, 3885 }, 3886 3887 [MV88E6123] = { 3888 .prod_num = PORT_SWITCH_ID_PROD_NUM_6123, 3889 .family = MV88E6XXX_FAMILY_6165, 3890 .name = "Marvell 88E6123", 3891 .num_databases = 4096, 3892 .num_ports = 3, 3893 .port_base_addr = 0x10, 3894 .global1_addr = 0x1b, 3895 .age_time_coeff = 15000, 3896 .g1_irqs = 9, 3897 .tag_protocol = DSA_TAG_PROTO_DSA, 3898 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3899 .ops = &mv88e6123_ops, 3900 }, 3901 3902 [MV88E6131] = { 3903 .prod_num = PORT_SWITCH_ID_PROD_NUM_6131, 3904 .family = MV88E6XXX_FAMILY_6185, 3905 .name = "Marvell 88E6131", 3906 .num_databases = 256, 3907 .num_ports = 8, 3908 .port_base_addr = 0x10, 3909 .global1_addr = 0x1b, 3910 .age_time_coeff = 15000, 3911 .g1_irqs = 9, 3912 .tag_protocol = DSA_TAG_PROTO_DSA, 3913 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 3914 .ops = &mv88e6131_ops, 3915 }, 3916 3917 [MV88E6161] = { 3918 .prod_num = PORT_SWITCH_ID_PROD_NUM_6161, 3919 .family = MV88E6XXX_FAMILY_6165, 3920 .name = "Marvell 88E6161", 3921 .num_databases = 4096, 3922 .num_ports = 6, 3923 .port_base_addr = 0x10, 3924 .global1_addr = 0x1b, 3925 .age_time_coeff = 15000, 3926 .g1_irqs = 9, 3927 .tag_protocol = DSA_TAG_PROTO_DSA, 3928 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3929 .ops = &mv88e6161_ops, 3930 }, 3931 3932 [MV88E6165] = { 3933 .prod_num = PORT_SWITCH_ID_PROD_NUM_6165, 3934 .family = MV88E6XXX_FAMILY_6165, 3935 .name = "Marvell 88E6165", 3936 .num_databases = 4096, 3937 .num_ports = 6, 3938 .port_base_addr = 0x10, 3939 .global1_addr = 0x1b, 3940 .age_time_coeff = 15000, 3941 .g1_irqs = 9, 3942 .tag_protocol = DSA_TAG_PROTO_DSA, 3943 .flags = MV88E6XXX_FLAGS_FAMILY_6165, 3944 .ops = &mv88e6165_ops, 3945 }, 3946 3947 [MV88E6171] = { 3948 .prod_num = PORT_SWITCH_ID_PROD_NUM_6171, 3949 .family = MV88E6XXX_FAMILY_6351, 3950 .name = "Marvell 88E6171", 3951 .num_databases = 4096, 3952 .num_ports = 7, 3953 .port_base_addr = 0x10, 3954 .global1_addr = 0x1b, 3955 .age_time_coeff = 15000, 3956 .g1_irqs = 9, 3957 .tag_protocol = DSA_TAG_PROTO_EDSA, 3958 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3959 .ops = &mv88e6171_ops, 3960 }, 3961 3962 [MV88E6172] = { 3963 .prod_num = PORT_SWITCH_ID_PROD_NUM_6172, 3964 .family = MV88E6XXX_FAMILY_6352, 3965 .name = "Marvell 88E6172", 3966 .num_databases = 4096, 3967 .num_ports = 7, 3968 .port_base_addr = 0x10, 3969 .global1_addr = 0x1b, 3970 .age_time_coeff = 15000, 3971 .g1_irqs = 9, 3972 .tag_protocol = DSA_TAG_PROTO_EDSA, 3973 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 3974 .ops = &mv88e6172_ops, 3975 }, 3976 3977 [MV88E6175] = { 3978 .prod_num = PORT_SWITCH_ID_PROD_NUM_6175, 3979 .family = MV88E6XXX_FAMILY_6351, 3980 .name = "Marvell 88E6175", 3981 .num_databases = 4096, 3982 .num_ports = 7, 3983 .port_base_addr = 0x10, 3984 .global1_addr = 0x1b, 3985 .age_time_coeff = 15000, 3986 .g1_irqs = 9, 3987 .tag_protocol = DSA_TAG_PROTO_EDSA, 3988 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 3989 .ops = &mv88e6175_ops, 3990 }, 3991 3992 [MV88E6176] = { 3993 .prod_num = PORT_SWITCH_ID_PROD_NUM_6176, 3994 .family = MV88E6XXX_FAMILY_6352, 3995 .name = "Marvell 88E6176", 3996 .num_databases = 4096, 3997 .num_ports = 7, 3998 .port_base_addr = 0x10, 3999 .global1_addr = 0x1b, 4000 .age_time_coeff = 15000, 4001 .g1_irqs = 9, 4002 .tag_protocol = DSA_TAG_PROTO_EDSA, 4003 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4004 .ops = &mv88e6176_ops, 4005 }, 4006 4007 [MV88E6185] = { 4008 .prod_num = PORT_SWITCH_ID_PROD_NUM_6185, 4009 .family = MV88E6XXX_FAMILY_6185, 4010 .name = "Marvell 88E6185", 4011 .num_databases = 256, 4012 .num_ports = 10, 4013 .port_base_addr = 0x10, 4014 .global1_addr = 0x1b, 4015 .age_time_coeff = 15000, 4016 .g1_irqs = 8, 4017 .tag_protocol = DSA_TAG_PROTO_EDSA, 4018 .flags = MV88E6XXX_FLAGS_FAMILY_6185, 4019 .ops = &mv88e6185_ops, 4020 }, 4021 4022 [MV88E6190] = { 4023 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190, 4024 .family = MV88E6XXX_FAMILY_6390, 4025 .name = "Marvell 88E6190", 4026 .num_databases = 4096, 4027 .num_ports = 11, /* 10 + Z80 */ 4028 .port_base_addr = 0x0, 4029 .global1_addr = 0x1b, 4030 .tag_protocol = DSA_TAG_PROTO_DSA, 4031 .age_time_coeff = 3750, 4032 .g1_irqs = 9, 4033 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4034 .ops = &mv88e6190_ops, 4035 }, 4036 4037 [MV88E6190X] = { 4038 .prod_num = PORT_SWITCH_ID_PROD_NUM_6190X, 4039 .family = MV88E6XXX_FAMILY_6390, 4040 .name = "Marvell 88E6190X", 4041 .num_databases = 4096, 4042 .num_ports = 11, /* 10 + Z80 */ 4043 .port_base_addr = 0x0, 4044 .global1_addr = 0x1b, 4045 .age_time_coeff = 3750, 4046 .g1_irqs = 9, 4047 .tag_protocol = DSA_TAG_PROTO_DSA, 4048 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4049 .ops = &mv88e6190x_ops, 4050 }, 4051 4052 [MV88E6191] = { 4053 .prod_num = PORT_SWITCH_ID_PROD_NUM_6191, 4054 .family = MV88E6XXX_FAMILY_6390, 4055 .name = "Marvell 88E6191", 4056 .num_databases = 4096, 4057 .num_ports = 11, /* 10 + Z80 */ 4058 .port_base_addr = 0x0, 4059 .global1_addr = 0x1b, 4060 .age_time_coeff = 3750, 4061 .g1_irqs = 9, 4062 .tag_protocol = DSA_TAG_PROTO_DSA, 4063 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4064 .ops = &mv88e6391_ops, 4065 }, 4066 4067 [MV88E6240] = { 4068 .prod_num = PORT_SWITCH_ID_PROD_NUM_6240, 4069 .family = MV88E6XXX_FAMILY_6352, 4070 .name = "Marvell 88E6240", 4071 .num_databases = 4096, 4072 .num_ports = 7, 4073 .port_base_addr = 0x10, 4074 .global1_addr = 0x1b, 4075 .age_time_coeff = 15000, 4076 .g1_irqs = 9, 4077 .tag_protocol = DSA_TAG_PROTO_EDSA, 4078 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4079 .ops = &mv88e6240_ops, 4080 }, 4081 4082 [MV88E6290] = { 4083 .prod_num = PORT_SWITCH_ID_PROD_NUM_6290, 4084 .family = MV88E6XXX_FAMILY_6390, 4085 .name = "Marvell 88E6290", 4086 .num_databases = 4096, 4087 .num_ports = 11, /* 10 + Z80 */ 4088 .port_base_addr = 0x0, 4089 .global1_addr = 0x1b, 4090 .age_time_coeff = 3750, 4091 .g1_irqs = 9, 4092 .tag_protocol = DSA_TAG_PROTO_DSA, 4093 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4094 .ops = &mv88e6290_ops, 4095 }, 4096 4097 [MV88E6320] = { 4098 .prod_num = PORT_SWITCH_ID_PROD_NUM_6320, 4099 .family = MV88E6XXX_FAMILY_6320, 4100 .name = "Marvell 88E6320", 4101 .num_databases = 4096, 4102 .num_ports = 7, 4103 .port_base_addr = 0x10, 4104 .global1_addr = 0x1b, 4105 .age_time_coeff = 15000, 4106 .g1_irqs = 8, 4107 .tag_protocol = DSA_TAG_PROTO_EDSA, 4108 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4109 .ops = &mv88e6320_ops, 4110 }, 4111 4112 [MV88E6321] = { 4113 .prod_num = PORT_SWITCH_ID_PROD_NUM_6321, 4114 .family = MV88E6XXX_FAMILY_6320, 4115 .name = "Marvell 88E6321", 4116 .num_databases = 4096, 4117 .num_ports = 7, 4118 .port_base_addr = 0x10, 4119 .global1_addr = 0x1b, 4120 .age_time_coeff = 15000, 4121 .g1_irqs = 8, 4122 .tag_protocol = DSA_TAG_PROTO_EDSA, 4123 .flags = MV88E6XXX_FLAGS_FAMILY_6320, 4124 .ops = &mv88e6321_ops, 4125 }, 4126 4127 [MV88E6141] = { 4128 .prod_num = PORT_SWITCH_ID_PROD_NUM_6141, 4129 .family = MV88E6XXX_FAMILY_6341, 4130 .name = "Marvell 88E6341", 4131 .num_databases = 4096, 4132 .num_ports = 6, 4133 .port_base_addr = 0x10, 4134 .global1_addr = 0x1b, 4135 .age_time_coeff = 3750, 4136 .tag_protocol = DSA_TAG_PROTO_EDSA, 4137 .flags = MV88E6XXX_FLAGS_FAMILY_6341, 4138 .ops = &mv88e6141_ops, 4139 }, 4140 4141 [MV88E6341] = { 4142 .prod_num = PORT_SWITCH_ID_PROD_NUM_6341, 4143 .family = MV88E6XXX_FAMILY_6341, 4144 .name = "Marvell 88E6341", 4145 .num_databases = 4096, 4146 .num_ports = 6, 4147 .port_base_addr = 0x10, 4148 .global1_addr = 0x1b, 4149 .age_time_coeff = 3750, 4150 .tag_protocol = DSA_TAG_PROTO_EDSA, 4151 .flags = MV88E6XXX_FLAGS_FAMILY_6341, 4152 .ops = &mv88e6341_ops, 4153 }, 4154 4155 [MV88E6350] = { 4156 .prod_num = PORT_SWITCH_ID_PROD_NUM_6350, 4157 .family = MV88E6XXX_FAMILY_6351, 4158 .name = "Marvell 88E6350", 4159 .num_databases = 4096, 4160 .num_ports = 7, 4161 .port_base_addr = 0x10, 4162 .global1_addr = 0x1b, 4163 .age_time_coeff = 15000, 4164 .g1_irqs = 9, 4165 .tag_protocol = DSA_TAG_PROTO_EDSA, 4166 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4167 .ops = &mv88e6350_ops, 4168 }, 4169 4170 [MV88E6351] = { 4171 .prod_num = PORT_SWITCH_ID_PROD_NUM_6351, 4172 .family = MV88E6XXX_FAMILY_6351, 4173 .name = "Marvell 88E6351", 4174 .num_databases = 4096, 4175 .num_ports = 7, 4176 .port_base_addr = 0x10, 4177 .global1_addr = 0x1b, 4178 .age_time_coeff = 15000, 4179 .g1_irqs = 9, 4180 .tag_protocol = DSA_TAG_PROTO_EDSA, 4181 .flags = MV88E6XXX_FLAGS_FAMILY_6351, 4182 .ops = &mv88e6351_ops, 4183 }, 4184 4185 [MV88E6352] = { 4186 .prod_num = PORT_SWITCH_ID_PROD_NUM_6352, 4187 .family = MV88E6XXX_FAMILY_6352, 4188 .name = "Marvell 88E6352", 4189 .num_databases = 4096, 4190 .num_ports = 7, 4191 .port_base_addr = 0x10, 4192 .global1_addr = 0x1b, 4193 .age_time_coeff = 15000, 4194 .g1_irqs = 9, 4195 .tag_protocol = DSA_TAG_PROTO_EDSA, 4196 .flags = MV88E6XXX_FLAGS_FAMILY_6352, 4197 .ops = &mv88e6352_ops, 4198 }, 4199 [MV88E6390] = { 4200 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390, 4201 .family = MV88E6XXX_FAMILY_6390, 4202 .name = "Marvell 88E6390", 4203 .num_databases = 4096, 4204 .num_ports = 11, /* 10 + Z80 */ 4205 .port_base_addr = 0x0, 4206 .global1_addr = 0x1b, 4207 .age_time_coeff = 3750, 4208 .g1_irqs = 9, 4209 .tag_protocol = DSA_TAG_PROTO_DSA, 4210 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4211 .ops = &mv88e6390_ops, 4212 }, 4213 [MV88E6390X] = { 4214 .prod_num = PORT_SWITCH_ID_PROD_NUM_6390X, 4215 .family = MV88E6XXX_FAMILY_6390, 4216 .name = "Marvell 88E6390X", 4217 .num_databases = 4096, 4218 .num_ports = 11, /* 10 + Z80 */ 4219 .port_base_addr = 0x0, 4220 .global1_addr = 0x1b, 4221 .age_time_coeff = 3750, 4222 .g1_irqs = 9, 4223 .tag_protocol = DSA_TAG_PROTO_DSA, 4224 .flags = MV88E6XXX_FLAGS_FAMILY_6390, 4225 .ops = &mv88e6390x_ops, 4226 }, 4227 }; 4228 4229 static const struct mv88e6xxx_info *mv88e6xxx_lookup_info(unsigned int prod_num) 4230 { 4231 int i; 4232 4233 for (i = 0; i < ARRAY_SIZE(mv88e6xxx_table); ++i) 4234 if (mv88e6xxx_table[i].prod_num == prod_num) 4235 return &mv88e6xxx_table[i]; 4236 4237 return NULL; 4238 } 4239 4240 static int mv88e6xxx_detect(struct mv88e6xxx_chip *chip) 4241 { 4242 const struct mv88e6xxx_info *info; 4243 unsigned int prod_num, rev; 4244 u16 id; 4245 int err; 4246 4247 mutex_lock(&chip->reg_lock); 4248 err = mv88e6xxx_port_read(chip, 0, PORT_SWITCH_ID, &id); 4249 mutex_unlock(&chip->reg_lock); 4250 if (err) 4251 return err; 4252 4253 prod_num = (id & 0xfff0) >> 4; 4254 rev = id & 0x000f; 4255 4256 info = mv88e6xxx_lookup_info(prod_num); 4257 if (!info) 4258 return -ENODEV; 4259 4260 /* Update the compatible info with the probed one */ 4261 chip->info = info; 4262 4263 err = mv88e6xxx_g2_require(chip); 4264 if (err) 4265 return err; 4266 4267 dev_info(chip->dev, "switch 0x%x detected: %s, revision %u\n", 4268 chip->info->prod_num, chip->info->name, rev); 4269 4270 return 0; 4271 } 4272 4273 static struct mv88e6xxx_chip *mv88e6xxx_alloc_chip(struct device *dev) 4274 { 4275 struct mv88e6xxx_chip *chip; 4276 4277 chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL); 4278 if (!chip) 4279 return NULL; 4280 4281 chip->dev = dev; 4282 4283 mutex_init(&chip->reg_lock); 4284 INIT_LIST_HEAD(&chip->mdios); 4285 4286 return chip; 4287 } 4288 4289 static void mv88e6xxx_phy_init(struct mv88e6xxx_chip *chip) 4290 { 4291 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) 4292 mv88e6xxx_ppu_state_init(chip); 4293 } 4294 4295 static void mv88e6xxx_phy_destroy(struct mv88e6xxx_chip *chip) 4296 { 4297 if (chip->info->ops->ppu_enable && chip->info->ops->ppu_disable) 4298 mv88e6xxx_ppu_state_destroy(chip); 4299 } 4300 4301 static int mv88e6xxx_smi_init(struct mv88e6xxx_chip *chip, 4302 struct mii_bus *bus, int sw_addr) 4303 { 4304 if (sw_addr == 0) 4305 chip->smi_ops = &mv88e6xxx_smi_single_chip_ops; 4306 else if (mv88e6xxx_has(chip, MV88E6XXX_FLAGS_MULTI_CHIP)) 4307 chip->smi_ops = &mv88e6xxx_smi_multi_chip_ops; 4308 else 4309 return -EINVAL; 4310 4311 chip->bus = bus; 4312 chip->sw_addr = sw_addr; 4313 4314 return 0; 4315 } 4316 4317 static enum dsa_tag_protocol mv88e6xxx_get_tag_protocol(struct dsa_switch *ds) 4318 { 4319 struct mv88e6xxx_chip *chip = ds->priv; 4320 4321 return chip->info->tag_protocol; 4322 } 4323 4324 static const char *mv88e6xxx_drv_probe(struct device *dsa_dev, 4325 struct device *host_dev, int sw_addr, 4326 void **priv) 4327 { 4328 struct mv88e6xxx_chip *chip; 4329 struct mii_bus *bus; 4330 int err; 4331 4332 bus = dsa_host_dev_to_mii_bus(host_dev); 4333 if (!bus) 4334 return NULL; 4335 4336 chip = mv88e6xxx_alloc_chip(dsa_dev); 4337 if (!chip) 4338 return NULL; 4339 4340 /* Legacy SMI probing will only support chips similar to 88E6085 */ 4341 chip->info = &mv88e6xxx_table[MV88E6085]; 4342 4343 err = mv88e6xxx_smi_init(chip, bus, sw_addr); 4344 if (err) 4345 goto free; 4346 4347 err = mv88e6xxx_detect(chip); 4348 if (err) 4349 goto free; 4350 4351 mutex_lock(&chip->reg_lock); 4352 err = mv88e6xxx_switch_reset(chip); 4353 mutex_unlock(&chip->reg_lock); 4354 if (err) 4355 goto free; 4356 4357 mv88e6xxx_phy_init(chip); 4358 4359 err = mv88e6xxx_mdios_register(chip, NULL); 4360 if (err) 4361 goto free; 4362 4363 *priv = chip; 4364 4365 return chip->info->name; 4366 free: 4367 devm_kfree(dsa_dev, chip); 4368 4369 return NULL; 4370 } 4371 4372 static int mv88e6xxx_port_mdb_prepare(struct dsa_switch *ds, int port, 4373 const struct switchdev_obj_port_mdb *mdb, 4374 struct switchdev_trans *trans) 4375 { 4376 /* We don't need any dynamic resource from the kernel (yet), 4377 * so skip the prepare phase. 4378 */ 4379 4380 return 0; 4381 } 4382 4383 static void mv88e6xxx_port_mdb_add(struct dsa_switch *ds, int port, 4384 const struct switchdev_obj_port_mdb *mdb, 4385 struct switchdev_trans *trans) 4386 { 4387 struct mv88e6xxx_chip *chip = ds->priv; 4388 4389 mutex_lock(&chip->reg_lock); 4390 if (mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4391 GLOBAL_ATU_DATA_STATE_MC_STATIC)) 4392 netdev_err(ds->ports[port].netdev, "failed to load multicast MAC address\n"); 4393 mutex_unlock(&chip->reg_lock); 4394 } 4395 4396 static int mv88e6xxx_port_mdb_del(struct dsa_switch *ds, int port, 4397 const struct switchdev_obj_port_mdb *mdb) 4398 { 4399 struct mv88e6xxx_chip *chip = ds->priv; 4400 int err; 4401 4402 mutex_lock(&chip->reg_lock); 4403 err = mv88e6xxx_port_db_load_purge(chip, port, mdb->addr, mdb->vid, 4404 GLOBAL_ATU_DATA_STATE_UNUSED); 4405 mutex_unlock(&chip->reg_lock); 4406 4407 return err; 4408 } 4409 4410 static int mv88e6xxx_port_mdb_dump(struct dsa_switch *ds, int port, 4411 struct switchdev_obj_port_mdb *mdb, 4412 int (*cb)(struct switchdev_obj *obj)) 4413 { 4414 struct mv88e6xxx_chip *chip = ds->priv; 4415 int err; 4416 4417 mutex_lock(&chip->reg_lock); 4418 err = mv88e6xxx_port_db_dump(chip, port, &mdb->obj, cb); 4419 mutex_unlock(&chip->reg_lock); 4420 4421 return err; 4422 } 4423 4424 static const struct dsa_switch_ops mv88e6xxx_switch_ops = { 4425 .probe = mv88e6xxx_drv_probe, 4426 .get_tag_protocol = mv88e6xxx_get_tag_protocol, 4427 .setup = mv88e6xxx_setup, 4428 .set_addr = mv88e6xxx_set_addr, 4429 .adjust_link = mv88e6xxx_adjust_link, 4430 .get_strings = mv88e6xxx_get_strings, 4431 .get_ethtool_stats = mv88e6xxx_get_ethtool_stats, 4432 .get_sset_count = mv88e6xxx_get_sset_count, 4433 .set_eee = mv88e6xxx_set_eee, 4434 .get_eee = mv88e6xxx_get_eee, 4435 .get_eeprom_len = mv88e6xxx_get_eeprom_len, 4436 .get_eeprom = mv88e6xxx_get_eeprom, 4437 .set_eeprom = mv88e6xxx_set_eeprom, 4438 .get_regs_len = mv88e6xxx_get_regs_len, 4439 .get_regs = mv88e6xxx_get_regs, 4440 .set_ageing_time = mv88e6xxx_set_ageing_time, 4441 .port_bridge_join = mv88e6xxx_port_bridge_join, 4442 .port_bridge_leave = mv88e6xxx_port_bridge_leave, 4443 .port_stp_state_set = mv88e6xxx_port_stp_state_set, 4444 .port_fast_age = mv88e6xxx_port_fast_age, 4445 .port_vlan_filtering = mv88e6xxx_port_vlan_filtering, 4446 .port_vlan_prepare = mv88e6xxx_port_vlan_prepare, 4447 .port_vlan_add = mv88e6xxx_port_vlan_add, 4448 .port_vlan_del = mv88e6xxx_port_vlan_del, 4449 .port_vlan_dump = mv88e6xxx_port_vlan_dump, 4450 .port_fdb_prepare = mv88e6xxx_port_fdb_prepare, 4451 .port_fdb_add = mv88e6xxx_port_fdb_add, 4452 .port_fdb_del = mv88e6xxx_port_fdb_del, 4453 .port_fdb_dump = mv88e6xxx_port_fdb_dump, 4454 .port_mdb_prepare = mv88e6xxx_port_mdb_prepare, 4455 .port_mdb_add = mv88e6xxx_port_mdb_add, 4456 .port_mdb_del = mv88e6xxx_port_mdb_del, 4457 .port_mdb_dump = mv88e6xxx_port_mdb_dump, 4458 }; 4459 4460 static struct dsa_switch_driver mv88e6xxx_switch_drv = { 4461 .ops = &mv88e6xxx_switch_ops, 4462 }; 4463 4464 static int mv88e6xxx_register_switch(struct mv88e6xxx_chip *chip) 4465 { 4466 struct device *dev = chip->dev; 4467 struct dsa_switch *ds; 4468 4469 ds = dsa_switch_alloc(dev, DSA_MAX_PORTS); 4470 if (!ds) 4471 return -ENOMEM; 4472 4473 ds->priv = chip; 4474 ds->ops = &mv88e6xxx_switch_ops; 4475 4476 dev_set_drvdata(dev, ds); 4477 4478 return dsa_register_switch(ds, dev); 4479 } 4480 4481 static void mv88e6xxx_unregister_switch(struct mv88e6xxx_chip *chip) 4482 { 4483 dsa_unregister_switch(chip->ds); 4484 } 4485 4486 static int mv88e6xxx_probe(struct mdio_device *mdiodev) 4487 { 4488 struct device *dev = &mdiodev->dev; 4489 struct device_node *np = dev->of_node; 4490 const struct mv88e6xxx_info *compat_info; 4491 struct mv88e6xxx_chip *chip; 4492 u32 eeprom_len; 4493 int err; 4494 4495 compat_info = of_device_get_match_data(dev); 4496 if (!compat_info) 4497 return -EINVAL; 4498 4499 chip = mv88e6xxx_alloc_chip(dev); 4500 if (!chip) 4501 return -ENOMEM; 4502 4503 chip->info = compat_info; 4504 4505 err = mv88e6xxx_verify_madatory_ops(chip, chip->info->ops); 4506 if (err) 4507 return err; 4508 4509 err = mv88e6xxx_smi_init(chip, mdiodev->bus, mdiodev->addr); 4510 if (err) 4511 return err; 4512 4513 chip->reset = devm_gpiod_get_optional(dev, "reset", GPIOD_OUT_LOW); 4514 if (IS_ERR(chip->reset)) 4515 return PTR_ERR(chip->reset); 4516 4517 err = mv88e6xxx_detect(chip); 4518 if (err) 4519 return err; 4520 4521 mv88e6xxx_phy_init(chip); 4522 4523 if (chip->info->ops->get_eeprom && 4524 !of_property_read_u32(np, "eeprom-length", &eeprom_len)) 4525 chip->eeprom_len = eeprom_len; 4526 4527 mutex_lock(&chip->reg_lock); 4528 err = mv88e6xxx_switch_reset(chip); 4529 mutex_unlock(&chip->reg_lock); 4530 if (err) 4531 goto out; 4532 4533 chip->irq = of_irq_get(np, 0); 4534 if (chip->irq == -EPROBE_DEFER) { 4535 err = chip->irq; 4536 goto out; 4537 } 4538 4539 if (chip->irq > 0) { 4540 /* Has to be performed before the MDIO bus is created, 4541 * because the PHYs will link there interrupts to these 4542 * interrupt controllers 4543 */ 4544 mutex_lock(&chip->reg_lock); 4545 err = mv88e6xxx_g1_irq_setup(chip); 4546 mutex_unlock(&chip->reg_lock); 4547 4548 if (err) 4549 goto out; 4550 4551 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) { 4552 err = mv88e6xxx_g2_irq_setup(chip); 4553 if (err) 4554 goto out_g1_irq; 4555 } 4556 } 4557 4558 err = mv88e6xxx_mdios_register(chip, np); 4559 if (err) 4560 goto out_g2_irq; 4561 4562 err = mv88e6xxx_register_switch(chip); 4563 if (err) 4564 goto out_mdio; 4565 4566 return 0; 4567 4568 out_mdio: 4569 mv88e6xxx_mdios_unregister(chip); 4570 out_g2_irq: 4571 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT) && chip->irq > 0) 4572 mv88e6xxx_g2_irq_free(chip); 4573 out_g1_irq: 4574 if (chip->irq > 0) { 4575 mutex_lock(&chip->reg_lock); 4576 mv88e6xxx_g1_irq_free(chip); 4577 mutex_unlock(&chip->reg_lock); 4578 } 4579 out: 4580 return err; 4581 } 4582 4583 static void mv88e6xxx_remove(struct mdio_device *mdiodev) 4584 { 4585 struct dsa_switch *ds = dev_get_drvdata(&mdiodev->dev); 4586 struct mv88e6xxx_chip *chip = ds->priv; 4587 4588 mv88e6xxx_phy_destroy(chip); 4589 mv88e6xxx_unregister_switch(chip); 4590 mv88e6xxx_mdios_unregister(chip); 4591 4592 if (chip->irq > 0) { 4593 if (mv88e6xxx_has(chip, MV88E6XXX_FLAG_G2_INT)) 4594 mv88e6xxx_g2_irq_free(chip); 4595 mv88e6xxx_g1_irq_free(chip); 4596 } 4597 } 4598 4599 static const struct of_device_id mv88e6xxx_of_match[] = { 4600 { 4601 .compatible = "marvell,mv88e6085", 4602 .data = &mv88e6xxx_table[MV88E6085], 4603 }, 4604 { 4605 .compatible = "marvell,mv88e6190", 4606 .data = &mv88e6xxx_table[MV88E6190], 4607 }, 4608 { /* sentinel */ }, 4609 }; 4610 4611 MODULE_DEVICE_TABLE(of, mv88e6xxx_of_match); 4612 4613 static struct mdio_driver mv88e6xxx_driver = { 4614 .probe = mv88e6xxx_probe, 4615 .remove = mv88e6xxx_remove, 4616 .mdiodrv.driver = { 4617 .name = "mv88e6085", 4618 .of_match_table = mv88e6xxx_of_match, 4619 }, 4620 }; 4621 4622 static int __init mv88e6xxx_init(void) 4623 { 4624 register_switch_driver(&mv88e6xxx_switch_drv); 4625 return mdio_driver_register(&mv88e6xxx_driver); 4626 } 4627 module_init(mv88e6xxx_init); 4628 4629 static void __exit mv88e6xxx_cleanup(void) 4630 { 4631 mdio_driver_unregister(&mv88e6xxx_driver); 4632 unregister_switch_driver(&mv88e6xxx_switch_drv); 4633 } 4634 module_exit(mv88e6xxx_cleanup); 4635 4636 MODULE_AUTHOR("Lennert Buytenhek <buytenh@wantstofly.org>"); 4637 MODULE_DESCRIPTION("Driver for Marvell 88E6XXX ethernet switch chips"); 4638 MODULE_LICENSE("GPL"); 4639