xref: /openbmc/linux/drivers/net/dsa/mt7530.h (revision f4356947)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com>
4  */
5 
6 #ifndef __MT7530_H
7 #define __MT7530_H
8 
9 #define MT7530_NUM_PORTS		7
10 #define MT7530_NUM_PHYS			5
11 #define MT7530_NUM_FDB_RECORDS		2048
12 #define MT7530_ALL_MEMBERS		0xff
13 
14 #define MTK_HDR_LEN	4
15 #define MT7530_MAX_MTU	(15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN)
16 
17 enum mt753x_id {
18 	ID_MT7530 = 0,
19 	ID_MT7621 = 1,
20 	ID_MT7531 = 2,
21 	ID_MT7988 = 3,
22 };
23 
24 #define	NUM_TRGMII_CTRL			5
25 
26 #define TRGMII_BASE(x)			(0x10000 + (x))
27 
28 /* Registers to ethsys access */
29 #define ETHSYS_CLKCFG0			0x2c
30 #define  ETHSYS_TRGMII_CLK_SEL362_5	BIT(11)
31 
32 #define SYSC_REG_RSTCTRL		0x34
33 #define  RESET_MCM			BIT(2)
34 
35 /* Registers to mac forward control for unknown frames */
36 #define MT7530_MFC			0x10
37 #define  BC_FFP(x)			(((x) & 0xff) << 24)
38 #define  BC_FFP_MASK			BC_FFP(~0)
39 #define  UNM_FFP(x)			(((x) & 0xff) << 16)
40 #define  UNM_FFP_MASK			UNM_FFP(~0)
41 #define  UNU_FFP(x)			(((x) & 0xff) << 8)
42 #define  UNU_FFP_MASK			UNU_FFP(~0)
43 #define  CPU_EN				BIT(7)
44 #define  CPU_PORT(x)			((x) << 4)
45 #define  CPU_MASK			(0xf << 4)
46 #define  MIRROR_EN			BIT(3)
47 #define  MIRROR_PORT(x)			((x) & 0x7)
48 #define  MIRROR_MASK			0x7
49 
50 /* Registers for CPU forward control */
51 #define MT7531_CFC			0x4
52 #define  MT7531_MIRROR_EN		BIT(19)
53 #define  MT7531_MIRROR_MASK		(MIRROR_MASK << 16)
54 #define  MT7531_MIRROR_PORT_GET(x)	(((x) >> 16) & MIRROR_MASK)
55 #define  MT7531_MIRROR_PORT_SET(x)	(((x) & MIRROR_MASK) << 16)
56 #define  MT7531_CPU_PMAP_MASK		GENMASK(7, 0)
57 
58 #define MT753X_MIRROR_REG(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
59 					 MT7531_CFC : MT7530_MFC)
60 #define MT753X_MIRROR_EN(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
61 					 MT7531_MIRROR_EN : MIRROR_EN)
62 #define MT753X_MIRROR_MASK(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
63 					 MT7531_MIRROR_MASK : MIRROR_MASK)
64 
65 /* Registers for BPDU and PAE frame control*/
66 #define MT753X_BPC			0x24
67 #define  MT753X_BPDU_PORT_FW_MASK	GENMASK(2, 0)
68 
69 enum mt753x_bpdu_port_fw {
70 	MT753X_BPDU_FOLLOW_MFC,
71 	MT753X_BPDU_CPU_EXCLUDE = 4,
72 	MT753X_BPDU_CPU_INCLUDE = 5,
73 	MT753X_BPDU_CPU_ONLY = 6,
74 	MT753X_BPDU_DROP = 7,
75 };
76 
77 /* Registers for address table access */
78 #define MT7530_ATA1			0x74
79 #define  STATIC_EMP			0
80 #define  STATIC_ENT			3
81 #define MT7530_ATA2			0x78
82 #define  ATA2_IVL			BIT(15)
83 #define  ATA2_FID(x)			(((x) & 0x7) << 12)
84 
85 /* Register for address table write data */
86 #define MT7530_ATWD			0x7c
87 
88 /* Register for address table control */
89 #define MT7530_ATC			0x80
90 #define  ATC_HASH			(((x) & 0xfff) << 16)
91 #define  ATC_BUSY			BIT(15)
92 #define  ATC_SRCH_END			BIT(14)
93 #define  ATC_SRCH_HIT			BIT(13)
94 #define  ATC_INVALID			BIT(12)
95 #define  ATC_MAT(x)			(((x) & 0xf) << 8)
96 #define  ATC_MAT_MACTAB			ATC_MAT(0)
97 
98 enum mt7530_fdb_cmd {
99 	MT7530_FDB_READ	= 0,
100 	MT7530_FDB_WRITE = 1,
101 	MT7530_FDB_FLUSH = 2,
102 	MT7530_FDB_START = 4,
103 	MT7530_FDB_NEXT = 5,
104 };
105 
106 /* Registers for table search read address */
107 #define MT7530_TSRA1			0x84
108 #define  MAC_BYTE_0			24
109 #define  MAC_BYTE_1			16
110 #define  MAC_BYTE_2			8
111 #define  MAC_BYTE_3			0
112 #define  MAC_BYTE_MASK			0xff
113 
114 #define MT7530_TSRA2			0x88
115 #define  MAC_BYTE_4			24
116 #define  MAC_BYTE_5			16
117 #define  CVID				0
118 #define  CVID_MASK			0xfff
119 
120 #define MT7530_ATRD			0x8C
121 #define	 AGE_TIMER			24
122 #define  AGE_TIMER_MASK			0xff
123 #define  PORT_MAP			4
124 #define  PORT_MAP_MASK			0xff
125 #define  ENT_STATUS			2
126 #define  ENT_STATUS_MASK		0x3
127 
128 /* Register for vlan table control */
129 #define MT7530_VTCR			0x90
130 #define  VTCR_BUSY			BIT(31)
131 #define  VTCR_INVALID			BIT(16)
132 #define  VTCR_FUNC(x)			(((x) & 0xf) << 12)
133 #define  VTCR_VID			((x) & 0xfff)
134 
135 enum mt7530_vlan_cmd {
136 	/* Read/Write the specified VID entry from VAWD register based
137 	 * on VID.
138 	 */
139 	MT7530_VTCR_RD_VID = 0,
140 	MT7530_VTCR_WR_VID = 1,
141 };
142 
143 /* Register for setup vlan and acl write data */
144 #define MT7530_VAWD1			0x94
145 #define  PORT_STAG			BIT(31)
146 /* Independent VLAN Learning */
147 #define  IVL_MAC			BIT(30)
148 /* Egress Tag Consistent */
149 #define  EG_CON				BIT(29)
150 /* Per VLAN Egress Tag Control */
151 #define  VTAG_EN			BIT(28)
152 /* VLAN Member Control */
153 #define  PORT_MEM(x)			(((x) & 0xff) << 16)
154 /* Filter ID */
155 #define  FID(x)				(((x) & 0x7) << 1)
156 /* VLAN Entry Valid */
157 #define  VLAN_VALID			BIT(0)
158 #define  PORT_MEM_SHFT			16
159 #define  PORT_MEM_MASK			0xff
160 
161 enum mt7530_fid {
162 	FID_STANDALONE = 0,
163 	FID_BRIDGED = 1,
164 };
165 
166 #define MT7530_VAWD2			0x98
167 /* Egress Tag Control */
168 #define  ETAG_CTRL_P(p, x)		(((x) & 0x3) << ((p) << 1))
169 #define  ETAG_CTRL_P_MASK(p)		ETAG_CTRL_P(p, 3)
170 
171 enum mt7530_vlan_egress_attr {
172 	MT7530_VLAN_EGRESS_UNTAG = 0,
173 	MT7530_VLAN_EGRESS_TAG = 2,
174 	MT7530_VLAN_EGRESS_STACK = 3,
175 };
176 
177 /* Register for address age control */
178 #define MT7530_AAC			0xa0
179 /* Disable ageing */
180 #define  AGE_DIS			BIT(20)
181 /* Age count */
182 #define  AGE_CNT_MASK			GENMASK(19, 12)
183 #define  AGE_CNT_MAX			0xff
184 #define  AGE_CNT(x)			(AGE_CNT_MASK & ((x) << 12))
185 /* Age unit */
186 #define  AGE_UNIT_MASK			GENMASK(11, 0)
187 #define  AGE_UNIT_MAX			0xfff
188 #define  AGE_UNIT(x)			(AGE_UNIT_MASK & (x))
189 
190 /* Register for port STP state control */
191 #define MT7530_SSP_P(x)			(0x2000 + ((x) * 0x100))
192 #define  FID_PST(fid, state)		(((state) & 0x3) << ((fid) * 2))
193 #define  FID_PST_MASK(fid)		FID_PST(fid, 0x3)
194 
195 enum mt7530_stp_state {
196 	MT7530_STP_DISABLED = 0,
197 	MT7530_STP_BLOCKING = 1,
198 	MT7530_STP_LISTENING = 1,
199 	MT7530_STP_LEARNING = 2,
200 	MT7530_STP_FORWARDING  = 3
201 };
202 
203 /* Register for port control */
204 #define MT7530_PCR_P(x)			(0x2004 + ((x) * 0x100))
205 #define  PORT_TX_MIR			BIT(9)
206 #define  PORT_RX_MIR			BIT(8)
207 #define  PORT_VLAN(x)			((x) & 0x3)
208 
209 enum mt7530_port_mode {
210 	/* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */
211 	MT7530_PORT_MATRIX_MODE = PORT_VLAN(0),
212 
213 	/* Fallback Mode: Forward received frames with ingress ports that do
214 	 * not belong to the VLAN member. Frames whose VID is not listed on
215 	 * the VLAN table are forwarded by the PCR_MATRIX members.
216 	 */
217 	MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1),
218 
219 	/* Security Mode: Discard any frame due to ingress membership
220 	 * violation or VID missed on the VLAN table.
221 	 */
222 	MT7530_PORT_SECURITY_MODE = PORT_VLAN(3),
223 };
224 
225 #define  PCR_MATRIX(x)			(((x) & 0xff) << 16)
226 #define  PORT_PRI(x)			(((x) & 0x7) << 24)
227 #define  EG_TAG(x)			(((x) & 0x3) << 28)
228 #define  PCR_MATRIX_MASK		PCR_MATRIX(0xff)
229 #define  PCR_MATRIX_CLR			PCR_MATRIX(0)
230 #define  PCR_PORT_VLAN_MASK		PORT_VLAN(3)
231 
232 /* Register for port security control */
233 #define MT7530_PSC_P(x)			(0x200c + ((x) * 0x100))
234 #define  SA_DIS				BIT(4)
235 
236 /* Register for port vlan control */
237 #define MT7530_PVC_P(x)			(0x2010 + ((x) * 0x100))
238 #define  PORT_SPEC_TAG			BIT(5)
239 #define  PVC_EG_TAG(x)			(((x) & 0x7) << 8)
240 #define  PVC_EG_TAG_MASK		PVC_EG_TAG(7)
241 #define  VLAN_ATTR(x)			(((x) & 0x3) << 6)
242 #define  VLAN_ATTR_MASK			VLAN_ATTR(3)
243 #define  ACC_FRM_MASK			GENMASK(1, 0)
244 
245 enum mt7530_vlan_port_eg_tag {
246 	MT7530_VLAN_EG_DISABLED = 0,
247 	MT7530_VLAN_EG_CONSISTENT = 1,
248 };
249 
250 enum mt7530_vlan_port_attr {
251 	MT7530_VLAN_USER = 0,
252 	MT7530_VLAN_TRANSPARENT = 3,
253 };
254 
255 enum mt7530_vlan_port_acc_frm {
256 	MT7530_VLAN_ACC_ALL = 0,
257 	MT7530_VLAN_ACC_TAGGED = 1,
258 	MT7530_VLAN_ACC_UNTAGGED = 2,
259 };
260 
261 #define  STAG_VPID			(((x) & 0xffff) << 16)
262 
263 /* Register for port port-and-protocol based vlan 1 control */
264 #define MT7530_PPBV1_P(x)		(0x2014 + ((x) * 0x100))
265 #define  G0_PORT_VID(x)			(((x) & 0xfff) << 0)
266 #define  G0_PORT_VID_MASK		G0_PORT_VID(0xfff)
267 #define  G0_PORT_VID_DEF		G0_PORT_VID(0)
268 
269 /* Register for port MAC control register */
270 #define MT7530_PMCR_P(x)		(0x3000 + ((x) * 0x100))
271 #define  PMCR_IFG_XMIT(x)		(((x) & 0x3) << 18)
272 #define  PMCR_EXT_PHY			BIT(17)
273 #define  PMCR_MAC_MODE			BIT(16)
274 #define  PMCR_FORCE_MODE		BIT(15)
275 #define  PMCR_TX_EN			BIT(14)
276 #define  PMCR_RX_EN			BIT(13)
277 #define  PMCR_BACKOFF_EN		BIT(9)
278 #define  PMCR_BACKPR_EN			BIT(8)
279 #define  PMCR_FORCE_EEE1G		BIT(7)
280 #define  PMCR_FORCE_EEE100		BIT(6)
281 #define  PMCR_TX_FC_EN			BIT(5)
282 #define  PMCR_RX_FC_EN			BIT(4)
283 #define  PMCR_FORCE_SPEED_1000		BIT(3)
284 #define  PMCR_FORCE_SPEED_100		BIT(2)
285 #define  PMCR_FORCE_FDX			BIT(1)
286 #define  PMCR_FORCE_LNK			BIT(0)
287 #define  PMCR_SPEED_MASK		(PMCR_FORCE_SPEED_100 | \
288 					 PMCR_FORCE_SPEED_1000)
289 #define  MT7531_FORCE_LNK		BIT(31)
290 #define  MT7531_FORCE_SPD		BIT(30)
291 #define  MT7531_FORCE_DPX		BIT(29)
292 #define  MT7531_FORCE_RX_FC		BIT(28)
293 #define  MT7531_FORCE_TX_FC		BIT(27)
294 #define  MT7531_FORCE_MODE		(MT7531_FORCE_LNK | \
295 					 MT7531_FORCE_SPD | \
296 					 MT7531_FORCE_DPX | \
297 					 MT7531_FORCE_RX_FC | \
298 					 MT7531_FORCE_TX_FC)
299 #define  PMCR_FORCE_MODE_ID(id)		((((id) == ID_MT7531) || ((id) == ID_MT7988)) ?	\
300 					 MT7531_FORCE_MODE : PMCR_FORCE_MODE)
301 #define  PMCR_LINK_SETTINGS_MASK	(PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \
302 					 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \
303 					 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
304 					 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \
305 					 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100)
306 #define  PMCR_CPU_PORT_SETTING(id)	(PMCR_FORCE_MODE_ID((id)) | \
307 					 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \
308 					 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \
309 					 PMCR_TX_EN | PMCR_RX_EN | \
310 					 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \
311 					 PMCR_FORCE_SPEED_1000 | \
312 					 PMCR_FORCE_FDX | PMCR_FORCE_LNK)
313 
314 #define MT7530_PMEEECR_P(x)		(0x3004 + (x) * 0x100)
315 #define  WAKEUP_TIME_1000(x)		(((x) & 0xFF) << 24)
316 #define  WAKEUP_TIME_100(x)		(((x) & 0xFF) << 16)
317 #define  LPI_THRESH_MASK		GENMASK(15, 4)
318 #define  LPI_THRESH_SHT			4
319 #define  SET_LPI_THRESH(x)		(((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK)
320 #define  GET_LPI_THRESH(x)		(((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT)
321 #define  LPI_MODE_EN			BIT(0)
322 
323 #define MT7530_PMSR_P(x)		(0x3008 + (x) * 0x100)
324 #define  PMSR_EEE1G			BIT(7)
325 #define  PMSR_EEE100M			BIT(6)
326 #define  PMSR_RX_FC			BIT(5)
327 #define  PMSR_TX_FC			BIT(4)
328 #define  PMSR_SPEED_1000		BIT(3)
329 #define  PMSR_SPEED_100			BIT(2)
330 #define  PMSR_SPEED_10			0x00
331 #define  PMSR_SPEED_MASK		(PMSR_SPEED_100 | PMSR_SPEED_1000)
332 #define  PMSR_DPX			BIT(1)
333 #define  PMSR_LINK			BIT(0)
334 
335 /* Register for port debug count */
336 #define MT7531_DBG_CNT(x)		(0x3018 + (x) * 0x100)
337 #define  MT7531_DIS_CLR			BIT(31)
338 
339 #define MT7530_GMACCR			0x30e0
340 #define  MAX_RX_JUMBO(x)		((x) << 2)
341 #define  MAX_RX_JUMBO_MASK		GENMASK(5, 2)
342 #define  MAX_RX_PKT_LEN_MASK		GENMASK(1, 0)
343 #define  MAX_RX_PKT_LEN_1522		0x0
344 #define  MAX_RX_PKT_LEN_1536		0x1
345 #define  MAX_RX_PKT_LEN_1552		0x2
346 #define  MAX_RX_PKT_LEN_JUMBO		0x3
347 
348 /* Register for MIB */
349 #define MT7530_PORT_MIB_COUNTER(x)	(0x4000 + (x) * 0x100)
350 #define MT7530_MIB_CCR			0x4fe0
351 #define  CCR_MIB_ENABLE			BIT(31)
352 #define  CCR_RX_OCT_CNT_GOOD		BIT(7)
353 #define  CCR_RX_OCT_CNT_BAD		BIT(6)
354 #define  CCR_TX_OCT_CNT_GOOD		BIT(5)
355 #define  CCR_TX_OCT_CNT_BAD		BIT(4)
356 #define  CCR_MIB_FLUSH			(CCR_RX_OCT_CNT_GOOD | \
357 					 CCR_RX_OCT_CNT_BAD | \
358 					 CCR_TX_OCT_CNT_GOOD | \
359 					 CCR_TX_OCT_CNT_BAD)
360 #define  CCR_MIB_ACTIVATE		(CCR_MIB_ENABLE | \
361 					 CCR_RX_OCT_CNT_GOOD | \
362 					 CCR_RX_OCT_CNT_BAD | \
363 					 CCR_TX_OCT_CNT_GOOD | \
364 					 CCR_TX_OCT_CNT_BAD)
365 
366 /* MT7531 SGMII register group */
367 #define MT7531_SGMII_REG_BASE(p)	(0x5000 + ((p) - 5) * 0x1000)
368 #define MT7531_PHYA_CTRL_SIGNAL3	0x128
369 
370 /* Register for system reset */
371 #define MT7530_SYS_CTRL			0x7000
372 #define  SYS_CTRL_PHY_RST		BIT(2)
373 #define  SYS_CTRL_SW_RST		BIT(1)
374 #define  SYS_CTRL_REG_RST		BIT(0)
375 
376 /* Register for system interrupt */
377 #define MT7530_SYS_INT_EN		0x7008
378 
379 /* Register for system interrupt status */
380 #define MT7530_SYS_INT_STS		0x700c
381 
382 /* Register for PHY Indirect Access Control */
383 #define MT7531_PHY_IAC			0x701C
384 #define  MT7531_PHY_ACS_ST		BIT(31)
385 #define  MT7531_MDIO_REG_ADDR_MASK	(0x1f << 25)
386 #define  MT7531_MDIO_PHY_ADDR_MASK	(0x1f << 20)
387 #define  MT7531_MDIO_CMD_MASK		(0x3 << 18)
388 #define  MT7531_MDIO_ST_MASK		(0x3 << 16)
389 #define  MT7531_MDIO_RW_DATA_MASK	(0xffff)
390 #define  MT7531_MDIO_REG_ADDR(x)	(((x) & 0x1f) << 25)
391 #define  MT7531_MDIO_DEV_ADDR(x)	(((x) & 0x1f) << 25)
392 #define  MT7531_MDIO_PHY_ADDR(x)	(((x) & 0x1f) << 20)
393 #define  MT7531_MDIO_CMD(x)		(((x) & 0x3) << 18)
394 #define  MT7531_MDIO_ST(x)		(((x) & 0x3) << 16)
395 
396 enum mt7531_phy_iac_cmd {
397 	MT7531_MDIO_ADDR = 0,
398 	MT7531_MDIO_WRITE = 1,
399 	MT7531_MDIO_READ = 2,
400 	MT7531_MDIO_READ_CL45 = 3,
401 };
402 
403 /* MDIO_ST: MDIO start field */
404 enum mt7531_mdio_st {
405 	MT7531_MDIO_ST_CL45 = 0,
406 	MT7531_MDIO_ST_CL22 = 1,
407 };
408 
409 #define  MT7531_MDIO_CL22_READ		(MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
410 					 MT7531_MDIO_CMD(MT7531_MDIO_READ))
411 #define  MT7531_MDIO_CL22_WRITE		(MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \
412 					 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
413 #define  MT7531_MDIO_CL45_ADDR		(MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
414 					 MT7531_MDIO_CMD(MT7531_MDIO_ADDR))
415 #define  MT7531_MDIO_CL45_READ		(MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
416 					 MT7531_MDIO_CMD(MT7531_MDIO_READ))
417 #define  MT7531_MDIO_CL45_WRITE		(MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \
418 					 MT7531_MDIO_CMD(MT7531_MDIO_WRITE))
419 
420 /* Register for RGMII clock phase */
421 #define MT7531_CLKGEN_CTRL		0x7500
422 #define  CLK_SKEW_OUT(x)		(((x) & 0x3) << 8)
423 #define  CLK_SKEW_OUT_MASK		GENMASK(9, 8)
424 #define  CLK_SKEW_IN(x)			(((x) & 0x3) << 6)
425 #define  CLK_SKEW_IN_MASK		GENMASK(7, 6)
426 #define  RXCLK_NO_DELAY			BIT(5)
427 #define  TXCLK_NO_REVERSE		BIT(4)
428 #define  GP_MODE(x)			(((x) & 0x3) << 1)
429 #define  GP_MODE_MASK			GENMASK(2, 1)
430 #define  GP_CLK_EN			BIT(0)
431 
432 enum mt7531_gp_mode {
433 	MT7531_GP_MODE_RGMII = 0,
434 	MT7531_GP_MODE_MII = 1,
435 	MT7531_GP_MODE_REV_MII = 2
436 };
437 
438 enum mt7531_clk_skew {
439 	MT7531_CLK_SKEW_NO_CHG = 0,
440 	MT7531_CLK_SKEW_DLY_100PPS = 1,
441 	MT7531_CLK_SKEW_DLY_200PPS = 2,
442 	MT7531_CLK_SKEW_REVERSE = 3,
443 };
444 
445 /* Register for hw trap status */
446 #define MT7530_HWTRAP			0x7800
447 #define  HWTRAP_XTAL_MASK		(BIT(10) | BIT(9))
448 #define  HWTRAP_XTAL_25MHZ		(BIT(10) | BIT(9))
449 #define  HWTRAP_XTAL_40MHZ		(BIT(10))
450 #define  HWTRAP_XTAL_20MHZ		(BIT(9))
451 
452 #define MT7531_HWTRAP			0x7800
453 #define  HWTRAP_XTAL_FSEL_MASK		BIT(7)
454 #define  HWTRAP_XTAL_FSEL_25MHZ		BIT(7)
455 #define  HWTRAP_XTAL_FSEL_40MHZ		0
456 /* Unique fields of (M)HWSTRAP for MT7531 */
457 #define  XTAL_FSEL_S			7
458 #define  XTAL_FSEL_M			BIT(7)
459 #define  PHY_EN				BIT(6)
460 #define  CHG_STRAP			BIT(8)
461 
462 /* Register for hw trap modification */
463 #define MT7530_MHWTRAP			0x7804
464 #define  MHWTRAP_PHY0_SEL		BIT(20)
465 #define  MHWTRAP_MANUAL			BIT(16)
466 #define  MHWTRAP_P5_MAC_SEL		BIT(13)
467 #define  MHWTRAP_P6_DIS			BIT(8)
468 #define  MHWTRAP_P5_RGMII_MODE		BIT(7)
469 #define  MHWTRAP_P5_DIS			BIT(6)
470 #define  MHWTRAP_PHY_ACCESS		BIT(5)
471 
472 /* Register for TOP signal control */
473 #define MT7530_TOP_SIG_CTRL		0x7808
474 #define  TOP_SIG_CTRL_NORMAL		(BIT(17) | BIT(16))
475 
476 #define MT7531_TOP_SIG_SR		0x780c
477 #define  PAD_DUAL_SGMII_EN		BIT(1)
478 #define  PAD_MCM_SMI_EN			BIT(0)
479 
480 #define MT7530_IO_DRV_CR		0x7810
481 #define  P5_IO_CLK_DRV(x)		((x) & 0x3)
482 #define  P5_IO_DATA_DRV(x)		(((x) & 0x3) << 4)
483 
484 #define MT7531_CHIP_REV			0x781C
485 
486 #define MT7531_PLLGP_EN			0x7820
487 #define  EN_COREPLL			BIT(2)
488 #define  SW_CLKSW			BIT(1)
489 #define  SW_PLLGP			BIT(0)
490 
491 #define MT7530_P6ECR			0x7830
492 #define  P6_INTF_MODE_MASK		0x3
493 #define  P6_INTF_MODE(x)		((x) & 0x3)
494 
495 #define MT7531_PLLGP_CR0		0x78a8
496 #define  RG_COREPLL_EN			BIT(22)
497 #define  RG_COREPLL_POSDIV_S		23
498 #define  RG_COREPLL_POSDIV_M		0x3800000
499 #define  RG_COREPLL_SDM_PCW_S		1
500 #define  RG_COREPLL_SDM_PCW_M		0x3ffffe
501 #define  RG_COREPLL_SDM_PCW_CHG		BIT(0)
502 
503 /* Registers for RGMII and SGMII PLL clock */
504 #define MT7531_ANA_PLLGP_CR2		0x78b0
505 #define MT7531_ANA_PLLGP_CR5		0x78bc
506 
507 /* Registers for TRGMII on the both side */
508 #define MT7530_TRGMII_RCK_CTRL		0x7a00
509 #define  RX_RST				BIT(31)
510 #define  RXC_DQSISEL			BIT(30)
511 #define  DQSI1_TAP_MASK			(0x7f << 8)
512 #define  DQSI0_TAP_MASK			0x7f
513 #define  DQSI1_TAP(x)			(((x) & 0x7f) << 8)
514 #define  DQSI0_TAP(x)			((x) & 0x7f)
515 
516 #define MT7530_TRGMII_RCK_RTT		0x7a04
517 #define  DQS1_GATE			BIT(31)
518 #define  DQS0_GATE			BIT(30)
519 
520 #define MT7530_TRGMII_RD(x)		(0x7a10 + (x) * 8)
521 #define  BSLIP_EN			BIT(31)
522 #define  EDGE_CHK			BIT(30)
523 #define  RD_TAP_MASK			0x7f
524 #define  RD_TAP(x)			((x) & 0x7f)
525 
526 #define MT7530_TRGMII_TXCTRL		0x7a40
527 #define  TRAIN_TXEN			BIT(31)
528 #define  TXC_INV			BIT(30)
529 #define  TX_RST				BIT(28)
530 
531 #define MT7530_TRGMII_TD_ODT(i)		(0x7a54 + 8 * (i))
532 #define  TD_DM_DRVP(x)			((x) & 0xf)
533 #define  TD_DM_DRVN(x)			(((x) & 0xf) << 4)
534 
535 #define MT7530_TRGMII_TCK_CTRL		0x7a78
536 #define  TCK_TAP(x)			(((x) & 0xf) << 8)
537 
538 #define MT7530_P5RGMIIRXCR		0x7b00
539 #define  CSR_RGMII_EDGE_ALIGN		BIT(8)
540 #define  CSR_RGMII_RXC_0DEG_CFG(x)	((x) & 0xf)
541 
542 #define MT7530_P5RGMIITXCR		0x7b04
543 #define  CSR_RGMII_TXC_CFG(x)		((x) & 0x1f)
544 
545 /* Registers for GPIO mode */
546 #define MT7531_GPIO_MODE0		0x7c0c
547 #define  MT7531_GPIO0_MASK		GENMASK(3, 0)
548 #define  MT7531_GPIO0_INTERRUPT		1
549 
550 #define MT7531_GPIO_MODE1		0x7c10
551 #define  MT7531_GPIO11_RG_RXD2_MASK	GENMASK(15, 12)
552 #define  MT7531_EXT_P_MDC_11		(2 << 12)
553 #define  MT7531_GPIO12_RG_RXD3_MASK	GENMASK(19, 16)
554 #define  MT7531_EXT_P_MDIO_12		(2 << 16)
555 
556 /* Registers for LED GPIO control (MT7530 only)
557  * All registers follow this pattern:
558  * [ 2: 0]  port 0
559  * [ 6: 4]  port 1
560  * [10: 8]  port 2
561  * [14:12]  port 3
562  * [18:16]  port 4
563  */
564 
565 /* LED enable, 0: Disable, 1: Enable (Default) */
566 #define MT7530_LED_EN			0x7d00
567 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */
568 #define MT7530_LED_IO_MODE		0x7d04
569 /* GPIO direction, 0: Input, 1: Output */
570 #define MT7530_LED_GPIO_DIR		0x7d10
571 /* GPIO output enable, 0: Disable, 1: Enable */
572 #define MT7530_LED_GPIO_OE		0x7d14
573 /* GPIO value, 0: Low, 1: High */
574 #define MT7530_LED_GPIO_DATA		0x7d18
575 
576 #define MT7530_CREV			0x7ffc
577 #define  CHIP_NAME_SHIFT		16
578 #define  MT7530_ID			0x7530
579 
580 #define MT7531_CREV			0x781C
581 #define  CHIP_REV_M			0x0f
582 #define  MT7531_ID			0x7531
583 
584 /* Registers for core PLL access through mmd indirect */
585 #define CORE_PLL_GROUP2			0x401
586 #define  RG_SYSPLL_EN_NORMAL		BIT(15)
587 #define  RG_SYSPLL_VODEN		BIT(14)
588 #define  RG_SYSPLL_LF			BIT(13)
589 #define  RG_SYSPLL_RST_DLY(x)		(((x) & 0x3) << 12)
590 #define  RG_SYSPLL_LVROD_EN		BIT(10)
591 #define  RG_SYSPLL_PREDIV(x)		(((x) & 0x3) << 8)
592 #define  RG_SYSPLL_POSDIV(x)		(((x) & 0x3) << 5)
593 #define  RG_SYSPLL_FBKSEL		BIT(4)
594 #define  RT_SYSPLL_EN_AFE_OLT		BIT(0)
595 
596 #define CORE_PLL_GROUP4			0x403
597 #define  RG_SYSPLL_DDSFBK_EN		BIT(12)
598 #define  RG_SYSPLL_BIAS_EN		BIT(11)
599 #define  RG_SYSPLL_BIAS_LPF_EN		BIT(10)
600 #define  MT7531_PHY_PLL_OFF		BIT(5)
601 #define  MT7531_PHY_PLL_BYPASS_MODE	BIT(4)
602 
603 #define MT753X_CTRL_PHY_ADDR		0
604 
605 #define CORE_PLL_GROUP5			0x404
606 #define  RG_LCDDS_PCW_NCPO1(x)		((x) & 0xffff)
607 
608 #define CORE_PLL_GROUP6			0x405
609 #define  RG_LCDDS_PCW_NCPO0(x)		((x) & 0xffff)
610 
611 #define CORE_PLL_GROUP7			0x406
612 #define  RG_LCDDS_PWDB			BIT(15)
613 #define  RG_LCDDS_ISO_EN		BIT(13)
614 #define  RG_LCCDS_C(x)			(((x) & 0x7) << 4)
615 #define  RG_LCDDS_PCW_NCPO_CHG		BIT(3)
616 
617 #define CORE_PLL_GROUP10		0x409
618 #define  RG_LCDDS_SSC_DELTA(x)		((x) & 0xfff)
619 
620 #define CORE_PLL_GROUP11		0x40a
621 #define  RG_LCDDS_SSC_DELTA1(x)		((x) & 0xfff)
622 
623 #define CORE_GSWPLL_GRP1		0x40d
624 #define  RG_GSWPLL_PREDIV(x)		(((x) & 0x3) << 14)
625 #define  RG_GSWPLL_POSDIV_200M(x)	(((x) & 0x3) << 12)
626 #define  RG_GSWPLL_EN_PRE		BIT(11)
627 #define  RG_GSWPLL_FBKSEL		BIT(10)
628 #define  RG_GSWPLL_BP			BIT(9)
629 #define  RG_GSWPLL_BR			BIT(8)
630 #define  RG_GSWPLL_FBKDIV_200M(x)	((x) & 0xff)
631 
632 #define CORE_GSWPLL_GRP2		0x40e
633 #define  RG_GSWPLL_POSDIV_500M(x)	(((x) & 0x3) << 8)
634 #define  RG_GSWPLL_FBKDIV_500M(x)	((x) & 0xff)
635 
636 #define CORE_TRGMII_GSW_CLK_CG		0x410
637 #define  REG_GSWCK_EN			BIT(0)
638 #define  REG_TRGMIICK_EN		BIT(1)
639 
640 #define MIB_DESC(_s, _o, _n)	\
641 	{			\
642 		.size = (_s),	\
643 		.offset = (_o),	\
644 		.name = (_n),	\
645 	}
646 
647 struct mt7530_mib_desc {
648 	unsigned int size;
649 	unsigned int offset;
650 	const char *name;
651 };
652 
653 struct mt7530_fdb {
654 	u16 vid;
655 	u8 port_mask;
656 	u8 aging;
657 	u8 mac[6];
658 	bool noarp;
659 };
660 
661 /* struct mt7530_port -	This is the main data structure for holding the state
662  *			of the port.
663  * @enable:	The status used for show port is enabled or not.
664  * @pm:		The matrix used to show all connections with the port.
665  * @pvid:	The VLAN specified is to be considered a PVID at ingress.  Any
666  *		untagged frames will be assigned to the related VLAN.
667  * @sgmii_pcs:	Pointer to PCS instance for SerDes ports
668  */
669 struct mt7530_port {
670 	bool enable;
671 	u32 pm;
672 	u16 pvid;
673 	struct phylink_pcs *sgmii_pcs;
674 };
675 
676 /* Port 5 interface select definitions */
677 enum p5_interface_select {
678 	P5_DISABLED = 0,
679 	P5_INTF_SEL_PHY_P0,
680 	P5_INTF_SEL_PHY_P4,
681 	P5_INTF_SEL_GMAC5,
682 	P5_INTF_SEL_GMAC5_SGMII,
683 };
684 
685 struct mt7530_priv;
686 
687 struct mt753x_pcs {
688 	struct phylink_pcs pcs;
689 	struct mt7530_priv *priv;
690 	int port;
691 };
692 
693 /* struct mt753x_info -	This is the main data structure for holding the specific
694  *			part for each supported device
695  * @sw_setup:		Holding the handler to a device initialization
696  * @phy_read_c22:	Holding the way reading PHY port using C22
697  * @phy_write_c22:	Holding the way writing PHY port using C22
698  * @phy_read_c45:	Holding the way reading PHY port using C45
699  * @phy_write_c45:	Holding the way writing PHY port using C45
700  * @pad_setup:		Holding the way setting up the bus pad for a certain
701  *			MAC port
702  * @phy_mode_supported:	Check if the PHY type is being supported on a certain
703  *			port
704  * @mac_port_validate:	Holding the way to set addition validate type for a
705  *			certan MAC port
706  * @mac_port_config:	Holding the way setting up the PHY attribute to a
707  *			certain MAC port
708  */
709 struct mt753x_info {
710 	enum mt753x_id id;
711 
712 	const struct phylink_pcs_ops *pcs_ops;
713 
714 	int (*sw_setup)(struct dsa_switch *ds);
715 	int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum);
716 	int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum,
717 			     u16 val);
718 	int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad,
719 			    int regnum);
720 	int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad,
721 			     int regnum, u16 val);
722 	int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface);
723 	int (*cpu_port_config)(struct dsa_switch *ds, int port);
724 	void (*mac_port_get_caps)(struct dsa_switch *ds, int port,
725 				  struct phylink_config *config);
726 	void (*mac_port_validate)(struct dsa_switch *ds, int port,
727 				  phy_interface_t interface,
728 				  unsigned long *supported);
729 	int (*mac_port_config)(struct dsa_switch *ds, int port,
730 			       unsigned int mode,
731 			       phy_interface_t interface);
732 };
733 
734 /* struct mt7530_priv -	This is the main data structure for holding the state
735  *			of the driver
736  * @dev:		The device pointer
737  * @ds:			The pointer to the dsa core structure
738  * @bus:		The bus used for the device and built-in PHY
739  * @regmap:		The regmap instance representing all switch registers
740  * @rstc:		The pointer to reset control used by MCM
741  * @core_pwr:		The power supplied into the core
742  * @io_pwr:		The power supplied into the I/O
743  * @reset:		The descriptor for GPIO line tied to its reset pin
744  * @mcm:		Flag for distinguishing if standalone IC or module
745  *			coupling
746  * @ports:		Holding the state among ports
747  * @reg_mutex:		The lock for protecting among process accessing
748  *			registers
749  * @p6_interface	Holding the current port 6 interface
750  * @p5_intf_sel:	Holding the current port 5 interface select
751  * @irq:		IRQ number of the switch
752  * @irq_domain:		IRQ domain of the switch irq_chip
753  * @irq_enable:		IRQ enable bits, synced to SYS_INT_EN
754  * @create_sgmii:	Pointer to function creating SGMII PCS instance(s)
755  */
756 struct mt7530_priv {
757 	struct device		*dev;
758 	struct dsa_switch	*ds;
759 	struct mii_bus		*bus;
760 	struct regmap		*regmap;
761 	struct reset_control	*rstc;
762 	struct regulator	*core_pwr;
763 	struct regulator	*io_pwr;
764 	struct gpio_desc	*reset;
765 	const struct mt753x_info *info;
766 	unsigned int		id;
767 	bool			mcm;
768 	phy_interface_t		p6_interface;
769 	phy_interface_t		p5_interface;
770 	unsigned int		p5_intf_sel;
771 	u8			mirror_rx;
772 	u8			mirror_tx;
773 	struct mt7530_port	ports[MT7530_NUM_PORTS];
774 	struct mt753x_pcs	pcs[MT7530_NUM_PORTS];
775 	/* protect among processes for registers access*/
776 	struct mutex reg_mutex;
777 	int irq;
778 	struct irq_domain *irq_domain;
779 	u32 irq_enable;
780 	int (*create_sgmii)(struct mt7530_priv *priv, bool dual_sgmii);
781 };
782 
783 struct mt7530_hw_vlan_entry {
784 	int port;
785 	u8  old_members;
786 	bool untagged;
787 };
788 
789 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e,
790 					     int port, bool untagged)
791 {
792 	e->port = port;
793 	e->untagged = untagged;
794 }
795 
796 typedef void (*mt7530_vlan_op)(struct mt7530_priv *,
797 			       struct mt7530_hw_vlan_entry *);
798 
799 struct mt7530_hw_stats {
800 	const char	*string;
801 	u16		reg;
802 	u8		sizeof_stat;
803 };
804 
805 struct mt7530_dummy_poll {
806 	struct mt7530_priv *priv;
807 	u32 reg;
808 };
809 
810 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p,
811 					  struct mt7530_priv *priv, u32 reg)
812 {
813 	p->priv = priv;
814 	p->reg = reg;
815 }
816 
817 int mt7530_probe_common(struct mt7530_priv *priv);
818 void mt7530_remove_common(struct mt7530_priv *priv);
819 
820 extern const struct dsa_switch_ops mt7530_switch_ops;
821 extern const struct mt753x_info mt753x_table[];
822 
823 #endif /* __MT7530_H */
824