1 /* 2 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 3 * 4 * This program is free software; you can redistribute it and/or modify 5 * it under the terms of the GNU General Public License version 2 as 6 * published by the Free Software Foundation. 7 * 8 * This program is distributed in the hope that it will be useful, 9 * but WITHOUT ANY WARRANTY; without even the implied warranty of 10 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 11 * GNU General Public License for more details. 12 */ 13 14 #ifndef __MT7530_H 15 #define __MT7530_H 16 17 #define MT7530_NUM_PORTS 7 18 #define MT7530_CPU_PORT 6 19 #define MT7530_NUM_FDB_RECORDS 2048 20 21 #define NUM_TRGMII_CTRL 5 22 23 #define TRGMII_BASE(x) (0x10000 + (x)) 24 25 /* Registers to ethsys access */ 26 #define ETHSYS_CLKCFG0 0x2c 27 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 28 29 #define SYSC_REG_RSTCTRL 0x34 30 #define RESET_MCM BIT(2) 31 32 /* Registers to mac forward control for unknown frames */ 33 #define MT7530_MFC 0x10 34 #define BC_FFP(x) (((x) & 0xff) << 24) 35 #define UNM_FFP(x) (((x) & 0xff) << 16) 36 #define UNU_FFP(x) (((x) & 0xff) << 8) 37 #define UNU_FFP_MASK UNU_FFP(~0) 38 39 /* Registers for address table access */ 40 #define MT7530_ATA1 0x74 41 #define STATIC_EMP 0 42 #define STATIC_ENT 3 43 #define MT7530_ATA2 0x78 44 45 /* Register for address table write data */ 46 #define MT7530_ATWD 0x7c 47 48 /* Register for address table control */ 49 #define MT7530_ATC 0x80 50 #define ATC_HASH (((x) & 0xfff) << 16) 51 #define ATC_BUSY BIT(15) 52 #define ATC_SRCH_END BIT(14) 53 #define ATC_SRCH_HIT BIT(13) 54 #define ATC_INVALID BIT(12) 55 #define ATC_MAT(x) (((x) & 0xf) << 8) 56 #define ATC_MAT_MACTAB ATC_MAT(0) 57 58 enum mt7530_fdb_cmd { 59 MT7530_FDB_READ = 0, 60 MT7530_FDB_WRITE = 1, 61 MT7530_FDB_FLUSH = 2, 62 MT7530_FDB_START = 4, 63 MT7530_FDB_NEXT = 5, 64 }; 65 66 /* Registers for table search read address */ 67 #define MT7530_TSRA1 0x84 68 #define MAC_BYTE_0 24 69 #define MAC_BYTE_1 16 70 #define MAC_BYTE_2 8 71 #define MAC_BYTE_3 0 72 #define MAC_BYTE_MASK 0xff 73 74 #define MT7530_TSRA2 0x88 75 #define MAC_BYTE_4 24 76 #define MAC_BYTE_5 16 77 #define CVID 0 78 #define CVID_MASK 0xfff 79 80 #define MT7530_ATRD 0x8C 81 #define AGE_TIMER 24 82 #define AGE_TIMER_MASK 0xff 83 #define PORT_MAP 4 84 #define PORT_MAP_MASK 0xff 85 #define ENT_STATUS 2 86 #define ENT_STATUS_MASK 0x3 87 88 /* Register for vlan table control */ 89 #define MT7530_VTCR 0x90 90 #define VTCR_BUSY BIT(31) 91 #define VTCR_FUNC (((x) & 0xf) << 12) 92 #define VTCR_FUNC_RD_VID 0x1 93 #define VTCR_FUNC_WR_VID 0x2 94 #define VTCR_FUNC_INV_VID 0x3 95 #define VTCR_FUNC_VAL_VID 0x4 96 #define VTCR_VID ((x) & 0xfff) 97 98 /* Register for setup vlan and acl write data */ 99 #define MT7530_VAWD1 0x94 100 #define PORT_STAG BIT(31) 101 #define IVL_MAC BIT(30) 102 #define PORT_MEM(x) (((x) & 0xff) << 16) 103 #define VALID BIT(1) 104 105 #define MT7530_VAWD2 0x98 106 107 /* Register for port STP state control */ 108 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 109 #define FID_PST(x) ((x) & 0x3) 110 #define FID_PST_MASK FID_PST(0x3) 111 112 enum mt7530_stp_state { 113 MT7530_STP_DISABLED = 0, 114 MT7530_STP_BLOCKING = 1, 115 MT7530_STP_LISTENING = 1, 116 MT7530_STP_LEARNING = 2, 117 MT7530_STP_FORWARDING = 3 118 }; 119 120 /* Register for port control */ 121 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 122 #define PORT_VLAN(x) ((x) & 0x3) 123 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 124 #define PORT_PRI(x) (((x) & 0x7) << 24) 125 #define EG_TAG(x) (((x) & 0x3) << 28) 126 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 127 #define PCR_MATRIX_CLR PCR_MATRIX(0) 128 129 /* Register for port security control */ 130 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 131 #define SA_DIS BIT(4) 132 133 /* Register for port vlan control */ 134 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 135 #define PORT_SPEC_TAG BIT(5) 136 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 137 #define STAG_VPID (((x) & 0xffff) << 16) 138 139 /* Register for port port-and-protocol based vlan 1 control */ 140 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 141 142 /* Register for port MAC control register */ 143 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 144 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 145 #define PMCR_MAC_MODE BIT(16) 146 #define PMCR_FORCE_MODE BIT(15) 147 #define PMCR_TX_EN BIT(14) 148 #define PMCR_RX_EN BIT(13) 149 #define PMCR_BACKOFF_EN BIT(9) 150 #define PMCR_BACKPR_EN BIT(8) 151 #define PMCR_TX_FC_EN BIT(5) 152 #define PMCR_RX_FC_EN BIT(4) 153 #define PMCR_FORCE_SPEED_1000 BIT(3) 154 #define PMCR_FORCE_SPEED_100 BIT(2) 155 #define PMCR_FORCE_FDX BIT(1) 156 #define PMCR_FORCE_LNK BIT(0) 157 #define PMCR_COMMON_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ 158 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ 159 PMCR_TX_EN | PMCR_RX_EN | \ 160 PMCR_TX_FC_EN | PMCR_RX_FC_EN) 161 #define PMCR_CPUP_LINK (PMCR_COMMON_LINK | PMCR_FORCE_MODE | \ 162 PMCR_FORCE_SPEED_1000 | \ 163 PMCR_FORCE_FDX | \ 164 PMCR_FORCE_LNK) 165 #define PMCR_USERP_LINK PMCR_COMMON_LINK 166 #define PMCR_FIXED_LINK (PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ 167 PMCR_FORCE_MODE | PMCR_TX_EN | \ 168 PMCR_RX_EN | PMCR_BACKPR_EN | \ 169 PMCR_BACKOFF_EN | \ 170 PMCR_FORCE_SPEED_1000 | \ 171 PMCR_FORCE_FDX | \ 172 PMCR_FORCE_LNK) 173 #define PMCR_FIXED_LINK_FC (PMCR_FIXED_LINK | \ 174 PMCR_TX_FC_EN | PMCR_RX_FC_EN) 175 176 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 177 178 /* Register for MIB */ 179 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 180 #define MT7530_MIB_CCR 0x4fe0 181 #define CCR_MIB_ENABLE BIT(31) 182 #define CCR_RX_OCT_CNT_GOOD BIT(7) 183 #define CCR_RX_OCT_CNT_BAD BIT(6) 184 #define CCR_TX_OCT_CNT_GOOD BIT(5) 185 #define CCR_TX_OCT_CNT_BAD BIT(4) 186 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 187 CCR_RX_OCT_CNT_BAD | \ 188 CCR_TX_OCT_CNT_GOOD | \ 189 CCR_TX_OCT_CNT_BAD) 190 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 191 CCR_RX_OCT_CNT_GOOD | \ 192 CCR_RX_OCT_CNT_BAD | \ 193 CCR_TX_OCT_CNT_GOOD | \ 194 CCR_TX_OCT_CNT_BAD) 195 /* Register for system reset */ 196 #define MT7530_SYS_CTRL 0x7000 197 #define SYS_CTRL_PHY_RST BIT(2) 198 #define SYS_CTRL_SW_RST BIT(1) 199 #define SYS_CTRL_REG_RST BIT(0) 200 201 /* Register for hw trap status */ 202 #define MT7530_HWTRAP 0x7800 203 204 /* Register for hw trap modification */ 205 #define MT7530_MHWTRAP 0x7804 206 #define MHWTRAP_MANUAL BIT(16) 207 #define MHWTRAP_P5_MAC_SEL BIT(13) 208 #define MHWTRAP_P6_DIS BIT(8) 209 #define MHWTRAP_P5_RGMII_MODE BIT(7) 210 #define MHWTRAP_P5_DIS BIT(6) 211 #define MHWTRAP_PHY_ACCESS BIT(5) 212 213 /* Register for TOP signal control */ 214 #define MT7530_TOP_SIG_CTRL 0x7808 215 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 216 217 #define MT7530_IO_DRV_CR 0x7810 218 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 219 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 220 221 #define MT7530_P6ECR 0x7830 222 #define P6_INTF_MODE_MASK 0x3 223 #define P6_INTF_MODE(x) ((x) & 0x3) 224 225 /* Registers for TRGMII on the both side */ 226 #define MT7530_TRGMII_RCK_CTRL 0x7a00 227 #define GSW_TRGMII_RCK_CTRL 0x300 228 #define RX_RST BIT(31) 229 #define RXC_DQSISEL BIT(30) 230 #define DQSI1_TAP_MASK (0x7f << 8) 231 #define DQSI0_TAP_MASK 0x7f 232 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 233 #define DQSI0_TAP(x) ((x) & 0x7f) 234 235 #define MT7530_TRGMII_RCK_RTT 0x7a04 236 #define GSW_TRGMII_RCK_RTT 0x304 237 #define DQS1_GATE BIT(31) 238 #define DQS0_GATE BIT(30) 239 240 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 241 #define GSW_TRGMII_RD(x) (0x310 + (x) * 8) 242 #define BSLIP_EN BIT(31) 243 #define EDGE_CHK BIT(30) 244 #define RD_TAP_MASK 0x7f 245 #define RD_TAP(x) ((x) & 0x7f) 246 247 #define GSW_TRGMII_TXCTRL 0x340 248 #define MT7530_TRGMII_TXCTRL 0x7a40 249 #define TRAIN_TXEN BIT(31) 250 #define TXC_INV BIT(30) 251 #define TX_RST BIT(28) 252 253 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 254 #define GSW_TRGMII_TD_ODT(i) (0x354 + 8 * (i)) 255 #define TD_DM_DRVP(x) ((x) & 0xf) 256 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 257 258 #define GSW_INTF_MODE 0x390 259 #define INTF_MODE_TRGMII BIT(1) 260 261 #define MT7530_TRGMII_TCK_CTRL 0x7a78 262 #define TCK_TAP(x) (((x) & 0xf) << 8) 263 264 #define MT7530_P5RGMIIRXCR 0x7b00 265 #define CSR_RGMII_EDGE_ALIGN BIT(8) 266 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 267 268 #define MT7530_P5RGMIITXCR 0x7b04 269 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 270 271 #define MT7530_CREV 0x7ffc 272 #define CHIP_NAME_SHIFT 16 273 #define MT7530_ID 0x7530 274 275 /* Registers for core PLL access through mmd indirect */ 276 #define CORE_PLL_GROUP2 0x401 277 #define RG_SYSPLL_EN_NORMAL BIT(15) 278 #define RG_SYSPLL_VODEN BIT(14) 279 #define RG_SYSPLL_LF BIT(13) 280 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 281 #define RG_SYSPLL_LVROD_EN BIT(10) 282 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 283 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 284 #define RG_SYSPLL_FBKSEL BIT(4) 285 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 286 287 #define CORE_PLL_GROUP4 0x403 288 #define RG_SYSPLL_DDSFBK_EN BIT(12) 289 #define RG_SYSPLL_BIAS_EN BIT(11) 290 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 291 292 #define CORE_PLL_GROUP5 0x404 293 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 294 295 #define CORE_PLL_GROUP6 0x405 296 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 297 298 #define CORE_PLL_GROUP7 0x406 299 #define RG_LCDDS_PWDB BIT(15) 300 #define RG_LCDDS_ISO_EN BIT(13) 301 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 302 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 303 304 #define CORE_PLL_GROUP10 0x409 305 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 306 307 #define CORE_PLL_GROUP11 0x40a 308 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 309 310 #define CORE_GSWPLL_GRP1 0x40d 311 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 312 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 313 #define RG_GSWPLL_EN_PRE BIT(11) 314 #define RG_GSWPLL_FBKSEL BIT(10) 315 #define RG_GSWPLL_BP BIT(9) 316 #define RG_GSWPLL_BR BIT(8) 317 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 318 319 #define CORE_GSWPLL_GRP2 0x40e 320 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 321 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 322 323 #define CORE_TRGMII_GSW_CLK_CG 0x410 324 #define REG_GSWCK_EN BIT(0) 325 #define REG_TRGMIICK_EN BIT(1) 326 327 #define MIB_DESC(_s, _o, _n) \ 328 { \ 329 .size = (_s), \ 330 .offset = (_o), \ 331 .name = (_n), \ 332 } 333 334 struct mt7530_mib_desc { 335 unsigned int size; 336 unsigned int offset; 337 const char *name; 338 }; 339 340 struct mt7530_fdb { 341 u16 vid; 342 u8 port_mask; 343 u8 aging; 344 u8 mac[6]; 345 bool noarp; 346 }; 347 348 struct mt7530_port { 349 bool enable; 350 u32 pm; 351 }; 352 353 /* struct mt7530_priv - This is the main data structure for holding the state 354 * of the driver 355 * @dev: The device pointer 356 * @ds: The pointer to the dsa core structure 357 * @bus: The bus used for the device and built-in PHY 358 * @rstc: The pointer to reset control used by MCM 359 * @ethernet: The regmap used for access TRGMII-based registers 360 * @core_pwr: The power supplied into the core 361 * @io_pwr: The power supplied into the I/O 362 * @reset: The descriptor for GPIO line tied to its reset pin 363 * @mcm: Flag for distinguishing if standalone IC or module 364 * coupling 365 * @ports: Holding the state among ports 366 * @reg_mutex: The lock for protecting among process accessing 367 * registers 368 */ 369 struct mt7530_priv { 370 struct device *dev; 371 struct dsa_switch *ds; 372 struct mii_bus *bus; 373 struct reset_control *rstc; 374 struct regmap *ethernet; 375 struct regulator *core_pwr; 376 struct regulator *io_pwr; 377 struct gpio_desc *reset; 378 bool mcm; 379 380 struct mt7530_port ports[MT7530_NUM_PORTS]; 381 /* protect among processes for registers access*/ 382 struct mutex reg_mutex; 383 }; 384 385 struct mt7530_hw_stats { 386 const char *string; 387 u16 reg; 388 u8 sizeof_stat; 389 }; 390 391 struct mt7530_dummy_poll { 392 struct mt7530_priv *priv; 393 u32 reg; 394 }; 395 396 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 397 struct mt7530_priv *priv, u32 reg) 398 { 399 p->priv = priv; 400 p->reg = reg; 401 } 402 403 #endif /* __MT7530_H */ 404