1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_CPU_PORT 6 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 enum { 15 ID_MT7530 = 0, 16 ID_MT7621 = 1, 17 }; 18 19 #define NUM_TRGMII_CTRL 5 20 21 #define TRGMII_BASE(x) (0x10000 + (x)) 22 23 /* Registers to ethsys access */ 24 #define ETHSYS_CLKCFG0 0x2c 25 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 26 27 #define SYSC_REG_RSTCTRL 0x34 28 #define RESET_MCM BIT(2) 29 30 /* Registers to mac forward control for unknown frames */ 31 #define MT7530_MFC 0x10 32 #define BC_FFP(x) (((x) & 0xff) << 24) 33 #define UNM_FFP(x) (((x) & 0xff) << 16) 34 #define UNM_FFP_MASK UNM_FFP(~0) 35 #define UNU_FFP(x) (((x) & 0xff) << 8) 36 #define UNU_FFP_MASK UNU_FFP(~0) 37 #define CPU_EN BIT(7) 38 #define CPU_PORT(x) ((x) << 4) 39 #define CPU_MASK (0xf << 4) 40 #define MIRROR_EN BIT(3) 41 #define MIRROR_PORT(x) ((x) & 0x7) 42 #define MIRROR_MASK 0x7 43 44 /* Registers for address table access */ 45 #define MT7530_ATA1 0x74 46 #define STATIC_EMP 0 47 #define STATIC_ENT 3 48 #define MT7530_ATA2 0x78 49 50 /* Register for address table write data */ 51 #define MT7530_ATWD 0x7c 52 53 /* Register for address table control */ 54 #define MT7530_ATC 0x80 55 #define ATC_HASH (((x) & 0xfff) << 16) 56 #define ATC_BUSY BIT(15) 57 #define ATC_SRCH_END BIT(14) 58 #define ATC_SRCH_HIT BIT(13) 59 #define ATC_INVALID BIT(12) 60 #define ATC_MAT(x) (((x) & 0xf) << 8) 61 #define ATC_MAT_MACTAB ATC_MAT(0) 62 63 enum mt7530_fdb_cmd { 64 MT7530_FDB_READ = 0, 65 MT7530_FDB_WRITE = 1, 66 MT7530_FDB_FLUSH = 2, 67 MT7530_FDB_START = 4, 68 MT7530_FDB_NEXT = 5, 69 }; 70 71 /* Registers for table search read address */ 72 #define MT7530_TSRA1 0x84 73 #define MAC_BYTE_0 24 74 #define MAC_BYTE_1 16 75 #define MAC_BYTE_2 8 76 #define MAC_BYTE_3 0 77 #define MAC_BYTE_MASK 0xff 78 79 #define MT7530_TSRA2 0x88 80 #define MAC_BYTE_4 24 81 #define MAC_BYTE_5 16 82 #define CVID 0 83 #define CVID_MASK 0xfff 84 85 #define MT7530_ATRD 0x8C 86 #define AGE_TIMER 24 87 #define AGE_TIMER_MASK 0xff 88 #define PORT_MAP 4 89 #define PORT_MAP_MASK 0xff 90 #define ENT_STATUS 2 91 #define ENT_STATUS_MASK 0x3 92 93 /* Register for vlan table control */ 94 #define MT7530_VTCR 0x90 95 #define VTCR_BUSY BIT(31) 96 #define VTCR_INVALID BIT(16) 97 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 98 #define VTCR_VID ((x) & 0xfff) 99 100 enum mt7530_vlan_cmd { 101 /* Read/Write the specified VID entry from VAWD register based 102 * on VID. 103 */ 104 MT7530_VTCR_RD_VID = 0, 105 MT7530_VTCR_WR_VID = 1, 106 }; 107 108 /* Register for setup vlan and acl write data */ 109 #define MT7530_VAWD1 0x94 110 #define PORT_STAG BIT(31) 111 /* Independent VLAN Learning */ 112 #define IVL_MAC BIT(30) 113 /* Per VLAN Egress Tag Control */ 114 #define VTAG_EN BIT(28) 115 /* VLAN Member Control */ 116 #define PORT_MEM(x) (((x) & 0xff) << 16) 117 /* VLAN Entry Valid */ 118 #define VLAN_VALID BIT(0) 119 #define PORT_MEM_SHFT 16 120 #define PORT_MEM_MASK 0xff 121 122 #define MT7530_VAWD2 0x98 123 /* Egress Tag Control */ 124 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 125 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 126 127 enum mt7530_vlan_egress_attr { 128 MT7530_VLAN_EGRESS_UNTAG = 0, 129 MT7530_VLAN_EGRESS_TAG = 2, 130 MT7530_VLAN_EGRESS_STACK = 3, 131 }; 132 133 /* Register for port STP state control */ 134 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 135 #define FID_PST(x) ((x) & 0x3) 136 #define FID_PST_MASK FID_PST(0x3) 137 138 enum mt7530_stp_state { 139 MT7530_STP_DISABLED = 0, 140 MT7530_STP_BLOCKING = 1, 141 MT7530_STP_LISTENING = 1, 142 MT7530_STP_LEARNING = 2, 143 MT7530_STP_FORWARDING = 3 144 }; 145 146 /* Register for port control */ 147 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 148 #define PORT_TX_MIR BIT(9) 149 #define PORT_RX_MIR BIT(8) 150 #define PORT_VLAN(x) ((x) & 0x3) 151 152 enum mt7530_port_mode { 153 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 154 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 155 156 /* Fallback Mode: Forward received frames with ingress ports that do 157 * not belong to the VLAN member. Frames whose VID is not listed on 158 * the VLAN table are forwarded by the PCR_MATRIX members. 159 */ 160 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 161 162 /* Security Mode: Discard any frame due to ingress membership 163 * violation or VID missed on the VLAN table. 164 */ 165 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 166 }; 167 168 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 169 #define PORT_PRI(x) (((x) & 0x7) << 24) 170 #define EG_TAG(x) (((x) & 0x3) << 28) 171 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 172 #define PCR_MATRIX_CLR PCR_MATRIX(0) 173 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 174 175 /* Register for port security control */ 176 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 177 #define SA_DIS BIT(4) 178 179 /* Register for port vlan control */ 180 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 181 #define PORT_SPEC_TAG BIT(5) 182 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 183 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 184 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 185 #define VLAN_ATTR_MASK VLAN_ATTR(3) 186 187 enum mt7530_vlan_port_eg_tag { 188 MT7530_VLAN_EG_DISABLED = 0, 189 MT7530_VLAN_EG_CONSISTENT = 1, 190 }; 191 192 enum mt7530_vlan_port_attr { 193 MT7530_VLAN_USER = 0, 194 MT7530_VLAN_TRANSPARENT = 3, 195 }; 196 197 #define STAG_VPID (((x) & 0xffff) << 16) 198 199 /* Register for port port-and-protocol based vlan 1 control */ 200 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 201 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 202 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 203 #define G0_PORT_VID_DEF G0_PORT_VID(1) 204 205 /* Register for port MAC control register */ 206 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 207 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 208 #define PMCR_EXT_PHY BIT(17) 209 #define PMCR_MAC_MODE BIT(16) 210 #define PMCR_FORCE_MODE BIT(15) 211 #define PMCR_TX_EN BIT(14) 212 #define PMCR_RX_EN BIT(13) 213 #define PMCR_BACKOFF_EN BIT(9) 214 #define PMCR_BACKPR_EN BIT(8) 215 #define PMCR_TX_FC_EN BIT(5) 216 #define PMCR_RX_FC_EN BIT(4) 217 #define PMCR_FORCE_SPEED_1000 BIT(3) 218 #define PMCR_FORCE_SPEED_100 BIT(2) 219 #define PMCR_FORCE_FDX BIT(1) 220 #define PMCR_FORCE_LNK BIT(0) 221 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 222 PMCR_FORCE_SPEED_1000) 223 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 224 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 225 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 226 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 227 228 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 229 #define PMSR_EEE1G BIT(7) 230 #define PMSR_EEE100M BIT(6) 231 #define PMSR_RX_FC BIT(5) 232 #define PMSR_TX_FC BIT(4) 233 #define PMSR_SPEED_1000 BIT(3) 234 #define PMSR_SPEED_100 BIT(2) 235 #define PMSR_SPEED_10 0x00 236 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 237 #define PMSR_DPX BIT(1) 238 #define PMSR_LINK BIT(0) 239 240 /* Register for MIB */ 241 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 242 #define MT7530_MIB_CCR 0x4fe0 243 #define CCR_MIB_ENABLE BIT(31) 244 #define CCR_RX_OCT_CNT_GOOD BIT(7) 245 #define CCR_RX_OCT_CNT_BAD BIT(6) 246 #define CCR_TX_OCT_CNT_GOOD BIT(5) 247 #define CCR_TX_OCT_CNT_BAD BIT(4) 248 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 249 CCR_RX_OCT_CNT_BAD | \ 250 CCR_TX_OCT_CNT_GOOD | \ 251 CCR_TX_OCT_CNT_BAD) 252 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 253 CCR_RX_OCT_CNT_GOOD | \ 254 CCR_RX_OCT_CNT_BAD | \ 255 CCR_TX_OCT_CNT_GOOD | \ 256 CCR_TX_OCT_CNT_BAD) 257 /* Register for system reset */ 258 #define MT7530_SYS_CTRL 0x7000 259 #define SYS_CTRL_PHY_RST BIT(2) 260 #define SYS_CTRL_SW_RST BIT(1) 261 #define SYS_CTRL_REG_RST BIT(0) 262 263 /* Register for hw trap status */ 264 #define MT7530_HWTRAP 0x7800 265 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 266 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 267 #define HWTRAP_XTAL_40MHZ (BIT(10)) 268 #define HWTRAP_XTAL_20MHZ (BIT(9)) 269 270 /* Register for hw trap modification */ 271 #define MT7530_MHWTRAP 0x7804 272 #define MHWTRAP_PHY0_SEL BIT(20) 273 #define MHWTRAP_MANUAL BIT(16) 274 #define MHWTRAP_P5_MAC_SEL BIT(13) 275 #define MHWTRAP_P6_DIS BIT(8) 276 #define MHWTRAP_P5_RGMII_MODE BIT(7) 277 #define MHWTRAP_P5_DIS BIT(6) 278 #define MHWTRAP_PHY_ACCESS BIT(5) 279 280 /* Register for TOP signal control */ 281 #define MT7530_TOP_SIG_CTRL 0x7808 282 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 283 284 #define MT7530_IO_DRV_CR 0x7810 285 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 286 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 287 288 #define MT7530_P6ECR 0x7830 289 #define P6_INTF_MODE_MASK 0x3 290 #define P6_INTF_MODE(x) ((x) & 0x3) 291 292 /* Registers for TRGMII on the both side */ 293 #define MT7530_TRGMII_RCK_CTRL 0x7a00 294 #define RX_RST BIT(31) 295 #define RXC_DQSISEL BIT(30) 296 #define DQSI1_TAP_MASK (0x7f << 8) 297 #define DQSI0_TAP_MASK 0x7f 298 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 299 #define DQSI0_TAP(x) ((x) & 0x7f) 300 301 #define MT7530_TRGMII_RCK_RTT 0x7a04 302 #define DQS1_GATE BIT(31) 303 #define DQS0_GATE BIT(30) 304 305 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 306 #define BSLIP_EN BIT(31) 307 #define EDGE_CHK BIT(30) 308 #define RD_TAP_MASK 0x7f 309 #define RD_TAP(x) ((x) & 0x7f) 310 311 #define MT7530_TRGMII_TXCTRL 0x7a40 312 #define TRAIN_TXEN BIT(31) 313 #define TXC_INV BIT(30) 314 #define TX_RST BIT(28) 315 316 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 317 #define TD_DM_DRVP(x) ((x) & 0xf) 318 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 319 320 #define MT7530_TRGMII_TCK_CTRL 0x7a78 321 #define TCK_TAP(x) (((x) & 0xf) << 8) 322 323 #define MT7530_P5RGMIIRXCR 0x7b00 324 #define CSR_RGMII_EDGE_ALIGN BIT(8) 325 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 326 327 #define MT7530_P5RGMIITXCR 0x7b04 328 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 329 330 #define MT7530_CREV 0x7ffc 331 #define CHIP_NAME_SHIFT 16 332 #define MT7530_ID 0x7530 333 334 /* Registers for core PLL access through mmd indirect */ 335 #define CORE_PLL_GROUP2 0x401 336 #define RG_SYSPLL_EN_NORMAL BIT(15) 337 #define RG_SYSPLL_VODEN BIT(14) 338 #define RG_SYSPLL_LF BIT(13) 339 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 340 #define RG_SYSPLL_LVROD_EN BIT(10) 341 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 342 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 343 #define RG_SYSPLL_FBKSEL BIT(4) 344 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 345 346 #define CORE_PLL_GROUP4 0x403 347 #define RG_SYSPLL_DDSFBK_EN BIT(12) 348 #define RG_SYSPLL_BIAS_EN BIT(11) 349 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 350 351 #define CORE_PLL_GROUP5 0x404 352 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 353 354 #define CORE_PLL_GROUP6 0x405 355 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 356 357 #define CORE_PLL_GROUP7 0x406 358 #define RG_LCDDS_PWDB BIT(15) 359 #define RG_LCDDS_ISO_EN BIT(13) 360 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 361 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 362 363 #define CORE_PLL_GROUP10 0x409 364 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 365 366 #define CORE_PLL_GROUP11 0x40a 367 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 368 369 #define CORE_GSWPLL_GRP1 0x40d 370 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 371 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 372 #define RG_GSWPLL_EN_PRE BIT(11) 373 #define RG_GSWPLL_FBKSEL BIT(10) 374 #define RG_GSWPLL_BP BIT(9) 375 #define RG_GSWPLL_BR BIT(8) 376 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 377 378 #define CORE_GSWPLL_GRP2 0x40e 379 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 380 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 381 382 #define CORE_TRGMII_GSW_CLK_CG 0x410 383 #define REG_GSWCK_EN BIT(0) 384 #define REG_TRGMIICK_EN BIT(1) 385 386 #define MIB_DESC(_s, _o, _n) \ 387 { \ 388 .size = (_s), \ 389 .offset = (_o), \ 390 .name = (_n), \ 391 } 392 393 struct mt7530_mib_desc { 394 unsigned int size; 395 unsigned int offset; 396 const char *name; 397 }; 398 399 struct mt7530_fdb { 400 u16 vid; 401 u8 port_mask; 402 u8 aging; 403 u8 mac[6]; 404 bool noarp; 405 }; 406 407 /* struct mt7530_port - This is the main data structure for holding the state 408 * of the port. 409 * @enable: The status used for show port is enabled or not. 410 * @pm: The matrix used to show all connections with the port. 411 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 412 * untagged frames will be assigned to the related VLAN. 413 * @vlan_filtering: The flags indicating whether the port that can recognize 414 * VLAN-tagged frames. 415 */ 416 struct mt7530_port { 417 bool enable; 418 u32 pm; 419 u16 pvid; 420 }; 421 422 /* Port 5 interface select definitions */ 423 enum p5_interface_select { 424 P5_DISABLED = 0, 425 P5_INTF_SEL_PHY_P0, 426 P5_INTF_SEL_PHY_P4, 427 P5_INTF_SEL_GMAC5, 428 }; 429 430 static const char *p5_intf_modes(unsigned int p5_interface) 431 { 432 switch (p5_interface) { 433 case P5_DISABLED: 434 return "DISABLED"; 435 case P5_INTF_SEL_PHY_P0: 436 return "PHY P0"; 437 case P5_INTF_SEL_PHY_P4: 438 return "PHY P4"; 439 case P5_INTF_SEL_GMAC5: 440 return "GMAC5"; 441 default: 442 return "unknown"; 443 } 444 } 445 446 /* struct mt7530_priv - This is the main data structure for holding the state 447 * of the driver 448 * @dev: The device pointer 449 * @ds: The pointer to the dsa core structure 450 * @bus: The bus used for the device and built-in PHY 451 * @rstc: The pointer to reset control used by MCM 452 * @core_pwr: The power supplied into the core 453 * @io_pwr: The power supplied into the I/O 454 * @reset: The descriptor for GPIO line tied to its reset pin 455 * @mcm: Flag for distinguishing if standalone IC or module 456 * coupling 457 * @ports: Holding the state among ports 458 * @reg_mutex: The lock for protecting among process accessing 459 * registers 460 * @p6_interface Holding the current port 6 interface 461 * @p5_intf_sel: Holding the current port 5 interface select 462 */ 463 struct mt7530_priv { 464 struct device *dev; 465 struct dsa_switch *ds; 466 struct mii_bus *bus; 467 struct reset_control *rstc; 468 struct regulator *core_pwr; 469 struct regulator *io_pwr; 470 struct gpio_desc *reset; 471 unsigned int id; 472 bool mcm; 473 phy_interface_t p6_interface; 474 phy_interface_t p5_interface; 475 unsigned int p5_intf_sel; 476 u8 mirror_rx; 477 u8 mirror_tx; 478 479 struct mt7530_port ports[MT7530_NUM_PORTS]; 480 /* protect among processes for registers access*/ 481 struct mutex reg_mutex; 482 }; 483 484 struct mt7530_hw_vlan_entry { 485 int port; 486 u8 old_members; 487 bool untagged; 488 }; 489 490 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 491 int port, bool untagged) 492 { 493 e->port = port; 494 e->untagged = untagged; 495 } 496 497 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 498 struct mt7530_hw_vlan_entry *); 499 500 struct mt7530_hw_stats { 501 const char *string; 502 u16 reg; 503 u8 sizeof_stat; 504 }; 505 506 struct mt7530_dummy_poll { 507 struct mt7530_priv *priv; 508 u32 reg; 509 }; 510 511 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 512 struct mt7530_priv *priv, u32 reg) 513 { 514 p->priv = priv; 515 p->reg = reg; 516 } 517 518 #endif /* __MT7530_H */ 519