1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 */ 5 6 #ifndef __MT7530_H 7 #define __MT7530_H 8 9 #define MT7530_NUM_PORTS 7 10 #define MT7530_NUM_PHYS 5 11 #define MT7530_NUM_FDB_RECORDS 2048 12 #define MT7530_ALL_MEMBERS 0xff 13 14 #define MTK_HDR_LEN 4 15 #define MT7530_MAX_MTU (15 * 1024 - ETH_HLEN - ETH_FCS_LEN - MTK_HDR_LEN) 16 17 enum mt753x_id { 18 ID_MT7530 = 0, 19 ID_MT7621 = 1, 20 ID_MT7531 = 2, 21 }; 22 23 #define NUM_TRGMII_CTRL 5 24 25 #define TRGMII_BASE(x) (0x10000 + (x)) 26 27 /* Registers to ethsys access */ 28 #define ETHSYS_CLKCFG0 0x2c 29 #define ETHSYS_TRGMII_CLK_SEL362_5 BIT(11) 30 31 #define SYSC_REG_RSTCTRL 0x34 32 #define RESET_MCM BIT(2) 33 34 /* Registers to mac forward control for unknown frames */ 35 #define MT7530_MFC 0x10 36 #define BC_FFP(x) (((x) & 0xff) << 24) 37 #define BC_FFP_MASK BC_FFP(~0) 38 #define UNM_FFP(x) (((x) & 0xff) << 16) 39 #define UNM_FFP_MASK UNM_FFP(~0) 40 #define UNU_FFP(x) (((x) & 0xff) << 8) 41 #define UNU_FFP_MASK UNU_FFP(~0) 42 #define CPU_EN BIT(7) 43 #define CPU_PORT(x) ((x) << 4) 44 #define CPU_MASK (0xf << 4) 45 #define MIRROR_EN BIT(3) 46 #define MIRROR_PORT(x) ((x) & 0x7) 47 #define MIRROR_MASK 0x7 48 49 /* Registers for CPU forward control */ 50 #define MT7531_CFC 0x4 51 #define MT7531_MIRROR_EN BIT(19) 52 #define MT7531_MIRROR_MASK (MIRROR_MASK << 16) 53 #define MT7531_MIRROR_PORT_GET(x) (((x) >> 16) & MIRROR_MASK) 54 #define MT7531_MIRROR_PORT_SET(x) (((x) & MIRROR_MASK) << 16) 55 #define MT7531_CPU_PMAP_MASK GENMASK(7, 0) 56 57 #define MT753X_MIRROR_REG(id) (((id) == ID_MT7531) ? \ 58 MT7531_CFC : MT7530_MFC) 59 #define MT753X_MIRROR_EN(id) (((id) == ID_MT7531) ? \ 60 MT7531_MIRROR_EN : MIRROR_EN) 61 #define MT753X_MIRROR_MASK(id) (((id) == ID_MT7531) ? \ 62 MT7531_MIRROR_MASK : MIRROR_MASK) 63 64 /* Registers for BPDU and PAE frame control*/ 65 #define MT753X_BPC 0x24 66 #define MT753X_BPDU_PORT_FW_MASK GENMASK(2, 0) 67 68 enum mt753x_bpdu_port_fw { 69 MT753X_BPDU_FOLLOW_MFC, 70 MT753X_BPDU_CPU_EXCLUDE = 4, 71 MT753X_BPDU_CPU_INCLUDE = 5, 72 MT753X_BPDU_CPU_ONLY = 6, 73 MT753X_BPDU_DROP = 7, 74 }; 75 76 /* Registers for address table access */ 77 #define MT7530_ATA1 0x74 78 #define STATIC_EMP 0 79 #define STATIC_ENT 3 80 #define MT7530_ATA2 0x78 81 #define ATA2_IVL BIT(15) 82 #define ATA2_FID(x) (((x) & 0x7) << 12) 83 84 /* Register for address table write data */ 85 #define MT7530_ATWD 0x7c 86 87 /* Register for address table control */ 88 #define MT7530_ATC 0x80 89 #define ATC_HASH (((x) & 0xfff) << 16) 90 #define ATC_BUSY BIT(15) 91 #define ATC_SRCH_END BIT(14) 92 #define ATC_SRCH_HIT BIT(13) 93 #define ATC_INVALID BIT(12) 94 #define ATC_MAT(x) (((x) & 0xf) << 8) 95 #define ATC_MAT_MACTAB ATC_MAT(0) 96 97 enum mt7530_fdb_cmd { 98 MT7530_FDB_READ = 0, 99 MT7530_FDB_WRITE = 1, 100 MT7530_FDB_FLUSH = 2, 101 MT7530_FDB_START = 4, 102 MT7530_FDB_NEXT = 5, 103 }; 104 105 /* Registers for table search read address */ 106 #define MT7530_TSRA1 0x84 107 #define MAC_BYTE_0 24 108 #define MAC_BYTE_1 16 109 #define MAC_BYTE_2 8 110 #define MAC_BYTE_3 0 111 #define MAC_BYTE_MASK 0xff 112 113 #define MT7530_TSRA2 0x88 114 #define MAC_BYTE_4 24 115 #define MAC_BYTE_5 16 116 #define CVID 0 117 #define CVID_MASK 0xfff 118 119 #define MT7530_ATRD 0x8C 120 #define AGE_TIMER 24 121 #define AGE_TIMER_MASK 0xff 122 #define PORT_MAP 4 123 #define PORT_MAP_MASK 0xff 124 #define ENT_STATUS 2 125 #define ENT_STATUS_MASK 0x3 126 127 /* Register for vlan table control */ 128 #define MT7530_VTCR 0x90 129 #define VTCR_BUSY BIT(31) 130 #define VTCR_INVALID BIT(16) 131 #define VTCR_FUNC(x) (((x) & 0xf) << 12) 132 #define VTCR_VID ((x) & 0xfff) 133 134 enum mt7530_vlan_cmd { 135 /* Read/Write the specified VID entry from VAWD register based 136 * on VID. 137 */ 138 MT7530_VTCR_RD_VID = 0, 139 MT7530_VTCR_WR_VID = 1, 140 }; 141 142 /* Register for setup vlan and acl write data */ 143 #define MT7530_VAWD1 0x94 144 #define PORT_STAG BIT(31) 145 /* Independent VLAN Learning */ 146 #define IVL_MAC BIT(30) 147 /* Egress Tag Consistent */ 148 #define EG_CON BIT(29) 149 /* Per VLAN Egress Tag Control */ 150 #define VTAG_EN BIT(28) 151 /* VLAN Member Control */ 152 #define PORT_MEM(x) (((x) & 0xff) << 16) 153 /* Filter ID */ 154 #define FID(x) (((x) & 0x7) << 1) 155 /* VLAN Entry Valid */ 156 #define VLAN_VALID BIT(0) 157 #define PORT_MEM_SHFT 16 158 #define PORT_MEM_MASK 0xff 159 160 enum mt7530_fid { 161 FID_STANDALONE = 0, 162 FID_BRIDGED = 1, 163 }; 164 165 #define MT7530_VAWD2 0x98 166 /* Egress Tag Control */ 167 #define ETAG_CTRL_P(p, x) (((x) & 0x3) << ((p) << 1)) 168 #define ETAG_CTRL_P_MASK(p) ETAG_CTRL_P(p, 3) 169 170 enum mt7530_vlan_egress_attr { 171 MT7530_VLAN_EGRESS_UNTAG = 0, 172 MT7530_VLAN_EGRESS_TAG = 2, 173 MT7530_VLAN_EGRESS_STACK = 3, 174 }; 175 176 /* Register for address age control */ 177 #define MT7530_AAC 0xa0 178 /* Disable ageing */ 179 #define AGE_DIS BIT(20) 180 /* Age count */ 181 #define AGE_CNT_MASK GENMASK(19, 12) 182 #define AGE_CNT_MAX 0xff 183 #define AGE_CNT(x) (AGE_CNT_MASK & ((x) << 12)) 184 /* Age unit */ 185 #define AGE_UNIT_MASK GENMASK(11, 0) 186 #define AGE_UNIT_MAX 0xfff 187 #define AGE_UNIT(x) (AGE_UNIT_MASK & (x)) 188 189 /* Register for port STP state control */ 190 #define MT7530_SSP_P(x) (0x2000 + ((x) * 0x100)) 191 #define FID_PST(fid, state) (((state) & 0x3) << ((fid) * 2)) 192 #define FID_PST_MASK(fid) FID_PST(fid, 0x3) 193 194 enum mt7530_stp_state { 195 MT7530_STP_DISABLED = 0, 196 MT7530_STP_BLOCKING = 1, 197 MT7530_STP_LISTENING = 1, 198 MT7530_STP_LEARNING = 2, 199 MT7530_STP_FORWARDING = 3 200 }; 201 202 /* Register for port control */ 203 #define MT7530_PCR_P(x) (0x2004 + ((x) * 0x100)) 204 #define PORT_TX_MIR BIT(9) 205 #define PORT_RX_MIR BIT(8) 206 #define PORT_VLAN(x) ((x) & 0x3) 207 208 enum mt7530_port_mode { 209 /* Port Matrix Mode: Frames are forwarded by the PCR_MATRIX members. */ 210 MT7530_PORT_MATRIX_MODE = PORT_VLAN(0), 211 212 /* Fallback Mode: Forward received frames with ingress ports that do 213 * not belong to the VLAN member. Frames whose VID is not listed on 214 * the VLAN table are forwarded by the PCR_MATRIX members. 215 */ 216 MT7530_PORT_FALLBACK_MODE = PORT_VLAN(1), 217 218 /* Security Mode: Discard any frame due to ingress membership 219 * violation or VID missed on the VLAN table. 220 */ 221 MT7530_PORT_SECURITY_MODE = PORT_VLAN(3), 222 }; 223 224 #define PCR_MATRIX(x) (((x) & 0xff) << 16) 225 #define PORT_PRI(x) (((x) & 0x7) << 24) 226 #define EG_TAG(x) (((x) & 0x3) << 28) 227 #define PCR_MATRIX_MASK PCR_MATRIX(0xff) 228 #define PCR_MATRIX_CLR PCR_MATRIX(0) 229 #define PCR_PORT_VLAN_MASK PORT_VLAN(3) 230 231 /* Register for port security control */ 232 #define MT7530_PSC_P(x) (0x200c + ((x) * 0x100)) 233 #define SA_DIS BIT(4) 234 235 /* Register for port vlan control */ 236 #define MT7530_PVC_P(x) (0x2010 + ((x) * 0x100)) 237 #define PORT_SPEC_TAG BIT(5) 238 #define PVC_EG_TAG(x) (((x) & 0x7) << 8) 239 #define PVC_EG_TAG_MASK PVC_EG_TAG(7) 240 #define VLAN_ATTR(x) (((x) & 0x3) << 6) 241 #define VLAN_ATTR_MASK VLAN_ATTR(3) 242 #define ACC_FRM_MASK GENMASK(1, 0) 243 244 enum mt7530_vlan_port_eg_tag { 245 MT7530_VLAN_EG_DISABLED = 0, 246 MT7530_VLAN_EG_CONSISTENT = 1, 247 }; 248 249 enum mt7530_vlan_port_attr { 250 MT7530_VLAN_USER = 0, 251 MT7530_VLAN_TRANSPARENT = 3, 252 }; 253 254 enum mt7530_vlan_port_acc_frm { 255 MT7530_VLAN_ACC_ALL = 0, 256 MT7530_VLAN_ACC_TAGGED = 1, 257 MT7530_VLAN_ACC_UNTAGGED = 2, 258 }; 259 260 #define STAG_VPID (((x) & 0xffff) << 16) 261 262 /* Register for port port-and-protocol based vlan 1 control */ 263 #define MT7530_PPBV1_P(x) (0x2014 + ((x) * 0x100)) 264 #define G0_PORT_VID(x) (((x) & 0xfff) << 0) 265 #define G0_PORT_VID_MASK G0_PORT_VID(0xfff) 266 #define G0_PORT_VID_DEF G0_PORT_VID(0) 267 268 /* Register for port MAC control register */ 269 #define MT7530_PMCR_P(x) (0x3000 + ((x) * 0x100)) 270 #define PMCR_IFG_XMIT(x) (((x) & 0x3) << 18) 271 #define PMCR_EXT_PHY BIT(17) 272 #define PMCR_MAC_MODE BIT(16) 273 #define PMCR_FORCE_MODE BIT(15) 274 #define PMCR_TX_EN BIT(14) 275 #define PMCR_RX_EN BIT(13) 276 #define PMCR_BACKOFF_EN BIT(9) 277 #define PMCR_BACKPR_EN BIT(8) 278 #define PMCR_FORCE_EEE1G BIT(7) 279 #define PMCR_FORCE_EEE100 BIT(6) 280 #define PMCR_TX_FC_EN BIT(5) 281 #define PMCR_RX_FC_EN BIT(4) 282 #define PMCR_FORCE_SPEED_1000 BIT(3) 283 #define PMCR_FORCE_SPEED_100 BIT(2) 284 #define PMCR_FORCE_FDX BIT(1) 285 #define PMCR_FORCE_LNK BIT(0) 286 #define PMCR_SPEED_MASK (PMCR_FORCE_SPEED_100 | \ 287 PMCR_FORCE_SPEED_1000) 288 #define MT7531_FORCE_LNK BIT(31) 289 #define MT7531_FORCE_SPD BIT(30) 290 #define MT7531_FORCE_DPX BIT(29) 291 #define MT7531_FORCE_RX_FC BIT(28) 292 #define MT7531_FORCE_TX_FC BIT(27) 293 #define MT7531_FORCE_MODE (MT7531_FORCE_LNK | \ 294 MT7531_FORCE_SPD | \ 295 MT7531_FORCE_DPX | \ 296 MT7531_FORCE_RX_FC | \ 297 MT7531_FORCE_TX_FC) 298 #define PMCR_FORCE_MODE_ID(id) (((id) == ID_MT7531) ? \ 299 MT7531_FORCE_MODE : \ 300 PMCR_FORCE_MODE) 301 #define PMCR_LINK_SETTINGS_MASK (PMCR_TX_EN | PMCR_FORCE_SPEED_1000 | \ 302 PMCR_RX_EN | PMCR_FORCE_SPEED_100 | \ 303 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 304 PMCR_FORCE_FDX | PMCR_FORCE_LNK | \ 305 PMCR_FORCE_EEE1G | PMCR_FORCE_EEE100) 306 #define PMCR_CPU_PORT_SETTING(id) (PMCR_FORCE_MODE_ID((id)) | \ 307 PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | \ 308 PMCR_BACKOFF_EN | PMCR_BACKPR_EN | \ 309 PMCR_TX_EN | PMCR_RX_EN | \ 310 PMCR_TX_FC_EN | PMCR_RX_FC_EN | \ 311 PMCR_FORCE_SPEED_1000 | \ 312 PMCR_FORCE_FDX | PMCR_FORCE_LNK) 313 314 #define MT7530_PMEEECR_P(x) (0x3004 + (x) * 0x100) 315 #define WAKEUP_TIME_1000(x) (((x) & 0xFF) << 24) 316 #define WAKEUP_TIME_100(x) (((x) & 0xFF) << 16) 317 #define LPI_THRESH_MASK GENMASK(15, 4) 318 #define LPI_THRESH_SHT 4 319 #define SET_LPI_THRESH(x) (((x) << LPI_THRESH_SHT) & LPI_THRESH_MASK) 320 #define GET_LPI_THRESH(x) (((x) & LPI_THRESH_MASK) >> LPI_THRESH_SHT) 321 #define LPI_MODE_EN BIT(0) 322 323 #define MT7530_PMSR_P(x) (0x3008 + (x) * 0x100) 324 #define PMSR_EEE1G BIT(7) 325 #define PMSR_EEE100M BIT(6) 326 #define PMSR_RX_FC BIT(5) 327 #define PMSR_TX_FC BIT(4) 328 #define PMSR_SPEED_1000 BIT(3) 329 #define PMSR_SPEED_100 BIT(2) 330 #define PMSR_SPEED_10 0x00 331 #define PMSR_SPEED_MASK (PMSR_SPEED_100 | PMSR_SPEED_1000) 332 #define PMSR_DPX BIT(1) 333 #define PMSR_LINK BIT(0) 334 335 /* Register for port debug count */ 336 #define MT7531_DBG_CNT(x) (0x3018 + (x) * 0x100) 337 #define MT7531_DIS_CLR BIT(31) 338 339 #define MT7530_GMACCR 0x30e0 340 #define MAX_RX_JUMBO(x) ((x) << 2) 341 #define MAX_RX_JUMBO_MASK GENMASK(5, 2) 342 #define MAX_RX_PKT_LEN_MASK GENMASK(1, 0) 343 #define MAX_RX_PKT_LEN_1522 0x0 344 #define MAX_RX_PKT_LEN_1536 0x1 345 #define MAX_RX_PKT_LEN_1552 0x2 346 #define MAX_RX_PKT_LEN_JUMBO 0x3 347 348 /* Register for MIB */ 349 #define MT7530_PORT_MIB_COUNTER(x) (0x4000 + (x) * 0x100) 350 #define MT7530_MIB_CCR 0x4fe0 351 #define CCR_MIB_ENABLE BIT(31) 352 #define CCR_RX_OCT_CNT_GOOD BIT(7) 353 #define CCR_RX_OCT_CNT_BAD BIT(6) 354 #define CCR_TX_OCT_CNT_GOOD BIT(5) 355 #define CCR_TX_OCT_CNT_BAD BIT(4) 356 #define CCR_MIB_FLUSH (CCR_RX_OCT_CNT_GOOD | \ 357 CCR_RX_OCT_CNT_BAD | \ 358 CCR_TX_OCT_CNT_GOOD | \ 359 CCR_TX_OCT_CNT_BAD) 360 #define CCR_MIB_ACTIVATE (CCR_MIB_ENABLE | \ 361 CCR_RX_OCT_CNT_GOOD | \ 362 CCR_RX_OCT_CNT_BAD | \ 363 CCR_TX_OCT_CNT_GOOD | \ 364 CCR_TX_OCT_CNT_BAD) 365 366 /* MT7531 SGMII register group */ 367 #define MT7531_SGMII_REG_BASE 0x5000 368 #define MT7531_SGMII_REG(p, r) (MT7531_SGMII_REG_BASE + \ 369 ((p) - 5) * 0x1000 + (r)) 370 371 /* Register forSGMII PCS_CONTROL_1 */ 372 #define MT7531_PCS_CONTROL_1(p) MT7531_SGMII_REG(p, 0x00) 373 #define MT7531_SGMII_LINK_STATUS BIT(18) 374 #define MT7531_SGMII_AN_ENABLE BIT(12) 375 #define MT7531_SGMII_AN_RESTART BIT(9) 376 #define MT7531_SGMII_AN_COMPLETE BIT(21) 377 378 /* Register for SGMII PCS_SPPED_ABILITY */ 379 #define MT7531_PCS_SPEED_ABILITY(p) MT7531_SGMII_REG(p, 0x08) 380 #define MT7531_SGMII_TX_CONFIG_MASK GENMASK(15, 0) 381 #define MT7531_SGMII_TX_CONFIG BIT(0) 382 383 /* Register for SGMII_MODE */ 384 #define MT7531_SGMII_MODE(p) MT7531_SGMII_REG(p, 0x20) 385 #define MT7531_SGMII_REMOTE_FAULT_DIS BIT(8) 386 #define MT7531_SGMII_IF_MODE_MASK GENMASK(5, 1) 387 #define MT7531_SGMII_FORCE_DUPLEX BIT(4) 388 #define MT7531_SGMII_FORCE_SPEED_MASK GENMASK(3, 2) 389 #define MT7531_SGMII_FORCE_SPEED_1000 BIT(3) 390 #define MT7531_SGMII_FORCE_SPEED_100 BIT(2) 391 #define MT7531_SGMII_FORCE_SPEED_10 0 392 #define MT7531_SGMII_SPEED_DUPLEX_AN BIT(1) 393 394 enum mt7531_sgmii_force_duplex { 395 MT7531_SGMII_FORCE_FULL_DUPLEX = 0, 396 MT7531_SGMII_FORCE_HALF_DUPLEX = 0x10, 397 }; 398 399 /* Fields of QPHY_PWR_STATE_CTRL */ 400 #define MT7531_QPHY_PWR_STATE_CTRL(p) MT7531_SGMII_REG(p, 0xe8) 401 #define MT7531_SGMII_PHYA_PWD BIT(4) 402 403 /* Values of SGMII SPEED */ 404 #define MT7531_PHYA_CTRL_SIGNAL3(p) MT7531_SGMII_REG(p, 0x128) 405 #define MT7531_RG_TPHY_SPEED_MASK (BIT(2) | BIT(3)) 406 #define MT7531_RG_TPHY_SPEED_1_25G 0x0 407 #define MT7531_RG_TPHY_SPEED_3_125G BIT(2) 408 409 /* Register for system reset */ 410 #define MT7530_SYS_CTRL 0x7000 411 #define SYS_CTRL_PHY_RST BIT(2) 412 #define SYS_CTRL_SW_RST BIT(1) 413 #define SYS_CTRL_REG_RST BIT(0) 414 415 /* Register for system interrupt */ 416 #define MT7530_SYS_INT_EN 0x7008 417 418 /* Register for system interrupt status */ 419 #define MT7530_SYS_INT_STS 0x700c 420 421 /* Register for PHY Indirect Access Control */ 422 #define MT7531_PHY_IAC 0x701C 423 #define MT7531_PHY_ACS_ST BIT(31) 424 #define MT7531_MDIO_REG_ADDR_MASK (0x1f << 25) 425 #define MT7531_MDIO_PHY_ADDR_MASK (0x1f << 20) 426 #define MT7531_MDIO_CMD_MASK (0x3 << 18) 427 #define MT7531_MDIO_ST_MASK (0x3 << 16) 428 #define MT7531_MDIO_RW_DATA_MASK (0xffff) 429 #define MT7531_MDIO_REG_ADDR(x) (((x) & 0x1f) << 25) 430 #define MT7531_MDIO_DEV_ADDR(x) (((x) & 0x1f) << 25) 431 #define MT7531_MDIO_PHY_ADDR(x) (((x) & 0x1f) << 20) 432 #define MT7531_MDIO_CMD(x) (((x) & 0x3) << 18) 433 #define MT7531_MDIO_ST(x) (((x) & 0x3) << 16) 434 435 enum mt7531_phy_iac_cmd { 436 MT7531_MDIO_ADDR = 0, 437 MT7531_MDIO_WRITE = 1, 438 MT7531_MDIO_READ = 2, 439 MT7531_MDIO_READ_CL45 = 3, 440 }; 441 442 /* MDIO_ST: MDIO start field */ 443 enum mt7531_mdio_st { 444 MT7531_MDIO_ST_CL45 = 0, 445 MT7531_MDIO_ST_CL22 = 1, 446 }; 447 448 #define MT7531_MDIO_CL22_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 449 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 450 #define MT7531_MDIO_CL22_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL22) | \ 451 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 452 #define MT7531_MDIO_CL45_ADDR (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 453 MT7531_MDIO_CMD(MT7531_MDIO_ADDR)) 454 #define MT7531_MDIO_CL45_READ (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 455 MT7531_MDIO_CMD(MT7531_MDIO_READ)) 456 #define MT7531_MDIO_CL45_WRITE (MT7531_MDIO_ST(MT7531_MDIO_ST_CL45) | \ 457 MT7531_MDIO_CMD(MT7531_MDIO_WRITE)) 458 459 /* Register for RGMII clock phase */ 460 #define MT7531_CLKGEN_CTRL 0x7500 461 #define CLK_SKEW_OUT(x) (((x) & 0x3) << 8) 462 #define CLK_SKEW_OUT_MASK GENMASK(9, 8) 463 #define CLK_SKEW_IN(x) (((x) & 0x3) << 6) 464 #define CLK_SKEW_IN_MASK GENMASK(7, 6) 465 #define RXCLK_NO_DELAY BIT(5) 466 #define TXCLK_NO_REVERSE BIT(4) 467 #define GP_MODE(x) (((x) & 0x3) << 1) 468 #define GP_MODE_MASK GENMASK(2, 1) 469 #define GP_CLK_EN BIT(0) 470 471 enum mt7531_gp_mode { 472 MT7531_GP_MODE_RGMII = 0, 473 MT7531_GP_MODE_MII = 1, 474 MT7531_GP_MODE_REV_MII = 2 475 }; 476 477 enum mt7531_clk_skew { 478 MT7531_CLK_SKEW_NO_CHG = 0, 479 MT7531_CLK_SKEW_DLY_100PPS = 1, 480 MT7531_CLK_SKEW_DLY_200PPS = 2, 481 MT7531_CLK_SKEW_REVERSE = 3, 482 }; 483 484 /* Register for hw trap status */ 485 #define MT7530_HWTRAP 0x7800 486 #define HWTRAP_XTAL_MASK (BIT(10) | BIT(9)) 487 #define HWTRAP_XTAL_25MHZ (BIT(10) | BIT(9)) 488 #define HWTRAP_XTAL_40MHZ (BIT(10)) 489 #define HWTRAP_XTAL_20MHZ (BIT(9)) 490 491 #define MT7531_HWTRAP 0x7800 492 #define HWTRAP_XTAL_FSEL_MASK BIT(7) 493 #define HWTRAP_XTAL_FSEL_25MHZ BIT(7) 494 #define HWTRAP_XTAL_FSEL_40MHZ 0 495 /* Unique fields of (M)HWSTRAP for MT7531 */ 496 #define XTAL_FSEL_S 7 497 #define XTAL_FSEL_M BIT(7) 498 #define PHY_EN BIT(6) 499 #define CHG_STRAP BIT(8) 500 501 /* Register for hw trap modification */ 502 #define MT7530_MHWTRAP 0x7804 503 #define MHWTRAP_PHY0_SEL BIT(20) 504 #define MHWTRAP_MANUAL BIT(16) 505 #define MHWTRAP_P5_MAC_SEL BIT(13) 506 #define MHWTRAP_P6_DIS BIT(8) 507 #define MHWTRAP_P5_RGMII_MODE BIT(7) 508 #define MHWTRAP_P5_DIS BIT(6) 509 #define MHWTRAP_PHY_ACCESS BIT(5) 510 511 /* Register for TOP signal control */ 512 #define MT7530_TOP_SIG_CTRL 0x7808 513 #define TOP_SIG_CTRL_NORMAL (BIT(17) | BIT(16)) 514 515 #define MT7531_TOP_SIG_SR 0x780c 516 #define PAD_DUAL_SGMII_EN BIT(1) 517 #define PAD_MCM_SMI_EN BIT(0) 518 519 #define MT7530_IO_DRV_CR 0x7810 520 #define P5_IO_CLK_DRV(x) ((x) & 0x3) 521 #define P5_IO_DATA_DRV(x) (((x) & 0x3) << 4) 522 523 #define MT7531_CHIP_REV 0x781C 524 525 #define MT7531_PLLGP_EN 0x7820 526 #define EN_COREPLL BIT(2) 527 #define SW_CLKSW BIT(1) 528 #define SW_PLLGP BIT(0) 529 530 #define MT7530_P6ECR 0x7830 531 #define P6_INTF_MODE_MASK 0x3 532 #define P6_INTF_MODE(x) ((x) & 0x3) 533 534 #define MT7531_PLLGP_CR0 0x78a8 535 #define RG_COREPLL_EN BIT(22) 536 #define RG_COREPLL_POSDIV_S 23 537 #define RG_COREPLL_POSDIV_M 0x3800000 538 #define RG_COREPLL_SDM_PCW_S 1 539 #define RG_COREPLL_SDM_PCW_M 0x3ffffe 540 #define RG_COREPLL_SDM_PCW_CHG BIT(0) 541 542 /* Registers for RGMII and SGMII PLL clock */ 543 #define MT7531_ANA_PLLGP_CR2 0x78b0 544 #define MT7531_ANA_PLLGP_CR5 0x78bc 545 546 /* Registers for TRGMII on the both side */ 547 #define MT7530_TRGMII_RCK_CTRL 0x7a00 548 #define RX_RST BIT(31) 549 #define RXC_DQSISEL BIT(30) 550 #define DQSI1_TAP_MASK (0x7f << 8) 551 #define DQSI0_TAP_MASK 0x7f 552 #define DQSI1_TAP(x) (((x) & 0x7f) << 8) 553 #define DQSI0_TAP(x) ((x) & 0x7f) 554 555 #define MT7530_TRGMII_RCK_RTT 0x7a04 556 #define DQS1_GATE BIT(31) 557 #define DQS0_GATE BIT(30) 558 559 #define MT7530_TRGMII_RD(x) (0x7a10 + (x) * 8) 560 #define BSLIP_EN BIT(31) 561 #define EDGE_CHK BIT(30) 562 #define RD_TAP_MASK 0x7f 563 #define RD_TAP(x) ((x) & 0x7f) 564 565 #define MT7530_TRGMII_TXCTRL 0x7a40 566 #define TRAIN_TXEN BIT(31) 567 #define TXC_INV BIT(30) 568 #define TX_RST BIT(28) 569 570 #define MT7530_TRGMII_TD_ODT(i) (0x7a54 + 8 * (i)) 571 #define TD_DM_DRVP(x) ((x) & 0xf) 572 #define TD_DM_DRVN(x) (((x) & 0xf) << 4) 573 574 #define MT7530_TRGMII_TCK_CTRL 0x7a78 575 #define TCK_TAP(x) (((x) & 0xf) << 8) 576 577 #define MT7530_P5RGMIIRXCR 0x7b00 578 #define CSR_RGMII_EDGE_ALIGN BIT(8) 579 #define CSR_RGMII_RXC_0DEG_CFG(x) ((x) & 0xf) 580 581 #define MT7530_P5RGMIITXCR 0x7b04 582 #define CSR_RGMII_TXC_CFG(x) ((x) & 0x1f) 583 584 /* Registers for GPIO mode */ 585 #define MT7531_GPIO_MODE0 0x7c0c 586 #define MT7531_GPIO0_MASK GENMASK(3, 0) 587 #define MT7531_GPIO0_INTERRUPT 1 588 589 #define MT7531_GPIO_MODE1 0x7c10 590 #define MT7531_GPIO11_RG_RXD2_MASK GENMASK(15, 12) 591 #define MT7531_EXT_P_MDC_11 (2 << 12) 592 #define MT7531_GPIO12_RG_RXD3_MASK GENMASK(19, 16) 593 #define MT7531_EXT_P_MDIO_12 (2 << 16) 594 595 /* Registers for LED GPIO control (MT7530 only) 596 * All registers follow this pattern: 597 * [ 2: 0] port 0 598 * [ 6: 4] port 1 599 * [10: 8] port 2 600 * [14:12] port 3 601 * [18:16] port 4 602 */ 603 604 /* LED enable, 0: Disable, 1: Enable (Default) */ 605 #define MT7530_LED_EN 0x7d00 606 /* LED mode, 0: GPIO mode, 1: PHY mode (Default) */ 607 #define MT7530_LED_IO_MODE 0x7d04 608 /* GPIO direction, 0: Input, 1: Output */ 609 #define MT7530_LED_GPIO_DIR 0x7d10 610 /* GPIO output enable, 0: Disable, 1: Enable */ 611 #define MT7530_LED_GPIO_OE 0x7d14 612 /* GPIO value, 0: Low, 1: High */ 613 #define MT7530_LED_GPIO_DATA 0x7d18 614 615 #define MT7530_CREV 0x7ffc 616 #define CHIP_NAME_SHIFT 16 617 #define MT7530_ID 0x7530 618 619 #define MT7531_CREV 0x781C 620 #define CHIP_REV_M 0x0f 621 #define MT7531_ID 0x7531 622 623 /* Registers for core PLL access through mmd indirect */ 624 #define CORE_PLL_GROUP2 0x401 625 #define RG_SYSPLL_EN_NORMAL BIT(15) 626 #define RG_SYSPLL_VODEN BIT(14) 627 #define RG_SYSPLL_LF BIT(13) 628 #define RG_SYSPLL_RST_DLY(x) (((x) & 0x3) << 12) 629 #define RG_SYSPLL_LVROD_EN BIT(10) 630 #define RG_SYSPLL_PREDIV(x) (((x) & 0x3) << 8) 631 #define RG_SYSPLL_POSDIV(x) (((x) & 0x3) << 5) 632 #define RG_SYSPLL_FBKSEL BIT(4) 633 #define RT_SYSPLL_EN_AFE_OLT BIT(0) 634 635 #define CORE_PLL_GROUP4 0x403 636 #define RG_SYSPLL_DDSFBK_EN BIT(12) 637 #define RG_SYSPLL_BIAS_EN BIT(11) 638 #define RG_SYSPLL_BIAS_LPF_EN BIT(10) 639 #define MT7531_PHY_PLL_OFF BIT(5) 640 #define MT7531_PHY_PLL_BYPASS_MODE BIT(4) 641 642 #define MT753X_CTRL_PHY_ADDR 0 643 644 #define CORE_PLL_GROUP5 0x404 645 #define RG_LCDDS_PCW_NCPO1(x) ((x) & 0xffff) 646 647 #define CORE_PLL_GROUP6 0x405 648 #define RG_LCDDS_PCW_NCPO0(x) ((x) & 0xffff) 649 650 #define CORE_PLL_GROUP7 0x406 651 #define RG_LCDDS_PWDB BIT(15) 652 #define RG_LCDDS_ISO_EN BIT(13) 653 #define RG_LCCDS_C(x) (((x) & 0x7) << 4) 654 #define RG_LCDDS_PCW_NCPO_CHG BIT(3) 655 656 #define CORE_PLL_GROUP10 0x409 657 #define RG_LCDDS_SSC_DELTA(x) ((x) & 0xfff) 658 659 #define CORE_PLL_GROUP11 0x40a 660 #define RG_LCDDS_SSC_DELTA1(x) ((x) & 0xfff) 661 662 #define CORE_GSWPLL_GRP1 0x40d 663 #define RG_GSWPLL_PREDIV(x) (((x) & 0x3) << 14) 664 #define RG_GSWPLL_POSDIV_200M(x) (((x) & 0x3) << 12) 665 #define RG_GSWPLL_EN_PRE BIT(11) 666 #define RG_GSWPLL_FBKSEL BIT(10) 667 #define RG_GSWPLL_BP BIT(9) 668 #define RG_GSWPLL_BR BIT(8) 669 #define RG_GSWPLL_FBKDIV_200M(x) ((x) & 0xff) 670 671 #define CORE_GSWPLL_GRP2 0x40e 672 #define RG_GSWPLL_POSDIV_500M(x) (((x) & 0x3) << 8) 673 #define RG_GSWPLL_FBKDIV_500M(x) ((x) & 0xff) 674 675 #define CORE_TRGMII_GSW_CLK_CG 0x410 676 #define REG_GSWCK_EN BIT(0) 677 #define REG_TRGMIICK_EN BIT(1) 678 679 #define MIB_DESC(_s, _o, _n) \ 680 { \ 681 .size = (_s), \ 682 .offset = (_o), \ 683 .name = (_n), \ 684 } 685 686 struct mt7530_mib_desc { 687 unsigned int size; 688 unsigned int offset; 689 const char *name; 690 }; 691 692 struct mt7530_fdb { 693 u16 vid; 694 u8 port_mask; 695 u8 aging; 696 u8 mac[6]; 697 bool noarp; 698 }; 699 700 /* struct mt7530_port - This is the main data structure for holding the state 701 * of the port. 702 * @enable: The status used for show port is enabled or not. 703 * @pm: The matrix used to show all connections with the port. 704 * @pvid: The VLAN specified is to be considered a PVID at ingress. Any 705 * untagged frames will be assigned to the related VLAN. 706 * @vlan_filtering: The flags indicating whether the port that can recognize 707 * VLAN-tagged frames. 708 */ 709 struct mt7530_port { 710 bool enable; 711 u32 pm; 712 u16 pvid; 713 }; 714 715 /* Port 5 interface select definitions */ 716 enum p5_interface_select { 717 P5_DISABLED = 0, 718 P5_INTF_SEL_PHY_P0, 719 P5_INTF_SEL_PHY_P4, 720 P5_INTF_SEL_GMAC5, 721 P5_INTF_SEL_GMAC5_SGMII, 722 }; 723 724 static const char *p5_intf_modes(unsigned int p5_interface) 725 { 726 switch (p5_interface) { 727 case P5_DISABLED: 728 return "DISABLED"; 729 case P5_INTF_SEL_PHY_P0: 730 return "PHY P0"; 731 case P5_INTF_SEL_PHY_P4: 732 return "PHY P4"; 733 case P5_INTF_SEL_GMAC5: 734 return "GMAC5"; 735 case P5_INTF_SEL_GMAC5_SGMII: 736 return "GMAC5_SGMII"; 737 default: 738 return "unknown"; 739 } 740 } 741 742 struct mt7530_priv; 743 744 struct mt753x_pcs { 745 struct phylink_pcs pcs; 746 struct mt7530_priv *priv; 747 int port; 748 }; 749 750 /* struct mt753x_info - This is the main data structure for holding the specific 751 * part for each supported device 752 * @sw_setup: Holding the handler to a device initialization 753 * @phy_read_c22: Holding the way reading PHY port using C22 754 * @phy_write_c22: Holding the way writing PHY port using C22 755 * @phy_read_c45: Holding the way reading PHY port using C45 756 * @phy_write_c45: Holding the way writing PHY port using C45 757 * @pad_setup: Holding the way setting up the bus pad for a certain 758 * MAC port 759 * @phy_mode_supported: Check if the PHY type is being supported on a certain 760 * port 761 * @mac_port_validate: Holding the way to set addition validate type for a 762 * certan MAC port 763 * @mac_port_config: Holding the way setting up the PHY attribute to a 764 * certain MAC port 765 */ 766 struct mt753x_info { 767 enum mt753x_id id; 768 769 const struct phylink_pcs_ops *pcs_ops; 770 771 int (*sw_setup)(struct dsa_switch *ds); 772 int (*phy_read_c22)(struct mt7530_priv *priv, int port, int regnum); 773 int (*phy_write_c22)(struct mt7530_priv *priv, int port, int regnum, 774 u16 val); 775 int (*phy_read_c45)(struct mt7530_priv *priv, int port, int devad, 776 int regnum); 777 int (*phy_write_c45)(struct mt7530_priv *priv, int port, int devad, 778 int regnum, u16 val); 779 int (*pad_setup)(struct dsa_switch *ds, phy_interface_t interface); 780 int (*cpu_port_config)(struct dsa_switch *ds, int port); 781 void (*mac_port_get_caps)(struct dsa_switch *ds, int port, 782 struct phylink_config *config); 783 void (*mac_port_validate)(struct dsa_switch *ds, int port, 784 phy_interface_t interface, 785 unsigned long *supported); 786 int (*mac_port_config)(struct dsa_switch *ds, int port, 787 unsigned int mode, 788 phy_interface_t interface); 789 }; 790 791 /* struct mt7530_priv - This is the main data structure for holding the state 792 * of the driver 793 * @dev: The device pointer 794 * @ds: The pointer to the dsa core structure 795 * @bus: The bus used for the device and built-in PHY 796 * @rstc: The pointer to reset control used by MCM 797 * @core_pwr: The power supplied into the core 798 * @io_pwr: The power supplied into the I/O 799 * @reset: The descriptor for GPIO line tied to its reset pin 800 * @mcm: Flag for distinguishing if standalone IC or module 801 * coupling 802 * @ports: Holding the state among ports 803 * @reg_mutex: The lock for protecting among process accessing 804 * registers 805 * @p6_interface Holding the current port 6 interface 806 * @p5_intf_sel: Holding the current port 5 interface select 807 * 808 * @irq: IRQ number of the switch 809 * @irq_domain: IRQ domain of the switch irq_chip 810 * @irq_enable: IRQ enable bits, synced to SYS_INT_EN 811 */ 812 struct mt7530_priv { 813 struct device *dev; 814 struct dsa_switch *ds; 815 struct mii_bus *bus; 816 struct reset_control *rstc; 817 struct regulator *core_pwr; 818 struct regulator *io_pwr; 819 struct gpio_desc *reset; 820 const struct mt753x_info *info; 821 unsigned int id; 822 bool mcm; 823 phy_interface_t p6_interface; 824 phy_interface_t p5_interface; 825 unsigned int p5_intf_sel; 826 u8 mirror_rx; 827 u8 mirror_tx; 828 829 struct mt7530_port ports[MT7530_NUM_PORTS]; 830 struct mt753x_pcs pcs[MT7530_NUM_PORTS]; 831 /* protect among processes for registers access*/ 832 struct mutex reg_mutex; 833 int irq; 834 struct irq_domain *irq_domain; 835 u32 irq_enable; 836 }; 837 838 struct mt7530_hw_vlan_entry { 839 int port; 840 u8 old_members; 841 bool untagged; 842 }; 843 844 static inline void mt7530_hw_vlan_entry_init(struct mt7530_hw_vlan_entry *e, 845 int port, bool untagged) 846 { 847 e->port = port; 848 e->untagged = untagged; 849 } 850 851 typedef void (*mt7530_vlan_op)(struct mt7530_priv *, 852 struct mt7530_hw_vlan_entry *); 853 854 struct mt7530_hw_stats { 855 const char *string; 856 u16 reg; 857 u8 sizeof_stat; 858 }; 859 860 struct mt7530_dummy_poll { 861 struct mt7530_priv *priv; 862 u32 reg; 863 }; 864 865 static inline void INIT_MT7530_DUMMY_POLL(struct mt7530_dummy_poll *p, 866 struct mt7530_priv *priv, u32 reg) 867 { 868 p->priv = priv; 869 p->reg = reg; 870 } 871 872 #endif /* __MT7530_H */ 873