1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 /* String, offset, and register size in bytes if different from 4 bytes */ 28 static const struct mt7530_mib_desc mt7530_mib[] = { 29 MIB_DESC(1, 0x00, "TxDrop"), 30 MIB_DESC(1, 0x04, "TxCrcErr"), 31 MIB_DESC(1, 0x08, "TxUnicast"), 32 MIB_DESC(1, 0x0c, "TxMulticast"), 33 MIB_DESC(1, 0x10, "TxBroadcast"), 34 MIB_DESC(1, 0x14, "TxCollision"), 35 MIB_DESC(1, 0x18, "TxSingleCollision"), 36 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 37 MIB_DESC(1, 0x20, "TxDeferred"), 38 MIB_DESC(1, 0x24, "TxLateCollision"), 39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 40 MIB_DESC(1, 0x2c, "TxPause"), 41 MIB_DESC(1, 0x30, "TxPktSz64"), 42 MIB_DESC(1, 0x34, "TxPktSz65To127"), 43 MIB_DESC(1, 0x38, "TxPktSz128To255"), 44 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 45 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 46 MIB_DESC(1, 0x44, "Tx1024ToMax"), 47 MIB_DESC(2, 0x48, "TxBytes"), 48 MIB_DESC(1, 0x60, "RxDrop"), 49 MIB_DESC(1, 0x64, "RxFiltering"), 50 MIB_DESC(1, 0x6c, "RxMulticast"), 51 MIB_DESC(1, 0x70, "RxBroadcast"), 52 MIB_DESC(1, 0x74, "RxAlignErr"), 53 MIB_DESC(1, 0x78, "RxCrcErr"), 54 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 55 MIB_DESC(1, 0x80, "RxFragErr"), 56 MIB_DESC(1, 0x84, "RxOverSzErr"), 57 MIB_DESC(1, 0x88, "RxJabberErr"), 58 MIB_DESC(1, 0x8c, "RxPause"), 59 MIB_DESC(1, 0x90, "RxPktSz64"), 60 MIB_DESC(1, 0x94, "RxPktSz65To127"), 61 MIB_DESC(1, 0x98, "RxPktSz128To255"), 62 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 63 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 64 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 65 MIB_DESC(2, 0xa8, "RxBytes"), 66 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 67 MIB_DESC(1, 0xb4, "RxIngressDrop"), 68 MIB_DESC(1, 0xb8, "RxArlDrop"), 69 }; 70 71 /* Since phy_device has not yet been created and 72 * phy_{read,write}_mmd_indirect is not available, we provide our own 73 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 74 * to complete this function. 75 */ 76 static int 77 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 78 { 79 struct mii_bus *bus = priv->bus; 80 int value, ret; 81 82 /* Write the desired MMD Devad */ 83 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 84 if (ret < 0) 85 goto err; 86 87 /* Write the desired MMD register address */ 88 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 89 if (ret < 0) 90 goto err; 91 92 /* Select the Function : DATA with no post increment */ 93 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 94 if (ret < 0) 95 goto err; 96 97 /* Read the content of the MMD's selected register */ 98 value = bus->read(bus, 0, MII_MMD_DATA); 99 100 return value; 101 err: 102 dev_err(&bus->dev, "failed to read mmd register\n"); 103 104 return ret; 105 } 106 107 static int 108 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 109 int devad, u32 data) 110 { 111 struct mii_bus *bus = priv->bus; 112 int ret; 113 114 /* Write the desired MMD Devad */ 115 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 116 if (ret < 0) 117 goto err; 118 119 /* Write the desired MMD register address */ 120 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 121 if (ret < 0) 122 goto err; 123 124 /* Select the Function : DATA with no post increment */ 125 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 126 if (ret < 0) 127 goto err; 128 129 /* Write the data into MMD's selected register */ 130 ret = bus->write(bus, 0, MII_MMD_DATA, data); 131 err: 132 if (ret < 0) 133 dev_err(&bus->dev, 134 "failed to write mmd register\n"); 135 return ret; 136 } 137 138 static void 139 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 140 { 141 struct mii_bus *bus = priv->bus; 142 143 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 144 145 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 146 147 mutex_unlock(&bus->mdio_lock); 148 } 149 150 static void 151 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 152 { 153 struct mii_bus *bus = priv->bus; 154 u32 val; 155 156 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 157 158 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 159 val &= ~mask; 160 val |= set; 161 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 162 163 mutex_unlock(&bus->mdio_lock); 164 } 165 166 static void 167 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 168 { 169 core_rmw(priv, reg, 0, val); 170 } 171 172 static void 173 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, val, 0); 176 } 177 178 static int 179 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 struct mii_bus *bus = priv->bus; 182 u16 page, r, lo, hi; 183 int ret; 184 185 page = (reg >> 6) & 0x3ff; 186 r = (reg >> 2) & 0xf; 187 lo = val & 0xffff; 188 hi = val >> 16; 189 190 /* MT7530 uses 31 as the pseudo port */ 191 ret = bus->write(bus, 0x1f, 0x1f, page); 192 if (ret < 0) 193 goto err; 194 195 ret = bus->write(bus, 0x1f, r, lo); 196 if (ret < 0) 197 goto err; 198 199 ret = bus->write(bus, 0x1f, 0x10, hi); 200 err: 201 if (ret < 0) 202 dev_err(&bus->dev, 203 "failed to write mt7530 register\n"); 204 return ret; 205 } 206 207 static u32 208 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 209 { 210 struct mii_bus *bus = priv->bus; 211 u16 page, r, lo, hi; 212 int ret; 213 214 page = (reg >> 6) & 0x3ff; 215 r = (reg >> 2) & 0xf; 216 217 /* MT7530 uses 31 as the pseudo port */ 218 ret = bus->write(bus, 0x1f, 0x1f, page); 219 if (ret < 0) { 220 dev_err(&bus->dev, 221 "failed to read mt7530 register\n"); 222 return ret; 223 } 224 225 lo = bus->read(bus, 0x1f, r); 226 hi = bus->read(bus, 0x1f, 0x10); 227 228 return (hi << 16) | (lo & 0xffff); 229 } 230 231 static void 232 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 233 { 234 struct mii_bus *bus = priv->bus; 235 236 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 237 238 mt7530_mii_write(priv, reg, val); 239 240 mutex_unlock(&bus->mdio_lock); 241 } 242 243 static u32 244 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 245 { 246 return mt7530_mii_read(p->priv, p->reg); 247 } 248 249 static u32 250 _mt7530_read(struct mt7530_dummy_poll *p) 251 { 252 struct mii_bus *bus = p->priv->bus; 253 u32 val; 254 255 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 256 257 val = mt7530_mii_read(p->priv, p->reg); 258 259 mutex_unlock(&bus->mdio_lock); 260 261 return val; 262 } 263 264 static u32 265 mt7530_read(struct mt7530_priv *priv, u32 reg) 266 { 267 struct mt7530_dummy_poll p; 268 269 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 270 return _mt7530_read(&p); 271 } 272 273 static void 274 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 275 u32 mask, u32 set) 276 { 277 struct mii_bus *bus = priv->bus; 278 u32 val; 279 280 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 281 282 val = mt7530_mii_read(priv, reg); 283 val &= ~mask; 284 val |= set; 285 mt7530_mii_write(priv, reg, val); 286 287 mutex_unlock(&bus->mdio_lock); 288 } 289 290 static void 291 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 292 { 293 mt7530_rmw(priv, reg, 0, val); 294 } 295 296 static void 297 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, val, 0); 300 } 301 302 static int 303 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 304 { 305 u32 val; 306 int ret; 307 struct mt7530_dummy_poll p; 308 309 /* Set the command operating upon the MAC address entries */ 310 val = ATC_BUSY | ATC_MAT(0) | cmd; 311 mt7530_write(priv, MT7530_ATC, val); 312 313 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 314 ret = readx_poll_timeout(_mt7530_read, &p, val, 315 !(val & ATC_BUSY), 20, 20000); 316 if (ret < 0) { 317 dev_err(priv->dev, "reset timeout\n"); 318 return ret; 319 } 320 321 /* Additional sanity for read command if the specified 322 * entry is invalid 323 */ 324 val = mt7530_read(priv, MT7530_ATC); 325 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 326 return -EINVAL; 327 328 if (rsp) 329 *rsp = val; 330 331 return 0; 332 } 333 334 static void 335 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 336 { 337 u32 reg[3]; 338 int i; 339 340 /* Read from ARL table into an array */ 341 for (i = 0; i < 3; i++) { 342 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 343 344 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 345 __func__, __LINE__, i, reg[i]); 346 } 347 348 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 349 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 350 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 351 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 352 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 353 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 354 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 355 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 356 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 357 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 358 } 359 360 static void 361 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 362 u8 port_mask, const u8 *mac, 363 u8 aging, u8 type) 364 { 365 u32 reg[3] = { 0 }; 366 int i; 367 368 reg[1] |= vid & CVID_MASK; 369 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 370 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 371 /* STATIC_ENT indicate that entry is static wouldn't 372 * be aged out and STATIC_EMP specified as erasing an 373 * entry 374 */ 375 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 376 reg[1] |= mac[5] << MAC_BYTE_5; 377 reg[1] |= mac[4] << MAC_BYTE_4; 378 reg[0] |= mac[3] << MAC_BYTE_3; 379 reg[0] |= mac[2] << MAC_BYTE_2; 380 reg[0] |= mac[1] << MAC_BYTE_1; 381 reg[0] |= mac[0] << MAC_BYTE_0; 382 383 /* Write array into the ARL table */ 384 for (i = 0; i < 3; i++) 385 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 386 } 387 388 /* Setup TX circuit including relevant PAD and driving */ 389 static int 390 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 391 { 392 struct mt7530_priv *priv = ds->priv; 393 u32 ncpo1, ssc_delta, trgint, i, xtal; 394 395 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 396 397 if (xtal == HWTRAP_XTAL_20MHZ) { 398 dev_err(priv->dev, 399 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 400 __func__); 401 return -EINVAL; 402 } 403 404 switch (interface) { 405 case PHY_INTERFACE_MODE_RGMII: 406 trgint = 0; 407 /* PLL frequency: 125MHz */ 408 ncpo1 = 0x0c80; 409 break; 410 case PHY_INTERFACE_MODE_TRGMII: 411 trgint = 1; 412 if (priv->id == ID_MT7621) { 413 /* PLL frequency: 150MHz: 1.2GBit */ 414 if (xtal == HWTRAP_XTAL_40MHZ) 415 ncpo1 = 0x0780; 416 if (xtal == HWTRAP_XTAL_25MHZ) 417 ncpo1 = 0x0a00; 418 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 419 if (xtal == HWTRAP_XTAL_40MHZ) 420 ncpo1 = 0x0c80; 421 if (xtal == HWTRAP_XTAL_25MHZ) 422 ncpo1 = 0x1400; 423 } 424 break; 425 default: 426 dev_err(priv->dev, "xMII interface %d not supported\n", 427 interface); 428 return -EINVAL; 429 } 430 431 if (xtal == HWTRAP_XTAL_25MHZ) 432 ssc_delta = 0x57; 433 else 434 ssc_delta = 0x87; 435 436 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 437 P6_INTF_MODE(trgint)); 438 439 /* Lower Tx Driving for TRGMII path */ 440 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 441 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 442 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 443 444 /* Disable MT7530 core and TRGMII Tx clocks */ 445 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 446 REG_GSWCK_EN | REG_TRGMIICK_EN); 447 448 /* Setup core clock for MT7530 */ 449 /* Disable PLL */ 450 core_write(priv, CORE_GSWPLL_GRP1, 0); 451 452 /* Set core clock into 500Mhz */ 453 core_write(priv, CORE_GSWPLL_GRP2, 454 RG_GSWPLL_POSDIV_500M(1) | 455 RG_GSWPLL_FBKDIV_500M(25)); 456 457 /* Enable PLL */ 458 core_write(priv, CORE_GSWPLL_GRP1, 459 RG_GSWPLL_EN_PRE | 460 RG_GSWPLL_POSDIV_200M(2) | 461 RG_GSWPLL_FBKDIV_200M(32)); 462 463 /* Setup the MT7530 TRGMII Tx Clock */ 464 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 465 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 466 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 467 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 468 core_write(priv, CORE_PLL_GROUP4, 469 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 470 RG_SYSPLL_BIAS_LPF_EN); 471 core_write(priv, CORE_PLL_GROUP2, 472 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 473 RG_SYSPLL_POSDIV(1)); 474 core_write(priv, CORE_PLL_GROUP7, 475 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 476 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 477 478 /* Enable MT7530 core and TRGMII Tx clocks */ 479 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 480 REG_GSWCK_EN | REG_TRGMIICK_EN); 481 482 if (!trgint) 483 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 484 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 485 RD_TAP_MASK, RD_TAP(16)); 486 return 0; 487 } 488 489 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 490 { 491 u32 val; 492 493 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 494 495 return (val & PAD_DUAL_SGMII_EN) != 0; 496 } 497 498 static int 499 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 500 { 501 struct mt7530_priv *priv = ds->priv; 502 u32 top_sig; 503 u32 hwstrap; 504 u32 xtal; 505 u32 val; 506 507 if (mt7531_dual_sgmii_supported(priv)) 508 return 0; 509 510 val = mt7530_read(priv, MT7531_CREV); 511 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 512 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 513 if ((val & CHIP_REV_M) > 0) 514 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 515 HWTRAP_XTAL_FSEL_25MHZ; 516 else 517 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 518 519 /* Step 1 : Disable MT7531 COREPLL */ 520 val = mt7530_read(priv, MT7531_PLLGP_EN); 521 val &= ~EN_COREPLL; 522 mt7530_write(priv, MT7531_PLLGP_EN, val); 523 524 /* Step 2: switch to XTAL output */ 525 val = mt7530_read(priv, MT7531_PLLGP_EN); 526 val |= SW_CLKSW; 527 mt7530_write(priv, MT7531_PLLGP_EN, val); 528 529 val = mt7530_read(priv, MT7531_PLLGP_CR0); 530 val &= ~RG_COREPLL_EN; 531 mt7530_write(priv, MT7531_PLLGP_CR0, val); 532 533 /* Step 3: disable PLLGP and enable program PLLGP */ 534 val = mt7530_read(priv, MT7531_PLLGP_EN); 535 val |= SW_PLLGP; 536 mt7530_write(priv, MT7531_PLLGP_EN, val); 537 538 /* Step 4: program COREPLL output frequency to 500MHz */ 539 val = mt7530_read(priv, MT7531_PLLGP_CR0); 540 val &= ~RG_COREPLL_POSDIV_M; 541 val |= 2 << RG_COREPLL_POSDIV_S; 542 mt7530_write(priv, MT7531_PLLGP_CR0, val); 543 usleep_range(25, 35); 544 545 switch (xtal) { 546 case HWTRAP_XTAL_FSEL_25MHZ: 547 val = mt7530_read(priv, MT7531_PLLGP_CR0); 548 val &= ~RG_COREPLL_SDM_PCW_M; 549 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 550 mt7530_write(priv, MT7531_PLLGP_CR0, val); 551 break; 552 case HWTRAP_XTAL_FSEL_40MHZ: 553 val = mt7530_read(priv, MT7531_PLLGP_CR0); 554 val &= ~RG_COREPLL_SDM_PCW_M; 555 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 556 mt7530_write(priv, MT7531_PLLGP_CR0, val); 557 break; 558 } 559 560 /* Set feedback divide ratio update signal to high */ 561 val = mt7530_read(priv, MT7531_PLLGP_CR0); 562 val |= RG_COREPLL_SDM_PCW_CHG; 563 mt7530_write(priv, MT7531_PLLGP_CR0, val); 564 /* Wait for at least 16 XTAL clocks */ 565 usleep_range(10, 20); 566 567 /* Step 5: set feedback divide ratio update signal to low */ 568 val = mt7530_read(priv, MT7531_PLLGP_CR0); 569 val &= ~RG_COREPLL_SDM_PCW_CHG; 570 mt7530_write(priv, MT7531_PLLGP_CR0, val); 571 572 /* Enable 325M clock for SGMII */ 573 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 574 575 /* Enable 250SSC clock for RGMII */ 576 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 577 578 /* Step 6: Enable MT7531 PLL */ 579 val = mt7530_read(priv, MT7531_PLLGP_CR0); 580 val |= RG_COREPLL_EN; 581 mt7530_write(priv, MT7531_PLLGP_CR0, val); 582 583 val = mt7530_read(priv, MT7531_PLLGP_EN); 584 val |= EN_COREPLL; 585 mt7530_write(priv, MT7531_PLLGP_EN, val); 586 usleep_range(25, 35); 587 588 return 0; 589 } 590 591 static void 592 mt7530_mib_reset(struct dsa_switch *ds) 593 { 594 struct mt7530_priv *priv = ds->priv; 595 596 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 597 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 598 } 599 600 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 601 { 602 return mdiobus_read_nested(priv->bus, port, regnum); 603 } 604 605 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 606 u16 val) 607 { 608 return mdiobus_write_nested(priv->bus, port, regnum, val); 609 } 610 611 static int 612 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 613 int regnum) 614 { 615 struct mii_bus *bus = priv->bus; 616 struct mt7530_dummy_poll p; 617 u32 reg, val; 618 int ret; 619 620 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 621 622 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 623 624 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 625 !(val & MT7531_PHY_ACS_ST), 20, 100000); 626 if (ret < 0) { 627 dev_err(priv->dev, "poll timeout\n"); 628 goto out; 629 } 630 631 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 632 MT7531_MDIO_DEV_ADDR(devad) | regnum; 633 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 634 635 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 636 !(val & MT7531_PHY_ACS_ST), 20, 100000); 637 if (ret < 0) { 638 dev_err(priv->dev, "poll timeout\n"); 639 goto out; 640 } 641 642 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 643 MT7531_MDIO_DEV_ADDR(devad); 644 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 645 646 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 647 !(val & MT7531_PHY_ACS_ST), 20, 100000); 648 if (ret < 0) { 649 dev_err(priv->dev, "poll timeout\n"); 650 goto out; 651 } 652 653 ret = val & MT7531_MDIO_RW_DATA_MASK; 654 out: 655 mutex_unlock(&bus->mdio_lock); 656 657 return ret; 658 } 659 660 static int 661 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 662 int regnum, u32 data) 663 { 664 struct mii_bus *bus = priv->bus; 665 struct mt7530_dummy_poll p; 666 u32 val, reg; 667 int ret; 668 669 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 670 671 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 672 673 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 674 !(val & MT7531_PHY_ACS_ST), 20, 100000); 675 if (ret < 0) { 676 dev_err(priv->dev, "poll timeout\n"); 677 goto out; 678 } 679 680 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 681 MT7531_MDIO_DEV_ADDR(devad) | regnum; 682 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 683 684 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 685 !(val & MT7531_PHY_ACS_ST), 20, 100000); 686 if (ret < 0) { 687 dev_err(priv->dev, "poll timeout\n"); 688 goto out; 689 } 690 691 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 692 MT7531_MDIO_DEV_ADDR(devad) | data; 693 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 694 695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 696 !(val & MT7531_PHY_ACS_ST), 20, 100000); 697 if (ret < 0) { 698 dev_err(priv->dev, "poll timeout\n"); 699 goto out; 700 } 701 702 out: 703 mutex_unlock(&bus->mdio_lock); 704 705 return ret; 706 } 707 708 static int 709 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 710 { 711 struct mii_bus *bus = priv->bus; 712 struct mt7530_dummy_poll p; 713 int ret; 714 u32 val; 715 716 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 717 718 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 719 720 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 721 !(val & MT7531_PHY_ACS_ST), 20, 100000); 722 if (ret < 0) { 723 dev_err(priv->dev, "poll timeout\n"); 724 goto out; 725 } 726 727 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 728 MT7531_MDIO_REG_ADDR(regnum); 729 730 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 731 732 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 733 !(val & MT7531_PHY_ACS_ST), 20, 100000); 734 if (ret < 0) { 735 dev_err(priv->dev, "poll timeout\n"); 736 goto out; 737 } 738 739 ret = val & MT7531_MDIO_RW_DATA_MASK; 740 out: 741 mutex_unlock(&bus->mdio_lock); 742 743 return ret; 744 } 745 746 static int 747 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 748 u16 data) 749 { 750 struct mii_bus *bus = priv->bus; 751 struct mt7530_dummy_poll p; 752 int ret; 753 u32 reg; 754 755 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 756 757 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 758 759 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 760 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 761 if (ret < 0) { 762 dev_err(priv->dev, "poll timeout\n"); 763 goto out; 764 } 765 766 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 767 MT7531_MDIO_REG_ADDR(regnum) | data; 768 769 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 770 771 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 772 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 773 if (ret < 0) { 774 dev_err(priv->dev, "poll timeout\n"); 775 goto out; 776 } 777 778 out: 779 mutex_unlock(&bus->mdio_lock); 780 781 return ret; 782 } 783 784 static int 785 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 786 { 787 int devad; 788 int ret; 789 790 if (regnum & MII_ADDR_C45) { 791 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 792 ret = mt7531_ind_c45_phy_read(priv, port, devad, 793 regnum & MII_REGADDR_C45_MASK); 794 } else { 795 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 796 } 797 798 return ret; 799 } 800 801 static int 802 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 803 u16 data) 804 { 805 int devad; 806 int ret; 807 808 if (regnum & MII_ADDR_C45) { 809 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 810 ret = mt7531_ind_c45_phy_write(priv, port, devad, 811 regnum & MII_REGADDR_C45_MASK, 812 data); 813 } else { 814 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 815 } 816 817 return ret; 818 } 819 820 static int 821 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 822 { 823 struct mt7530_priv *priv = bus->priv; 824 825 return priv->info->phy_read(priv, port, regnum); 826 } 827 828 static int 829 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 830 { 831 struct mt7530_priv *priv = bus->priv; 832 833 return priv->info->phy_write(priv, port, regnum, val); 834 } 835 836 static void 837 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 838 uint8_t *data) 839 { 840 int i; 841 842 if (stringset != ETH_SS_STATS) 843 return; 844 845 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 846 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 847 ETH_GSTRING_LEN); 848 } 849 850 static void 851 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 852 uint64_t *data) 853 { 854 struct mt7530_priv *priv = ds->priv; 855 const struct mt7530_mib_desc *mib; 856 u32 reg, i; 857 u64 hi; 858 859 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 860 mib = &mt7530_mib[i]; 861 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 862 863 data[i] = mt7530_read(priv, reg); 864 if (mib->size == 2) { 865 hi = mt7530_read(priv, reg + 4); 866 data[i] |= hi << 32; 867 } 868 } 869 } 870 871 static int 872 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 873 { 874 if (sset != ETH_SS_STATS) 875 return 0; 876 877 return ARRAY_SIZE(mt7530_mib); 878 } 879 880 static int 881 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 882 { 883 struct mt7530_priv *priv = ds->priv; 884 unsigned int secs = msecs / 1000; 885 unsigned int tmp_age_count; 886 unsigned int error = -1; 887 unsigned int age_count; 888 unsigned int age_unit; 889 890 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 891 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 892 return -ERANGE; 893 894 /* iterate through all possible age_count to find the closest pair */ 895 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 896 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 897 898 if (tmp_age_unit <= AGE_UNIT_MAX) { 899 unsigned int tmp_error = secs - 900 (tmp_age_count + 1) * (tmp_age_unit + 1); 901 902 /* found a closer pair */ 903 if (error > tmp_error) { 904 error = tmp_error; 905 age_count = tmp_age_count; 906 age_unit = tmp_age_unit; 907 } 908 909 /* found the exact match, so break the loop */ 910 if (!error) 911 break; 912 } 913 } 914 915 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 916 917 return 0; 918 } 919 920 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 921 { 922 struct mt7530_priv *priv = ds->priv; 923 u8 tx_delay = 0; 924 int val; 925 926 mutex_lock(&priv->reg_mutex); 927 928 val = mt7530_read(priv, MT7530_MHWTRAP); 929 930 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 931 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 932 933 switch (priv->p5_intf_sel) { 934 case P5_INTF_SEL_PHY_P0: 935 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 936 val |= MHWTRAP_PHY0_SEL; 937 fallthrough; 938 case P5_INTF_SEL_PHY_P4: 939 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 940 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 941 942 /* Setup the MAC by default for the cpu port */ 943 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 944 break; 945 case P5_INTF_SEL_GMAC5: 946 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 947 val &= ~MHWTRAP_P5_DIS; 948 break; 949 case P5_DISABLED: 950 interface = PHY_INTERFACE_MODE_NA; 951 break; 952 default: 953 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 954 priv->p5_intf_sel); 955 goto unlock_exit; 956 } 957 958 /* Setup RGMII settings */ 959 if (phy_interface_mode_is_rgmii(interface)) { 960 val |= MHWTRAP_P5_RGMII_MODE; 961 962 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 963 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 964 965 /* Don't set delay in DSA mode */ 966 if (!dsa_is_dsa_port(priv->ds, 5) && 967 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 968 interface == PHY_INTERFACE_MODE_RGMII_ID)) 969 tx_delay = 4; /* n * 0.5 ns */ 970 971 /* P5 RGMII TX Clock Control: delay x */ 972 mt7530_write(priv, MT7530_P5RGMIITXCR, 973 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 974 975 /* reduce P5 RGMII Tx driving, 8mA */ 976 mt7530_write(priv, MT7530_IO_DRV_CR, 977 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 978 } 979 980 mt7530_write(priv, MT7530_MHWTRAP, val); 981 982 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 983 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 984 985 priv->p5_interface = interface; 986 987 unlock_exit: 988 mutex_unlock(&priv->reg_mutex); 989 } 990 991 static int 992 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 993 { 994 struct mt7530_priv *priv = ds->priv; 995 int ret; 996 997 /* Setup max capability of CPU port at first */ 998 if (priv->info->cpu_port_config) { 999 ret = priv->info->cpu_port_config(ds, port); 1000 if (ret) 1001 return ret; 1002 } 1003 1004 /* Enable Mediatek header mode on the cpu port */ 1005 mt7530_write(priv, MT7530_PVC_P(port), 1006 PORT_SPEC_TAG); 1007 1008 /* Disable flooding by default */ 1009 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1010 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1011 1012 /* Set CPU port number */ 1013 if (priv->id == ID_MT7621) 1014 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1015 1016 /* CPU port gets connected to all user ports of 1017 * the switch. 1018 */ 1019 mt7530_write(priv, MT7530_PCR_P(port), 1020 PCR_MATRIX(dsa_user_ports(priv->ds))); 1021 1022 return 0; 1023 } 1024 1025 static int 1026 mt7530_port_enable(struct dsa_switch *ds, int port, 1027 struct phy_device *phy) 1028 { 1029 struct mt7530_priv *priv = ds->priv; 1030 1031 if (!dsa_is_user_port(ds, port)) 1032 return 0; 1033 1034 mutex_lock(&priv->reg_mutex); 1035 1036 /* Allow the user port gets connected to the cpu port and also 1037 * restore the port matrix if the port is the member of a certain 1038 * bridge. 1039 */ 1040 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1041 priv->ports[port].enable = true; 1042 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1043 priv->ports[port].pm); 1044 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1045 1046 mutex_unlock(&priv->reg_mutex); 1047 1048 return 0; 1049 } 1050 1051 static void 1052 mt7530_port_disable(struct dsa_switch *ds, int port) 1053 { 1054 struct mt7530_priv *priv = ds->priv; 1055 1056 if (!dsa_is_user_port(ds, port)) 1057 return; 1058 1059 mutex_lock(&priv->reg_mutex); 1060 1061 /* Clear up all port matrix which could be restored in the next 1062 * enablement for the port. 1063 */ 1064 priv->ports[port].enable = false; 1065 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1066 PCR_MATRIX_CLR); 1067 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1068 1069 mutex_unlock(&priv->reg_mutex); 1070 } 1071 1072 static int 1073 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1074 { 1075 struct mt7530_priv *priv = ds->priv; 1076 struct mii_bus *bus = priv->bus; 1077 int length; 1078 u32 val; 1079 1080 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1081 * largest MTU of the slave ports. Because the switch only has a global 1082 * RX length register, only allowing CPU port here is enough. 1083 */ 1084 if (!dsa_is_cpu_port(ds, port)) 1085 return 0; 1086 1087 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1088 1089 val = mt7530_mii_read(priv, MT7530_GMACCR); 1090 val &= ~MAX_RX_PKT_LEN_MASK; 1091 1092 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1093 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1094 if (length <= 1522) { 1095 val |= MAX_RX_PKT_LEN_1522; 1096 } else if (length <= 1536) { 1097 val |= MAX_RX_PKT_LEN_1536; 1098 } else if (length <= 1552) { 1099 val |= MAX_RX_PKT_LEN_1552; 1100 } else { 1101 val &= ~MAX_RX_JUMBO_MASK; 1102 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1103 val |= MAX_RX_PKT_LEN_JUMBO; 1104 } 1105 1106 mt7530_mii_write(priv, MT7530_GMACCR, val); 1107 1108 mutex_unlock(&bus->mdio_lock); 1109 1110 return 0; 1111 } 1112 1113 static int 1114 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1115 { 1116 return MT7530_MAX_MTU; 1117 } 1118 1119 static void 1120 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1121 { 1122 struct mt7530_priv *priv = ds->priv; 1123 u32 stp_state; 1124 1125 switch (state) { 1126 case BR_STATE_DISABLED: 1127 stp_state = MT7530_STP_DISABLED; 1128 break; 1129 case BR_STATE_BLOCKING: 1130 stp_state = MT7530_STP_BLOCKING; 1131 break; 1132 case BR_STATE_LISTENING: 1133 stp_state = MT7530_STP_LISTENING; 1134 break; 1135 case BR_STATE_LEARNING: 1136 stp_state = MT7530_STP_LEARNING; 1137 break; 1138 case BR_STATE_FORWARDING: 1139 default: 1140 stp_state = MT7530_STP_FORWARDING; 1141 break; 1142 } 1143 1144 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 1145 } 1146 1147 static int 1148 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1149 struct switchdev_brport_flags flags, 1150 struct netlink_ext_ack *extack) 1151 { 1152 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1153 BR_BCAST_FLOOD)) 1154 return -EINVAL; 1155 1156 return 0; 1157 } 1158 1159 static int 1160 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1161 struct switchdev_brport_flags flags, 1162 struct netlink_ext_ack *extack) 1163 { 1164 struct mt7530_priv *priv = ds->priv; 1165 1166 if (flags.mask & BR_LEARNING) 1167 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1168 flags.val & BR_LEARNING ? 0 : SA_DIS); 1169 1170 if (flags.mask & BR_FLOOD) 1171 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1172 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1173 1174 if (flags.mask & BR_MCAST_FLOOD) 1175 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1176 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1177 1178 if (flags.mask & BR_BCAST_FLOOD) 1179 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1180 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1181 1182 return 0; 1183 } 1184 1185 static int 1186 mt7530_port_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 1187 struct netlink_ext_ack *extack) 1188 { 1189 struct mt7530_priv *priv = ds->priv; 1190 1191 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1192 mrouter ? UNM_FFP(BIT(port)) : 0); 1193 1194 return 0; 1195 } 1196 1197 static int 1198 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1199 struct net_device *bridge) 1200 { 1201 struct mt7530_priv *priv = ds->priv; 1202 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1203 int i; 1204 1205 mutex_lock(&priv->reg_mutex); 1206 1207 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1208 /* Add this port to the port matrix of the other ports in the 1209 * same bridge. If the port is disabled, port matrix is kept 1210 * and not being setup until the port becomes enabled. 1211 */ 1212 if (dsa_is_user_port(ds, i) && i != port) { 1213 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1214 continue; 1215 if (priv->ports[i].enable) 1216 mt7530_set(priv, MT7530_PCR_P(i), 1217 PCR_MATRIX(BIT(port))); 1218 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1219 1220 port_bitmap |= BIT(i); 1221 } 1222 } 1223 1224 /* Add the all other ports to this port matrix. */ 1225 if (priv->ports[port].enable) 1226 mt7530_rmw(priv, MT7530_PCR_P(port), 1227 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1228 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1229 1230 mutex_unlock(&priv->reg_mutex); 1231 1232 return 0; 1233 } 1234 1235 static void 1236 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1237 { 1238 struct mt7530_priv *priv = ds->priv; 1239 bool all_user_ports_removed = true; 1240 int i; 1241 1242 /* When a port is removed from the bridge, the port would be set up 1243 * back to the default as is at initial boot which is a VLAN-unaware 1244 * port. 1245 */ 1246 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1247 MT7530_PORT_MATRIX_MODE); 1248 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1249 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1250 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1251 1252 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1253 if (dsa_is_user_port(ds, i) && 1254 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1255 all_user_ports_removed = false; 1256 break; 1257 } 1258 } 1259 1260 /* CPU port also does the same thing until all user ports belonging to 1261 * the CPU port get out of VLAN filtering mode. 1262 */ 1263 if (all_user_ports_removed) { 1264 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1265 PCR_MATRIX(dsa_user_ports(priv->ds))); 1266 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1267 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1268 } 1269 } 1270 1271 static void 1272 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1273 { 1274 struct mt7530_priv *priv = ds->priv; 1275 1276 /* Trapped into security mode allows packet forwarding through VLAN 1277 * table lookup. CPU port is set to fallback mode to let untagged 1278 * frames pass through. 1279 */ 1280 if (dsa_is_cpu_port(ds, port)) 1281 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1282 MT7530_PORT_FALLBACK_MODE); 1283 else 1284 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1285 MT7530_PORT_SECURITY_MODE); 1286 1287 /* Set the port as a user port which is to be able to recognize VID 1288 * from incoming packets before fetching entry within the VLAN table. 1289 */ 1290 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1291 VLAN_ATTR(MT7530_VLAN_USER) | 1292 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1293 } 1294 1295 static void 1296 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1297 struct net_device *bridge) 1298 { 1299 struct mt7530_priv *priv = ds->priv; 1300 int i; 1301 1302 mutex_lock(&priv->reg_mutex); 1303 1304 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1305 /* Remove this port from the port matrix of the other ports 1306 * in the same bridge. If the port is disabled, port matrix 1307 * is kept and not being setup until the port becomes enabled. 1308 * And the other port's port matrix cannot be broken when the 1309 * other port is still a VLAN-aware port. 1310 */ 1311 if (dsa_is_user_port(ds, i) && i != port && 1312 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1313 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1314 continue; 1315 if (priv->ports[i].enable) 1316 mt7530_clear(priv, MT7530_PCR_P(i), 1317 PCR_MATRIX(BIT(port))); 1318 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1319 } 1320 } 1321 1322 /* Set the cpu port to be the only one in the port matrix of 1323 * this port. 1324 */ 1325 if (priv->ports[port].enable) 1326 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1327 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1328 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1329 1330 mutex_unlock(&priv->reg_mutex); 1331 } 1332 1333 static int 1334 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1335 const unsigned char *addr, u16 vid) 1336 { 1337 struct mt7530_priv *priv = ds->priv; 1338 int ret; 1339 u8 port_mask = BIT(port); 1340 1341 mutex_lock(&priv->reg_mutex); 1342 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1343 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1344 mutex_unlock(&priv->reg_mutex); 1345 1346 return ret; 1347 } 1348 1349 static int 1350 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1351 const unsigned char *addr, u16 vid) 1352 { 1353 struct mt7530_priv *priv = ds->priv; 1354 int ret; 1355 u8 port_mask = BIT(port); 1356 1357 mutex_lock(&priv->reg_mutex); 1358 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1359 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1360 mutex_unlock(&priv->reg_mutex); 1361 1362 return ret; 1363 } 1364 1365 static int 1366 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1367 dsa_fdb_dump_cb_t *cb, void *data) 1368 { 1369 struct mt7530_priv *priv = ds->priv; 1370 struct mt7530_fdb _fdb = { 0 }; 1371 int cnt = MT7530_NUM_FDB_RECORDS; 1372 int ret = 0; 1373 u32 rsp = 0; 1374 1375 mutex_lock(&priv->reg_mutex); 1376 1377 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1378 if (ret < 0) 1379 goto err; 1380 1381 do { 1382 if (rsp & ATC_SRCH_HIT) { 1383 mt7530_fdb_read(priv, &_fdb); 1384 if (_fdb.port_mask & BIT(port)) { 1385 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1386 data); 1387 if (ret < 0) 1388 break; 1389 } 1390 } 1391 } while (--cnt && 1392 !(rsp & ATC_SRCH_END) && 1393 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1394 err: 1395 mutex_unlock(&priv->reg_mutex); 1396 1397 return 0; 1398 } 1399 1400 static int 1401 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1402 const struct switchdev_obj_port_mdb *mdb) 1403 { 1404 struct mt7530_priv *priv = ds->priv; 1405 const u8 *addr = mdb->addr; 1406 u16 vid = mdb->vid; 1407 u8 port_mask = 0; 1408 int ret; 1409 1410 mutex_lock(&priv->reg_mutex); 1411 1412 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1413 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1414 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1415 & PORT_MAP_MASK; 1416 1417 port_mask |= BIT(port); 1418 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1419 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1420 1421 mutex_unlock(&priv->reg_mutex); 1422 1423 return ret; 1424 } 1425 1426 static int 1427 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1428 const struct switchdev_obj_port_mdb *mdb) 1429 { 1430 struct mt7530_priv *priv = ds->priv; 1431 const u8 *addr = mdb->addr; 1432 u16 vid = mdb->vid; 1433 u8 port_mask = 0; 1434 int ret; 1435 1436 mutex_lock(&priv->reg_mutex); 1437 1438 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1439 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1440 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1441 & PORT_MAP_MASK; 1442 1443 port_mask &= ~BIT(port); 1444 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1445 port_mask ? STATIC_ENT : STATIC_EMP); 1446 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1447 1448 mutex_unlock(&priv->reg_mutex); 1449 1450 return ret; 1451 } 1452 1453 static int 1454 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1455 { 1456 struct mt7530_dummy_poll p; 1457 u32 val; 1458 int ret; 1459 1460 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1461 mt7530_write(priv, MT7530_VTCR, val); 1462 1463 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1464 ret = readx_poll_timeout(_mt7530_read, &p, val, 1465 !(val & VTCR_BUSY), 20, 20000); 1466 if (ret < 0) { 1467 dev_err(priv->dev, "poll timeout\n"); 1468 return ret; 1469 } 1470 1471 val = mt7530_read(priv, MT7530_VTCR); 1472 if (val & VTCR_INVALID) { 1473 dev_err(priv->dev, "read VTCR invalid\n"); 1474 return -EINVAL; 1475 } 1476 1477 return 0; 1478 } 1479 1480 static int 1481 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1482 struct netlink_ext_ack *extack) 1483 { 1484 if (vlan_filtering) { 1485 /* The port is being kept as VLAN-unaware port when bridge is 1486 * set up with vlan_filtering not being set, Otherwise, the 1487 * port and the corresponding CPU port is required the setup 1488 * for becoming a VLAN-aware port. 1489 */ 1490 mt7530_port_set_vlan_aware(ds, port); 1491 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1492 } else { 1493 mt7530_port_set_vlan_unaware(ds, port); 1494 } 1495 1496 return 0; 1497 } 1498 1499 static void 1500 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1501 struct mt7530_hw_vlan_entry *entry) 1502 { 1503 u8 new_members; 1504 u32 val; 1505 1506 new_members = entry->old_members | BIT(entry->port) | 1507 BIT(MT7530_CPU_PORT); 1508 1509 /* Validate the entry with independent learning, create egress tag per 1510 * VLAN and joining the port as one of the port members. 1511 */ 1512 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1513 mt7530_write(priv, MT7530_VAWD1, val); 1514 1515 /* Decide whether adding tag or not for those outgoing packets from the 1516 * port inside the VLAN. 1517 */ 1518 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1519 MT7530_VLAN_EGRESS_TAG; 1520 mt7530_rmw(priv, MT7530_VAWD2, 1521 ETAG_CTRL_P_MASK(entry->port), 1522 ETAG_CTRL_P(entry->port, val)); 1523 1524 /* CPU port is always taken as a tagged port for serving more than one 1525 * VLANs across and also being applied with egress type stack mode for 1526 * that VLAN tags would be appended after hardware special tag used as 1527 * DSA tag. 1528 */ 1529 mt7530_rmw(priv, MT7530_VAWD2, 1530 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1531 ETAG_CTRL_P(MT7530_CPU_PORT, 1532 MT7530_VLAN_EGRESS_STACK)); 1533 } 1534 1535 static void 1536 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1537 struct mt7530_hw_vlan_entry *entry) 1538 { 1539 u8 new_members; 1540 u32 val; 1541 1542 new_members = entry->old_members & ~BIT(entry->port); 1543 1544 val = mt7530_read(priv, MT7530_VAWD1); 1545 if (!(val & VLAN_VALID)) { 1546 dev_err(priv->dev, 1547 "Cannot be deleted due to invalid entry\n"); 1548 return; 1549 } 1550 1551 /* If certain member apart from CPU port is still alive in the VLAN, 1552 * the entry would be kept valid. Otherwise, the entry is got to be 1553 * disabled. 1554 */ 1555 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1556 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1557 VLAN_VALID; 1558 mt7530_write(priv, MT7530_VAWD1, val); 1559 } else { 1560 mt7530_write(priv, MT7530_VAWD1, 0); 1561 mt7530_write(priv, MT7530_VAWD2, 0); 1562 } 1563 } 1564 1565 static void 1566 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1567 struct mt7530_hw_vlan_entry *entry, 1568 mt7530_vlan_op vlan_op) 1569 { 1570 u32 val; 1571 1572 /* Fetch entry */ 1573 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1574 1575 val = mt7530_read(priv, MT7530_VAWD1); 1576 1577 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1578 1579 /* Manipulate entry */ 1580 vlan_op(priv, entry); 1581 1582 /* Flush result to hardware */ 1583 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1584 } 1585 1586 static int 1587 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1588 const struct switchdev_obj_port_vlan *vlan, 1589 struct netlink_ext_ack *extack) 1590 { 1591 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1592 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1593 struct mt7530_hw_vlan_entry new_entry; 1594 struct mt7530_priv *priv = ds->priv; 1595 1596 mutex_lock(&priv->reg_mutex); 1597 1598 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1599 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1600 1601 if (pvid) { 1602 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1603 G0_PORT_VID(vlan->vid)); 1604 priv->ports[port].pvid = vlan->vid; 1605 } 1606 1607 mutex_unlock(&priv->reg_mutex); 1608 1609 return 0; 1610 } 1611 1612 static int 1613 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1614 const struct switchdev_obj_port_vlan *vlan) 1615 { 1616 struct mt7530_hw_vlan_entry target_entry; 1617 struct mt7530_priv *priv = ds->priv; 1618 u16 pvid; 1619 1620 mutex_lock(&priv->reg_mutex); 1621 1622 pvid = priv->ports[port].pvid; 1623 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1624 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1625 mt7530_hw_vlan_del); 1626 1627 /* PVID is being restored to the default whenever the PVID port 1628 * is being removed from the VLAN. 1629 */ 1630 if (pvid == vlan->vid) 1631 pvid = G0_PORT_VID_DEF; 1632 1633 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1634 priv->ports[port].pvid = pvid; 1635 1636 mutex_unlock(&priv->reg_mutex); 1637 1638 return 0; 1639 } 1640 1641 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1642 { 1643 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1644 MIRROR_PORT(val); 1645 } 1646 1647 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1648 { 1649 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1650 MIRROR_PORT(val); 1651 } 1652 1653 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1654 struct dsa_mall_mirror_tc_entry *mirror, 1655 bool ingress) 1656 { 1657 struct mt7530_priv *priv = ds->priv; 1658 int monitor_port; 1659 u32 val; 1660 1661 /* Check for existent entry */ 1662 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1663 return -EEXIST; 1664 1665 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1666 1667 /* MT7530 only supports one monitor port */ 1668 monitor_port = mt753x_mirror_port_get(priv->id, val); 1669 if (val & MT753X_MIRROR_EN(priv->id) && 1670 monitor_port != mirror->to_local_port) 1671 return -EEXIST; 1672 1673 val |= MT753X_MIRROR_EN(priv->id); 1674 val &= ~MT753X_MIRROR_MASK(priv->id); 1675 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1676 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1677 1678 val = mt7530_read(priv, MT7530_PCR_P(port)); 1679 if (ingress) { 1680 val |= PORT_RX_MIR; 1681 priv->mirror_rx |= BIT(port); 1682 } else { 1683 val |= PORT_TX_MIR; 1684 priv->mirror_tx |= BIT(port); 1685 } 1686 mt7530_write(priv, MT7530_PCR_P(port), val); 1687 1688 return 0; 1689 } 1690 1691 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1692 struct dsa_mall_mirror_tc_entry *mirror) 1693 { 1694 struct mt7530_priv *priv = ds->priv; 1695 u32 val; 1696 1697 val = mt7530_read(priv, MT7530_PCR_P(port)); 1698 if (mirror->ingress) { 1699 val &= ~PORT_RX_MIR; 1700 priv->mirror_rx &= ~BIT(port); 1701 } else { 1702 val &= ~PORT_TX_MIR; 1703 priv->mirror_tx &= ~BIT(port); 1704 } 1705 mt7530_write(priv, MT7530_PCR_P(port), val); 1706 1707 if (!priv->mirror_rx && !priv->mirror_tx) { 1708 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1709 val &= ~MT753X_MIRROR_EN(priv->id); 1710 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1711 } 1712 } 1713 1714 static enum dsa_tag_protocol 1715 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1716 enum dsa_tag_protocol mp) 1717 { 1718 struct mt7530_priv *priv = ds->priv; 1719 1720 if (port != MT7530_CPU_PORT) { 1721 dev_warn(priv->dev, 1722 "port not matched with tagging CPU port\n"); 1723 return DSA_TAG_PROTO_NONE; 1724 } else { 1725 return DSA_TAG_PROTO_MTK; 1726 } 1727 } 1728 1729 #ifdef CONFIG_GPIOLIB 1730 static inline u32 1731 mt7530_gpio_to_bit(unsigned int offset) 1732 { 1733 /* Map GPIO offset to register bit 1734 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1735 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1736 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1737 * [14:12] port 3 LED 0..2 as GPIO 9..11 1738 * [18:16] port 4 LED 0..2 as GPIO 12..14 1739 */ 1740 return BIT(offset + offset / 3); 1741 } 1742 1743 static int 1744 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1745 { 1746 struct mt7530_priv *priv = gpiochip_get_data(gc); 1747 u32 bit = mt7530_gpio_to_bit(offset); 1748 1749 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1750 } 1751 1752 static void 1753 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1754 { 1755 struct mt7530_priv *priv = gpiochip_get_data(gc); 1756 u32 bit = mt7530_gpio_to_bit(offset); 1757 1758 if (value) 1759 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1760 else 1761 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1762 } 1763 1764 static int 1765 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1766 { 1767 struct mt7530_priv *priv = gpiochip_get_data(gc); 1768 u32 bit = mt7530_gpio_to_bit(offset); 1769 1770 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1771 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1772 } 1773 1774 static int 1775 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1776 { 1777 struct mt7530_priv *priv = gpiochip_get_data(gc); 1778 u32 bit = mt7530_gpio_to_bit(offset); 1779 1780 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1781 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1782 1783 return 0; 1784 } 1785 1786 static int 1787 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1788 { 1789 struct mt7530_priv *priv = gpiochip_get_data(gc); 1790 u32 bit = mt7530_gpio_to_bit(offset); 1791 1792 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1793 1794 if (value) 1795 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1796 else 1797 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1798 1799 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1800 1801 return 0; 1802 } 1803 1804 static int 1805 mt7530_setup_gpio(struct mt7530_priv *priv) 1806 { 1807 struct device *dev = priv->dev; 1808 struct gpio_chip *gc; 1809 1810 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1811 if (!gc) 1812 return -ENOMEM; 1813 1814 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1815 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1816 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1817 1818 gc->label = "mt7530"; 1819 gc->parent = dev; 1820 gc->owner = THIS_MODULE; 1821 gc->get_direction = mt7530_gpio_get_direction; 1822 gc->direction_input = mt7530_gpio_direction_input; 1823 gc->direction_output = mt7530_gpio_direction_output; 1824 gc->get = mt7530_gpio_get; 1825 gc->set = mt7530_gpio_set; 1826 gc->base = -1; 1827 gc->ngpio = 15; 1828 gc->can_sleep = true; 1829 1830 return devm_gpiochip_add_data(dev, gc, priv); 1831 } 1832 #endif /* CONFIG_GPIOLIB */ 1833 1834 static irqreturn_t 1835 mt7530_irq_thread_fn(int irq, void *dev_id) 1836 { 1837 struct mt7530_priv *priv = dev_id; 1838 bool handled = false; 1839 u32 val; 1840 int p; 1841 1842 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1843 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1844 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1845 mutex_unlock(&priv->bus->mdio_lock); 1846 1847 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1848 if (BIT(p) & val) { 1849 unsigned int irq; 1850 1851 irq = irq_find_mapping(priv->irq_domain, p); 1852 handle_nested_irq(irq); 1853 handled = true; 1854 } 1855 } 1856 1857 return IRQ_RETVAL(handled); 1858 } 1859 1860 static void 1861 mt7530_irq_mask(struct irq_data *d) 1862 { 1863 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1864 1865 priv->irq_enable &= ~BIT(d->hwirq); 1866 } 1867 1868 static void 1869 mt7530_irq_unmask(struct irq_data *d) 1870 { 1871 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1872 1873 priv->irq_enable |= BIT(d->hwirq); 1874 } 1875 1876 static void 1877 mt7530_irq_bus_lock(struct irq_data *d) 1878 { 1879 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1880 1881 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1882 } 1883 1884 static void 1885 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1886 { 1887 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1888 1889 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1890 mutex_unlock(&priv->bus->mdio_lock); 1891 } 1892 1893 static struct irq_chip mt7530_irq_chip = { 1894 .name = KBUILD_MODNAME, 1895 .irq_mask = mt7530_irq_mask, 1896 .irq_unmask = mt7530_irq_unmask, 1897 .irq_bus_lock = mt7530_irq_bus_lock, 1898 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1899 }; 1900 1901 static int 1902 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1903 irq_hw_number_t hwirq) 1904 { 1905 irq_set_chip_data(irq, domain->host_data); 1906 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1907 irq_set_nested_thread(irq, true); 1908 irq_set_noprobe(irq); 1909 1910 return 0; 1911 } 1912 1913 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1914 .map = mt7530_irq_map, 1915 .xlate = irq_domain_xlate_onecell, 1916 }; 1917 1918 static void 1919 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1920 { 1921 struct dsa_switch *ds = priv->ds; 1922 int p; 1923 1924 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1925 if (BIT(p) & ds->phys_mii_mask) { 1926 unsigned int irq; 1927 1928 irq = irq_create_mapping(priv->irq_domain, p); 1929 ds->slave_mii_bus->irq[p] = irq; 1930 } 1931 } 1932 } 1933 1934 static int 1935 mt7530_setup_irq(struct mt7530_priv *priv) 1936 { 1937 struct device *dev = priv->dev; 1938 struct device_node *np = dev->of_node; 1939 int ret; 1940 1941 if (!of_property_read_bool(np, "interrupt-controller")) { 1942 dev_info(dev, "no interrupt support\n"); 1943 return 0; 1944 } 1945 1946 priv->irq = of_irq_get(np, 0); 1947 if (priv->irq <= 0) { 1948 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 1949 return priv->irq ? : -EINVAL; 1950 } 1951 1952 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 1953 &mt7530_irq_domain_ops, priv); 1954 if (!priv->irq_domain) { 1955 dev_err(dev, "failed to create IRQ domain\n"); 1956 return -ENOMEM; 1957 } 1958 1959 /* This register must be set for MT7530 to properly fire interrupts */ 1960 if (priv->id != ID_MT7531) 1961 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 1962 1963 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 1964 IRQF_ONESHOT, KBUILD_MODNAME, priv); 1965 if (ret) { 1966 irq_domain_remove(priv->irq_domain); 1967 dev_err(dev, "failed to request IRQ: %d\n", ret); 1968 return ret; 1969 } 1970 1971 return 0; 1972 } 1973 1974 static void 1975 mt7530_free_mdio_irq(struct mt7530_priv *priv) 1976 { 1977 int p; 1978 1979 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1980 if (BIT(p) & priv->ds->phys_mii_mask) { 1981 unsigned int irq; 1982 1983 irq = irq_find_mapping(priv->irq_domain, p); 1984 irq_dispose_mapping(irq); 1985 } 1986 } 1987 } 1988 1989 static void 1990 mt7530_free_irq_common(struct mt7530_priv *priv) 1991 { 1992 free_irq(priv->irq, priv); 1993 irq_domain_remove(priv->irq_domain); 1994 } 1995 1996 static void 1997 mt7530_free_irq(struct mt7530_priv *priv) 1998 { 1999 mt7530_free_mdio_irq(priv); 2000 mt7530_free_irq_common(priv); 2001 } 2002 2003 static int 2004 mt7530_setup_mdio(struct mt7530_priv *priv) 2005 { 2006 struct dsa_switch *ds = priv->ds; 2007 struct device *dev = priv->dev; 2008 struct mii_bus *bus; 2009 static int idx; 2010 int ret; 2011 2012 bus = devm_mdiobus_alloc(dev); 2013 if (!bus) 2014 return -ENOMEM; 2015 2016 ds->slave_mii_bus = bus; 2017 bus->priv = priv; 2018 bus->name = KBUILD_MODNAME "-mii"; 2019 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2020 bus->read = mt753x_phy_read; 2021 bus->write = mt753x_phy_write; 2022 bus->parent = dev; 2023 bus->phy_mask = ~ds->phys_mii_mask; 2024 2025 if (priv->irq) 2026 mt7530_setup_mdio_irq(priv); 2027 2028 ret = mdiobus_register(bus); 2029 if (ret) { 2030 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2031 if (priv->irq) 2032 mt7530_free_mdio_irq(priv); 2033 } 2034 2035 return ret; 2036 } 2037 2038 static int 2039 mt7530_setup(struct dsa_switch *ds) 2040 { 2041 struct mt7530_priv *priv = ds->priv; 2042 struct device_node *phy_node; 2043 struct device_node *mac_np; 2044 struct mt7530_dummy_poll p; 2045 phy_interface_t interface; 2046 struct device_node *dn; 2047 u32 id, val; 2048 int ret, i; 2049 2050 /* The parent node of master netdev which holds the common system 2051 * controller also is the container for two GMACs nodes representing 2052 * as two netdev instances. 2053 */ 2054 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 2055 ds->mtu_enforcement_ingress = true; 2056 2057 if (priv->id == ID_MT7530) { 2058 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2059 ret = regulator_enable(priv->core_pwr); 2060 if (ret < 0) { 2061 dev_err(priv->dev, 2062 "Failed to enable core power: %d\n", ret); 2063 return ret; 2064 } 2065 2066 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2067 ret = regulator_enable(priv->io_pwr); 2068 if (ret < 0) { 2069 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2070 ret); 2071 return ret; 2072 } 2073 } 2074 2075 /* Reset whole chip through gpio pin or memory-mapped registers for 2076 * different type of hardware 2077 */ 2078 if (priv->mcm) { 2079 reset_control_assert(priv->rstc); 2080 usleep_range(1000, 1100); 2081 reset_control_deassert(priv->rstc); 2082 } else { 2083 gpiod_set_value_cansleep(priv->reset, 0); 2084 usleep_range(1000, 1100); 2085 gpiod_set_value_cansleep(priv->reset, 1); 2086 } 2087 2088 /* Waiting for MT7530 got to stable */ 2089 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2090 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2091 20, 1000000); 2092 if (ret < 0) { 2093 dev_err(priv->dev, "reset timeout\n"); 2094 return ret; 2095 } 2096 2097 id = mt7530_read(priv, MT7530_CREV); 2098 id >>= CHIP_NAME_SHIFT; 2099 if (id != MT7530_ID) { 2100 dev_err(priv->dev, "chip %x can't be supported\n", id); 2101 return -ENODEV; 2102 } 2103 2104 /* Reset the switch through internal reset */ 2105 mt7530_write(priv, MT7530_SYS_CTRL, 2106 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2107 SYS_CTRL_REG_RST); 2108 2109 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2110 val = mt7530_read(priv, MT7530_MHWTRAP); 2111 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2112 val |= MHWTRAP_MANUAL; 2113 mt7530_write(priv, MT7530_MHWTRAP, val); 2114 2115 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2116 2117 /* Enable and reset MIB counters */ 2118 mt7530_mib_reset(ds); 2119 2120 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2121 /* Disable forwarding by default on all ports */ 2122 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2123 PCR_MATRIX_CLR); 2124 2125 if (dsa_is_cpu_port(ds, i)) { 2126 ret = mt753x_cpu_port_enable(ds, i); 2127 if (ret) 2128 return ret; 2129 } else { 2130 mt7530_port_disable(ds, i); 2131 2132 /* Disable learning by default on all user ports */ 2133 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2134 } 2135 /* Enable consistent egress tag */ 2136 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2137 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2138 } 2139 2140 /* Setup port 5 */ 2141 priv->p5_intf_sel = P5_DISABLED; 2142 interface = PHY_INTERFACE_MODE_NA; 2143 2144 if (!dsa_is_unused_port(ds, 5)) { 2145 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2146 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2147 if (ret && ret != -ENODEV) 2148 return ret; 2149 } else { 2150 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2151 for_each_child_of_node(dn, mac_np) { 2152 if (!of_device_is_compatible(mac_np, 2153 "mediatek,eth-mac")) 2154 continue; 2155 2156 ret = of_property_read_u32(mac_np, "reg", &id); 2157 if (ret < 0 || id != 1) 2158 continue; 2159 2160 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2161 if (!phy_node) 2162 continue; 2163 2164 if (phy_node->parent == priv->dev->of_node->parent) { 2165 ret = of_get_phy_mode(mac_np, &interface); 2166 if (ret && ret != -ENODEV) { 2167 of_node_put(mac_np); 2168 return ret; 2169 } 2170 id = of_mdio_parse_addr(ds->dev, phy_node); 2171 if (id == 0) 2172 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2173 if (id == 4) 2174 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2175 } 2176 of_node_put(mac_np); 2177 of_node_put(phy_node); 2178 break; 2179 } 2180 } 2181 2182 #ifdef CONFIG_GPIOLIB 2183 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2184 ret = mt7530_setup_gpio(priv); 2185 if (ret) 2186 return ret; 2187 } 2188 #endif /* CONFIG_GPIOLIB */ 2189 2190 mt7530_setup_port5(ds, interface); 2191 2192 /* Flush the FDB table */ 2193 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2194 if (ret < 0) 2195 return ret; 2196 2197 return 0; 2198 } 2199 2200 static int 2201 mt7531_setup(struct dsa_switch *ds) 2202 { 2203 struct mt7530_priv *priv = ds->priv; 2204 struct mt7530_dummy_poll p; 2205 u32 val, id; 2206 int ret, i; 2207 2208 /* Reset whole chip through gpio pin or memory-mapped registers for 2209 * different type of hardware 2210 */ 2211 if (priv->mcm) { 2212 reset_control_assert(priv->rstc); 2213 usleep_range(1000, 1100); 2214 reset_control_deassert(priv->rstc); 2215 } else { 2216 gpiod_set_value_cansleep(priv->reset, 0); 2217 usleep_range(1000, 1100); 2218 gpiod_set_value_cansleep(priv->reset, 1); 2219 } 2220 2221 /* Waiting for MT7530 got to stable */ 2222 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2223 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2224 20, 1000000); 2225 if (ret < 0) { 2226 dev_err(priv->dev, "reset timeout\n"); 2227 return ret; 2228 } 2229 2230 id = mt7530_read(priv, MT7531_CREV); 2231 id >>= CHIP_NAME_SHIFT; 2232 2233 if (id != MT7531_ID) { 2234 dev_err(priv->dev, "chip %x can't be supported\n", id); 2235 return -ENODEV; 2236 } 2237 2238 /* Reset the switch through internal reset */ 2239 mt7530_write(priv, MT7530_SYS_CTRL, 2240 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2241 SYS_CTRL_REG_RST); 2242 2243 if (mt7531_dual_sgmii_supported(priv)) { 2244 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2245 2246 /* Let ds->slave_mii_bus be able to access external phy. */ 2247 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2248 MT7531_EXT_P_MDC_11); 2249 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2250 MT7531_EXT_P_MDIO_12); 2251 } else { 2252 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2253 } 2254 dev_dbg(ds->dev, "P5 support %s interface\n", 2255 p5_intf_modes(priv->p5_intf_sel)); 2256 2257 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2258 MT7531_GPIO0_INTERRUPT); 2259 2260 /* Let phylink decide the interface later. */ 2261 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2262 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2263 2264 /* Enable PHY core PLL, since phy_device has not yet been created 2265 * provided for phy_[read,write]_mmd_indirect is called, we provide 2266 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2267 * function. 2268 */ 2269 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2270 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2271 val |= MT7531_PHY_PLL_BYPASS_MODE; 2272 val &= ~MT7531_PHY_PLL_OFF; 2273 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2274 CORE_PLL_GROUP4, val); 2275 2276 /* BPDU to CPU port */ 2277 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2278 BIT(MT7530_CPU_PORT)); 2279 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2280 MT753X_BPDU_CPU_ONLY); 2281 2282 /* Enable and reset MIB counters */ 2283 mt7530_mib_reset(ds); 2284 2285 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2286 /* Disable forwarding by default on all ports */ 2287 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2288 PCR_MATRIX_CLR); 2289 2290 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2291 2292 if (dsa_is_cpu_port(ds, i)) { 2293 ret = mt753x_cpu_port_enable(ds, i); 2294 if (ret) 2295 return ret; 2296 } else { 2297 mt7530_port_disable(ds, i); 2298 2299 /* Disable learning by default on all user ports */ 2300 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2301 } 2302 2303 /* Enable consistent egress tag */ 2304 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2305 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2306 } 2307 2308 ds->mtu_enforcement_ingress = true; 2309 2310 /* Flush the FDB table */ 2311 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2312 if (ret < 0) 2313 return ret; 2314 2315 return 0; 2316 } 2317 2318 static bool 2319 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2320 const struct phylink_link_state *state) 2321 { 2322 struct mt7530_priv *priv = ds->priv; 2323 2324 switch (port) { 2325 case 0 ... 4: /* Internal phy */ 2326 if (state->interface != PHY_INTERFACE_MODE_GMII) 2327 return false; 2328 break; 2329 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2330 if (!phy_interface_mode_is_rgmii(state->interface) && 2331 state->interface != PHY_INTERFACE_MODE_MII && 2332 state->interface != PHY_INTERFACE_MODE_GMII) 2333 return false; 2334 break; 2335 case 6: /* 1st cpu port */ 2336 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2337 state->interface != PHY_INTERFACE_MODE_TRGMII) 2338 return false; 2339 break; 2340 default: 2341 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2342 port); 2343 return false; 2344 } 2345 2346 return true; 2347 } 2348 2349 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2350 { 2351 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2352 } 2353 2354 static bool 2355 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2356 const struct phylink_link_state *state) 2357 { 2358 struct mt7530_priv *priv = ds->priv; 2359 2360 switch (port) { 2361 case 0 ... 4: /* Internal phy */ 2362 if (state->interface != PHY_INTERFACE_MODE_GMII) 2363 return false; 2364 break; 2365 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2366 if (mt7531_is_rgmii_port(priv, port)) 2367 return phy_interface_mode_is_rgmii(state->interface); 2368 fallthrough; 2369 case 6: /* 1st cpu port supports sgmii/8023z only */ 2370 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2371 !phy_interface_mode_is_8023z(state->interface)) 2372 return false; 2373 break; 2374 default: 2375 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2376 port); 2377 return false; 2378 } 2379 2380 return true; 2381 } 2382 2383 static bool 2384 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2385 const struct phylink_link_state *state) 2386 { 2387 struct mt7530_priv *priv = ds->priv; 2388 2389 return priv->info->phy_mode_supported(ds, port, state); 2390 } 2391 2392 static int 2393 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2394 { 2395 struct mt7530_priv *priv = ds->priv; 2396 2397 return priv->info->pad_setup(ds, state->interface); 2398 } 2399 2400 static int 2401 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2402 phy_interface_t interface) 2403 { 2404 struct mt7530_priv *priv = ds->priv; 2405 2406 /* Only need to setup port5. */ 2407 if (port != 5) 2408 return 0; 2409 2410 mt7530_setup_port5(priv->ds, interface); 2411 2412 return 0; 2413 } 2414 2415 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2416 phy_interface_t interface, 2417 struct phy_device *phydev) 2418 { 2419 u32 val; 2420 2421 if (!mt7531_is_rgmii_port(priv, port)) { 2422 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2423 port); 2424 return -EINVAL; 2425 } 2426 2427 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2428 val |= GP_CLK_EN; 2429 val &= ~GP_MODE_MASK; 2430 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2431 val &= ~CLK_SKEW_IN_MASK; 2432 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2433 val &= ~CLK_SKEW_OUT_MASK; 2434 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2435 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2436 2437 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2438 if (!phydev || phy_driver_is_genphy(phydev)) { 2439 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2440 switch (interface) { 2441 case PHY_INTERFACE_MODE_RGMII: 2442 val |= TXCLK_NO_REVERSE; 2443 val |= RXCLK_NO_DELAY; 2444 break; 2445 case PHY_INTERFACE_MODE_RGMII_RXID: 2446 val |= TXCLK_NO_REVERSE; 2447 break; 2448 case PHY_INTERFACE_MODE_RGMII_TXID: 2449 val |= RXCLK_NO_DELAY; 2450 break; 2451 case PHY_INTERFACE_MODE_RGMII_ID: 2452 break; 2453 default: 2454 return -EINVAL; 2455 } 2456 } 2457 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2458 2459 return 0; 2460 } 2461 2462 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2463 unsigned long *supported) 2464 { 2465 /* Port5 supports ethier RGMII or SGMII. 2466 * Port6 supports SGMII only. 2467 */ 2468 switch (port) { 2469 case 5: 2470 if (mt7531_is_rgmii_port(priv, port)) 2471 break; 2472 fallthrough; 2473 case 6: 2474 phylink_set(supported, 1000baseX_Full); 2475 phylink_set(supported, 2500baseX_Full); 2476 phylink_set(supported, 2500baseT_Full); 2477 } 2478 } 2479 2480 static void 2481 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2482 unsigned int mode, phy_interface_t interface, 2483 int speed, int duplex) 2484 { 2485 struct mt7530_priv *priv = ds->priv; 2486 unsigned int val; 2487 2488 /* For adjusting speed and duplex of SGMII force mode. */ 2489 if (interface != PHY_INTERFACE_MODE_SGMII || 2490 phylink_autoneg_inband(mode)) 2491 return; 2492 2493 /* SGMII force mode setting */ 2494 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2495 val &= ~MT7531_SGMII_IF_MODE_MASK; 2496 2497 switch (speed) { 2498 case SPEED_10: 2499 val |= MT7531_SGMII_FORCE_SPEED_10; 2500 break; 2501 case SPEED_100: 2502 val |= MT7531_SGMII_FORCE_SPEED_100; 2503 break; 2504 case SPEED_1000: 2505 val |= MT7531_SGMII_FORCE_SPEED_1000; 2506 break; 2507 } 2508 2509 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2510 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2511 */ 2512 if ((speed == SPEED_10 || speed == SPEED_100) && 2513 duplex != DUPLEX_FULL) 2514 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2515 2516 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2517 } 2518 2519 static bool mt753x_is_mac_port(u32 port) 2520 { 2521 return (port == 5 || port == 6); 2522 } 2523 2524 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2525 phy_interface_t interface) 2526 { 2527 u32 val; 2528 2529 if (!mt753x_is_mac_port(port)) 2530 return -EINVAL; 2531 2532 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2533 MT7531_SGMII_PHYA_PWD); 2534 2535 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2536 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2537 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2538 * encoding. 2539 */ 2540 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2541 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2542 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2543 2544 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2545 2546 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2547 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2548 */ 2549 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2550 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2551 MT7531_SGMII_FORCE_SPEED_1000); 2552 2553 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2554 2555 return 0; 2556 } 2557 2558 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2559 phy_interface_t interface) 2560 { 2561 if (!mt753x_is_mac_port(port)) 2562 return -EINVAL; 2563 2564 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2565 MT7531_SGMII_PHYA_PWD); 2566 2567 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2568 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2569 2570 mt7530_set(priv, MT7531_SGMII_MODE(port), 2571 MT7531_SGMII_REMOTE_FAULT_DIS | 2572 MT7531_SGMII_SPEED_DUPLEX_AN); 2573 2574 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2575 MT7531_SGMII_TX_CONFIG_MASK, 1); 2576 2577 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2578 2579 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2580 2581 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2582 2583 return 0; 2584 } 2585 2586 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2587 { 2588 struct mt7530_priv *priv = ds->priv; 2589 u32 val; 2590 2591 /* Only restart AN when AN is enabled */ 2592 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2593 if (val & MT7531_SGMII_AN_ENABLE) { 2594 val |= MT7531_SGMII_AN_RESTART; 2595 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2596 } 2597 } 2598 2599 static int 2600 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2601 phy_interface_t interface) 2602 { 2603 struct mt7530_priv *priv = ds->priv; 2604 struct phy_device *phydev; 2605 struct dsa_port *dp; 2606 2607 if (!mt753x_is_mac_port(port)) { 2608 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2609 return -EINVAL; 2610 } 2611 2612 switch (interface) { 2613 case PHY_INTERFACE_MODE_RGMII: 2614 case PHY_INTERFACE_MODE_RGMII_ID: 2615 case PHY_INTERFACE_MODE_RGMII_RXID: 2616 case PHY_INTERFACE_MODE_RGMII_TXID: 2617 dp = dsa_to_port(ds, port); 2618 phydev = dp->slave->phydev; 2619 return mt7531_rgmii_setup(priv, port, interface, phydev); 2620 case PHY_INTERFACE_MODE_SGMII: 2621 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2622 case PHY_INTERFACE_MODE_NA: 2623 case PHY_INTERFACE_MODE_1000BASEX: 2624 case PHY_INTERFACE_MODE_2500BASEX: 2625 if (phylink_autoneg_inband(mode)) 2626 return -EINVAL; 2627 2628 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2629 default: 2630 return -EINVAL; 2631 } 2632 2633 return -EINVAL; 2634 } 2635 2636 static int 2637 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2638 const struct phylink_link_state *state) 2639 { 2640 struct mt7530_priv *priv = ds->priv; 2641 2642 return priv->info->mac_port_config(ds, port, mode, state->interface); 2643 } 2644 2645 static void 2646 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2647 const struct phylink_link_state *state) 2648 { 2649 struct mt7530_priv *priv = ds->priv; 2650 u32 mcr_cur, mcr_new; 2651 2652 if (!mt753x_phy_mode_supported(ds, port, state)) 2653 goto unsupported; 2654 2655 switch (port) { 2656 case 0 ... 4: /* Internal phy */ 2657 if (state->interface != PHY_INTERFACE_MODE_GMII) 2658 goto unsupported; 2659 break; 2660 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2661 if (priv->p5_interface == state->interface) 2662 break; 2663 2664 if (mt753x_mac_config(ds, port, mode, state) < 0) 2665 goto unsupported; 2666 2667 if (priv->p5_intf_sel != P5_DISABLED) 2668 priv->p5_interface = state->interface; 2669 break; 2670 case 6: /* 1st cpu port */ 2671 if (priv->p6_interface == state->interface) 2672 break; 2673 2674 mt753x_pad_setup(ds, state); 2675 2676 if (mt753x_mac_config(ds, port, mode, state) < 0) 2677 goto unsupported; 2678 2679 priv->p6_interface = state->interface; 2680 break; 2681 default: 2682 unsupported: 2683 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2684 __func__, phy_modes(state->interface), port); 2685 return; 2686 } 2687 2688 if (phylink_autoneg_inband(mode) && 2689 state->interface != PHY_INTERFACE_MODE_SGMII) { 2690 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2691 __func__); 2692 return; 2693 } 2694 2695 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2696 mcr_new = mcr_cur; 2697 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2698 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2699 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2700 2701 /* Are we connected to external phy */ 2702 if (port == 5 && dsa_is_user_port(ds, 5)) 2703 mcr_new |= PMCR_EXT_PHY; 2704 2705 if (mcr_new != mcr_cur) 2706 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2707 } 2708 2709 static void 2710 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2711 { 2712 struct mt7530_priv *priv = ds->priv; 2713 2714 if (!priv->info->mac_pcs_an_restart) 2715 return; 2716 2717 priv->info->mac_pcs_an_restart(ds, port); 2718 } 2719 2720 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2721 unsigned int mode, 2722 phy_interface_t interface) 2723 { 2724 struct mt7530_priv *priv = ds->priv; 2725 2726 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2727 } 2728 2729 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2730 unsigned int mode, phy_interface_t interface, 2731 int speed, int duplex) 2732 { 2733 struct mt7530_priv *priv = ds->priv; 2734 2735 if (!priv->info->mac_pcs_link_up) 2736 return; 2737 2738 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2739 } 2740 2741 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2742 unsigned int mode, 2743 phy_interface_t interface, 2744 struct phy_device *phydev, 2745 int speed, int duplex, 2746 bool tx_pause, bool rx_pause) 2747 { 2748 struct mt7530_priv *priv = ds->priv; 2749 u32 mcr; 2750 2751 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2752 2753 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2754 2755 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2756 * variants. 2757 */ 2758 if (interface == PHY_INTERFACE_MODE_TRGMII || 2759 (phy_interface_mode_is_8023z(interface))) { 2760 speed = SPEED_1000; 2761 duplex = DUPLEX_FULL; 2762 } 2763 2764 switch (speed) { 2765 case SPEED_1000: 2766 mcr |= PMCR_FORCE_SPEED_1000; 2767 break; 2768 case SPEED_100: 2769 mcr |= PMCR_FORCE_SPEED_100; 2770 break; 2771 } 2772 if (duplex == DUPLEX_FULL) { 2773 mcr |= PMCR_FORCE_FDX; 2774 if (tx_pause) 2775 mcr |= PMCR_TX_FC_EN; 2776 if (rx_pause) 2777 mcr |= PMCR_RX_FC_EN; 2778 } 2779 2780 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) { 2781 switch (speed) { 2782 case SPEED_1000: 2783 mcr |= PMCR_FORCE_EEE1G; 2784 break; 2785 case SPEED_100: 2786 mcr |= PMCR_FORCE_EEE100; 2787 break; 2788 } 2789 } 2790 2791 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2792 } 2793 2794 static int 2795 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2796 { 2797 struct mt7530_priv *priv = ds->priv; 2798 phy_interface_t interface; 2799 int speed; 2800 int ret; 2801 2802 switch (port) { 2803 case 5: 2804 if (mt7531_is_rgmii_port(priv, port)) 2805 interface = PHY_INTERFACE_MODE_RGMII; 2806 else 2807 interface = PHY_INTERFACE_MODE_2500BASEX; 2808 2809 priv->p5_interface = interface; 2810 break; 2811 case 6: 2812 interface = PHY_INTERFACE_MODE_2500BASEX; 2813 2814 mt7531_pad_setup(ds, interface); 2815 2816 priv->p6_interface = interface; 2817 break; 2818 default: 2819 return -EINVAL; 2820 } 2821 2822 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2823 speed = SPEED_2500; 2824 else 2825 speed = SPEED_1000; 2826 2827 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2828 if (ret) 2829 return ret; 2830 mt7530_write(priv, MT7530_PMCR_P(port), 2831 PMCR_CPU_PORT_SETTING(priv->id)); 2832 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2833 speed, DUPLEX_FULL, true, true); 2834 2835 return 0; 2836 } 2837 2838 static void 2839 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2840 unsigned long *supported) 2841 { 2842 if (port == 5) 2843 phylink_set(supported, 1000baseX_Full); 2844 } 2845 2846 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2847 unsigned long *supported) 2848 { 2849 struct mt7530_priv *priv = ds->priv; 2850 2851 mt7531_sgmii_validate(priv, port, supported); 2852 } 2853 2854 static void 2855 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2856 unsigned long *supported, 2857 struct phylink_link_state *state) 2858 { 2859 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2860 struct mt7530_priv *priv = ds->priv; 2861 2862 if (state->interface != PHY_INTERFACE_MODE_NA && 2863 !mt753x_phy_mode_supported(ds, port, state)) { 2864 linkmode_zero(supported); 2865 return; 2866 } 2867 2868 phylink_set_port_modes(mask); 2869 2870 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2871 !phy_interface_mode_is_8023z(state->interface)) { 2872 phylink_set(mask, 10baseT_Half); 2873 phylink_set(mask, 10baseT_Full); 2874 phylink_set(mask, 100baseT_Half); 2875 phylink_set(mask, 100baseT_Full); 2876 phylink_set(mask, Autoneg); 2877 } 2878 2879 /* This switch only supports 1G full-duplex. */ 2880 if (state->interface != PHY_INTERFACE_MODE_MII) 2881 phylink_set(mask, 1000baseT_Full); 2882 2883 priv->info->mac_port_validate(ds, port, mask); 2884 2885 phylink_set(mask, Pause); 2886 phylink_set(mask, Asym_Pause); 2887 2888 linkmode_and(supported, supported, mask); 2889 linkmode_and(state->advertising, state->advertising, mask); 2890 2891 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2892 * to advertise both, only report advertising at 2500BaseX. 2893 */ 2894 phylink_helper_basex_speed(state); 2895 } 2896 2897 static int 2898 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2899 struct phylink_link_state *state) 2900 { 2901 struct mt7530_priv *priv = ds->priv; 2902 u32 pmsr; 2903 2904 if (port < 0 || port >= MT7530_NUM_PORTS) 2905 return -EINVAL; 2906 2907 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2908 2909 state->link = (pmsr & PMSR_LINK); 2910 state->an_complete = state->link; 2911 state->duplex = !!(pmsr & PMSR_DPX); 2912 2913 switch (pmsr & PMSR_SPEED_MASK) { 2914 case PMSR_SPEED_10: 2915 state->speed = SPEED_10; 2916 break; 2917 case PMSR_SPEED_100: 2918 state->speed = SPEED_100; 2919 break; 2920 case PMSR_SPEED_1000: 2921 state->speed = SPEED_1000; 2922 break; 2923 default: 2924 state->speed = SPEED_UNKNOWN; 2925 break; 2926 } 2927 2928 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2929 if (pmsr & PMSR_RX_FC) 2930 state->pause |= MLO_PAUSE_RX; 2931 if (pmsr & PMSR_TX_FC) 2932 state->pause |= MLO_PAUSE_TX; 2933 2934 return 1; 2935 } 2936 2937 static int 2938 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2939 struct phylink_link_state *state) 2940 { 2941 u32 status, val; 2942 u16 config_reg; 2943 2944 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2945 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2946 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2947 (status & MT7531_SGMII_AN_ENABLE)) { 2948 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2949 config_reg = val >> 16; 2950 2951 switch (config_reg & LPA_SGMII_SPD_MASK) { 2952 case LPA_SGMII_1000: 2953 state->speed = SPEED_1000; 2954 break; 2955 case LPA_SGMII_100: 2956 state->speed = SPEED_100; 2957 break; 2958 case LPA_SGMII_10: 2959 state->speed = SPEED_10; 2960 break; 2961 default: 2962 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2963 state->link = false; 2964 return -EINVAL; 2965 } 2966 2967 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2968 state->duplex = DUPLEX_FULL; 2969 else 2970 state->duplex = DUPLEX_HALF; 2971 } 2972 2973 return 0; 2974 } 2975 2976 static int 2977 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 2978 struct phylink_link_state *state) 2979 { 2980 struct mt7530_priv *priv = ds->priv; 2981 2982 if (state->interface == PHY_INTERFACE_MODE_SGMII) 2983 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 2984 2985 return -EOPNOTSUPP; 2986 } 2987 2988 static int 2989 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 2990 struct phylink_link_state *state) 2991 { 2992 struct mt7530_priv *priv = ds->priv; 2993 2994 return priv->info->mac_port_get_state(ds, port, state); 2995 } 2996 2997 static int 2998 mt753x_setup(struct dsa_switch *ds) 2999 { 3000 struct mt7530_priv *priv = ds->priv; 3001 int ret = priv->info->sw_setup(ds); 3002 3003 if (ret) 3004 return ret; 3005 3006 ret = mt7530_setup_irq(priv); 3007 if (ret) 3008 return ret; 3009 3010 ret = mt7530_setup_mdio(priv); 3011 if (ret && priv->irq) 3012 mt7530_free_irq_common(priv); 3013 3014 return ret; 3015 } 3016 3017 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3018 struct ethtool_eee *e) 3019 { 3020 struct mt7530_priv *priv = ds->priv; 3021 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3022 3023 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3024 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3025 3026 return 0; 3027 } 3028 3029 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3030 struct ethtool_eee *e) 3031 { 3032 struct mt7530_priv *priv = ds->priv; 3033 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3034 3035 if (e->tx_lpi_timer > 0xFFF) 3036 return -EINVAL; 3037 3038 set = SET_LPI_THRESH(e->tx_lpi_timer); 3039 if (!e->tx_lpi_enabled) 3040 /* Force LPI Mode without a delay */ 3041 set |= LPI_MODE_EN; 3042 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3043 3044 return 0; 3045 } 3046 3047 static const struct dsa_switch_ops mt7530_switch_ops = { 3048 .get_tag_protocol = mtk_get_tag_protocol, 3049 .setup = mt753x_setup, 3050 .get_strings = mt7530_get_strings, 3051 .get_ethtool_stats = mt7530_get_ethtool_stats, 3052 .get_sset_count = mt7530_get_sset_count, 3053 .set_ageing_time = mt7530_set_ageing_time, 3054 .port_enable = mt7530_port_enable, 3055 .port_disable = mt7530_port_disable, 3056 .port_change_mtu = mt7530_port_change_mtu, 3057 .port_max_mtu = mt7530_port_max_mtu, 3058 .port_stp_state_set = mt7530_stp_state_set, 3059 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3060 .port_bridge_flags = mt7530_port_bridge_flags, 3061 .port_set_mrouter = mt7530_port_set_mrouter, 3062 .port_bridge_join = mt7530_port_bridge_join, 3063 .port_bridge_leave = mt7530_port_bridge_leave, 3064 .port_fdb_add = mt7530_port_fdb_add, 3065 .port_fdb_del = mt7530_port_fdb_del, 3066 .port_fdb_dump = mt7530_port_fdb_dump, 3067 .port_mdb_add = mt7530_port_mdb_add, 3068 .port_mdb_del = mt7530_port_mdb_del, 3069 .port_vlan_filtering = mt7530_port_vlan_filtering, 3070 .port_vlan_add = mt7530_port_vlan_add, 3071 .port_vlan_del = mt7530_port_vlan_del, 3072 .port_mirror_add = mt753x_port_mirror_add, 3073 .port_mirror_del = mt753x_port_mirror_del, 3074 .phylink_validate = mt753x_phylink_validate, 3075 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 3076 .phylink_mac_config = mt753x_phylink_mac_config, 3077 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 3078 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3079 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3080 .get_mac_eee = mt753x_get_mac_eee, 3081 .set_mac_eee = mt753x_set_mac_eee, 3082 }; 3083 3084 static const struct mt753x_info mt753x_table[] = { 3085 [ID_MT7621] = { 3086 .id = ID_MT7621, 3087 .sw_setup = mt7530_setup, 3088 .phy_read = mt7530_phy_read, 3089 .phy_write = mt7530_phy_write, 3090 .pad_setup = mt7530_pad_clk_setup, 3091 .phy_mode_supported = mt7530_phy_mode_supported, 3092 .mac_port_validate = mt7530_mac_port_validate, 3093 .mac_port_get_state = mt7530_phylink_mac_link_state, 3094 .mac_port_config = mt7530_mac_config, 3095 }, 3096 [ID_MT7530] = { 3097 .id = ID_MT7530, 3098 .sw_setup = mt7530_setup, 3099 .phy_read = mt7530_phy_read, 3100 .phy_write = mt7530_phy_write, 3101 .pad_setup = mt7530_pad_clk_setup, 3102 .phy_mode_supported = mt7530_phy_mode_supported, 3103 .mac_port_validate = mt7530_mac_port_validate, 3104 .mac_port_get_state = mt7530_phylink_mac_link_state, 3105 .mac_port_config = mt7530_mac_config, 3106 }, 3107 [ID_MT7531] = { 3108 .id = ID_MT7531, 3109 .sw_setup = mt7531_setup, 3110 .phy_read = mt7531_ind_phy_read, 3111 .phy_write = mt7531_ind_phy_write, 3112 .pad_setup = mt7531_pad_setup, 3113 .cpu_port_config = mt7531_cpu_port_config, 3114 .phy_mode_supported = mt7531_phy_mode_supported, 3115 .mac_port_validate = mt7531_mac_port_validate, 3116 .mac_port_get_state = mt7531_phylink_mac_link_state, 3117 .mac_port_config = mt7531_mac_config, 3118 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 3119 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 3120 }, 3121 }; 3122 3123 static const struct of_device_id mt7530_of_match[] = { 3124 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3125 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3126 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3127 { /* sentinel */ }, 3128 }; 3129 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3130 3131 static int 3132 mt7530_probe(struct mdio_device *mdiodev) 3133 { 3134 struct mt7530_priv *priv; 3135 struct device_node *dn; 3136 3137 dn = mdiodev->dev.of_node; 3138 3139 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3140 if (!priv) 3141 return -ENOMEM; 3142 3143 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3144 if (!priv->ds) 3145 return -ENOMEM; 3146 3147 priv->ds->dev = &mdiodev->dev; 3148 priv->ds->num_ports = DSA_MAX_PORTS; 3149 3150 /* Use medatek,mcm property to distinguish hardware type that would 3151 * casues a little bit differences on power-on sequence. 3152 */ 3153 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3154 if (priv->mcm) { 3155 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3156 3157 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3158 if (IS_ERR(priv->rstc)) { 3159 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3160 return PTR_ERR(priv->rstc); 3161 } 3162 } 3163 3164 /* Get the hardware identifier from the devicetree node. 3165 * We will need it for some of the clock and regulator setup. 3166 */ 3167 priv->info = of_device_get_match_data(&mdiodev->dev); 3168 if (!priv->info) 3169 return -EINVAL; 3170 3171 /* Sanity check if these required device operations are filled 3172 * properly. 3173 */ 3174 if (!priv->info->sw_setup || !priv->info->pad_setup || 3175 !priv->info->phy_read || !priv->info->phy_write || 3176 !priv->info->phy_mode_supported || 3177 !priv->info->mac_port_validate || 3178 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 3179 return -EINVAL; 3180 3181 priv->id = priv->info->id; 3182 3183 if (priv->id == ID_MT7530) { 3184 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3185 if (IS_ERR(priv->core_pwr)) 3186 return PTR_ERR(priv->core_pwr); 3187 3188 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3189 if (IS_ERR(priv->io_pwr)) 3190 return PTR_ERR(priv->io_pwr); 3191 } 3192 3193 /* Not MCM that indicates switch works as the remote standalone 3194 * integrated circuit so the GPIO pin would be used to complete 3195 * the reset, otherwise memory-mapped register accessing used 3196 * through syscon provides in the case of MCM. 3197 */ 3198 if (!priv->mcm) { 3199 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3200 GPIOD_OUT_LOW); 3201 if (IS_ERR(priv->reset)) { 3202 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3203 return PTR_ERR(priv->reset); 3204 } 3205 } 3206 3207 priv->bus = mdiodev->bus; 3208 priv->dev = &mdiodev->dev; 3209 priv->ds->priv = priv; 3210 priv->ds->ops = &mt7530_switch_ops; 3211 mutex_init(&priv->reg_mutex); 3212 dev_set_drvdata(&mdiodev->dev, priv); 3213 3214 return dsa_register_switch(priv->ds); 3215 } 3216 3217 static void 3218 mt7530_remove(struct mdio_device *mdiodev) 3219 { 3220 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3221 int ret = 0; 3222 3223 ret = regulator_disable(priv->core_pwr); 3224 if (ret < 0) 3225 dev_err(priv->dev, 3226 "Failed to disable core power: %d\n", ret); 3227 3228 ret = regulator_disable(priv->io_pwr); 3229 if (ret < 0) 3230 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3231 ret); 3232 3233 if (priv->irq) 3234 mt7530_free_irq(priv); 3235 3236 dsa_unregister_switch(priv->ds); 3237 mutex_destroy(&priv->reg_mutex); 3238 } 3239 3240 static struct mdio_driver mt7530_mdio_driver = { 3241 .probe = mt7530_probe, 3242 .remove = mt7530_remove, 3243 .mdiodrv.driver = { 3244 .name = "mt7530", 3245 .of_match_table = mt7530_of_match, 3246 }, 3247 }; 3248 3249 mdio_module_driver(mt7530_mdio_driver); 3250 3251 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3252 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3253 MODULE_LICENSE("GPL"); 3254