1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 146 { 147 struct mii_bus *bus = priv->bus; 148 149 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 150 151 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 152 153 mutex_unlock(&bus->mdio_lock); 154 } 155 156 static void 157 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 158 { 159 struct mii_bus *bus = priv->bus; 160 u32 val; 161 162 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 163 164 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 165 val &= ~mask; 166 val |= set; 167 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 168 169 mutex_unlock(&bus->mdio_lock); 170 } 171 172 static void 173 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, 0, val); 176 } 177 178 static void 179 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 core_rmw(priv, reg, val, 0); 182 } 183 184 static int 185 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 186 { 187 struct mii_bus *bus = priv->bus; 188 u16 page, r, lo, hi; 189 int ret; 190 191 page = (reg >> 6) & 0x3ff; 192 r = (reg >> 2) & 0xf; 193 lo = val & 0xffff; 194 hi = val >> 16; 195 196 /* MT7530 uses 31 as the pseudo port */ 197 ret = bus->write(bus, 0x1f, 0x1f, page); 198 if (ret < 0) 199 goto err; 200 201 ret = bus->write(bus, 0x1f, r, lo); 202 if (ret < 0) 203 goto err; 204 205 ret = bus->write(bus, 0x1f, 0x10, hi); 206 err: 207 if (ret < 0) 208 dev_err(&bus->dev, 209 "failed to write mt7530 register\n"); 210 return ret; 211 } 212 213 static u32 214 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 215 { 216 struct mii_bus *bus = priv->bus; 217 u16 page, r, lo, hi; 218 int ret; 219 220 page = (reg >> 6) & 0x3ff; 221 r = (reg >> 2) & 0xf; 222 223 /* MT7530 uses 31 as the pseudo port */ 224 ret = bus->write(bus, 0x1f, 0x1f, page); 225 if (ret < 0) { 226 dev_err(&bus->dev, 227 "failed to read mt7530 register\n"); 228 return ret; 229 } 230 231 lo = bus->read(bus, 0x1f, r); 232 hi = bus->read(bus, 0x1f, 0x10); 233 234 return (hi << 16) | (lo & 0xffff); 235 } 236 237 static void 238 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 239 { 240 struct mii_bus *bus = priv->bus; 241 242 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 243 244 mt7530_mii_write(priv, reg, val); 245 246 mutex_unlock(&bus->mdio_lock); 247 } 248 249 static u32 250 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 251 { 252 return mt7530_mii_read(p->priv, p->reg); 253 } 254 255 static u32 256 _mt7530_read(struct mt7530_dummy_poll *p) 257 { 258 struct mii_bus *bus = p->priv->bus; 259 u32 val; 260 261 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 262 263 val = mt7530_mii_read(p->priv, p->reg); 264 265 mutex_unlock(&bus->mdio_lock); 266 267 return val; 268 } 269 270 static u32 271 mt7530_read(struct mt7530_priv *priv, u32 reg) 272 { 273 struct mt7530_dummy_poll p; 274 275 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 276 return _mt7530_read(&p); 277 } 278 279 static void 280 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 281 u32 mask, u32 set) 282 { 283 struct mii_bus *bus = priv->bus; 284 u32 val; 285 286 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 287 288 val = mt7530_mii_read(priv, reg); 289 val &= ~mask; 290 val |= set; 291 mt7530_mii_write(priv, reg, val); 292 293 mutex_unlock(&bus->mdio_lock); 294 } 295 296 static void 297 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, 0, val); 300 } 301 302 static void 303 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 304 { 305 mt7530_rmw(priv, reg, val, 0); 306 } 307 308 static int 309 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 310 { 311 u32 val; 312 int ret; 313 struct mt7530_dummy_poll p; 314 315 /* Set the command operating upon the MAC address entries */ 316 val = ATC_BUSY | ATC_MAT(0) | cmd; 317 mt7530_write(priv, MT7530_ATC, val); 318 319 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 320 ret = readx_poll_timeout(_mt7530_read, &p, val, 321 !(val & ATC_BUSY), 20, 20000); 322 if (ret < 0) { 323 dev_err(priv->dev, "reset timeout\n"); 324 return ret; 325 } 326 327 /* Additional sanity for read command if the specified 328 * entry is invalid 329 */ 330 val = mt7530_read(priv, MT7530_ATC); 331 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 332 return -EINVAL; 333 334 if (rsp) 335 *rsp = val; 336 337 return 0; 338 } 339 340 static void 341 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 342 { 343 u32 reg[3]; 344 int i; 345 346 /* Read from ARL table into an array */ 347 for (i = 0; i < 3; i++) { 348 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 349 350 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 351 __func__, __LINE__, i, reg[i]); 352 } 353 354 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 355 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 356 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 357 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 358 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 359 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 360 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 361 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 362 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 363 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 364 } 365 366 static void 367 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 368 u8 port_mask, const u8 *mac, 369 u8 aging, u8 type) 370 { 371 u32 reg[3] = { 0 }; 372 int i; 373 374 reg[1] |= vid & CVID_MASK; 375 reg[1] |= ATA2_IVL; 376 reg[1] |= ATA2_FID(FID_BRIDGED); 377 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 378 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 379 /* STATIC_ENT indicate that entry is static wouldn't 380 * be aged out and STATIC_EMP specified as erasing an 381 * entry 382 */ 383 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 384 reg[1] |= mac[5] << MAC_BYTE_5; 385 reg[1] |= mac[4] << MAC_BYTE_4; 386 reg[0] |= mac[3] << MAC_BYTE_3; 387 reg[0] |= mac[2] << MAC_BYTE_2; 388 reg[0] |= mac[1] << MAC_BYTE_1; 389 reg[0] |= mac[0] << MAC_BYTE_0; 390 391 /* Write array into the ARL table */ 392 for (i = 0; i < 3; i++) 393 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 394 } 395 396 /* Setup TX circuit including relevant PAD and driving */ 397 static int 398 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 399 { 400 struct mt7530_priv *priv = ds->priv; 401 u32 ncpo1, ssc_delta, trgint, i, xtal; 402 403 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 404 405 if (xtal == HWTRAP_XTAL_20MHZ) { 406 dev_err(priv->dev, 407 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 408 __func__); 409 return -EINVAL; 410 } 411 412 switch (interface) { 413 case PHY_INTERFACE_MODE_RGMII: 414 trgint = 0; 415 /* PLL frequency: 125MHz */ 416 ncpo1 = 0x0c80; 417 break; 418 case PHY_INTERFACE_MODE_TRGMII: 419 trgint = 1; 420 if (priv->id == ID_MT7621) { 421 /* PLL frequency: 150MHz: 1.2GBit */ 422 if (xtal == HWTRAP_XTAL_40MHZ) 423 ncpo1 = 0x0780; 424 if (xtal == HWTRAP_XTAL_25MHZ) 425 ncpo1 = 0x0a00; 426 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 427 if (xtal == HWTRAP_XTAL_40MHZ) 428 ncpo1 = 0x0c80; 429 if (xtal == HWTRAP_XTAL_25MHZ) 430 ncpo1 = 0x1400; 431 } 432 break; 433 default: 434 dev_err(priv->dev, "xMII interface %d not supported\n", 435 interface); 436 return -EINVAL; 437 } 438 439 if (xtal == HWTRAP_XTAL_25MHZ) 440 ssc_delta = 0x57; 441 else 442 ssc_delta = 0x87; 443 444 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 445 P6_INTF_MODE(trgint)); 446 447 /* Lower Tx Driving for TRGMII path */ 448 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 449 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 450 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 451 452 /* Disable MT7530 core and TRGMII Tx clocks */ 453 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 454 REG_GSWCK_EN | REG_TRGMIICK_EN); 455 456 /* Setup core clock for MT7530 */ 457 /* Disable PLL */ 458 core_write(priv, CORE_GSWPLL_GRP1, 0); 459 460 /* Set core clock into 500Mhz */ 461 core_write(priv, CORE_GSWPLL_GRP2, 462 RG_GSWPLL_POSDIV_500M(1) | 463 RG_GSWPLL_FBKDIV_500M(25)); 464 465 /* Enable PLL */ 466 core_write(priv, CORE_GSWPLL_GRP1, 467 RG_GSWPLL_EN_PRE | 468 RG_GSWPLL_POSDIV_200M(2) | 469 RG_GSWPLL_FBKDIV_200M(32)); 470 471 /* Setup the MT7530 TRGMII Tx Clock */ 472 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 473 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 474 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 475 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 476 core_write(priv, CORE_PLL_GROUP4, 477 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 478 RG_SYSPLL_BIAS_LPF_EN); 479 core_write(priv, CORE_PLL_GROUP2, 480 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 481 RG_SYSPLL_POSDIV(1)); 482 core_write(priv, CORE_PLL_GROUP7, 483 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 484 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 485 486 /* Enable MT7530 core and TRGMII Tx clocks */ 487 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 488 REG_GSWCK_EN | REG_TRGMIICK_EN); 489 490 if (!trgint) 491 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 492 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 493 RD_TAP_MASK, RD_TAP(16)); 494 return 0; 495 } 496 497 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 498 { 499 u32 val; 500 501 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 502 503 return (val & PAD_DUAL_SGMII_EN) != 0; 504 } 505 506 static int 507 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 508 { 509 return 0; 510 } 511 512 static void 513 mt7531_pll_setup(struct mt7530_priv *priv) 514 { 515 u32 top_sig; 516 u32 hwstrap; 517 u32 xtal; 518 u32 val; 519 520 if (mt7531_dual_sgmii_supported(priv)) 521 return; 522 523 val = mt7530_read(priv, MT7531_CREV); 524 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 525 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 526 if ((val & CHIP_REV_M) > 0) 527 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 528 HWTRAP_XTAL_FSEL_25MHZ; 529 else 530 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 531 532 /* Step 1 : Disable MT7531 COREPLL */ 533 val = mt7530_read(priv, MT7531_PLLGP_EN); 534 val &= ~EN_COREPLL; 535 mt7530_write(priv, MT7531_PLLGP_EN, val); 536 537 /* Step 2: switch to XTAL output */ 538 val = mt7530_read(priv, MT7531_PLLGP_EN); 539 val |= SW_CLKSW; 540 mt7530_write(priv, MT7531_PLLGP_EN, val); 541 542 val = mt7530_read(priv, MT7531_PLLGP_CR0); 543 val &= ~RG_COREPLL_EN; 544 mt7530_write(priv, MT7531_PLLGP_CR0, val); 545 546 /* Step 3: disable PLLGP and enable program PLLGP */ 547 val = mt7530_read(priv, MT7531_PLLGP_EN); 548 val |= SW_PLLGP; 549 mt7530_write(priv, MT7531_PLLGP_EN, val); 550 551 /* Step 4: program COREPLL output frequency to 500MHz */ 552 val = mt7530_read(priv, MT7531_PLLGP_CR0); 553 val &= ~RG_COREPLL_POSDIV_M; 554 val |= 2 << RG_COREPLL_POSDIV_S; 555 mt7530_write(priv, MT7531_PLLGP_CR0, val); 556 usleep_range(25, 35); 557 558 switch (xtal) { 559 case HWTRAP_XTAL_FSEL_25MHZ: 560 val = mt7530_read(priv, MT7531_PLLGP_CR0); 561 val &= ~RG_COREPLL_SDM_PCW_M; 562 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 563 mt7530_write(priv, MT7531_PLLGP_CR0, val); 564 break; 565 case HWTRAP_XTAL_FSEL_40MHZ: 566 val = mt7530_read(priv, MT7531_PLLGP_CR0); 567 val &= ~RG_COREPLL_SDM_PCW_M; 568 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 569 mt7530_write(priv, MT7531_PLLGP_CR0, val); 570 break; 571 } 572 573 /* Set feedback divide ratio update signal to high */ 574 val = mt7530_read(priv, MT7531_PLLGP_CR0); 575 val |= RG_COREPLL_SDM_PCW_CHG; 576 mt7530_write(priv, MT7531_PLLGP_CR0, val); 577 /* Wait for at least 16 XTAL clocks */ 578 usleep_range(10, 20); 579 580 /* Step 5: set feedback divide ratio update signal to low */ 581 val = mt7530_read(priv, MT7531_PLLGP_CR0); 582 val &= ~RG_COREPLL_SDM_PCW_CHG; 583 mt7530_write(priv, MT7531_PLLGP_CR0, val); 584 585 /* Enable 325M clock for SGMII */ 586 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 587 588 /* Enable 250SSC clock for RGMII */ 589 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 590 591 /* Step 6: Enable MT7531 PLL */ 592 val = mt7530_read(priv, MT7531_PLLGP_CR0); 593 val |= RG_COREPLL_EN; 594 mt7530_write(priv, MT7531_PLLGP_CR0, val); 595 596 val = mt7530_read(priv, MT7531_PLLGP_EN); 597 val |= EN_COREPLL; 598 mt7530_write(priv, MT7531_PLLGP_EN, val); 599 usleep_range(25, 35); 600 } 601 602 static void 603 mt7530_mib_reset(struct dsa_switch *ds) 604 { 605 struct mt7530_priv *priv = ds->priv; 606 607 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 608 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 609 } 610 611 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 612 { 613 return mdiobus_read_nested(priv->bus, port, regnum); 614 } 615 616 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 617 u16 val) 618 { 619 return mdiobus_write_nested(priv->bus, port, regnum, val); 620 } 621 622 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 623 int devad, int regnum) 624 { 625 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 626 } 627 628 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 629 int regnum, u16 val) 630 { 631 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 632 } 633 634 static int 635 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 636 int regnum) 637 { 638 struct mii_bus *bus = priv->bus; 639 struct mt7530_dummy_poll p; 640 u32 reg, val; 641 int ret; 642 643 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 644 645 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 646 647 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 648 !(val & MT7531_PHY_ACS_ST), 20, 100000); 649 if (ret < 0) { 650 dev_err(priv->dev, "poll timeout\n"); 651 goto out; 652 } 653 654 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 655 MT7531_MDIO_DEV_ADDR(devad) | regnum; 656 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 657 658 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 659 !(val & MT7531_PHY_ACS_ST), 20, 100000); 660 if (ret < 0) { 661 dev_err(priv->dev, "poll timeout\n"); 662 goto out; 663 } 664 665 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 666 MT7531_MDIO_DEV_ADDR(devad); 667 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 668 669 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 670 !(val & MT7531_PHY_ACS_ST), 20, 100000); 671 if (ret < 0) { 672 dev_err(priv->dev, "poll timeout\n"); 673 goto out; 674 } 675 676 ret = val & MT7531_MDIO_RW_DATA_MASK; 677 out: 678 mutex_unlock(&bus->mdio_lock); 679 680 return ret; 681 } 682 683 static int 684 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 685 int regnum, u16 data) 686 { 687 struct mii_bus *bus = priv->bus; 688 struct mt7530_dummy_poll p; 689 u32 val, reg; 690 int ret; 691 692 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 693 694 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 695 696 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 697 !(val & MT7531_PHY_ACS_ST), 20, 100000); 698 if (ret < 0) { 699 dev_err(priv->dev, "poll timeout\n"); 700 goto out; 701 } 702 703 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 704 MT7531_MDIO_DEV_ADDR(devad) | regnum; 705 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 706 707 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 708 !(val & MT7531_PHY_ACS_ST), 20, 100000); 709 if (ret < 0) { 710 dev_err(priv->dev, "poll timeout\n"); 711 goto out; 712 } 713 714 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 715 MT7531_MDIO_DEV_ADDR(devad) | data; 716 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 717 718 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 719 !(val & MT7531_PHY_ACS_ST), 20, 100000); 720 if (ret < 0) { 721 dev_err(priv->dev, "poll timeout\n"); 722 goto out; 723 } 724 725 out: 726 mutex_unlock(&bus->mdio_lock); 727 728 return ret; 729 } 730 731 static int 732 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 733 { 734 struct mii_bus *bus = priv->bus; 735 struct mt7530_dummy_poll p; 736 int ret; 737 u32 val; 738 739 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 740 741 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 742 743 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 744 !(val & MT7531_PHY_ACS_ST), 20, 100000); 745 if (ret < 0) { 746 dev_err(priv->dev, "poll timeout\n"); 747 goto out; 748 } 749 750 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 751 MT7531_MDIO_REG_ADDR(regnum); 752 753 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 754 755 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 756 !(val & MT7531_PHY_ACS_ST), 20, 100000); 757 if (ret < 0) { 758 dev_err(priv->dev, "poll timeout\n"); 759 goto out; 760 } 761 762 ret = val & MT7531_MDIO_RW_DATA_MASK; 763 out: 764 mutex_unlock(&bus->mdio_lock); 765 766 return ret; 767 } 768 769 static int 770 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 771 u16 data) 772 { 773 struct mii_bus *bus = priv->bus; 774 struct mt7530_dummy_poll p; 775 int ret; 776 u32 reg; 777 778 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 779 780 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 781 782 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 783 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 784 if (ret < 0) { 785 dev_err(priv->dev, "poll timeout\n"); 786 goto out; 787 } 788 789 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 790 MT7531_MDIO_REG_ADDR(regnum) | data; 791 792 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 793 794 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 795 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 796 if (ret < 0) { 797 dev_err(priv->dev, "poll timeout\n"); 798 goto out; 799 } 800 801 out: 802 mutex_unlock(&bus->mdio_lock); 803 804 return ret; 805 } 806 807 static int 808 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 809 { 810 struct mt7530_priv *priv = bus->priv; 811 812 return priv->info->phy_read_c22(priv, port, regnum); 813 } 814 815 static int 816 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 817 { 818 struct mt7530_priv *priv = bus->priv; 819 820 return priv->info->phy_read_c45(priv, port, devad, regnum); 821 } 822 823 static int 824 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 825 { 826 struct mt7530_priv *priv = bus->priv; 827 828 return priv->info->phy_write_c22(priv, port, regnum, val); 829 } 830 831 static int 832 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 833 u16 val) 834 { 835 struct mt7530_priv *priv = bus->priv; 836 837 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 838 } 839 840 static void 841 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 842 uint8_t *data) 843 { 844 int i; 845 846 if (stringset != ETH_SS_STATS) 847 return; 848 849 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 850 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 851 ETH_GSTRING_LEN); 852 } 853 854 static void 855 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 856 uint64_t *data) 857 { 858 struct mt7530_priv *priv = ds->priv; 859 const struct mt7530_mib_desc *mib; 860 u32 reg, i; 861 u64 hi; 862 863 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 864 mib = &mt7530_mib[i]; 865 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 866 867 data[i] = mt7530_read(priv, reg); 868 if (mib->size == 2) { 869 hi = mt7530_read(priv, reg + 4); 870 data[i] |= hi << 32; 871 } 872 } 873 } 874 875 static int 876 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 877 { 878 if (sset != ETH_SS_STATS) 879 return 0; 880 881 return ARRAY_SIZE(mt7530_mib); 882 } 883 884 static int 885 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 886 { 887 struct mt7530_priv *priv = ds->priv; 888 unsigned int secs = msecs / 1000; 889 unsigned int tmp_age_count; 890 unsigned int error = -1; 891 unsigned int age_count; 892 unsigned int age_unit; 893 894 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 895 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 896 return -ERANGE; 897 898 /* iterate through all possible age_count to find the closest pair */ 899 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 900 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 901 902 if (tmp_age_unit <= AGE_UNIT_MAX) { 903 unsigned int tmp_error = secs - 904 (tmp_age_count + 1) * (tmp_age_unit + 1); 905 906 /* found a closer pair */ 907 if (error > tmp_error) { 908 error = tmp_error; 909 age_count = tmp_age_count; 910 age_unit = tmp_age_unit; 911 } 912 913 /* found the exact match, so break the loop */ 914 if (!error) 915 break; 916 } 917 } 918 919 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 920 921 return 0; 922 } 923 924 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 925 { 926 struct mt7530_priv *priv = ds->priv; 927 u8 tx_delay = 0; 928 int val; 929 930 mutex_lock(&priv->reg_mutex); 931 932 val = mt7530_read(priv, MT7530_MHWTRAP); 933 934 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 935 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 936 937 switch (priv->p5_intf_sel) { 938 case P5_INTF_SEL_PHY_P0: 939 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 940 val |= MHWTRAP_PHY0_SEL; 941 fallthrough; 942 case P5_INTF_SEL_PHY_P4: 943 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 944 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 945 946 /* Setup the MAC by default for the cpu port */ 947 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 948 break; 949 case P5_INTF_SEL_GMAC5: 950 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 951 val &= ~MHWTRAP_P5_DIS; 952 break; 953 case P5_DISABLED: 954 interface = PHY_INTERFACE_MODE_NA; 955 break; 956 default: 957 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 958 priv->p5_intf_sel); 959 goto unlock_exit; 960 } 961 962 /* Setup RGMII settings */ 963 if (phy_interface_mode_is_rgmii(interface)) { 964 val |= MHWTRAP_P5_RGMII_MODE; 965 966 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 967 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 968 969 /* Don't set delay in DSA mode */ 970 if (!dsa_is_dsa_port(priv->ds, 5) && 971 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 972 interface == PHY_INTERFACE_MODE_RGMII_ID)) 973 tx_delay = 4; /* n * 0.5 ns */ 974 975 /* P5 RGMII TX Clock Control: delay x */ 976 mt7530_write(priv, MT7530_P5RGMIITXCR, 977 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 978 979 /* reduce P5 RGMII Tx driving, 8mA */ 980 mt7530_write(priv, MT7530_IO_DRV_CR, 981 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 982 } 983 984 mt7530_write(priv, MT7530_MHWTRAP, val); 985 986 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 987 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 988 989 priv->p5_interface = interface; 990 991 unlock_exit: 992 mutex_unlock(&priv->reg_mutex); 993 } 994 995 static int 996 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 997 { 998 struct mt7530_priv *priv = ds->priv; 999 int ret; 1000 1001 /* Setup max capability of CPU port at first */ 1002 if (priv->info->cpu_port_config) { 1003 ret = priv->info->cpu_port_config(ds, port); 1004 if (ret) 1005 return ret; 1006 } 1007 1008 /* Enable Mediatek header mode on the cpu port */ 1009 mt7530_write(priv, MT7530_PVC_P(port), 1010 PORT_SPEC_TAG); 1011 1012 /* Disable flooding by default */ 1013 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1014 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1015 1016 /* Set CPU port number */ 1017 if (priv->id == ID_MT7621) 1018 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1019 1020 /* CPU port gets connected to all user ports of 1021 * the switch. 1022 */ 1023 mt7530_write(priv, MT7530_PCR_P(port), 1024 PCR_MATRIX(dsa_user_ports(priv->ds))); 1025 1026 /* Set to fallback mode for independent VLAN learning */ 1027 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1028 MT7530_PORT_FALLBACK_MODE); 1029 1030 return 0; 1031 } 1032 1033 static int 1034 mt7530_port_enable(struct dsa_switch *ds, int port, 1035 struct phy_device *phy) 1036 { 1037 struct dsa_port *dp = dsa_to_port(ds, port); 1038 struct mt7530_priv *priv = ds->priv; 1039 1040 mutex_lock(&priv->reg_mutex); 1041 1042 /* Allow the user port gets connected to the cpu port and also 1043 * restore the port matrix if the port is the member of a certain 1044 * bridge. 1045 */ 1046 if (dsa_port_is_user(dp)) { 1047 struct dsa_port *cpu_dp = dp->cpu_dp; 1048 1049 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1050 } 1051 priv->ports[port].enable = true; 1052 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1053 priv->ports[port].pm); 1054 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1055 1056 mutex_unlock(&priv->reg_mutex); 1057 1058 return 0; 1059 } 1060 1061 static void 1062 mt7530_port_disable(struct dsa_switch *ds, int port) 1063 { 1064 struct mt7530_priv *priv = ds->priv; 1065 1066 mutex_lock(&priv->reg_mutex); 1067 1068 /* Clear up all port matrix which could be restored in the next 1069 * enablement for the port. 1070 */ 1071 priv->ports[port].enable = false; 1072 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1073 PCR_MATRIX_CLR); 1074 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1075 1076 mutex_unlock(&priv->reg_mutex); 1077 } 1078 1079 static int 1080 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1081 { 1082 struct mt7530_priv *priv = ds->priv; 1083 struct mii_bus *bus = priv->bus; 1084 int length; 1085 u32 val; 1086 1087 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1088 * largest MTU of the slave ports. Because the switch only has a global 1089 * RX length register, only allowing CPU port here is enough. 1090 */ 1091 if (!dsa_is_cpu_port(ds, port)) 1092 return 0; 1093 1094 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1095 1096 val = mt7530_mii_read(priv, MT7530_GMACCR); 1097 val &= ~MAX_RX_PKT_LEN_MASK; 1098 1099 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1100 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1101 if (length <= 1522) { 1102 val |= MAX_RX_PKT_LEN_1522; 1103 } else if (length <= 1536) { 1104 val |= MAX_RX_PKT_LEN_1536; 1105 } else if (length <= 1552) { 1106 val |= MAX_RX_PKT_LEN_1552; 1107 } else { 1108 val &= ~MAX_RX_JUMBO_MASK; 1109 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1110 val |= MAX_RX_PKT_LEN_JUMBO; 1111 } 1112 1113 mt7530_mii_write(priv, MT7530_GMACCR, val); 1114 1115 mutex_unlock(&bus->mdio_lock); 1116 1117 return 0; 1118 } 1119 1120 static int 1121 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1122 { 1123 return MT7530_MAX_MTU; 1124 } 1125 1126 static void 1127 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1128 { 1129 struct mt7530_priv *priv = ds->priv; 1130 u32 stp_state; 1131 1132 switch (state) { 1133 case BR_STATE_DISABLED: 1134 stp_state = MT7530_STP_DISABLED; 1135 break; 1136 case BR_STATE_BLOCKING: 1137 stp_state = MT7530_STP_BLOCKING; 1138 break; 1139 case BR_STATE_LISTENING: 1140 stp_state = MT7530_STP_LISTENING; 1141 break; 1142 case BR_STATE_LEARNING: 1143 stp_state = MT7530_STP_LEARNING; 1144 break; 1145 case BR_STATE_FORWARDING: 1146 default: 1147 stp_state = MT7530_STP_FORWARDING; 1148 break; 1149 } 1150 1151 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1152 FID_PST(FID_BRIDGED, stp_state)); 1153 } 1154 1155 static int 1156 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1157 struct switchdev_brport_flags flags, 1158 struct netlink_ext_ack *extack) 1159 { 1160 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1161 BR_BCAST_FLOOD)) 1162 return -EINVAL; 1163 1164 return 0; 1165 } 1166 1167 static int 1168 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1169 struct switchdev_brport_flags flags, 1170 struct netlink_ext_ack *extack) 1171 { 1172 struct mt7530_priv *priv = ds->priv; 1173 1174 if (flags.mask & BR_LEARNING) 1175 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1176 flags.val & BR_LEARNING ? 0 : SA_DIS); 1177 1178 if (flags.mask & BR_FLOOD) 1179 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1180 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1181 1182 if (flags.mask & BR_MCAST_FLOOD) 1183 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1184 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1185 1186 if (flags.mask & BR_BCAST_FLOOD) 1187 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1188 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1189 1190 return 0; 1191 } 1192 1193 static int 1194 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1195 struct dsa_bridge bridge, bool *tx_fwd_offload, 1196 struct netlink_ext_ack *extack) 1197 { 1198 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1199 struct dsa_port *cpu_dp = dp->cpu_dp; 1200 u32 port_bitmap = BIT(cpu_dp->index); 1201 struct mt7530_priv *priv = ds->priv; 1202 1203 mutex_lock(&priv->reg_mutex); 1204 1205 dsa_switch_for_each_user_port(other_dp, ds) { 1206 int other_port = other_dp->index; 1207 1208 if (dp == other_dp) 1209 continue; 1210 1211 /* Add this port to the port matrix of the other ports in the 1212 * same bridge. If the port is disabled, port matrix is kept 1213 * and not being setup until the port becomes enabled. 1214 */ 1215 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1216 continue; 1217 1218 if (priv->ports[other_port].enable) 1219 mt7530_set(priv, MT7530_PCR_P(other_port), 1220 PCR_MATRIX(BIT(port))); 1221 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1222 1223 port_bitmap |= BIT(other_port); 1224 } 1225 1226 /* Add the all other ports to this port matrix. */ 1227 if (priv->ports[port].enable) 1228 mt7530_rmw(priv, MT7530_PCR_P(port), 1229 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1230 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1231 1232 /* Set to fallback mode for independent VLAN learning */ 1233 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1234 MT7530_PORT_FALLBACK_MODE); 1235 1236 mutex_unlock(&priv->reg_mutex); 1237 1238 return 0; 1239 } 1240 1241 static void 1242 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1243 { 1244 struct mt7530_priv *priv = ds->priv; 1245 bool all_user_ports_removed = true; 1246 int i; 1247 1248 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1249 * bridge. Don't set standalone ports to fallback mode. 1250 */ 1251 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1252 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1253 MT7530_PORT_FALLBACK_MODE); 1254 1255 mt7530_rmw(priv, MT7530_PVC_P(port), 1256 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1257 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1258 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1259 MT7530_VLAN_ACC_ALL); 1260 1261 /* Set PVID to 0 */ 1262 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1263 G0_PORT_VID_DEF); 1264 1265 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1266 if (dsa_is_user_port(ds, i) && 1267 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1268 all_user_ports_removed = false; 1269 break; 1270 } 1271 } 1272 1273 /* CPU port also does the same thing until all user ports belonging to 1274 * the CPU port get out of VLAN filtering mode. 1275 */ 1276 if (all_user_ports_removed) { 1277 struct dsa_port *dp = dsa_to_port(ds, port); 1278 struct dsa_port *cpu_dp = dp->cpu_dp; 1279 1280 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1281 PCR_MATRIX(dsa_user_ports(priv->ds))); 1282 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1283 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1284 } 1285 } 1286 1287 static void 1288 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1289 { 1290 struct mt7530_priv *priv = ds->priv; 1291 1292 /* Trapped into security mode allows packet forwarding through VLAN 1293 * table lookup. 1294 */ 1295 if (dsa_is_user_port(ds, port)) { 1296 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1297 MT7530_PORT_SECURITY_MODE); 1298 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1299 G0_PORT_VID(priv->ports[port].pvid)); 1300 1301 /* Only accept tagged frames if PVID is not set */ 1302 if (!priv->ports[port].pvid) 1303 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1304 MT7530_VLAN_ACC_TAGGED); 1305 1306 /* Set the port as a user port which is to be able to recognize 1307 * VID from incoming packets before fetching entry within the 1308 * VLAN table. 1309 */ 1310 mt7530_rmw(priv, MT7530_PVC_P(port), 1311 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1312 VLAN_ATTR(MT7530_VLAN_USER) | 1313 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1314 } else { 1315 /* Also set CPU ports to the "user" VLAN port attribute, to 1316 * allow VLAN classification, but keep the EG_TAG attribute as 1317 * "consistent" (i.o.w. don't change its value) for packets 1318 * received by the switch from the CPU, so that tagged packets 1319 * are forwarded to user ports as tagged, and untagged as 1320 * untagged. 1321 */ 1322 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1323 VLAN_ATTR(MT7530_VLAN_USER)); 1324 } 1325 } 1326 1327 static void 1328 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1329 struct dsa_bridge bridge) 1330 { 1331 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1332 struct dsa_port *cpu_dp = dp->cpu_dp; 1333 struct mt7530_priv *priv = ds->priv; 1334 1335 mutex_lock(&priv->reg_mutex); 1336 1337 dsa_switch_for_each_user_port(other_dp, ds) { 1338 int other_port = other_dp->index; 1339 1340 if (dp == other_dp) 1341 continue; 1342 1343 /* Remove this port from the port matrix of the other ports 1344 * in the same bridge. If the port is disabled, port matrix 1345 * is kept and not being setup until the port becomes enabled. 1346 */ 1347 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1348 continue; 1349 1350 if (priv->ports[other_port].enable) 1351 mt7530_clear(priv, MT7530_PCR_P(other_port), 1352 PCR_MATRIX(BIT(port))); 1353 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1354 } 1355 1356 /* Set the cpu port to be the only one in the port matrix of 1357 * this port. 1358 */ 1359 if (priv->ports[port].enable) 1360 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1361 PCR_MATRIX(BIT(cpu_dp->index))); 1362 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1363 1364 /* When a port is removed from the bridge, the port would be set up 1365 * back to the default as is at initial boot which is a VLAN-unaware 1366 * port. 1367 */ 1368 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1369 MT7530_PORT_MATRIX_MODE); 1370 1371 mutex_unlock(&priv->reg_mutex); 1372 } 1373 1374 static int 1375 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1376 const unsigned char *addr, u16 vid, 1377 struct dsa_db db) 1378 { 1379 struct mt7530_priv *priv = ds->priv; 1380 int ret; 1381 u8 port_mask = BIT(port); 1382 1383 mutex_lock(&priv->reg_mutex); 1384 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1385 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1386 mutex_unlock(&priv->reg_mutex); 1387 1388 return ret; 1389 } 1390 1391 static int 1392 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1393 const unsigned char *addr, u16 vid, 1394 struct dsa_db db) 1395 { 1396 struct mt7530_priv *priv = ds->priv; 1397 int ret; 1398 u8 port_mask = BIT(port); 1399 1400 mutex_lock(&priv->reg_mutex); 1401 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1402 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1403 mutex_unlock(&priv->reg_mutex); 1404 1405 return ret; 1406 } 1407 1408 static int 1409 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1410 dsa_fdb_dump_cb_t *cb, void *data) 1411 { 1412 struct mt7530_priv *priv = ds->priv; 1413 struct mt7530_fdb _fdb = { 0 }; 1414 int cnt = MT7530_NUM_FDB_RECORDS; 1415 int ret = 0; 1416 u32 rsp = 0; 1417 1418 mutex_lock(&priv->reg_mutex); 1419 1420 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1421 if (ret < 0) 1422 goto err; 1423 1424 do { 1425 if (rsp & ATC_SRCH_HIT) { 1426 mt7530_fdb_read(priv, &_fdb); 1427 if (_fdb.port_mask & BIT(port)) { 1428 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1429 data); 1430 if (ret < 0) 1431 break; 1432 } 1433 } 1434 } while (--cnt && 1435 !(rsp & ATC_SRCH_END) && 1436 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1437 err: 1438 mutex_unlock(&priv->reg_mutex); 1439 1440 return 0; 1441 } 1442 1443 static int 1444 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1445 const struct switchdev_obj_port_mdb *mdb, 1446 struct dsa_db db) 1447 { 1448 struct mt7530_priv *priv = ds->priv; 1449 const u8 *addr = mdb->addr; 1450 u16 vid = mdb->vid; 1451 u8 port_mask = 0; 1452 int ret; 1453 1454 mutex_lock(&priv->reg_mutex); 1455 1456 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1457 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1458 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1459 & PORT_MAP_MASK; 1460 1461 port_mask |= BIT(port); 1462 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1463 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1464 1465 mutex_unlock(&priv->reg_mutex); 1466 1467 return ret; 1468 } 1469 1470 static int 1471 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1472 const struct switchdev_obj_port_mdb *mdb, 1473 struct dsa_db db) 1474 { 1475 struct mt7530_priv *priv = ds->priv; 1476 const u8 *addr = mdb->addr; 1477 u16 vid = mdb->vid; 1478 u8 port_mask = 0; 1479 int ret; 1480 1481 mutex_lock(&priv->reg_mutex); 1482 1483 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1484 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1485 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1486 & PORT_MAP_MASK; 1487 1488 port_mask &= ~BIT(port); 1489 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1490 port_mask ? STATIC_ENT : STATIC_EMP); 1491 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1492 1493 mutex_unlock(&priv->reg_mutex); 1494 1495 return ret; 1496 } 1497 1498 static int 1499 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1500 { 1501 struct mt7530_dummy_poll p; 1502 u32 val; 1503 int ret; 1504 1505 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1506 mt7530_write(priv, MT7530_VTCR, val); 1507 1508 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1509 ret = readx_poll_timeout(_mt7530_read, &p, val, 1510 !(val & VTCR_BUSY), 20, 20000); 1511 if (ret < 0) { 1512 dev_err(priv->dev, "poll timeout\n"); 1513 return ret; 1514 } 1515 1516 val = mt7530_read(priv, MT7530_VTCR); 1517 if (val & VTCR_INVALID) { 1518 dev_err(priv->dev, "read VTCR invalid\n"); 1519 return -EINVAL; 1520 } 1521 1522 return 0; 1523 } 1524 1525 static int 1526 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1527 struct netlink_ext_ack *extack) 1528 { 1529 struct dsa_port *dp = dsa_to_port(ds, port); 1530 struct dsa_port *cpu_dp = dp->cpu_dp; 1531 1532 if (vlan_filtering) { 1533 /* The port is being kept as VLAN-unaware port when bridge is 1534 * set up with vlan_filtering not being set, Otherwise, the 1535 * port and the corresponding CPU port is required the setup 1536 * for becoming a VLAN-aware port. 1537 */ 1538 mt7530_port_set_vlan_aware(ds, port); 1539 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1540 } else { 1541 mt7530_port_set_vlan_unaware(ds, port); 1542 } 1543 1544 return 0; 1545 } 1546 1547 static void 1548 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1549 struct mt7530_hw_vlan_entry *entry) 1550 { 1551 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1552 u8 new_members; 1553 u32 val; 1554 1555 new_members = entry->old_members | BIT(entry->port); 1556 1557 /* Validate the entry with independent learning, create egress tag per 1558 * VLAN and joining the port as one of the port members. 1559 */ 1560 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1561 VLAN_VALID; 1562 mt7530_write(priv, MT7530_VAWD1, val); 1563 1564 /* Decide whether adding tag or not for those outgoing packets from the 1565 * port inside the VLAN. 1566 * CPU port is always taken as a tagged port for serving more than one 1567 * VLANs across and also being applied with egress type stack mode for 1568 * that VLAN tags would be appended after hardware special tag used as 1569 * DSA tag. 1570 */ 1571 if (dsa_port_is_cpu(dp)) 1572 val = MT7530_VLAN_EGRESS_STACK; 1573 else if (entry->untagged) 1574 val = MT7530_VLAN_EGRESS_UNTAG; 1575 else 1576 val = MT7530_VLAN_EGRESS_TAG; 1577 mt7530_rmw(priv, MT7530_VAWD2, 1578 ETAG_CTRL_P_MASK(entry->port), 1579 ETAG_CTRL_P(entry->port, val)); 1580 } 1581 1582 static void 1583 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1584 struct mt7530_hw_vlan_entry *entry) 1585 { 1586 u8 new_members; 1587 u32 val; 1588 1589 new_members = entry->old_members & ~BIT(entry->port); 1590 1591 val = mt7530_read(priv, MT7530_VAWD1); 1592 if (!(val & VLAN_VALID)) { 1593 dev_err(priv->dev, 1594 "Cannot be deleted due to invalid entry\n"); 1595 return; 1596 } 1597 1598 if (new_members) { 1599 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1600 VLAN_VALID; 1601 mt7530_write(priv, MT7530_VAWD1, val); 1602 } else { 1603 mt7530_write(priv, MT7530_VAWD1, 0); 1604 mt7530_write(priv, MT7530_VAWD2, 0); 1605 } 1606 } 1607 1608 static void 1609 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1610 struct mt7530_hw_vlan_entry *entry, 1611 mt7530_vlan_op vlan_op) 1612 { 1613 u32 val; 1614 1615 /* Fetch entry */ 1616 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1617 1618 val = mt7530_read(priv, MT7530_VAWD1); 1619 1620 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1621 1622 /* Manipulate entry */ 1623 vlan_op(priv, entry); 1624 1625 /* Flush result to hardware */ 1626 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1627 } 1628 1629 static int 1630 mt7530_setup_vlan0(struct mt7530_priv *priv) 1631 { 1632 u32 val; 1633 1634 /* Validate the entry with independent learning, keep the original 1635 * ingress tag attribute. 1636 */ 1637 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1638 VLAN_VALID; 1639 mt7530_write(priv, MT7530_VAWD1, val); 1640 1641 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1642 } 1643 1644 static int 1645 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1646 const struct switchdev_obj_port_vlan *vlan, 1647 struct netlink_ext_ack *extack) 1648 { 1649 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1650 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1651 struct mt7530_hw_vlan_entry new_entry; 1652 struct mt7530_priv *priv = ds->priv; 1653 1654 mutex_lock(&priv->reg_mutex); 1655 1656 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1657 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1658 1659 if (pvid) { 1660 priv->ports[port].pvid = vlan->vid; 1661 1662 /* Accept all frames if PVID is set */ 1663 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1664 MT7530_VLAN_ACC_ALL); 1665 1666 /* Only configure PVID if VLAN filtering is enabled */ 1667 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1668 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1669 G0_PORT_VID_MASK, 1670 G0_PORT_VID(vlan->vid)); 1671 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1672 /* This VLAN is overwritten without PVID, so unset it */ 1673 priv->ports[port].pvid = G0_PORT_VID_DEF; 1674 1675 /* Only accept tagged frames if the port is VLAN-aware */ 1676 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1677 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1678 MT7530_VLAN_ACC_TAGGED); 1679 1680 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1681 G0_PORT_VID_DEF); 1682 } 1683 1684 mutex_unlock(&priv->reg_mutex); 1685 1686 return 0; 1687 } 1688 1689 static int 1690 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1691 const struct switchdev_obj_port_vlan *vlan) 1692 { 1693 struct mt7530_hw_vlan_entry target_entry; 1694 struct mt7530_priv *priv = ds->priv; 1695 1696 mutex_lock(&priv->reg_mutex); 1697 1698 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1699 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1700 mt7530_hw_vlan_del); 1701 1702 /* PVID is being restored to the default whenever the PVID port 1703 * is being removed from the VLAN. 1704 */ 1705 if (priv->ports[port].pvid == vlan->vid) { 1706 priv->ports[port].pvid = G0_PORT_VID_DEF; 1707 1708 /* Only accept tagged frames if the port is VLAN-aware */ 1709 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1710 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1711 MT7530_VLAN_ACC_TAGGED); 1712 1713 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1714 G0_PORT_VID_DEF); 1715 } 1716 1717 1718 mutex_unlock(&priv->reg_mutex); 1719 1720 return 0; 1721 } 1722 1723 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1724 { 1725 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1726 MIRROR_PORT(val); 1727 } 1728 1729 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1730 { 1731 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1732 MIRROR_PORT(val); 1733 } 1734 1735 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1736 struct dsa_mall_mirror_tc_entry *mirror, 1737 bool ingress, struct netlink_ext_ack *extack) 1738 { 1739 struct mt7530_priv *priv = ds->priv; 1740 int monitor_port; 1741 u32 val; 1742 1743 /* Check for existent entry */ 1744 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1745 return -EEXIST; 1746 1747 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1748 1749 /* MT7530 only supports one monitor port */ 1750 monitor_port = mt753x_mirror_port_get(priv->id, val); 1751 if (val & MT753X_MIRROR_EN(priv->id) && 1752 monitor_port != mirror->to_local_port) 1753 return -EEXIST; 1754 1755 val |= MT753X_MIRROR_EN(priv->id); 1756 val &= ~MT753X_MIRROR_MASK(priv->id); 1757 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1758 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1759 1760 val = mt7530_read(priv, MT7530_PCR_P(port)); 1761 if (ingress) { 1762 val |= PORT_RX_MIR; 1763 priv->mirror_rx |= BIT(port); 1764 } else { 1765 val |= PORT_TX_MIR; 1766 priv->mirror_tx |= BIT(port); 1767 } 1768 mt7530_write(priv, MT7530_PCR_P(port), val); 1769 1770 return 0; 1771 } 1772 1773 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1774 struct dsa_mall_mirror_tc_entry *mirror) 1775 { 1776 struct mt7530_priv *priv = ds->priv; 1777 u32 val; 1778 1779 val = mt7530_read(priv, MT7530_PCR_P(port)); 1780 if (mirror->ingress) { 1781 val &= ~PORT_RX_MIR; 1782 priv->mirror_rx &= ~BIT(port); 1783 } else { 1784 val &= ~PORT_TX_MIR; 1785 priv->mirror_tx &= ~BIT(port); 1786 } 1787 mt7530_write(priv, MT7530_PCR_P(port), val); 1788 1789 if (!priv->mirror_rx && !priv->mirror_tx) { 1790 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1791 val &= ~MT753X_MIRROR_EN(priv->id); 1792 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1793 } 1794 } 1795 1796 static enum dsa_tag_protocol 1797 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1798 enum dsa_tag_protocol mp) 1799 { 1800 return DSA_TAG_PROTO_MTK; 1801 } 1802 1803 #ifdef CONFIG_GPIOLIB 1804 static inline u32 1805 mt7530_gpio_to_bit(unsigned int offset) 1806 { 1807 /* Map GPIO offset to register bit 1808 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1809 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1810 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1811 * [14:12] port 3 LED 0..2 as GPIO 9..11 1812 * [18:16] port 4 LED 0..2 as GPIO 12..14 1813 */ 1814 return BIT(offset + offset / 3); 1815 } 1816 1817 static int 1818 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1819 { 1820 struct mt7530_priv *priv = gpiochip_get_data(gc); 1821 u32 bit = mt7530_gpio_to_bit(offset); 1822 1823 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1824 } 1825 1826 static void 1827 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1828 { 1829 struct mt7530_priv *priv = gpiochip_get_data(gc); 1830 u32 bit = mt7530_gpio_to_bit(offset); 1831 1832 if (value) 1833 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1834 else 1835 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1836 } 1837 1838 static int 1839 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1840 { 1841 struct mt7530_priv *priv = gpiochip_get_data(gc); 1842 u32 bit = mt7530_gpio_to_bit(offset); 1843 1844 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1845 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1846 } 1847 1848 static int 1849 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1850 { 1851 struct mt7530_priv *priv = gpiochip_get_data(gc); 1852 u32 bit = mt7530_gpio_to_bit(offset); 1853 1854 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1855 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1856 1857 return 0; 1858 } 1859 1860 static int 1861 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1862 { 1863 struct mt7530_priv *priv = gpiochip_get_data(gc); 1864 u32 bit = mt7530_gpio_to_bit(offset); 1865 1866 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1867 1868 if (value) 1869 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1870 else 1871 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1872 1873 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1874 1875 return 0; 1876 } 1877 1878 static int 1879 mt7530_setup_gpio(struct mt7530_priv *priv) 1880 { 1881 struct device *dev = priv->dev; 1882 struct gpio_chip *gc; 1883 1884 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1885 if (!gc) 1886 return -ENOMEM; 1887 1888 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1889 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1890 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1891 1892 gc->label = "mt7530"; 1893 gc->parent = dev; 1894 gc->owner = THIS_MODULE; 1895 gc->get_direction = mt7530_gpio_get_direction; 1896 gc->direction_input = mt7530_gpio_direction_input; 1897 gc->direction_output = mt7530_gpio_direction_output; 1898 gc->get = mt7530_gpio_get; 1899 gc->set = mt7530_gpio_set; 1900 gc->base = -1; 1901 gc->ngpio = 15; 1902 gc->can_sleep = true; 1903 1904 return devm_gpiochip_add_data(dev, gc, priv); 1905 } 1906 #endif /* CONFIG_GPIOLIB */ 1907 1908 static irqreturn_t 1909 mt7530_irq_thread_fn(int irq, void *dev_id) 1910 { 1911 struct mt7530_priv *priv = dev_id; 1912 bool handled = false; 1913 u32 val; 1914 int p; 1915 1916 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1917 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1918 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1919 mutex_unlock(&priv->bus->mdio_lock); 1920 1921 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1922 if (BIT(p) & val) { 1923 unsigned int irq; 1924 1925 irq = irq_find_mapping(priv->irq_domain, p); 1926 handle_nested_irq(irq); 1927 handled = true; 1928 } 1929 } 1930 1931 return IRQ_RETVAL(handled); 1932 } 1933 1934 static void 1935 mt7530_irq_mask(struct irq_data *d) 1936 { 1937 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1938 1939 priv->irq_enable &= ~BIT(d->hwirq); 1940 } 1941 1942 static void 1943 mt7530_irq_unmask(struct irq_data *d) 1944 { 1945 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1946 1947 priv->irq_enable |= BIT(d->hwirq); 1948 } 1949 1950 static void 1951 mt7530_irq_bus_lock(struct irq_data *d) 1952 { 1953 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1954 1955 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1956 } 1957 1958 static void 1959 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1960 { 1961 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1962 1963 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1964 mutex_unlock(&priv->bus->mdio_lock); 1965 } 1966 1967 static struct irq_chip mt7530_irq_chip = { 1968 .name = KBUILD_MODNAME, 1969 .irq_mask = mt7530_irq_mask, 1970 .irq_unmask = mt7530_irq_unmask, 1971 .irq_bus_lock = mt7530_irq_bus_lock, 1972 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1973 }; 1974 1975 static int 1976 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1977 irq_hw_number_t hwirq) 1978 { 1979 irq_set_chip_data(irq, domain->host_data); 1980 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1981 irq_set_nested_thread(irq, true); 1982 irq_set_noprobe(irq); 1983 1984 return 0; 1985 } 1986 1987 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1988 .map = mt7530_irq_map, 1989 .xlate = irq_domain_xlate_onecell, 1990 }; 1991 1992 static void 1993 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1994 { 1995 struct dsa_switch *ds = priv->ds; 1996 int p; 1997 1998 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1999 if (BIT(p) & ds->phys_mii_mask) { 2000 unsigned int irq; 2001 2002 irq = irq_create_mapping(priv->irq_domain, p); 2003 ds->slave_mii_bus->irq[p] = irq; 2004 } 2005 } 2006 } 2007 2008 static int 2009 mt7530_setup_irq(struct mt7530_priv *priv) 2010 { 2011 struct device *dev = priv->dev; 2012 struct device_node *np = dev->of_node; 2013 int ret; 2014 2015 if (!of_property_read_bool(np, "interrupt-controller")) { 2016 dev_info(dev, "no interrupt support\n"); 2017 return 0; 2018 } 2019 2020 priv->irq = of_irq_get(np, 0); 2021 if (priv->irq <= 0) { 2022 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2023 return priv->irq ? : -EINVAL; 2024 } 2025 2026 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2027 &mt7530_irq_domain_ops, priv); 2028 if (!priv->irq_domain) { 2029 dev_err(dev, "failed to create IRQ domain\n"); 2030 return -ENOMEM; 2031 } 2032 2033 /* This register must be set for MT7530 to properly fire interrupts */ 2034 if (priv->id != ID_MT7531) 2035 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2036 2037 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2038 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2039 if (ret) { 2040 irq_domain_remove(priv->irq_domain); 2041 dev_err(dev, "failed to request IRQ: %d\n", ret); 2042 return ret; 2043 } 2044 2045 return 0; 2046 } 2047 2048 static void 2049 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2050 { 2051 int p; 2052 2053 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2054 if (BIT(p) & priv->ds->phys_mii_mask) { 2055 unsigned int irq; 2056 2057 irq = irq_find_mapping(priv->irq_domain, p); 2058 irq_dispose_mapping(irq); 2059 } 2060 } 2061 } 2062 2063 static void 2064 mt7530_free_irq_common(struct mt7530_priv *priv) 2065 { 2066 free_irq(priv->irq, priv); 2067 irq_domain_remove(priv->irq_domain); 2068 } 2069 2070 static void 2071 mt7530_free_irq(struct mt7530_priv *priv) 2072 { 2073 mt7530_free_mdio_irq(priv); 2074 mt7530_free_irq_common(priv); 2075 } 2076 2077 static int 2078 mt7530_setup_mdio(struct mt7530_priv *priv) 2079 { 2080 struct dsa_switch *ds = priv->ds; 2081 struct device *dev = priv->dev; 2082 struct mii_bus *bus; 2083 static int idx; 2084 int ret; 2085 2086 bus = devm_mdiobus_alloc(dev); 2087 if (!bus) 2088 return -ENOMEM; 2089 2090 ds->slave_mii_bus = bus; 2091 bus->priv = priv; 2092 bus->name = KBUILD_MODNAME "-mii"; 2093 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2094 bus->read = mt753x_phy_read_c22; 2095 bus->write = mt753x_phy_write_c22; 2096 bus->read_c45 = mt753x_phy_read_c45; 2097 bus->write_c45 = mt753x_phy_write_c45; 2098 bus->parent = dev; 2099 bus->phy_mask = ~ds->phys_mii_mask; 2100 2101 if (priv->irq) 2102 mt7530_setup_mdio_irq(priv); 2103 2104 ret = devm_mdiobus_register(dev, bus); 2105 if (ret) { 2106 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2107 if (priv->irq) 2108 mt7530_free_mdio_irq(priv); 2109 } 2110 2111 return ret; 2112 } 2113 2114 static int 2115 mt7530_setup(struct dsa_switch *ds) 2116 { 2117 struct mt7530_priv *priv = ds->priv; 2118 struct device_node *dn = NULL; 2119 struct device_node *phy_node; 2120 struct device_node *mac_np; 2121 struct mt7530_dummy_poll p; 2122 phy_interface_t interface; 2123 struct dsa_port *cpu_dp; 2124 u32 id, val; 2125 int ret, i; 2126 2127 /* The parent node of master netdev which holds the common system 2128 * controller also is the container for two GMACs nodes representing 2129 * as two netdev instances. 2130 */ 2131 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2132 dn = cpu_dp->master->dev.of_node->parent; 2133 /* It doesn't matter which CPU port is found first, 2134 * their masters should share the same parent OF node 2135 */ 2136 break; 2137 } 2138 2139 if (!dn) { 2140 dev_err(ds->dev, "parent OF node of DSA master not found"); 2141 return -EINVAL; 2142 } 2143 2144 ds->assisted_learning_on_cpu_port = true; 2145 ds->mtu_enforcement_ingress = true; 2146 2147 if (priv->id == ID_MT7530) { 2148 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2149 ret = regulator_enable(priv->core_pwr); 2150 if (ret < 0) { 2151 dev_err(priv->dev, 2152 "Failed to enable core power: %d\n", ret); 2153 return ret; 2154 } 2155 2156 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2157 ret = regulator_enable(priv->io_pwr); 2158 if (ret < 0) { 2159 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2160 ret); 2161 return ret; 2162 } 2163 } 2164 2165 /* Reset whole chip through gpio pin or memory-mapped registers for 2166 * different type of hardware 2167 */ 2168 if (priv->mcm) { 2169 reset_control_assert(priv->rstc); 2170 usleep_range(1000, 1100); 2171 reset_control_deassert(priv->rstc); 2172 } else { 2173 gpiod_set_value_cansleep(priv->reset, 0); 2174 usleep_range(1000, 1100); 2175 gpiod_set_value_cansleep(priv->reset, 1); 2176 } 2177 2178 /* Waiting for MT7530 got to stable */ 2179 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2180 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2181 20, 1000000); 2182 if (ret < 0) { 2183 dev_err(priv->dev, "reset timeout\n"); 2184 return ret; 2185 } 2186 2187 id = mt7530_read(priv, MT7530_CREV); 2188 id >>= CHIP_NAME_SHIFT; 2189 if (id != MT7530_ID) { 2190 dev_err(priv->dev, "chip %x can't be supported\n", id); 2191 return -ENODEV; 2192 } 2193 2194 /* Reset the switch through internal reset */ 2195 mt7530_write(priv, MT7530_SYS_CTRL, 2196 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2197 SYS_CTRL_REG_RST); 2198 2199 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2200 val = mt7530_read(priv, MT7530_MHWTRAP); 2201 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2202 val |= MHWTRAP_MANUAL; 2203 mt7530_write(priv, MT7530_MHWTRAP, val); 2204 2205 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2206 2207 /* Enable and reset MIB counters */ 2208 mt7530_mib_reset(ds); 2209 2210 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2211 /* Disable forwarding by default on all ports */ 2212 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2213 PCR_MATRIX_CLR); 2214 2215 /* Disable learning by default on all ports */ 2216 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2217 2218 if (dsa_is_cpu_port(ds, i)) { 2219 ret = mt753x_cpu_port_enable(ds, i); 2220 if (ret) 2221 return ret; 2222 } else { 2223 mt7530_port_disable(ds, i); 2224 2225 /* Set default PVID to 0 on all user ports */ 2226 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2227 G0_PORT_VID_DEF); 2228 } 2229 /* Enable consistent egress tag */ 2230 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2231 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2232 } 2233 2234 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2235 ret = mt7530_setup_vlan0(priv); 2236 if (ret) 2237 return ret; 2238 2239 /* Setup port 5 */ 2240 priv->p5_intf_sel = P5_DISABLED; 2241 interface = PHY_INTERFACE_MODE_NA; 2242 2243 if (!dsa_is_unused_port(ds, 5)) { 2244 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2245 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2246 if (ret && ret != -ENODEV) 2247 return ret; 2248 } else { 2249 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2250 for_each_child_of_node(dn, mac_np) { 2251 if (!of_device_is_compatible(mac_np, 2252 "mediatek,eth-mac")) 2253 continue; 2254 2255 ret = of_property_read_u32(mac_np, "reg", &id); 2256 if (ret < 0 || id != 1) 2257 continue; 2258 2259 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2260 if (!phy_node) 2261 continue; 2262 2263 if (phy_node->parent == priv->dev->of_node->parent) { 2264 ret = of_get_phy_mode(mac_np, &interface); 2265 if (ret && ret != -ENODEV) { 2266 of_node_put(mac_np); 2267 of_node_put(phy_node); 2268 return ret; 2269 } 2270 id = of_mdio_parse_addr(ds->dev, phy_node); 2271 if (id == 0) 2272 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2273 if (id == 4) 2274 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2275 } 2276 of_node_put(mac_np); 2277 of_node_put(phy_node); 2278 break; 2279 } 2280 } 2281 2282 #ifdef CONFIG_GPIOLIB 2283 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2284 ret = mt7530_setup_gpio(priv); 2285 if (ret) 2286 return ret; 2287 } 2288 #endif /* CONFIG_GPIOLIB */ 2289 2290 mt7530_setup_port5(ds, interface); 2291 2292 /* Flush the FDB table */ 2293 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2294 if (ret < 0) 2295 return ret; 2296 2297 return 0; 2298 } 2299 2300 static int 2301 mt7531_setup(struct dsa_switch *ds) 2302 { 2303 struct mt7530_priv *priv = ds->priv; 2304 struct mt7530_dummy_poll p; 2305 struct dsa_port *cpu_dp; 2306 u32 val, id; 2307 int ret, i; 2308 2309 /* Reset whole chip through gpio pin or memory-mapped registers for 2310 * different type of hardware 2311 */ 2312 if (priv->mcm) { 2313 reset_control_assert(priv->rstc); 2314 usleep_range(1000, 1100); 2315 reset_control_deassert(priv->rstc); 2316 } else { 2317 gpiod_set_value_cansleep(priv->reset, 0); 2318 usleep_range(1000, 1100); 2319 gpiod_set_value_cansleep(priv->reset, 1); 2320 } 2321 2322 /* Waiting for MT7530 got to stable */ 2323 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2324 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2325 20, 1000000); 2326 if (ret < 0) { 2327 dev_err(priv->dev, "reset timeout\n"); 2328 return ret; 2329 } 2330 2331 id = mt7530_read(priv, MT7531_CREV); 2332 id >>= CHIP_NAME_SHIFT; 2333 2334 if (id != MT7531_ID) { 2335 dev_err(priv->dev, "chip %x can't be supported\n", id); 2336 return -ENODEV; 2337 } 2338 2339 /* all MACs must be forced link-down before sw reset */ 2340 for (i = 0; i < MT7530_NUM_PORTS; i++) 2341 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2342 2343 /* Reset the switch through internal reset */ 2344 mt7530_write(priv, MT7530_SYS_CTRL, 2345 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2346 SYS_CTRL_REG_RST); 2347 2348 mt7531_pll_setup(priv); 2349 2350 if (mt7531_dual_sgmii_supported(priv)) { 2351 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2352 2353 /* Let ds->slave_mii_bus be able to access external phy. */ 2354 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2355 MT7531_EXT_P_MDC_11); 2356 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2357 MT7531_EXT_P_MDIO_12); 2358 } else { 2359 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2360 } 2361 dev_dbg(ds->dev, "P5 support %s interface\n", 2362 p5_intf_modes(priv->p5_intf_sel)); 2363 2364 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2365 MT7531_GPIO0_INTERRUPT); 2366 2367 /* Let phylink decide the interface later. */ 2368 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2369 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2370 2371 /* Enable PHY core PLL, since phy_device has not yet been created 2372 * provided for phy_[read,write]_mmd_indirect is called, we provide 2373 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2374 * function. 2375 */ 2376 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2377 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2378 val |= MT7531_PHY_PLL_BYPASS_MODE; 2379 val &= ~MT7531_PHY_PLL_OFF; 2380 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2381 CORE_PLL_GROUP4, val); 2382 2383 /* BPDU to CPU port */ 2384 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2385 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2386 BIT(cpu_dp->index)); 2387 break; 2388 } 2389 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2390 MT753X_BPDU_CPU_ONLY); 2391 2392 /* Enable and reset MIB counters */ 2393 mt7530_mib_reset(ds); 2394 2395 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2396 /* Disable forwarding by default on all ports */ 2397 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2398 PCR_MATRIX_CLR); 2399 2400 /* Disable learning by default on all ports */ 2401 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2402 2403 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2404 2405 if (dsa_is_cpu_port(ds, i)) { 2406 ret = mt753x_cpu_port_enable(ds, i); 2407 if (ret) 2408 return ret; 2409 } else { 2410 mt7530_port_disable(ds, i); 2411 2412 /* Set default PVID to 0 on all user ports */ 2413 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2414 G0_PORT_VID_DEF); 2415 } 2416 2417 /* Enable consistent egress tag */ 2418 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2419 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2420 } 2421 2422 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2423 ret = mt7530_setup_vlan0(priv); 2424 if (ret) 2425 return ret; 2426 2427 ds->assisted_learning_on_cpu_port = true; 2428 ds->mtu_enforcement_ingress = true; 2429 2430 /* Flush the FDB table */ 2431 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2432 if (ret < 0) 2433 return ret; 2434 2435 return 0; 2436 } 2437 2438 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2439 struct phylink_config *config) 2440 { 2441 switch (port) { 2442 case 0 ... 4: /* Internal phy */ 2443 __set_bit(PHY_INTERFACE_MODE_GMII, 2444 config->supported_interfaces); 2445 break; 2446 2447 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2448 phy_interface_set_rgmii(config->supported_interfaces); 2449 __set_bit(PHY_INTERFACE_MODE_MII, 2450 config->supported_interfaces); 2451 __set_bit(PHY_INTERFACE_MODE_GMII, 2452 config->supported_interfaces); 2453 break; 2454 2455 case 6: /* 1st cpu port */ 2456 __set_bit(PHY_INTERFACE_MODE_RGMII, 2457 config->supported_interfaces); 2458 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2459 config->supported_interfaces); 2460 break; 2461 } 2462 } 2463 2464 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2465 { 2466 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2467 } 2468 2469 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2470 struct phylink_config *config) 2471 { 2472 struct mt7530_priv *priv = ds->priv; 2473 2474 switch (port) { 2475 case 0 ... 4: /* Internal phy */ 2476 __set_bit(PHY_INTERFACE_MODE_GMII, 2477 config->supported_interfaces); 2478 break; 2479 2480 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2481 if (mt7531_is_rgmii_port(priv, port)) { 2482 phy_interface_set_rgmii(config->supported_interfaces); 2483 break; 2484 } 2485 fallthrough; 2486 2487 case 6: /* 1st cpu port supports sgmii/8023z only */ 2488 __set_bit(PHY_INTERFACE_MODE_SGMII, 2489 config->supported_interfaces); 2490 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2491 config->supported_interfaces); 2492 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2493 config->supported_interfaces); 2494 2495 config->mac_capabilities |= MAC_2500FD; 2496 break; 2497 } 2498 } 2499 2500 static int 2501 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2502 { 2503 struct mt7530_priv *priv = ds->priv; 2504 2505 return priv->info->pad_setup(ds, state->interface); 2506 } 2507 2508 static int 2509 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2510 phy_interface_t interface) 2511 { 2512 struct mt7530_priv *priv = ds->priv; 2513 2514 /* Only need to setup port5. */ 2515 if (port != 5) 2516 return 0; 2517 2518 mt7530_setup_port5(priv->ds, interface); 2519 2520 return 0; 2521 } 2522 2523 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2524 phy_interface_t interface, 2525 struct phy_device *phydev) 2526 { 2527 u32 val; 2528 2529 if (!mt7531_is_rgmii_port(priv, port)) { 2530 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2531 port); 2532 return -EINVAL; 2533 } 2534 2535 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2536 val |= GP_CLK_EN; 2537 val &= ~GP_MODE_MASK; 2538 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2539 val &= ~CLK_SKEW_IN_MASK; 2540 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2541 val &= ~CLK_SKEW_OUT_MASK; 2542 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2543 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2544 2545 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2546 if (!phydev || phy_driver_is_genphy(phydev)) { 2547 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2548 switch (interface) { 2549 case PHY_INTERFACE_MODE_RGMII: 2550 val |= TXCLK_NO_REVERSE; 2551 val |= RXCLK_NO_DELAY; 2552 break; 2553 case PHY_INTERFACE_MODE_RGMII_RXID: 2554 val |= TXCLK_NO_REVERSE; 2555 break; 2556 case PHY_INTERFACE_MODE_RGMII_TXID: 2557 val |= RXCLK_NO_DELAY; 2558 break; 2559 case PHY_INTERFACE_MODE_RGMII_ID: 2560 break; 2561 default: 2562 return -EINVAL; 2563 } 2564 } 2565 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2566 2567 return 0; 2568 } 2569 2570 static void mt7531_pcs_link_up(struct phylink_pcs *pcs, unsigned int mode, 2571 phy_interface_t interface, int speed, int duplex) 2572 { 2573 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2574 int port = pcs_to_mt753x_pcs(pcs)->port; 2575 unsigned int val; 2576 2577 /* For adjusting speed and duplex of SGMII force mode. */ 2578 if (interface != PHY_INTERFACE_MODE_SGMII || 2579 phylink_autoneg_inband(mode)) 2580 return; 2581 2582 /* SGMII force mode setting */ 2583 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2584 val &= ~MT7531_SGMII_IF_MODE_MASK; 2585 2586 switch (speed) { 2587 case SPEED_10: 2588 val |= MT7531_SGMII_FORCE_SPEED_10; 2589 break; 2590 case SPEED_100: 2591 val |= MT7531_SGMII_FORCE_SPEED_100; 2592 break; 2593 case SPEED_1000: 2594 val |= MT7531_SGMII_FORCE_SPEED_1000; 2595 break; 2596 } 2597 2598 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2599 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2600 * 2601 * The speed check is unnecessary as the MAC capabilities apply 2602 * this restriction. --rmk 2603 */ 2604 if ((speed == SPEED_10 || speed == SPEED_100) && 2605 duplex != DUPLEX_FULL) 2606 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2607 2608 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2609 } 2610 2611 static bool mt753x_is_mac_port(u32 port) 2612 { 2613 return (port == 5 || port == 6); 2614 } 2615 2616 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2617 phy_interface_t interface) 2618 { 2619 u32 val; 2620 2621 if (!mt753x_is_mac_port(port)) 2622 return -EINVAL; 2623 2624 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2625 MT7531_SGMII_PHYA_PWD); 2626 2627 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2628 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2629 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2630 * encoding. 2631 */ 2632 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2633 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2634 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2635 2636 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2637 2638 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2639 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2640 */ 2641 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2642 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2643 MT7531_SGMII_FORCE_SPEED_1000); 2644 2645 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2646 2647 return 0; 2648 } 2649 2650 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2651 phy_interface_t interface) 2652 { 2653 if (!mt753x_is_mac_port(port)) 2654 return -EINVAL; 2655 2656 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2657 MT7531_SGMII_PHYA_PWD); 2658 2659 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2660 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2661 2662 mt7530_set(priv, MT7531_SGMII_MODE(port), 2663 MT7531_SGMII_REMOTE_FAULT_DIS | 2664 MT7531_SGMII_SPEED_DUPLEX_AN); 2665 2666 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2667 MT7531_SGMII_TX_CONFIG_MASK, 1); 2668 2669 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2670 2671 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2672 2673 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2674 2675 return 0; 2676 } 2677 2678 static void mt7531_pcs_an_restart(struct phylink_pcs *pcs) 2679 { 2680 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2681 int port = pcs_to_mt753x_pcs(pcs)->port; 2682 u32 val; 2683 2684 /* Only restart AN when AN is enabled */ 2685 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2686 if (val & MT7531_SGMII_AN_ENABLE) { 2687 val |= MT7531_SGMII_AN_RESTART; 2688 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2689 } 2690 } 2691 2692 static int 2693 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2694 phy_interface_t interface) 2695 { 2696 struct mt7530_priv *priv = ds->priv; 2697 struct phy_device *phydev; 2698 struct dsa_port *dp; 2699 2700 if (!mt753x_is_mac_port(port)) { 2701 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2702 return -EINVAL; 2703 } 2704 2705 switch (interface) { 2706 case PHY_INTERFACE_MODE_RGMII: 2707 case PHY_INTERFACE_MODE_RGMII_ID: 2708 case PHY_INTERFACE_MODE_RGMII_RXID: 2709 case PHY_INTERFACE_MODE_RGMII_TXID: 2710 dp = dsa_to_port(ds, port); 2711 phydev = dp->slave->phydev; 2712 return mt7531_rgmii_setup(priv, port, interface, phydev); 2713 case PHY_INTERFACE_MODE_SGMII: 2714 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2715 case PHY_INTERFACE_MODE_NA: 2716 case PHY_INTERFACE_MODE_1000BASEX: 2717 case PHY_INTERFACE_MODE_2500BASEX: 2718 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2719 default: 2720 return -EINVAL; 2721 } 2722 2723 return -EINVAL; 2724 } 2725 2726 static int 2727 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2728 const struct phylink_link_state *state) 2729 { 2730 struct mt7530_priv *priv = ds->priv; 2731 2732 return priv->info->mac_port_config(ds, port, mode, state->interface); 2733 } 2734 2735 static struct phylink_pcs * 2736 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2737 phy_interface_t interface) 2738 { 2739 struct mt7530_priv *priv = ds->priv; 2740 2741 switch (interface) { 2742 case PHY_INTERFACE_MODE_TRGMII: 2743 case PHY_INTERFACE_MODE_SGMII: 2744 case PHY_INTERFACE_MODE_1000BASEX: 2745 case PHY_INTERFACE_MODE_2500BASEX: 2746 return &priv->pcs[port].pcs; 2747 2748 default: 2749 return NULL; 2750 } 2751 } 2752 2753 static void 2754 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2755 const struct phylink_link_state *state) 2756 { 2757 struct mt7530_priv *priv = ds->priv; 2758 u32 mcr_cur, mcr_new; 2759 2760 switch (port) { 2761 case 0 ... 4: /* Internal phy */ 2762 if (state->interface != PHY_INTERFACE_MODE_GMII) 2763 goto unsupported; 2764 break; 2765 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2766 if (priv->p5_interface == state->interface) 2767 break; 2768 2769 if (mt753x_mac_config(ds, port, mode, state) < 0) 2770 goto unsupported; 2771 2772 if (priv->p5_intf_sel != P5_DISABLED) 2773 priv->p5_interface = state->interface; 2774 break; 2775 case 6: /* 1st cpu port */ 2776 if (priv->p6_interface == state->interface) 2777 break; 2778 2779 mt753x_pad_setup(ds, state); 2780 2781 if (mt753x_mac_config(ds, port, mode, state) < 0) 2782 goto unsupported; 2783 2784 priv->p6_interface = state->interface; 2785 break; 2786 default: 2787 unsupported: 2788 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2789 __func__, phy_modes(state->interface), port); 2790 return; 2791 } 2792 2793 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2794 mcr_new = mcr_cur; 2795 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2796 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2797 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2798 2799 /* Are we connected to external phy */ 2800 if (port == 5 && dsa_is_user_port(ds, 5)) 2801 mcr_new |= PMCR_EXT_PHY; 2802 2803 if (mcr_new != mcr_cur) 2804 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2805 } 2806 2807 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2808 unsigned int mode, 2809 phy_interface_t interface) 2810 { 2811 struct mt7530_priv *priv = ds->priv; 2812 2813 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2814 } 2815 2816 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2817 unsigned int mode, 2818 phy_interface_t interface, 2819 int speed, int duplex) 2820 { 2821 if (pcs->ops->pcs_link_up) 2822 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2823 } 2824 2825 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2826 unsigned int mode, 2827 phy_interface_t interface, 2828 struct phy_device *phydev, 2829 int speed, int duplex, 2830 bool tx_pause, bool rx_pause) 2831 { 2832 struct mt7530_priv *priv = ds->priv; 2833 u32 mcr; 2834 2835 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2836 2837 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2838 * variants. 2839 */ 2840 if (interface == PHY_INTERFACE_MODE_TRGMII || 2841 (phy_interface_mode_is_8023z(interface))) { 2842 speed = SPEED_1000; 2843 duplex = DUPLEX_FULL; 2844 } 2845 2846 switch (speed) { 2847 case SPEED_1000: 2848 mcr |= PMCR_FORCE_SPEED_1000; 2849 break; 2850 case SPEED_100: 2851 mcr |= PMCR_FORCE_SPEED_100; 2852 break; 2853 } 2854 if (duplex == DUPLEX_FULL) { 2855 mcr |= PMCR_FORCE_FDX; 2856 if (tx_pause) 2857 mcr |= PMCR_TX_FC_EN; 2858 if (rx_pause) 2859 mcr |= PMCR_RX_FC_EN; 2860 } 2861 2862 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2863 switch (speed) { 2864 case SPEED_1000: 2865 mcr |= PMCR_FORCE_EEE1G; 2866 break; 2867 case SPEED_100: 2868 mcr |= PMCR_FORCE_EEE100; 2869 break; 2870 } 2871 } 2872 2873 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2874 } 2875 2876 static int 2877 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2878 { 2879 struct mt7530_priv *priv = ds->priv; 2880 phy_interface_t interface; 2881 int speed; 2882 int ret; 2883 2884 switch (port) { 2885 case 5: 2886 if (mt7531_is_rgmii_port(priv, port)) 2887 interface = PHY_INTERFACE_MODE_RGMII; 2888 else 2889 interface = PHY_INTERFACE_MODE_2500BASEX; 2890 2891 priv->p5_interface = interface; 2892 break; 2893 case 6: 2894 interface = PHY_INTERFACE_MODE_2500BASEX; 2895 2896 priv->p6_interface = interface; 2897 break; 2898 default: 2899 return -EINVAL; 2900 } 2901 2902 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2903 speed = SPEED_2500; 2904 else 2905 speed = SPEED_1000; 2906 2907 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2908 if (ret) 2909 return ret; 2910 mt7530_write(priv, MT7530_PMCR_P(port), 2911 PMCR_CPU_PORT_SETTING(priv->id)); 2912 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2913 interface, speed, DUPLEX_FULL); 2914 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2915 speed, DUPLEX_FULL, true, true); 2916 2917 return 0; 2918 } 2919 2920 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2921 struct phylink_config *config) 2922 { 2923 struct mt7530_priv *priv = ds->priv; 2924 2925 /* This switch only supports full-duplex at 1Gbps */ 2926 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2927 MAC_10 | MAC_100 | MAC_1000FD; 2928 2929 /* This driver does not make use of the speed, duplex, pause or the 2930 * advertisement in its mac_config, so it is safe to mark this driver 2931 * as non-legacy. 2932 */ 2933 config->legacy_pre_march2020 = false; 2934 2935 priv->info->mac_port_get_caps(ds, port, config); 2936 } 2937 2938 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2939 unsigned long *supported, 2940 const struct phylink_link_state *state) 2941 { 2942 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2943 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2944 phy_interface_mode_is_8023z(state->interface)) 2945 phylink_clear(supported, Autoneg); 2946 2947 return 0; 2948 } 2949 2950 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2951 struct phylink_link_state *state) 2952 { 2953 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2954 int port = pcs_to_mt753x_pcs(pcs)->port; 2955 u32 pmsr; 2956 2957 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2958 2959 state->link = (pmsr & PMSR_LINK); 2960 state->an_complete = state->link; 2961 state->duplex = !!(pmsr & PMSR_DPX); 2962 2963 switch (pmsr & PMSR_SPEED_MASK) { 2964 case PMSR_SPEED_10: 2965 state->speed = SPEED_10; 2966 break; 2967 case PMSR_SPEED_100: 2968 state->speed = SPEED_100; 2969 break; 2970 case PMSR_SPEED_1000: 2971 state->speed = SPEED_1000; 2972 break; 2973 default: 2974 state->speed = SPEED_UNKNOWN; 2975 break; 2976 } 2977 2978 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2979 if (pmsr & PMSR_RX_FC) 2980 state->pause |= MLO_PAUSE_RX; 2981 if (pmsr & PMSR_TX_FC) 2982 state->pause |= MLO_PAUSE_TX; 2983 } 2984 2985 static int 2986 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2987 struct phylink_link_state *state) 2988 { 2989 u32 status, val; 2990 u16 config_reg; 2991 2992 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2993 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2994 state->an_complete = !!(status & MT7531_SGMII_AN_COMPLETE); 2995 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2996 (status & MT7531_SGMII_AN_ENABLE)) { 2997 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2998 config_reg = val >> 16; 2999 3000 switch (config_reg & LPA_SGMII_SPD_MASK) { 3001 case LPA_SGMII_1000: 3002 state->speed = SPEED_1000; 3003 break; 3004 case LPA_SGMII_100: 3005 state->speed = SPEED_100; 3006 break; 3007 case LPA_SGMII_10: 3008 state->speed = SPEED_10; 3009 break; 3010 default: 3011 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 3012 state->link = false; 3013 return -EINVAL; 3014 } 3015 3016 if (config_reg & LPA_SGMII_FULL_DUPLEX) 3017 state->duplex = DUPLEX_FULL; 3018 else 3019 state->duplex = DUPLEX_HALF; 3020 } 3021 3022 return 0; 3023 } 3024 3025 static void 3026 mt7531_sgmii_pcs_get_state_inband(struct mt7530_priv *priv, int port, 3027 struct phylink_link_state *state) 3028 { 3029 unsigned int val; 3030 3031 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 3032 state->link = !!(val & MT7531_SGMII_LINK_STATUS); 3033 if (!state->link) 3034 return; 3035 3036 state->an_complete = state->link; 3037 3038 if (state->interface == PHY_INTERFACE_MODE_2500BASEX) 3039 state->speed = SPEED_2500; 3040 else 3041 state->speed = SPEED_1000; 3042 3043 state->duplex = DUPLEX_FULL; 3044 state->pause = MLO_PAUSE_NONE; 3045 } 3046 3047 static void mt7531_pcs_get_state(struct phylink_pcs *pcs, 3048 struct phylink_link_state *state) 3049 { 3050 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 3051 int port = pcs_to_mt753x_pcs(pcs)->port; 3052 3053 if (state->interface == PHY_INTERFACE_MODE_SGMII) { 3054 mt7531_sgmii_pcs_get_state_an(priv, port, state); 3055 return; 3056 } else if ((state->interface == PHY_INTERFACE_MODE_1000BASEX) || 3057 (state->interface == PHY_INTERFACE_MODE_2500BASEX)) { 3058 mt7531_sgmii_pcs_get_state_inband(priv, port, state); 3059 return; 3060 } 3061 3062 state->link = false; 3063 } 3064 3065 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 3066 phy_interface_t interface, 3067 const unsigned long *advertising, 3068 bool permit_pause_to_mac) 3069 { 3070 return 0; 3071 } 3072 3073 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3074 { 3075 } 3076 3077 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3078 .pcs_validate = mt753x_pcs_validate, 3079 .pcs_get_state = mt7530_pcs_get_state, 3080 .pcs_config = mt753x_pcs_config, 3081 .pcs_an_restart = mt7530_pcs_an_restart, 3082 }; 3083 3084 static const struct phylink_pcs_ops mt7531_pcs_ops = { 3085 .pcs_validate = mt753x_pcs_validate, 3086 .pcs_get_state = mt7531_pcs_get_state, 3087 .pcs_config = mt753x_pcs_config, 3088 .pcs_an_restart = mt7531_pcs_an_restart, 3089 .pcs_link_up = mt7531_pcs_link_up, 3090 }; 3091 3092 static int 3093 mt753x_setup(struct dsa_switch *ds) 3094 { 3095 struct mt7530_priv *priv = ds->priv; 3096 int i, ret; 3097 3098 /* Initialise the PCS devices */ 3099 for (i = 0; i < priv->ds->num_ports; i++) { 3100 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3101 priv->pcs[i].priv = priv; 3102 priv->pcs[i].port = i; 3103 if (mt753x_is_mac_port(i)) 3104 priv->pcs[i].pcs.poll = 1; 3105 } 3106 3107 ret = priv->info->sw_setup(ds); 3108 if (ret) 3109 return ret; 3110 3111 ret = mt7530_setup_irq(priv); 3112 if (ret) 3113 return ret; 3114 3115 ret = mt7530_setup_mdio(priv); 3116 if (ret && priv->irq) 3117 mt7530_free_irq_common(priv); 3118 3119 return ret; 3120 } 3121 3122 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3123 struct ethtool_eee *e) 3124 { 3125 struct mt7530_priv *priv = ds->priv; 3126 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3127 3128 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3129 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3130 3131 return 0; 3132 } 3133 3134 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3135 struct ethtool_eee *e) 3136 { 3137 struct mt7530_priv *priv = ds->priv; 3138 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3139 3140 if (e->tx_lpi_timer > 0xFFF) 3141 return -EINVAL; 3142 3143 set = SET_LPI_THRESH(e->tx_lpi_timer); 3144 if (!e->tx_lpi_enabled) 3145 /* Force LPI Mode without a delay */ 3146 set |= LPI_MODE_EN; 3147 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3148 3149 return 0; 3150 } 3151 3152 static const struct dsa_switch_ops mt7530_switch_ops = { 3153 .get_tag_protocol = mtk_get_tag_protocol, 3154 .setup = mt753x_setup, 3155 .get_strings = mt7530_get_strings, 3156 .get_ethtool_stats = mt7530_get_ethtool_stats, 3157 .get_sset_count = mt7530_get_sset_count, 3158 .set_ageing_time = mt7530_set_ageing_time, 3159 .port_enable = mt7530_port_enable, 3160 .port_disable = mt7530_port_disable, 3161 .port_change_mtu = mt7530_port_change_mtu, 3162 .port_max_mtu = mt7530_port_max_mtu, 3163 .port_stp_state_set = mt7530_stp_state_set, 3164 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3165 .port_bridge_flags = mt7530_port_bridge_flags, 3166 .port_bridge_join = mt7530_port_bridge_join, 3167 .port_bridge_leave = mt7530_port_bridge_leave, 3168 .port_fdb_add = mt7530_port_fdb_add, 3169 .port_fdb_del = mt7530_port_fdb_del, 3170 .port_fdb_dump = mt7530_port_fdb_dump, 3171 .port_mdb_add = mt7530_port_mdb_add, 3172 .port_mdb_del = mt7530_port_mdb_del, 3173 .port_vlan_filtering = mt7530_port_vlan_filtering, 3174 .port_vlan_add = mt7530_port_vlan_add, 3175 .port_vlan_del = mt7530_port_vlan_del, 3176 .port_mirror_add = mt753x_port_mirror_add, 3177 .port_mirror_del = mt753x_port_mirror_del, 3178 .phylink_get_caps = mt753x_phylink_get_caps, 3179 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3180 .phylink_mac_config = mt753x_phylink_mac_config, 3181 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3182 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3183 .get_mac_eee = mt753x_get_mac_eee, 3184 .set_mac_eee = mt753x_set_mac_eee, 3185 }; 3186 3187 static const struct mt753x_info mt753x_table[] = { 3188 [ID_MT7621] = { 3189 .id = ID_MT7621, 3190 .pcs_ops = &mt7530_pcs_ops, 3191 .sw_setup = mt7530_setup, 3192 .phy_read_c22 = mt7530_phy_read_c22, 3193 .phy_write_c22 = mt7530_phy_write_c22, 3194 .phy_read_c45 = mt7530_phy_read_c45, 3195 .phy_write_c45 = mt7530_phy_write_c45, 3196 .pad_setup = mt7530_pad_clk_setup, 3197 .mac_port_get_caps = mt7530_mac_port_get_caps, 3198 .mac_port_config = mt7530_mac_config, 3199 }, 3200 [ID_MT7530] = { 3201 .id = ID_MT7530, 3202 .pcs_ops = &mt7530_pcs_ops, 3203 .sw_setup = mt7530_setup, 3204 .phy_read_c22 = mt7530_phy_read_c22, 3205 .phy_write_c22 = mt7530_phy_write_c22, 3206 .phy_read_c45 = mt7530_phy_read_c45, 3207 .phy_write_c45 = mt7530_phy_write_c45, 3208 .pad_setup = mt7530_pad_clk_setup, 3209 .mac_port_get_caps = mt7530_mac_port_get_caps, 3210 .mac_port_config = mt7530_mac_config, 3211 }, 3212 [ID_MT7531] = { 3213 .id = ID_MT7531, 3214 .pcs_ops = &mt7531_pcs_ops, 3215 .sw_setup = mt7531_setup, 3216 .phy_read_c22 = mt7531_ind_c22_phy_read, 3217 .phy_write_c22 = mt7531_ind_c22_phy_write, 3218 .phy_read_c45 = mt7531_ind_c45_phy_read, 3219 .phy_write_c45 = mt7531_ind_c45_phy_write, 3220 .pad_setup = mt7531_pad_setup, 3221 .cpu_port_config = mt7531_cpu_port_config, 3222 .mac_port_get_caps = mt7531_mac_port_get_caps, 3223 .mac_port_config = mt7531_mac_config, 3224 }, 3225 }; 3226 3227 static const struct of_device_id mt7530_of_match[] = { 3228 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3229 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3230 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3231 { /* sentinel */ }, 3232 }; 3233 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3234 3235 static int 3236 mt7530_probe(struct mdio_device *mdiodev) 3237 { 3238 struct mt7530_priv *priv; 3239 struct device_node *dn; 3240 3241 dn = mdiodev->dev.of_node; 3242 3243 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3244 if (!priv) 3245 return -ENOMEM; 3246 3247 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3248 if (!priv->ds) 3249 return -ENOMEM; 3250 3251 priv->ds->dev = &mdiodev->dev; 3252 priv->ds->num_ports = MT7530_NUM_PORTS; 3253 3254 /* Use medatek,mcm property to distinguish hardware type that would 3255 * casues a little bit differences on power-on sequence. 3256 */ 3257 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3258 if (priv->mcm) { 3259 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3260 3261 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3262 if (IS_ERR(priv->rstc)) { 3263 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3264 return PTR_ERR(priv->rstc); 3265 } 3266 } 3267 3268 /* Get the hardware identifier from the devicetree node. 3269 * We will need it for some of the clock and regulator setup. 3270 */ 3271 priv->info = of_device_get_match_data(&mdiodev->dev); 3272 if (!priv->info) 3273 return -EINVAL; 3274 3275 /* Sanity check if these required device operations are filled 3276 * properly. 3277 */ 3278 if (!priv->info->sw_setup || !priv->info->pad_setup || 3279 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3280 !priv->info->mac_port_get_caps || 3281 !priv->info->mac_port_config) 3282 return -EINVAL; 3283 3284 priv->id = priv->info->id; 3285 3286 if (priv->id == ID_MT7530) { 3287 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3288 if (IS_ERR(priv->core_pwr)) 3289 return PTR_ERR(priv->core_pwr); 3290 3291 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3292 if (IS_ERR(priv->io_pwr)) 3293 return PTR_ERR(priv->io_pwr); 3294 } 3295 3296 /* Not MCM that indicates switch works as the remote standalone 3297 * integrated circuit so the GPIO pin would be used to complete 3298 * the reset, otherwise memory-mapped register accessing used 3299 * through syscon provides in the case of MCM. 3300 */ 3301 if (!priv->mcm) { 3302 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3303 GPIOD_OUT_LOW); 3304 if (IS_ERR(priv->reset)) { 3305 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3306 return PTR_ERR(priv->reset); 3307 } 3308 } 3309 3310 priv->bus = mdiodev->bus; 3311 priv->dev = &mdiodev->dev; 3312 priv->ds->priv = priv; 3313 priv->ds->ops = &mt7530_switch_ops; 3314 mutex_init(&priv->reg_mutex); 3315 dev_set_drvdata(&mdiodev->dev, priv); 3316 3317 return dsa_register_switch(priv->ds); 3318 } 3319 3320 static void 3321 mt7530_remove(struct mdio_device *mdiodev) 3322 { 3323 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3324 int ret = 0; 3325 3326 if (!priv) 3327 return; 3328 3329 ret = regulator_disable(priv->core_pwr); 3330 if (ret < 0) 3331 dev_err(priv->dev, 3332 "Failed to disable core power: %d\n", ret); 3333 3334 ret = regulator_disable(priv->io_pwr); 3335 if (ret < 0) 3336 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3337 ret); 3338 3339 if (priv->irq) 3340 mt7530_free_irq(priv); 3341 3342 dsa_unregister_switch(priv->ds); 3343 mutex_destroy(&priv->reg_mutex); 3344 } 3345 3346 static void mt7530_shutdown(struct mdio_device *mdiodev) 3347 { 3348 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3349 3350 if (!priv) 3351 return; 3352 3353 dsa_switch_shutdown(priv->ds); 3354 3355 dev_set_drvdata(&mdiodev->dev, NULL); 3356 } 3357 3358 static struct mdio_driver mt7530_mdio_driver = { 3359 .probe = mt7530_probe, 3360 .remove = mt7530_remove, 3361 .shutdown = mt7530_shutdown, 3362 .mdiodrv.driver = { 3363 .name = "mt7530", 3364 .of_match_table = mt7530_of_match, 3365 }, 3366 }; 3367 3368 mdio_module_driver(mt7530_mdio_driver); 3369 3370 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3371 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3372 MODULE_LICENSE("GPL"); 3373