1 /* 2 * Mediatek MT7530 DSA Switch driver 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <linux/etherdevice.h> 15 #include <linux/if_bridge.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/netdevice.h> 21 #include <linux/of_mdio.h> 22 #include <linux/of_net.h> 23 #include <linux/of_platform.h> 24 #include <linux/phy.h> 25 #include <linux/regmap.h> 26 #include <linux/regulator/consumer.h> 27 #include <linux/reset.h> 28 #include <linux/gpio/consumer.h> 29 #include <net/dsa.h> 30 31 #include "mt7530.h" 32 33 /* String, offset, and register size in bytes if different from 4 bytes */ 34 static const struct mt7530_mib_desc mt7530_mib[] = { 35 MIB_DESC(1, 0x00, "TxDrop"), 36 MIB_DESC(1, 0x04, "TxCrcErr"), 37 MIB_DESC(1, 0x08, "TxUnicast"), 38 MIB_DESC(1, 0x0c, "TxMulticast"), 39 MIB_DESC(1, 0x10, "TxBroadcast"), 40 MIB_DESC(1, 0x14, "TxCollision"), 41 MIB_DESC(1, 0x18, "TxSingleCollision"), 42 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 43 MIB_DESC(1, 0x20, "TxDeferred"), 44 MIB_DESC(1, 0x24, "TxLateCollision"), 45 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 46 MIB_DESC(1, 0x2c, "TxPause"), 47 MIB_DESC(1, 0x30, "TxPktSz64"), 48 MIB_DESC(1, 0x34, "TxPktSz65To127"), 49 MIB_DESC(1, 0x38, "TxPktSz128To255"), 50 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 51 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 52 MIB_DESC(1, 0x44, "Tx1024ToMax"), 53 MIB_DESC(2, 0x48, "TxBytes"), 54 MIB_DESC(1, 0x60, "RxDrop"), 55 MIB_DESC(1, 0x64, "RxFiltering"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 static int 78 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) 79 { 80 int ret; 81 82 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); 83 if (ret < 0) 84 dev_err(priv->dev, 85 "failed to priv write register\n"); 86 return ret; 87 } 88 89 static u32 90 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) 91 { 92 int ret; 93 u32 val; 94 95 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); 96 if (ret < 0) { 97 dev_err(priv->dev, 98 "failed to priv read register\n"); 99 return ret; 100 } 101 102 return val; 103 } 104 105 static void 106 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, 107 u32 mask, u32 set) 108 { 109 u32 val; 110 111 val = mt7623_trgmii_read(priv, reg); 112 val &= ~mask; 113 val |= set; 114 mt7623_trgmii_write(priv, reg, val); 115 } 116 117 static void 118 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) 119 { 120 mt7623_trgmii_rmw(priv, reg, 0, val); 121 } 122 123 static void 124 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) 125 { 126 mt7623_trgmii_rmw(priv, reg, val, 0); 127 } 128 129 static int 130 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 131 { 132 struct mii_bus *bus = priv->bus; 133 int value, ret; 134 135 /* Write the desired MMD Devad */ 136 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 137 if (ret < 0) 138 goto err; 139 140 /* Write the desired MMD register address */ 141 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 142 if (ret < 0) 143 goto err; 144 145 /* Select the Function : DATA with no post increment */ 146 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 147 if (ret < 0) 148 goto err; 149 150 /* Read the content of the MMD's selected register */ 151 value = bus->read(bus, 0, MII_MMD_DATA); 152 153 return value; 154 err: 155 dev_err(&bus->dev, "failed to read mmd register\n"); 156 157 return ret; 158 } 159 160 static int 161 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 162 int devad, u32 data) 163 { 164 struct mii_bus *bus = priv->bus; 165 int ret; 166 167 /* Write the desired MMD Devad */ 168 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 169 if (ret < 0) 170 goto err; 171 172 /* Write the desired MMD register address */ 173 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 174 if (ret < 0) 175 goto err; 176 177 /* Select the Function : DATA with no post increment */ 178 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 179 if (ret < 0) 180 goto err; 181 182 /* Write the data into MMD's selected register */ 183 ret = bus->write(bus, 0, MII_MMD_DATA, data); 184 err: 185 if (ret < 0) 186 dev_err(&bus->dev, 187 "failed to write mmd register\n"); 188 return ret; 189 } 190 191 static void 192 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 193 { 194 struct mii_bus *bus = priv->bus; 195 196 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 197 198 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 199 200 mutex_unlock(&bus->mdio_lock); 201 } 202 203 static void 204 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 205 { 206 struct mii_bus *bus = priv->bus; 207 u32 val; 208 209 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 210 211 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 212 val &= ~mask; 213 val |= set; 214 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 215 216 mutex_unlock(&bus->mdio_lock); 217 } 218 219 static void 220 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 221 { 222 core_rmw(priv, reg, 0, val); 223 } 224 225 static void 226 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 227 { 228 core_rmw(priv, reg, val, 0); 229 } 230 231 static int 232 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 233 { 234 struct mii_bus *bus = priv->bus; 235 u16 page, r, lo, hi; 236 int ret; 237 238 page = (reg >> 6) & 0x3ff; 239 r = (reg >> 2) & 0xf; 240 lo = val & 0xffff; 241 hi = val >> 16; 242 243 /* MT7530 uses 31 as the pseudo port */ 244 ret = bus->write(bus, 0x1f, 0x1f, page); 245 if (ret < 0) 246 goto err; 247 248 ret = bus->write(bus, 0x1f, r, lo); 249 if (ret < 0) 250 goto err; 251 252 ret = bus->write(bus, 0x1f, 0x10, hi); 253 err: 254 if (ret < 0) 255 dev_err(&bus->dev, 256 "failed to write mt7530 register\n"); 257 return ret; 258 } 259 260 static u32 261 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 262 { 263 struct mii_bus *bus = priv->bus; 264 u16 page, r, lo, hi; 265 int ret; 266 267 page = (reg >> 6) & 0x3ff; 268 r = (reg >> 2) & 0xf; 269 270 /* MT7530 uses 31 as the pseudo port */ 271 ret = bus->write(bus, 0x1f, 0x1f, page); 272 if (ret < 0) { 273 dev_err(&bus->dev, 274 "failed to read mt7530 register\n"); 275 return ret; 276 } 277 278 lo = bus->read(bus, 0x1f, r); 279 hi = bus->read(bus, 0x1f, 0x10); 280 281 return (hi << 16) | (lo & 0xffff); 282 } 283 284 static void 285 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 286 { 287 struct mii_bus *bus = priv->bus; 288 289 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 290 291 mt7530_mii_write(priv, reg, val); 292 293 mutex_unlock(&bus->mdio_lock); 294 } 295 296 static u32 297 _mt7530_read(struct mt7530_dummy_poll *p) 298 { 299 struct mii_bus *bus = p->priv->bus; 300 u32 val; 301 302 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 303 304 val = mt7530_mii_read(p->priv, p->reg); 305 306 mutex_unlock(&bus->mdio_lock); 307 308 return val; 309 } 310 311 static u32 312 mt7530_read(struct mt7530_priv *priv, u32 reg) 313 { 314 struct mt7530_dummy_poll p; 315 316 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 317 return _mt7530_read(&p); 318 } 319 320 static void 321 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 322 u32 mask, u32 set) 323 { 324 struct mii_bus *bus = priv->bus; 325 u32 val; 326 327 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 328 329 val = mt7530_mii_read(priv, reg); 330 val &= ~mask; 331 val |= set; 332 mt7530_mii_write(priv, reg, val); 333 334 mutex_unlock(&bus->mdio_lock); 335 } 336 337 static void 338 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 339 { 340 mt7530_rmw(priv, reg, 0, val); 341 } 342 343 static void 344 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 345 { 346 mt7530_rmw(priv, reg, val, 0); 347 } 348 349 static int 350 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 351 { 352 u32 val; 353 int ret; 354 struct mt7530_dummy_poll p; 355 356 /* Set the command operating upon the MAC address entries */ 357 val = ATC_BUSY | ATC_MAT(0) | cmd; 358 mt7530_write(priv, MT7530_ATC, val); 359 360 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 361 ret = readx_poll_timeout(_mt7530_read, &p, val, 362 !(val & ATC_BUSY), 20, 20000); 363 if (ret < 0) { 364 dev_err(priv->dev, "reset timeout\n"); 365 return ret; 366 } 367 368 /* Additional sanity for read command if the specified 369 * entry is invalid 370 */ 371 val = mt7530_read(priv, MT7530_ATC); 372 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 373 return -EINVAL; 374 375 if (rsp) 376 *rsp = val; 377 378 return 0; 379 } 380 381 static void 382 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 383 { 384 u32 reg[3]; 385 int i; 386 387 /* Read from ARL table into an array */ 388 for (i = 0; i < 3; i++) { 389 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 390 391 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 392 __func__, __LINE__, i, reg[i]); 393 } 394 395 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 396 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 397 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 398 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 399 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 400 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 401 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 402 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 403 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 404 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 405 } 406 407 static void 408 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 409 u8 port_mask, const u8 *mac, 410 u8 aging, u8 type) 411 { 412 u32 reg[3] = { 0 }; 413 int i; 414 415 reg[1] |= vid & CVID_MASK; 416 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 417 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 418 /* STATIC_ENT indicate that entry is static wouldn't 419 * be aged out and STATIC_EMP specified as erasing an 420 * entry 421 */ 422 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 423 reg[1] |= mac[5] << MAC_BYTE_5; 424 reg[1] |= mac[4] << MAC_BYTE_4; 425 reg[0] |= mac[3] << MAC_BYTE_3; 426 reg[0] |= mac[2] << MAC_BYTE_2; 427 reg[0] |= mac[1] << MAC_BYTE_1; 428 reg[0] |= mac[0] << MAC_BYTE_0; 429 430 /* Write array into the ARL table */ 431 for (i = 0; i < 3; i++) 432 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 433 } 434 435 static int 436 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) 437 { 438 struct mt7530_priv *priv = ds->priv; 439 u32 ncpo1, ssc_delta, trgint, i; 440 441 switch (mode) { 442 case PHY_INTERFACE_MODE_RGMII: 443 trgint = 0; 444 ncpo1 = 0x0c80; 445 ssc_delta = 0x87; 446 break; 447 case PHY_INTERFACE_MODE_TRGMII: 448 trgint = 1; 449 ncpo1 = 0x1400; 450 ssc_delta = 0x57; 451 break; 452 default: 453 dev_err(priv->dev, "xMII mode %d not supported\n", mode); 454 return -EINVAL; 455 } 456 457 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 458 P6_INTF_MODE(trgint)); 459 460 /* Lower Tx Driving for TRGMII path */ 461 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 462 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 463 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 464 465 /* Setup core clock for MT7530 */ 466 if (!trgint) { 467 /* Disable MT7530 core clock */ 468 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 469 470 /* Disable PLL, since phy_device has not yet been created 471 * provided for phy_[read,write]_mmd_indirect is called, we 472 * provide our own core_write_mmd_indirect to complete this 473 * function. 474 */ 475 core_write_mmd_indirect(priv, 476 CORE_GSWPLL_GRP1, 477 MDIO_MMD_VEND2, 478 0); 479 480 /* Set core clock into 500Mhz */ 481 core_write(priv, CORE_GSWPLL_GRP2, 482 RG_GSWPLL_POSDIV_500M(1) | 483 RG_GSWPLL_FBKDIV_500M(25)); 484 485 /* Enable PLL */ 486 core_write(priv, CORE_GSWPLL_GRP1, 487 RG_GSWPLL_EN_PRE | 488 RG_GSWPLL_POSDIV_200M(2) | 489 RG_GSWPLL_FBKDIV_200M(32)); 490 491 /* Enable MT7530 core clock */ 492 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 493 } 494 495 /* Setup the MT7530 TRGMII Tx Clock */ 496 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 497 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 498 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 499 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 500 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 501 core_write(priv, CORE_PLL_GROUP4, 502 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 503 RG_SYSPLL_BIAS_LPF_EN); 504 core_write(priv, CORE_PLL_GROUP2, 505 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 506 RG_SYSPLL_POSDIV(1)); 507 core_write(priv, CORE_PLL_GROUP7, 508 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 509 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 510 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 511 REG_GSWCK_EN | REG_TRGMIICK_EN); 512 513 if (!trgint) 514 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 515 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 516 RD_TAP_MASK, RD_TAP(16)); 517 else 518 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII); 519 520 return 0; 521 } 522 523 static int 524 mt7623_pad_clk_setup(struct dsa_switch *ds) 525 { 526 struct mt7530_priv *priv = ds->priv; 527 int i; 528 529 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 530 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), 531 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 532 533 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); 534 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); 535 536 return 0; 537 } 538 539 static void 540 mt7530_mib_reset(struct dsa_switch *ds) 541 { 542 struct mt7530_priv *priv = ds->priv; 543 544 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 546 } 547 548 static void 549 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) 550 { 551 u32 mask = PMCR_TX_EN | PMCR_RX_EN; 552 553 if (enable) 554 mt7530_set(priv, MT7530_PMCR_P(port), mask); 555 else 556 mt7530_clear(priv, MT7530_PMCR_P(port), mask); 557 } 558 559 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 560 { 561 struct mt7530_priv *priv = ds->priv; 562 563 return mdiobus_read_nested(priv->bus, port, regnum); 564 } 565 566 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 567 u16 val) 568 { 569 struct mt7530_priv *priv = ds->priv; 570 571 return mdiobus_write_nested(priv->bus, port, regnum, val); 572 } 573 574 static void 575 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 576 uint8_t *data) 577 { 578 int i; 579 580 if (stringset != ETH_SS_STATS) 581 return; 582 583 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 584 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 585 ETH_GSTRING_LEN); 586 } 587 588 static void 589 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 590 uint64_t *data) 591 { 592 struct mt7530_priv *priv = ds->priv; 593 const struct mt7530_mib_desc *mib; 594 u32 reg, i; 595 u64 hi; 596 597 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 598 mib = &mt7530_mib[i]; 599 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 600 601 data[i] = mt7530_read(priv, reg); 602 if (mib->size == 2) { 603 hi = mt7530_read(priv, reg + 4); 604 data[i] |= hi << 32; 605 } 606 } 607 } 608 609 static int 610 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 611 { 612 if (sset != ETH_SS_STATS) 613 return 0; 614 615 return ARRAY_SIZE(mt7530_mib); 616 } 617 618 static void mt7530_adjust_link(struct dsa_switch *ds, int port, 619 struct phy_device *phydev) 620 { 621 struct mt7530_priv *priv = ds->priv; 622 623 if (phy_is_pseudo_fixed_link(phydev)) { 624 if (priv->id == ID_MT7530) { 625 dev_dbg(priv->dev, "phy-mode for master device = %x\n", 626 phydev->interface); 627 628 /* Setup TX circuit incluing relevant PAD and driving */ 629 mt7530_pad_clk_setup(ds, phydev->interface); 630 631 /* Setup RX circuit, relevant PAD and driving on the 632 * host which must be placed after the setup on the 633 * device side is all finished. 634 */ 635 mt7623_pad_clk_setup(ds); 636 } 637 } else { 638 u16 lcl_adv = 0, rmt_adv = 0; 639 u8 flowctrl; 640 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE; 641 642 switch (phydev->speed) { 643 case SPEED_1000: 644 mcr |= PMCR_FORCE_SPEED_1000; 645 break; 646 case SPEED_100: 647 mcr |= PMCR_FORCE_SPEED_100; 648 break; 649 } 650 651 if (phydev->link) 652 mcr |= PMCR_FORCE_LNK; 653 654 if (phydev->duplex) { 655 mcr |= PMCR_FORCE_FDX; 656 657 if (phydev->pause) 658 rmt_adv = LPA_PAUSE_CAP; 659 if (phydev->asym_pause) 660 rmt_adv |= LPA_PAUSE_ASYM; 661 662 lcl_adv = linkmode_adv_to_lcl_adv_t( 663 phydev->advertising); 664 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 665 666 if (flowctrl & FLOW_CTRL_TX) 667 mcr |= PMCR_TX_FC_EN; 668 if (flowctrl & FLOW_CTRL_RX) 669 mcr |= PMCR_RX_FC_EN; 670 } 671 mt7530_write(priv, MT7530_PMCR_P(port), mcr); 672 } 673 } 674 675 static int 676 mt7530_cpu_port_enable(struct mt7530_priv *priv, 677 int port) 678 { 679 /* Enable Mediatek header mode on the cpu port */ 680 mt7530_write(priv, MT7530_PVC_P(port), 681 PORT_SPEC_TAG); 682 683 /* Setup the MAC by default for the cpu port */ 684 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK); 685 686 /* Disable auto learning on the cpu port */ 687 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); 688 689 /* Unknown unicast frame fordwarding to the cpu port */ 690 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); 691 692 /* Set CPU port number */ 693 if (priv->id == ID_MT7621) 694 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 695 696 /* CPU port gets connected to all user ports of 697 * the switch 698 */ 699 mt7530_write(priv, MT7530_PCR_P(port), 700 PCR_MATRIX(dsa_user_ports(priv->ds))); 701 702 return 0; 703 } 704 705 static int 706 mt7530_port_enable(struct dsa_switch *ds, int port, 707 struct phy_device *phy) 708 { 709 struct mt7530_priv *priv = ds->priv; 710 711 mutex_lock(&priv->reg_mutex); 712 713 /* Setup the MAC for the user port */ 714 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK); 715 716 /* Allow the user port gets connected to the cpu port and also 717 * restore the port matrix if the port is the member of a certain 718 * bridge. 719 */ 720 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 721 priv->ports[port].enable = true; 722 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 723 priv->ports[port].pm); 724 mt7530_port_set_status(priv, port, 1); 725 726 mutex_unlock(&priv->reg_mutex); 727 728 return 0; 729 } 730 731 static void 732 mt7530_port_disable(struct dsa_switch *ds, int port) 733 { 734 struct mt7530_priv *priv = ds->priv; 735 736 mutex_lock(&priv->reg_mutex); 737 738 /* Clear up all port matrix which could be restored in the next 739 * enablement for the port. 740 */ 741 priv->ports[port].enable = false; 742 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 743 PCR_MATRIX_CLR); 744 mt7530_port_set_status(priv, port, 0); 745 746 mutex_unlock(&priv->reg_mutex); 747 } 748 749 static void 750 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 751 { 752 struct mt7530_priv *priv = ds->priv; 753 u32 stp_state; 754 755 switch (state) { 756 case BR_STATE_DISABLED: 757 stp_state = MT7530_STP_DISABLED; 758 break; 759 case BR_STATE_BLOCKING: 760 stp_state = MT7530_STP_BLOCKING; 761 break; 762 case BR_STATE_LISTENING: 763 stp_state = MT7530_STP_LISTENING; 764 break; 765 case BR_STATE_LEARNING: 766 stp_state = MT7530_STP_LEARNING; 767 break; 768 case BR_STATE_FORWARDING: 769 default: 770 stp_state = MT7530_STP_FORWARDING; 771 break; 772 } 773 774 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 775 } 776 777 static int 778 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 779 struct net_device *bridge) 780 { 781 struct mt7530_priv *priv = ds->priv; 782 u32 port_bitmap = BIT(MT7530_CPU_PORT); 783 int i; 784 785 mutex_lock(&priv->reg_mutex); 786 787 for (i = 0; i < MT7530_NUM_PORTS; i++) { 788 /* Add this port to the port matrix of the other ports in the 789 * same bridge. If the port is disabled, port matrix is kept 790 * and not being setup until the port becomes enabled. 791 */ 792 if (dsa_is_user_port(ds, i) && i != port) { 793 if (dsa_to_port(ds, i)->bridge_dev != bridge) 794 continue; 795 if (priv->ports[i].enable) 796 mt7530_set(priv, MT7530_PCR_P(i), 797 PCR_MATRIX(BIT(port))); 798 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 799 800 port_bitmap |= BIT(i); 801 } 802 } 803 804 /* Add the all other ports to this port matrix. */ 805 if (priv->ports[port].enable) 806 mt7530_rmw(priv, MT7530_PCR_P(port), 807 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 808 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 809 810 mutex_unlock(&priv->reg_mutex); 811 812 return 0; 813 } 814 815 static void 816 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 817 { 818 struct mt7530_priv *priv = ds->priv; 819 bool all_user_ports_removed = true; 820 int i; 821 822 /* When a port is removed from the bridge, the port would be set up 823 * back to the default as is at initial boot which is a VLAN-unaware 824 * port. 825 */ 826 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 827 MT7530_PORT_MATRIX_MODE); 828 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 829 VLAN_ATTR(MT7530_VLAN_TRANSPARENT)); 830 831 for (i = 0; i < MT7530_NUM_PORTS; i++) { 832 if (dsa_is_user_port(ds, i) && 833 dsa_port_is_vlan_filtering(&ds->ports[i])) { 834 all_user_ports_removed = false; 835 break; 836 } 837 } 838 839 /* CPU port also does the same thing until all user ports belonging to 840 * the CPU port get out of VLAN filtering mode. 841 */ 842 if (all_user_ports_removed) { 843 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 844 PCR_MATRIX(dsa_user_ports(priv->ds))); 845 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), 846 PORT_SPEC_TAG); 847 } 848 } 849 850 static void 851 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 852 { 853 struct mt7530_priv *priv = ds->priv; 854 855 /* The real fabric path would be decided on the membership in the 856 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 857 * means potential VLAN can be consisting of certain subset of all 858 * ports. 859 */ 860 mt7530_rmw(priv, MT7530_PCR_P(port), 861 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 862 863 /* Trapped into security mode allows packet forwarding through VLAN 864 * table lookup. 865 */ 866 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 867 MT7530_PORT_SECURITY_MODE); 868 869 /* Set the port as a user port which is to be able to recognize VID 870 * from incoming packets before fetching entry within the VLAN table. 871 */ 872 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 873 VLAN_ATTR(MT7530_VLAN_USER)); 874 } 875 876 static void 877 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 878 struct net_device *bridge) 879 { 880 struct mt7530_priv *priv = ds->priv; 881 int i; 882 883 mutex_lock(&priv->reg_mutex); 884 885 for (i = 0; i < MT7530_NUM_PORTS; i++) { 886 /* Remove this port from the port matrix of the other ports 887 * in the same bridge. If the port is disabled, port matrix 888 * is kept and not being setup until the port becomes enabled. 889 * And the other port's port matrix cannot be broken when the 890 * other port is still a VLAN-aware port. 891 */ 892 if (dsa_is_user_port(ds, i) && i != port && 893 !dsa_port_is_vlan_filtering(&ds->ports[i])) { 894 if (dsa_to_port(ds, i)->bridge_dev != bridge) 895 continue; 896 if (priv->ports[i].enable) 897 mt7530_clear(priv, MT7530_PCR_P(i), 898 PCR_MATRIX(BIT(port))); 899 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 900 } 901 } 902 903 /* Set the cpu port to be the only one in the port matrix of 904 * this port. 905 */ 906 if (priv->ports[port].enable) 907 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 908 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 909 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 910 911 mutex_unlock(&priv->reg_mutex); 912 } 913 914 static int 915 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 916 const unsigned char *addr, u16 vid) 917 { 918 struct mt7530_priv *priv = ds->priv; 919 int ret; 920 u8 port_mask = BIT(port); 921 922 mutex_lock(&priv->reg_mutex); 923 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 924 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 925 mutex_unlock(&priv->reg_mutex); 926 927 return ret; 928 } 929 930 static int 931 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 932 const unsigned char *addr, u16 vid) 933 { 934 struct mt7530_priv *priv = ds->priv; 935 int ret; 936 u8 port_mask = BIT(port); 937 938 mutex_lock(&priv->reg_mutex); 939 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 940 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 941 mutex_unlock(&priv->reg_mutex); 942 943 return ret; 944 } 945 946 static int 947 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 948 dsa_fdb_dump_cb_t *cb, void *data) 949 { 950 struct mt7530_priv *priv = ds->priv; 951 struct mt7530_fdb _fdb = { 0 }; 952 int cnt = MT7530_NUM_FDB_RECORDS; 953 int ret = 0; 954 u32 rsp = 0; 955 956 mutex_lock(&priv->reg_mutex); 957 958 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 959 if (ret < 0) 960 goto err; 961 962 do { 963 if (rsp & ATC_SRCH_HIT) { 964 mt7530_fdb_read(priv, &_fdb); 965 if (_fdb.port_mask & BIT(port)) { 966 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 967 data); 968 if (ret < 0) 969 break; 970 } 971 } 972 } while (--cnt && 973 !(rsp & ATC_SRCH_END) && 974 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 975 err: 976 mutex_unlock(&priv->reg_mutex); 977 978 return 0; 979 } 980 981 static int 982 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 983 { 984 struct mt7530_dummy_poll p; 985 u32 val; 986 int ret; 987 988 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 989 mt7530_write(priv, MT7530_VTCR, val); 990 991 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 992 ret = readx_poll_timeout(_mt7530_read, &p, val, 993 !(val & VTCR_BUSY), 20, 20000); 994 if (ret < 0) { 995 dev_err(priv->dev, "poll timeout\n"); 996 return ret; 997 } 998 999 val = mt7530_read(priv, MT7530_VTCR); 1000 if (val & VTCR_INVALID) { 1001 dev_err(priv->dev, "read VTCR invalid\n"); 1002 return -EINVAL; 1003 } 1004 1005 return 0; 1006 } 1007 1008 static int 1009 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, 1010 bool vlan_filtering) 1011 { 1012 if (vlan_filtering) { 1013 /* The port is being kept as VLAN-unaware port when bridge is 1014 * set up with vlan_filtering not being set, Otherwise, the 1015 * port and the corresponding CPU port is required the setup 1016 * for becoming a VLAN-aware port. 1017 */ 1018 mt7530_port_set_vlan_aware(ds, port); 1019 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1020 } else { 1021 mt7530_port_set_vlan_unaware(ds, port); 1022 } 1023 1024 return 0; 1025 } 1026 1027 static int 1028 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, 1029 const struct switchdev_obj_port_vlan *vlan) 1030 { 1031 /* nothing needed */ 1032 1033 return 0; 1034 } 1035 1036 static void 1037 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1038 struct mt7530_hw_vlan_entry *entry) 1039 { 1040 u8 new_members; 1041 u32 val; 1042 1043 new_members = entry->old_members | BIT(entry->port) | 1044 BIT(MT7530_CPU_PORT); 1045 1046 /* Validate the entry with independent learning, create egress tag per 1047 * VLAN and joining the port as one of the port members. 1048 */ 1049 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1050 mt7530_write(priv, MT7530_VAWD1, val); 1051 1052 /* Decide whether adding tag or not for those outgoing packets from the 1053 * port inside the VLAN. 1054 */ 1055 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1056 MT7530_VLAN_EGRESS_TAG; 1057 mt7530_rmw(priv, MT7530_VAWD2, 1058 ETAG_CTRL_P_MASK(entry->port), 1059 ETAG_CTRL_P(entry->port, val)); 1060 1061 /* CPU port is always taken as a tagged port for serving more than one 1062 * VLANs across and also being applied with egress type stack mode for 1063 * that VLAN tags would be appended after hardware special tag used as 1064 * DSA tag. 1065 */ 1066 mt7530_rmw(priv, MT7530_VAWD2, 1067 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1068 ETAG_CTRL_P(MT7530_CPU_PORT, 1069 MT7530_VLAN_EGRESS_STACK)); 1070 } 1071 1072 static void 1073 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1074 struct mt7530_hw_vlan_entry *entry) 1075 { 1076 u8 new_members; 1077 u32 val; 1078 1079 new_members = entry->old_members & ~BIT(entry->port); 1080 1081 val = mt7530_read(priv, MT7530_VAWD1); 1082 if (!(val & VLAN_VALID)) { 1083 dev_err(priv->dev, 1084 "Cannot be deleted due to invalid entry\n"); 1085 return; 1086 } 1087 1088 /* If certain member apart from CPU port is still alive in the VLAN, 1089 * the entry would be kept valid. Otherwise, the entry is got to be 1090 * disabled. 1091 */ 1092 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1093 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1094 VLAN_VALID; 1095 mt7530_write(priv, MT7530_VAWD1, val); 1096 } else { 1097 mt7530_write(priv, MT7530_VAWD1, 0); 1098 mt7530_write(priv, MT7530_VAWD2, 0); 1099 } 1100 } 1101 1102 static void 1103 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1104 struct mt7530_hw_vlan_entry *entry, 1105 mt7530_vlan_op vlan_op) 1106 { 1107 u32 val; 1108 1109 /* Fetch entry */ 1110 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1111 1112 val = mt7530_read(priv, MT7530_VAWD1); 1113 1114 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1115 1116 /* Manipulate entry */ 1117 vlan_op(priv, entry); 1118 1119 /* Flush result to hardware */ 1120 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1121 } 1122 1123 static void 1124 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1125 const struct switchdev_obj_port_vlan *vlan) 1126 { 1127 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1128 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1129 struct mt7530_hw_vlan_entry new_entry; 1130 struct mt7530_priv *priv = ds->priv; 1131 u16 vid; 1132 1133 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1134 * being set. 1135 */ 1136 if (!dsa_port_is_vlan_filtering(&ds->ports[port])) 1137 return; 1138 1139 mutex_lock(&priv->reg_mutex); 1140 1141 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1142 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1143 mt7530_hw_vlan_update(priv, vid, &new_entry, 1144 mt7530_hw_vlan_add); 1145 } 1146 1147 if (pvid) { 1148 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1149 G0_PORT_VID(vlan->vid_end)); 1150 priv->ports[port].pvid = vlan->vid_end; 1151 } 1152 1153 mutex_unlock(&priv->reg_mutex); 1154 } 1155 1156 static int 1157 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1158 const struct switchdev_obj_port_vlan *vlan) 1159 { 1160 struct mt7530_hw_vlan_entry target_entry; 1161 struct mt7530_priv *priv = ds->priv; 1162 u16 vid, pvid; 1163 1164 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1165 * being set. 1166 */ 1167 if (!dsa_port_is_vlan_filtering(&ds->ports[port])) 1168 return 0; 1169 1170 mutex_lock(&priv->reg_mutex); 1171 1172 pvid = priv->ports[port].pvid; 1173 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1174 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1175 mt7530_hw_vlan_update(priv, vid, &target_entry, 1176 mt7530_hw_vlan_del); 1177 1178 /* PVID is being restored to the default whenever the PVID port 1179 * is being removed from the VLAN. 1180 */ 1181 if (pvid == vid) 1182 pvid = G0_PORT_VID_DEF; 1183 } 1184 1185 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1186 priv->ports[port].pvid = pvid; 1187 1188 mutex_unlock(&priv->reg_mutex); 1189 1190 return 0; 1191 } 1192 1193 static enum dsa_tag_protocol 1194 mtk_get_tag_protocol(struct dsa_switch *ds, int port) 1195 { 1196 struct mt7530_priv *priv = ds->priv; 1197 1198 if (port != MT7530_CPU_PORT) { 1199 dev_warn(priv->dev, 1200 "port not matched with tagging CPU port\n"); 1201 return DSA_TAG_PROTO_NONE; 1202 } else { 1203 return DSA_TAG_PROTO_MTK; 1204 } 1205 } 1206 1207 static int 1208 mt7530_setup(struct dsa_switch *ds) 1209 { 1210 struct mt7530_priv *priv = ds->priv; 1211 int ret, i; 1212 u32 id, val; 1213 struct device_node *dn; 1214 struct mt7530_dummy_poll p; 1215 1216 /* The parent node of master netdev which holds the common system 1217 * controller also is the container for two GMACs nodes representing 1218 * as two netdev instances. 1219 */ 1220 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent; 1221 1222 if (priv->id == ID_MT7530) { 1223 priv->ethernet = syscon_node_to_regmap(dn); 1224 if (IS_ERR(priv->ethernet)) 1225 return PTR_ERR(priv->ethernet); 1226 1227 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1228 ret = regulator_enable(priv->core_pwr); 1229 if (ret < 0) { 1230 dev_err(priv->dev, 1231 "Failed to enable core power: %d\n", ret); 1232 return ret; 1233 } 1234 1235 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1236 ret = regulator_enable(priv->io_pwr); 1237 if (ret < 0) { 1238 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1239 ret); 1240 return ret; 1241 } 1242 } 1243 1244 /* Reset whole chip through gpio pin or memory-mapped registers for 1245 * different type of hardware 1246 */ 1247 if (priv->mcm) { 1248 reset_control_assert(priv->rstc); 1249 usleep_range(1000, 1100); 1250 reset_control_deassert(priv->rstc); 1251 } else { 1252 gpiod_set_value_cansleep(priv->reset, 0); 1253 usleep_range(1000, 1100); 1254 gpiod_set_value_cansleep(priv->reset, 1); 1255 } 1256 1257 /* Waiting for MT7530 got to stable */ 1258 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1259 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1260 20, 1000000); 1261 if (ret < 0) { 1262 dev_err(priv->dev, "reset timeout\n"); 1263 return ret; 1264 } 1265 1266 id = mt7530_read(priv, MT7530_CREV); 1267 id >>= CHIP_NAME_SHIFT; 1268 if (id != MT7530_ID) { 1269 dev_err(priv->dev, "chip %x can't be supported\n", id); 1270 return -ENODEV; 1271 } 1272 1273 /* Reset the switch through internal reset */ 1274 mt7530_write(priv, MT7530_SYS_CTRL, 1275 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1276 SYS_CTRL_REG_RST); 1277 1278 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1279 val = mt7530_read(priv, MT7530_MHWTRAP); 1280 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1281 val |= MHWTRAP_MANUAL; 1282 mt7530_write(priv, MT7530_MHWTRAP, val); 1283 1284 /* Enable and reset MIB counters */ 1285 mt7530_mib_reset(ds); 1286 1287 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); 1288 1289 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1290 /* Disable forwarding by default on all ports */ 1291 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1292 PCR_MATRIX_CLR); 1293 1294 if (dsa_is_cpu_port(ds, i)) 1295 mt7530_cpu_port_enable(priv, i); 1296 else 1297 mt7530_port_disable(ds, i); 1298 } 1299 1300 /* Flush the FDB table */ 1301 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1302 if (ret < 0) 1303 return ret; 1304 1305 return 0; 1306 } 1307 1308 static const struct dsa_switch_ops mt7530_switch_ops = { 1309 .get_tag_protocol = mtk_get_tag_protocol, 1310 .setup = mt7530_setup, 1311 .get_strings = mt7530_get_strings, 1312 .phy_read = mt7530_phy_read, 1313 .phy_write = mt7530_phy_write, 1314 .get_ethtool_stats = mt7530_get_ethtool_stats, 1315 .get_sset_count = mt7530_get_sset_count, 1316 .adjust_link = mt7530_adjust_link, 1317 .port_enable = mt7530_port_enable, 1318 .port_disable = mt7530_port_disable, 1319 .port_stp_state_set = mt7530_stp_state_set, 1320 .port_bridge_join = mt7530_port_bridge_join, 1321 .port_bridge_leave = mt7530_port_bridge_leave, 1322 .port_fdb_add = mt7530_port_fdb_add, 1323 .port_fdb_del = mt7530_port_fdb_del, 1324 .port_fdb_dump = mt7530_port_fdb_dump, 1325 .port_vlan_filtering = mt7530_port_vlan_filtering, 1326 .port_vlan_prepare = mt7530_port_vlan_prepare, 1327 .port_vlan_add = mt7530_port_vlan_add, 1328 .port_vlan_del = mt7530_port_vlan_del, 1329 }; 1330 1331 static const struct of_device_id mt7530_of_match[] = { 1332 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, }, 1333 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, }, 1334 { /* sentinel */ }, 1335 }; 1336 MODULE_DEVICE_TABLE(of, mt7530_of_match); 1337 1338 static int 1339 mt7530_probe(struct mdio_device *mdiodev) 1340 { 1341 struct mt7530_priv *priv; 1342 struct device_node *dn; 1343 1344 dn = mdiodev->dev.of_node; 1345 1346 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1347 if (!priv) 1348 return -ENOMEM; 1349 1350 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS); 1351 if (!priv->ds) 1352 return -ENOMEM; 1353 1354 /* Use medatek,mcm property to distinguish hardware type that would 1355 * casues a little bit differences on power-on sequence. 1356 */ 1357 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 1358 if (priv->mcm) { 1359 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 1360 1361 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 1362 if (IS_ERR(priv->rstc)) { 1363 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1364 return PTR_ERR(priv->rstc); 1365 } 1366 } 1367 1368 /* Get the hardware identifier from the devicetree node. 1369 * We will need it for some of the clock and regulator setup. 1370 */ 1371 priv->id = (unsigned int)(unsigned long) 1372 of_device_get_match_data(&mdiodev->dev); 1373 1374 if (priv->id == ID_MT7530) { 1375 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 1376 if (IS_ERR(priv->core_pwr)) 1377 return PTR_ERR(priv->core_pwr); 1378 1379 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 1380 if (IS_ERR(priv->io_pwr)) 1381 return PTR_ERR(priv->io_pwr); 1382 } 1383 1384 /* Not MCM that indicates switch works as the remote standalone 1385 * integrated circuit so the GPIO pin would be used to complete 1386 * the reset, otherwise memory-mapped register accessing used 1387 * through syscon provides in the case of MCM. 1388 */ 1389 if (!priv->mcm) { 1390 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 1391 GPIOD_OUT_LOW); 1392 if (IS_ERR(priv->reset)) { 1393 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1394 return PTR_ERR(priv->reset); 1395 } 1396 } 1397 1398 priv->bus = mdiodev->bus; 1399 priv->dev = &mdiodev->dev; 1400 priv->ds->priv = priv; 1401 priv->ds->ops = &mt7530_switch_ops; 1402 mutex_init(&priv->reg_mutex); 1403 dev_set_drvdata(&mdiodev->dev, priv); 1404 1405 return dsa_register_switch(priv->ds); 1406 } 1407 1408 static void 1409 mt7530_remove(struct mdio_device *mdiodev) 1410 { 1411 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 1412 int ret = 0; 1413 1414 ret = regulator_disable(priv->core_pwr); 1415 if (ret < 0) 1416 dev_err(priv->dev, 1417 "Failed to disable core power: %d\n", ret); 1418 1419 ret = regulator_disable(priv->io_pwr); 1420 if (ret < 0) 1421 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 1422 ret); 1423 1424 dsa_unregister_switch(priv->ds); 1425 mutex_destroy(&priv->reg_mutex); 1426 } 1427 1428 static struct mdio_driver mt7530_mdio_driver = { 1429 .probe = mt7530_probe, 1430 .remove = mt7530_remove, 1431 .mdiodrv.driver = { 1432 .name = "mt7530", 1433 .of_match_table = mt7530_of_match, 1434 }, 1435 }; 1436 1437 mdio_module_driver(mt7530_mdio_driver); 1438 1439 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1440 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 1441 MODULE_LICENSE("GPL"); 1442