1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 /* String, offset, and register size in bytes if different from 4 bytes */ 28 static const struct mt7530_mib_desc mt7530_mib[] = { 29 MIB_DESC(1, 0x00, "TxDrop"), 30 MIB_DESC(1, 0x04, "TxCrcErr"), 31 MIB_DESC(1, 0x08, "TxUnicast"), 32 MIB_DESC(1, 0x0c, "TxMulticast"), 33 MIB_DESC(1, 0x10, "TxBroadcast"), 34 MIB_DESC(1, 0x14, "TxCollision"), 35 MIB_DESC(1, 0x18, "TxSingleCollision"), 36 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 37 MIB_DESC(1, 0x20, "TxDeferred"), 38 MIB_DESC(1, 0x24, "TxLateCollision"), 39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 40 MIB_DESC(1, 0x2c, "TxPause"), 41 MIB_DESC(1, 0x30, "TxPktSz64"), 42 MIB_DESC(1, 0x34, "TxPktSz65To127"), 43 MIB_DESC(1, 0x38, "TxPktSz128To255"), 44 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 45 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 46 MIB_DESC(1, 0x44, "Tx1024ToMax"), 47 MIB_DESC(2, 0x48, "TxBytes"), 48 MIB_DESC(1, 0x60, "RxDrop"), 49 MIB_DESC(1, 0x64, "RxFiltering"), 50 MIB_DESC(1, 0x68, "RxUnicast"), 51 MIB_DESC(1, 0x6c, "RxMulticast"), 52 MIB_DESC(1, 0x70, "RxBroadcast"), 53 MIB_DESC(1, 0x74, "RxAlignErr"), 54 MIB_DESC(1, 0x78, "RxCrcErr"), 55 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 56 MIB_DESC(1, 0x80, "RxFragErr"), 57 MIB_DESC(1, 0x84, "RxOverSzErr"), 58 MIB_DESC(1, 0x88, "RxJabberErr"), 59 MIB_DESC(1, 0x8c, "RxPause"), 60 MIB_DESC(1, 0x90, "RxPktSz64"), 61 MIB_DESC(1, 0x94, "RxPktSz65To127"), 62 MIB_DESC(1, 0x98, "RxPktSz128To255"), 63 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 64 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 65 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 66 MIB_DESC(2, 0xa8, "RxBytes"), 67 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 68 MIB_DESC(1, 0xb4, "RxIngressDrop"), 69 MIB_DESC(1, 0xb8, "RxArlDrop"), 70 }; 71 72 /* Since phy_device has not yet been created and 73 * phy_{read,write}_mmd_indirect is not available, we provide our own 74 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 75 * to complete this function. 76 */ 77 static int 78 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 79 { 80 struct mii_bus *bus = priv->bus; 81 int value, ret; 82 83 /* Write the desired MMD Devad */ 84 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 85 if (ret < 0) 86 goto err; 87 88 /* Write the desired MMD register address */ 89 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 90 if (ret < 0) 91 goto err; 92 93 /* Select the Function : DATA with no post increment */ 94 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 95 if (ret < 0) 96 goto err; 97 98 /* Read the content of the MMD's selected register */ 99 value = bus->read(bus, 0, MII_MMD_DATA); 100 101 return value; 102 err: 103 dev_err(&bus->dev, "failed to read mmd register\n"); 104 105 return ret; 106 } 107 108 static int 109 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 110 int devad, u32 data) 111 { 112 struct mii_bus *bus = priv->bus; 113 int ret; 114 115 /* Write the desired MMD Devad */ 116 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 117 if (ret < 0) 118 goto err; 119 120 /* Write the desired MMD register address */ 121 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 122 if (ret < 0) 123 goto err; 124 125 /* Select the Function : DATA with no post increment */ 126 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 127 if (ret < 0) 128 goto err; 129 130 /* Write the data into MMD's selected register */ 131 ret = bus->write(bus, 0, MII_MMD_DATA, data); 132 err: 133 if (ret < 0) 134 dev_err(&bus->dev, 135 "failed to write mmd register\n"); 136 return ret; 137 } 138 139 static void 140 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 141 { 142 struct mii_bus *bus = priv->bus; 143 144 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 145 146 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 147 148 mutex_unlock(&bus->mdio_lock); 149 } 150 151 static void 152 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 153 { 154 struct mii_bus *bus = priv->bus; 155 u32 val; 156 157 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 158 159 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 160 val &= ~mask; 161 val |= set; 162 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 163 164 mutex_unlock(&bus->mdio_lock); 165 } 166 167 static void 168 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 169 { 170 core_rmw(priv, reg, 0, val); 171 } 172 173 static void 174 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 175 { 176 core_rmw(priv, reg, val, 0); 177 } 178 179 static int 180 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 181 { 182 struct mii_bus *bus = priv->bus; 183 u16 page, r, lo, hi; 184 int ret; 185 186 page = (reg >> 6) & 0x3ff; 187 r = (reg >> 2) & 0xf; 188 lo = val & 0xffff; 189 hi = val >> 16; 190 191 /* MT7530 uses 31 as the pseudo port */ 192 ret = bus->write(bus, 0x1f, 0x1f, page); 193 if (ret < 0) 194 goto err; 195 196 ret = bus->write(bus, 0x1f, r, lo); 197 if (ret < 0) 198 goto err; 199 200 ret = bus->write(bus, 0x1f, 0x10, hi); 201 err: 202 if (ret < 0) 203 dev_err(&bus->dev, 204 "failed to write mt7530 register\n"); 205 return ret; 206 } 207 208 static u32 209 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 210 { 211 struct mii_bus *bus = priv->bus; 212 u16 page, r, lo, hi; 213 int ret; 214 215 page = (reg >> 6) & 0x3ff; 216 r = (reg >> 2) & 0xf; 217 218 /* MT7530 uses 31 as the pseudo port */ 219 ret = bus->write(bus, 0x1f, 0x1f, page); 220 if (ret < 0) { 221 dev_err(&bus->dev, 222 "failed to read mt7530 register\n"); 223 return ret; 224 } 225 226 lo = bus->read(bus, 0x1f, r); 227 hi = bus->read(bus, 0x1f, 0x10); 228 229 return (hi << 16) | (lo & 0xffff); 230 } 231 232 static void 233 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 234 { 235 struct mii_bus *bus = priv->bus; 236 237 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 238 239 mt7530_mii_write(priv, reg, val); 240 241 mutex_unlock(&bus->mdio_lock); 242 } 243 244 static u32 245 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 246 { 247 return mt7530_mii_read(p->priv, p->reg); 248 } 249 250 static u32 251 _mt7530_read(struct mt7530_dummy_poll *p) 252 { 253 struct mii_bus *bus = p->priv->bus; 254 u32 val; 255 256 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 257 258 val = mt7530_mii_read(p->priv, p->reg); 259 260 mutex_unlock(&bus->mdio_lock); 261 262 return val; 263 } 264 265 static u32 266 mt7530_read(struct mt7530_priv *priv, u32 reg) 267 { 268 struct mt7530_dummy_poll p; 269 270 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 271 return _mt7530_read(&p); 272 } 273 274 static void 275 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 276 u32 mask, u32 set) 277 { 278 struct mii_bus *bus = priv->bus; 279 u32 val; 280 281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 282 283 val = mt7530_mii_read(priv, reg); 284 val &= ~mask; 285 val |= set; 286 mt7530_mii_write(priv, reg, val); 287 288 mutex_unlock(&bus->mdio_lock); 289 } 290 291 static void 292 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 293 { 294 mt7530_rmw(priv, reg, 0, val); 295 } 296 297 static void 298 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 299 { 300 mt7530_rmw(priv, reg, val, 0); 301 } 302 303 static int 304 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 305 { 306 u32 val; 307 int ret; 308 struct mt7530_dummy_poll p; 309 310 /* Set the command operating upon the MAC address entries */ 311 val = ATC_BUSY | ATC_MAT(0) | cmd; 312 mt7530_write(priv, MT7530_ATC, val); 313 314 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 315 ret = readx_poll_timeout(_mt7530_read, &p, val, 316 !(val & ATC_BUSY), 20, 20000); 317 if (ret < 0) { 318 dev_err(priv->dev, "reset timeout\n"); 319 return ret; 320 } 321 322 /* Additional sanity for read command if the specified 323 * entry is invalid 324 */ 325 val = mt7530_read(priv, MT7530_ATC); 326 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 327 return -EINVAL; 328 329 if (rsp) 330 *rsp = val; 331 332 return 0; 333 } 334 335 static void 336 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 337 { 338 u32 reg[3]; 339 int i; 340 341 /* Read from ARL table into an array */ 342 for (i = 0; i < 3; i++) { 343 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 344 345 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 346 __func__, __LINE__, i, reg[i]); 347 } 348 349 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 350 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 351 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 352 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 353 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 354 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 355 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 356 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 357 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 358 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 359 } 360 361 static void 362 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 363 u8 port_mask, const u8 *mac, 364 u8 aging, u8 type) 365 { 366 u32 reg[3] = { 0 }; 367 int i; 368 369 reg[1] |= vid & CVID_MASK; 370 if (vid > 1) 371 reg[1] |= ATA2_IVL; 372 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 373 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 374 /* STATIC_ENT indicate that entry is static wouldn't 375 * be aged out and STATIC_EMP specified as erasing an 376 * entry 377 */ 378 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 379 reg[1] |= mac[5] << MAC_BYTE_5; 380 reg[1] |= mac[4] << MAC_BYTE_4; 381 reg[0] |= mac[3] << MAC_BYTE_3; 382 reg[0] |= mac[2] << MAC_BYTE_2; 383 reg[0] |= mac[1] << MAC_BYTE_1; 384 reg[0] |= mac[0] << MAC_BYTE_0; 385 386 /* Write array into the ARL table */ 387 for (i = 0; i < 3; i++) 388 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 389 } 390 391 /* Setup TX circuit including relevant PAD and driving */ 392 static int 393 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 394 { 395 struct mt7530_priv *priv = ds->priv; 396 u32 ncpo1, ssc_delta, trgint, i, xtal; 397 398 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 399 400 if (xtal == HWTRAP_XTAL_20MHZ) { 401 dev_err(priv->dev, 402 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 403 __func__); 404 return -EINVAL; 405 } 406 407 switch (interface) { 408 case PHY_INTERFACE_MODE_RGMII: 409 trgint = 0; 410 /* PLL frequency: 125MHz */ 411 ncpo1 = 0x0c80; 412 break; 413 case PHY_INTERFACE_MODE_TRGMII: 414 trgint = 1; 415 if (priv->id == ID_MT7621) { 416 /* PLL frequency: 150MHz: 1.2GBit */ 417 if (xtal == HWTRAP_XTAL_40MHZ) 418 ncpo1 = 0x0780; 419 if (xtal == HWTRAP_XTAL_25MHZ) 420 ncpo1 = 0x0a00; 421 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 422 if (xtal == HWTRAP_XTAL_40MHZ) 423 ncpo1 = 0x0c80; 424 if (xtal == HWTRAP_XTAL_25MHZ) 425 ncpo1 = 0x1400; 426 } 427 break; 428 default: 429 dev_err(priv->dev, "xMII interface %d not supported\n", 430 interface); 431 return -EINVAL; 432 } 433 434 if (xtal == HWTRAP_XTAL_25MHZ) 435 ssc_delta = 0x57; 436 else 437 ssc_delta = 0x87; 438 439 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 440 P6_INTF_MODE(trgint)); 441 442 /* Lower Tx Driving for TRGMII path */ 443 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 444 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 445 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 446 447 /* Disable MT7530 core and TRGMII Tx clocks */ 448 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 449 REG_GSWCK_EN | REG_TRGMIICK_EN); 450 451 /* Setup core clock for MT7530 */ 452 /* Disable PLL */ 453 core_write(priv, CORE_GSWPLL_GRP1, 0); 454 455 /* Set core clock into 500Mhz */ 456 core_write(priv, CORE_GSWPLL_GRP2, 457 RG_GSWPLL_POSDIV_500M(1) | 458 RG_GSWPLL_FBKDIV_500M(25)); 459 460 /* Enable PLL */ 461 core_write(priv, CORE_GSWPLL_GRP1, 462 RG_GSWPLL_EN_PRE | 463 RG_GSWPLL_POSDIV_200M(2) | 464 RG_GSWPLL_FBKDIV_200M(32)); 465 466 /* Setup the MT7530 TRGMII Tx Clock */ 467 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 468 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 469 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 470 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 471 core_write(priv, CORE_PLL_GROUP4, 472 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 473 RG_SYSPLL_BIAS_LPF_EN); 474 core_write(priv, CORE_PLL_GROUP2, 475 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 476 RG_SYSPLL_POSDIV(1)); 477 core_write(priv, CORE_PLL_GROUP7, 478 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 479 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 480 481 /* Enable MT7530 core and TRGMII Tx clocks */ 482 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 483 REG_GSWCK_EN | REG_TRGMIICK_EN); 484 485 if (!trgint) 486 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 487 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 488 RD_TAP_MASK, RD_TAP(16)); 489 return 0; 490 } 491 492 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 493 { 494 u32 val; 495 496 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 497 498 return (val & PAD_DUAL_SGMII_EN) != 0; 499 } 500 501 static int 502 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 503 { 504 struct mt7530_priv *priv = ds->priv; 505 u32 top_sig; 506 u32 hwstrap; 507 u32 xtal; 508 u32 val; 509 510 if (mt7531_dual_sgmii_supported(priv)) 511 return 0; 512 513 val = mt7530_read(priv, MT7531_CREV); 514 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 515 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 516 if ((val & CHIP_REV_M) > 0) 517 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 518 HWTRAP_XTAL_FSEL_25MHZ; 519 else 520 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 521 522 /* Step 1 : Disable MT7531 COREPLL */ 523 val = mt7530_read(priv, MT7531_PLLGP_EN); 524 val &= ~EN_COREPLL; 525 mt7530_write(priv, MT7531_PLLGP_EN, val); 526 527 /* Step 2: switch to XTAL output */ 528 val = mt7530_read(priv, MT7531_PLLGP_EN); 529 val |= SW_CLKSW; 530 mt7530_write(priv, MT7531_PLLGP_EN, val); 531 532 val = mt7530_read(priv, MT7531_PLLGP_CR0); 533 val &= ~RG_COREPLL_EN; 534 mt7530_write(priv, MT7531_PLLGP_CR0, val); 535 536 /* Step 3: disable PLLGP and enable program PLLGP */ 537 val = mt7530_read(priv, MT7531_PLLGP_EN); 538 val |= SW_PLLGP; 539 mt7530_write(priv, MT7531_PLLGP_EN, val); 540 541 /* Step 4: program COREPLL output frequency to 500MHz */ 542 val = mt7530_read(priv, MT7531_PLLGP_CR0); 543 val &= ~RG_COREPLL_POSDIV_M; 544 val |= 2 << RG_COREPLL_POSDIV_S; 545 mt7530_write(priv, MT7531_PLLGP_CR0, val); 546 usleep_range(25, 35); 547 548 switch (xtal) { 549 case HWTRAP_XTAL_FSEL_25MHZ: 550 val = mt7530_read(priv, MT7531_PLLGP_CR0); 551 val &= ~RG_COREPLL_SDM_PCW_M; 552 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 553 mt7530_write(priv, MT7531_PLLGP_CR0, val); 554 break; 555 case HWTRAP_XTAL_FSEL_40MHZ: 556 val = mt7530_read(priv, MT7531_PLLGP_CR0); 557 val &= ~RG_COREPLL_SDM_PCW_M; 558 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 559 mt7530_write(priv, MT7531_PLLGP_CR0, val); 560 break; 561 } 562 563 /* Set feedback divide ratio update signal to high */ 564 val = mt7530_read(priv, MT7531_PLLGP_CR0); 565 val |= RG_COREPLL_SDM_PCW_CHG; 566 mt7530_write(priv, MT7531_PLLGP_CR0, val); 567 /* Wait for at least 16 XTAL clocks */ 568 usleep_range(10, 20); 569 570 /* Step 5: set feedback divide ratio update signal to low */ 571 val = mt7530_read(priv, MT7531_PLLGP_CR0); 572 val &= ~RG_COREPLL_SDM_PCW_CHG; 573 mt7530_write(priv, MT7531_PLLGP_CR0, val); 574 575 /* Enable 325M clock for SGMII */ 576 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 577 578 /* Enable 250SSC clock for RGMII */ 579 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 580 581 /* Step 6: Enable MT7531 PLL */ 582 val = mt7530_read(priv, MT7531_PLLGP_CR0); 583 val |= RG_COREPLL_EN; 584 mt7530_write(priv, MT7531_PLLGP_CR0, val); 585 586 val = mt7530_read(priv, MT7531_PLLGP_EN); 587 val |= EN_COREPLL; 588 mt7530_write(priv, MT7531_PLLGP_EN, val); 589 usleep_range(25, 35); 590 591 return 0; 592 } 593 594 static void 595 mt7530_mib_reset(struct dsa_switch *ds) 596 { 597 struct mt7530_priv *priv = ds->priv; 598 599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 601 } 602 603 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 604 { 605 return mdiobus_read_nested(priv->bus, port, regnum); 606 } 607 608 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 609 u16 val) 610 { 611 return mdiobus_write_nested(priv->bus, port, regnum, val); 612 } 613 614 static int 615 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 616 int regnum) 617 { 618 struct mii_bus *bus = priv->bus; 619 struct mt7530_dummy_poll p; 620 u32 reg, val; 621 int ret; 622 623 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 624 625 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 626 627 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 628 !(val & MT7531_PHY_ACS_ST), 20, 100000); 629 if (ret < 0) { 630 dev_err(priv->dev, "poll timeout\n"); 631 goto out; 632 } 633 634 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 635 MT7531_MDIO_DEV_ADDR(devad) | regnum; 636 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 637 638 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 639 !(val & MT7531_PHY_ACS_ST), 20, 100000); 640 if (ret < 0) { 641 dev_err(priv->dev, "poll timeout\n"); 642 goto out; 643 } 644 645 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 646 MT7531_MDIO_DEV_ADDR(devad); 647 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 648 649 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 650 !(val & MT7531_PHY_ACS_ST), 20, 100000); 651 if (ret < 0) { 652 dev_err(priv->dev, "poll timeout\n"); 653 goto out; 654 } 655 656 ret = val & MT7531_MDIO_RW_DATA_MASK; 657 out: 658 mutex_unlock(&bus->mdio_lock); 659 660 return ret; 661 } 662 663 static int 664 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 665 int regnum, u32 data) 666 { 667 struct mii_bus *bus = priv->bus; 668 struct mt7530_dummy_poll p; 669 u32 val, reg; 670 int ret; 671 672 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 673 674 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 675 676 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 677 !(val & MT7531_PHY_ACS_ST), 20, 100000); 678 if (ret < 0) { 679 dev_err(priv->dev, "poll timeout\n"); 680 goto out; 681 } 682 683 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 684 MT7531_MDIO_DEV_ADDR(devad) | regnum; 685 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | data; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 out: 706 mutex_unlock(&bus->mdio_lock); 707 708 return ret; 709 } 710 711 static int 712 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 713 { 714 struct mii_bus *bus = priv->bus; 715 struct mt7530_dummy_poll p; 716 int ret; 717 u32 val; 718 719 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 720 721 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 722 723 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 724 !(val & MT7531_PHY_ACS_ST), 20, 100000); 725 if (ret < 0) { 726 dev_err(priv->dev, "poll timeout\n"); 727 goto out; 728 } 729 730 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 731 MT7531_MDIO_REG_ADDR(regnum); 732 733 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 734 735 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 736 !(val & MT7531_PHY_ACS_ST), 20, 100000); 737 if (ret < 0) { 738 dev_err(priv->dev, "poll timeout\n"); 739 goto out; 740 } 741 742 ret = val & MT7531_MDIO_RW_DATA_MASK; 743 out: 744 mutex_unlock(&bus->mdio_lock); 745 746 return ret; 747 } 748 749 static int 750 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 751 u16 data) 752 { 753 struct mii_bus *bus = priv->bus; 754 struct mt7530_dummy_poll p; 755 int ret; 756 u32 reg; 757 758 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 759 760 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 761 762 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 763 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 764 if (ret < 0) { 765 dev_err(priv->dev, "poll timeout\n"); 766 goto out; 767 } 768 769 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 770 MT7531_MDIO_REG_ADDR(regnum) | data; 771 772 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 773 774 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 775 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 776 if (ret < 0) { 777 dev_err(priv->dev, "poll timeout\n"); 778 goto out; 779 } 780 781 out: 782 mutex_unlock(&bus->mdio_lock); 783 784 return ret; 785 } 786 787 static int 788 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 789 { 790 int devad; 791 int ret; 792 793 if (regnum & MII_ADDR_C45) { 794 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 795 ret = mt7531_ind_c45_phy_read(priv, port, devad, 796 regnum & MII_REGADDR_C45_MASK); 797 } else { 798 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 799 } 800 801 return ret; 802 } 803 804 static int 805 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 806 u16 data) 807 { 808 int devad; 809 int ret; 810 811 if (regnum & MII_ADDR_C45) { 812 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 813 ret = mt7531_ind_c45_phy_write(priv, port, devad, 814 regnum & MII_REGADDR_C45_MASK, 815 data); 816 } else { 817 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 818 } 819 820 return ret; 821 } 822 823 static int 824 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 825 { 826 struct mt7530_priv *priv = bus->priv; 827 828 return priv->info->phy_read(priv, port, regnum); 829 } 830 831 static int 832 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 833 { 834 struct mt7530_priv *priv = bus->priv; 835 836 return priv->info->phy_write(priv, port, regnum, val); 837 } 838 839 static void 840 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 841 uint8_t *data) 842 { 843 int i; 844 845 if (stringset != ETH_SS_STATS) 846 return; 847 848 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 849 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 850 ETH_GSTRING_LEN); 851 } 852 853 static void 854 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 855 uint64_t *data) 856 { 857 struct mt7530_priv *priv = ds->priv; 858 const struct mt7530_mib_desc *mib; 859 u32 reg, i; 860 u64 hi; 861 862 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 863 mib = &mt7530_mib[i]; 864 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 865 866 data[i] = mt7530_read(priv, reg); 867 if (mib->size == 2) { 868 hi = mt7530_read(priv, reg + 4); 869 data[i] |= hi << 32; 870 } 871 } 872 } 873 874 static int 875 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 876 { 877 if (sset != ETH_SS_STATS) 878 return 0; 879 880 return ARRAY_SIZE(mt7530_mib); 881 } 882 883 static int 884 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 885 { 886 struct mt7530_priv *priv = ds->priv; 887 unsigned int secs = msecs / 1000; 888 unsigned int tmp_age_count; 889 unsigned int error = -1; 890 unsigned int age_count; 891 unsigned int age_unit; 892 893 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 894 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 895 return -ERANGE; 896 897 /* iterate through all possible age_count to find the closest pair */ 898 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 899 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 900 901 if (tmp_age_unit <= AGE_UNIT_MAX) { 902 unsigned int tmp_error = secs - 903 (tmp_age_count + 1) * (tmp_age_unit + 1); 904 905 /* found a closer pair */ 906 if (error > tmp_error) { 907 error = tmp_error; 908 age_count = tmp_age_count; 909 age_unit = tmp_age_unit; 910 } 911 912 /* found the exact match, so break the loop */ 913 if (!error) 914 break; 915 } 916 } 917 918 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 919 920 return 0; 921 } 922 923 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 924 { 925 struct mt7530_priv *priv = ds->priv; 926 u8 tx_delay = 0; 927 int val; 928 929 mutex_lock(&priv->reg_mutex); 930 931 val = mt7530_read(priv, MT7530_MHWTRAP); 932 933 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 934 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 935 936 switch (priv->p5_intf_sel) { 937 case P5_INTF_SEL_PHY_P0: 938 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 939 val |= MHWTRAP_PHY0_SEL; 940 fallthrough; 941 case P5_INTF_SEL_PHY_P4: 942 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 943 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 944 945 /* Setup the MAC by default for the cpu port */ 946 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 947 break; 948 case P5_INTF_SEL_GMAC5: 949 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 950 val &= ~MHWTRAP_P5_DIS; 951 break; 952 case P5_DISABLED: 953 interface = PHY_INTERFACE_MODE_NA; 954 break; 955 default: 956 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 957 priv->p5_intf_sel); 958 goto unlock_exit; 959 } 960 961 /* Setup RGMII settings */ 962 if (phy_interface_mode_is_rgmii(interface)) { 963 val |= MHWTRAP_P5_RGMII_MODE; 964 965 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 966 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 967 968 /* Don't set delay in DSA mode */ 969 if (!dsa_is_dsa_port(priv->ds, 5) && 970 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 971 interface == PHY_INTERFACE_MODE_RGMII_ID)) 972 tx_delay = 4; /* n * 0.5 ns */ 973 974 /* P5 RGMII TX Clock Control: delay x */ 975 mt7530_write(priv, MT7530_P5RGMIITXCR, 976 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 977 978 /* reduce P5 RGMII Tx driving, 8mA */ 979 mt7530_write(priv, MT7530_IO_DRV_CR, 980 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 981 } 982 983 mt7530_write(priv, MT7530_MHWTRAP, val); 984 985 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 986 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 987 988 priv->p5_interface = interface; 989 990 unlock_exit: 991 mutex_unlock(&priv->reg_mutex); 992 } 993 994 static int 995 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 996 { 997 struct mt7530_priv *priv = ds->priv; 998 int ret; 999 1000 /* Setup max capability of CPU port at first */ 1001 if (priv->info->cpu_port_config) { 1002 ret = priv->info->cpu_port_config(ds, port); 1003 if (ret) 1004 return ret; 1005 } 1006 1007 /* Enable Mediatek header mode on the cpu port */ 1008 mt7530_write(priv, MT7530_PVC_P(port), 1009 PORT_SPEC_TAG); 1010 1011 /* Disable flooding by default */ 1012 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1013 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1014 1015 /* Set CPU port number */ 1016 if (priv->id == ID_MT7621) 1017 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1018 1019 /* CPU port gets connected to all user ports of 1020 * the switch. 1021 */ 1022 mt7530_write(priv, MT7530_PCR_P(port), 1023 PCR_MATRIX(dsa_user_ports(priv->ds))); 1024 1025 return 0; 1026 } 1027 1028 static int 1029 mt7530_port_enable(struct dsa_switch *ds, int port, 1030 struct phy_device *phy) 1031 { 1032 struct mt7530_priv *priv = ds->priv; 1033 1034 if (!dsa_is_user_port(ds, port)) 1035 return 0; 1036 1037 mutex_lock(&priv->reg_mutex); 1038 1039 /* Allow the user port gets connected to the cpu port and also 1040 * restore the port matrix if the port is the member of a certain 1041 * bridge. 1042 */ 1043 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1044 priv->ports[port].enable = true; 1045 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1046 priv->ports[port].pm); 1047 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1048 1049 mutex_unlock(&priv->reg_mutex); 1050 1051 return 0; 1052 } 1053 1054 static void 1055 mt7530_port_disable(struct dsa_switch *ds, int port) 1056 { 1057 struct mt7530_priv *priv = ds->priv; 1058 1059 if (!dsa_is_user_port(ds, port)) 1060 return; 1061 1062 mutex_lock(&priv->reg_mutex); 1063 1064 /* Clear up all port matrix which could be restored in the next 1065 * enablement for the port. 1066 */ 1067 priv->ports[port].enable = false; 1068 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1069 PCR_MATRIX_CLR); 1070 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1071 1072 mutex_unlock(&priv->reg_mutex); 1073 } 1074 1075 static int 1076 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1077 { 1078 struct mt7530_priv *priv = ds->priv; 1079 struct mii_bus *bus = priv->bus; 1080 int length; 1081 u32 val; 1082 1083 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1084 * largest MTU of the slave ports. Because the switch only has a global 1085 * RX length register, only allowing CPU port here is enough. 1086 */ 1087 if (!dsa_is_cpu_port(ds, port)) 1088 return 0; 1089 1090 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1091 1092 val = mt7530_mii_read(priv, MT7530_GMACCR); 1093 val &= ~MAX_RX_PKT_LEN_MASK; 1094 1095 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1096 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1097 if (length <= 1522) { 1098 val |= MAX_RX_PKT_LEN_1522; 1099 } else if (length <= 1536) { 1100 val |= MAX_RX_PKT_LEN_1536; 1101 } else if (length <= 1552) { 1102 val |= MAX_RX_PKT_LEN_1552; 1103 } else { 1104 val &= ~MAX_RX_JUMBO_MASK; 1105 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1106 val |= MAX_RX_PKT_LEN_JUMBO; 1107 } 1108 1109 mt7530_mii_write(priv, MT7530_GMACCR, val); 1110 1111 mutex_unlock(&bus->mdio_lock); 1112 1113 return 0; 1114 } 1115 1116 static int 1117 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1118 { 1119 return MT7530_MAX_MTU; 1120 } 1121 1122 static void 1123 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1124 { 1125 struct mt7530_priv *priv = ds->priv; 1126 u32 stp_state; 1127 1128 switch (state) { 1129 case BR_STATE_DISABLED: 1130 stp_state = MT7530_STP_DISABLED; 1131 break; 1132 case BR_STATE_BLOCKING: 1133 stp_state = MT7530_STP_BLOCKING; 1134 break; 1135 case BR_STATE_LISTENING: 1136 stp_state = MT7530_STP_LISTENING; 1137 break; 1138 case BR_STATE_LEARNING: 1139 stp_state = MT7530_STP_LEARNING; 1140 break; 1141 case BR_STATE_FORWARDING: 1142 default: 1143 stp_state = MT7530_STP_FORWARDING; 1144 break; 1145 } 1146 1147 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 1148 } 1149 1150 static int 1151 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1152 struct switchdev_brport_flags flags, 1153 struct netlink_ext_ack *extack) 1154 { 1155 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1156 BR_BCAST_FLOOD)) 1157 return -EINVAL; 1158 1159 return 0; 1160 } 1161 1162 static int 1163 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1164 struct switchdev_brport_flags flags, 1165 struct netlink_ext_ack *extack) 1166 { 1167 struct mt7530_priv *priv = ds->priv; 1168 1169 if (flags.mask & BR_LEARNING) 1170 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1171 flags.val & BR_LEARNING ? 0 : SA_DIS); 1172 1173 if (flags.mask & BR_FLOOD) 1174 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1175 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1176 1177 if (flags.mask & BR_MCAST_FLOOD) 1178 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1179 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1180 1181 if (flags.mask & BR_BCAST_FLOOD) 1182 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1183 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1184 1185 return 0; 1186 } 1187 1188 static int 1189 mt7530_port_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 1190 struct netlink_ext_ack *extack) 1191 { 1192 struct mt7530_priv *priv = ds->priv; 1193 1194 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1195 mrouter ? UNM_FFP(BIT(port)) : 0); 1196 1197 return 0; 1198 } 1199 1200 static int 1201 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1202 struct net_device *bridge) 1203 { 1204 struct mt7530_priv *priv = ds->priv; 1205 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1206 int i; 1207 1208 mutex_lock(&priv->reg_mutex); 1209 1210 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1211 /* Add this port to the port matrix of the other ports in the 1212 * same bridge. If the port is disabled, port matrix is kept 1213 * and not being setup until the port becomes enabled. 1214 */ 1215 if (dsa_is_user_port(ds, i) && i != port) { 1216 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1217 continue; 1218 if (priv->ports[i].enable) 1219 mt7530_set(priv, MT7530_PCR_P(i), 1220 PCR_MATRIX(BIT(port))); 1221 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1222 1223 port_bitmap |= BIT(i); 1224 } 1225 } 1226 1227 /* Add the all other ports to this port matrix. */ 1228 if (priv->ports[port].enable) 1229 mt7530_rmw(priv, MT7530_PCR_P(port), 1230 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1231 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1232 1233 mutex_unlock(&priv->reg_mutex); 1234 1235 return 0; 1236 } 1237 1238 static void 1239 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1240 { 1241 struct mt7530_priv *priv = ds->priv; 1242 bool all_user_ports_removed = true; 1243 int i; 1244 1245 /* When a port is removed from the bridge, the port would be set up 1246 * back to the default as is at initial boot which is a VLAN-unaware 1247 * port. 1248 */ 1249 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1250 MT7530_PORT_MATRIX_MODE); 1251 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1252 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1253 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1254 1255 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1256 if (dsa_is_user_port(ds, i) && 1257 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1258 all_user_ports_removed = false; 1259 break; 1260 } 1261 } 1262 1263 /* CPU port also does the same thing until all user ports belonging to 1264 * the CPU port get out of VLAN filtering mode. 1265 */ 1266 if (all_user_ports_removed) { 1267 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1268 PCR_MATRIX(dsa_user_ports(priv->ds))); 1269 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1270 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1271 } 1272 } 1273 1274 static void 1275 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1276 { 1277 struct mt7530_priv *priv = ds->priv; 1278 1279 /* Trapped into security mode allows packet forwarding through VLAN 1280 * table lookup. CPU port is set to fallback mode to let untagged 1281 * frames pass through. 1282 */ 1283 if (dsa_is_cpu_port(ds, port)) 1284 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1285 MT7530_PORT_FALLBACK_MODE); 1286 else 1287 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1288 MT7530_PORT_SECURITY_MODE); 1289 1290 /* Set the port as a user port which is to be able to recognize VID 1291 * from incoming packets before fetching entry within the VLAN table. 1292 */ 1293 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1294 VLAN_ATTR(MT7530_VLAN_USER) | 1295 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1296 } 1297 1298 static void 1299 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1300 struct net_device *bridge) 1301 { 1302 struct mt7530_priv *priv = ds->priv; 1303 int i; 1304 1305 mutex_lock(&priv->reg_mutex); 1306 1307 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1308 /* Remove this port from the port matrix of the other ports 1309 * in the same bridge. If the port is disabled, port matrix 1310 * is kept and not being setup until the port becomes enabled. 1311 * And the other port's port matrix cannot be broken when the 1312 * other port is still a VLAN-aware port. 1313 */ 1314 if (dsa_is_user_port(ds, i) && i != port && 1315 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1316 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1317 continue; 1318 if (priv->ports[i].enable) 1319 mt7530_clear(priv, MT7530_PCR_P(i), 1320 PCR_MATRIX(BIT(port))); 1321 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1322 } 1323 } 1324 1325 /* Set the cpu port to be the only one in the port matrix of 1326 * this port. 1327 */ 1328 if (priv->ports[port].enable) 1329 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1330 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1331 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1332 1333 mutex_unlock(&priv->reg_mutex); 1334 } 1335 1336 static int 1337 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1338 const unsigned char *addr, u16 vid) 1339 { 1340 struct mt7530_priv *priv = ds->priv; 1341 int ret; 1342 u8 port_mask = BIT(port); 1343 1344 mutex_lock(&priv->reg_mutex); 1345 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1346 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1347 mutex_unlock(&priv->reg_mutex); 1348 1349 return ret; 1350 } 1351 1352 static int 1353 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1354 const unsigned char *addr, u16 vid) 1355 { 1356 struct mt7530_priv *priv = ds->priv; 1357 int ret; 1358 u8 port_mask = BIT(port); 1359 1360 mutex_lock(&priv->reg_mutex); 1361 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1362 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1363 mutex_unlock(&priv->reg_mutex); 1364 1365 return ret; 1366 } 1367 1368 static int 1369 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1370 dsa_fdb_dump_cb_t *cb, void *data) 1371 { 1372 struct mt7530_priv *priv = ds->priv; 1373 struct mt7530_fdb _fdb = { 0 }; 1374 int cnt = MT7530_NUM_FDB_RECORDS; 1375 int ret = 0; 1376 u32 rsp = 0; 1377 1378 mutex_lock(&priv->reg_mutex); 1379 1380 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1381 if (ret < 0) 1382 goto err; 1383 1384 do { 1385 if (rsp & ATC_SRCH_HIT) { 1386 mt7530_fdb_read(priv, &_fdb); 1387 if (_fdb.port_mask & BIT(port)) { 1388 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1389 data); 1390 if (ret < 0) 1391 break; 1392 } 1393 } 1394 } while (--cnt && 1395 !(rsp & ATC_SRCH_END) && 1396 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1397 err: 1398 mutex_unlock(&priv->reg_mutex); 1399 1400 return 0; 1401 } 1402 1403 static int 1404 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1405 const struct switchdev_obj_port_mdb *mdb) 1406 { 1407 struct mt7530_priv *priv = ds->priv; 1408 const u8 *addr = mdb->addr; 1409 u16 vid = mdb->vid; 1410 u8 port_mask = 0; 1411 int ret; 1412 1413 mutex_lock(&priv->reg_mutex); 1414 1415 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1416 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1417 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1418 & PORT_MAP_MASK; 1419 1420 port_mask |= BIT(port); 1421 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1422 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1423 1424 mutex_unlock(&priv->reg_mutex); 1425 1426 return ret; 1427 } 1428 1429 static int 1430 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1431 const struct switchdev_obj_port_mdb *mdb) 1432 { 1433 struct mt7530_priv *priv = ds->priv; 1434 const u8 *addr = mdb->addr; 1435 u16 vid = mdb->vid; 1436 u8 port_mask = 0; 1437 int ret; 1438 1439 mutex_lock(&priv->reg_mutex); 1440 1441 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1442 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1443 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1444 & PORT_MAP_MASK; 1445 1446 port_mask &= ~BIT(port); 1447 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1448 port_mask ? STATIC_ENT : STATIC_EMP); 1449 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1450 1451 mutex_unlock(&priv->reg_mutex); 1452 1453 return ret; 1454 } 1455 1456 static int 1457 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1458 { 1459 struct mt7530_dummy_poll p; 1460 u32 val; 1461 int ret; 1462 1463 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1464 mt7530_write(priv, MT7530_VTCR, val); 1465 1466 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1467 ret = readx_poll_timeout(_mt7530_read, &p, val, 1468 !(val & VTCR_BUSY), 20, 20000); 1469 if (ret < 0) { 1470 dev_err(priv->dev, "poll timeout\n"); 1471 return ret; 1472 } 1473 1474 val = mt7530_read(priv, MT7530_VTCR); 1475 if (val & VTCR_INVALID) { 1476 dev_err(priv->dev, "read VTCR invalid\n"); 1477 return -EINVAL; 1478 } 1479 1480 return 0; 1481 } 1482 1483 static int 1484 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1485 struct netlink_ext_ack *extack) 1486 { 1487 if (vlan_filtering) { 1488 /* The port is being kept as VLAN-unaware port when bridge is 1489 * set up with vlan_filtering not being set, Otherwise, the 1490 * port and the corresponding CPU port is required the setup 1491 * for becoming a VLAN-aware port. 1492 */ 1493 mt7530_port_set_vlan_aware(ds, port); 1494 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1495 } else { 1496 mt7530_port_set_vlan_unaware(ds, port); 1497 } 1498 1499 return 0; 1500 } 1501 1502 static void 1503 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1504 struct mt7530_hw_vlan_entry *entry) 1505 { 1506 u8 new_members; 1507 u32 val; 1508 1509 new_members = entry->old_members | BIT(entry->port) | 1510 BIT(MT7530_CPU_PORT); 1511 1512 /* Validate the entry with independent learning, create egress tag per 1513 * VLAN and joining the port as one of the port members. 1514 */ 1515 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1516 mt7530_write(priv, MT7530_VAWD1, val); 1517 1518 /* Decide whether adding tag or not for those outgoing packets from the 1519 * port inside the VLAN. 1520 */ 1521 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1522 MT7530_VLAN_EGRESS_TAG; 1523 mt7530_rmw(priv, MT7530_VAWD2, 1524 ETAG_CTRL_P_MASK(entry->port), 1525 ETAG_CTRL_P(entry->port, val)); 1526 1527 /* CPU port is always taken as a tagged port for serving more than one 1528 * VLANs across and also being applied with egress type stack mode for 1529 * that VLAN tags would be appended after hardware special tag used as 1530 * DSA tag. 1531 */ 1532 mt7530_rmw(priv, MT7530_VAWD2, 1533 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1534 ETAG_CTRL_P(MT7530_CPU_PORT, 1535 MT7530_VLAN_EGRESS_STACK)); 1536 } 1537 1538 static void 1539 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1540 struct mt7530_hw_vlan_entry *entry) 1541 { 1542 u8 new_members; 1543 u32 val; 1544 1545 new_members = entry->old_members & ~BIT(entry->port); 1546 1547 val = mt7530_read(priv, MT7530_VAWD1); 1548 if (!(val & VLAN_VALID)) { 1549 dev_err(priv->dev, 1550 "Cannot be deleted due to invalid entry\n"); 1551 return; 1552 } 1553 1554 /* If certain member apart from CPU port is still alive in the VLAN, 1555 * the entry would be kept valid. Otherwise, the entry is got to be 1556 * disabled. 1557 */ 1558 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1559 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1560 VLAN_VALID; 1561 mt7530_write(priv, MT7530_VAWD1, val); 1562 } else { 1563 mt7530_write(priv, MT7530_VAWD1, 0); 1564 mt7530_write(priv, MT7530_VAWD2, 0); 1565 } 1566 } 1567 1568 static void 1569 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1570 struct mt7530_hw_vlan_entry *entry, 1571 mt7530_vlan_op vlan_op) 1572 { 1573 u32 val; 1574 1575 /* Fetch entry */ 1576 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1577 1578 val = mt7530_read(priv, MT7530_VAWD1); 1579 1580 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1581 1582 /* Manipulate entry */ 1583 vlan_op(priv, entry); 1584 1585 /* Flush result to hardware */ 1586 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1587 } 1588 1589 static int 1590 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1591 const struct switchdev_obj_port_vlan *vlan, 1592 struct netlink_ext_ack *extack) 1593 { 1594 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1595 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1596 struct mt7530_hw_vlan_entry new_entry; 1597 struct mt7530_priv *priv = ds->priv; 1598 1599 mutex_lock(&priv->reg_mutex); 1600 1601 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1602 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1603 1604 if (pvid) { 1605 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1606 G0_PORT_VID(vlan->vid)); 1607 priv->ports[port].pvid = vlan->vid; 1608 } 1609 1610 mutex_unlock(&priv->reg_mutex); 1611 1612 return 0; 1613 } 1614 1615 static int 1616 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1617 const struct switchdev_obj_port_vlan *vlan) 1618 { 1619 struct mt7530_hw_vlan_entry target_entry; 1620 struct mt7530_priv *priv = ds->priv; 1621 u16 pvid; 1622 1623 mutex_lock(&priv->reg_mutex); 1624 1625 pvid = priv->ports[port].pvid; 1626 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1627 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1628 mt7530_hw_vlan_del); 1629 1630 /* PVID is being restored to the default whenever the PVID port 1631 * is being removed from the VLAN. 1632 */ 1633 if (pvid == vlan->vid) 1634 pvid = G0_PORT_VID_DEF; 1635 1636 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1637 priv->ports[port].pvid = pvid; 1638 1639 mutex_unlock(&priv->reg_mutex); 1640 1641 return 0; 1642 } 1643 1644 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1645 { 1646 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1647 MIRROR_PORT(val); 1648 } 1649 1650 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1651 { 1652 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1653 MIRROR_PORT(val); 1654 } 1655 1656 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1657 struct dsa_mall_mirror_tc_entry *mirror, 1658 bool ingress) 1659 { 1660 struct mt7530_priv *priv = ds->priv; 1661 int monitor_port; 1662 u32 val; 1663 1664 /* Check for existent entry */ 1665 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1666 return -EEXIST; 1667 1668 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1669 1670 /* MT7530 only supports one monitor port */ 1671 monitor_port = mt753x_mirror_port_get(priv->id, val); 1672 if (val & MT753X_MIRROR_EN(priv->id) && 1673 monitor_port != mirror->to_local_port) 1674 return -EEXIST; 1675 1676 val |= MT753X_MIRROR_EN(priv->id); 1677 val &= ~MT753X_MIRROR_MASK(priv->id); 1678 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1679 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1680 1681 val = mt7530_read(priv, MT7530_PCR_P(port)); 1682 if (ingress) { 1683 val |= PORT_RX_MIR; 1684 priv->mirror_rx |= BIT(port); 1685 } else { 1686 val |= PORT_TX_MIR; 1687 priv->mirror_tx |= BIT(port); 1688 } 1689 mt7530_write(priv, MT7530_PCR_P(port), val); 1690 1691 return 0; 1692 } 1693 1694 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1695 struct dsa_mall_mirror_tc_entry *mirror) 1696 { 1697 struct mt7530_priv *priv = ds->priv; 1698 u32 val; 1699 1700 val = mt7530_read(priv, MT7530_PCR_P(port)); 1701 if (mirror->ingress) { 1702 val &= ~PORT_RX_MIR; 1703 priv->mirror_rx &= ~BIT(port); 1704 } else { 1705 val &= ~PORT_TX_MIR; 1706 priv->mirror_tx &= ~BIT(port); 1707 } 1708 mt7530_write(priv, MT7530_PCR_P(port), val); 1709 1710 if (!priv->mirror_rx && !priv->mirror_tx) { 1711 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1712 val &= ~MT753X_MIRROR_EN(priv->id); 1713 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1714 } 1715 } 1716 1717 static enum dsa_tag_protocol 1718 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1719 enum dsa_tag_protocol mp) 1720 { 1721 struct mt7530_priv *priv = ds->priv; 1722 1723 if (port != MT7530_CPU_PORT) { 1724 dev_warn(priv->dev, 1725 "port not matched with tagging CPU port\n"); 1726 return DSA_TAG_PROTO_NONE; 1727 } else { 1728 return DSA_TAG_PROTO_MTK; 1729 } 1730 } 1731 1732 #ifdef CONFIG_GPIOLIB 1733 static inline u32 1734 mt7530_gpio_to_bit(unsigned int offset) 1735 { 1736 /* Map GPIO offset to register bit 1737 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1738 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1739 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1740 * [14:12] port 3 LED 0..2 as GPIO 9..11 1741 * [18:16] port 4 LED 0..2 as GPIO 12..14 1742 */ 1743 return BIT(offset + offset / 3); 1744 } 1745 1746 static int 1747 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1748 { 1749 struct mt7530_priv *priv = gpiochip_get_data(gc); 1750 u32 bit = mt7530_gpio_to_bit(offset); 1751 1752 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1753 } 1754 1755 static void 1756 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1757 { 1758 struct mt7530_priv *priv = gpiochip_get_data(gc); 1759 u32 bit = mt7530_gpio_to_bit(offset); 1760 1761 if (value) 1762 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1763 else 1764 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1765 } 1766 1767 static int 1768 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1769 { 1770 struct mt7530_priv *priv = gpiochip_get_data(gc); 1771 u32 bit = mt7530_gpio_to_bit(offset); 1772 1773 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1774 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1775 } 1776 1777 static int 1778 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1779 { 1780 struct mt7530_priv *priv = gpiochip_get_data(gc); 1781 u32 bit = mt7530_gpio_to_bit(offset); 1782 1783 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1784 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1785 1786 return 0; 1787 } 1788 1789 static int 1790 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1791 { 1792 struct mt7530_priv *priv = gpiochip_get_data(gc); 1793 u32 bit = mt7530_gpio_to_bit(offset); 1794 1795 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1796 1797 if (value) 1798 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1799 else 1800 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1801 1802 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1803 1804 return 0; 1805 } 1806 1807 static int 1808 mt7530_setup_gpio(struct mt7530_priv *priv) 1809 { 1810 struct device *dev = priv->dev; 1811 struct gpio_chip *gc; 1812 1813 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1814 if (!gc) 1815 return -ENOMEM; 1816 1817 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1818 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1819 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1820 1821 gc->label = "mt7530"; 1822 gc->parent = dev; 1823 gc->owner = THIS_MODULE; 1824 gc->get_direction = mt7530_gpio_get_direction; 1825 gc->direction_input = mt7530_gpio_direction_input; 1826 gc->direction_output = mt7530_gpio_direction_output; 1827 gc->get = mt7530_gpio_get; 1828 gc->set = mt7530_gpio_set; 1829 gc->base = -1; 1830 gc->ngpio = 15; 1831 gc->can_sleep = true; 1832 1833 return devm_gpiochip_add_data(dev, gc, priv); 1834 } 1835 #endif /* CONFIG_GPIOLIB */ 1836 1837 static irqreturn_t 1838 mt7530_irq_thread_fn(int irq, void *dev_id) 1839 { 1840 struct mt7530_priv *priv = dev_id; 1841 bool handled = false; 1842 u32 val; 1843 int p; 1844 1845 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1846 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1847 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1848 mutex_unlock(&priv->bus->mdio_lock); 1849 1850 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1851 if (BIT(p) & val) { 1852 unsigned int irq; 1853 1854 irq = irq_find_mapping(priv->irq_domain, p); 1855 handle_nested_irq(irq); 1856 handled = true; 1857 } 1858 } 1859 1860 return IRQ_RETVAL(handled); 1861 } 1862 1863 static void 1864 mt7530_irq_mask(struct irq_data *d) 1865 { 1866 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1867 1868 priv->irq_enable &= ~BIT(d->hwirq); 1869 } 1870 1871 static void 1872 mt7530_irq_unmask(struct irq_data *d) 1873 { 1874 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1875 1876 priv->irq_enable |= BIT(d->hwirq); 1877 } 1878 1879 static void 1880 mt7530_irq_bus_lock(struct irq_data *d) 1881 { 1882 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1883 1884 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1885 } 1886 1887 static void 1888 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1889 { 1890 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1891 1892 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1893 mutex_unlock(&priv->bus->mdio_lock); 1894 } 1895 1896 static struct irq_chip mt7530_irq_chip = { 1897 .name = KBUILD_MODNAME, 1898 .irq_mask = mt7530_irq_mask, 1899 .irq_unmask = mt7530_irq_unmask, 1900 .irq_bus_lock = mt7530_irq_bus_lock, 1901 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1902 }; 1903 1904 static int 1905 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1906 irq_hw_number_t hwirq) 1907 { 1908 irq_set_chip_data(irq, domain->host_data); 1909 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1910 irq_set_nested_thread(irq, true); 1911 irq_set_noprobe(irq); 1912 1913 return 0; 1914 } 1915 1916 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1917 .map = mt7530_irq_map, 1918 .xlate = irq_domain_xlate_onecell, 1919 }; 1920 1921 static void 1922 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1923 { 1924 struct dsa_switch *ds = priv->ds; 1925 int p; 1926 1927 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1928 if (BIT(p) & ds->phys_mii_mask) { 1929 unsigned int irq; 1930 1931 irq = irq_create_mapping(priv->irq_domain, p); 1932 ds->slave_mii_bus->irq[p] = irq; 1933 } 1934 } 1935 } 1936 1937 static int 1938 mt7530_setup_irq(struct mt7530_priv *priv) 1939 { 1940 struct device *dev = priv->dev; 1941 struct device_node *np = dev->of_node; 1942 int ret; 1943 1944 if (!of_property_read_bool(np, "interrupt-controller")) { 1945 dev_info(dev, "no interrupt support\n"); 1946 return 0; 1947 } 1948 1949 priv->irq = of_irq_get(np, 0); 1950 if (priv->irq <= 0) { 1951 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 1952 return priv->irq ? : -EINVAL; 1953 } 1954 1955 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 1956 &mt7530_irq_domain_ops, priv); 1957 if (!priv->irq_domain) { 1958 dev_err(dev, "failed to create IRQ domain\n"); 1959 return -ENOMEM; 1960 } 1961 1962 /* This register must be set for MT7530 to properly fire interrupts */ 1963 if (priv->id != ID_MT7531) 1964 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 1965 1966 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 1967 IRQF_ONESHOT, KBUILD_MODNAME, priv); 1968 if (ret) { 1969 irq_domain_remove(priv->irq_domain); 1970 dev_err(dev, "failed to request IRQ: %d\n", ret); 1971 return ret; 1972 } 1973 1974 return 0; 1975 } 1976 1977 static void 1978 mt7530_free_mdio_irq(struct mt7530_priv *priv) 1979 { 1980 int p; 1981 1982 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1983 if (BIT(p) & priv->ds->phys_mii_mask) { 1984 unsigned int irq; 1985 1986 irq = irq_find_mapping(priv->irq_domain, p); 1987 irq_dispose_mapping(irq); 1988 } 1989 } 1990 } 1991 1992 static void 1993 mt7530_free_irq_common(struct mt7530_priv *priv) 1994 { 1995 free_irq(priv->irq, priv); 1996 irq_domain_remove(priv->irq_domain); 1997 } 1998 1999 static void 2000 mt7530_free_irq(struct mt7530_priv *priv) 2001 { 2002 mt7530_free_mdio_irq(priv); 2003 mt7530_free_irq_common(priv); 2004 } 2005 2006 static int 2007 mt7530_setup_mdio(struct mt7530_priv *priv) 2008 { 2009 struct dsa_switch *ds = priv->ds; 2010 struct device *dev = priv->dev; 2011 struct mii_bus *bus; 2012 static int idx; 2013 int ret; 2014 2015 bus = devm_mdiobus_alloc(dev); 2016 if (!bus) 2017 return -ENOMEM; 2018 2019 ds->slave_mii_bus = bus; 2020 bus->priv = priv; 2021 bus->name = KBUILD_MODNAME "-mii"; 2022 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2023 bus->read = mt753x_phy_read; 2024 bus->write = mt753x_phy_write; 2025 bus->parent = dev; 2026 bus->phy_mask = ~ds->phys_mii_mask; 2027 2028 if (priv->irq) 2029 mt7530_setup_mdio_irq(priv); 2030 2031 ret = mdiobus_register(bus); 2032 if (ret) { 2033 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2034 if (priv->irq) 2035 mt7530_free_mdio_irq(priv); 2036 } 2037 2038 return ret; 2039 } 2040 2041 static int 2042 mt7530_setup(struct dsa_switch *ds) 2043 { 2044 struct mt7530_priv *priv = ds->priv; 2045 struct device_node *phy_node; 2046 struct device_node *mac_np; 2047 struct mt7530_dummy_poll p; 2048 phy_interface_t interface; 2049 struct device_node *dn; 2050 u32 id, val; 2051 int ret, i; 2052 2053 /* The parent node of master netdev which holds the common system 2054 * controller also is the container for two GMACs nodes representing 2055 * as two netdev instances. 2056 */ 2057 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 2058 ds->mtu_enforcement_ingress = true; 2059 2060 if (priv->id == ID_MT7530) { 2061 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2062 ret = regulator_enable(priv->core_pwr); 2063 if (ret < 0) { 2064 dev_err(priv->dev, 2065 "Failed to enable core power: %d\n", ret); 2066 return ret; 2067 } 2068 2069 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2070 ret = regulator_enable(priv->io_pwr); 2071 if (ret < 0) { 2072 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2073 ret); 2074 return ret; 2075 } 2076 } 2077 2078 /* Reset whole chip through gpio pin or memory-mapped registers for 2079 * different type of hardware 2080 */ 2081 if (priv->mcm) { 2082 reset_control_assert(priv->rstc); 2083 usleep_range(1000, 1100); 2084 reset_control_deassert(priv->rstc); 2085 } else { 2086 gpiod_set_value_cansleep(priv->reset, 0); 2087 usleep_range(1000, 1100); 2088 gpiod_set_value_cansleep(priv->reset, 1); 2089 } 2090 2091 /* Waiting for MT7530 got to stable */ 2092 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2093 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2094 20, 1000000); 2095 if (ret < 0) { 2096 dev_err(priv->dev, "reset timeout\n"); 2097 return ret; 2098 } 2099 2100 id = mt7530_read(priv, MT7530_CREV); 2101 id >>= CHIP_NAME_SHIFT; 2102 if (id != MT7530_ID) { 2103 dev_err(priv->dev, "chip %x can't be supported\n", id); 2104 return -ENODEV; 2105 } 2106 2107 /* Reset the switch through internal reset */ 2108 mt7530_write(priv, MT7530_SYS_CTRL, 2109 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2110 SYS_CTRL_REG_RST); 2111 2112 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2113 val = mt7530_read(priv, MT7530_MHWTRAP); 2114 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2115 val |= MHWTRAP_MANUAL; 2116 mt7530_write(priv, MT7530_MHWTRAP, val); 2117 2118 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2119 2120 /* Enable and reset MIB counters */ 2121 mt7530_mib_reset(ds); 2122 2123 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2124 /* Disable forwarding by default on all ports */ 2125 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2126 PCR_MATRIX_CLR); 2127 2128 if (dsa_is_cpu_port(ds, i)) { 2129 ret = mt753x_cpu_port_enable(ds, i); 2130 if (ret) 2131 return ret; 2132 } else { 2133 mt7530_port_disable(ds, i); 2134 2135 /* Disable learning by default on all user ports */ 2136 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2137 } 2138 /* Enable consistent egress tag */ 2139 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2140 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2141 } 2142 2143 /* Setup port 5 */ 2144 priv->p5_intf_sel = P5_DISABLED; 2145 interface = PHY_INTERFACE_MODE_NA; 2146 2147 if (!dsa_is_unused_port(ds, 5)) { 2148 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2149 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2150 if (ret && ret != -ENODEV) 2151 return ret; 2152 } else { 2153 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2154 for_each_child_of_node(dn, mac_np) { 2155 if (!of_device_is_compatible(mac_np, 2156 "mediatek,eth-mac")) 2157 continue; 2158 2159 ret = of_property_read_u32(mac_np, "reg", &id); 2160 if (ret < 0 || id != 1) 2161 continue; 2162 2163 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2164 if (!phy_node) 2165 continue; 2166 2167 if (phy_node->parent == priv->dev->of_node->parent) { 2168 ret = of_get_phy_mode(mac_np, &interface); 2169 if (ret && ret != -ENODEV) { 2170 of_node_put(mac_np); 2171 return ret; 2172 } 2173 id = of_mdio_parse_addr(ds->dev, phy_node); 2174 if (id == 0) 2175 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2176 if (id == 4) 2177 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2178 } 2179 of_node_put(mac_np); 2180 of_node_put(phy_node); 2181 break; 2182 } 2183 } 2184 2185 #ifdef CONFIG_GPIOLIB 2186 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2187 ret = mt7530_setup_gpio(priv); 2188 if (ret) 2189 return ret; 2190 } 2191 #endif /* CONFIG_GPIOLIB */ 2192 2193 mt7530_setup_port5(ds, interface); 2194 2195 /* Flush the FDB table */ 2196 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2197 if (ret < 0) 2198 return ret; 2199 2200 return 0; 2201 } 2202 2203 static int 2204 mt7531_setup(struct dsa_switch *ds) 2205 { 2206 struct mt7530_priv *priv = ds->priv; 2207 struct mt7530_dummy_poll p; 2208 u32 val, id; 2209 int ret, i; 2210 2211 /* Reset whole chip through gpio pin or memory-mapped registers for 2212 * different type of hardware 2213 */ 2214 if (priv->mcm) { 2215 reset_control_assert(priv->rstc); 2216 usleep_range(1000, 1100); 2217 reset_control_deassert(priv->rstc); 2218 } else { 2219 gpiod_set_value_cansleep(priv->reset, 0); 2220 usleep_range(1000, 1100); 2221 gpiod_set_value_cansleep(priv->reset, 1); 2222 } 2223 2224 /* Waiting for MT7530 got to stable */ 2225 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2226 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2227 20, 1000000); 2228 if (ret < 0) { 2229 dev_err(priv->dev, "reset timeout\n"); 2230 return ret; 2231 } 2232 2233 id = mt7530_read(priv, MT7531_CREV); 2234 id >>= CHIP_NAME_SHIFT; 2235 2236 if (id != MT7531_ID) { 2237 dev_err(priv->dev, "chip %x can't be supported\n", id); 2238 return -ENODEV; 2239 } 2240 2241 /* Reset the switch through internal reset */ 2242 mt7530_write(priv, MT7530_SYS_CTRL, 2243 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2244 SYS_CTRL_REG_RST); 2245 2246 if (mt7531_dual_sgmii_supported(priv)) { 2247 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2248 2249 /* Let ds->slave_mii_bus be able to access external phy. */ 2250 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2251 MT7531_EXT_P_MDC_11); 2252 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2253 MT7531_EXT_P_MDIO_12); 2254 } else { 2255 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2256 } 2257 dev_dbg(ds->dev, "P5 support %s interface\n", 2258 p5_intf_modes(priv->p5_intf_sel)); 2259 2260 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2261 MT7531_GPIO0_INTERRUPT); 2262 2263 /* Let phylink decide the interface later. */ 2264 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2265 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2266 2267 /* Enable PHY core PLL, since phy_device has not yet been created 2268 * provided for phy_[read,write]_mmd_indirect is called, we provide 2269 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2270 * function. 2271 */ 2272 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2273 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2274 val |= MT7531_PHY_PLL_BYPASS_MODE; 2275 val &= ~MT7531_PHY_PLL_OFF; 2276 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2277 CORE_PLL_GROUP4, val); 2278 2279 /* BPDU to CPU port */ 2280 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2281 BIT(MT7530_CPU_PORT)); 2282 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2283 MT753X_BPDU_CPU_ONLY); 2284 2285 /* Enable and reset MIB counters */ 2286 mt7530_mib_reset(ds); 2287 2288 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2289 /* Disable forwarding by default on all ports */ 2290 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2291 PCR_MATRIX_CLR); 2292 2293 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2294 2295 if (dsa_is_cpu_port(ds, i)) { 2296 ret = mt753x_cpu_port_enable(ds, i); 2297 if (ret) 2298 return ret; 2299 } else { 2300 mt7530_port_disable(ds, i); 2301 2302 /* Disable learning by default on all user ports */ 2303 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2304 } 2305 2306 /* Enable consistent egress tag */ 2307 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2308 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2309 } 2310 2311 ds->mtu_enforcement_ingress = true; 2312 2313 /* Flush the FDB table */ 2314 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2315 if (ret < 0) 2316 return ret; 2317 2318 return 0; 2319 } 2320 2321 static bool 2322 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2323 const struct phylink_link_state *state) 2324 { 2325 struct mt7530_priv *priv = ds->priv; 2326 2327 switch (port) { 2328 case 0 ... 4: /* Internal phy */ 2329 if (state->interface != PHY_INTERFACE_MODE_GMII) 2330 return false; 2331 break; 2332 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2333 if (!phy_interface_mode_is_rgmii(state->interface) && 2334 state->interface != PHY_INTERFACE_MODE_MII && 2335 state->interface != PHY_INTERFACE_MODE_GMII) 2336 return false; 2337 break; 2338 case 6: /* 1st cpu port */ 2339 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2340 state->interface != PHY_INTERFACE_MODE_TRGMII) 2341 return false; 2342 break; 2343 default: 2344 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2345 port); 2346 return false; 2347 } 2348 2349 return true; 2350 } 2351 2352 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2353 { 2354 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2355 } 2356 2357 static bool 2358 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2359 const struct phylink_link_state *state) 2360 { 2361 struct mt7530_priv *priv = ds->priv; 2362 2363 switch (port) { 2364 case 0 ... 4: /* Internal phy */ 2365 if (state->interface != PHY_INTERFACE_MODE_GMII) 2366 return false; 2367 break; 2368 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2369 if (mt7531_is_rgmii_port(priv, port)) 2370 return phy_interface_mode_is_rgmii(state->interface); 2371 fallthrough; 2372 case 6: /* 1st cpu port supports sgmii/8023z only */ 2373 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2374 !phy_interface_mode_is_8023z(state->interface)) 2375 return false; 2376 break; 2377 default: 2378 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2379 port); 2380 return false; 2381 } 2382 2383 return true; 2384 } 2385 2386 static bool 2387 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2388 const struct phylink_link_state *state) 2389 { 2390 struct mt7530_priv *priv = ds->priv; 2391 2392 return priv->info->phy_mode_supported(ds, port, state); 2393 } 2394 2395 static int 2396 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2397 { 2398 struct mt7530_priv *priv = ds->priv; 2399 2400 return priv->info->pad_setup(ds, state->interface); 2401 } 2402 2403 static int 2404 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2405 phy_interface_t interface) 2406 { 2407 struct mt7530_priv *priv = ds->priv; 2408 2409 /* Only need to setup port5. */ 2410 if (port != 5) 2411 return 0; 2412 2413 mt7530_setup_port5(priv->ds, interface); 2414 2415 return 0; 2416 } 2417 2418 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2419 phy_interface_t interface, 2420 struct phy_device *phydev) 2421 { 2422 u32 val; 2423 2424 if (!mt7531_is_rgmii_port(priv, port)) { 2425 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2426 port); 2427 return -EINVAL; 2428 } 2429 2430 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2431 val |= GP_CLK_EN; 2432 val &= ~GP_MODE_MASK; 2433 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2434 val &= ~CLK_SKEW_IN_MASK; 2435 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2436 val &= ~CLK_SKEW_OUT_MASK; 2437 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2438 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2439 2440 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2441 if (!phydev || phy_driver_is_genphy(phydev)) { 2442 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2443 switch (interface) { 2444 case PHY_INTERFACE_MODE_RGMII: 2445 val |= TXCLK_NO_REVERSE; 2446 val |= RXCLK_NO_DELAY; 2447 break; 2448 case PHY_INTERFACE_MODE_RGMII_RXID: 2449 val |= TXCLK_NO_REVERSE; 2450 break; 2451 case PHY_INTERFACE_MODE_RGMII_TXID: 2452 val |= RXCLK_NO_DELAY; 2453 break; 2454 case PHY_INTERFACE_MODE_RGMII_ID: 2455 break; 2456 default: 2457 return -EINVAL; 2458 } 2459 } 2460 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2461 2462 return 0; 2463 } 2464 2465 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2466 unsigned long *supported) 2467 { 2468 /* Port5 supports ethier RGMII or SGMII. 2469 * Port6 supports SGMII only. 2470 */ 2471 switch (port) { 2472 case 5: 2473 if (mt7531_is_rgmii_port(priv, port)) 2474 break; 2475 fallthrough; 2476 case 6: 2477 phylink_set(supported, 1000baseX_Full); 2478 phylink_set(supported, 2500baseX_Full); 2479 phylink_set(supported, 2500baseT_Full); 2480 } 2481 } 2482 2483 static void 2484 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2485 unsigned int mode, phy_interface_t interface, 2486 int speed, int duplex) 2487 { 2488 struct mt7530_priv *priv = ds->priv; 2489 unsigned int val; 2490 2491 /* For adjusting speed and duplex of SGMII force mode. */ 2492 if (interface != PHY_INTERFACE_MODE_SGMII || 2493 phylink_autoneg_inband(mode)) 2494 return; 2495 2496 /* SGMII force mode setting */ 2497 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2498 val &= ~MT7531_SGMII_IF_MODE_MASK; 2499 2500 switch (speed) { 2501 case SPEED_10: 2502 val |= MT7531_SGMII_FORCE_SPEED_10; 2503 break; 2504 case SPEED_100: 2505 val |= MT7531_SGMII_FORCE_SPEED_100; 2506 break; 2507 case SPEED_1000: 2508 val |= MT7531_SGMII_FORCE_SPEED_1000; 2509 break; 2510 } 2511 2512 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2513 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2514 */ 2515 if ((speed == SPEED_10 || speed == SPEED_100) && 2516 duplex != DUPLEX_FULL) 2517 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2518 2519 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2520 } 2521 2522 static bool mt753x_is_mac_port(u32 port) 2523 { 2524 return (port == 5 || port == 6); 2525 } 2526 2527 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2528 phy_interface_t interface) 2529 { 2530 u32 val; 2531 2532 if (!mt753x_is_mac_port(port)) 2533 return -EINVAL; 2534 2535 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2536 MT7531_SGMII_PHYA_PWD); 2537 2538 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2539 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2540 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2541 * encoding. 2542 */ 2543 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2544 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2545 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2546 2547 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2548 2549 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2550 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2551 */ 2552 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2553 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2554 MT7531_SGMII_FORCE_SPEED_1000); 2555 2556 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2557 2558 return 0; 2559 } 2560 2561 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2562 phy_interface_t interface) 2563 { 2564 if (!mt753x_is_mac_port(port)) 2565 return -EINVAL; 2566 2567 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2568 MT7531_SGMII_PHYA_PWD); 2569 2570 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2571 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2572 2573 mt7530_set(priv, MT7531_SGMII_MODE(port), 2574 MT7531_SGMII_REMOTE_FAULT_DIS | 2575 MT7531_SGMII_SPEED_DUPLEX_AN); 2576 2577 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2578 MT7531_SGMII_TX_CONFIG_MASK, 1); 2579 2580 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2581 2582 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2583 2584 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2585 2586 return 0; 2587 } 2588 2589 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2590 { 2591 struct mt7530_priv *priv = ds->priv; 2592 u32 val; 2593 2594 /* Only restart AN when AN is enabled */ 2595 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2596 if (val & MT7531_SGMII_AN_ENABLE) { 2597 val |= MT7531_SGMII_AN_RESTART; 2598 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2599 } 2600 } 2601 2602 static int 2603 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2604 phy_interface_t interface) 2605 { 2606 struct mt7530_priv *priv = ds->priv; 2607 struct phy_device *phydev; 2608 struct dsa_port *dp; 2609 2610 if (!mt753x_is_mac_port(port)) { 2611 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2612 return -EINVAL; 2613 } 2614 2615 switch (interface) { 2616 case PHY_INTERFACE_MODE_RGMII: 2617 case PHY_INTERFACE_MODE_RGMII_ID: 2618 case PHY_INTERFACE_MODE_RGMII_RXID: 2619 case PHY_INTERFACE_MODE_RGMII_TXID: 2620 dp = dsa_to_port(ds, port); 2621 phydev = dp->slave->phydev; 2622 return mt7531_rgmii_setup(priv, port, interface, phydev); 2623 case PHY_INTERFACE_MODE_SGMII: 2624 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2625 case PHY_INTERFACE_MODE_NA: 2626 case PHY_INTERFACE_MODE_1000BASEX: 2627 case PHY_INTERFACE_MODE_2500BASEX: 2628 if (phylink_autoneg_inband(mode)) 2629 return -EINVAL; 2630 2631 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2632 default: 2633 return -EINVAL; 2634 } 2635 2636 return -EINVAL; 2637 } 2638 2639 static int 2640 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2641 const struct phylink_link_state *state) 2642 { 2643 struct mt7530_priv *priv = ds->priv; 2644 2645 return priv->info->mac_port_config(ds, port, mode, state->interface); 2646 } 2647 2648 static void 2649 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2650 const struct phylink_link_state *state) 2651 { 2652 struct mt7530_priv *priv = ds->priv; 2653 u32 mcr_cur, mcr_new; 2654 2655 if (!mt753x_phy_mode_supported(ds, port, state)) 2656 goto unsupported; 2657 2658 switch (port) { 2659 case 0 ... 4: /* Internal phy */ 2660 if (state->interface != PHY_INTERFACE_MODE_GMII) 2661 goto unsupported; 2662 break; 2663 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2664 if (priv->p5_interface == state->interface) 2665 break; 2666 2667 if (mt753x_mac_config(ds, port, mode, state) < 0) 2668 goto unsupported; 2669 2670 if (priv->p5_intf_sel != P5_DISABLED) 2671 priv->p5_interface = state->interface; 2672 break; 2673 case 6: /* 1st cpu port */ 2674 if (priv->p6_interface == state->interface) 2675 break; 2676 2677 mt753x_pad_setup(ds, state); 2678 2679 if (mt753x_mac_config(ds, port, mode, state) < 0) 2680 goto unsupported; 2681 2682 priv->p6_interface = state->interface; 2683 break; 2684 default: 2685 unsupported: 2686 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2687 __func__, phy_modes(state->interface), port); 2688 return; 2689 } 2690 2691 if (phylink_autoneg_inband(mode) && 2692 state->interface != PHY_INTERFACE_MODE_SGMII) { 2693 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2694 __func__); 2695 return; 2696 } 2697 2698 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2699 mcr_new = mcr_cur; 2700 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2701 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2702 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2703 2704 /* Are we connected to external phy */ 2705 if (port == 5 && dsa_is_user_port(ds, 5)) 2706 mcr_new |= PMCR_EXT_PHY; 2707 2708 if (mcr_new != mcr_cur) 2709 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2710 } 2711 2712 static void 2713 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2714 { 2715 struct mt7530_priv *priv = ds->priv; 2716 2717 if (!priv->info->mac_pcs_an_restart) 2718 return; 2719 2720 priv->info->mac_pcs_an_restart(ds, port); 2721 } 2722 2723 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2724 unsigned int mode, 2725 phy_interface_t interface) 2726 { 2727 struct mt7530_priv *priv = ds->priv; 2728 2729 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2730 } 2731 2732 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2733 unsigned int mode, phy_interface_t interface, 2734 int speed, int duplex) 2735 { 2736 struct mt7530_priv *priv = ds->priv; 2737 2738 if (!priv->info->mac_pcs_link_up) 2739 return; 2740 2741 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2742 } 2743 2744 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2745 unsigned int mode, 2746 phy_interface_t interface, 2747 struct phy_device *phydev, 2748 int speed, int duplex, 2749 bool tx_pause, bool rx_pause) 2750 { 2751 struct mt7530_priv *priv = ds->priv; 2752 u32 mcr; 2753 2754 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2755 2756 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2757 2758 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2759 * variants. 2760 */ 2761 if (interface == PHY_INTERFACE_MODE_TRGMII || 2762 (phy_interface_mode_is_8023z(interface))) { 2763 speed = SPEED_1000; 2764 duplex = DUPLEX_FULL; 2765 } 2766 2767 switch (speed) { 2768 case SPEED_1000: 2769 mcr |= PMCR_FORCE_SPEED_1000; 2770 break; 2771 case SPEED_100: 2772 mcr |= PMCR_FORCE_SPEED_100; 2773 break; 2774 } 2775 if (duplex == DUPLEX_FULL) { 2776 mcr |= PMCR_FORCE_FDX; 2777 if (tx_pause) 2778 mcr |= PMCR_TX_FC_EN; 2779 if (rx_pause) 2780 mcr |= PMCR_RX_FC_EN; 2781 } 2782 2783 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) { 2784 switch (speed) { 2785 case SPEED_1000: 2786 mcr |= PMCR_FORCE_EEE1G; 2787 break; 2788 case SPEED_100: 2789 mcr |= PMCR_FORCE_EEE100; 2790 break; 2791 } 2792 } 2793 2794 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2795 } 2796 2797 static int 2798 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2799 { 2800 struct mt7530_priv *priv = ds->priv; 2801 phy_interface_t interface; 2802 int speed; 2803 int ret; 2804 2805 switch (port) { 2806 case 5: 2807 if (mt7531_is_rgmii_port(priv, port)) 2808 interface = PHY_INTERFACE_MODE_RGMII; 2809 else 2810 interface = PHY_INTERFACE_MODE_2500BASEX; 2811 2812 priv->p5_interface = interface; 2813 break; 2814 case 6: 2815 interface = PHY_INTERFACE_MODE_2500BASEX; 2816 2817 mt7531_pad_setup(ds, interface); 2818 2819 priv->p6_interface = interface; 2820 break; 2821 default: 2822 return -EINVAL; 2823 } 2824 2825 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2826 speed = SPEED_2500; 2827 else 2828 speed = SPEED_1000; 2829 2830 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2831 if (ret) 2832 return ret; 2833 mt7530_write(priv, MT7530_PMCR_P(port), 2834 PMCR_CPU_PORT_SETTING(priv->id)); 2835 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2836 speed, DUPLEX_FULL, true, true); 2837 2838 return 0; 2839 } 2840 2841 static void 2842 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2843 unsigned long *supported) 2844 { 2845 if (port == 5) 2846 phylink_set(supported, 1000baseX_Full); 2847 } 2848 2849 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2850 unsigned long *supported) 2851 { 2852 struct mt7530_priv *priv = ds->priv; 2853 2854 mt7531_sgmii_validate(priv, port, supported); 2855 } 2856 2857 static void 2858 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2859 unsigned long *supported, 2860 struct phylink_link_state *state) 2861 { 2862 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2863 struct mt7530_priv *priv = ds->priv; 2864 2865 if (state->interface != PHY_INTERFACE_MODE_NA && 2866 !mt753x_phy_mode_supported(ds, port, state)) { 2867 linkmode_zero(supported); 2868 return; 2869 } 2870 2871 phylink_set_port_modes(mask); 2872 2873 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2874 !phy_interface_mode_is_8023z(state->interface)) { 2875 phylink_set(mask, 10baseT_Half); 2876 phylink_set(mask, 10baseT_Full); 2877 phylink_set(mask, 100baseT_Half); 2878 phylink_set(mask, 100baseT_Full); 2879 phylink_set(mask, Autoneg); 2880 } 2881 2882 /* This switch only supports 1G full-duplex. */ 2883 if (state->interface != PHY_INTERFACE_MODE_MII) 2884 phylink_set(mask, 1000baseT_Full); 2885 2886 priv->info->mac_port_validate(ds, port, mask); 2887 2888 phylink_set(mask, Pause); 2889 phylink_set(mask, Asym_Pause); 2890 2891 linkmode_and(supported, supported, mask); 2892 linkmode_and(state->advertising, state->advertising, mask); 2893 2894 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2895 * to advertise both, only report advertising at 2500BaseX. 2896 */ 2897 phylink_helper_basex_speed(state); 2898 } 2899 2900 static int 2901 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2902 struct phylink_link_state *state) 2903 { 2904 struct mt7530_priv *priv = ds->priv; 2905 u32 pmsr; 2906 2907 if (port < 0 || port >= MT7530_NUM_PORTS) 2908 return -EINVAL; 2909 2910 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2911 2912 state->link = (pmsr & PMSR_LINK); 2913 state->an_complete = state->link; 2914 state->duplex = !!(pmsr & PMSR_DPX); 2915 2916 switch (pmsr & PMSR_SPEED_MASK) { 2917 case PMSR_SPEED_10: 2918 state->speed = SPEED_10; 2919 break; 2920 case PMSR_SPEED_100: 2921 state->speed = SPEED_100; 2922 break; 2923 case PMSR_SPEED_1000: 2924 state->speed = SPEED_1000; 2925 break; 2926 default: 2927 state->speed = SPEED_UNKNOWN; 2928 break; 2929 } 2930 2931 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2932 if (pmsr & PMSR_RX_FC) 2933 state->pause |= MLO_PAUSE_RX; 2934 if (pmsr & PMSR_TX_FC) 2935 state->pause |= MLO_PAUSE_TX; 2936 2937 return 1; 2938 } 2939 2940 static int 2941 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2942 struct phylink_link_state *state) 2943 { 2944 u32 status, val; 2945 u16 config_reg; 2946 2947 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2948 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2949 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2950 (status & MT7531_SGMII_AN_ENABLE)) { 2951 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2952 config_reg = val >> 16; 2953 2954 switch (config_reg & LPA_SGMII_SPD_MASK) { 2955 case LPA_SGMII_1000: 2956 state->speed = SPEED_1000; 2957 break; 2958 case LPA_SGMII_100: 2959 state->speed = SPEED_100; 2960 break; 2961 case LPA_SGMII_10: 2962 state->speed = SPEED_10; 2963 break; 2964 default: 2965 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2966 state->link = false; 2967 return -EINVAL; 2968 } 2969 2970 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2971 state->duplex = DUPLEX_FULL; 2972 else 2973 state->duplex = DUPLEX_HALF; 2974 } 2975 2976 return 0; 2977 } 2978 2979 static int 2980 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 2981 struct phylink_link_state *state) 2982 { 2983 struct mt7530_priv *priv = ds->priv; 2984 2985 if (state->interface == PHY_INTERFACE_MODE_SGMII) 2986 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 2987 2988 return -EOPNOTSUPP; 2989 } 2990 2991 static int 2992 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 2993 struct phylink_link_state *state) 2994 { 2995 struct mt7530_priv *priv = ds->priv; 2996 2997 return priv->info->mac_port_get_state(ds, port, state); 2998 } 2999 3000 static int 3001 mt753x_setup(struct dsa_switch *ds) 3002 { 3003 struct mt7530_priv *priv = ds->priv; 3004 int ret = priv->info->sw_setup(ds); 3005 3006 if (ret) 3007 return ret; 3008 3009 ret = mt7530_setup_irq(priv); 3010 if (ret) 3011 return ret; 3012 3013 ret = mt7530_setup_mdio(priv); 3014 if (ret && priv->irq) 3015 mt7530_free_irq_common(priv); 3016 3017 return ret; 3018 } 3019 3020 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3021 struct ethtool_eee *e) 3022 { 3023 struct mt7530_priv *priv = ds->priv; 3024 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3025 3026 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3027 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3028 3029 return 0; 3030 } 3031 3032 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3033 struct ethtool_eee *e) 3034 { 3035 struct mt7530_priv *priv = ds->priv; 3036 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3037 3038 if (e->tx_lpi_timer > 0xFFF) 3039 return -EINVAL; 3040 3041 set = SET_LPI_THRESH(e->tx_lpi_timer); 3042 if (!e->tx_lpi_enabled) 3043 /* Force LPI Mode without a delay */ 3044 set |= LPI_MODE_EN; 3045 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3046 3047 return 0; 3048 } 3049 3050 static const struct dsa_switch_ops mt7530_switch_ops = { 3051 .get_tag_protocol = mtk_get_tag_protocol, 3052 .setup = mt753x_setup, 3053 .get_strings = mt7530_get_strings, 3054 .get_ethtool_stats = mt7530_get_ethtool_stats, 3055 .get_sset_count = mt7530_get_sset_count, 3056 .set_ageing_time = mt7530_set_ageing_time, 3057 .port_enable = mt7530_port_enable, 3058 .port_disable = mt7530_port_disable, 3059 .port_change_mtu = mt7530_port_change_mtu, 3060 .port_max_mtu = mt7530_port_max_mtu, 3061 .port_stp_state_set = mt7530_stp_state_set, 3062 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3063 .port_bridge_flags = mt7530_port_bridge_flags, 3064 .port_set_mrouter = mt7530_port_set_mrouter, 3065 .port_bridge_join = mt7530_port_bridge_join, 3066 .port_bridge_leave = mt7530_port_bridge_leave, 3067 .port_fdb_add = mt7530_port_fdb_add, 3068 .port_fdb_del = mt7530_port_fdb_del, 3069 .port_fdb_dump = mt7530_port_fdb_dump, 3070 .port_mdb_add = mt7530_port_mdb_add, 3071 .port_mdb_del = mt7530_port_mdb_del, 3072 .port_vlan_filtering = mt7530_port_vlan_filtering, 3073 .port_vlan_add = mt7530_port_vlan_add, 3074 .port_vlan_del = mt7530_port_vlan_del, 3075 .port_mirror_add = mt753x_port_mirror_add, 3076 .port_mirror_del = mt753x_port_mirror_del, 3077 .phylink_validate = mt753x_phylink_validate, 3078 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 3079 .phylink_mac_config = mt753x_phylink_mac_config, 3080 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 3081 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3082 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3083 .get_mac_eee = mt753x_get_mac_eee, 3084 .set_mac_eee = mt753x_set_mac_eee, 3085 }; 3086 3087 static const struct mt753x_info mt753x_table[] = { 3088 [ID_MT7621] = { 3089 .id = ID_MT7621, 3090 .sw_setup = mt7530_setup, 3091 .phy_read = mt7530_phy_read, 3092 .phy_write = mt7530_phy_write, 3093 .pad_setup = mt7530_pad_clk_setup, 3094 .phy_mode_supported = mt7530_phy_mode_supported, 3095 .mac_port_validate = mt7530_mac_port_validate, 3096 .mac_port_get_state = mt7530_phylink_mac_link_state, 3097 .mac_port_config = mt7530_mac_config, 3098 }, 3099 [ID_MT7530] = { 3100 .id = ID_MT7530, 3101 .sw_setup = mt7530_setup, 3102 .phy_read = mt7530_phy_read, 3103 .phy_write = mt7530_phy_write, 3104 .pad_setup = mt7530_pad_clk_setup, 3105 .phy_mode_supported = mt7530_phy_mode_supported, 3106 .mac_port_validate = mt7530_mac_port_validate, 3107 .mac_port_get_state = mt7530_phylink_mac_link_state, 3108 .mac_port_config = mt7530_mac_config, 3109 }, 3110 [ID_MT7531] = { 3111 .id = ID_MT7531, 3112 .sw_setup = mt7531_setup, 3113 .phy_read = mt7531_ind_phy_read, 3114 .phy_write = mt7531_ind_phy_write, 3115 .pad_setup = mt7531_pad_setup, 3116 .cpu_port_config = mt7531_cpu_port_config, 3117 .phy_mode_supported = mt7531_phy_mode_supported, 3118 .mac_port_validate = mt7531_mac_port_validate, 3119 .mac_port_get_state = mt7531_phylink_mac_link_state, 3120 .mac_port_config = mt7531_mac_config, 3121 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 3122 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 3123 }, 3124 }; 3125 3126 static const struct of_device_id mt7530_of_match[] = { 3127 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3128 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3129 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3130 { /* sentinel */ }, 3131 }; 3132 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3133 3134 static int 3135 mt7530_probe(struct mdio_device *mdiodev) 3136 { 3137 struct mt7530_priv *priv; 3138 struct device_node *dn; 3139 3140 dn = mdiodev->dev.of_node; 3141 3142 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3143 if (!priv) 3144 return -ENOMEM; 3145 3146 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3147 if (!priv->ds) 3148 return -ENOMEM; 3149 3150 priv->ds->dev = &mdiodev->dev; 3151 priv->ds->num_ports = DSA_MAX_PORTS; 3152 3153 /* Use medatek,mcm property to distinguish hardware type that would 3154 * casues a little bit differences on power-on sequence. 3155 */ 3156 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3157 if (priv->mcm) { 3158 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3159 3160 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3161 if (IS_ERR(priv->rstc)) { 3162 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3163 return PTR_ERR(priv->rstc); 3164 } 3165 } 3166 3167 /* Get the hardware identifier from the devicetree node. 3168 * We will need it for some of the clock and regulator setup. 3169 */ 3170 priv->info = of_device_get_match_data(&mdiodev->dev); 3171 if (!priv->info) 3172 return -EINVAL; 3173 3174 /* Sanity check if these required device operations are filled 3175 * properly. 3176 */ 3177 if (!priv->info->sw_setup || !priv->info->pad_setup || 3178 !priv->info->phy_read || !priv->info->phy_write || 3179 !priv->info->phy_mode_supported || 3180 !priv->info->mac_port_validate || 3181 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 3182 return -EINVAL; 3183 3184 priv->id = priv->info->id; 3185 3186 if (priv->id == ID_MT7530) { 3187 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3188 if (IS_ERR(priv->core_pwr)) 3189 return PTR_ERR(priv->core_pwr); 3190 3191 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3192 if (IS_ERR(priv->io_pwr)) 3193 return PTR_ERR(priv->io_pwr); 3194 } 3195 3196 /* Not MCM that indicates switch works as the remote standalone 3197 * integrated circuit so the GPIO pin would be used to complete 3198 * the reset, otherwise memory-mapped register accessing used 3199 * through syscon provides in the case of MCM. 3200 */ 3201 if (!priv->mcm) { 3202 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3203 GPIOD_OUT_LOW); 3204 if (IS_ERR(priv->reset)) { 3205 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3206 return PTR_ERR(priv->reset); 3207 } 3208 } 3209 3210 priv->bus = mdiodev->bus; 3211 priv->dev = &mdiodev->dev; 3212 priv->ds->priv = priv; 3213 priv->ds->ops = &mt7530_switch_ops; 3214 mutex_init(&priv->reg_mutex); 3215 dev_set_drvdata(&mdiodev->dev, priv); 3216 3217 return dsa_register_switch(priv->ds); 3218 } 3219 3220 static void 3221 mt7530_remove(struct mdio_device *mdiodev) 3222 { 3223 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3224 int ret = 0; 3225 3226 ret = regulator_disable(priv->core_pwr); 3227 if (ret < 0) 3228 dev_err(priv->dev, 3229 "Failed to disable core power: %d\n", ret); 3230 3231 ret = regulator_disable(priv->io_pwr); 3232 if (ret < 0) 3233 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3234 ret); 3235 3236 if (priv->irq) 3237 mt7530_free_irq(priv); 3238 3239 dsa_unregister_switch(priv->ds); 3240 mutex_destroy(&priv->reg_mutex); 3241 } 3242 3243 static struct mdio_driver mt7530_mdio_driver = { 3244 .probe = mt7530_probe, 3245 .remove = mt7530_remove, 3246 .mdiodrv.driver = { 3247 .name = "mt7530", 3248 .of_match_table = mt7530_of_match, 3249 }, 3250 }; 3251 3252 mdio_module_driver(mt7530_mdio_driver); 3253 3254 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3255 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3256 MODULE_LICENSE("GPL"); 3257