1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_net.h> 15 #include <linux/of_platform.h> 16 #include <linux/phy.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/gpio/consumer.h> 21 #include <net/dsa.h> 22 23 #include "mt7530.h" 24 25 /* String, offset, and register size in bytes if different from 4 bytes */ 26 static const struct mt7530_mib_desc mt7530_mib[] = { 27 MIB_DESC(1, 0x00, "TxDrop"), 28 MIB_DESC(1, 0x04, "TxCrcErr"), 29 MIB_DESC(1, 0x08, "TxUnicast"), 30 MIB_DESC(1, 0x0c, "TxMulticast"), 31 MIB_DESC(1, 0x10, "TxBroadcast"), 32 MIB_DESC(1, 0x14, "TxCollision"), 33 MIB_DESC(1, 0x18, "TxSingleCollision"), 34 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 35 MIB_DESC(1, 0x20, "TxDeferred"), 36 MIB_DESC(1, 0x24, "TxLateCollision"), 37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 38 MIB_DESC(1, 0x2c, "TxPause"), 39 MIB_DESC(1, 0x30, "TxPktSz64"), 40 MIB_DESC(1, 0x34, "TxPktSz65To127"), 41 MIB_DESC(1, 0x38, "TxPktSz128To255"), 42 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 43 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 44 MIB_DESC(1, 0x44, "Tx1024ToMax"), 45 MIB_DESC(2, 0x48, "TxBytes"), 46 MIB_DESC(1, 0x60, "RxDrop"), 47 MIB_DESC(1, 0x64, "RxFiltering"), 48 MIB_DESC(1, 0x6c, "RxMulticast"), 49 MIB_DESC(1, 0x70, "RxBroadcast"), 50 MIB_DESC(1, 0x74, "RxAlignErr"), 51 MIB_DESC(1, 0x78, "RxCrcErr"), 52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 53 MIB_DESC(1, 0x80, "RxFragErr"), 54 MIB_DESC(1, 0x84, "RxOverSzErr"), 55 MIB_DESC(1, 0x88, "RxJabberErr"), 56 MIB_DESC(1, 0x8c, "RxPause"), 57 MIB_DESC(1, 0x90, "RxPktSz64"), 58 MIB_DESC(1, 0x94, "RxPktSz65To127"), 59 MIB_DESC(1, 0x98, "RxPktSz128To255"), 60 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 63 MIB_DESC(2, 0xa8, "RxBytes"), 64 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 65 MIB_DESC(1, 0xb4, "RxIngressDrop"), 66 MIB_DESC(1, 0xb8, "RxArlDrop"), 67 }; 68 69 static int 70 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) 71 { 72 int ret; 73 74 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); 75 if (ret < 0) 76 dev_err(priv->dev, 77 "failed to priv write register\n"); 78 return ret; 79 } 80 81 static u32 82 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) 83 { 84 int ret; 85 u32 val; 86 87 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); 88 if (ret < 0) { 89 dev_err(priv->dev, 90 "failed to priv read register\n"); 91 return ret; 92 } 93 94 return val; 95 } 96 97 static void 98 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, 99 u32 mask, u32 set) 100 { 101 u32 val; 102 103 val = mt7623_trgmii_read(priv, reg); 104 val &= ~mask; 105 val |= set; 106 mt7623_trgmii_write(priv, reg, val); 107 } 108 109 static void 110 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) 111 { 112 mt7623_trgmii_rmw(priv, reg, 0, val); 113 } 114 115 static void 116 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) 117 { 118 mt7623_trgmii_rmw(priv, reg, val, 0); 119 } 120 121 static int 122 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 123 { 124 struct mii_bus *bus = priv->bus; 125 int value, ret; 126 127 /* Write the desired MMD Devad */ 128 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 129 if (ret < 0) 130 goto err; 131 132 /* Write the desired MMD register address */ 133 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 134 if (ret < 0) 135 goto err; 136 137 /* Select the Function : DATA with no post increment */ 138 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 139 if (ret < 0) 140 goto err; 141 142 /* Read the content of the MMD's selected register */ 143 value = bus->read(bus, 0, MII_MMD_DATA); 144 145 return value; 146 err: 147 dev_err(&bus->dev, "failed to read mmd register\n"); 148 149 return ret; 150 } 151 152 static int 153 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 154 int devad, u32 data) 155 { 156 struct mii_bus *bus = priv->bus; 157 int ret; 158 159 /* Write the desired MMD Devad */ 160 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 161 if (ret < 0) 162 goto err; 163 164 /* Write the desired MMD register address */ 165 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 166 if (ret < 0) 167 goto err; 168 169 /* Select the Function : DATA with no post increment */ 170 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 171 if (ret < 0) 172 goto err; 173 174 /* Write the data into MMD's selected register */ 175 ret = bus->write(bus, 0, MII_MMD_DATA, data); 176 err: 177 if (ret < 0) 178 dev_err(&bus->dev, 179 "failed to write mmd register\n"); 180 return ret; 181 } 182 183 static void 184 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 struct mii_bus *bus = priv->bus; 187 188 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 189 190 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 191 192 mutex_unlock(&bus->mdio_lock); 193 } 194 195 static void 196 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 197 { 198 struct mii_bus *bus = priv->bus; 199 u32 val; 200 201 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 202 203 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 204 val &= ~mask; 205 val |= set; 206 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 207 208 mutex_unlock(&bus->mdio_lock); 209 } 210 211 static void 212 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 213 { 214 core_rmw(priv, reg, 0, val); 215 } 216 217 static void 218 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 219 { 220 core_rmw(priv, reg, val, 0); 221 } 222 223 static int 224 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 225 { 226 struct mii_bus *bus = priv->bus; 227 u16 page, r, lo, hi; 228 int ret; 229 230 page = (reg >> 6) & 0x3ff; 231 r = (reg >> 2) & 0xf; 232 lo = val & 0xffff; 233 hi = val >> 16; 234 235 /* MT7530 uses 31 as the pseudo port */ 236 ret = bus->write(bus, 0x1f, 0x1f, page); 237 if (ret < 0) 238 goto err; 239 240 ret = bus->write(bus, 0x1f, r, lo); 241 if (ret < 0) 242 goto err; 243 244 ret = bus->write(bus, 0x1f, 0x10, hi); 245 err: 246 if (ret < 0) 247 dev_err(&bus->dev, 248 "failed to write mt7530 register\n"); 249 return ret; 250 } 251 252 static u32 253 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 254 { 255 struct mii_bus *bus = priv->bus; 256 u16 page, r, lo, hi; 257 int ret; 258 259 page = (reg >> 6) & 0x3ff; 260 r = (reg >> 2) & 0xf; 261 262 /* MT7530 uses 31 as the pseudo port */ 263 ret = bus->write(bus, 0x1f, 0x1f, page); 264 if (ret < 0) { 265 dev_err(&bus->dev, 266 "failed to read mt7530 register\n"); 267 return ret; 268 } 269 270 lo = bus->read(bus, 0x1f, r); 271 hi = bus->read(bus, 0x1f, 0x10); 272 273 return (hi << 16) | (lo & 0xffff); 274 } 275 276 static void 277 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 struct mii_bus *bus = priv->bus; 280 281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 282 283 mt7530_mii_write(priv, reg, val); 284 285 mutex_unlock(&bus->mdio_lock); 286 } 287 288 static u32 289 _mt7530_read(struct mt7530_dummy_poll *p) 290 { 291 struct mii_bus *bus = p->priv->bus; 292 u32 val; 293 294 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 295 296 val = mt7530_mii_read(p->priv, p->reg); 297 298 mutex_unlock(&bus->mdio_lock); 299 300 return val; 301 } 302 303 static u32 304 mt7530_read(struct mt7530_priv *priv, u32 reg) 305 { 306 struct mt7530_dummy_poll p; 307 308 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 309 return _mt7530_read(&p); 310 } 311 312 static void 313 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 314 u32 mask, u32 set) 315 { 316 struct mii_bus *bus = priv->bus; 317 u32 val; 318 319 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 320 321 val = mt7530_mii_read(priv, reg); 322 val &= ~mask; 323 val |= set; 324 mt7530_mii_write(priv, reg, val); 325 326 mutex_unlock(&bus->mdio_lock); 327 } 328 329 static void 330 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 331 { 332 mt7530_rmw(priv, reg, 0, val); 333 } 334 335 static void 336 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 337 { 338 mt7530_rmw(priv, reg, val, 0); 339 } 340 341 static int 342 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 343 { 344 u32 val; 345 int ret; 346 struct mt7530_dummy_poll p; 347 348 /* Set the command operating upon the MAC address entries */ 349 val = ATC_BUSY | ATC_MAT(0) | cmd; 350 mt7530_write(priv, MT7530_ATC, val); 351 352 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 353 ret = readx_poll_timeout(_mt7530_read, &p, val, 354 !(val & ATC_BUSY), 20, 20000); 355 if (ret < 0) { 356 dev_err(priv->dev, "reset timeout\n"); 357 return ret; 358 } 359 360 /* Additional sanity for read command if the specified 361 * entry is invalid 362 */ 363 val = mt7530_read(priv, MT7530_ATC); 364 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 365 return -EINVAL; 366 367 if (rsp) 368 *rsp = val; 369 370 return 0; 371 } 372 373 static void 374 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 375 { 376 u32 reg[3]; 377 int i; 378 379 /* Read from ARL table into an array */ 380 for (i = 0; i < 3; i++) { 381 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 382 383 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 384 __func__, __LINE__, i, reg[i]); 385 } 386 387 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 388 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 389 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 390 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 391 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 392 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 393 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 394 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 395 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 396 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 397 } 398 399 static void 400 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 401 u8 port_mask, const u8 *mac, 402 u8 aging, u8 type) 403 { 404 u32 reg[3] = { 0 }; 405 int i; 406 407 reg[1] |= vid & CVID_MASK; 408 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 409 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 410 /* STATIC_ENT indicate that entry is static wouldn't 411 * be aged out and STATIC_EMP specified as erasing an 412 * entry 413 */ 414 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 415 reg[1] |= mac[5] << MAC_BYTE_5; 416 reg[1] |= mac[4] << MAC_BYTE_4; 417 reg[0] |= mac[3] << MAC_BYTE_3; 418 reg[0] |= mac[2] << MAC_BYTE_2; 419 reg[0] |= mac[1] << MAC_BYTE_1; 420 reg[0] |= mac[0] << MAC_BYTE_0; 421 422 /* Write array into the ARL table */ 423 for (i = 0; i < 3; i++) 424 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 425 } 426 427 static int 428 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) 429 { 430 struct mt7530_priv *priv = ds->priv; 431 u32 ncpo1, ssc_delta, trgint, i, xtal; 432 433 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 434 435 if (xtal == HWTRAP_XTAL_20MHZ) { 436 dev_err(priv->dev, 437 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 438 __func__); 439 return -EINVAL; 440 } 441 442 switch (mode) { 443 case PHY_INTERFACE_MODE_RGMII: 444 trgint = 0; 445 /* PLL frequency: 125MHz */ 446 ncpo1 = 0x0c80; 447 break; 448 case PHY_INTERFACE_MODE_TRGMII: 449 trgint = 1; 450 if (priv->id == ID_MT7621) { 451 /* PLL frequency: 150MHz: 1.2GBit */ 452 if (xtal == HWTRAP_XTAL_40MHZ) 453 ncpo1 = 0x0780; 454 if (xtal == HWTRAP_XTAL_25MHZ) 455 ncpo1 = 0x0a00; 456 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 457 if (xtal == HWTRAP_XTAL_40MHZ) 458 ncpo1 = 0x0c80; 459 if (xtal == HWTRAP_XTAL_25MHZ) 460 ncpo1 = 0x1400; 461 } 462 break; 463 default: 464 dev_err(priv->dev, "xMII mode %d not supported\n", mode); 465 return -EINVAL; 466 } 467 468 if (xtal == HWTRAP_XTAL_25MHZ) 469 ssc_delta = 0x57; 470 else 471 ssc_delta = 0x87; 472 473 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 474 P6_INTF_MODE(trgint)); 475 476 /* Lower Tx Driving for TRGMII path */ 477 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 478 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 479 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 480 481 /* Setup core clock for MT7530 */ 482 if (!trgint) { 483 /* Disable MT7530 core clock */ 484 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 485 486 /* Disable PLL, since phy_device has not yet been created 487 * provided for phy_[read,write]_mmd_indirect is called, we 488 * provide our own core_write_mmd_indirect to complete this 489 * function. 490 */ 491 core_write_mmd_indirect(priv, 492 CORE_GSWPLL_GRP1, 493 MDIO_MMD_VEND2, 494 0); 495 496 /* Set core clock into 500Mhz */ 497 core_write(priv, CORE_GSWPLL_GRP2, 498 RG_GSWPLL_POSDIV_500M(1) | 499 RG_GSWPLL_FBKDIV_500M(25)); 500 501 /* Enable PLL */ 502 core_write(priv, CORE_GSWPLL_GRP1, 503 RG_GSWPLL_EN_PRE | 504 RG_GSWPLL_POSDIV_200M(2) | 505 RG_GSWPLL_FBKDIV_200M(32)); 506 507 /* Enable MT7530 core clock */ 508 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 509 } 510 511 /* Setup the MT7530 TRGMII Tx Clock */ 512 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 513 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 514 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 515 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 516 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 517 core_write(priv, CORE_PLL_GROUP4, 518 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 519 RG_SYSPLL_BIAS_LPF_EN); 520 core_write(priv, CORE_PLL_GROUP2, 521 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 522 RG_SYSPLL_POSDIV(1)); 523 core_write(priv, CORE_PLL_GROUP7, 524 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 525 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 526 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 527 REG_GSWCK_EN | REG_TRGMIICK_EN); 528 529 if (!trgint) 530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 531 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 532 RD_TAP_MASK, RD_TAP(16)); 533 else 534 if (priv->id != ID_MT7621) 535 mt7623_trgmii_set(priv, GSW_INTF_MODE, 536 INTF_MODE_TRGMII); 537 538 return 0; 539 } 540 541 static int 542 mt7623_pad_clk_setup(struct dsa_switch *ds) 543 { 544 struct mt7530_priv *priv = ds->priv; 545 int i; 546 547 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 548 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), 549 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 550 551 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); 552 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); 553 554 return 0; 555 } 556 557 static void 558 mt7530_mib_reset(struct dsa_switch *ds) 559 { 560 struct mt7530_priv *priv = ds->priv; 561 562 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 563 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 564 } 565 566 static void 567 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) 568 { 569 u32 mask = PMCR_TX_EN | PMCR_RX_EN; 570 571 if (enable) 572 mt7530_set(priv, MT7530_PMCR_P(port), mask); 573 else 574 mt7530_clear(priv, MT7530_PMCR_P(port), mask); 575 } 576 577 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 578 { 579 struct mt7530_priv *priv = ds->priv; 580 581 return mdiobus_read_nested(priv->bus, port, regnum); 582 } 583 584 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 585 u16 val) 586 { 587 struct mt7530_priv *priv = ds->priv; 588 589 return mdiobus_write_nested(priv->bus, port, regnum, val); 590 } 591 592 static void 593 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 594 uint8_t *data) 595 { 596 int i; 597 598 if (stringset != ETH_SS_STATS) 599 return; 600 601 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 602 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 603 ETH_GSTRING_LEN); 604 } 605 606 static void 607 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 608 uint64_t *data) 609 { 610 struct mt7530_priv *priv = ds->priv; 611 const struct mt7530_mib_desc *mib; 612 u32 reg, i; 613 u64 hi; 614 615 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 616 mib = &mt7530_mib[i]; 617 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 618 619 data[i] = mt7530_read(priv, reg); 620 if (mib->size == 2) { 621 hi = mt7530_read(priv, reg + 4); 622 data[i] |= hi << 32; 623 } 624 } 625 } 626 627 static int 628 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 629 { 630 if (sset != ETH_SS_STATS) 631 return 0; 632 633 return ARRAY_SIZE(mt7530_mib); 634 } 635 636 static void mt7530_adjust_link(struct dsa_switch *ds, int port, 637 struct phy_device *phydev) 638 { 639 struct mt7530_priv *priv = ds->priv; 640 641 if (phy_is_pseudo_fixed_link(phydev)) { 642 dev_dbg(priv->dev, "phy-mode for master device = %x\n", 643 phydev->interface); 644 645 /* Setup TX circuit incluing relevant PAD and driving */ 646 mt7530_pad_clk_setup(ds, phydev->interface); 647 648 if (priv->id == ID_MT7530) { 649 /* Setup RX circuit, relevant PAD and driving on the 650 * host which must be placed after the setup on the 651 * device side is all finished. 652 */ 653 mt7623_pad_clk_setup(ds); 654 } 655 } else { 656 u16 lcl_adv = 0, rmt_adv = 0; 657 u8 flowctrl; 658 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE; 659 660 switch (phydev->speed) { 661 case SPEED_1000: 662 mcr |= PMCR_FORCE_SPEED_1000; 663 break; 664 case SPEED_100: 665 mcr |= PMCR_FORCE_SPEED_100; 666 break; 667 } 668 669 if (phydev->link) 670 mcr |= PMCR_FORCE_LNK; 671 672 if (phydev->duplex) { 673 mcr |= PMCR_FORCE_FDX; 674 675 if (phydev->pause) 676 rmt_adv = LPA_PAUSE_CAP; 677 if (phydev->asym_pause) 678 rmt_adv |= LPA_PAUSE_ASYM; 679 680 lcl_adv = linkmode_adv_to_lcl_adv_t( 681 phydev->advertising); 682 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 683 684 if (flowctrl & FLOW_CTRL_TX) 685 mcr |= PMCR_TX_FC_EN; 686 if (flowctrl & FLOW_CTRL_RX) 687 mcr |= PMCR_RX_FC_EN; 688 } 689 mt7530_write(priv, MT7530_PMCR_P(port), mcr); 690 } 691 } 692 693 static int 694 mt7530_cpu_port_enable(struct mt7530_priv *priv, 695 int port) 696 { 697 /* Enable Mediatek header mode on the cpu port */ 698 mt7530_write(priv, MT7530_PVC_P(port), 699 PORT_SPEC_TAG); 700 701 /* Setup the MAC by default for the cpu port */ 702 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK); 703 704 /* Disable auto learning on the cpu port */ 705 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); 706 707 /* Unknown unicast frame fordwarding to the cpu port */ 708 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); 709 710 /* Set CPU port number */ 711 if (priv->id == ID_MT7621) 712 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 713 714 /* CPU port gets connected to all user ports of 715 * the switch 716 */ 717 mt7530_write(priv, MT7530_PCR_P(port), 718 PCR_MATRIX(dsa_user_ports(priv->ds))); 719 720 return 0; 721 } 722 723 static int 724 mt7530_port_enable(struct dsa_switch *ds, int port, 725 struct phy_device *phy) 726 { 727 struct mt7530_priv *priv = ds->priv; 728 729 mutex_lock(&priv->reg_mutex); 730 731 /* Setup the MAC for the user port */ 732 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK); 733 734 /* Allow the user port gets connected to the cpu port and also 735 * restore the port matrix if the port is the member of a certain 736 * bridge. 737 */ 738 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 739 priv->ports[port].enable = true; 740 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 741 priv->ports[port].pm); 742 mt7530_port_set_status(priv, port, 1); 743 744 mutex_unlock(&priv->reg_mutex); 745 746 return 0; 747 } 748 749 static void 750 mt7530_port_disable(struct dsa_switch *ds, int port) 751 { 752 struct mt7530_priv *priv = ds->priv; 753 754 mutex_lock(&priv->reg_mutex); 755 756 /* Clear up all port matrix which could be restored in the next 757 * enablement for the port. 758 */ 759 priv->ports[port].enable = false; 760 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 761 PCR_MATRIX_CLR); 762 mt7530_port_set_status(priv, port, 0); 763 764 mutex_unlock(&priv->reg_mutex); 765 } 766 767 static void 768 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 769 { 770 struct mt7530_priv *priv = ds->priv; 771 u32 stp_state; 772 773 switch (state) { 774 case BR_STATE_DISABLED: 775 stp_state = MT7530_STP_DISABLED; 776 break; 777 case BR_STATE_BLOCKING: 778 stp_state = MT7530_STP_BLOCKING; 779 break; 780 case BR_STATE_LISTENING: 781 stp_state = MT7530_STP_LISTENING; 782 break; 783 case BR_STATE_LEARNING: 784 stp_state = MT7530_STP_LEARNING; 785 break; 786 case BR_STATE_FORWARDING: 787 default: 788 stp_state = MT7530_STP_FORWARDING; 789 break; 790 } 791 792 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 793 } 794 795 static int 796 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 797 struct net_device *bridge) 798 { 799 struct mt7530_priv *priv = ds->priv; 800 u32 port_bitmap = BIT(MT7530_CPU_PORT); 801 int i; 802 803 mutex_lock(&priv->reg_mutex); 804 805 for (i = 0; i < MT7530_NUM_PORTS; i++) { 806 /* Add this port to the port matrix of the other ports in the 807 * same bridge. If the port is disabled, port matrix is kept 808 * and not being setup until the port becomes enabled. 809 */ 810 if (dsa_is_user_port(ds, i) && i != port) { 811 if (dsa_to_port(ds, i)->bridge_dev != bridge) 812 continue; 813 if (priv->ports[i].enable) 814 mt7530_set(priv, MT7530_PCR_P(i), 815 PCR_MATRIX(BIT(port))); 816 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 817 818 port_bitmap |= BIT(i); 819 } 820 } 821 822 /* Add the all other ports to this port matrix. */ 823 if (priv->ports[port].enable) 824 mt7530_rmw(priv, MT7530_PCR_P(port), 825 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 826 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 827 828 mutex_unlock(&priv->reg_mutex); 829 830 return 0; 831 } 832 833 static void 834 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 835 { 836 struct mt7530_priv *priv = ds->priv; 837 bool all_user_ports_removed = true; 838 int i; 839 840 /* When a port is removed from the bridge, the port would be set up 841 * back to the default as is at initial boot which is a VLAN-unaware 842 * port. 843 */ 844 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 845 MT7530_PORT_MATRIX_MODE); 846 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 847 VLAN_ATTR(MT7530_VLAN_TRANSPARENT)); 848 849 for (i = 0; i < MT7530_NUM_PORTS; i++) { 850 if (dsa_is_user_port(ds, i) && 851 dsa_port_is_vlan_filtering(&ds->ports[i])) { 852 all_user_ports_removed = false; 853 break; 854 } 855 } 856 857 /* CPU port also does the same thing until all user ports belonging to 858 * the CPU port get out of VLAN filtering mode. 859 */ 860 if (all_user_ports_removed) { 861 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 862 PCR_MATRIX(dsa_user_ports(priv->ds))); 863 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), 864 PORT_SPEC_TAG); 865 } 866 } 867 868 static void 869 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 870 { 871 struct mt7530_priv *priv = ds->priv; 872 873 /* The real fabric path would be decided on the membership in the 874 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 875 * means potential VLAN can be consisting of certain subset of all 876 * ports. 877 */ 878 mt7530_rmw(priv, MT7530_PCR_P(port), 879 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 880 881 /* Trapped into security mode allows packet forwarding through VLAN 882 * table lookup. 883 */ 884 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 885 MT7530_PORT_SECURITY_MODE); 886 887 /* Set the port as a user port which is to be able to recognize VID 888 * from incoming packets before fetching entry within the VLAN table. 889 */ 890 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 891 VLAN_ATTR(MT7530_VLAN_USER)); 892 } 893 894 static void 895 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 896 struct net_device *bridge) 897 { 898 struct mt7530_priv *priv = ds->priv; 899 int i; 900 901 mutex_lock(&priv->reg_mutex); 902 903 for (i = 0; i < MT7530_NUM_PORTS; i++) { 904 /* Remove this port from the port matrix of the other ports 905 * in the same bridge. If the port is disabled, port matrix 906 * is kept and not being setup until the port becomes enabled. 907 * And the other port's port matrix cannot be broken when the 908 * other port is still a VLAN-aware port. 909 */ 910 if (dsa_is_user_port(ds, i) && i != port && 911 !dsa_port_is_vlan_filtering(&ds->ports[i])) { 912 if (dsa_to_port(ds, i)->bridge_dev != bridge) 913 continue; 914 if (priv->ports[i].enable) 915 mt7530_clear(priv, MT7530_PCR_P(i), 916 PCR_MATRIX(BIT(port))); 917 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 918 } 919 } 920 921 /* Set the cpu port to be the only one in the port matrix of 922 * this port. 923 */ 924 if (priv->ports[port].enable) 925 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 926 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 927 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 928 929 mutex_unlock(&priv->reg_mutex); 930 } 931 932 static int 933 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 934 const unsigned char *addr, u16 vid) 935 { 936 struct mt7530_priv *priv = ds->priv; 937 int ret; 938 u8 port_mask = BIT(port); 939 940 mutex_lock(&priv->reg_mutex); 941 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 942 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 943 mutex_unlock(&priv->reg_mutex); 944 945 return ret; 946 } 947 948 static int 949 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 950 const unsigned char *addr, u16 vid) 951 { 952 struct mt7530_priv *priv = ds->priv; 953 int ret; 954 u8 port_mask = BIT(port); 955 956 mutex_lock(&priv->reg_mutex); 957 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 958 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 959 mutex_unlock(&priv->reg_mutex); 960 961 return ret; 962 } 963 964 static int 965 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 966 dsa_fdb_dump_cb_t *cb, void *data) 967 { 968 struct mt7530_priv *priv = ds->priv; 969 struct mt7530_fdb _fdb = { 0 }; 970 int cnt = MT7530_NUM_FDB_RECORDS; 971 int ret = 0; 972 u32 rsp = 0; 973 974 mutex_lock(&priv->reg_mutex); 975 976 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 977 if (ret < 0) 978 goto err; 979 980 do { 981 if (rsp & ATC_SRCH_HIT) { 982 mt7530_fdb_read(priv, &_fdb); 983 if (_fdb.port_mask & BIT(port)) { 984 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 985 data); 986 if (ret < 0) 987 break; 988 } 989 } 990 } while (--cnt && 991 !(rsp & ATC_SRCH_END) && 992 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 993 err: 994 mutex_unlock(&priv->reg_mutex); 995 996 return 0; 997 } 998 999 static int 1000 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1001 { 1002 struct mt7530_dummy_poll p; 1003 u32 val; 1004 int ret; 1005 1006 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1007 mt7530_write(priv, MT7530_VTCR, val); 1008 1009 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1010 ret = readx_poll_timeout(_mt7530_read, &p, val, 1011 !(val & VTCR_BUSY), 20, 20000); 1012 if (ret < 0) { 1013 dev_err(priv->dev, "poll timeout\n"); 1014 return ret; 1015 } 1016 1017 val = mt7530_read(priv, MT7530_VTCR); 1018 if (val & VTCR_INVALID) { 1019 dev_err(priv->dev, "read VTCR invalid\n"); 1020 return -EINVAL; 1021 } 1022 1023 return 0; 1024 } 1025 1026 static int 1027 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, 1028 bool vlan_filtering) 1029 { 1030 if (vlan_filtering) { 1031 /* The port is being kept as VLAN-unaware port when bridge is 1032 * set up with vlan_filtering not being set, Otherwise, the 1033 * port and the corresponding CPU port is required the setup 1034 * for becoming a VLAN-aware port. 1035 */ 1036 mt7530_port_set_vlan_aware(ds, port); 1037 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1038 } else { 1039 mt7530_port_set_vlan_unaware(ds, port); 1040 } 1041 1042 return 0; 1043 } 1044 1045 static int 1046 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, 1047 const struct switchdev_obj_port_vlan *vlan) 1048 { 1049 /* nothing needed */ 1050 1051 return 0; 1052 } 1053 1054 static void 1055 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1056 struct mt7530_hw_vlan_entry *entry) 1057 { 1058 u8 new_members; 1059 u32 val; 1060 1061 new_members = entry->old_members | BIT(entry->port) | 1062 BIT(MT7530_CPU_PORT); 1063 1064 /* Validate the entry with independent learning, create egress tag per 1065 * VLAN and joining the port as one of the port members. 1066 */ 1067 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1068 mt7530_write(priv, MT7530_VAWD1, val); 1069 1070 /* Decide whether adding tag or not for those outgoing packets from the 1071 * port inside the VLAN. 1072 */ 1073 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1074 MT7530_VLAN_EGRESS_TAG; 1075 mt7530_rmw(priv, MT7530_VAWD2, 1076 ETAG_CTRL_P_MASK(entry->port), 1077 ETAG_CTRL_P(entry->port, val)); 1078 1079 /* CPU port is always taken as a tagged port for serving more than one 1080 * VLANs across and also being applied with egress type stack mode for 1081 * that VLAN tags would be appended after hardware special tag used as 1082 * DSA tag. 1083 */ 1084 mt7530_rmw(priv, MT7530_VAWD2, 1085 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1086 ETAG_CTRL_P(MT7530_CPU_PORT, 1087 MT7530_VLAN_EGRESS_STACK)); 1088 } 1089 1090 static void 1091 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1092 struct mt7530_hw_vlan_entry *entry) 1093 { 1094 u8 new_members; 1095 u32 val; 1096 1097 new_members = entry->old_members & ~BIT(entry->port); 1098 1099 val = mt7530_read(priv, MT7530_VAWD1); 1100 if (!(val & VLAN_VALID)) { 1101 dev_err(priv->dev, 1102 "Cannot be deleted due to invalid entry\n"); 1103 return; 1104 } 1105 1106 /* If certain member apart from CPU port is still alive in the VLAN, 1107 * the entry would be kept valid. Otherwise, the entry is got to be 1108 * disabled. 1109 */ 1110 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1111 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1112 VLAN_VALID; 1113 mt7530_write(priv, MT7530_VAWD1, val); 1114 } else { 1115 mt7530_write(priv, MT7530_VAWD1, 0); 1116 mt7530_write(priv, MT7530_VAWD2, 0); 1117 } 1118 } 1119 1120 static void 1121 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1122 struct mt7530_hw_vlan_entry *entry, 1123 mt7530_vlan_op vlan_op) 1124 { 1125 u32 val; 1126 1127 /* Fetch entry */ 1128 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1129 1130 val = mt7530_read(priv, MT7530_VAWD1); 1131 1132 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1133 1134 /* Manipulate entry */ 1135 vlan_op(priv, entry); 1136 1137 /* Flush result to hardware */ 1138 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1139 } 1140 1141 static void 1142 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1143 const struct switchdev_obj_port_vlan *vlan) 1144 { 1145 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1146 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1147 struct mt7530_hw_vlan_entry new_entry; 1148 struct mt7530_priv *priv = ds->priv; 1149 u16 vid; 1150 1151 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1152 * being set. 1153 */ 1154 if (!dsa_port_is_vlan_filtering(&ds->ports[port])) 1155 return; 1156 1157 mutex_lock(&priv->reg_mutex); 1158 1159 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1160 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1161 mt7530_hw_vlan_update(priv, vid, &new_entry, 1162 mt7530_hw_vlan_add); 1163 } 1164 1165 if (pvid) { 1166 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1167 G0_PORT_VID(vlan->vid_end)); 1168 priv->ports[port].pvid = vlan->vid_end; 1169 } 1170 1171 mutex_unlock(&priv->reg_mutex); 1172 } 1173 1174 static int 1175 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1176 const struct switchdev_obj_port_vlan *vlan) 1177 { 1178 struct mt7530_hw_vlan_entry target_entry; 1179 struct mt7530_priv *priv = ds->priv; 1180 u16 vid, pvid; 1181 1182 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1183 * being set. 1184 */ 1185 if (!dsa_port_is_vlan_filtering(&ds->ports[port])) 1186 return 0; 1187 1188 mutex_lock(&priv->reg_mutex); 1189 1190 pvid = priv->ports[port].pvid; 1191 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1192 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1193 mt7530_hw_vlan_update(priv, vid, &target_entry, 1194 mt7530_hw_vlan_del); 1195 1196 /* PVID is being restored to the default whenever the PVID port 1197 * is being removed from the VLAN. 1198 */ 1199 if (pvid == vid) 1200 pvid = G0_PORT_VID_DEF; 1201 } 1202 1203 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1204 priv->ports[port].pvid = pvid; 1205 1206 mutex_unlock(&priv->reg_mutex); 1207 1208 return 0; 1209 } 1210 1211 static enum dsa_tag_protocol 1212 mtk_get_tag_protocol(struct dsa_switch *ds, int port) 1213 { 1214 struct mt7530_priv *priv = ds->priv; 1215 1216 if (port != MT7530_CPU_PORT) { 1217 dev_warn(priv->dev, 1218 "port not matched with tagging CPU port\n"); 1219 return DSA_TAG_PROTO_NONE; 1220 } else { 1221 return DSA_TAG_PROTO_MTK; 1222 } 1223 } 1224 1225 static int 1226 mt7530_setup(struct dsa_switch *ds) 1227 { 1228 struct mt7530_priv *priv = ds->priv; 1229 int ret, i; 1230 u32 id, val; 1231 struct device_node *dn; 1232 struct mt7530_dummy_poll p; 1233 1234 /* The parent node of master netdev which holds the common system 1235 * controller also is the container for two GMACs nodes representing 1236 * as two netdev instances. 1237 */ 1238 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent; 1239 1240 if (priv->id == ID_MT7530) { 1241 priv->ethernet = syscon_node_to_regmap(dn); 1242 if (IS_ERR(priv->ethernet)) 1243 return PTR_ERR(priv->ethernet); 1244 1245 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1246 ret = regulator_enable(priv->core_pwr); 1247 if (ret < 0) { 1248 dev_err(priv->dev, 1249 "Failed to enable core power: %d\n", ret); 1250 return ret; 1251 } 1252 1253 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1254 ret = regulator_enable(priv->io_pwr); 1255 if (ret < 0) { 1256 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1257 ret); 1258 return ret; 1259 } 1260 } 1261 1262 /* Reset whole chip through gpio pin or memory-mapped registers for 1263 * different type of hardware 1264 */ 1265 if (priv->mcm) { 1266 reset_control_assert(priv->rstc); 1267 usleep_range(1000, 1100); 1268 reset_control_deassert(priv->rstc); 1269 } else { 1270 gpiod_set_value_cansleep(priv->reset, 0); 1271 usleep_range(1000, 1100); 1272 gpiod_set_value_cansleep(priv->reset, 1); 1273 } 1274 1275 /* Waiting for MT7530 got to stable */ 1276 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1277 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1278 20, 1000000); 1279 if (ret < 0) { 1280 dev_err(priv->dev, "reset timeout\n"); 1281 return ret; 1282 } 1283 1284 id = mt7530_read(priv, MT7530_CREV); 1285 id >>= CHIP_NAME_SHIFT; 1286 if (id != MT7530_ID) { 1287 dev_err(priv->dev, "chip %x can't be supported\n", id); 1288 return -ENODEV; 1289 } 1290 1291 /* Reset the switch through internal reset */ 1292 mt7530_write(priv, MT7530_SYS_CTRL, 1293 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1294 SYS_CTRL_REG_RST); 1295 1296 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1297 val = mt7530_read(priv, MT7530_MHWTRAP); 1298 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1299 val |= MHWTRAP_MANUAL; 1300 mt7530_write(priv, MT7530_MHWTRAP, val); 1301 1302 /* Enable and reset MIB counters */ 1303 mt7530_mib_reset(ds); 1304 1305 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); 1306 1307 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1308 /* Disable forwarding by default on all ports */ 1309 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1310 PCR_MATRIX_CLR); 1311 1312 if (dsa_is_cpu_port(ds, i)) 1313 mt7530_cpu_port_enable(priv, i); 1314 else 1315 mt7530_port_disable(ds, i); 1316 } 1317 1318 /* Flush the FDB table */ 1319 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1320 if (ret < 0) 1321 return ret; 1322 1323 return 0; 1324 } 1325 1326 static const struct dsa_switch_ops mt7530_switch_ops = { 1327 .get_tag_protocol = mtk_get_tag_protocol, 1328 .setup = mt7530_setup, 1329 .get_strings = mt7530_get_strings, 1330 .phy_read = mt7530_phy_read, 1331 .phy_write = mt7530_phy_write, 1332 .get_ethtool_stats = mt7530_get_ethtool_stats, 1333 .get_sset_count = mt7530_get_sset_count, 1334 .adjust_link = mt7530_adjust_link, 1335 .port_enable = mt7530_port_enable, 1336 .port_disable = mt7530_port_disable, 1337 .port_stp_state_set = mt7530_stp_state_set, 1338 .port_bridge_join = mt7530_port_bridge_join, 1339 .port_bridge_leave = mt7530_port_bridge_leave, 1340 .port_fdb_add = mt7530_port_fdb_add, 1341 .port_fdb_del = mt7530_port_fdb_del, 1342 .port_fdb_dump = mt7530_port_fdb_dump, 1343 .port_vlan_filtering = mt7530_port_vlan_filtering, 1344 .port_vlan_prepare = mt7530_port_vlan_prepare, 1345 .port_vlan_add = mt7530_port_vlan_add, 1346 .port_vlan_del = mt7530_port_vlan_del, 1347 }; 1348 1349 static const struct of_device_id mt7530_of_match[] = { 1350 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, }, 1351 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, }, 1352 { /* sentinel */ }, 1353 }; 1354 MODULE_DEVICE_TABLE(of, mt7530_of_match); 1355 1356 static int 1357 mt7530_probe(struct mdio_device *mdiodev) 1358 { 1359 struct mt7530_priv *priv; 1360 struct device_node *dn; 1361 1362 dn = mdiodev->dev.of_node; 1363 1364 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1365 if (!priv) 1366 return -ENOMEM; 1367 1368 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS); 1369 if (!priv->ds) 1370 return -ENOMEM; 1371 1372 /* Use medatek,mcm property to distinguish hardware type that would 1373 * casues a little bit differences on power-on sequence. 1374 */ 1375 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 1376 if (priv->mcm) { 1377 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 1378 1379 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 1380 if (IS_ERR(priv->rstc)) { 1381 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1382 return PTR_ERR(priv->rstc); 1383 } 1384 } 1385 1386 /* Get the hardware identifier from the devicetree node. 1387 * We will need it for some of the clock and regulator setup. 1388 */ 1389 priv->id = (unsigned int)(unsigned long) 1390 of_device_get_match_data(&mdiodev->dev); 1391 1392 if (priv->id == ID_MT7530) { 1393 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 1394 if (IS_ERR(priv->core_pwr)) 1395 return PTR_ERR(priv->core_pwr); 1396 1397 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 1398 if (IS_ERR(priv->io_pwr)) 1399 return PTR_ERR(priv->io_pwr); 1400 } 1401 1402 /* Not MCM that indicates switch works as the remote standalone 1403 * integrated circuit so the GPIO pin would be used to complete 1404 * the reset, otherwise memory-mapped register accessing used 1405 * through syscon provides in the case of MCM. 1406 */ 1407 if (!priv->mcm) { 1408 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 1409 GPIOD_OUT_LOW); 1410 if (IS_ERR(priv->reset)) { 1411 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1412 return PTR_ERR(priv->reset); 1413 } 1414 } 1415 1416 priv->bus = mdiodev->bus; 1417 priv->dev = &mdiodev->dev; 1418 priv->ds->priv = priv; 1419 priv->ds->ops = &mt7530_switch_ops; 1420 mutex_init(&priv->reg_mutex); 1421 dev_set_drvdata(&mdiodev->dev, priv); 1422 1423 return dsa_register_switch(priv->ds); 1424 } 1425 1426 static void 1427 mt7530_remove(struct mdio_device *mdiodev) 1428 { 1429 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 1430 int ret = 0; 1431 1432 ret = regulator_disable(priv->core_pwr); 1433 if (ret < 0) 1434 dev_err(priv->dev, 1435 "Failed to disable core power: %d\n", ret); 1436 1437 ret = regulator_disable(priv->io_pwr); 1438 if (ret < 0) 1439 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 1440 ret); 1441 1442 dsa_unregister_switch(priv->ds); 1443 mutex_destroy(&priv->reg_mutex); 1444 } 1445 1446 static struct mdio_driver mt7530_mdio_driver = { 1447 .probe = mt7530_probe, 1448 .remove = mt7530_remove, 1449 .mdiodrv.driver = { 1450 .name = "mt7530", 1451 .of_match_table = mt7530_of_match, 1452 }, 1453 }; 1454 1455 mdio_module_driver(mt7530_mdio_driver); 1456 1457 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1458 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 1459 MODULE_LICENSE("GPL"); 1460