1 /* 2 * Mediatek MT7530 DSA Switch driver 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <linux/etherdevice.h> 15 #include <linux/if_bridge.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/netdevice.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/gpio/consumer.h> 30 #include <net/dsa.h> 31 #include <net/switchdev.h> 32 33 #include "mt7530.h" 34 35 /* String, offset, and register size in bytes if different from 4 bytes */ 36 static const struct mt7530_mib_desc mt7530_mib[] = { 37 MIB_DESC(1, 0x00, "TxDrop"), 38 MIB_DESC(1, 0x04, "TxCrcErr"), 39 MIB_DESC(1, 0x08, "TxUnicast"), 40 MIB_DESC(1, 0x0c, "TxMulticast"), 41 MIB_DESC(1, 0x10, "TxBroadcast"), 42 MIB_DESC(1, 0x14, "TxCollision"), 43 MIB_DESC(1, 0x18, "TxSingleCollision"), 44 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 45 MIB_DESC(1, 0x20, "TxDeferred"), 46 MIB_DESC(1, 0x24, "TxLateCollision"), 47 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 48 MIB_DESC(1, 0x2c, "TxPause"), 49 MIB_DESC(1, 0x30, "TxPktSz64"), 50 MIB_DESC(1, 0x34, "TxPktSz65To127"), 51 MIB_DESC(1, 0x38, "TxPktSz128To255"), 52 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 53 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 54 MIB_DESC(1, 0x44, "Tx1024ToMax"), 55 MIB_DESC(2, 0x48, "TxBytes"), 56 MIB_DESC(1, 0x60, "RxDrop"), 57 MIB_DESC(1, 0x64, "RxFiltering"), 58 MIB_DESC(1, 0x6c, "RxMulticast"), 59 MIB_DESC(1, 0x70, "RxBroadcast"), 60 MIB_DESC(1, 0x74, "RxAlignErr"), 61 MIB_DESC(1, 0x78, "RxCrcErr"), 62 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 63 MIB_DESC(1, 0x80, "RxFragErr"), 64 MIB_DESC(1, 0x84, "RxOverSzErr"), 65 MIB_DESC(1, 0x88, "RxJabberErr"), 66 MIB_DESC(1, 0x8c, "RxPause"), 67 MIB_DESC(1, 0x90, "RxPktSz64"), 68 MIB_DESC(1, 0x94, "RxPktSz65To127"), 69 MIB_DESC(1, 0x98, "RxPktSz128To255"), 70 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 71 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 72 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 73 MIB_DESC(2, 0xa8, "RxBytes"), 74 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 75 MIB_DESC(1, 0xb4, "RxIngressDrop"), 76 MIB_DESC(1, 0xb8, "RxArlDrop"), 77 }; 78 79 static int 80 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) 81 { 82 int ret; 83 84 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); 85 if (ret < 0) 86 dev_err(priv->dev, 87 "failed to priv write register\n"); 88 return ret; 89 } 90 91 static u32 92 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) 93 { 94 int ret; 95 u32 val; 96 97 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); 98 if (ret < 0) { 99 dev_err(priv->dev, 100 "failed to priv read register\n"); 101 return ret; 102 } 103 104 return val; 105 } 106 107 static void 108 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, 109 u32 mask, u32 set) 110 { 111 u32 val; 112 113 val = mt7623_trgmii_read(priv, reg); 114 val &= ~mask; 115 val |= set; 116 mt7623_trgmii_write(priv, reg, val); 117 } 118 119 static void 120 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) 121 { 122 mt7623_trgmii_rmw(priv, reg, 0, val); 123 } 124 125 static void 126 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) 127 { 128 mt7623_trgmii_rmw(priv, reg, val, 0); 129 } 130 131 static int 132 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 133 { 134 struct mii_bus *bus = priv->bus; 135 int value, ret; 136 137 /* Write the desired MMD Devad */ 138 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 139 if (ret < 0) 140 goto err; 141 142 /* Write the desired MMD register address */ 143 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 144 if (ret < 0) 145 goto err; 146 147 /* Select the Function : DATA with no post increment */ 148 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 149 if (ret < 0) 150 goto err; 151 152 /* Read the content of the MMD's selected register */ 153 value = bus->read(bus, 0, MII_MMD_DATA); 154 155 return value; 156 err: 157 dev_err(&bus->dev, "failed to read mmd register\n"); 158 159 return ret; 160 } 161 162 static int 163 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 164 int devad, u32 data) 165 { 166 struct mii_bus *bus = priv->bus; 167 int ret; 168 169 /* Write the desired MMD Devad */ 170 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 171 if (ret < 0) 172 goto err; 173 174 /* Write the desired MMD register address */ 175 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 176 if (ret < 0) 177 goto err; 178 179 /* Select the Function : DATA with no post increment */ 180 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 181 if (ret < 0) 182 goto err; 183 184 /* Write the data into MMD's selected register */ 185 ret = bus->write(bus, 0, MII_MMD_DATA, data); 186 err: 187 if (ret < 0) 188 dev_err(&bus->dev, 189 "failed to write mmd register\n"); 190 return ret; 191 } 192 193 static void 194 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 195 { 196 struct mii_bus *bus = priv->bus; 197 198 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 199 200 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 201 202 mutex_unlock(&bus->mdio_lock); 203 } 204 205 static void 206 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 207 { 208 struct mii_bus *bus = priv->bus; 209 u32 val; 210 211 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 212 213 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 214 val &= ~mask; 215 val |= set; 216 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 217 218 mutex_unlock(&bus->mdio_lock); 219 } 220 221 static void 222 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 223 { 224 core_rmw(priv, reg, 0, val); 225 } 226 227 static void 228 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 229 { 230 core_rmw(priv, reg, val, 0); 231 } 232 233 static int 234 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 235 { 236 struct mii_bus *bus = priv->bus; 237 u16 page, r, lo, hi; 238 int ret; 239 240 page = (reg >> 6) & 0x3ff; 241 r = (reg >> 2) & 0xf; 242 lo = val & 0xffff; 243 hi = val >> 16; 244 245 /* MT7530 uses 31 as the pseudo port */ 246 ret = bus->write(bus, 0x1f, 0x1f, page); 247 if (ret < 0) 248 goto err; 249 250 ret = bus->write(bus, 0x1f, r, lo); 251 if (ret < 0) 252 goto err; 253 254 ret = bus->write(bus, 0x1f, 0x10, hi); 255 err: 256 if (ret < 0) 257 dev_err(&bus->dev, 258 "failed to write mt7530 register\n"); 259 return ret; 260 } 261 262 static u32 263 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 264 { 265 struct mii_bus *bus = priv->bus; 266 u16 page, r, lo, hi; 267 int ret; 268 269 page = (reg >> 6) & 0x3ff; 270 r = (reg >> 2) & 0xf; 271 272 /* MT7530 uses 31 as the pseudo port */ 273 ret = bus->write(bus, 0x1f, 0x1f, page); 274 if (ret < 0) { 275 dev_err(&bus->dev, 276 "failed to read mt7530 register\n"); 277 return ret; 278 } 279 280 lo = bus->read(bus, 0x1f, r); 281 hi = bus->read(bus, 0x1f, 0x10); 282 283 return (hi << 16) | (lo & 0xffff); 284 } 285 286 static void 287 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 288 { 289 struct mii_bus *bus = priv->bus; 290 291 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 292 293 mt7530_mii_write(priv, reg, val); 294 295 mutex_unlock(&bus->mdio_lock); 296 } 297 298 static u32 299 _mt7530_read(struct mt7530_dummy_poll *p) 300 { 301 struct mii_bus *bus = p->priv->bus; 302 u32 val; 303 304 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 305 306 val = mt7530_mii_read(p->priv, p->reg); 307 308 mutex_unlock(&bus->mdio_lock); 309 310 return val; 311 } 312 313 static u32 314 mt7530_read(struct mt7530_priv *priv, u32 reg) 315 { 316 struct mt7530_dummy_poll p; 317 318 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 319 return _mt7530_read(&p); 320 } 321 322 static void 323 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 324 u32 mask, u32 set) 325 { 326 struct mii_bus *bus = priv->bus; 327 u32 val; 328 329 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 330 331 val = mt7530_mii_read(priv, reg); 332 val &= ~mask; 333 val |= set; 334 mt7530_mii_write(priv, reg, val); 335 336 mutex_unlock(&bus->mdio_lock); 337 } 338 339 static void 340 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 341 { 342 mt7530_rmw(priv, reg, 0, val); 343 } 344 345 static void 346 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 347 { 348 mt7530_rmw(priv, reg, val, 0); 349 } 350 351 static int 352 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 353 { 354 u32 val; 355 int ret; 356 struct mt7530_dummy_poll p; 357 358 /* Set the command operating upon the MAC address entries */ 359 val = ATC_BUSY | ATC_MAT(0) | cmd; 360 mt7530_write(priv, MT7530_ATC, val); 361 362 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 363 ret = readx_poll_timeout(_mt7530_read, &p, val, 364 !(val & ATC_BUSY), 20, 20000); 365 if (ret < 0) { 366 dev_err(priv->dev, "reset timeout\n"); 367 return ret; 368 } 369 370 /* Additional sanity for read command if the specified 371 * entry is invalid 372 */ 373 val = mt7530_read(priv, MT7530_ATC); 374 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 375 return -EINVAL; 376 377 if (rsp) 378 *rsp = val; 379 380 return 0; 381 } 382 383 static void 384 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 385 { 386 u32 reg[3]; 387 int i; 388 389 /* Read from ARL table into an array */ 390 for (i = 0; i < 3; i++) { 391 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 392 393 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 394 __func__, __LINE__, i, reg[i]); 395 } 396 397 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 398 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 399 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 400 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 401 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 402 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 403 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 404 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 405 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 406 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 407 } 408 409 static void 410 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 411 u8 port_mask, const u8 *mac, 412 u8 aging, u8 type) 413 { 414 u32 reg[3] = { 0 }; 415 int i; 416 417 reg[1] |= vid & CVID_MASK; 418 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 419 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 420 /* STATIC_ENT indicate that entry is static wouldn't 421 * be aged out and STATIC_EMP specified as erasing an 422 * entry 423 */ 424 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 425 reg[1] |= mac[5] << MAC_BYTE_5; 426 reg[1] |= mac[4] << MAC_BYTE_4; 427 reg[0] |= mac[3] << MAC_BYTE_3; 428 reg[0] |= mac[2] << MAC_BYTE_2; 429 reg[0] |= mac[1] << MAC_BYTE_1; 430 reg[0] |= mac[0] << MAC_BYTE_0; 431 432 /* Write array into the ARL table */ 433 for (i = 0; i < 3; i++) 434 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 435 } 436 437 static int 438 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) 439 { 440 struct mt7530_priv *priv = ds->priv; 441 u32 ncpo1, ssc_delta, trgint, i; 442 443 switch (mode) { 444 case PHY_INTERFACE_MODE_RGMII: 445 trgint = 0; 446 ncpo1 = 0x0c80; 447 ssc_delta = 0x87; 448 break; 449 case PHY_INTERFACE_MODE_TRGMII: 450 trgint = 1; 451 ncpo1 = 0x1400; 452 ssc_delta = 0x57; 453 break; 454 default: 455 dev_err(priv->dev, "xMII mode %d not supported\n", mode); 456 return -EINVAL; 457 } 458 459 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 460 P6_INTF_MODE(trgint)); 461 462 /* Lower Tx Driving for TRGMII path */ 463 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 464 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 465 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 466 467 /* Setup core clock for MT7530 */ 468 if (!trgint) { 469 /* Disable MT7530 core clock */ 470 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 471 472 /* Disable PLL, since phy_device has not yet been created 473 * provided for phy_[read,write]_mmd_indirect is called, we 474 * provide our own core_write_mmd_indirect to complete this 475 * function. 476 */ 477 core_write_mmd_indirect(priv, 478 CORE_GSWPLL_GRP1, 479 MDIO_MMD_VEND2, 480 0); 481 482 /* Set core clock into 500Mhz */ 483 core_write(priv, CORE_GSWPLL_GRP2, 484 RG_GSWPLL_POSDIV_500M(1) | 485 RG_GSWPLL_FBKDIV_500M(25)); 486 487 /* Enable PLL */ 488 core_write(priv, CORE_GSWPLL_GRP1, 489 RG_GSWPLL_EN_PRE | 490 RG_GSWPLL_POSDIV_200M(2) | 491 RG_GSWPLL_FBKDIV_200M(32)); 492 493 /* Enable MT7530 core clock */ 494 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 495 } 496 497 /* Setup the MT7530 TRGMII Tx Clock */ 498 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 499 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 500 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 501 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 502 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 503 core_write(priv, CORE_PLL_GROUP4, 504 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 505 RG_SYSPLL_BIAS_LPF_EN); 506 core_write(priv, CORE_PLL_GROUP2, 507 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 508 RG_SYSPLL_POSDIV(1)); 509 core_write(priv, CORE_PLL_GROUP7, 510 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 511 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 512 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 513 REG_GSWCK_EN | REG_TRGMIICK_EN); 514 515 if (!trgint) 516 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 517 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 518 RD_TAP_MASK, RD_TAP(16)); 519 else 520 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII); 521 522 return 0; 523 } 524 525 static int 526 mt7623_pad_clk_setup(struct dsa_switch *ds) 527 { 528 struct mt7530_priv *priv = ds->priv; 529 int i; 530 531 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 532 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), 533 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 534 535 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); 536 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); 537 538 return 0; 539 } 540 541 static void 542 mt7530_mib_reset(struct dsa_switch *ds) 543 { 544 struct mt7530_priv *priv = ds->priv; 545 546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 547 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 548 } 549 550 static void 551 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) 552 { 553 u32 mask = PMCR_TX_EN | PMCR_RX_EN; 554 555 if (enable) 556 mt7530_set(priv, MT7530_PMCR_P(port), mask); 557 else 558 mt7530_clear(priv, MT7530_PMCR_P(port), mask); 559 } 560 561 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 562 { 563 struct mt7530_priv *priv = ds->priv; 564 565 return mdiobus_read_nested(priv->bus, port, regnum); 566 } 567 568 int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) 569 { 570 struct mt7530_priv *priv = ds->priv; 571 572 return mdiobus_write_nested(priv->bus, port, regnum, val); 573 } 574 575 static void 576 mt7530_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 577 { 578 int i; 579 580 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 581 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 582 ETH_GSTRING_LEN); 583 } 584 585 static void 586 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 587 uint64_t *data) 588 { 589 struct mt7530_priv *priv = ds->priv; 590 const struct mt7530_mib_desc *mib; 591 u32 reg, i; 592 u64 hi; 593 594 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 595 mib = &mt7530_mib[i]; 596 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 597 598 data[i] = mt7530_read(priv, reg); 599 if (mib->size == 2) { 600 hi = mt7530_read(priv, reg + 4); 601 data[i] |= hi << 32; 602 } 603 } 604 } 605 606 static int 607 mt7530_get_sset_count(struct dsa_switch *ds) 608 { 609 return ARRAY_SIZE(mt7530_mib); 610 } 611 612 static void mt7530_adjust_link(struct dsa_switch *ds, int port, 613 struct phy_device *phydev) 614 { 615 struct mt7530_priv *priv = ds->priv; 616 617 if (phy_is_pseudo_fixed_link(phydev)) { 618 dev_dbg(priv->dev, "phy-mode for master device = %x\n", 619 phydev->interface); 620 621 /* Setup TX circuit incluing relevant PAD and driving */ 622 mt7530_pad_clk_setup(ds, phydev->interface); 623 624 /* Setup RX circuit, relevant PAD and driving on the host 625 * which must be placed after the setup on the device side is 626 * all finished. 627 */ 628 mt7623_pad_clk_setup(ds); 629 } 630 } 631 632 static int 633 mt7530_cpu_port_enable(struct mt7530_priv *priv, 634 int port) 635 { 636 /* Enable Mediatek header mode on the cpu port */ 637 mt7530_write(priv, MT7530_PVC_P(port), 638 PORT_SPEC_TAG); 639 640 /* Setup the MAC by default for the cpu port */ 641 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK); 642 643 /* Disable auto learning on the cpu port */ 644 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); 645 646 /* Unknown unicast frame fordwarding to the cpu port */ 647 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); 648 649 /* CPU port gets connected to all user ports of 650 * the switch 651 */ 652 mt7530_write(priv, MT7530_PCR_P(port), 653 PCR_MATRIX(priv->ds->enabled_port_mask)); 654 655 return 0; 656 } 657 658 static int 659 mt7530_port_enable(struct dsa_switch *ds, int port, 660 struct phy_device *phy) 661 { 662 struct mt7530_priv *priv = ds->priv; 663 664 mutex_lock(&priv->reg_mutex); 665 666 /* Setup the MAC for the user port */ 667 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK); 668 669 /* Allow the user port gets connected to the cpu port and also 670 * restore the port matrix if the port is the member of a certain 671 * bridge. 672 */ 673 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 674 priv->ports[port].enable = true; 675 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 676 priv->ports[port].pm); 677 mt7530_port_set_status(priv, port, 1); 678 679 mutex_unlock(&priv->reg_mutex); 680 681 return 0; 682 } 683 684 static void 685 mt7530_port_disable(struct dsa_switch *ds, int port, 686 struct phy_device *phy) 687 { 688 struct mt7530_priv *priv = ds->priv; 689 690 mutex_lock(&priv->reg_mutex); 691 692 /* Clear up all port matrix which could be restored in the next 693 * enablement for the port. 694 */ 695 priv->ports[port].enable = false; 696 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 697 PCR_MATRIX_CLR); 698 mt7530_port_set_status(priv, port, 0); 699 700 mutex_unlock(&priv->reg_mutex); 701 } 702 703 static void 704 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 705 { 706 struct mt7530_priv *priv = ds->priv; 707 u32 stp_state; 708 709 switch (state) { 710 case BR_STATE_DISABLED: 711 stp_state = MT7530_STP_DISABLED; 712 break; 713 case BR_STATE_BLOCKING: 714 stp_state = MT7530_STP_BLOCKING; 715 break; 716 case BR_STATE_LISTENING: 717 stp_state = MT7530_STP_LISTENING; 718 break; 719 case BR_STATE_LEARNING: 720 stp_state = MT7530_STP_LEARNING; 721 break; 722 case BR_STATE_FORWARDING: 723 default: 724 stp_state = MT7530_STP_FORWARDING; 725 break; 726 } 727 728 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 729 } 730 731 static int 732 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 733 struct net_device *bridge) 734 { 735 struct mt7530_priv *priv = ds->priv; 736 u32 port_bitmap = BIT(MT7530_CPU_PORT); 737 int i; 738 739 mutex_lock(&priv->reg_mutex); 740 741 for (i = 0; i < MT7530_NUM_PORTS; i++) { 742 /* Add this port to the port matrix of the other ports in the 743 * same bridge. If the port is disabled, port matrix is kept 744 * and not being setup until the port becomes enabled. 745 */ 746 if (ds->enabled_port_mask & BIT(i) && i != port) { 747 if (ds->ports[i].bridge_dev != bridge) 748 continue; 749 if (priv->ports[i].enable) 750 mt7530_set(priv, MT7530_PCR_P(i), 751 PCR_MATRIX(BIT(port))); 752 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 753 754 port_bitmap |= BIT(i); 755 } 756 } 757 758 /* Add the all other ports to this port matrix. */ 759 if (priv->ports[port].enable) 760 mt7530_rmw(priv, MT7530_PCR_P(port), 761 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 762 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 763 764 mutex_unlock(&priv->reg_mutex); 765 766 return 0; 767 } 768 769 static void 770 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 771 struct net_device *bridge) 772 { 773 struct mt7530_priv *priv = ds->priv; 774 int i; 775 776 mutex_lock(&priv->reg_mutex); 777 778 for (i = 0; i < MT7530_NUM_PORTS; i++) { 779 /* Remove this port from the port matrix of the other ports 780 * in the same bridge. If the port is disabled, port matrix 781 * is kept and not being setup until the port becomes enabled. 782 */ 783 if (ds->enabled_port_mask & BIT(i) && i != port) { 784 if (ds->ports[i].bridge_dev != bridge) 785 continue; 786 if (priv->ports[i].enable) 787 mt7530_clear(priv, MT7530_PCR_P(i), 788 PCR_MATRIX(BIT(port))); 789 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 790 } 791 } 792 793 /* Set the cpu port to be the only one in the port matrix of 794 * this port. 795 */ 796 if (priv->ports[port].enable) 797 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 798 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 799 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 800 801 mutex_unlock(&priv->reg_mutex); 802 } 803 804 static int 805 mt7530_port_fdb_prepare(struct dsa_switch *ds, int port, 806 const struct switchdev_obj_port_fdb *fdb, 807 struct switchdev_trans *trans) 808 { 809 struct mt7530_priv *priv = ds->priv; 810 int ret; 811 812 /* Because auto-learned entrie shares the same FDB table. 813 * an entry is reserved with no port_mask to make sure fdb_add 814 * is called while the entry is still available. 815 */ 816 mutex_lock(&priv->reg_mutex); 817 mt7530_fdb_write(priv, fdb->vid, 0, fdb->addr, -1, STATIC_ENT); 818 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); 819 mutex_unlock(&priv->reg_mutex); 820 821 return ret; 822 } 823 824 static void 825 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 826 const struct switchdev_obj_port_fdb *fdb, 827 struct switchdev_trans *trans) 828 { 829 struct mt7530_priv *priv = ds->priv; 830 u8 port_mask = BIT(port); 831 832 mutex_lock(&priv->reg_mutex); 833 mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_ENT); 834 mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); 835 mutex_unlock(&priv->reg_mutex); 836 } 837 838 static int 839 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 840 const struct switchdev_obj_port_fdb *fdb) 841 { 842 struct mt7530_priv *priv = ds->priv; 843 int ret; 844 u8 port_mask = BIT(port); 845 846 mutex_lock(&priv->reg_mutex); 847 mt7530_fdb_write(priv, fdb->vid, port_mask, fdb->addr, -1, STATIC_EMP); 848 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); 849 mutex_unlock(&priv->reg_mutex); 850 851 return ret; 852 } 853 854 static int 855 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 856 struct switchdev_obj_port_fdb *fdb, 857 int (*cb)(struct switchdev_obj *obj)) 858 { 859 struct mt7530_priv *priv = ds->priv; 860 struct mt7530_fdb _fdb = { 0 }; 861 int cnt = MT7530_NUM_FDB_RECORDS; 862 int ret = 0; 863 u32 rsp = 0; 864 865 mutex_lock(&priv->reg_mutex); 866 867 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 868 if (ret < 0) 869 goto err; 870 871 do { 872 if (rsp & ATC_SRCH_HIT) { 873 mt7530_fdb_read(priv, &_fdb); 874 if (_fdb.port_mask & BIT(port)) { 875 ether_addr_copy(fdb->addr, _fdb.mac); 876 fdb->vid = _fdb.vid; 877 fdb->ndm_state = _fdb.noarp ? 878 NUD_NOARP : NUD_REACHABLE; 879 ret = cb(&fdb->obj); 880 if (ret < 0) 881 break; 882 } 883 } 884 } while (--cnt && 885 !(rsp & ATC_SRCH_END) && 886 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 887 err: 888 mutex_unlock(&priv->reg_mutex); 889 890 return 0; 891 } 892 893 static enum dsa_tag_protocol 894 mtk_get_tag_protocol(struct dsa_switch *ds) 895 { 896 struct mt7530_priv *priv = ds->priv; 897 898 if (!dsa_is_cpu_port(ds, MT7530_CPU_PORT)) { 899 dev_warn(priv->dev, 900 "port not matched with tagging CPU port\n"); 901 return DSA_TAG_PROTO_NONE; 902 } else { 903 return DSA_TAG_PROTO_MTK; 904 } 905 } 906 907 static int 908 mt7530_setup(struct dsa_switch *ds) 909 { 910 struct mt7530_priv *priv = ds->priv; 911 int ret, i; 912 u32 id, val; 913 struct device_node *dn; 914 struct mt7530_dummy_poll p; 915 916 /* The parent node of master_netdev which holds the common system 917 * controller also is the container for two GMACs nodes representing 918 * as two netdev instances. 919 */ 920 dn = ds->master_netdev->dev.of_node->parent; 921 priv->ethernet = syscon_node_to_regmap(dn); 922 if (IS_ERR(priv->ethernet)) 923 return PTR_ERR(priv->ethernet); 924 925 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 926 ret = regulator_enable(priv->core_pwr); 927 if (ret < 0) { 928 dev_err(priv->dev, 929 "Failed to enable core power: %d\n", ret); 930 return ret; 931 } 932 933 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 934 ret = regulator_enable(priv->io_pwr); 935 if (ret < 0) { 936 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 937 ret); 938 return ret; 939 } 940 941 /* Reset whole chip through gpio pin or memory-mapped registers for 942 * different type of hardware 943 */ 944 if (priv->mcm) { 945 reset_control_assert(priv->rstc); 946 usleep_range(1000, 1100); 947 reset_control_deassert(priv->rstc); 948 } else { 949 gpiod_set_value_cansleep(priv->reset, 0); 950 usleep_range(1000, 1100); 951 gpiod_set_value_cansleep(priv->reset, 1); 952 } 953 954 /* Waiting for MT7530 got to stable */ 955 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 956 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 957 20, 1000000); 958 if (ret < 0) { 959 dev_err(priv->dev, "reset timeout\n"); 960 return ret; 961 } 962 963 id = mt7530_read(priv, MT7530_CREV); 964 id >>= CHIP_NAME_SHIFT; 965 if (id != MT7530_ID) { 966 dev_err(priv->dev, "chip %x can't be supported\n", id); 967 return -ENODEV; 968 } 969 970 /* Reset the switch through internal reset */ 971 mt7530_write(priv, MT7530_SYS_CTRL, 972 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 973 SYS_CTRL_REG_RST); 974 975 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 976 val = mt7530_read(priv, MT7530_MHWTRAP); 977 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 978 val |= MHWTRAP_MANUAL; 979 mt7530_write(priv, MT7530_MHWTRAP, val); 980 981 /* Enable and reset MIB counters */ 982 mt7530_mib_reset(ds); 983 984 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); 985 986 for (i = 0; i < MT7530_NUM_PORTS; i++) { 987 /* Disable forwarding by default on all ports */ 988 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 989 PCR_MATRIX_CLR); 990 991 if (dsa_is_cpu_port(ds, i)) 992 mt7530_cpu_port_enable(priv, i); 993 else 994 mt7530_port_disable(ds, i, NULL); 995 } 996 997 /* Flush the FDB table */ 998 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, 0); 999 if (ret < 0) 1000 return ret; 1001 1002 return 0; 1003 } 1004 1005 static struct dsa_switch_ops mt7530_switch_ops = { 1006 .get_tag_protocol = mtk_get_tag_protocol, 1007 .setup = mt7530_setup, 1008 .get_strings = mt7530_get_strings, 1009 .phy_read = mt7530_phy_read, 1010 .phy_write = mt7530_phy_write, 1011 .get_ethtool_stats = mt7530_get_ethtool_stats, 1012 .get_sset_count = mt7530_get_sset_count, 1013 .adjust_link = mt7530_adjust_link, 1014 .port_enable = mt7530_port_enable, 1015 .port_disable = mt7530_port_disable, 1016 .port_stp_state_set = mt7530_stp_state_set, 1017 .port_bridge_join = mt7530_port_bridge_join, 1018 .port_bridge_leave = mt7530_port_bridge_leave, 1019 .port_fdb_prepare = mt7530_port_fdb_prepare, 1020 .port_fdb_add = mt7530_port_fdb_add, 1021 .port_fdb_del = mt7530_port_fdb_del, 1022 .port_fdb_dump = mt7530_port_fdb_dump, 1023 }; 1024 1025 static int 1026 mt7530_probe(struct mdio_device *mdiodev) 1027 { 1028 struct mt7530_priv *priv; 1029 struct device_node *dn; 1030 1031 dn = mdiodev->dev.of_node; 1032 1033 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1034 if (!priv) 1035 return -ENOMEM; 1036 1037 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS); 1038 if (!priv->ds) 1039 return -ENOMEM; 1040 1041 /* Use medatek,mcm property to distinguish hardware type that would 1042 * casues a little bit differences on power-on sequence. 1043 */ 1044 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 1045 if (priv->mcm) { 1046 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 1047 1048 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 1049 if (IS_ERR(priv->rstc)) { 1050 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1051 return PTR_ERR(priv->rstc); 1052 } 1053 } 1054 1055 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 1056 if (IS_ERR(priv->core_pwr)) 1057 return PTR_ERR(priv->core_pwr); 1058 1059 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 1060 if (IS_ERR(priv->io_pwr)) 1061 return PTR_ERR(priv->io_pwr); 1062 1063 /* Not MCM that indicates switch works as the remote standalone 1064 * integrated circuit so the GPIO pin would be used to complete 1065 * the reset, otherwise memory-mapped register accessing used 1066 * through syscon provides in the case of MCM. 1067 */ 1068 if (!priv->mcm) { 1069 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 1070 GPIOD_OUT_LOW); 1071 if (IS_ERR(priv->reset)) { 1072 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1073 return PTR_ERR(priv->reset); 1074 } 1075 } 1076 1077 priv->bus = mdiodev->bus; 1078 priv->dev = &mdiodev->dev; 1079 priv->ds->priv = priv; 1080 priv->ds->ops = &mt7530_switch_ops; 1081 mutex_init(&priv->reg_mutex); 1082 dev_set_drvdata(&mdiodev->dev, priv); 1083 1084 return dsa_register_switch(priv->ds, &mdiodev->dev); 1085 } 1086 1087 static void 1088 mt7530_remove(struct mdio_device *mdiodev) 1089 { 1090 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 1091 int ret = 0; 1092 1093 ret = regulator_disable(priv->core_pwr); 1094 if (ret < 0) 1095 dev_err(priv->dev, 1096 "Failed to disable core power: %d\n", ret); 1097 1098 ret = regulator_disable(priv->io_pwr); 1099 if (ret < 0) 1100 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 1101 ret); 1102 1103 dsa_unregister_switch(priv->ds); 1104 mutex_destroy(&priv->reg_mutex); 1105 } 1106 1107 static const struct of_device_id mt7530_of_match[] = { 1108 { .compatible = "mediatek,mt7530" }, 1109 { /* sentinel */ }, 1110 }; 1111 1112 static struct mdio_driver mt7530_mdio_driver = { 1113 .probe = mt7530_probe, 1114 .remove = mt7530_remove, 1115 .mdiodrv.driver = { 1116 .name = "mt7530", 1117 .of_match_table = mt7530_of_match, 1118 }, 1119 }; 1120 1121 mdio_module_driver(mt7530_mdio_driver); 1122 1123 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1124 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 1125 MODULE_LICENSE("GPL"); 1126 MODULE_ALIAS("platform:mediatek-mt7530"); 1127