1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 /* String, offset, and register size in bytes if different from 4 bytes */ 28 static const struct mt7530_mib_desc mt7530_mib[] = { 29 MIB_DESC(1, 0x00, "TxDrop"), 30 MIB_DESC(1, 0x04, "TxCrcErr"), 31 MIB_DESC(1, 0x08, "TxUnicast"), 32 MIB_DESC(1, 0x0c, "TxMulticast"), 33 MIB_DESC(1, 0x10, "TxBroadcast"), 34 MIB_DESC(1, 0x14, "TxCollision"), 35 MIB_DESC(1, 0x18, "TxSingleCollision"), 36 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 37 MIB_DESC(1, 0x20, "TxDeferred"), 38 MIB_DESC(1, 0x24, "TxLateCollision"), 39 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 40 MIB_DESC(1, 0x2c, "TxPause"), 41 MIB_DESC(1, 0x30, "TxPktSz64"), 42 MIB_DESC(1, 0x34, "TxPktSz65To127"), 43 MIB_DESC(1, 0x38, "TxPktSz128To255"), 44 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 45 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 46 MIB_DESC(1, 0x44, "Tx1024ToMax"), 47 MIB_DESC(2, 0x48, "TxBytes"), 48 MIB_DESC(1, 0x60, "RxDrop"), 49 MIB_DESC(1, 0x64, "RxFiltering"), 50 MIB_DESC(1, 0x6c, "RxMulticast"), 51 MIB_DESC(1, 0x70, "RxBroadcast"), 52 MIB_DESC(1, 0x74, "RxAlignErr"), 53 MIB_DESC(1, 0x78, "RxCrcErr"), 54 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 55 MIB_DESC(1, 0x80, "RxFragErr"), 56 MIB_DESC(1, 0x84, "RxOverSzErr"), 57 MIB_DESC(1, 0x88, "RxJabberErr"), 58 MIB_DESC(1, 0x8c, "RxPause"), 59 MIB_DESC(1, 0x90, "RxPktSz64"), 60 MIB_DESC(1, 0x94, "RxPktSz65To127"), 61 MIB_DESC(1, 0x98, "RxPktSz128To255"), 62 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 63 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 64 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 65 MIB_DESC(2, 0xa8, "RxBytes"), 66 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 67 MIB_DESC(1, 0xb4, "RxIngressDrop"), 68 MIB_DESC(1, 0xb8, "RxArlDrop"), 69 }; 70 71 /* Since phy_device has not yet been created and 72 * phy_{read,write}_mmd_indirect is not available, we provide our own 73 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 74 * to complete this function. 75 */ 76 static int 77 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 78 { 79 struct mii_bus *bus = priv->bus; 80 int value, ret; 81 82 /* Write the desired MMD Devad */ 83 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 84 if (ret < 0) 85 goto err; 86 87 /* Write the desired MMD register address */ 88 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 89 if (ret < 0) 90 goto err; 91 92 /* Select the Function : DATA with no post increment */ 93 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 94 if (ret < 0) 95 goto err; 96 97 /* Read the content of the MMD's selected register */ 98 value = bus->read(bus, 0, MII_MMD_DATA); 99 100 return value; 101 err: 102 dev_err(&bus->dev, "failed to read mmd register\n"); 103 104 return ret; 105 } 106 107 static int 108 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 109 int devad, u32 data) 110 { 111 struct mii_bus *bus = priv->bus; 112 int ret; 113 114 /* Write the desired MMD Devad */ 115 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 116 if (ret < 0) 117 goto err; 118 119 /* Write the desired MMD register address */ 120 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 121 if (ret < 0) 122 goto err; 123 124 /* Select the Function : DATA with no post increment */ 125 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 126 if (ret < 0) 127 goto err; 128 129 /* Write the data into MMD's selected register */ 130 ret = bus->write(bus, 0, MII_MMD_DATA, data); 131 err: 132 if (ret < 0) 133 dev_err(&bus->dev, 134 "failed to write mmd register\n"); 135 return ret; 136 } 137 138 static void 139 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 140 { 141 struct mii_bus *bus = priv->bus; 142 143 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 144 145 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 146 147 mutex_unlock(&bus->mdio_lock); 148 } 149 150 static void 151 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 152 { 153 struct mii_bus *bus = priv->bus; 154 u32 val; 155 156 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 157 158 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 159 val &= ~mask; 160 val |= set; 161 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 162 163 mutex_unlock(&bus->mdio_lock); 164 } 165 166 static void 167 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 168 { 169 core_rmw(priv, reg, 0, val); 170 } 171 172 static void 173 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 core_rmw(priv, reg, val, 0); 176 } 177 178 static int 179 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 180 { 181 struct mii_bus *bus = priv->bus; 182 u16 page, r, lo, hi; 183 int ret; 184 185 page = (reg >> 6) & 0x3ff; 186 r = (reg >> 2) & 0xf; 187 lo = val & 0xffff; 188 hi = val >> 16; 189 190 /* MT7530 uses 31 as the pseudo port */ 191 ret = bus->write(bus, 0x1f, 0x1f, page); 192 if (ret < 0) 193 goto err; 194 195 ret = bus->write(bus, 0x1f, r, lo); 196 if (ret < 0) 197 goto err; 198 199 ret = bus->write(bus, 0x1f, 0x10, hi); 200 err: 201 if (ret < 0) 202 dev_err(&bus->dev, 203 "failed to write mt7530 register\n"); 204 return ret; 205 } 206 207 static u32 208 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 209 { 210 struct mii_bus *bus = priv->bus; 211 u16 page, r, lo, hi; 212 int ret; 213 214 page = (reg >> 6) & 0x3ff; 215 r = (reg >> 2) & 0xf; 216 217 /* MT7530 uses 31 as the pseudo port */ 218 ret = bus->write(bus, 0x1f, 0x1f, page); 219 if (ret < 0) { 220 dev_err(&bus->dev, 221 "failed to read mt7530 register\n"); 222 return ret; 223 } 224 225 lo = bus->read(bus, 0x1f, r); 226 hi = bus->read(bus, 0x1f, 0x10); 227 228 return (hi << 16) | (lo & 0xffff); 229 } 230 231 static void 232 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 233 { 234 struct mii_bus *bus = priv->bus; 235 236 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 237 238 mt7530_mii_write(priv, reg, val); 239 240 mutex_unlock(&bus->mdio_lock); 241 } 242 243 static u32 244 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 245 { 246 return mt7530_mii_read(p->priv, p->reg); 247 } 248 249 static u32 250 _mt7530_read(struct mt7530_dummy_poll *p) 251 { 252 struct mii_bus *bus = p->priv->bus; 253 u32 val; 254 255 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 256 257 val = mt7530_mii_read(p->priv, p->reg); 258 259 mutex_unlock(&bus->mdio_lock); 260 261 return val; 262 } 263 264 static u32 265 mt7530_read(struct mt7530_priv *priv, u32 reg) 266 { 267 struct mt7530_dummy_poll p; 268 269 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 270 return _mt7530_read(&p); 271 } 272 273 static void 274 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 275 u32 mask, u32 set) 276 { 277 struct mii_bus *bus = priv->bus; 278 u32 val; 279 280 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 281 282 val = mt7530_mii_read(priv, reg); 283 val &= ~mask; 284 val |= set; 285 mt7530_mii_write(priv, reg, val); 286 287 mutex_unlock(&bus->mdio_lock); 288 } 289 290 static void 291 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 292 { 293 mt7530_rmw(priv, reg, 0, val); 294 } 295 296 static void 297 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 298 { 299 mt7530_rmw(priv, reg, val, 0); 300 } 301 302 static int 303 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 304 { 305 u32 val; 306 int ret; 307 struct mt7530_dummy_poll p; 308 309 /* Set the command operating upon the MAC address entries */ 310 val = ATC_BUSY | ATC_MAT(0) | cmd; 311 mt7530_write(priv, MT7530_ATC, val); 312 313 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 314 ret = readx_poll_timeout(_mt7530_read, &p, val, 315 !(val & ATC_BUSY), 20, 20000); 316 if (ret < 0) { 317 dev_err(priv->dev, "reset timeout\n"); 318 return ret; 319 } 320 321 /* Additional sanity for read command if the specified 322 * entry is invalid 323 */ 324 val = mt7530_read(priv, MT7530_ATC); 325 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 326 return -EINVAL; 327 328 if (rsp) 329 *rsp = val; 330 331 return 0; 332 } 333 334 static void 335 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 336 { 337 u32 reg[3]; 338 int i; 339 340 /* Read from ARL table into an array */ 341 for (i = 0; i < 3; i++) { 342 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 343 344 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 345 __func__, __LINE__, i, reg[i]); 346 } 347 348 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 349 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 350 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 351 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 352 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 353 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 354 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 355 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 356 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 357 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 358 } 359 360 static void 361 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 362 u8 port_mask, const u8 *mac, 363 u8 aging, u8 type) 364 { 365 u32 reg[3] = { 0 }; 366 int i; 367 368 reg[1] |= vid & CVID_MASK; 369 reg[1] |= ATA2_IVL; 370 reg[1] |= ATA2_FID(FID_BRIDGED); 371 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 372 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 373 /* STATIC_ENT indicate that entry is static wouldn't 374 * be aged out and STATIC_EMP specified as erasing an 375 * entry 376 */ 377 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 378 reg[1] |= mac[5] << MAC_BYTE_5; 379 reg[1] |= mac[4] << MAC_BYTE_4; 380 reg[0] |= mac[3] << MAC_BYTE_3; 381 reg[0] |= mac[2] << MAC_BYTE_2; 382 reg[0] |= mac[1] << MAC_BYTE_1; 383 reg[0] |= mac[0] << MAC_BYTE_0; 384 385 /* Write array into the ARL table */ 386 for (i = 0; i < 3; i++) 387 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 388 } 389 390 /* Setup TX circuit including relevant PAD and driving */ 391 static int 392 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 393 { 394 struct mt7530_priv *priv = ds->priv; 395 u32 ncpo1, ssc_delta, trgint, i, xtal; 396 397 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 398 399 if (xtal == HWTRAP_XTAL_20MHZ) { 400 dev_err(priv->dev, 401 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 402 __func__); 403 return -EINVAL; 404 } 405 406 switch (interface) { 407 case PHY_INTERFACE_MODE_RGMII: 408 trgint = 0; 409 /* PLL frequency: 125MHz */ 410 ncpo1 = 0x0c80; 411 break; 412 case PHY_INTERFACE_MODE_TRGMII: 413 trgint = 1; 414 if (priv->id == ID_MT7621) { 415 /* PLL frequency: 150MHz: 1.2GBit */ 416 if (xtal == HWTRAP_XTAL_40MHZ) 417 ncpo1 = 0x0780; 418 if (xtal == HWTRAP_XTAL_25MHZ) 419 ncpo1 = 0x0a00; 420 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 421 if (xtal == HWTRAP_XTAL_40MHZ) 422 ncpo1 = 0x0c80; 423 if (xtal == HWTRAP_XTAL_25MHZ) 424 ncpo1 = 0x1400; 425 } 426 break; 427 default: 428 dev_err(priv->dev, "xMII interface %d not supported\n", 429 interface); 430 return -EINVAL; 431 } 432 433 if (xtal == HWTRAP_XTAL_25MHZ) 434 ssc_delta = 0x57; 435 else 436 ssc_delta = 0x87; 437 438 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 439 P6_INTF_MODE(trgint)); 440 441 /* Lower Tx Driving for TRGMII path */ 442 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 443 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 444 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 445 446 /* Disable MT7530 core and TRGMII Tx clocks */ 447 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, 448 REG_GSWCK_EN | REG_TRGMIICK_EN); 449 450 /* Setup core clock for MT7530 */ 451 /* Disable PLL */ 452 core_write(priv, CORE_GSWPLL_GRP1, 0); 453 454 /* Set core clock into 500Mhz */ 455 core_write(priv, CORE_GSWPLL_GRP2, 456 RG_GSWPLL_POSDIV_500M(1) | 457 RG_GSWPLL_FBKDIV_500M(25)); 458 459 /* Enable PLL */ 460 core_write(priv, CORE_GSWPLL_GRP1, 461 RG_GSWPLL_EN_PRE | 462 RG_GSWPLL_POSDIV_200M(2) | 463 RG_GSWPLL_FBKDIV_200M(32)); 464 465 /* Setup the MT7530 TRGMII Tx Clock */ 466 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 467 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 468 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 469 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 470 core_write(priv, CORE_PLL_GROUP4, 471 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 472 RG_SYSPLL_BIAS_LPF_EN); 473 core_write(priv, CORE_PLL_GROUP2, 474 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 475 RG_SYSPLL_POSDIV(1)); 476 core_write(priv, CORE_PLL_GROUP7, 477 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 478 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 479 480 /* Enable MT7530 core and TRGMII Tx clocks */ 481 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 482 REG_GSWCK_EN | REG_TRGMIICK_EN); 483 484 if (!trgint) 485 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 486 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 487 RD_TAP_MASK, RD_TAP(16)); 488 return 0; 489 } 490 491 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 492 { 493 u32 val; 494 495 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 496 497 return (val & PAD_DUAL_SGMII_EN) != 0; 498 } 499 500 static int 501 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 502 { 503 struct mt7530_priv *priv = ds->priv; 504 u32 top_sig; 505 u32 hwstrap; 506 u32 xtal; 507 u32 val; 508 509 if (mt7531_dual_sgmii_supported(priv)) 510 return 0; 511 512 val = mt7530_read(priv, MT7531_CREV); 513 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 514 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 515 if ((val & CHIP_REV_M) > 0) 516 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 517 HWTRAP_XTAL_FSEL_25MHZ; 518 else 519 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 520 521 /* Step 1 : Disable MT7531 COREPLL */ 522 val = mt7530_read(priv, MT7531_PLLGP_EN); 523 val &= ~EN_COREPLL; 524 mt7530_write(priv, MT7531_PLLGP_EN, val); 525 526 /* Step 2: switch to XTAL output */ 527 val = mt7530_read(priv, MT7531_PLLGP_EN); 528 val |= SW_CLKSW; 529 mt7530_write(priv, MT7531_PLLGP_EN, val); 530 531 val = mt7530_read(priv, MT7531_PLLGP_CR0); 532 val &= ~RG_COREPLL_EN; 533 mt7530_write(priv, MT7531_PLLGP_CR0, val); 534 535 /* Step 3: disable PLLGP and enable program PLLGP */ 536 val = mt7530_read(priv, MT7531_PLLGP_EN); 537 val |= SW_PLLGP; 538 mt7530_write(priv, MT7531_PLLGP_EN, val); 539 540 /* Step 4: program COREPLL output frequency to 500MHz */ 541 val = mt7530_read(priv, MT7531_PLLGP_CR0); 542 val &= ~RG_COREPLL_POSDIV_M; 543 val |= 2 << RG_COREPLL_POSDIV_S; 544 mt7530_write(priv, MT7531_PLLGP_CR0, val); 545 usleep_range(25, 35); 546 547 switch (xtal) { 548 case HWTRAP_XTAL_FSEL_25MHZ: 549 val = mt7530_read(priv, MT7531_PLLGP_CR0); 550 val &= ~RG_COREPLL_SDM_PCW_M; 551 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 552 mt7530_write(priv, MT7531_PLLGP_CR0, val); 553 break; 554 case HWTRAP_XTAL_FSEL_40MHZ: 555 val = mt7530_read(priv, MT7531_PLLGP_CR0); 556 val &= ~RG_COREPLL_SDM_PCW_M; 557 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 558 mt7530_write(priv, MT7531_PLLGP_CR0, val); 559 break; 560 } 561 562 /* Set feedback divide ratio update signal to high */ 563 val = mt7530_read(priv, MT7531_PLLGP_CR0); 564 val |= RG_COREPLL_SDM_PCW_CHG; 565 mt7530_write(priv, MT7531_PLLGP_CR0, val); 566 /* Wait for at least 16 XTAL clocks */ 567 usleep_range(10, 20); 568 569 /* Step 5: set feedback divide ratio update signal to low */ 570 val = mt7530_read(priv, MT7531_PLLGP_CR0); 571 val &= ~RG_COREPLL_SDM_PCW_CHG; 572 mt7530_write(priv, MT7531_PLLGP_CR0, val); 573 574 /* Enable 325M clock for SGMII */ 575 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 576 577 /* Enable 250SSC clock for RGMII */ 578 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 579 580 /* Step 6: Enable MT7531 PLL */ 581 val = mt7530_read(priv, MT7531_PLLGP_CR0); 582 val |= RG_COREPLL_EN; 583 mt7530_write(priv, MT7531_PLLGP_CR0, val); 584 585 val = mt7530_read(priv, MT7531_PLLGP_EN); 586 val |= EN_COREPLL; 587 mt7530_write(priv, MT7531_PLLGP_EN, val); 588 usleep_range(25, 35); 589 590 return 0; 591 } 592 593 static void 594 mt7530_mib_reset(struct dsa_switch *ds) 595 { 596 struct mt7530_priv *priv = ds->priv; 597 598 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 600 } 601 602 static int mt7530_phy_read(struct mt7530_priv *priv, int port, int regnum) 603 { 604 return mdiobus_read_nested(priv->bus, port, regnum); 605 } 606 607 static int mt7530_phy_write(struct mt7530_priv *priv, int port, int regnum, 608 u16 val) 609 { 610 return mdiobus_write_nested(priv->bus, port, regnum, val); 611 } 612 613 static int 614 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 615 int regnum) 616 { 617 struct mii_bus *bus = priv->bus; 618 struct mt7530_dummy_poll p; 619 u32 reg, val; 620 int ret; 621 622 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 623 624 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 625 626 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 627 !(val & MT7531_PHY_ACS_ST), 20, 100000); 628 if (ret < 0) { 629 dev_err(priv->dev, "poll timeout\n"); 630 goto out; 631 } 632 633 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 634 MT7531_MDIO_DEV_ADDR(devad) | regnum; 635 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 636 637 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 638 !(val & MT7531_PHY_ACS_ST), 20, 100000); 639 if (ret < 0) { 640 dev_err(priv->dev, "poll timeout\n"); 641 goto out; 642 } 643 644 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 645 MT7531_MDIO_DEV_ADDR(devad); 646 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 647 648 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 649 !(val & MT7531_PHY_ACS_ST), 20, 100000); 650 if (ret < 0) { 651 dev_err(priv->dev, "poll timeout\n"); 652 goto out; 653 } 654 655 ret = val & MT7531_MDIO_RW_DATA_MASK; 656 out: 657 mutex_unlock(&bus->mdio_lock); 658 659 return ret; 660 } 661 662 static int 663 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 664 int regnum, u32 data) 665 { 666 struct mii_bus *bus = priv->bus; 667 struct mt7530_dummy_poll p; 668 u32 val, reg; 669 int ret; 670 671 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 672 673 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 674 675 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 676 !(val & MT7531_PHY_ACS_ST), 20, 100000); 677 if (ret < 0) { 678 dev_err(priv->dev, "poll timeout\n"); 679 goto out; 680 } 681 682 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 683 MT7531_MDIO_DEV_ADDR(devad) | regnum; 684 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 685 686 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 687 !(val & MT7531_PHY_ACS_ST), 20, 100000); 688 if (ret < 0) { 689 dev_err(priv->dev, "poll timeout\n"); 690 goto out; 691 } 692 693 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 694 MT7531_MDIO_DEV_ADDR(devad) | data; 695 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 696 697 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 698 !(val & MT7531_PHY_ACS_ST), 20, 100000); 699 if (ret < 0) { 700 dev_err(priv->dev, "poll timeout\n"); 701 goto out; 702 } 703 704 out: 705 mutex_unlock(&bus->mdio_lock); 706 707 return ret; 708 } 709 710 static int 711 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 712 { 713 struct mii_bus *bus = priv->bus; 714 struct mt7530_dummy_poll p; 715 int ret; 716 u32 val; 717 718 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 719 720 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 721 722 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 723 !(val & MT7531_PHY_ACS_ST), 20, 100000); 724 if (ret < 0) { 725 dev_err(priv->dev, "poll timeout\n"); 726 goto out; 727 } 728 729 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 730 MT7531_MDIO_REG_ADDR(regnum); 731 732 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 733 734 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 735 !(val & MT7531_PHY_ACS_ST), 20, 100000); 736 if (ret < 0) { 737 dev_err(priv->dev, "poll timeout\n"); 738 goto out; 739 } 740 741 ret = val & MT7531_MDIO_RW_DATA_MASK; 742 out: 743 mutex_unlock(&bus->mdio_lock); 744 745 return ret; 746 } 747 748 static int 749 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 750 u16 data) 751 { 752 struct mii_bus *bus = priv->bus; 753 struct mt7530_dummy_poll p; 754 int ret; 755 u32 reg; 756 757 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 758 759 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 760 761 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 762 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 763 if (ret < 0) { 764 dev_err(priv->dev, "poll timeout\n"); 765 goto out; 766 } 767 768 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 769 MT7531_MDIO_REG_ADDR(regnum) | data; 770 771 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 772 773 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 774 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 775 if (ret < 0) { 776 dev_err(priv->dev, "poll timeout\n"); 777 goto out; 778 } 779 780 out: 781 mutex_unlock(&bus->mdio_lock); 782 783 return ret; 784 } 785 786 static int 787 mt7531_ind_phy_read(struct mt7530_priv *priv, int port, int regnum) 788 { 789 int devad; 790 int ret; 791 792 if (regnum & MII_ADDR_C45) { 793 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 794 ret = mt7531_ind_c45_phy_read(priv, port, devad, 795 regnum & MII_REGADDR_C45_MASK); 796 } else { 797 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 798 } 799 800 return ret; 801 } 802 803 static int 804 mt7531_ind_phy_write(struct mt7530_priv *priv, int port, int regnum, 805 u16 data) 806 { 807 int devad; 808 int ret; 809 810 if (regnum & MII_ADDR_C45) { 811 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 812 ret = mt7531_ind_c45_phy_write(priv, port, devad, 813 regnum & MII_REGADDR_C45_MASK, 814 data); 815 } else { 816 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 817 } 818 819 return ret; 820 } 821 822 static int 823 mt753x_phy_read(struct mii_bus *bus, int port, int regnum) 824 { 825 struct mt7530_priv *priv = bus->priv; 826 827 return priv->info->phy_read(priv, port, regnum); 828 } 829 830 static int 831 mt753x_phy_write(struct mii_bus *bus, int port, int regnum, u16 val) 832 { 833 struct mt7530_priv *priv = bus->priv; 834 835 return priv->info->phy_write(priv, port, regnum, val); 836 } 837 838 static void 839 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 840 uint8_t *data) 841 { 842 int i; 843 844 if (stringset != ETH_SS_STATS) 845 return; 846 847 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 848 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 849 ETH_GSTRING_LEN); 850 } 851 852 static void 853 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 854 uint64_t *data) 855 { 856 struct mt7530_priv *priv = ds->priv; 857 const struct mt7530_mib_desc *mib; 858 u32 reg, i; 859 u64 hi; 860 861 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 862 mib = &mt7530_mib[i]; 863 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 864 865 data[i] = mt7530_read(priv, reg); 866 if (mib->size == 2) { 867 hi = mt7530_read(priv, reg + 4); 868 data[i] |= hi << 32; 869 } 870 } 871 } 872 873 static int 874 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 875 { 876 if (sset != ETH_SS_STATS) 877 return 0; 878 879 return ARRAY_SIZE(mt7530_mib); 880 } 881 882 static int 883 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 884 { 885 struct mt7530_priv *priv = ds->priv; 886 unsigned int secs = msecs / 1000; 887 unsigned int tmp_age_count; 888 unsigned int error = -1; 889 unsigned int age_count; 890 unsigned int age_unit; 891 892 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 893 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 894 return -ERANGE; 895 896 /* iterate through all possible age_count to find the closest pair */ 897 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 898 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 899 900 if (tmp_age_unit <= AGE_UNIT_MAX) { 901 unsigned int tmp_error = secs - 902 (tmp_age_count + 1) * (tmp_age_unit + 1); 903 904 /* found a closer pair */ 905 if (error > tmp_error) { 906 error = tmp_error; 907 age_count = tmp_age_count; 908 age_unit = tmp_age_unit; 909 } 910 911 /* found the exact match, so break the loop */ 912 if (!error) 913 break; 914 } 915 } 916 917 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 918 919 return 0; 920 } 921 922 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 923 { 924 struct mt7530_priv *priv = ds->priv; 925 u8 tx_delay = 0; 926 int val; 927 928 mutex_lock(&priv->reg_mutex); 929 930 val = mt7530_read(priv, MT7530_MHWTRAP); 931 932 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 933 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 934 935 switch (priv->p5_intf_sel) { 936 case P5_INTF_SEL_PHY_P0: 937 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 938 val |= MHWTRAP_PHY0_SEL; 939 fallthrough; 940 case P5_INTF_SEL_PHY_P4: 941 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 942 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 943 944 /* Setup the MAC by default for the cpu port */ 945 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 946 break; 947 case P5_INTF_SEL_GMAC5: 948 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 949 val &= ~MHWTRAP_P5_DIS; 950 break; 951 case P5_DISABLED: 952 interface = PHY_INTERFACE_MODE_NA; 953 break; 954 default: 955 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 956 priv->p5_intf_sel); 957 goto unlock_exit; 958 } 959 960 /* Setup RGMII settings */ 961 if (phy_interface_mode_is_rgmii(interface)) { 962 val |= MHWTRAP_P5_RGMII_MODE; 963 964 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 965 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 966 967 /* Don't set delay in DSA mode */ 968 if (!dsa_is_dsa_port(priv->ds, 5) && 969 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 970 interface == PHY_INTERFACE_MODE_RGMII_ID)) 971 tx_delay = 4; /* n * 0.5 ns */ 972 973 /* P5 RGMII TX Clock Control: delay x */ 974 mt7530_write(priv, MT7530_P5RGMIITXCR, 975 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 976 977 /* reduce P5 RGMII Tx driving, 8mA */ 978 mt7530_write(priv, MT7530_IO_DRV_CR, 979 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 980 } 981 982 mt7530_write(priv, MT7530_MHWTRAP, val); 983 984 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 985 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 986 987 priv->p5_interface = interface; 988 989 unlock_exit: 990 mutex_unlock(&priv->reg_mutex); 991 } 992 993 static int 994 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 995 { 996 struct mt7530_priv *priv = ds->priv; 997 int ret; 998 999 /* Setup max capability of CPU port at first */ 1000 if (priv->info->cpu_port_config) { 1001 ret = priv->info->cpu_port_config(ds, port); 1002 if (ret) 1003 return ret; 1004 } 1005 1006 /* Enable Mediatek header mode on the cpu port */ 1007 mt7530_write(priv, MT7530_PVC_P(port), 1008 PORT_SPEC_TAG); 1009 1010 /* Disable flooding by default */ 1011 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1012 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1013 1014 /* Set CPU port number */ 1015 if (priv->id == ID_MT7621) 1016 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1017 1018 /* CPU port gets connected to all user ports of 1019 * the switch. 1020 */ 1021 mt7530_write(priv, MT7530_PCR_P(port), 1022 PCR_MATRIX(dsa_user_ports(priv->ds))); 1023 1024 /* Set to fallback mode for independent VLAN learning */ 1025 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1026 MT7530_PORT_FALLBACK_MODE); 1027 1028 return 0; 1029 } 1030 1031 static int 1032 mt7530_port_enable(struct dsa_switch *ds, int port, 1033 struct phy_device *phy) 1034 { 1035 struct mt7530_priv *priv = ds->priv; 1036 1037 if (!dsa_is_user_port(ds, port)) 1038 return 0; 1039 1040 mutex_lock(&priv->reg_mutex); 1041 1042 /* Allow the user port gets connected to the cpu port and also 1043 * restore the port matrix if the port is the member of a certain 1044 * bridge. 1045 */ 1046 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1047 priv->ports[port].enable = true; 1048 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1049 priv->ports[port].pm); 1050 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1051 1052 mutex_unlock(&priv->reg_mutex); 1053 1054 return 0; 1055 } 1056 1057 static void 1058 mt7530_port_disable(struct dsa_switch *ds, int port) 1059 { 1060 struct mt7530_priv *priv = ds->priv; 1061 1062 if (!dsa_is_user_port(ds, port)) 1063 return; 1064 1065 mutex_lock(&priv->reg_mutex); 1066 1067 /* Clear up all port matrix which could be restored in the next 1068 * enablement for the port. 1069 */ 1070 priv->ports[port].enable = false; 1071 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1072 PCR_MATRIX_CLR); 1073 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1074 1075 mutex_unlock(&priv->reg_mutex); 1076 } 1077 1078 static int 1079 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1080 { 1081 struct mt7530_priv *priv = ds->priv; 1082 struct mii_bus *bus = priv->bus; 1083 int length; 1084 u32 val; 1085 1086 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1087 * largest MTU of the slave ports. Because the switch only has a global 1088 * RX length register, only allowing CPU port here is enough. 1089 */ 1090 if (!dsa_is_cpu_port(ds, port)) 1091 return 0; 1092 1093 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1094 1095 val = mt7530_mii_read(priv, MT7530_GMACCR); 1096 val &= ~MAX_RX_PKT_LEN_MASK; 1097 1098 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1099 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1100 if (length <= 1522) { 1101 val |= MAX_RX_PKT_LEN_1522; 1102 } else if (length <= 1536) { 1103 val |= MAX_RX_PKT_LEN_1536; 1104 } else if (length <= 1552) { 1105 val |= MAX_RX_PKT_LEN_1552; 1106 } else { 1107 val &= ~MAX_RX_JUMBO_MASK; 1108 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1109 val |= MAX_RX_PKT_LEN_JUMBO; 1110 } 1111 1112 mt7530_mii_write(priv, MT7530_GMACCR, val); 1113 1114 mutex_unlock(&bus->mdio_lock); 1115 1116 return 0; 1117 } 1118 1119 static int 1120 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1121 { 1122 return MT7530_MAX_MTU; 1123 } 1124 1125 static void 1126 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1127 { 1128 struct mt7530_priv *priv = ds->priv; 1129 u32 stp_state; 1130 1131 switch (state) { 1132 case BR_STATE_DISABLED: 1133 stp_state = MT7530_STP_DISABLED; 1134 break; 1135 case BR_STATE_BLOCKING: 1136 stp_state = MT7530_STP_BLOCKING; 1137 break; 1138 case BR_STATE_LISTENING: 1139 stp_state = MT7530_STP_LISTENING; 1140 break; 1141 case BR_STATE_LEARNING: 1142 stp_state = MT7530_STP_LEARNING; 1143 break; 1144 case BR_STATE_FORWARDING: 1145 default: 1146 stp_state = MT7530_STP_FORWARDING; 1147 break; 1148 } 1149 1150 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1151 FID_PST(FID_BRIDGED, stp_state)); 1152 } 1153 1154 static int 1155 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1156 struct switchdev_brport_flags flags, 1157 struct netlink_ext_ack *extack) 1158 { 1159 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1160 BR_BCAST_FLOOD)) 1161 return -EINVAL; 1162 1163 return 0; 1164 } 1165 1166 static int 1167 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1168 struct switchdev_brport_flags flags, 1169 struct netlink_ext_ack *extack) 1170 { 1171 struct mt7530_priv *priv = ds->priv; 1172 1173 if (flags.mask & BR_LEARNING) 1174 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1175 flags.val & BR_LEARNING ? 0 : SA_DIS); 1176 1177 if (flags.mask & BR_FLOOD) 1178 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1179 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1180 1181 if (flags.mask & BR_MCAST_FLOOD) 1182 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1183 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1184 1185 if (flags.mask & BR_BCAST_FLOOD) 1186 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1187 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1188 1189 return 0; 1190 } 1191 1192 static int 1193 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1194 struct net_device *bridge) 1195 { 1196 struct mt7530_priv *priv = ds->priv; 1197 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1198 int i; 1199 1200 mutex_lock(&priv->reg_mutex); 1201 1202 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1203 /* Add this port to the port matrix of the other ports in the 1204 * same bridge. If the port is disabled, port matrix is kept 1205 * and not being setup until the port becomes enabled. 1206 */ 1207 if (dsa_is_user_port(ds, i) && i != port) { 1208 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1209 continue; 1210 if (priv->ports[i].enable) 1211 mt7530_set(priv, MT7530_PCR_P(i), 1212 PCR_MATRIX(BIT(port))); 1213 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1214 1215 port_bitmap |= BIT(i); 1216 } 1217 } 1218 1219 /* Add the all other ports to this port matrix. */ 1220 if (priv->ports[port].enable) 1221 mt7530_rmw(priv, MT7530_PCR_P(port), 1222 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1223 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1224 1225 /* Set to fallback mode for independent VLAN learning */ 1226 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1227 MT7530_PORT_FALLBACK_MODE); 1228 1229 mutex_unlock(&priv->reg_mutex); 1230 1231 return 0; 1232 } 1233 1234 static void 1235 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1236 { 1237 struct mt7530_priv *priv = ds->priv; 1238 bool all_user_ports_removed = true; 1239 int i; 1240 1241 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1242 * bridge. Don't set standalone ports to fallback mode. 1243 */ 1244 if (dsa_to_port(ds, port)->bridge_dev) 1245 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1246 MT7530_PORT_FALLBACK_MODE); 1247 1248 mt7530_rmw(priv, MT7530_PVC_P(port), 1249 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1250 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1251 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1252 MT7530_VLAN_ACC_ALL); 1253 1254 /* Set PVID to 0 */ 1255 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1256 G0_PORT_VID_DEF); 1257 1258 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1259 if (dsa_is_user_port(ds, i) && 1260 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1261 all_user_ports_removed = false; 1262 break; 1263 } 1264 } 1265 1266 /* CPU port also does the same thing until all user ports belonging to 1267 * the CPU port get out of VLAN filtering mode. 1268 */ 1269 if (all_user_ports_removed) { 1270 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1271 PCR_MATRIX(dsa_user_ports(priv->ds))); 1272 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1273 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1274 } 1275 } 1276 1277 static void 1278 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1279 { 1280 struct mt7530_priv *priv = ds->priv; 1281 1282 /* Trapped into security mode allows packet forwarding through VLAN 1283 * table lookup. 1284 */ 1285 if (dsa_is_user_port(ds, port)) { 1286 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1287 MT7530_PORT_SECURITY_MODE); 1288 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1289 G0_PORT_VID(priv->ports[port].pvid)); 1290 1291 /* Only accept tagged frames if PVID is not set */ 1292 if (!priv->ports[port].pvid) 1293 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1294 MT7530_VLAN_ACC_TAGGED); 1295 } 1296 1297 /* Set the port as a user port which is to be able to recognize VID 1298 * from incoming packets before fetching entry within the VLAN table. 1299 */ 1300 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1301 VLAN_ATTR(MT7530_VLAN_USER) | 1302 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1303 } 1304 1305 static void 1306 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1307 struct net_device *bridge) 1308 { 1309 struct mt7530_priv *priv = ds->priv; 1310 int i; 1311 1312 mutex_lock(&priv->reg_mutex); 1313 1314 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1315 /* Remove this port from the port matrix of the other ports 1316 * in the same bridge. If the port is disabled, port matrix 1317 * is kept and not being setup until the port becomes enabled. 1318 * And the other port's port matrix cannot be broken when the 1319 * other port is still a VLAN-aware port. 1320 */ 1321 if (dsa_is_user_port(ds, i) && i != port && 1322 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1323 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1324 continue; 1325 if (priv->ports[i].enable) 1326 mt7530_clear(priv, MT7530_PCR_P(i), 1327 PCR_MATRIX(BIT(port))); 1328 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1329 } 1330 } 1331 1332 /* Set the cpu port to be the only one in the port matrix of 1333 * this port. 1334 */ 1335 if (priv->ports[port].enable) 1336 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1337 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1338 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1339 1340 /* When a port is removed from the bridge, the port would be set up 1341 * back to the default as is at initial boot which is a VLAN-unaware 1342 * port. 1343 */ 1344 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1345 MT7530_PORT_MATRIX_MODE); 1346 1347 mutex_unlock(&priv->reg_mutex); 1348 } 1349 1350 static int 1351 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1352 const unsigned char *addr, u16 vid) 1353 { 1354 struct mt7530_priv *priv = ds->priv; 1355 int ret; 1356 u8 port_mask = BIT(port); 1357 1358 mutex_lock(&priv->reg_mutex); 1359 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1360 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1361 mutex_unlock(&priv->reg_mutex); 1362 1363 return ret; 1364 } 1365 1366 static int 1367 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1368 const unsigned char *addr, u16 vid) 1369 { 1370 struct mt7530_priv *priv = ds->priv; 1371 int ret; 1372 u8 port_mask = BIT(port); 1373 1374 mutex_lock(&priv->reg_mutex); 1375 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1376 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1377 mutex_unlock(&priv->reg_mutex); 1378 1379 return ret; 1380 } 1381 1382 static int 1383 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1384 dsa_fdb_dump_cb_t *cb, void *data) 1385 { 1386 struct mt7530_priv *priv = ds->priv; 1387 struct mt7530_fdb _fdb = { 0 }; 1388 int cnt = MT7530_NUM_FDB_RECORDS; 1389 int ret = 0; 1390 u32 rsp = 0; 1391 1392 mutex_lock(&priv->reg_mutex); 1393 1394 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1395 if (ret < 0) 1396 goto err; 1397 1398 do { 1399 if (rsp & ATC_SRCH_HIT) { 1400 mt7530_fdb_read(priv, &_fdb); 1401 if (_fdb.port_mask & BIT(port)) { 1402 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1403 data); 1404 if (ret < 0) 1405 break; 1406 } 1407 } 1408 } while (--cnt && 1409 !(rsp & ATC_SRCH_END) && 1410 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1411 err: 1412 mutex_unlock(&priv->reg_mutex); 1413 1414 return 0; 1415 } 1416 1417 static int 1418 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1419 const struct switchdev_obj_port_mdb *mdb) 1420 { 1421 struct mt7530_priv *priv = ds->priv; 1422 const u8 *addr = mdb->addr; 1423 u16 vid = mdb->vid; 1424 u8 port_mask = 0; 1425 int ret; 1426 1427 mutex_lock(&priv->reg_mutex); 1428 1429 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1430 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1431 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1432 & PORT_MAP_MASK; 1433 1434 port_mask |= BIT(port); 1435 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1436 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1437 1438 mutex_unlock(&priv->reg_mutex); 1439 1440 return ret; 1441 } 1442 1443 static int 1444 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1445 const struct switchdev_obj_port_mdb *mdb) 1446 { 1447 struct mt7530_priv *priv = ds->priv; 1448 const u8 *addr = mdb->addr; 1449 u16 vid = mdb->vid; 1450 u8 port_mask = 0; 1451 int ret; 1452 1453 mutex_lock(&priv->reg_mutex); 1454 1455 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1456 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1457 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1458 & PORT_MAP_MASK; 1459 1460 port_mask &= ~BIT(port); 1461 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1462 port_mask ? STATIC_ENT : STATIC_EMP); 1463 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1464 1465 mutex_unlock(&priv->reg_mutex); 1466 1467 return ret; 1468 } 1469 1470 static int 1471 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1472 { 1473 struct mt7530_dummy_poll p; 1474 u32 val; 1475 int ret; 1476 1477 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1478 mt7530_write(priv, MT7530_VTCR, val); 1479 1480 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1481 ret = readx_poll_timeout(_mt7530_read, &p, val, 1482 !(val & VTCR_BUSY), 20, 20000); 1483 if (ret < 0) { 1484 dev_err(priv->dev, "poll timeout\n"); 1485 return ret; 1486 } 1487 1488 val = mt7530_read(priv, MT7530_VTCR); 1489 if (val & VTCR_INVALID) { 1490 dev_err(priv->dev, "read VTCR invalid\n"); 1491 return -EINVAL; 1492 } 1493 1494 return 0; 1495 } 1496 1497 static int 1498 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1499 struct netlink_ext_ack *extack) 1500 { 1501 if (vlan_filtering) { 1502 /* The port is being kept as VLAN-unaware port when bridge is 1503 * set up with vlan_filtering not being set, Otherwise, the 1504 * port and the corresponding CPU port is required the setup 1505 * for becoming a VLAN-aware port. 1506 */ 1507 mt7530_port_set_vlan_aware(ds, port); 1508 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1509 } else { 1510 mt7530_port_set_vlan_unaware(ds, port); 1511 } 1512 1513 return 0; 1514 } 1515 1516 static void 1517 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1518 struct mt7530_hw_vlan_entry *entry) 1519 { 1520 u8 new_members; 1521 u32 val; 1522 1523 new_members = entry->old_members | BIT(entry->port) | 1524 BIT(MT7530_CPU_PORT); 1525 1526 /* Validate the entry with independent learning, create egress tag per 1527 * VLAN and joining the port as one of the port members. 1528 */ 1529 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1530 VLAN_VALID; 1531 mt7530_write(priv, MT7530_VAWD1, val); 1532 1533 /* Decide whether adding tag or not for those outgoing packets from the 1534 * port inside the VLAN. 1535 */ 1536 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1537 MT7530_VLAN_EGRESS_TAG; 1538 mt7530_rmw(priv, MT7530_VAWD2, 1539 ETAG_CTRL_P_MASK(entry->port), 1540 ETAG_CTRL_P(entry->port, val)); 1541 1542 /* CPU port is always taken as a tagged port for serving more than one 1543 * VLANs across and also being applied with egress type stack mode for 1544 * that VLAN tags would be appended after hardware special tag used as 1545 * DSA tag. 1546 */ 1547 mt7530_rmw(priv, MT7530_VAWD2, 1548 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1549 ETAG_CTRL_P(MT7530_CPU_PORT, 1550 MT7530_VLAN_EGRESS_STACK)); 1551 } 1552 1553 static void 1554 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1555 struct mt7530_hw_vlan_entry *entry) 1556 { 1557 u8 new_members; 1558 u32 val; 1559 1560 new_members = entry->old_members & ~BIT(entry->port); 1561 1562 val = mt7530_read(priv, MT7530_VAWD1); 1563 if (!(val & VLAN_VALID)) { 1564 dev_err(priv->dev, 1565 "Cannot be deleted due to invalid entry\n"); 1566 return; 1567 } 1568 1569 /* If certain member apart from CPU port is still alive in the VLAN, 1570 * the entry would be kept valid. Otherwise, the entry is got to be 1571 * disabled. 1572 */ 1573 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1574 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1575 VLAN_VALID; 1576 mt7530_write(priv, MT7530_VAWD1, val); 1577 } else { 1578 mt7530_write(priv, MT7530_VAWD1, 0); 1579 mt7530_write(priv, MT7530_VAWD2, 0); 1580 } 1581 } 1582 1583 static void 1584 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1585 struct mt7530_hw_vlan_entry *entry, 1586 mt7530_vlan_op vlan_op) 1587 { 1588 u32 val; 1589 1590 /* Fetch entry */ 1591 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1592 1593 val = mt7530_read(priv, MT7530_VAWD1); 1594 1595 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1596 1597 /* Manipulate entry */ 1598 vlan_op(priv, entry); 1599 1600 /* Flush result to hardware */ 1601 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1602 } 1603 1604 static int 1605 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1606 const struct switchdev_obj_port_vlan *vlan, 1607 struct netlink_ext_ack *extack) 1608 { 1609 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1610 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1611 struct mt7530_hw_vlan_entry new_entry; 1612 struct mt7530_priv *priv = ds->priv; 1613 1614 mutex_lock(&priv->reg_mutex); 1615 1616 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1617 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1618 1619 if (pvid) { 1620 priv->ports[port].pvid = vlan->vid; 1621 1622 /* Accept all frames if PVID is set */ 1623 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1624 MT7530_VLAN_ACC_ALL); 1625 1626 /* Only configure PVID if VLAN filtering is enabled */ 1627 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1628 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1629 G0_PORT_VID_MASK, 1630 G0_PORT_VID(vlan->vid)); 1631 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1632 /* This VLAN is overwritten without PVID, so unset it */ 1633 priv->ports[port].pvid = G0_PORT_VID_DEF; 1634 1635 /* Only accept tagged frames if the port is VLAN-aware */ 1636 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1637 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1638 MT7530_VLAN_ACC_TAGGED); 1639 1640 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1641 G0_PORT_VID_DEF); 1642 } 1643 1644 mutex_unlock(&priv->reg_mutex); 1645 1646 return 0; 1647 } 1648 1649 static int 1650 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1651 const struct switchdev_obj_port_vlan *vlan) 1652 { 1653 struct mt7530_hw_vlan_entry target_entry; 1654 struct mt7530_priv *priv = ds->priv; 1655 1656 mutex_lock(&priv->reg_mutex); 1657 1658 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1659 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1660 mt7530_hw_vlan_del); 1661 1662 /* PVID is being restored to the default whenever the PVID port 1663 * is being removed from the VLAN. 1664 */ 1665 if (priv->ports[port].pvid == vlan->vid) { 1666 priv->ports[port].pvid = G0_PORT_VID_DEF; 1667 1668 /* Only accept tagged frames if the port is VLAN-aware */ 1669 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1670 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1671 MT7530_VLAN_ACC_TAGGED); 1672 1673 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1674 G0_PORT_VID_DEF); 1675 } 1676 1677 1678 mutex_unlock(&priv->reg_mutex); 1679 1680 return 0; 1681 } 1682 1683 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1684 { 1685 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1686 MIRROR_PORT(val); 1687 } 1688 1689 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1690 { 1691 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1692 MIRROR_PORT(val); 1693 } 1694 1695 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1696 struct dsa_mall_mirror_tc_entry *mirror, 1697 bool ingress) 1698 { 1699 struct mt7530_priv *priv = ds->priv; 1700 int monitor_port; 1701 u32 val; 1702 1703 /* Check for existent entry */ 1704 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1705 return -EEXIST; 1706 1707 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1708 1709 /* MT7530 only supports one monitor port */ 1710 monitor_port = mt753x_mirror_port_get(priv->id, val); 1711 if (val & MT753X_MIRROR_EN(priv->id) && 1712 monitor_port != mirror->to_local_port) 1713 return -EEXIST; 1714 1715 val |= MT753X_MIRROR_EN(priv->id); 1716 val &= ~MT753X_MIRROR_MASK(priv->id); 1717 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1718 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1719 1720 val = mt7530_read(priv, MT7530_PCR_P(port)); 1721 if (ingress) { 1722 val |= PORT_RX_MIR; 1723 priv->mirror_rx |= BIT(port); 1724 } else { 1725 val |= PORT_TX_MIR; 1726 priv->mirror_tx |= BIT(port); 1727 } 1728 mt7530_write(priv, MT7530_PCR_P(port), val); 1729 1730 return 0; 1731 } 1732 1733 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1734 struct dsa_mall_mirror_tc_entry *mirror) 1735 { 1736 struct mt7530_priv *priv = ds->priv; 1737 u32 val; 1738 1739 val = mt7530_read(priv, MT7530_PCR_P(port)); 1740 if (mirror->ingress) { 1741 val &= ~PORT_RX_MIR; 1742 priv->mirror_rx &= ~BIT(port); 1743 } else { 1744 val &= ~PORT_TX_MIR; 1745 priv->mirror_tx &= ~BIT(port); 1746 } 1747 mt7530_write(priv, MT7530_PCR_P(port), val); 1748 1749 if (!priv->mirror_rx && !priv->mirror_tx) { 1750 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1751 val &= ~MT753X_MIRROR_EN(priv->id); 1752 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1753 } 1754 } 1755 1756 static enum dsa_tag_protocol 1757 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1758 enum dsa_tag_protocol mp) 1759 { 1760 return DSA_TAG_PROTO_MTK; 1761 } 1762 1763 #ifdef CONFIG_GPIOLIB 1764 static inline u32 1765 mt7530_gpio_to_bit(unsigned int offset) 1766 { 1767 /* Map GPIO offset to register bit 1768 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1769 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1770 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1771 * [14:12] port 3 LED 0..2 as GPIO 9..11 1772 * [18:16] port 4 LED 0..2 as GPIO 12..14 1773 */ 1774 return BIT(offset + offset / 3); 1775 } 1776 1777 static int 1778 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1779 { 1780 struct mt7530_priv *priv = gpiochip_get_data(gc); 1781 u32 bit = mt7530_gpio_to_bit(offset); 1782 1783 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1784 } 1785 1786 static void 1787 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1788 { 1789 struct mt7530_priv *priv = gpiochip_get_data(gc); 1790 u32 bit = mt7530_gpio_to_bit(offset); 1791 1792 if (value) 1793 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1794 else 1795 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1796 } 1797 1798 static int 1799 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1800 { 1801 struct mt7530_priv *priv = gpiochip_get_data(gc); 1802 u32 bit = mt7530_gpio_to_bit(offset); 1803 1804 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1805 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1806 } 1807 1808 static int 1809 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1810 { 1811 struct mt7530_priv *priv = gpiochip_get_data(gc); 1812 u32 bit = mt7530_gpio_to_bit(offset); 1813 1814 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1815 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1816 1817 return 0; 1818 } 1819 1820 static int 1821 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1822 { 1823 struct mt7530_priv *priv = gpiochip_get_data(gc); 1824 u32 bit = mt7530_gpio_to_bit(offset); 1825 1826 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1827 1828 if (value) 1829 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1830 else 1831 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1832 1833 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1834 1835 return 0; 1836 } 1837 1838 static int 1839 mt7530_setup_gpio(struct mt7530_priv *priv) 1840 { 1841 struct device *dev = priv->dev; 1842 struct gpio_chip *gc; 1843 1844 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1845 if (!gc) 1846 return -ENOMEM; 1847 1848 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1849 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1850 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1851 1852 gc->label = "mt7530"; 1853 gc->parent = dev; 1854 gc->owner = THIS_MODULE; 1855 gc->get_direction = mt7530_gpio_get_direction; 1856 gc->direction_input = mt7530_gpio_direction_input; 1857 gc->direction_output = mt7530_gpio_direction_output; 1858 gc->get = mt7530_gpio_get; 1859 gc->set = mt7530_gpio_set; 1860 gc->base = -1; 1861 gc->ngpio = 15; 1862 gc->can_sleep = true; 1863 1864 return devm_gpiochip_add_data(dev, gc, priv); 1865 } 1866 #endif /* CONFIG_GPIOLIB */ 1867 1868 static irqreturn_t 1869 mt7530_irq_thread_fn(int irq, void *dev_id) 1870 { 1871 struct mt7530_priv *priv = dev_id; 1872 bool handled = false; 1873 u32 val; 1874 int p; 1875 1876 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1877 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1878 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1879 mutex_unlock(&priv->bus->mdio_lock); 1880 1881 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1882 if (BIT(p) & val) { 1883 unsigned int irq; 1884 1885 irq = irq_find_mapping(priv->irq_domain, p); 1886 handle_nested_irq(irq); 1887 handled = true; 1888 } 1889 } 1890 1891 return IRQ_RETVAL(handled); 1892 } 1893 1894 static void 1895 mt7530_irq_mask(struct irq_data *d) 1896 { 1897 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1898 1899 priv->irq_enable &= ~BIT(d->hwirq); 1900 } 1901 1902 static void 1903 mt7530_irq_unmask(struct irq_data *d) 1904 { 1905 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1906 1907 priv->irq_enable |= BIT(d->hwirq); 1908 } 1909 1910 static void 1911 mt7530_irq_bus_lock(struct irq_data *d) 1912 { 1913 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1914 1915 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 1916 } 1917 1918 static void 1919 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1920 { 1921 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1922 1923 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1924 mutex_unlock(&priv->bus->mdio_lock); 1925 } 1926 1927 static struct irq_chip mt7530_irq_chip = { 1928 .name = KBUILD_MODNAME, 1929 .irq_mask = mt7530_irq_mask, 1930 .irq_unmask = mt7530_irq_unmask, 1931 .irq_bus_lock = mt7530_irq_bus_lock, 1932 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1933 }; 1934 1935 static int 1936 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1937 irq_hw_number_t hwirq) 1938 { 1939 irq_set_chip_data(irq, domain->host_data); 1940 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1941 irq_set_nested_thread(irq, true); 1942 irq_set_noprobe(irq); 1943 1944 return 0; 1945 } 1946 1947 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1948 .map = mt7530_irq_map, 1949 .xlate = irq_domain_xlate_onecell, 1950 }; 1951 1952 static void 1953 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 1954 { 1955 struct dsa_switch *ds = priv->ds; 1956 int p; 1957 1958 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1959 if (BIT(p) & ds->phys_mii_mask) { 1960 unsigned int irq; 1961 1962 irq = irq_create_mapping(priv->irq_domain, p); 1963 ds->slave_mii_bus->irq[p] = irq; 1964 } 1965 } 1966 } 1967 1968 static int 1969 mt7530_setup_irq(struct mt7530_priv *priv) 1970 { 1971 struct device *dev = priv->dev; 1972 struct device_node *np = dev->of_node; 1973 int ret; 1974 1975 if (!of_property_read_bool(np, "interrupt-controller")) { 1976 dev_info(dev, "no interrupt support\n"); 1977 return 0; 1978 } 1979 1980 priv->irq = of_irq_get(np, 0); 1981 if (priv->irq <= 0) { 1982 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 1983 return priv->irq ? : -EINVAL; 1984 } 1985 1986 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 1987 &mt7530_irq_domain_ops, priv); 1988 if (!priv->irq_domain) { 1989 dev_err(dev, "failed to create IRQ domain\n"); 1990 return -ENOMEM; 1991 } 1992 1993 /* This register must be set for MT7530 to properly fire interrupts */ 1994 if (priv->id != ID_MT7531) 1995 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 1996 1997 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 1998 IRQF_ONESHOT, KBUILD_MODNAME, priv); 1999 if (ret) { 2000 irq_domain_remove(priv->irq_domain); 2001 dev_err(dev, "failed to request IRQ: %d\n", ret); 2002 return ret; 2003 } 2004 2005 return 0; 2006 } 2007 2008 static void 2009 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2010 { 2011 int p; 2012 2013 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2014 if (BIT(p) & priv->ds->phys_mii_mask) { 2015 unsigned int irq; 2016 2017 irq = irq_find_mapping(priv->irq_domain, p); 2018 irq_dispose_mapping(irq); 2019 } 2020 } 2021 } 2022 2023 static void 2024 mt7530_free_irq_common(struct mt7530_priv *priv) 2025 { 2026 free_irq(priv->irq, priv); 2027 irq_domain_remove(priv->irq_domain); 2028 } 2029 2030 static void 2031 mt7530_free_irq(struct mt7530_priv *priv) 2032 { 2033 mt7530_free_mdio_irq(priv); 2034 mt7530_free_irq_common(priv); 2035 } 2036 2037 static int 2038 mt7530_setup_mdio(struct mt7530_priv *priv) 2039 { 2040 struct dsa_switch *ds = priv->ds; 2041 struct device *dev = priv->dev; 2042 struct mii_bus *bus; 2043 static int idx; 2044 int ret; 2045 2046 bus = devm_mdiobus_alloc(dev); 2047 if (!bus) 2048 return -ENOMEM; 2049 2050 ds->slave_mii_bus = bus; 2051 bus->priv = priv; 2052 bus->name = KBUILD_MODNAME "-mii"; 2053 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2054 bus->read = mt753x_phy_read; 2055 bus->write = mt753x_phy_write; 2056 bus->parent = dev; 2057 bus->phy_mask = ~ds->phys_mii_mask; 2058 2059 if (priv->irq) 2060 mt7530_setup_mdio_irq(priv); 2061 2062 ret = mdiobus_register(bus); 2063 if (ret) { 2064 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2065 if (priv->irq) 2066 mt7530_free_mdio_irq(priv); 2067 } 2068 2069 return ret; 2070 } 2071 2072 static int 2073 mt7530_setup(struct dsa_switch *ds) 2074 { 2075 struct mt7530_priv *priv = ds->priv; 2076 struct device_node *phy_node; 2077 struct device_node *mac_np; 2078 struct mt7530_dummy_poll p; 2079 phy_interface_t interface; 2080 struct device_node *dn; 2081 u32 id, val; 2082 int ret, i; 2083 2084 /* The parent node of master netdev which holds the common system 2085 * controller also is the container for two GMACs nodes representing 2086 * as two netdev instances. 2087 */ 2088 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 2089 ds->assisted_learning_on_cpu_port = true; 2090 ds->mtu_enforcement_ingress = true; 2091 2092 if (priv->id == ID_MT7530) { 2093 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2094 ret = regulator_enable(priv->core_pwr); 2095 if (ret < 0) { 2096 dev_err(priv->dev, 2097 "Failed to enable core power: %d\n", ret); 2098 return ret; 2099 } 2100 2101 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2102 ret = regulator_enable(priv->io_pwr); 2103 if (ret < 0) { 2104 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2105 ret); 2106 return ret; 2107 } 2108 } 2109 2110 /* Reset whole chip through gpio pin or memory-mapped registers for 2111 * different type of hardware 2112 */ 2113 if (priv->mcm) { 2114 reset_control_assert(priv->rstc); 2115 usleep_range(1000, 1100); 2116 reset_control_deassert(priv->rstc); 2117 } else { 2118 gpiod_set_value_cansleep(priv->reset, 0); 2119 usleep_range(1000, 1100); 2120 gpiod_set_value_cansleep(priv->reset, 1); 2121 } 2122 2123 /* Waiting for MT7530 got to stable */ 2124 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2125 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2126 20, 1000000); 2127 if (ret < 0) { 2128 dev_err(priv->dev, "reset timeout\n"); 2129 return ret; 2130 } 2131 2132 id = mt7530_read(priv, MT7530_CREV); 2133 id >>= CHIP_NAME_SHIFT; 2134 if (id != MT7530_ID) { 2135 dev_err(priv->dev, "chip %x can't be supported\n", id); 2136 return -ENODEV; 2137 } 2138 2139 /* Reset the switch through internal reset */ 2140 mt7530_write(priv, MT7530_SYS_CTRL, 2141 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2142 SYS_CTRL_REG_RST); 2143 2144 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 2145 val = mt7530_read(priv, MT7530_MHWTRAP); 2146 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2147 val |= MHWTRAP_MANUAL; 2148 mt7530_write(priv, MT7530_MHWTRAP, val); 2149 2150 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2151 2152 /* Enable and reset MIB counters */ 2153 mt7530_mib_reset(ds); 2154 2155 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2156 /* Disable forwarding by default on all ports */ 2157 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2158 PCR_MATRIX_CLR); 2159 2160 /* Disable learning by default on all ports */ 2161 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2162 2163 if (dsa_is_cpu_port(ds, i)) { 2164 ret = mt753x_cpu_port_enable(ds, i); 2165 if (ret) 2166 return ret; 2167 } else { 2168 mt7530_port_disable(ds, i); 2169 2170 /* Set default PVID to 0 on all user ports */ 2171 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2172 G0_PORT_VID_DEF); 2173 } 2174 /* Enable consistent egress tag */ 2175 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2176 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2177 } 2178 2179 /* Setup port 5 */ 2180 priv->p5_intf_sel = P5_DISABLED; 2181 interface = PHY_INTERFACE_MODE_NA; 2182 2183 if (!dsa_is_unused_port(ds, 5)) { 2184 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2185 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2186 if (ret && ret != -ENODEV) 2187 return ret; 2188 } else { 2189 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2190 for_each_child_of_node(dn, mac_np) { 2191 if (!of_device_is_compatible(mac_np, 2192 "mediatek,eth-mac")) 2193 continue; 2194 2195 ret = of_property_read_u32(mac_np, "reg", &id); 2196 if (ret < 0 || id != 1) 2197 continue; 2198 2199 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2200 if (!phy_node) 2201 continue; 2202 2203 if (phy_node->parent == priv->dev->of_node->parent) { 2204 ret = of_get_phy_mode(mac_np, &interface); 2205 if (ret && ret != -ENODEV) { 2206 of_node_put(mac_np); 2207 return ret; 2208 } 2209 id = of_mdio_parse_addr(ds->dev, phy_node); 2210 if (id == 0) 2211 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2212 if (id == 4) 2213 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2214 } 2215 of_node_put(mac_np); 2216 of_node_put(phy_node); 2217 break; 2218 } 2219 } 2220 2221 #ifdef CONFIG_GPIOLIB 2222 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2223 ret = mt7530_setup_gpio(priv); 2224 if (ret) 2225 return ret; 2226 } 2227 #endif /* CONFIG_GPIOLIB */ 2228 2229 mt7530_setup_port5(ds, interface); 2230 2231 /* Flush the FDB table */ 2232 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2233 if (ret < 0) 2234 return ret; 2235 2236 return 0; 2237 } 2238 2239 static int 2240 mt7531_setup(struct dsa_switch *ds) 2241 { 2242 struct mt7530_priv *priv = ds->priv; 2243 struct mt7530_dummy_poll p; 2244 u32 val, id; 2245 int ret, i; 2246 2247 /* Reset whole chip through gpio pin or memory-mapped registers for 2248 * different type of hardware 2249 */ 2250 if (priv->mcm) { 2251 reset_control_assert(priv->rstc); 2252 usleep_range(1000, 1100); 2253 reset_control_deassert(priv->rstc); 2254 } else { 2255 gpiod_set_value_cansleep(priv->reset, 0); 2256 usleep_range(1000, 1100); 2257 gpiod_set_value_cansleep(priv->reset, 1); 2258 } 2259 2260 /* Waiting for MT7530 got to stable */ 2261 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2262 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2263 20, 1000000); 2264 if (ret < 0) { 2265 dev_err(priv->dev, "reset timeout\n"); 2266 return ret; 2267 } 2268 2269 id = mt7530_read(priv, MT7531_CREV); 2270 id >>= CHIP_NAME_SHIFT; 2271 2272 if (id != MT7531_ID) { 2273 dev_err(priv->dev, "chip %x can't be supported\n", id); 2274 return -ENODEV; 2275 } 2276 2277 /* Reset the switch through internal reset */ 2278 mt7530_write(priv, MT7530_SYS_CTRL, 2279 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2280 SYS_CTRL_REG_RST); 2281 2282 if (mt7531_dual_sgmii_supported(priv)) { 2283 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2284 2285 /* Let ds->slave_mii_bus be able to access external phy. */ 2286 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2287 MT7531_EXT_P_MDC_11); 2288 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2289 MT7531_EXT_P_MDIO_12); 2290 } else { 2291 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2292 } 2293 dev_dbg(ds->dev, "P5 support %s interface\n", 2294 p5_intf_modes(priv->p5_intf_sel)); 2295 2296 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2297 MT7531_GPIO0_INTERRUPT); 2298 2299 /* Let phylink decide the interface later. */ 2300 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2301 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2302 2303 /* Enable PHY core PLL, since phy_device has not yet been created 2304 * provided for phy_[read,write]_mmd_indirect is called, we provide 2305 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2306 * function. 2307 */ 2308 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2309 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2310 val |= MT7531_PHY_PLL_BYPASS_MODE; 2311 val &= ~MT7531_PHY_PLL_OFF; 2312 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2313 CORE_PLL_GROUP4, val); 2314 2315 /* BPDU to CPU port */ 2316 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2317 BIT(MT7530_CPU_PORT)); 2318 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2319 MT753X_BPDU_CPU_ONLY); 2320 2321 /* Enable and reset MIB counters */ 2322 mt7530_mib_reset(ds); 2323 2324 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2325 /* Disable forwarding by default on all ports */ 2326 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2327 PCR_MATRIX_CLR); 2328 2329 /* Disable learning by default on all ports */ 2330 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2331 2332 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2333 2334 if (dsa_is_cpu_port(ds, i)) { 2335 ret = mt753x_cpu_port_enable(ds, i); 2336 if (ret) 2337 return ret; 2338 } else { 2339 mt7530_port_disable(ds, i); 2340 2341 /* Set default PVID to 0 on all user ports */ 2342 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2343 G0_PORT_VID_DEF); 2344 } 2345 2346 /* Enable consistent egress tag */ 2347 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2348 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2349 } 2350 2351 ds->assisted_learning_on_cpu_port = true; 2352 ds->mtu_enforcement_ingress = true; 2353 2354 /* Flush the FDB table */ 2355 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2356 if (ret < 0) 2357 return ret; 2358 2359 return 0; 2360 } 2361 2362 static bool 2363 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2364 const struct phylink_link_state *state) 2365 { 2366 struct mt7530_priv *priv = ds->priv; 2367 2368 switch (port) { 2369 case 0 ... 4: /* Internal phy */ 2370 if (state->interface != PHY_INTERFACE_MODE_GMII) 2371 return false; 2372 break; 2373 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2374 if (!phy_interface_mode_is_rgmii(state->interface) && 2375 state->interface != PHY_INTERFACE_MODE_MII && 2376 state->interface != PHY_INTERFACE_MODE_GMII) 2377 return false; 2378 break; 2379 case 6: /* 1st cpu port */ 2380 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2381 state->interface != PHY_INTERFACE_MODE_TRGMII) 2382 return false; 2383 break; 2384 default: 2385 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2386 port); 2387 return false; 2388 } 2389 2390 return true; 2391 } 2392 2393 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2394 { 2395 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2396 } 2397 2398 static bool 2399 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2400 const struct phylink_link_state *state) 2401 { 2402 struct mt7530_priv *priv = ds->priv; 2403 2404 switch (port) { 2405 case 0 ... 4: /* Internal phy */ 2406 if (state->interface != PHY_INTERFACE_MODE_GMII) 2407 return false; 2408 break; 2409 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2410 if (mt7531_is_rgmii_port(priv, port)) 2411 return phy_interface_mode_is_rgmii(state->interface); 2412 fallthrough; 2413 case 6: /* 1st cpu port supports sgmii/8023z only */ 2414 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2415 !phy_interface_mode_is_8023z(state->interface)) 2416 return false; 2417 break; 2418 default: 2419 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2420 port); 2421 return false; 2422 } 2423 2424 return true; 2425 } 2426 2427 static bool 2428 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2429 const struct phylink_link_state *state) 2430 { 2431 struct mt7530_priv *priv = ds->priv; 2432 2433 return priv->info->phy_mode_supported(ds, port, state); 2434 } 2435 2436 static int 2437 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2438 { 2439 struct mt7530_priv *priv = ds->priv; 2440 2441 return priv->info->pad_setup(ds, state->interface); 2442 } 2443 2444 static int 2445 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2446 phy_interface_t interface) 2447 { 2448 struct mt7530_priv *priv = ds->priv; 2449 2450 /* Only need to setup port5. */ 2451 if (port != 5) 2452 return 0; 2453 2454 mt7530_setup_port5(priv->ds, interface); 2455 2456 return 0; 2457 } 2458 2459 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2460 phy_interface_t interface, 2461 struct phy_device *phydev) 2462 { 2463 u32 val; 2464 2465 if (!mt7531_is_rgmii_port(priv, port)) { 2466 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2467 port); 2468 return -EINVAL; 2469 } 2470 2471 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2472 val |= GP_CLK_EN; 2473 val &= ~GP_MODE_MASK; 2474 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2475 val &= ~CLK_SKEW_IN_MASK; 2476 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2477 val &= ~CLK_SKEW_OUT_MASK; 2478 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2479 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2480 2481 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2482 if (!phydev || phy_driver_is_genphy(phydev)) { 2483 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2484 switch (interface) { 2485 case PHY_INTERFACE_MODE_RGMII: 2486 val |= TXCLK_NO_REVERSE; 2487 val |= RXCLK_NO_DELAY; 2488 break; 2489 case PHY_INTERFACE_MODE_RGMII_RXID: 2490 val |= TXCLK_NO_REVERSE; 2491 break; 2492 case PHY_INTERFACE_MODE_RGMII_TXID: 2493 val |= RXCLK_NO_DELAY; 2494 break; 2495 case PHY_INTERFACE_MODE_RGMII_ID: 2496 break; 2497 default: 2498 return -EINVAL; 2499 } 2500 } 2501 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2502 2503 return 0; 2504 } 2505 2506 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2507 unsigned long *supported) 2508 { 2509 /* Port5 supports ethier RGMII or SGMII. 2510 * Port6 supports SGMII only. 2511 */ 2512 switch (port) { 2513 case 5: 2514 if (mt7531_is_rgmii_port(priv, port)) 2515 break; 2516 fallthrough; 2517 case 6: 2518 phylink_set(supported, 1000baseX_Full); 2519 phylink_set(supported, 2500baseX_Full); 2520 phylink_set(supported, 2500baseT_Full); 2521 } 2522 } 2523 2524 static void 2525 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2526 unsigned int mode, phy_interface_t interface, 2527 int speed, int duplex) 2528 { 2529 struct mt7530_priv *priv = ds->priv; 2530 unsigned int val; 2531 2532 /* For adjusting speed and duplex of SGMII force mode. */ 2533 if (interface != PHY_INTERFACE_MODE_SGMII || 2534 phylink_autoneg_inband(mode)) 2535 return; 2536 2537 /* SGMII force mode setting */ 2538 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2539 val &= ~MT7531_SGMII_IF_MODE_MASK; 2540 2541 switch (speed) { 2542 case SPEED_10: 2543 val |= MT7531_SGMII_FORCE_SPEED_10; 2544 break; 2545 case SPEED_100: 2546 val |= MT7531_SGMII_FORCE_SPEED_100; 2547 break; 2548 case SPEED_1000: 2549 val |= MT7531_SGMII_FORCE_SPEED_1000; 2550 break; 2551 } 2552 2553 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2554 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2555 */ 2556 if ((speed == SPEED_10 || speed == SPEED_100) && 2557 duplex != DUPLEX_FULL) 2558 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2559 2560 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2561 } 2562 2563 static bool mt753x_is_mac_port(u32 port) 2564 { 2565 return (port == 5 || port == 6); 2566 } 2567 2568 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2569 phy_interface_t interface) 2570 { 2571 u32 val; 2572 2573 if (!mt753x_is_mac_port(port)) 2574 return -EINVAL; 2575 2576 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2577 MT7531_SGMII_PHYA_PWD); 2578 2579 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2580 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2581 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2582 * encoding. 2583 */ 2584 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2585 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2586 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2587 2588 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2589 2590 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2591 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2592 */ 2593 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2594 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2595 MT7531_SGMII_FORCE_SPEED_1000); 2596 2597 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2598 2599 return 0; 2600 } 2601 2602 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2603 phy_interface_t interface) 2604 { 2605 if (!mt753x_is_mac_port(port)) 2606 return -EINVAL; 2607 2608 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2609 MT7531_SGMII_PHYA_PWD); 2610 2611 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2612 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2613 2614 mt7530_set(priv, MT7531_SGMII_MODE(port), 2615 MT7531_SGMII_REMOTE_FAULT_DIS | 2616 MT7531_SGMII_SPEED_DUPLEX_AN); 2617 2618 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2619 MT7531_SGMII_TX_CONFIG_MASK, 1); 2620 2621 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2622 2623 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2624 2625 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2626 2627 return 0; 2628 } 2629 2630 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2631 { 2632 struct mt7530_priv *priv = ds->priv; 2633 u32 val; 2634 2635 /* Only restart AN when AN is enabled */ 2636 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2637 if (val & MT7531_SGMII_AN_ENABLE) { 2638 val |= MT7531_SGMII_AN_RESTART; 2639 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2640 } 2641 } 2642 2643 static int 2644 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2645 phy_interface_t interface) 2646 { 2647 struct mt7530_priv *priv = ds->priv; 2648 struct phy_device *phydev; 2649 struct dsa_port *dp; 2650 2651 if (!mt753x_is_mac_port(port)) { 2652 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2653 return -EINVAL; 2654 } 2655 2656 switch (interface) { 2657 case PHY_INTERFACE_MODE_RGMII: 2658 case PHY_INTERFACE_MODE_RGMII_ID: 2659 case PHY_INTERFACE_MODE_RGMII_RXID: 2660 case PHY_INTERFACE_MODE_RGMII_TXID: 2661 dp = dsa_to_port(ds, port); 2662 phydev = dp->slave->phydev; 2663 return mt7531_rgmii_setup(priv, port, interface, phydev); 2664 case PHY_INTERFACE_MODE_SGMII: 2665 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2666 case PHY_INTERFACE_MODE_NA: 2667 case PHY_INTERFACE_MODE_1000BASEX: 2668 case PHY_INTERFACE_MODE_2500BASEX: 2669 if (phylink_autoneg_inband(mode)) 2670 return -EINVAL; 2671 2672 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2673 default: 2674 return -EINVAL; 2675 } 2676 2677 return -EINVAL; 2678 } 2679 2680 static int 2681 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2682 const struct phylink_link_state *state) 2683 { 2684 struct mt7530_priv *priv = ds->priv; 2685 2686 return priv->info->mac_port_config(ds, port, mode, state->interface); 2687 } 2688 2689 static void 2690 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2691 const struct phylink_link_state *state) 2692 { 2693 struct mt7530_priv *priv = ds->priv; 2694 u32 mcr_cur, mcr_new; 2695 2696 if (!mt753x_phy_mode_supported(ds, port, state)) 2697 goto unsupported; 2698 2699 switch (port) { 2700 case 0 ... 4: /* Internal phy */ 2701 if (state->interface != PHY_INTERFACE_MODE_GMII) 2702 goto unsupported; 2703 break; 2704 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2705 if (priv->p5_interface == state->interface) 2706 break; 2707 2708 if (mt753x_mac_config(ds, port, mode, state) < 0) 2709 goto unsupported; 2710 2711 if (priv->p5_intf_sel != P5_DISABLED) 2712 priv->p5_interface = state->interface; 2713 break; 2714 case 6: /* 1st cpu port */ 2715 if (priv->p6_interface == state->interface) 2716 break; 2717 2718 mt753x_pad_setup(ds, state); 2719 2720 if (mt753x_mac_config(ds, port, mode, state) < 0) 2721 goto unsupported; 2722 2723 priv->p6_interface = state->interface; 2724 break; 2725 default: 2726 unsupported: 2727 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2728 __func__, phy_modes(state->interface), port); 2729 return; 2730 } 2731 2732 if (phylink_autoneg_inband(mode) && 2733 state->interface != PHY_INTERFACE_MODE_SGMII) { 2734 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2735 __func__); 2736 return; 2737 } 2738 2739 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2740 mcr_new = mcr_cur; 2741 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2742 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2743 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2744 2745 /* Are we connected to external phy */ 2746 if (port == 5 && dsa_is_user_port(ds, 5)) 2747 mcr_new |= PMCR_EXT_PHY; 2748 2749 if (mcr_new != mcr_cur) 2750 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2751 } 2752 2753 static void 2754 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2755 { 2756 struct mt7530_priv *priv = ds->priv; 2757 2758 if (!priv->info->mac_pcs_an_restart) 2759 return; 2760 2761 priv->info->mac_pcs_an_restart(ds, port); 2762 } 2763 2764 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2765 unsigned int mode, 2766 phy_interface_t interface) 2767 { 2768 struct mt7530_priv *priv = ds->priv; 2769 2770 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2771 } 2772 2773 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2774 unsigned int mode, phy_interface_t interface, 2775 int speed, int duplex) 2776 { 2777 struct mt7530_priv *priv = ds->priv; 2778 2779 if (!priv->info->mac_pcs_link_up) 2780 return; 2781 2782 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2783 } 2784 2785 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2786 unsigned int mode, 2787 phy_interface_t interface, 2788 struct phy_device *phydev, 2789 int speed, int duplex, 2790 bool tx_pause, bool rx_pause) 2791 { 2792 struct mt7530_priv *priv = ds->priv; 2793 u32 mcr; 2794 2795 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2796 2797 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2798 2799 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2800 * variants. 2801 */ 2802 if (interface == PHY_INTERFACE_MODE_TRGMII || 2803 (phy_interface_mode_is_8023z(interface))) { 2804 speed = SPEED_1000; 2805 duplex = DUPLEX_FULL; 2806 } 2807 2808 switch (speed) { 2809 case SPEED_1000: 2810 mcr |= PMCR_FORCE_SPEED_1000; 2811 break; 2812 case SPEED_100: 2813 mcr |= PMCR_FORCE_SPEED_100; 2814 break; 2815 } 2816 if (duplex == DUPLEX_FULL) { 2817 mcr |= PMCR_FORCE_FDX; 2818 if (tx_pause) 2819 mcr |= PMCR_TX_FC_EN; 2820 if (rx_pause) 2821 mcr |= PMCR_RX_FC_EN; 2822 } 2823 2824 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, 0) >= 0) { 2825 switch (speed) { 2826 case SPEED_1000: 2827 mcr |= PMCR_FORCE_EEE1G; 2828 break; 2829 case SPEED_100: 2830 mcr |= PMCR_FORCE_EEE100; 2831 break; 2832 } 2833 } 2834 2835 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2836 } 2837 2838 static int 2839 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2840 { 2841 struct mt7530_priv *priv = ds->priv; 2842 phy_interface_t interface; 2843 int speed; 2844 int ret; 2845 2846 switch (port) { 2847 case 5: 2848 if (mt7531_is_rgmii_port(priv, port)) 2849 interface = PHY_INTERFACE_MODE_RGMII; 2850 else 2851 interface = PHY_INTERFACE_MODE_2500BASEX; 2852 2853 priv->p5_interface = interface; 2854 break; 2855 case 6: 2856 interface = PHY_INTERFACE_MODE_2500BASEX; 2857 2858 mt7531_pad_setup(ds, interface); 2859 2860 priv->p6_interface = interface; 2861 break; 2862 default: 2863 return -EINVAL; 2864 } 2865 2866 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2867 speed = SPEED_2500; 2868 else 2869 speed = SPEED_1000; 2870 2871 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2872 if (ret) 2873 return ret; 2874 mt7530_write(priv, MT7530_PMCR_P(port), 2875 PMCR_CPU_PORT_SETTING(priv->id)); 2876 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2877 speed, DUPLEX_FULL, true, true); 2878 2879 return 0; 2880 } 2881 2882 static void 2883 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2884 unsigned long *supported) 2885 { 2886 if (port == 5) 2887 phylink_set(supported, 1000baseX_Full); 2888 } 2889 2890 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2891 unsigned long *supported) 2892 { 2893 struct mt7530_priv *priv = ds->priv; 2894 2895 mt7531_sgmii_validate(priv, port, supported); 2896 } 2897 2898 static void 2899 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2900 unsigned long *supported, 2901 struct phylink_link_state *state) 2902 { 2903 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2904 struct mt7530_priv *priv = ds->priv; 2905 2906 if (state->interface != PHY_INTERFACE_MODE_NA && 2907 !mt753x_phy_mode_supported(ds, port, state)) { 2908 linkmode_zero(supported); 2909 return; 2910 } 2911 2912 phylink_set_port_modes(mask); 2913 2914 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2915 !phy_interface_mode_is_8023z(state->interface)) { 2916 phylink_set(mask, 10baseT_Half); 2917 phylink_set(mask, 10baseT_Full); 2918 phylink_set(mask, 100baseT_Half); 2919 phylink_set(mask, 100baseT_Full); 2920 phylink_set(mask, Autoneg); 2921 } 2922 2923 /* This switch only supports 1G full-duplex. */ 2924 if (state->interface != PHY_INTERFACE_MODE_MII) 2925 phylink_set(mask, 1000baseT_Full); 2926 2927 priv->info->mac_port_validate(ds, port, mask); 2928 2929 phylink_set(mask, Pause); 2930 phylink_set(mask, Asym_Pause); 2931 2932 linkmode_and(supported, supported, mask); 2933 linkmode_and(state->advertising, state->advertising, mask); 2934 2935 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2936 * to advertise both, only report advertising at 2500BaseX. 2937 */ 2938 phylink_helper_basex_speed(state); 2939 } 2940 2941 static int 2942 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2943 struct phylink_link_state *state) 2944 { 2945 struct mt7530_priv *priv = ds->priv; 2946 u32 pmsr; 2947 2948 if (port < 0 || port >= MT7530_NUM_PORTS) 2949 return -EINVAL; 2950 2951 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2952 2953 state->link = (pmsr & PMSR_LINK); 2954 state->an_complete = state->link; 2955 state->duplex = !!(pmsr & PMSR_DPX); 2956 2957 switch (pmsr & PMSR_SPEED_MASK) { 2958 case PMSR_SPEED_10: 2959 state->speed = SPEED_10; 2960 break; 2961 case PMSR_SPEED_100: 2962 state->speed = SPEED_100; 2963 break; 2964 case PMSR_SPEED_1000: 2965 state->speed = SPEED_1000; 2966 break; 2967 default: 2968 state->speed = SPEED_UNKNOWN; 2969 break; 2970 } 2971 2972 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2973 if (pmsr & PMSR_RX_FC) 2974 state->pause |= MLO_PAUSE_RX; 2975 if (pmsr & PMSR_TX_FC) 2976 state->pause |= MLO_PAUSE_TX; 2977 2978 return 1; 2979 } 2980 2981 static int 2982 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2983 struct phylink_link_state *state) 2984 { 2985 u32 status, val; 2986 u16 config_reg; 2987 2988 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2989 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2990 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2991 (status & MT7531_SGMII_AN_ENABLE)) { 2992 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2993 config_reg = val >> 16; 2994 2995 switch (config_reg & LPA_SGMII_SPD_MASK) { 2996 case LPA_SGMII_1000: 2997 state->speed = SPEED_1000; 2998 break; 2999 case LPA_SGMII_100: 3000 state->speed = SPEED_100; 3001 break; 3002 case LPA_SGMII_10: 3003 state->speed = SPEED_10; 3004 break; 3005 default: 3006 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 3007 state->link = false; 3008 return -EINVAL; 3009 } 3010 3011 if (config_reg & LPA_SGMII_FULL_DUPLEX) 3012 state->duplex = DUPLEX_FULL; 3013 else 3014 state->duplex = DUPLEX_HALF; 3015 } 3016 3017 return 0; 3018 } 3019 3020 static int 3021 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 3022 struct phylink_link_state *state) 3023 { 3024 struct mt7530_priv *priv = ds->priv; 3025 3026 if (state->interface == PHY_INTERFACE_MODE_SGMII) 3027 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 3028 3029 return -EOPNOTSUPP; 3030 } 3031 3032 static int 3033 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 3034 struct phylink_link_state *state) 3035 { 3036 struct mt7530_priv *priv = ds->priv; 3037 3038 return priv->info->mac_port_get_state(ds, port, state); 3039 } 3040 3041 static int 3042 mt753x_setup(struct dsa_switch *ds) 3043 { 3044 struct mt7530_priv *priv = ds->priv; 3045 int ret = priv->info->sw_setup(ds); 3046 3047 if (ret) 3048 return ret; 3049 3050 ret = mt7530_setup_irq(priv); 3051 if (ret) 3052 return ret; 3053 3054 ret = mt7530_setup_mdio(priv); 3055 if (ret && priv->irq) 3056 mt7530_free_irq_common(priv); 3057 3058 return ret; 3059 } 3060 3061 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3062 struct ethtool_eee *e) 3063 { 3064 struct mt7530_priv *priv = ds->priv; 3065 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3066 3067 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3068 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3069 3070 return 0; 3071 } 3072 3073 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3074 struct ethtool_eee *e) 3075 { 3076 struct mt7530_priv *priv = ds->priv; 3077 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3078 3079 if (e->tx_lpi_timer > 0xFFF) 3080 return -EINVAL; 3081 3082 set = SET_LPI_THRESH(e->tx_lpi_timer); 3083 if (!e->tx_lpi_enabled) 3084 /* Force LPI Mode without a delay */ 3085 set |= LPI_MODE_EN; 3086 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3087 3088 return 0; 3089 } 3090 3091 static const struct dsa_switch_ops mt7530_switch_ops = { 3092 .get_tag_protocol = mtk_get_tag_protocol, 3093 .setup = mt753x_setup, 3094 .get_strings = mt7530_get_strings, 3095 .get_ethtool_stats = mt7530_get_ethtool_stats, 3096 .get_sset_count = mt7530_get_sset_count, 3097 .set_ageing_time = mt7530_set_ageing_time, 3098 .port_enable = mt7530_port_enable, 3099 .port_disable = mt7530_port_disable, 3100 .port_change_mtu = mt7530_port_change_mtu, 3101 .port_max_mtu = mt7530_port_max_mtu, 3102 .port_stp_state_set = mt7530_stp_state_set, 3103 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3104 .port_bridge_flags = mt7530_port_bridge_flags, 3105 .port_bridge_join = mt7530_port_bridge_join, 3106 .port_bridge_leave = mt7530_port_bridge_leave, 3107 .port_fdb_add = mt7530_port_fdb_add, 3108 .port_fdb_del = mt7530_port_fdb_del, 3109 .port_fdb_dump = mt7530_port_fdb_dump, 3110 .port_mdb_add = mt7530_port_mdb_add, 3111 .port_mdb_del = mt7530_port_mdb_del, 3112 .port_vlan_filtering = mt7530_port_vlan_filtering, 3113 .port_vlan_add = mt7530_port_vlan_add, 3114 .port_vlan_del = mt7530_port_vlan_del, 3115 .port_mirror_add = mt753x_port_mirror_add, 3116 .port_mirror_del = mt753x_port_mirror_del, 3117 .phylink_validate = mt753x_phylink_validate, 3118 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 3119 .phylink_mac_config = mt753x_phylink_mac_config, 3120 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 3121 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3122 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3123 .get_mac_eee = mt753x_get_mac_eee, 3124 .set_mac_eee = mt753x_set_mac_eee, 3125 }; 3126 3127 static const struct mt753x_info mt753x_table[] = { 3128 [ID_MT7621] = { 3129 .id = ID_MT7621, 3130 .sw_setup = mt7530_setup, 3131 .phy_read = mt7530_phy_read, 3132 .phy_write = mt7530_phy_write, 3133 .pad_setup = mt7530_pad_clk_setup, 3134 .phy_mode_supported = mt7530_phy_mode_supported, 3135 .mac_port_validate = mt7530_mac_port_validate, 3136 .mac_port_get_state = mt7530_phylink_mac_link_state, 3137 .mac_port_config = mt7530_mac_config, 3138 }, 3139 [ID_MT7530] = { 3140 .id = ID_MT7530, 3141 .sw_setup = mt7530_setup, 3142 .phy_read = mt7530_phy_read, 3143 .phy_write = mt7530_phy_write, 3144 .pad_setup = mt7530_pad_clk_setup, 3145 .phy_mode_supported = mt7530_phy_mode_supported, 3146 .mac_port_validate = mt7530_mac_port_validate, 3147 .mac_port_get_state = mt7530_phylink_mac_link_state, 3148 .mac_port_config = mt7530_mac_config, 3149 }, 3150 [ID_MT7531] = { 3151 .id = ID_MT7531, 3152 .sw_setup = mt7531_setup, 3153 .phy_read = mt7531_ind_phy_read, 3154 .phy_write = mt7531_ind_phy_write, 3155 .pad_setup = mt7531_pad_setup, 3156 .cpu_port_config = mt7531_cpu_port_config, 3157 .phy_mode_supported = mt7531_phy_mode_supported, 3158 .mac_port_validate = mt7531_mac_port_validate, 3159 .mac_port_get_state = mt7531_phylink_mac_link_state, 3160 .mac_port_config = mt7531_mac_config, 3161 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 3162 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 3163 }, 3164 }; 3165 3166 static const struct of_device_id mt7530_of_match[] = { 3167 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 3168 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 3169 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 3170 { /* sentinel */ }, 3171 }; 3172 MODULE_DEVICE_TABLE(of, mt7530_of_match); 3173 3174 static int 3175 mt7530_probe(struct mdio_device *mdiodev) 3176 { 3177 struct mt7530_priv *priv; 3178 struct device_node *dn; 3179 3180 dn = mdiodev->dev.of_node; 3181 3182 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 3183 if (!priv) 3184 return -ENOMEM; 3185 3186 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 3187 if (!priv->ds) 3188 return -ENOMEM; 3189 3190 priv->ds->dev = &mdiodev->dev; 3191 priv->ds->num_ports = DSA_MAX_PORTS; 3192 3193 /* Use medatek,mcm property to distinguish hardware type that would 3194 * casues a little bit differences on power-on sequence. 3195 */ 3196 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 3197 if (priv->mcm) { 3198 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 3199 3200 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 3201 if (IS_ERR(priv->rstc)) { 3202 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3203 return PTR_ERR(priv->rstc); 3204 } 3205 } 3206 3207 /* Get the hardware identifier from the devicetree node. 3208 * We will need it for some of the clock and regulator setup. 3209 */ 3210 priv->info = of_device_get_match_data(&mdiodev->dev); 3211 if (!priv->info) 3212 return -EINVAL; 3213 3214 /* Sanity check if these required device operations are filled 3215 * properly. 3216 */ 3217 if (!priv->info->sw_setup || !priv->info->pad_setup || 3218 !priv->info->phy_read || !priv->info->phy_write || 3219 !priv->info->phy_mode_supported || 3220 !priv->info->mac_port_validate || 3221 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 3222 return -EINVAL; 3223 3224 priv->id = priv->info->id; 3225 3226 if (priv->id == ID_MT7530) { 3227 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 3228 if (IS_ERR(priv->core_pwr)) 3229 return PTR_ERR(priv->core_pwr); 3230 3231 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 3232 if (IS_ERR(priv->io_pwr)) 3233 return PTR_ERR(priv->io_pwr); 3234 } 3235 3236 /* Not MCM that indicates switch works as the remote standalone 3237 * integrated circuit so the GPIO pin would be used to complete 3238 * the reset, otherwise memory-mapped register accessing used 3239 * through syscon provides in the case of MCM. 3240 */ 3241 if (!priv->mcm) { 3242 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 3243 GPIOD_OUT_LOW); 3244 if (IS_ERR(priv->reset)) { 3245 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 3246 return PTR_ERR(priv->reset); 3247 } 3248 } 3249 3250 priv->bus = mdiodev->bus; 3251 priv->dev = &mdiodev->dev; 3252 priv->ds->priv = priv; 3253 priv->ds->ops = &mt7530_switch_ops; 3254 mutex_init(&priv->reg_mutex); 3255 dev_set_drvdata(&mdiodev->dev, priv); 3256 3257 return dsa_register_switch(priv->ds); 3258 } 3259 3260 static void 3261 mt7530_remove(struct mdio_device *mdiodev) 3262 { 3263 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 3264 int ret = 0; 3265 3266 ret = regulator_disable(priv->core_pwr); 3267 if (ret < 0) 3268 dev_err(priv->dev, 3269 "Failed to disable core power: %d\n", ret); 3270 3271 ret = regulator_disable(priv->io_pwr); 3272 if (ret < 0) 3273 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 3274 ret); 3275 3276 if (priv->irq) 3277 mt7530_free_irq(priv); 3278 3279 dsa_unregister_switch(priv->ds); 3280 mutex_destroy(&priv->reg_mutex); 3281 } 3282 3283 static struct mdio_driver mt7530_mdio_driver = { 3284 .probe = mt7530_probe, 3285 .remove = mt7530_remove, 3286 .mdiodrv.driver = { 3287 .name = "mt7530", 3288 .of_match_table = mt7530_of_match, 3289 }, 3290 }; 3291 3292 mdio_module_driver(mt7530_mdio_driver); 3293 3294 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3295 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3296 MODULE_LICENSE("GPL"); 3297