1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_net.h> 15 #include <linux/of_platform.h> 16 #include <linux/phylink.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/gpio/driver.h> 22 #include <net/dsa.h> 23 24 #include "mt7530.h" 25 26 /* String, offset, and register size in bytes if different from 4 bytes */ 27 static const struct mt7530_mib_desc mt7530_mib[] = { 28 MIB_DESC(1, 0x00, "TxDrop"), 29 MIB_DESC(1, 0x04, "TxCrcErr"), 30 MIB_DESC(1, 0x08, "TxUnicast"), 31 MIB_DESC(1, 0x0c, "TxMulticast"), 32 MIB_DESC(1, 0x10, "TxBroadcast"), 33 MIB_DESC(1, 0x14, "TxCollision"), 34 MIB_DESC(1, 0x18, "TxSingleCollision"), 35 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 36 MIB_DESC(1, 0x20, "TxDeferred"), 37 MIB_DESC(1, 0x24, "TxLateCollision"), 38 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 39 MIB_DESC(1, 0x2c, "TxPause"), 40 MIB_DESC(1, 0x30, "TxPktSz64"), 41 MIB_DESC(1, 0x34, "TxPktSz65To127"), 42 MIB_DESC(1, 0x38, "TxPktSz128To255"), 43 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 44 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 45 MIB_DESC(1, 0x44, "Tx1024ToMax"), 46 MIB_DESC(2, 0x48, "TxBytes"), 47 MIB_DESC(1, 0x60, "RxDrop"), 48 MIB_DESC(1, 0x64, "RxFiltering"), 49 MIB_DESC(1, 0x6c, "RxMulticast"), 50 MIB_DESC(1, 0x70, "RxBroadcast"), 51 MIB_DESC(1, 0x74, "RxAlignErr"), 52 MIB_DESC(1, 0x78, "RxCrcErr"), 53 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 54 MIB_DESC(1, 0x80, "RxFragErr"), 55 MIB_DESC(1, 0x84, "RxOverSzErr"), 56 MIB_DESC(1, 0x88, "RxJabberErr"), 57 MIB_DESC(1, 0x8c, "RxPause"), 58 MIB_DESC(1, 0x90, "RxPktSz64"), 59 MIB_DESC(1, 0x94, "RxPktSz65To127"), 60 MIB_DESC(1, 0x98, "RxPktSz128To255"), 61 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 62 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 63 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 64 MIB_DESC(2, 0xa8, "RxBytes"), 65 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 66 MIB_DESC(1, 0xb4, "RxIngressDrop"), 67 MIB_DESC(1, 0xb8, "RxArlDrop"), 68 }; 69 70 static int 71 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 72 { 73 struct mii_bus *bus = priv->bus; 74 int value, ret; 75 76 /* Write the desired MMD Devad */ 77 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 78 if (ret < 0) 79 goto err; 80 81 /* Write the desired MMD register address */ 82 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 83 if (ret < 0) 84 goto err; 85 86 /* Select the Function : DATA with no post increment */ 87 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 88 if (ret < 0) 89 goto err; 90 91 /* Read the content of the MMD's selected register */ 92 value = bus->read(bus, 0, MII_MMD_DATA); 93 94 return value; 95 err: 96 dev_err(&bus->dev, "failed to read mmd register\n"); 97 98 return ret; 99 } 100 101 static int 102 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 103 int devad, u32 data) 104 { 105 struct mii_bus *bus = priv->bus; 106 int ret; 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 110 if (ret < 0) 111 goto err; 112 113 /* Write the desired MMD register address */ 114 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 115 if (ret < 0) 116 goto err; 117 118 /* Select the Function : DATA with no post increment */ 119 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 120 if (ret < 0) 121 goto err; 122 123 /* Write the data into MMD's selected register */ 124 ret = bus->write(bus, 0, MII_MMD_DATA, data); 125 err: 126 if (ret < 0) 127 dev_err(&bus->dev, 128 "failed to write mmd register\n"); 129 return ret; 130 } 131 132 static void 133 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 134 { 135 struct mii_bus *bus = priv->bus; 136 137 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 138 139 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 140 141 mutex_unlock(&bus->mdio_lock); 142 } 143 144 static void 145 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 146 { 147 struct mii_bus *bus = priv->bus; 148 u32 val; 149 150 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 151 152 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 153 val &= ~mask; 154 val |= set; 155 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 156 157 mutex_unlock(&bus->mdio_lock); 158 } 159 160 static void 161 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 162 { 163 core_rmw(priv, reg, 0, val); 164 } 165 166 static void 167 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 168 { 169 core_rmw(priv, reg, val, 0); 170 } 171 172 static int 173 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 struct mii_bus *bus = priv->bus; 176 u16 page, r, lo, hi; 177 int ret; 178 179 page = (reg >> 6) & 0x3ff; 180 r = (reg >> 2) & 0xf; 181 lo = val & 0xffff; 182 hi = val >> 16; 183 184 /* MT7530 uses 31 as the pseudo port */ 185 ret = bus->write(bus, 0x1f, 0x1f, page); 186 if (ret < 0) 187 goto err; 188 189 ret = bus->write(bus, 0x1f, r, lo); 190 if (ret < 0) 191 goto err; 192 193 ret = bus->write(bus, 0x1f, 0x10, hi); 194 err: 195 if (ret < 0) 196 dev_err(&bus->dev, 197 "failed to write mt7530 register\n"); 198 return ret; 199 } 200 201 static u32 202 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 203 { 204 struct mii_bus *bus = priv->bus; 205 u16 page, r, lo, hi; 206 int ret; 207 208 page = (reg >> 6) & 0x3ff; 209 r = (reg >> 2) & 0xf; 210 211 /* MT7530 uses 31 as the pseudo port */ 212 ret = bus->write(bus, 0x1f, 0x1f, page); 213 if (ret < 0) { 214 dev_err(&bus->dev, 215 "failed to read mt7530 register\n"); 216 return ret; 217 } 218 219 lo = bus->read(bus, 0x1f, r); 220 hi = bus->read(bus, 0x1f, 0x10); 221 222 return (hi << 16) | (lo & 0xffff); 223 } 224 225 static void 226 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 227 { 228 struct mii_bus *bus = priv->bus; 229 230 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 231 232 mt7530_mii_write(priv, reg, val); 233 234 mutex_unlock(&bus->mdio_lock); 235 } 236 237 static u32 238 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 239 { 240 return mt7530_mii_read(p->priv, p->reg); 241 } 242 243 static u32 244 _mt7530_read(struct mt7530_dummy_poll *p) 245 { 246 struct mii_bus *bus = p->priv->bus; 247 u32 val; 248 249 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 250 251 val = mt7530_mii_read(p->priv, p->reg); 252 253 mutex_unlock(&bus->mdio_lock); 254 255 return val; 256 } 257 258 static u32 259 mt7530_read(struct mt7530_priv *priv, u32 reg) 260 { 261 struct mt7530_dummy_poll p; 262 263 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 264 return _mt7530_read(&p); 265 } 266 267 static void 268 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 269 u32 mask, u32 set) 270 { 271 struct mii_bus *bus = priv->bus; 272 u32 val; 273 274 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 275 276 val = mt7530_mii_read(priv, reg); 277 val &= ~mask; 278 val |= set; 279 mt7530_mii_write(priv, reg, val); 280 281 mutex_unlock(&bus->mdio_lock); 282 } 283 284 static void 285 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 286 { 287 mt7530_rmw(priv, reg, 0, val); 288 } 289 290 static void 291 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 292 { 293 mt7530_rmw(priv, reg, val, 0); 294 } 295 296 static int 297 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 298 { 299 u32 val; 300 int ret; 301 struct mt7530_dummy_poll p; 302 303 /* Set the command operating upon the MAC address entries */ 304 val = ATC_BUSY | ATC_MAT(0) | cmd; 305 mt7530_write(priv, MT7530_ATC, val); 306 307 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 308 ret = readx_poll_timeout(_mt7530_read, &p, val, 309 !(val & ATC_BUSY), 20, 20000); 310 if (ret < 0) { 311 dev_err(priv->dev, "reset timeout\n"); 312 return ret; 313 } 314 315 /* Additional sanity for read command if the specified 316 * entry is invalid 317 */ 318 val = mt7530_read(priv, MT7530_ATC); 319 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 320 return -EINVAL; 321 322 if (rsp) 323 *rsp = val; 324 325 return 0; 326 } 327 328 static void 329 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 330 { 331 u32 reg[3]; 332 int i; 333 334 /* Read from ARL table into an array */ 335 for (i = 0; i < 3; i++) { 336 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 337 338 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 339 __func__, __LINE__, i, reg[i]); 340 } 341 342 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 343 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 344 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 345 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 346 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 347 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 348 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 349 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 350 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 351 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 352 } 353 354 static void 355 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 356 u8 port_mask, const u8 *mac, 357 u8 aging, u8 type) 358 { 359 u32 reg[3] = { 0 }; 360 int i; 361 362 reg[1] |= vid & CVID_MASK; 363 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 364 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 365 /* STATIC_ENT indicate that entry is static wouldn't 366 * be aged out and STATIC_EMP specified as erasing an 367 * entry 368 */ 369 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 370 reg[1] |= mac[5] << MAC_BYTE_5; 371 reg[1] |= mac[4] << MAC_BYTE_4; 372 reg[0] |= mac[3] << MAC_BYTE_3; 373 reg[0] |= mac[2] << MAC_BYTE_2; 374 reg[0] |= mac[1] << MAC_BYTE_1; 375 reg[0] |= mac[0] << MAC_BYTE_0; 376 377 /* Write array into the ARL table */ 378 for (i = 0; i < 3; i++) 379 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 380 } 381 382 /* Setup TX circuit including relevant PAD and driving */ 383 static int 384 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 385 { 386 struct mt7530_priv *priv = ds->priv; 387 u32 ncpo1, ssc_delta, trgint, i, xtal; 388 389 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 390 391 if (xtal == HWTRAP_XTAL_20MHZ) { 392 dev_err(priv->dev, 393 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 394 __func__); 395 return -EINVAL; 396 } 397 398 switch (interface) { 399 case PHY_INTERFACE_MODE_RGMII: 400 trgint = 0; 401 /* PLL frequency: 125MHz */ 402 ncpo1 = 0x0c80; 403 break; 404 case PHY_INTERFACE_MODE_TRGMII: 405 trgint = 1; 406 if (priv->id == ID_MT7621) { 407 /* PLL frequency: 150MHz: 1.2GBit */ 408 if (xtal == HWTRAP_XTAL_40MHZ) 409 ncpo1 = 0x0780; 410 if (xtal == HWTRAP_XTAL_25MHZ) 411 ncpo1 = 0x0a00; 412 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 413 if (xtal == HWTRAP_XTAL_40MHZ) 414 ncpo1 = 0x0c80; 415 if (xtal == HWTRAP_XTAL_25MHZ) 416 ncpo1 = 0x1400; 417 } 418 break; 419 default: 420 dev_err(priv->dev, "xMII interface %d not supported\n", 421 interface); 422 return -EINVAL; 423 } 424 425 if (xtal == HWTRAP_XTAL_25MHZ) 426 ssc_delta = 0x57; 427 else 428 ssc_delta = 0x87; 429 430 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 431 P6_INTF_MODE(trgint)); 432 433 /* Lower Tx Driving for TRGMII path */ 434 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 435 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 436 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 437 438 /* Setup core clock for MT7530 */ 439 /* Disable MT7530 core clock */ 440 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 441 442 /* Disable PLL, since phy_device has not yet been created 443 * provided for phy_[read,write]_mmd_indirect is called, we 444 * provide our own core_write_mmd_indirect to complete this 445 * function. 446 */ 447 core_write_mmd_indirect(priv, 448 CORE_GSWPLL_GRP1, 449 MDIO_MMD_VEND2, 450 0); 451 452 /* Set core clock into 500Mhz */ 453 core_write(priv, CORE_GSWPLL_GRP2, 454 RG_GSWPLL_POSDIV_500M(1) | 455 RG_GSWPLL_FBKDIV_500M(25)); 456 457 /* Enable PLL */ 458 core_write(priv, CORE_GSWPLL_GRP1, 459 RG_GSWPLL_EN_PRE | 460 RG_GSWPLL_POSDIV_200M(2) | 461 RG_GSWPLL_FBKDIV_200M(32)); 462 463 /* Enable MT7530 core clock */ 464 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 465 466 /* Setup the MT7530 TRGMII Tx Clock */ 467 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 468 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 469 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 470 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 471 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 472 core_write(priv, CORE_PLL_GROUP4, 473 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 474 RG_SYSPLL_BIAS_LPF_EN); 475 core_write(priv, CORE_PLL_GROUP2, 476 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 477 RG_SYSPLL_POSDIV(1)); 478 core_write(priv, CORE_PLL_GROUP7, 479 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 480 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 481 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 482 REG_GSWCK_EN | REG_TRGMIICK_EN); 483 484 if (!trgint) 485 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 486 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 487 RD_TAP_MASK, RD_TAP(16)); 488 return 0; 489 } 490 491 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 492 { 493 u32 val; 494 495 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 496 497 return (val & PAD_DUAL_SGMII_EN) != 0; 498 } 499 500 static int 501 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 502 { 503 struct mt7530_priv *priv = ds->priv; 504 u32 top_sig; 505 u32 hwstrap; 506 u32 xtal; 507 u32 val; 508 509 if (mt7531_dual_sgmii_supported(priv)) 510 return 0; 511 512 val = mt7530_read(priv, MT7531_CREV); 513 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 514 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 515 if ((val & CHIP_REV_M) > 0) 516 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 517 HWTRAP_XTAL_FSEL_25MHZ; 518 else 519 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 520 521 /* Step 1 : Disable MT7531 COREPLL */ 522 val = mt7530_read(priv, MT7531_PLLGP_EN); 523 val &= ~EN_COREPLL; 524 mt7530_write(priv, MT7531_PLLGP_EN, val); 525 526 /* Step 2: switch to XTAL output */ 527 val = mt7530_read(priv, MT7531_PLLGP_EN); 528 val |= SW_CLKSW; 529 mt7530_write(priv, MT7531_PLLGP_EN, val); 530 531 val = mt7530_read(priv, MT7531_PLLGP_CR0); 532 val &= ~RG_COREPLL_EN; 533 mt7530_write(priv, MT7531_PLLGP_CR0, val); 534 535 /* Step 3: disable PLLGP and enable program PLLGP */ 536 val = mt7530_read(priv, MT7531_PLLGP_EN); 537 val |= SW_PLLGP; 538 mt7530_write(priv, MT7531_PLLGP_EN, val); 539 540 /* Step 4: program COREPLL output frequency to 500MHz */ 541 val = mt7530_read(priv, MT7531_PLLGP_CR0); 542 val &= ~RG_COREPLL_POSDIV_M; 543 val |= 2 << RG_COREPLL_POSDIV_S; 544 mt7530_write(priv, MT7531_PLLGP_CR0, val); 545 usleep_range(25, 35); 546 547 switch (xtal) { 548 case HWTRAP_XTAL_FSEL_25MHZ: 549 val = mt7530_read(priv, MT7531_PLLGP_CR0); 550 val &= ~RG_COREPLL_SDM_PCW_M; 551 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 552 mt7530_write(priv, MT7531_PLLGP_CR0, val); 553 break; 554 case HWTRAP_XTAL_FSEL_40MHZ: 555 val = mt7530_read(priv, MT7531_PLLGP_CR0); 556 val &= ~RG_COREPLL_SDM_PCW_M; 557 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 558 mt7530_write(priv, MT7531_PLLGP_CR0, val); 559 break; 560 } 561 562 /* Set feedback divide ratio update signal to high */ 563 val = mt7530_read(priv, MT7531_PLLGP_CR0); 564 val |= RG_COREPLL_SDM_PCW_CHG; 565 mt7530_write(priv, MT7531_PLLGP_CR0, val); 566 /* Wait for at least 16 XTAL clocks */ 567 usleep_range(10, 20); 568 569 /* Step 5: set feedback divide ratio update signal to low */ 570 val = mt7530_read(priv, MT7531_PLLGP_CR0); 571 val &= ~RG_COREPLL_SDM_PCW_CHG; 572 mt7530_write(priv, MT7531_PLLGP_CR0, val); 573 574 /* Enable 325M clock for SGMII */ 575 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 576 577 /* Enable 250SSC clock for RGMII */ 578 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 579 580 /* Step 6: Enable MT7531 PLL */ 581 val = mt7530_read(priv, MT7531_PLLGP_CR0); 582 val |= RG_COREPLL_EN; 583 mt7530_write(priv, MT7531_PLLGP_CR0, val); 584 585 val = mt7530_read(priv, MT7531_PLLGP_EN); 586 val |= EN_COREPLL; 587 mt7530_write(priv, MT7531_PLLGP_EN, val); 588 usleep_range(25, 35); 589 590 return 0; 591 } 592 593 static void 594 mt7530_mib_reset(struct dsa_switch *ds) 595 { 596 struct mt7530_priv *priv = ds->priv; 597 598 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 599 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 600 } 601 602 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 603 { 604 struct mt7530_priv *priv = ds->priv; 605 606 return mdiobus_read_nested(priv->bus, port, regnum); 607 } 608 609 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 610 u16 val) 611 { 612 struct mt7530_priv *priv = ds->priv; 613 614 return mdiobus_write_nested(priv->bus, port, regnum, val); 615 } 616 617 static int 618 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 619 int regnum) 620 { 621 struct mii_bus *bus = priv->bus; 622 struct mt7530_dummy_poll p; 623 u32 reg, val; 624 int ret; 625 626 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 627 628 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 629 630 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 631 !(val & MT7531_PHY_ACS_ST), 20, 100000); 632 if (ret < 0) { 633 dev_err(priv->dev, "poll timeout\n"); 634 goto out; 635 } 636 637 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 638 MT7531_MDIO_DEV_ADDR(devad) | regnum; 639 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 640 641 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 642 !(val & MT7531_PHY_ACS_ST), 20, 100000); 643 if (ret < 0) { 644 dev_err(priv->dev, "poll timeout\n"); 645 goto out; 646 } 647 648 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 649 MT7531_MDIO_DEV_ADDR(devad); 650 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 651 652 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 653 !(val & MT7531_PHY_ACS_ST), 20, 100000); 654 if (ret < 0) { 655 dev_err(priv->dev, "poll timeout\n"); 656 goto out; 657 } 658 659 ret = val & MT7531_MDIO_RW_DATA_MASK; 660 out: 661 mutex_unlock(&bus->mdio_lock); 662 663 return ret; 664 } 665 666 static int 667 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 668 int regnum, u32 data) 669 { 670 struct mii_bus *bus = priv->bus; 671 struct mt7530_dummy_poll p; 672 u32 val, reg; 673 int ret; 674 675 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 676 677 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 678 679 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 680 !(val & MT7531_PHY_ACS_ST), 20, 100000); 681 if (ret < 0) { 682 dev_err(priv->dev, "poll timeout\n"); 683 goto out; 684 } 685 686 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 687 MT7531_MDIO_DEV_ADDR(devad) | regnum; 688 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 689 690 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 691 !(val & MT7531_PHY_ACS_ST), 20, 100000); 692 if (ret < 0) { 693 dev_err(priv->dev, "poll timeout\n"); 694 goto out; 695 } 696 697 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 698 MT7531_MDIO_DEV_ADDR(devad) | data; 699 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 700 701 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 702 !(val & MT7531_PHY_ACS_ST), 20, 100000); 703 if (ret < 0) { 704 dev_err(priv->dev, "poll timeout\n"); 705 goto out; 706 } 707 708 out: 709 mutex_unlock(&bus->mdio_lock); 710 711 return ret; 712 } 713 714 static int 715 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 716 { 717 struct mii_bus *bus = priv->bus; 718 struct mt7530_dummy_poll p; 719 int ret; 720 u32 val; 721 722 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 723 724 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 725 726 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 727 !(val & MT7531_PHY_ACS_ST), 20, 100000); 728 if (ret < 0) { 729 dev_err(priv->dev, "poll timeout\n"); 730 goto out; 731 } 732 733 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 734 MT7531_MDIO_REG_ADDR(regnum); 735 736 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 737 738 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 739 !(val & MT7531_PHY_ACS_ST), 20, 100000); 740 if (ret < 0) { 741 dev_err(priv->dev, "poll timeout\n"); 742 goto out; 743 } 744 745 ret = val & MT7531_MDIO_RW_DATA_MASK; 746 out: 747 mutex_unlock(&bus->mdio_lock); 748 749 return ret; 750 } 751 752 static int 753 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 754 u16 data) 755 { 756 struct mii_bus *bus = priv->bus; 757 struct mt7530_dummy_poll p; 758 int ret; 759 u32 reg; 760 761 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 762 763 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 764 765 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 766 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 767 if (ret < 0) { 768 dev_err(priv->dev, "poll timeout\n"); 769 goto out; 770 } 771 772 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 773 MT7531_MDIO_REG_ADDR(regnum) | data; 774 775 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 776 777 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 778 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 779 if (ret < 0) { 780 dev_err(priv->dev, "poll timeout\n"); 781 goto out; 782 } 783 784 out: 785 mutex_unlock(&bus->mdio_lock); 786 787 return ret; 788 } 789 790 static int 791 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) 792 { 793 struct mt7530_priv *priv = ds->priv; 794 int devad; 795 int ret; 796 797 if (regnum & MII_ADDR_C45) { 798 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 799 ret = mt7531_ind_c45_phy_read(priv, port, devad, 800 regnum & MII_REGADDR_C45_MASK); 801 } else { 802 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 803 } 804 805 return ret; 806 } 807 808 static int 809 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, 810 u16 data) 811 { 812 struct mt7530_priv *priv = ds->priv; 813 int devad; 814 int ret; 815 816 if (regnum & MII_ADDR_C45) { 817 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 818 ret = mt7531_ind_c45_phy_write(priv, port, devad, 819 regnum & MII_REGADDR_C45_MASK, 820 data); 821 } else { 822 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 823 } 824 825 return ret; 826 } 827 828 static void 829 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 830 uint8_t *data) 831 { 832 int i; 833 834 if (stringset != ETH_SS_STATS) 835 return; 836 837 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 838 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 839 ETH_GSTRING_LEN); 840 } 841 842 static void 843 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 844 uint64_t *data) 845 { 846 struct mt7530_priv *priv = ds->priv; 847 const struct mt7530_mib_desc *mib; 848 u32 reg, i; 849 u64 hi; 850 851 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 852 mib = &mt7530_mib[i]; 853 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 854 855 data[i] = mt7530_read(priv, reg); 856 if (mib->size == 2) { 857 hi = mt7530_read(priv, reg + 4); 858 data[i] |= hi << 32; 859 } 860 } 861 } 862 863 static int 864 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 865 { 866 if (sset != ETH_SS_STATS) 867 return 0; 868 869 return ARRAY_SIZE(mt7530_mib); 870 } 871 872 static int 873 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 874 { 875 struct mt7530_priv *priv = ds->priv; 876 unsigned int secs = msecs / 1000; 877 unsigned int tmp_age_count; 878 unsigned int error = -1; 879 unsigned int age_count; 880 unsigned int age_unit; 881 882 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 883 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 884 return -ERANGE; 885 886 /* iterate through all possible age_count to find the closest pair */ 887 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 888 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 889 890 if (tmp_age_unit <= AGE_UNIT_MAX) { 891 unsigned int tmp_error = secs - 892 (tmp_age_count + 1) * (tmp_age_unit + 1); 893 894 /* found a closer pair */ 895 if (error > tmp_error) { 896 error = tmp_error; 897 age_count = tmp_age_count; 898 age_unit = tmp_age_unit; 899 } 900 901 /* found the exact match, so break the loop */ 902 if (!error) 903 break; 904 } 905 } 906 907 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 908 909 return 0; 910 } 911 912 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 913 { 914 struct mt7530_priv *priv = ds->priv; 915 u8 tx_delay = 0; 916 int val; 917 918 mutex_lock(&priv->reg_mutex); 919 920 val = mt7530_read(priv, MT7530_MHWTRAP); 921 922 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 923 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 924 925 switch (priv->p5_intf_sel) { 926 case P5_INTF_SEL_PHY_P0: 927 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 928 val |= MHWTRAP_PHY0_SEL; 929 fallthrough; 930 case P5_INTF_SEL_PHY_P4: 931 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 932 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 933 934 /* Setup the MAC by default for the cpu port */ 935 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 936 break; 937 case P5_INTF_SEL_GMAC5: 938 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 939 val &= ~MHWTRAP_P5_DIS; 940 break; 941 case P5_DISABLED: 942 interface = PHY_INTERFACE_MODE_NA; 943 break; 944 default: 945 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 946 priv->p5_intf_sel); 947 goto unlock_exit; 948 } 949 950 /* Setup RGMII settings */ 951 if (phy_interface_mode_is_rgmii(interface)) { 952 val |= MHWTRAP_P5_RGMII_MODE; 953 954 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 955 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 956 957 /* Don't set delay in DSA mode */ 958 if (!dsa_is_dsa_port(priv->ds, 5) && 959 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 960 interface == PHY_INTERFACE_MODE_RGMII_ID)) 961 tx_delay = 4; /* n * 0.5 ns */ 962 963 /* P5 RGMII TX Clock Control: delay x */ 964 mt7530_write(priv, MT7530_P5RGMIITXCR, 965 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 966 967 /* reduce P5 RGMII Tx driving, 8mA */ 968 mt7530_write(priv, MT7530_IO_DRV_CR, 969 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 970 } 971 972 mt7530_write(priv, MT7530_MHWTRAP, val); 973 974 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 975 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 976 977 priv->p5_interface = interface; 978 979 unlock_exit: 980 mutex_unlock(&priv->reg_mutex); 981 } 982 983 static int 984 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 985 { 986 struct mt7530_priv *priv = ds->priv; 987 int ret; 988 989 /* Setup max capability of CPU port at first */ 990 if (priv->info->cpu_port_config) { 991 ret = priv->info->cpu_port_config(ds, port); 992 if (ret) 993 return ret; 994 } 995 996 /* Enable Mediatek header mode on the cpu port */ 997 mt7530_write(priv, MT7530_PVC_P(port), 998 PORT_SPEC_TAG); 999 1000 /* Unknown multicast frame forwarding to the cpu port */ 1001 mt7530_rmw(priv, MT7530_MFC, UNM_FFP_MASK, UNM_FFP(BIT(port))); 1002 1003 /* Set CPU port number */ 1004 if (priv->id == ID_MT7621) 1005 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1006 1007 /* CPU port gets connected to all user ports of 1008 * the switch. 1009 */ 1010 mt7530_write(priv, MT7530_PCR_P(port), 1011 PCR_MATRIX(dsa_user_ports(priv->ds))); 1012 1013 return 0; 1014 } 1015 1016 static int 1017 mt7530_port_enable(struct dsa_switch *ds, int port, 1018 struct phy_device *phy) 1019 { 1020 struct mt7530_priv *priv = ds->priv; 1021 1022 if (!dsa_is_user_port(ds, port)) 1023 return 0; 1024 1025 mutex_lock(&priv->reg_mutex); 1026 1027 /* Allow the user port gets connected to the cpu port and also 1028 * restore the port matrix if the port is the member of a certain 1029 * bridge. 1030 */ 1031 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1032 priv->ports[port].enable = true; 1033 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1034 priv->ports[port].pm); 1035 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1036 1037 mutex_unlock(&priv->reg_mutex); 1038 1039 return 0; 1040 } 1041 1042 static void 1043 mt7530_port_disable(struct dsa_switch *ds, int port) 1044 { 1045 struct mt7530_priv *priv = ds->priv; 1046 1047 if (!dsa_is_user_port(ds, port)) 1048 return; 1049 1050 mutex_lock(&priv->reg_mutex); 1051 1052 /* Clear up all port matrix which could be restored in the next 1053 * enablement for the port. 1054 */ 1055 priv->ports[port].enable = false; 1056 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1057 PCR_MATRIX_CLR); 1058 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1059 1060 mutex_unlock(&priv->reg_mutex); 1061 } 1062 1063 static int 1064 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1065 { 1066 struct mt7530_priv *priv = ds->priv; 1067 struct mii_bus *bus = priv->bus; 1068 int length; 1069 u32 val; 1070 1071 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1072 * largest MTU of the slave ports. Because the switch only has a global 1073 * RX length register, only allowing CPU port here is enough. 1074 */ 1075 if (!dsa_is_cpu_port(ds, port)) 1076 return 0; 1077 1078 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1079 1080 val = mt7530_mii_read(priv, MT7530_GMACCR); 1081 val &= ~MAX_RX_PKT_LEN_MASK; 1082 1083 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1084 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1085 if (length <= 1522) { 1086 val |= MAX_RX_PKT_LEN_1522; 1087 } else if (length <= 1536) { 1088 val |= MAX_RX_PKT_LEN_1536; 1089 } else if (length <= 1552) { 1090 val |= MAX_RX_PKT_LEN_1552; 1091 } else { 1092 val &= ~MAX_RX_JUMBO_MASK; 1093 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1094 val |= MAX_RX_PKT_LEN_JUMBO; 1095 } 1096 1097 mt7530_mii_write(priv, MT7530_GMACCR, val); 1098 1099 mutex_unlock(&bus->mdio_lock); 1100 1101 return 0; 1102 } 1103 1104 static int 1105 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1106 { 1107 return MT7530_MAX_MTU; 1108 } 1109 1110 static void 1111 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1112 { 1113 struct mt7530_priv *priv = ds->priv; 1114 u32 stp_state; 1115 1116 switch (state) { 1117 case BR_STATE_DISABLED: 1118 stp_state = MT7530_STP_DISABLED; 1119 break; 1120 case BR_STATE_BLOCKING: 1121 stp_state = MT7530_STP_BLOCKING; 1122 break; 1123 case BR_STATE_LISTENING: 1124 stp_state = MT7530_STP_LISTENING; 1125 break; 1126 case BR_STATE_LEARNING: 1127 stp_state = MT7530_STP_LEARNING; 1128 break; 1129 case BR_STATE_FORWARDING: 1130 default: 1131 stp_state = MT7530_STP_FORWARDING; 1132 break; 1133 } 1134 1135 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 1136 } 1137 1138 static int 1139 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1140 struct net_device *bridge) 1141 { 1142 struct mt7530_priv *priv = ds->priv; 1143 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1144 int i; 1145 1146 mutex_lock(&priv->reg_mutex); 1147 1148 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1149 /* Add this port to the port matrix of the other ports in the 1150 * same bridge. If the port is disabled, port matrix is kept 1151 * and not being setup until the port becomes enabled. 1152 */ 1153 if (dsa_is_user_port(ds, i) && i != port) { 1154 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1155 continue; 1156 if (priv->ports[i].enable) 1157 mt7530_set(priv, MT7530_PCR_P(i), 1158 PCR_MATRIX(BIT(port))); 1159 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1160 1161 port_bitmap |= BIT(i); 1162 } 1163 } 1164 1165 /* Add the all other ports to this port matrix. */ 1166 if (priv->ports[port].enable) 1167 mt7530_rmw(priv, MT7530_PCR_P(port), 1168 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1169 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1170 1171 mutex_unlock(&priv->reg_mutex); 1172 1173 return 0; 1174 } 1175 1176 static void 1177 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1178 { 1179 struct mt7530_priv *priv = ds->priv; 1180 bool all_user_ports_removed = true; 1181 int i; 1182 1183 /* When a port is removed from the bridge, the port would be set up 1184 * back to the default as is at initial boot which is a VLAN-unaware 1185 * port. 1186 */ 1187 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1188 MT7530_PORT_MATRIX_MODE); 1189 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1190 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1191 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1192 1193 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1194 if (dsa_is_user_port(ds, i) && 1195 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1196 all_user_ports_removed = false; 1197 break; 1198 } 1199 } 1200 1201 /* CPU port also does the same thing until all user ports belonging to 1202 * the CPU port get out of VLAN filtering mode. 1203 */ 1204 if (all_user_ports_removed) { 1205 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1206 PCR_MATRIX(dsa_user_ports(priv->ds))); 1207 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1208 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1209 } 1210 } 1211 1212 static void 1213 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1214 { 1215 struct mt7530_priv *priv = ds->priv; 1216 1217 /* The real fabric path would be decided on the membership in the 1218 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 1219 * means potential VLAN can be consisting of certain subset of all 1220 * ports. 1221 */ 1222 mt7530_rmw(priv, MT7530_PCR_P(port), 1223 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 1224 1225 /* Trapped into security mode allows packet forwarding through VLAN 1226 * table lookup. CPU port is set to fallback mode to let untagged 1227 * frames pass through. 1228 */ 1229 if (dsa_is_cpu_port(ds, port)) 1230 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1231 MT7530_PORT_FALLBACK_MODE); 1232 else 1233 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1234 MT7530_PORT_SECURITY_MODE); 1235 1236 /* Set the port as a user port which is to be able to recognize VID 1237 * from incoming packets before fetching entry within the VLAN table. 1238 */ 1239 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1240 VLAN_ATTR(MT7530_VLAN_USER) | 1241 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1242 } 1243 1244 static void 1245 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1246 struct net_device *bridge) 1247 { 1248 struct mt7530_priv *priv = ds->priv; 1249 int i; 1250 1251 mutex_lock(&priv->reg_mutex); 1252 1253 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1254 /* Remove this port from the port matrix of the other ports 1255 * in the same bridge. If the port is disabled, port matrix 1256 * is kept and not being setup until the port becomes enabled. 1257 * And the other port's port matrix cannot be broken when the 1258 * other port is still a VLAN-aware port. 1259 */ 1260 if (dsa_is_user_port(ds, i) && i != port && 1261 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1262 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1263 continue; 1264 if (priv->ports[i].enable) 1265 mt7530_clear(priv, MT7530_PCR_P(i), 1266 PCR_MATRIX(BIT(port))); 1267 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1268 } 1269 } 1270 1271 /* Set the cpu port to be the only one in the port matrix of 1272 * this port. 1273 */ 1274 if (priv->ports[port].enable) 1275 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1276 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1277 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1278 1279 mutex_unlock(&priv->reg_mutex); 1280 } 1281 1282 static int 1283 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1284 const unsigned char *addr, u16 vid) 1285 { 1286 struct mt7530_priv *priv = ds->priv; 1287 int ret; 1288 u8 port_mask = BIT(port); 1289 1290 mutex_lock(&priv->reg_mutex); 1291 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1292 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1293 mutex_unlock(&priv->reg_mutex); 1294 1295 return ret; 1296 } 1297 1298 static int 1299 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1300 const unsigned char *addr, u16 vid) 1301 { 1302 struct mt7530_priv *priv = ds->priv; 1303 int ret; 1304 u8 port_mask = BIT(port); 1305 1306 mutex_lock(&priv->reg_mutex); 1307 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1308 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1309 mutex_unlock(&priv->reg_mutex); 1310 1311 return ret; 1312 } 1313 1314 static int 1315 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1316 dsa_fdb_dump_cb_t *cb, void *data) 1317 { 1318 struct mt7530_priv *priv = ds->priv; 1319 struct mt7530_fdb _fdb = { 0 }; 1320 int cnt = MT7530_NUM_FDB_RECORDS; 1321 int ret = 0; 1322 u32 rsp = 0; 1323 1324 mutex_lock(&priv->reg_mutex); 1325 1326 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1327 if (ret < 0) 1328 goto err; 1329 1330 do { 1331 if (rsp & ATC_SRCH_HIT) { 1332 mt7530_fdb_read(priv, &_fdb); 1333 if (_fdb.port_mask & BIT(port)) { 1334 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1335 data); 1336 if (ret < 0) 1337 break; 1338 } 1339 } 1340 } while (--cnt && 1341 !(rsp & ATC_SRCH_END) && 1342 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1343 err: 1344 mutex_unlock(&priv->reg_mutex); 1345 1346 return 0; 1347 } 1348 1349 static int 1350 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1351 { 1352 struct mt7530_dummy_poll p; 1353 u32 val; 1354 int ret; 1355 1356 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1357 mt7530_write(priv, MT7530_VTCR, val); 1358 1359 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1360 ret = readx_poll_timeout(_mt7530_read, &p, val, 1361 !(val & VTCR_BUSY), 20, 20000); 1362 if (ret < 0) { 1363 dev_err(priv->dev, "poll timeout\n"); 1364 return ret; 1365 } 1366 1367 val = mt7530_read(priv, MT7530_VTCR); 1368 if (val & VTCR_INVALID) { 1369 dev_err(priv->dev, "read VTCR invalid\n"); 1370 return -EINVAL; 1371 } 1372 1373 return 0; 1374 } 1375 1376 static int 1377 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1378 struct netlink_ext_ack *extack) 1379 { 1380 if (vlan_filtering) { 1381 /* The port is being kept as VLAN-unaware port when bridge is 1382 * set up with vlan_filtering not being set, Otherwise, the 1383 * port and the corresponding CPU port is required the setup 1384 * for becoming a VLAN-aware port. 1385 */ 1386 mt7530_port_set_vlan_aware(ds, port); 1387 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1388 } else { 1389 mt7530_port_set_vlan_unaware(ds, port); 1390 } 1391 1392 return 0; 1393 } 1394 1395 static void 1396 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1397 struct mt7530_hw_vlan_entry *entry) 1398 { 1399 u8 new_members; 1400 u32 val; 1401 1402 new_members = entry->old_members | BIT(entry->port) | 1403 BIT(MT7530_CPU_PORT); 1404 1405 /* Validate the entry with independent learning, create egress tag per 1406 * VLAN and joining the port as one of the port members. 1407 */ 1408 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1409 mt7530_write(priv, MT7530_VAWD1, val); 1410 1411 /* Decide whether adding tag or not for those outgoing packets from the 1412 * port inside the VLAN. 1413 */ 1414 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1415 MT7530_VLAN_EGRESS_TAG; 1416 mt7530_rmw(priv, MT7530_VAWD2, 1417 ETAG_CTRL_P_MASK(entry->port), 1418 ETAG_CTRL_P(entry->port, val)); 1419 1420 /* CPU port is always taken as a tagged port for serving more than one 1421 * VLANs across and also being applied with egress type stack mode for 1422 * that VLAN tags would be appended after hardware special tag used as 1423 * DSA tag. 1424 */ 1425 mt7530_rmw(priv, MT7530_VAWD2, 1426 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1427 ETAG_CTRL_P(MT7530_CPU_PORT, 1428 MT7530_VLAN_EGRESS_STACK)); 1429 } 1430 1431 static void 1432 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1433 struct mt7530_hw_vlan_entry *entry) 1434 { 1435 u8 new_members; 1436 u32 val; 1437 1438 new_members = entry->old_members & ~BIT(entry->port); 1439 1440 val = mt7530_read(priv, MT7530_VAWD1); 1441 if (!(val & VLAN_VALID)) { 1442 dev_err(priv->dev, 1443 "Cannot be deleted due to invalid entry\n"); 1444 return; 1445 } 1446 1447 /* If certain member apart from CPU port is still alive in the VLAN, 1448 * the entry would be kept valid. Otherwise, the entry is got to be 1449 * disabled. 1450 */ 1451 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1452 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1453 VLAN_VALID; 1454 mt7530_write(priv, MT7530_VAWD1, val); 1455 } else { 1456 mt7530_write(priv, MT7530_VAWD1, 0); 1457 mt7530_write(priv, MT7530_VAWD2, 0); 1458 } 1459 } 1460 1461 static void 1462 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1463 struct mt7530_hw_vlan_entry *entry, 1464 mt7530_vlan_op vlan_op) 1465 { 1466 u32 val; 1467 1468 /* Fetch entry */ 1469 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1470 1471 val = mt7530_read(priv, MT7530_VAWD1); 1472 1473 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1474 1475 /* Manipulate entry */ 1476 vlan_op(priv, entry); 1477 1478 /* Flush result to hardware */ 1479 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1480 } 1481 1482 static int 1483 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1484 const struct switchdev_obj_port_vlan *vlan, 1485 struct netlink_ext_ack *extack) 1486 { 1487 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1488 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1489 struct mt7530_hw_vlan_entry new_entry; 1490 struct mt7530_priv *priv = ds->priv; 1491 1492 mutex_lock(&priv->reg_mutex); 1493 1494 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1495 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1496 1497 if (pvid) { 1498 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1499 G0_PORT_VID(vlan->vid)); 1500 priv->ports[port].pvid = vlan->vid; 1501 } 1502 1503 mutex_unlock(&priv->reg_mutex); 1504 1505 return 0; 1506 } 1507 1508 static int 1509 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1510 const struct switchdev_obj_port_vlan *vlan) 1511 { 1512 struct mt7530_hw_vlan_entry target_entry; 1513 struct mt7530_priv *priv = ds->priv; 1514 u16 pvid; 1515 1516 mutex_lock(&priv->reg_mutex); 1517 1518 pvid = priv->ports[port].pvid; 1519 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1520 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1521 mt7530_hw_vlan_del); 1522 1523 /* PVID is being restored to the default whenever the PVID port 1524 * is being removed from the VLAN. 1525 */ 1526 if (pvid == vlan->vid) 1527 pvid = G0_PORT_VID_DEF; 1528 1529 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1530 priv->ports[port].pvid = pvid; 1531 1532 mutex_unlock(&priv->reg_mutex); 1533 1534 return 0; 1535 } 1536 1537 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1538 { 1539 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1540 MIRROR_PORT(val); 1541 } 1542 1543 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1544 { 1545 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1546 MIRROR_PORT(val); 1547 } 1548 1549 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1550 struct dsa_mall_mirror_tc_entry *mirror, 1551 bool ingress) 1552 { 1553 struct mt7530_priv *priv = ds->priv; 1554 int monitor_port; 1555 u32 val; 1556 1557 /* Check for existent entry */ 1558 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1559 return -EEXIST; 1560 1561 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1562 1563 /* MT7530 only supports one monitor port */ 1564 monitor_port = mt753x_mirror_port_get(priv->id, val); 1565 if (val & MT753X_MIRROR_EN(priv->id) && 1566 monitor_port != mirror->to_local_port) 1567 return -EEXIST; 1568 1569 val |= MT753X_MIRROR_EN(priv->id); 1570 val &= ~MT753X_MIRROR_MASK(priv->id); 1571 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1572 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1573 1574 val = mt7530_read(priv, MT7530_PCR_P(port)); 1575 if (ingress) { 1576 val |= PORT_RX_MIR; 1577 priv->mirror_rx |= BIT(port); 1578 } else { 1579 val |= PORT_TX_MIR; 1580 priv->mirror_tx |= BIT(port); 1581 } 1582 mt7530_write(priv, MT7530_PCR_P(port), val); 1583 1584 return 0; 1585 } 1586 1587 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1588 struct dsa_mall_mirror_tc_entry *mirror) 1589 { 1590 struct mt7530_priv *priv = ds->priv; 1591 u32 val; 1592 1593 val = mt7530_read(priv, MT7530_PCR_P(port)); 1594 if (mirror->ingress) { 1595 val &= ~PORT_RX_MIR; 1596 priv->mirror_rx &= ~BIT(port); 1597 } else { 1598 val &= ~PORT_TX_MIR; 1599 priv->mirror_tx &= ~BIT(port); 1600 } 1601 mt7530_write(priv, MT7530_PCR_P(port), val); 1602 1603 if (!priv->mirror_rx && !priv->mirror_tx) { 1604 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1605 val &= ~MT753X_MIRROR_EN(priv->id); 1606 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1607 } 1608 } 1609 1610 static enum dsa_tag_protocol 1611 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1612 enum dsa_tag_protocol mp) 1613 { 1614 struct mt7530_priv *priv = ds->priv; 1615 1616 if (port != MT7530_CPU_PORT) { 1617 dev_warn(priv->dev, 1618 "port not matched with tagging CPU port\n"); 1619 return DSA_TAG_PROTO_NONE; 1620 } else { 1621 return DSA_TAG_PROTO_MTK; 1622 } 1623 } 1624 1625 #ifdef CONFIG_GPIOLIB 1626 static inline u32 1627 mt7530_gpio_to_bit(unsigned int offset) 1628 { 1629 /* Map GPIO offset to register bit 1630 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1631 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1632 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1633 * [14:12] port 3 LED 0..2 as GPIO 9..11 1634 * [18:16] port 4 LED 0..2 as GPIO 12..14 1635 */ 1636 return BIT(offset + offset / 3); 1637 } 1638 1639 static int 1640 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1641 { 1642 struct mt7530_priv *priv = gpiochip_get_data(gc); 1643 u32 bit = mt7530_gpio_to_bit(offset); 1644 1645 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1646 } 1647 1648 static void 1649 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1650 { 1651 struct mt7530_priv *priv = gpiochip_get_data(gc); 1652 u32 bit = mt7530_gpio_to_bit(offset); 1653 1654 if (value) 1655 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1656 else 1657 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1658 } 1659 1660 static int 1661 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1662 { 1663 struct mt7530_priv *priv = gpiochip_get_data(gc); 1664 u32 bit = mt7530_gpio_to_bit(offset); 1665 1666 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1667 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1668 } 1669 1670 static int 1671 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1672 { 1673 struct mt7530_priv *priv = gpiochip_get_data(gc); 1674 u32 bit = mt7530_gpio_to_bit(offset); 1675 1676 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1677 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1678 1679 return 0; 1680 } 1681 1682 static int 1683 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1684 { 1685 struct mt7530_priv *priv = gpiochip_get_data(gc); 1686 u32 bit = mt7530_gpio_to_bit(offset); 1687 1688 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1689 1690 if (value) 1691 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1692 else 1693 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1694 1695 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1696 1697 return 0; 1698 } 1699 1700 static int 1701 mt7530_setup_gpio(struct mt7530_priv *priv) 1702 { 1703 struct device *dev = priv->dev; 1704 struct gpio_chip *gc; 1705 1706 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1707 if (!gc) 1708 return -ENOMEM; 1709 1710 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1711 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1712 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1713 1714 gc->label = "mt7530"; 1715 gc->parent = dev; 1716 gc->owner = THIS_MODULE; 1717 gc->get_direction = mt7530_gpio_get_direction; 1718 gc->direction_input = mt7530_gpio_direction_input; 1719 gc->direction_output = mt7530_gpio_direction_output; 1720 gc->get = mt7530_gpio_get; 1721 gc->set = mt7530_gpio_set; 1722 gc->base = -1; 1723 gc->ngpio = 15; 1724 gc->can_sleep = true; 1725 1726 return devm_gpiochip_add_data(dev, gc, priv); 1727 } 1728 #endif /* CONFIG_GPIOLIB */ 1729 1730 static int 1731 mt7530_setup(struct dsa_switch *ds) 1732 { 1733 struct mt7530_priv *priv = ds->priv; 1734 struct device_node *phy_node; 1735 struct device_node *mac_np; 1736 struct mt7530_dummy_poll p; 1737 phy_interface_t interface; 1738 struct device_node *dn; 1739 u32 id, val; 1740 int ret, i; 1741 1742 /* The parent node of master netdev which holds the common system 1743 * controller also is the container for two GMACs nodes representing 1744 * as two netdev instances. 1745 */ 1746 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 1747 ds->mtu_enforcement_ingress = true; 1748 1749 if (priv->id == ID_MT7530) { 1750 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1751 ret = regulator_enable(priv->core_pwr); 1752 if (ret < 0) { 1753 dev_err(priv->dev, 1754 "Failed to enable core power: %d\n", ret); 1755 return ret; 1756 } 1757 1758 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1759 ret = regulator_enable(priv->io_pwr); 1760 if (ret < 0) { 1761 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1762 ret); 1763 return ret; 1764 } 1765 } 1766 1767 /* Reset whole chip through gpio pin or memory-mapped registers for 1768 * different type of hardware 1769 */ 1770 if (priv->mcm) { 1771 reset_control_assert(priv->rstc); 1772 usleep_range(1000, 1100); 1773 reset_control_deassert(priv->rstc); 1774 } else { 1775 gpiod_set_value_cansleep(priv->reset, 0); 1776 usleep_range(1000, 1100); 1777 gpiod_set_value_cansleep(priv->reset, 1); 1778 } 1779 1780 /* Waiting for MT7530 got to stable */ 1781 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1782 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1783 20, 1000000); 1784 if (ret < 0) { 1785 dev_err(priv->dev, "reset timeout\n"); 1786 return ret; 1787 } 1788 1789 id = mt7530_read(priv, MT7530_CREV); 1790 id >>= CHIP_NAME_SHIFT; 1791 if (id != MT7530_ID) { 1792 dev_err(priv->dev, "chip %x can't be supported\n", id); 1793 return -ENODEV; 1794 } 1795 1796 /* Reset the switch through internal reset */ 1797 mt7530_write(priv, MT7530_SYS_CTRL, 1798 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1799 SYS_CTRL_REG_RST); 1800 1801 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1802 val = mt7530_read(priv, MT7530_MHWTRAP); 1803 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1804 val |= MHWTRAP_MANUAL; 1805 mt7530_write(priv, MT7530_MHWTRAP, val); 1806 1807 priv->p6_interface = PHY_INTERFACE_MODE_NA; 1808 1809 /* Enable and reset MIB counters */ 1810 mt7530_mib_reset(ds); 1811 1812 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1813 /* Disable forwarding by default on all ports */ 1814 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1815 PCR_MATRIX_CLR); 1816 1817 if (dsa_is_cpu_port(ds, i)) { 1818 ret = mt753x_cpu_port_enable(ds, i); 1819 if (ret) 1820 return ret; 1821 } else 1822 mt7530_port_disable(ds, i); 1823 1824 /* Enable consistent egress tag */ 1825 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 1826 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1827 } 1828 1829 /* Setup port 5 */ 1830 priv->p5_intf_sel = P5_DISABLED; 1831 interface = PHY_INTERFACE_MODE_NA; 1832 1833 if (!dsa_is_unused_port(ds, 5)) { 1834 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 1835 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 1836 if (ret && ret != -ENODEV) 1837 return ret; 1838 } else { 1839 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 1840 for_each_child_of_node(dn, mac_np) { 1841 if (!of_device_is_compatible(mac_np, 1842 "mediatek,eth-mac")) 1843 continue; 1844 1845 ret = of_property_read_u32(mac_np, "reg", &id); 1846 if (ret < 0 || id != 1) 1847 continue; 1848 1849 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 1850 if (!phy_node) 1851 continue; 1852 1853 if (phy_node->parent == priv->dev->of_node->parent) { 1854 ret = of_get_phy_mode(mac_np, &interface); 1855 if (ret && ret != -ENODEV) { 1856 of_node_put(mac_np); 1857 return ret; 1858 } 1859 id = of_mdio_parse_addr(ds->dev, phy_node); 1860 if (id == 0) 1861 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 1862 if (id == 4) 1863 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 1864 } 1865 of_node_put(mac_np); 1866 of_node_put(phy_node); 1867 break; 1868 } 1869 } 1870 1871 #ifdef CONFIG_GPIOLIB 1872 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 1873 ret = mt7530_setup_gpio(priv); 1874 if (ret) 1875 return ret; 1876 } 1877 #endif /* CONFIG_GPIOLIB */ 1878 1879 mt7530_setup_port5(ds, interface); 1880 1881 /* Flush the FDB table */ 1882 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1883 if (ret < 0) 1884 return ret; 1885 1886 return 0; 1887 } 1888 1889 static int 1890 mt7531_setup(struct dsa_switch *ds) 1891 { 1892 struct mt7530_priv *priv = ds->priv; 1893 struct mt7530_dummy_poll p; 1894 u32 val, id; 1895 int ret, i; 1896 1897 /* Reset whole chip through gpio pin or memory-mapped registers for 1898 * different type of hardware 1899 */ 1900 if (priv->mcm) { 1901 reset_control_assert(priv->rstc); 1902 usleep_range(1000, 1100); 1903 reset_control_deassert(priv->rstc); 1904 } else { 1905 gpiod_set_value_cansleep(priv->reset, 0); 1906 usleep_range(1000, 1100); 1907 gpiod_set_value_cansleep(priv->reset, 1); 1908 } 1909 1910 /* Waiting for MT7530 got to stable */ 1911 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1912 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1913 20, 1000000); 1914 if (ret < 0) { 1915 dev_err(priv->dev, "reset timeout\n"); 1916 return ret; 1917 } 1918 1919 id = mt7530_read(priv, MT7531_CREV); 1920 id >>= CHIP_NAME_SHIFT; 1921 1922 if (id != MT7531_ID) { 1923 dev_err(priv->dev, "chip %x can't be supported\n", id); 1924 return -ENODEV; 1925 } 1926 1927 /* Reset the switch through internal reset */ 1928 mt7530_write(priv, MT7530_SYS_CTRL, 1929 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1930 SYS_CTRL_REG_RST); 1931 1932 if (mt7531_dual_sgmii_supported(priv)) { 1933 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 1934 1935 /* Let ds->slave_mii_bus be able to access external phy. */ 1936 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 1937 MT7531_EXT_P_MDC_11); 1938 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 1939 MT7531_EXT_P_MDIO_12); 1940 } else { 1941 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 1942 } 1943 dev_dbg(ds->dev, "P5 support %s interface\n", 1944 p5_intf_modes(priv->p5_intf_sel)); 1945 1946 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 1947 MT7531_GPIO0_INTERRUPT); 1948 1949 /* Let phylink decide the interface later. */ 1950 priv->p5_interface = PHY_INTERFACE_MODE_NA; 1951 priv->p6_interface = PHY_INTERFACE_MODE_NA; 1952 1953 /* Enable PHY core PLL, since phy_device has not yet been created 1954 * provided for phy_[read,write]_mmd_indirect is called, we provide 1955 * our own mt7531_ind_mmd_phy_[read,write] to complete this 1956 * function. 1957 */ 1958 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 1959 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 1960 val |= MT7531_PHY_PLL_BYPASS_MODE; 1961 val &= ~MT7531_PHY_PLL_OFF; 1962 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 1963 CORE_PLL_GROUP4, val); 1964 1965 /* BPDU to CPU port */ 1966 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 1967 BIT(MT7530_CPU_PORT)); 1968 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 1969 MT753X_BPDU_CPU_ONLY); 1970 1971 /* Enable and reset MIB counters */ 1972 mt7530_mib_reset(ds); 1973 1974 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1975 /* Disable forwarding by default on all ports */ 1976 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1977 PCR_MATRIX_CLR); 1978 1979 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 1980 1981 if (dsa_is_cpu_port(ds, i)) { 1982 ret = mt753x_cpu_port_enable(ds, i); 1983 if (ret) 1984 return ret; 1985 } else 1986 mt7530_port_disable(ds, i); 1987 1988 /* Enable consistent egress tag */ 1989 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 1990 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1991 } 1992 1993 ds->mtu_enforcement_ingress = true; 1994 1995 /* Flush the FDB table */ 1996 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1997 if (ret < 0) 1998 return ret; 1999 2000 return 0; 2001 } 2002 2003 static bool 2004 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2005 const struct phylink_link_state *state) 2006 { 2007 struct mt7530_priv *priv = ds->priv; 2008 2009 switch (port) { 2010 case 0 ... 4: /* Internal phy */ 2011 if (state->interface != PHY_INTERFACE_MODE_GMII) 2012 return false; 2013 break; 2014 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2015 if (!phy_interface_mode_is_rgmii(state->interface) && 2016 state->interface != PHY_INTERFACE_MODE_MII && 2017 state->interface != PHY_INTERFACE_MODE_GMII) 2018 return false; 2019 break; 2020 case 6: /* 1st cpu port */ 2021 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2022 state->interface != PHY_INTERFACE_MODE_TRGMII) 2023 return false; 2024 break; 2025 default: 2026 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2027 port); 2028 return false; 2029 } 2030 2031 return true; 2032 } 2033 2034 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2035 { 2036 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2037 } 2038 2039 static bool 2040 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2041 const struct phylink_link_state *state) 2042 { 2043 struct mt7530_priv *priv = ds->priv; 2044 2045 switch (port) { 2046 case 0 ... 4: /* Internal phy */ 2047 if (state->interface != PHY_INTERFACE_MODE_GMII) 2048 return false; 2049 break; 2050 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2051 if (mt7531_is_rgmii_port(priv, port)) 2052 return phy_interface_mode_is_rgmii(state->interface); 2053 fallthrough; 2054 case 6: /* 1st cpu port supports sgmii/8023z only */ 2055 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2056 !phy_interface_mode_is_8023z(state->interface)) 2057 return false; 2058 break; 2059 default: 2060 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2061 port); 2062 return false; 2063 } 2064 2065 return true; 2066 } 2067 2068 static bool 2069 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2070 const struct phylink_link_state *state) 2071 { 2072 struct mt7530_priv *priv = ds->priv; 2073 2074 return priv->info->phy_mode_supported(ds, port, state); 2075 } 2076 2077 static int 2078 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2079 { 2080 struct mt7530_priv *priv = ds->priv; 2081 2082 return priv->info->pad_setup(ds, state->interface); 2083 } 2084 2085 static int 2086 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2087 phy_interface_t interface) 2088 { 2089 struct mt7530_priv *priv = ds->priv; 2090 2091 /* Only need to setup port5. */ 2092 if (port != 5) 2093 return 0; 2094 2095 mt7530_setup_port5(priv->ds, interface); 2096 2097 return 0; 2098 } 2099 2100 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2101 phy_interface_t interface, 2102 struct phy_device *phydev) 2103 { 2104 u32 val; 2105 2106 if (!mt7531_is_rgmii_port(priv, port)) { 2107 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2108 port); 2109 return -EINVAL; 2110 } 2111 2112 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2113 val |= GP_CLK_EN; 2114 val &= ~GP_MODE_MASK; 2115 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2116 val &= ~CLK_SKEW_IN_MASK; 2117 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2118 val &= ~CLK_SKEW_OUT_MASK; 2119 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2120 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2121 2122 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2123 if (!phydev || phy_driver_is_genphy(phydev)) { 2124 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2125 switch (interface) { 2126 case PHY_INTERFACE_MODE_RGMII: 2127 val |= TXCLK_NO_REVERSE; 2128 val |= RXCLK_NO_DELAY; 2129 break; 2130 case PHY_INTERFACE_MODE_RGMII_RXID: 2131 val |= TXCLK_NO_REVERSE; 2132 break; 2133 case PHY_INTERFACE_MODE_RGMII_TXID: 2134 val |= RXCLK_NO_DELAY; 2135 break; 2136 case PHY_INTERFACE_MODE_RGMII_ID: 2137 break; 2138 default: 2139 return -EINVAL; 2140 } 2141 } 2142 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2143 2144 return 0; 2145 } 2146 2147 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2148 unsigned long *supported) 2149 { 2150 /* Port5 supports ethier RGMII or SGMII. 2151 * Port6 supports SGMII only. 2152 */ 2153 switch (port) { 2154 case 5: 2155 if (mt7531_is_rgmii_port(priv, port)) 2156 break; 2157 fallthrough; 2158 case 6: 2159 phylink_set(supported, 1000baseX_Full); 2160 phylink_set(supported, 2500baseX_Full); 2161 phylink_set(supported, 2500baseT_Full); 2162 } 2163 } 2164 2165 static void 2166 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2167 unsigned int mode, phy_interface_t interface, 2168 int speed, int duplex) 2169 { 2170 struct mt7530_priv *priv = ds->priv; 2171 unsigned int val; 2172 2173 /* For adjusting speed and duplex of SGMII force mode. */ 2174 if (interface != PHY_INTERFACE_MODE_SGMII || 2175 phylink_autoneg_inband(mode)) 2176 return; 2177 2178 /* SGMII force mode setting */ 2179 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2180 val &= ~MT7531_SGMII_IF_MODE_MASK; 2181 2182 switch (speed) { 2183 case SPEED_10: 2184 val |= MT7531_SGMII_FORCE_SPEED_10; 2185 break; 2186 case SPEED_100: 2187 val |= MT7531_SGMII_FORCE_SPEED_100; 2188 break; 2189 case SPEED_1000: 2190 val |= MT7531_SGMII_FORCE_SPEED_1000; 2191 break; 2192 } 2193 2194 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2195 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2196 */ 2197 if ((speed == SPEED_10 || speed == SPEED_100) && 2198 duplex != DUPLEX_FULL) 2199 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2200 2201 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2202 } 2203 2204 static bool mt753x_is_mac_port(u32 port) 2205 { 2206 return (port == 5 || port == 6); 2207 } 2208 2209 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2210 phy_interface_t interface) 2211 { 2212 u32 val; 2213 2214 if (!mt753x_is_mac_port(port)) 2215 return -EINVAL; 2216 2217 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2218 MT7531_SGMII_PHYA_PWD); 2219 2220 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2221 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2222 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2223 * encoding. 2224 */ 2225 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2226 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2227 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2228 2229 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2230 2231 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2232 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2233 */ 2234 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2235 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2236 MT7531_SGMII_FORCE_SPEED_1000); 2237 2238 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2239 2240 return 0; 2241 } 2242 2243 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2244 phy_interface_t interface) 2245 { 2246 if (!mt753x_is_mac_port(port)) 2247 return -EINVAL; 2248 2249 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2250 MT7531_SGMII_PHYA_PWD); 2251 2252 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2253 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2254 2255 mt7530_set(priv, MT7531_SGMII_MODE(port), 2256 MT7531_SGMII_REMOTE_FAULT_DIS | 2257 MT7531_SGMII_SPEED_DUPLEX_AN); 2258 2259 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2260 MT7531_SGMII_TX_CONFIG_MASK, 1); 2261 2262 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2263 2264 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2265 2266 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2267 2268 return 0; 2269 } 2270 2271 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2272 { 2273 struct mt7530_priv *priv = ds->priv; 2274 u32 val; 2275 2276 /* Only restart AN when AN is enabled */ 2277 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2278 if (val & MT7531_SGMII_AN_ENABLE) { 2279 val |= MT7531_SGMII_AN_RESTART; 2280 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2281 } 2282 } 2283 2284 static int 2285 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2286 phy_interface_t interface) 2287 { 2288 struct mt7530_priv *priv = ds->priv; 2289 struct phy_device *phydev; 2290 struct dsa_port *dp; 2291 2292 if (!mt753x_is_mac_port(port)) { 2293 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2294 return -EINVAL; 2295 } 2296 2297 switch (interface) { 2298 case PHY_INTERFACE_MODE_RGMII: 2299 case PHY_INTERFACE_MODE_RGMII_ID: 2300 case PHY_INTERFACE_MODE_RGMII_RXID: 2301 case PHY_INTERFACE_MODE_RGMII_TXID: 2302 dp = dsa_to_port(ds, port); 2303 phydev = dp->slave->phydev; 2304 return mt7531_rgmii_setup(priv, port, interface, phydev); 2305 case PHY_INTERFACE_MODE_SGMII: 2306 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2307 case PHY_INTERFACE_MODE_NA: 2308 case PHY_INTERFACE_MODE_1000BASEX: 2309 case PHY_INTERFACE_MODE_2500BASEX: 2310 if (phylink_autoneg_inband(mode)) 2311 return -EINVAL; 2312 2313 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2314 default: 2315 return -EINVAL; 2316 } 2317 2318 return -EINVAL; 2319 } 2320 2321 static int 2322 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2323 const struct phylink_link_state *state) 2324 { 2325 struct mt7530_priv *priv = ds->priv; 2326 2327 return priv->info->mac_port_config(ds, port, mode, state->interface); 2328 } 2329 2330 static void 2331 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2332 const struct phylink_link_state *state) 2333 { 2334 struct mt7530_priv *priv = ds->priv; 2335 u32 mcr_cur, mcr_new; 2336 2337 if (!mt753x_phy_mode_supported(ds, port, state)) 2338 goto unsupported; 2339 2340 switch (port) { 2341 case 0 ... 4: /* Internal phy */ 2342 if (state->interface != PHY_INTERFACE_MODE_GMII) 2343 goto unsupported; 2344 break; 2345 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2346 if (priv->p5_interface == state->interface) 2347 break; 2348 2349 if (mt753x_mac_config(ds, port, mode, state) < 0) 2350 goto unsupported; 2351 2352 if (priv->p5_intf_sel != P5_DISABLED) 2353 priv->p5_interface = state->interface; 2354 break; 2355 case 6: /* 1st cpu port */ 2356 if (priv->p6_interface == state->interface) 2357 break; 2358 2359 mt753x_pad_setup(ds, state); 2360 2361 if (mt753x_mac_config(ds, port, mode, state) < 0) 2362 goto unsupported; 2363 2364 priv->p6_interface = state->interface; 2365 break; 2366 default: 2367 unsupported: 2368 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2369 __func__, phy_modes(state->interface), port); 2370 return; 2371 } 2372 2373 if (phylink_autoneg_inband(mode) && 2374 state->interface != PHY_INTERFACE_MODE_SGMII) { 2375 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2376 __func__); 2377 return; 2378 } 2379 2380 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2381 mcr_new = mcr_cur; 2382 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2383 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2384 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2385 2386 /* Are we connected to external phy */ 2387 if (port == 5 && dsa_is_user_port(ds, 5)) 2388 mcr_new |= PMCR_EXT_PHY; 2389 2390 if (mcr_new != mcr_cur) 2391 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2392 } 2393 2394 static void 2395 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2396 { 2397 struct mt7530_priv *priv = ds->priv; 2398 2399 if (!priv->info->mac_pcs_an_restart) 2400 return; 2401 2402 priv->info->mac_pcs_an_restart(ds, port); 2403 } 2404 2405 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2406 unsigned int mode, 2407 phy_interface_t interface) 2408 { 2409 struct mt7530_priv *priv = ds->priv; 2410 2411 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2412 } 2413 2414 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2415 unsigned int mode, phy_interface_t interface, 2416 int speed, int duplex) 2417 { 2418 struct mt7530_priv *priv = ds->priv; 2419 2420 if (!priv->info->mac_pcs_link_up) 2421 return; 2422 2423 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2424 } 2425 2426 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2427 unsigned int mode, 2428 phy_interface_t interface, 2429 struct phy_device *phydev, 2430 int speed, int duplex, 2431 bool tx_pause, bool rx_pause) 2432 { 2433 struct mt7530_priv *priv = ds->priv; 2434 u32 mcr; 2435 2436 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2437 2438 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2439 2440 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2441 * variants. 2442 */ 2443 if (interface == PHY_INTERFACE_MODE_TRGMII || 2444 (phy_interface_mode_is_8023z(interface))) { 2445 speed = SPEED_1000; 2446 duplex = DUPLEX_FULL; 2447 } 2448 2449 switch (speed) { 2450 case SPEED_1000: 2451 mcr |= PMCR_FORCE_SPEED_1000; 2452 break; 2453 case SPEED_100: 2454 mcr |= PMCR_FORCE_SPEED_100; 2455 break; 2456 } 2457 if (duplex == DUPLEX_FULL) { 2458 mcr |= PMCR_FORCE_FDX; 2459 if (tx_pause) 2460 mcr |= PMCR_TX_FC_EN; 2461 if (rx_pause) 2462 mcr |= PMCR_RX_FC_EN; 2463 } 2464 2465 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2466 } 2467 2468 static int 2469 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2470 { 2471 struct mt7530_priv *priv = ds->priv; 2472 phy_interface_t interface; 2473 int speed; 2474 int ret; 2475 2476 switch (port) { 2477 case 5: 2478 if (mt7531_is_rgmii_port(priv, port)) 2479 interface = PHY_INTERFACE_MODE_RGMII; 2480 else 2481 interface = PHY_INTERFACE_MODE_2500BASEX; 2482 2483 priv->p5_interface = interface; 2484 break; 2485 case 6: 2486 interface = PHY_INTERFACE_MODE_2500BASEX; 2487 2488 mt7531_pad_setup(ds, interface); 2489 2490 priv->p6_interface = interface; 2491 break; 2492 default: 2493 return -EINVAL; 2494 } 2495 2496 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2497 speed = SPEED_2500; 2498 else 2499 speed = SPEED_1000; 2500 2501 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2502 if (ret) 2503 return ret; 2504 mt7530_write(priv, MT7530_PMCR_P(port), 2505 PMCR_CPU_PORT_SETTING(priv->id)); 2506 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2507 speed, DUPLEX_FULL, true, true); 2508 2509 return 0; 2510 } 2511 2512 static void 2513 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2514 unsigned long *supported) 2515 { 2516 if (port == 5) 2517 phylink_set(supported, 1000baseX_Full); 2518 } 2519 2520 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2521 unsigned long *supported) 2522 { 2523 struct mt7530_priv *priv = ds->priv; 2524 2525 mt7531_sgmii_validate(priv, port, supported); 2526 } 2527 2528 static void 2529 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2530 unsigned long *supported, 2531 struct phylink_link_state *state) 2532 { 2533 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2534 struct mt7530_priv *priv = ds->priv; 2535 2536 if (state->interface != PHY_INTERFACE_MODE_NA && 2537 !mt753x_phy_mode_supported(ds, port, state)) { 2538 linkmode_zero(supported); 2539 return; 2540 } 2541 2542 phylink_set_port_modes(mask); 2543 2544 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2545 !phy_interface_mode_is_8023z(state->interface)) { 2546 phylink_set(mask, 10baseT_Half); 2547 phylink_set(mask, 10baseT_Full); 2548 phylink_set(mask, 100baseT_Half); 2549 phylink_set(mask, 100baseT_Full); 2550 phylink_set(mask, Autoneg); 2551 } 2552 2553 /* This switch only supports 1G full-duplex. */ 2554 if (state->interface != PHY_INTERFACE_MODE_MII) 2555 phylink_set(mask, 1000baseT_Full); 2556 2557 priv->info->mac_port_validate(ds, port, mask); 2558 2559 phylink_set(mask, Pause); 2560 phylink_set(mask, Asym_Pause); 2561 2562 linkmode_and(supported, supported, mask); 2563 linkmode_and(state->advertising, state->advertising, mask); 2564 2565 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2566 * to advertise both, only report advertising at 2500BaseX. 2567 */ 2568 phylink_helper_basex_speed(state); 2569 } 2570 2571 static int 2572 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2573 struct phylink_link_state *state) 2574 { 2575 struct mt7530_priv *priv = ds->priv; 2576 u32 pmsr; 2577 2578 if (port < 0 || port >= MT7530_NUM_PORTS) 2579 return -EINVAL; 2580 2581 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2582 2583 state->link = (pmsr & PMSR_LINK); 2584 state->an_complete = state->link; 2585 state->duplex = !!(pmsr & PMSR_DPX); 2586 2587 switch (pmsr & PMSR_SPEED_MASK) { 2588 case PMSR_SPEED_10: 2589 state->speed = SPEED_10; 2590 break; 2591 case PMSR_SPEED_100: 2592 state->speed = SPEED_100; 2593 break; 2594 case PMSR_SPEED_1000: 2595 state->speed = SPEED_1000; 2596 break; 2597 default: 2598 state->speed = SPEED_UNKNOWN; 2599 break; 2600 } 2601 2602 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2603 if (pmsr & PMSR_RX_FC) 2604 state->pause |= MLO_PAUSE_RX; 2605 if (pmsr & PMSR_TX_FC) 2606 state->pause |= MLO_PAUSE_TX; 2607 2608 return 1; 2609 } 2610 2611 static int 2612 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2613 struct phylink_link_state *state) 2614 { 2615 u32 status, val; 2616 u16 config_reg; 2617 2618 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2619 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2620 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2621 (status & MT7531_SGMII_AN_ENABLE)) { 2622 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2623 config_reg = val >> 16; 2624 2625 switch (config_reg & LPA_SGMII_SPD_MASK) { 2626 case LPA_SGMII_1000: 2627 state->speed = SPEED_1000; 2628 break; 2629 case LPA_SGMII_100: 2630 state->speed = SPEED_100; 2631 break; 2632 case LPA_SGMII_10: 2633 state->speed = SPEED_10; 2634 break; 2635 default: 2636 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2637 state->link = false; 2638 return -EINVAL; 2639 } 2640 2641 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2642 state->duplex = DUPLEX_FULL; 2643 else 2644 state->duplex = DUPLEX_HALF; 2645 } 2646 2647 return 0; 2648 } 2649 2650 static int 2651 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 2652 struct phylink_link_state *state) 2653 { 2654 struct mt7530_priv *priv = ds->priv; 2655 2656 if (state->interface == PHY_INTERFACE_MODE_SGMII) 2657 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 2658 2659 return -EOPNOTSUPP; 2660 } 2661 2662 static int 2663 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 2664 struct phylink_link_state *state) 2665 { 2666 struct mt7530_priv *priv = ds->priv; 2667 2668 return priv->info->mac_port_get_state(ds, port, state); 2669 } 2670 2671 static int 2672 mt753x_setup(struct dsa_switch *ds) 2673 { 2674 struct mt7530_priv *priv = ds->priv; 2675 2676 return priv->info->sw_setup(ds); 2677 } 2678 2679 static int 2680 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) 2681 { 2682 struct mt7530_priv *priv = ds->priv; 2683 2684 return priv->info->phy_read(ds, port, regnum); 2685 } 2686 2687 static int 2688 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) 2689 { 2690 struct mt7530_priv *priv = ds->priv; 2691 2692 return priv->info->phy_write(ds, port, regnum, val); 2693 } 2694 2695 static const struct dsa_switch_ops mt7530_switch_ops = { 2696 .get_tag_protocol = mtk_get_tag_protocol, 2697 .setup = mt753x_setup, 2698 .get_strings = mt7530_get_strings, 2699 .phy_read = mt753x_phy_read, 2700 .phy_write = mt753x_phy_write, 2701 .get_ethtool_stats = mt7530_get_ethtool_stats, 2702 .get_sset_count = mt7530_get_sset_count, 2703 .set_ageing_time = mt7530_set_ageing_time, 2704 .port_enable = mt7530_port_enable, 2705 .port_disable = mt7530_port_disable, 2706 .port_change_mtu = mt7530_port_change_mtu, 2707 .port_max_mtu = mt7530_port_max_mtu, 2708 .port_stp_state_set = mt7530_stp_state_set, 2709 .port_bridge_join = mt7530_port_bridge_join, 2710 .port_bridge_leave = mt7530_port_bridge_leave, 2711 .port_fdb_add = mt7530_port_fdb_add, 2712 .port_fdb_del = mt7530_port_fdb_del, 2713 .port_fdb_dump = mt7530_port_fdb_dump, 2714 .port_vlan_filtering = mt7530_port_vlan_filtering, 2715 .port_vlan_add = mt7530_port_vlan_add, 2716 .port_vlan_del = mt7530_port_vlan_del, 2717 .port_mirror_add = mt753x_port_mirror_add, 2718 .port_mirror_del = mt753x_port_mirror_del, 2719 .phylink_validate = mt753x_phylink_validate, 2720 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 2721 .phylink_mac_config = mt753x_phylink_mac_config, 2722 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 2723 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 2724 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 2725 }; 2726 2727 static const struct mt753x_info mt753x_table[] = { 2728 [ID_MT7621] = { 2729 .id = ID_MT7621, 2730 .sw_setup = mt7530_setup, 2731 .phy_read = mt7530_phy_read, 2732 .phy_write = mt7530_phy_write, 2733 .pad_setup = mt7530_pad_clk_setup, 2734 .phy_mode_supported = mt7530_phy_mode_supported, 2735 .mac_port_validate = mt7530_mac_port_validate, 2736 .mac_port_get_state = mt7530_phylink_mac_link_state, 2737 .mac_port_config = mt7530_mac_config, 2738 }, 2739 [ID_MT7530] = { 2740 .id = ID_MT7530, 2741 .sw_setup = mt7530_setup, 2742 .phy_read = mt7530_phy_read, 2743 .phy_write = mt7530_phy_write, 2744 .pad_setup = mt7530_pad_clk_setup, 2745 .phy_mode_supported = mt7530_phy_mode_supported, 2746 .mac_port_validate = mt7530_mac_port_validate, 2747 .mac_port_get_state = mt7530_phylink_mac_link_state, 2748 .mac_port_config = mt7530_mac_config, 2749 }, 2750 [ID_MT7531] = { 2751 .id = ID_MT7531, 2752 .sw_setup = mt7531_setup, 2753 .phy_read = mt7531_ind_phy_read, 2754 .phy_write = mt7531_ind_phy_write, 2755 .pad_setup = mt7531_pad_setup, 2756 .cpu_port_config = mt7531_cpu_port_config, 2757 .phy_mode_supported = mt7531_phy_mode_supported, 2758 .mac_port_validate = mt7531_mac_port_validate, 2759 .mac_port_get_state = mt7531_phylink_mac_link_state, 2760 .mac_port_config = mt7531_mac_config, 2761 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 2762 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 2763 }, 2764 }; 2765 2766 static const struct of_device_id mt7530_of_match[] = { 2767 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 2768 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 2769 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 2770 { /* sentinel */ }, 2771 }; 2772 MODULE_DEVICE_TABLE(of, mt7530_of_match); 2773 2774 static int 2775 mt7530_probe(struct mdio_device *mdiodev) 2776 { 2777 struct mt7530_priv *priv; 2778 struct device_node *dn; 2779 2780 dn = mdiodev->dev.of_node; 2781 2782 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 2783 if (!priv) 2784 return -ENOMEM; 2785 2786 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 2787 if (!priv->ds) 2788 return -ENOMEM; 2789 2790 priv->ds->dev = &mdiodev->dev; 2791 priv->ds->num_ports = DSA_MAX_PORTS; 2792 2793 /* Use medatek,mcm property to distinguish hardware type that would 2794 * casues a little bit differences on power-on sequence. 2795 */ 2796 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 2797 if (priv->mcm) { 2798 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 2799 2800 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 2801 if (IS_ERR(priv->rstc)) { 2802 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2803 return PTR_ERR(priv->rstc); 2804 } 2805 } 2806 2807 /* Get the hardware identifier from the devicetree node. 2808 * We will need it for some of the clock and regulator setup. 2809 */ 2810 priv->info = of_device_get_match_data(&mdiodev->dev); 2811 if (!priv->info) 2812 return -EINVAL; 2813 2814 /* Sanity check if these required device operations are filled 2815 * properly. 2816 */ 2817 if (!priv->info->sw_setup || !priv->info->pad_setup || 2818 !priv->info->phy_read || !priv->info->phy_write || 2819 !priv->info->phy_mode_supported || 2820 !priv->info->mac_port_validate || 2821 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 2822 return -EINVAL; 2823 2824 priv->id = priv->info->id; 2825 2826 if (priv->id == ID_MT7530) { 2827 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 2828 if (IS_ERR(priv->core_pwr)) 2829 return PTR_ERR(priv->core_pwr); 2830 2831 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 2832 if (IS_ERR(priv->io_pwr)) 2833 return PTR_ERR(priv->io_pwr); 2834 } 2835 2836 /* Not MCM that indicates switch works as the remote standalone 2837 * integrated circuit so the GPIO pin would be used to complete 2838 * the reset, otherwise memory-mapped register accessing used 2839 * through syscon provides in the case of MCM. 2840 */ 2841 if (!priv->mcm) { 2842 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 2843 GPIOD_OUT_LOW); 2844 if (IS_ERR(priv->reset)) { 2845 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2846 return PTR_ERR(priv->reset); 2847 } 2848 } 2849 2850 priv->bus = mdiodev->bus; 2851 priv->dev = &mdiodev->dev; 2852 priv->ds->priv = priv; 2853 priv->ds->ops = &mt7530_switch_ops; 2854 mutex_init(&priv->reg_mutex); 2855 dev_set_drvdata(&mdiodev->dev, priv); 2856 2857 return dsa_register_switch(priv->ds); 2858 } 2859 2860 static void 2861 mt7530_remove(struct mdio_device *mdiodev) 2862 { 2863 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 2864 int ret = 0; 2865 2866 ret = regulator_disable(priv->core_pwr); 2867 if (ret < 0) 2868 dev_err(priv->dev, 2869 "Failed to disable core power: %d\n", ret); 2870 2871 ret = regulator_disable(priv->io_pwr); 2872 if (ret < 0) 2873 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 2874 ret); 2875 2876 dsa_unregister_switch(priv->ds); 2877 mutex_destroy(&priv->reg_mutex); 2878 } 2879 2880 static struct mdio_driver mt7530_mdio_driver = { 2881 .probe = mt7530_probe, 2882 .remove = mt7530_remove, 2883 .mdiodrv.driver = { 2884 .name = "mt7530", 2885 .of_match_table = mt7530_of_match, 2886 }, 2887 }; 2888 2889 mdio_module_driver(mt7530_mdio_driver); 2890 2891 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 2892 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 2893 MODULE_LICENSE("GPL"); 2894