1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_net.h> 15 #include <linux/of_platform.h> 16 #include <linux/phy.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/gpio/consumer.h> 21 #include <net/dsa.h> 22 23 #include "mt7530.h" 24 25 /* String, offset, and register size in bytes if different from 4 bytes */ 26 static const struct mt7530_mib_desc mt7530_mib[] = { 27 MIB_DESC(1, 0x00, "TxDrop"), 28 MIB_DESC(1, 0x04, "TxCrcErr"), 29 MIB_DESC(1, 0x08, "TxUnicast"), 30 MIB_DESC(1, 0x0c, "TxMulticast"), 31 MIB_DESC(1, 0x10, "TxBroadcast"), 32 MIB_DESC(1, 0x14, "TxCollision"), 33 MIB_DESC(1, 0x18, "TxSingleCollision"), 34 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 35 MIB_DESC(1, 0x20, "TxDeferred"), 36 MIB_DESC(1, 0x24, "TxLateCollision"), 37 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 38 MIB_DESC(1, 0x2c, "TxPause"), 39 MIB_DESC(1, 0x30, "TxPktSz64"), 40 MIB_DESC(1, 0x34, "TxPktSz65To127"), 41 MIB_DESC(1, 0x38, "TxPktSz128To255"), 42 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 43 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 44 MIB_DESC(1, 0x44, "Tx1024ToMax"), 45 MIB_DESC(2, 0x48, "TxBytes"), 46 MIB_DESC(1, 0x60, "RxDrop"), 47 MIB_DESC(1, 0x64, "RxFiltering"), 48 MIB_DESC(1, 0x6c, "RxMulticast"), 49 MIB_DESC(1, 0x70, "RxBroadcast"), 50 MIB_DESC(1, 0x74, "RxAlignErr"), 51 MIB_DESC(1, 0x78, "RxCrcErr"), 52 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 53 MIB_DESC(1, 0x80, "RxFragErr"), 54 MIB_DESC(1, 0x84, "RxOverSzErr"), 55 MIB_DESC(1, 0x88, "RxJabberErr"), 56 MIB_DESC(1, 0x8c, "RxPause"), 57 MIB_DESC(1, 0x90, "RxPktSz64"), 58 MIB_DESC(1, 0x94, "RxPktSz65To127"), 59 MIB_DESC(1, 0x98, "RxPktSz128To255"), 60 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 61 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 62 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 63 MIB_DESC(2, 0xa8, "RxBytes"), 64 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 65 MIB_DESC(1, 0xb4, "RxIngressDrop"), 66 MIB_DESC(1, 0xb8, "RxArlDrop"), 67 }; 68 69 static int 70 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) 71 { 72 int ret; 73 74 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); 75 if (ret < 0) 76 dev_err(priv->dev, 77 "failed to priv write register\n"); 78 return ret; 79 } 80 81 static u32 82 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) 83 { 84 int ret; 85 u32 val; 86 87 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); 88 if (ret < 0) { 89 dev_err(priv->dev, 90 "failed to priv read register\n"); 91 return ret; 92 } 93 94 return val; 95 } 96 97 static void 98 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, 99 u32 mask, u32 set) 100 { 101 u32 val; 102 103 val = mt7623_trgmii_read(priv, reg); 104 val &= ~mask; 105 val |= set; 106 mt7623_trgmii_write(priv, reg, val); 107 } 108 109 static void 110 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) 111 { 112 mt7623_trgmii_rmw(priv, reg, 0, val); 113 } 114 115 static void 116 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) 117 { 118 mt7623_trgmii_rmw(priv, reg, val, 0); 119 } 120 121 static int 122 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 123 { 124 struct mii_bus *bus = priv->bus; 125 int value, ret; 126 127 /* Write the desired MMD Devad */ 128 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 129 if (ret < 0) 130 goto err; 131 132 /* Write the desired MMD register address */ 133 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 134 if (ret < 0) 135 goto err; 136 137 /* Select the Function : DATA with no post increment */ 138 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 139 if (ret < 0) 140 goto err; 141 142 /* Read the content of the MMD's selected register */ 143 value = bus->read(bus, 0, MII_MMD_DATA); 144 145 return value; 146 err: 147 dev_err(&bus->dev, "failed to read mmd register\n"); 148 149 return ret; 150 } 151 152 static int 153 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 154 int devad, u32 data) 155 { 156 struct mii_bus *bus = priv->bus; 157 int ret; 158 159 /* Write the desired MMD Devad */ 160 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 161 if (ret < 0) 162 goto err; 163 164 /* Write the desired MMD register address */ 165 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 166 if (ret < 0) 167 goto err; 168 169 /* Select the Function : DATA with no post increment */ 170 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 171 if (ret < 0) 172 goto err; 173 174 /* Write the data into MMD's selected register */ 175 ret = bus->write(bus, 0, MII_MMD_DATA, data); 176 err: 177 if (ret < 0) 178 dev_err(&bus->dev, 179 "failed to write mmd register\n"); 180 return ret; 181 } 182 183 static void 184 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 struct mii_bus *bus = priv->bus; 187 188 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 189 190 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 191 192 mutex_unlock(&bus->mdio_lock); 193 } 194 195 static void 196 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 197 { 198 struct mii_bus *bus = priv->bus; 199 u32 val; 200 201 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 202 203 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 204 val &= ~mask; 205 val |= set; 206 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 207 208 mutex_unlock(&bus->mdio_lock); 209 } 210 211 static void 212 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 213 { 214 core_rmw(priv, reg, 0, val); 215 } 216 217 static void 218 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 219 { 220 core_rmw(priv, reg, val, 0); 221 } 222 223 static int 224 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 225 { 226 struct mii_bus *bus = priv->bus; 227 u16 page, r, lo, hi; 228 int ret; 229 230 page = (reg >> 6) & 0x3ff; 231 r = (reg >> 2) & 0xf; 232 lo = val & 0xffff; 233 hi = val >> 16; 234 235 /* MT7530 uses 31 as the pseudo port */ 236 ret = bus->write(bus, 0x1f, 0x1f, page); 237 if (ret < 0) 238 goto err; 239 240 ret = bus->write(bus, 0x1f, r, lo); 241 if (ret < 0) 242 goto err; 243 244 ret = bus->write(bus, 0x1f, 0x10, hi); 245 err: 246 if (ret < 0) 247 dev_err(&bus->dev, 248 "failed to write mt7530 register\n"); 249 return ret; 250 } 251 252 static u32 253 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 254 { 255 struct mii_bus *bus = priv->bus; 256 u16 page, r, lo, hi; 257 int ret; 258 259 page = (reg >> 6) & 0x3ff; 260 r = (reg >> 2) & 0xf; 261 262 /* MT7530 uses 31 as the pseudo port */ 263 ret = bus->write(bus, 0x1f, 0x1f, page); 264 if (ret < 0) { 265 dev_err(&bus->dev, 266 "failed to read mt7530 register\n"); 267 return ret; 268 } 269 270 lo = bus->read(bus, 0x1f, r); 271 hi = bus->read(bus, 0x1f, 0x10); 272 273 return (hi << 16) | (lo & 0xffff); 274 } 275 276 static void 277 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 struct mii_bus *bus = priv->bus; 280 281 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 282 283 mt7530_mii_write(priv, reg, val); 284 285 mutex_unlock(&bus->mdio_lock); 286 } 287 288 static u32 289 _mt7530_read(struct mt7530_dummy_poll *p) 290 { 291 struct mii_bus *bus = p->priv->bus; 292 u32 val; 293 294 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 295 296 val = mt7530_mii_read(p->priv, p->reg); 297 298 mutex_unlock(&bus->mdio_lock); 299 300 return val; 301 } 302 303 static u32 304 mt7530_read(struct mt7530_priv *priv, u32 reg) 305 { 306 struct mt7530_dummy_poll p; 307 308 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 309 return _mt7530_read(&p); 310 } 311 312 static void 313 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 314 u32 mask, u32 set) 315 { 316 struct mii_bus *bus = priv->bus; 317 u32 val; 318 319 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 320 321 val = mt7530_mii_read(priv, reg); 322 val &= ~mask; 323 val |= set; 324 mt7530_mii_write(priv, reg, val); 325 326 mutex_unlock(&bus->mdio_lock); 327 } 328 329 static void 330 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 331 { 332 mt7530_rmw(priv, reg, 0, val); 333 } 334 335 static void 336 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 337 { 338 mt7530_rmw(priv, reg, val, 0); 339 } 340 341 static int 342 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 343 { 344 u32 val; 345 int ret; 346 struct mt7530_dummy_poll p; 347 348 /* Set the command operating upon the MAC address entries */ 349 val = ATC_BUSY | ATC_MAT(0) | cmd; 350 mt7530_write(priv, MT7530_ATC, val); 351 352 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 353 ret = readx_poll_timeout(_mt7530_read, &p, val, 354 !(val & ATC_BUSY), 20, 20000); 355 if (ret < 0) { 356 dev_err(priv->dev, "reset timeout\n"); 357 return ret; 358 } 359 360 /* Additional sanity for read command if the specified 361 * entry is invalid 362 */ 363 val = mt7530_read(priv, MT7530_ATC); 364 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 365 return -EINVAL; 366 367 if (rsp) 368 *rsp = val; 369 370 return 0; 371 } 372 373 static void 374 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 375 { 376 u32 reg[3]; 377 int i; 378 379 /* Read from ARL table into an array */ 380 for (i = 0; i < 3; i++) { 381 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 382 383 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 384 __func__, __LINE__, i, reg[i]); 385 } 386 387 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 388 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 389 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 390 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 391 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 392 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 393 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 394 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 395 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 396 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 397 } 398 399 static void 400 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 401 u8 port_mask, const u8 *mac, 402 u8 aging, u8 type) 403 { 404 u32 reg[3] = { 0 }; 405 int i; 406 407 reg[1] |= vid & CVID_MASK; 408 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 409 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 410 /* STATIC_ENT indicate that entry is static wouldn't 411 * be aged out and STATIC_EMP specified as erasing an 412 * entry 413 */ 414 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 415 reg[1] |= mac[5] << MAC_BYTE_5; 416 reg[1] |= mac[4] << MAC_BYTE_4; 417 reg[0] |= mac[3] << MAC_BYTE_3; 418 reg[0] |= mac[2] << MAC_BYTE_2; 419 reg[0] |= mac[1] << MAC_BYTE_1; 420 reg[0] |= mac[0] << MAC_BYTE_0; 421 422 /* Write array into the ARL table */ 423 for (i = 0; i < 3; i++) 424 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 425 } 426 427 static int 428 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) 429 { 430 struct mt7530_priv *priv = ds->priv; 431 u32 ncpo1, ssc_delta, trgint, i; 432 433 switch (mode) { 434 case PHY_INTERFACE_MODE_RGMII: 435 trgint = 0; 436 ncpo1 = 0x0c80; 437 ssc_delta = 0x87; 438 break; 439 case PHY_INTERFACE_MODE_TRGMII: 440 trgint = 1; 441 ncpo1 = 0x1400; 442 ssc_delta = 0x57; 443 break; 444 default: 445 dev_err(priv->dev, "xMII mode %d not supported\n", mode); 446 return -EINVAL; 447 } 448 449 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 450 P6_INTF_MODE(trgint)); 451 452 /* Lower Tx Driving for TRGMII path */ 453 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 454 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 455 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 456 457 /* Setup core clock for MT7530 */ 458 if (!trgint) { 459 /* Disable MT7530 core clock */ 460 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 461 462 /* Disable PLL, since phy_device has not yet been created 463 * provided for phy_[read,write]_mmd_indirect is called, we 464 * provide our own core_write_mmd_indirect to complete this 465 * function. 466 */ 467 core_write_mmd_indirect(priv, 468 CORE_GSWPLL_GRP1, 469 MDIO_MMD_VEND2, 470 0); 471 472 /* Set core clock into 500Mhz */ 473 core_write(priv, CORE_GSWPLL_GRP2, 474 RG_GSWPLL_POSDIV_500M(1) | 475 RG_GSWPLL_FBKDIV_500M(25)); 476 477 /* Enable PLL */ 478 core_write(priv, CORE_GSWPLL_GRP1, 479 RG_GSWPLL_EN_PRE | 480 RG_GSWPLL_POSDIV_200M(2) | 481 RG_GSWPLL_FBKDIV_200M(32)); 482 483 /* Enable MT7530 core clock */ 484 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 485 } 486 487 /* Setup the MT7530 TRGMII Tx Clock */ 488 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 489 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 490 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 491 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 492 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 493 core_write(priv, CORE_PLL_GROUP4, 494 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 495 RG_SYSPLL_BIAS_LPF_EN); 496 core_write(priv, CORE_PLL_GROUP2, 497 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 498 RG_SYSPLL_POSDIV(1)); 499 core_write(priv, CORE_PLL_GROUP7, 500 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 501 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 502 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 503 REG_GSWCK_EN | REG_TRGMIICK_EN); 504 505 if (!trgint) 506 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 507 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 508 RD_TAP_MASK, RD_TAP(16)); 509 else 510 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII); 511 512 return 0; 513 } 514 515 static int 516 mt7623_pad_clk_setup(struct dsa_switch *ds) 517 { 518 struct mt7530_priv *priv = ds->priv; 519 int i; 520 521 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 522 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), 523 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 524 525 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); 526 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); 527 528 return 0; 529 } 530 531 static void 532 mt7530_mib_reset(struct dsa_switch *ds) 533 { 534 struct mt7530_priv *priv = ds->priv; 535 536 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 537 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 538 } 539 540 static void 541 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) 542 { 543 u32 mask = PMCR_TX_EN | PMCR_RX_EN; 544 545 if (enable) 546 mt7530_set(priv, MT7530_PMCR_P(port), mask); 547 else 548 mt7530_clear(priv, MT7530_PMCR_P(port), mask); 549 } 550 551 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 552 { 553 struct mt7530_priv *priv = ds->priv; 554 555 return mdiobus_read_nested(priv->bus, port, regnum); 556 } 557 558 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 559 u16 val) 560 { 561 struct mt7530_priv *priv = ds->priv; 562 563 return mdiobus_write_nested(priv->bus, port, regnum, val); 564 } 565 566 static void 567 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 568 uint8_t *data) 569 { 570 int i; 571 572 if (stringset != ETH_SS_STATS) 573 return; 574 575 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 576 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 577 ETH_GSTRING_LEN); 578 } 579 580 static void 581 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 582 uint64_t *data) 583 { 584 struct mt7530_priv *priv = ds->priv; 585 const struct mt7530_mib_desc *mib; 586 u32 reg, i; 587 u64 hi; 588 589 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 590 mib = &mt7530_mib[i]; 591 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 592 593 data[i] = mt7530_read(priv, reg); 594 if (mib->size == 2) { 595 hi = mt7530_read(priv, reg + 4); 596 data[i] |= hi << 32; 597 } 598 } 599 } 600 601 static int 602 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 603 { 604 if (sset != ETH_SS_STATS) 605 return 0; 606 607 return ARRAY_SIZE(mt7530_mib); 608 } 609 610 static void mt7530_adjust_link(struct dsa_switch *ds, int port, 611 struct phy_device *phydev) 612 { 613 struct mt7530_priv *priv = ds->priv; 614 615 if (phy_is_pseudo_fixed_link(phydev)) { 616 if (priv->id == ID_MT7530) { 617 dev_dbg(priv->dev, "phy-mode for master device = %x\n", 618 phydev->interface); 619 620 /* Setup TX circuit incluing relevant PAD and driving */ 621 mt7530_pad_clk_setup(ds, phydev->interface); 622 623 /* Setup RX circuit, relevant PAD and driving on the 624 * host which must be placed after the setup on the 625 * device side is all finished. 626 */ 627 mt7623_pad_clk_setup(ds); 628 } 629 } else { 630 u16 lcl_adv = 0, rmt_adv = 0; 631 u8 flowctrl; 632 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE; 633 634 switch (phydev->speed) { 635 case SPEED_1000: 636 mcr |= PMCR_FORCE_SPEED_1000; 637 break; 638 case SPEED_100: 639 mcr |= PMCR_FORCE_SPEED_100; 640 break; 641 } 642 643 if (phydev->link) 644 mcr |= PMCR_FORCE_LNK; 645 646 if (phydev->duplex) { 647 mcr |= PMCR_FORCE_FDX; 648 649 if (phydev->pause) 650 rmt_adv = LPA_PAUSE_CAP; 651 if (phydev->asym_pause) 652 rmt_adv |= LPA_PAUSE_ASYM; 653 654 lcl_adv = linkmode_adv_to_lcl_adv_t( 655 phydev->advertising); 656 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 657 658 if (flowctrl & FLOW_CTRL_TX) 659 mcr |= PMCR_TX_FC_EN; 660 if (flowctrl & FLOW_CTRL_RX) 661 mcr |= PMCR_RX_FC_EN; 662 } 663 mt7530_write(priv, MT7530_PMCR_P(port), mcr); 664 } 665 } 666 667 static int 668 mt7530_cpu_port_enable(struct mt7530_priv *priv, 669 int port) 670 { 671 /* Enable Mediatek header mode on the cpu port */ 672 mt7530_write(priv, MT7530_PVC_P(port), 673 PORT_SPEC_TAG); 674 675 /* Setup the MAC by default for the cpu port */ 676 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK); 677 678 /* Disable auto learning on the cpu port */ 679 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); 680 681 /* Unknown unicast frame fordwarding to the cpu port */ 682 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); 683 684 /* Set CPU port number */ 685 if (priv->id == ID_MT7621) 686 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 687 688 /* CPU port gets connected to all user ports of 689 * the switch 690 */ 691 mt7530_write(priv, MT7530_PCR_P(port), 692 PCR_MATRIX(dsa_user_ports(priv->ds))); 693 694 return 0; 695 } 696 697 static int 698 mt7530_port_enable(struct dsa_switch *ds, int port, 699 struct phy_device *phy) 700 { 701 struct mt7530_priv *priv = ds->priv; 702 703 mutex_lock(&priv->reg_mutex); 704 705 /* Setup the MAC for the user port */ 706 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK); 707 708 /* Allow the user port gets connected to the cpu port and also 709 * restore the port matrix if the port is the member of a certain 710 * bridge. 711 */ 712 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 713 priv->ports[port].enable = true; 714 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 715 priv->ports[port].pm); 716 mt7530_port_set_status(priv, port, 1); 717 718 mutex_unlock(&priv->reg_mutex); 719 720 return 0; 721 } 722 723 static void 724 mt7530_port_disable(struct dsa_switch *ds, int port) 725 { 726 struct mt7530_priv *priv = ds->priv; 727 728 mutex_lock(&priv->reg_mutex); 729 730 /* Clear up all port matrix which could be restored in the next 731 * enablement for the port. 732 */ 733 priv->ports[port].enable = false; 734 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 735 PCR_MATRIX_CLR); 736 mt7530_port_set_status(priv, port, 0); 737 738 mutex_unlock(&priv->reg_mutex); 739 } 740 741 static void 742 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 743 { 744 struct mt7530_priv *priv = ds->priv; 745 u32 stp_state; 746 747 switch (state) { 748 case BR_STATE_DISABLED: 749 stp_state = MT7530_STP_DISABLED; 750 break; 751 case BR_STATE_BLOCKING: 752 stp_state = MT7530_STP_BLOCKING; 753 break; 754 case BR_STATE_LISTENING: 755 stp_state = MT7530_STP_LISTENING; 756 break; 757 case BR_STATE_LEARNING: 758 stp_state = MT7530_STP_LEARNING; 759 break; 760 case BR_STATE_FORWARDING: 761 default: 762 stp_state = MT7530_STP_FORWARDING; 763 break; 764 } 765 766 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 767 } 768 769 static int 770 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 771 struct net_device *bridge) 772 { 773 struct mt7530_priv *priv = ds->priv; 774 u32 port_bitmap = BIT(MT7530_CPU_PORT); 775 int i; 776 777 mutex_lock(&priv->reg_mutex); 778 779 for (i = 0; i < MT7530_NUM_PORTS; i++) { 780 /* Add this port to the port matrix of the other ports in the 781 * same bridge. If the port is disabled, port matrix is kept 782 * and not being setup until the port becomes enabled. 783 */ 784 if (dsa_is_user_port(ds, i) && i != port) { 785 if (dsa_to_port(ds, i)->bridge_dev != bridge) 786 continue; 787 if (priv->ports[i].enable) 788 mt7530_set(priv, MT7530_PCR_P(i), 789 PCR_MATRIX(BIT(port))); 790 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 791 792 port_bitmap |= BIT(i); 793 } 794 } 795 796 /* Add the all other ports to this port matrix. */ 797 if (priv->ports[port].enable) 798 mt7530_rmw(priv, MT7530_PCR_P(port), 799 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 800 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 801 802 mutex_unlock(&priv->reg_mutex); 803 804 return 0; 805 } 806 807 static void 808 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 809 { 810 struct mt7530_priv *priv = ds->priv; 811 bool all_user_ports_removed = true; 812 int i; 813 814 /* When a port is removed from the bridge, the port would be set up 815 * back to the default as is at initial boot which is a VLAN-unaware 816 * port. 817 */ 818 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 819 MT7530_PORT_MATRIX_MODE); 820 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 821 VLAN_ATTR(MT7530_VLAN_TRANSPARENT)); 822 823 for (i = 0; i < MT7530_NUM_PORTS; i++) { 824 if (dsa_is_user_port(ds, i) && 825 dsa_port_is_vlan_filtering(&ds->ports[i])) { 826 all_user_ports_removed = false; 827 break; 828 } 829 } 830 831 /* CPU port also does the same thing until all user ports belonging to 832 * the CPU port get out of VLAN filtering mode. 833 */ 834 if (all_user_ports_removed) { 835 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 836 PCR_MATRIX(dsa_user_ports(priv->ds))); 837 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), 838 PORT_SPEC_TAG); 839 } 840 } 841 842 static void 843 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 844 { 845 struct mt7530_priv *priv = ds->priv; 846 847 /* The real fabric path would be decided on the membership in the 848 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 849 * means potential VLAN can be consisting of certain subset of all 850 * ports. 851 */ 852 mt7530_rmw(priv, MT7530_PCR_P(port), 853 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 854 855 /* Trapped into security mode allows packet forwarding through VLAN 856 * table lookup. 857 */ 858 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 859 MT7530_PORT_SECURITY_MODE); 860 861 /* Set the port as a user port which is to be able to recognize VID 862 * from incoming packets before fetching entry within the VLAN table. 863 */ 864 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 865 VLAN_ATTR(MT7530_VLAN_USER)); 866 } 867 868 static void 869 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 870 struct net_device *bridge) 871 { 872 struct mt7530_priv *priv = ds->priv; 873 int i; 874 875 mutex_lock(&priv->reg_mutex); 876 877 for (i = 0; i < MT7530_NUM_PORTS; i++) { 878 /* Remove this port from the port matrix of the other ports 879 * in the same bridge. If the port is disabled, port matrix 880 * is kept and not being setup until the port becomes enabled. 881 * And the other port's port matrix cannot be broken when the 882 * other port is still a VLAN-aware port. 883 */ 884 if (dsa_is_user_port(ds, i) && i != port && 885 !dsa_port_is_vlan_filtering(&ds->ports[i])) { 886 if (dsa_to_port(ds, i)->bridge_dev != bridge) 887 continue; 888 if (priv->ports[i].enable) 889 mt7530_clear(priv, MT7530_PCR_P(i), 890 PCR_MATRIX(BIT(port))); 891 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 892 } 893 } 894 895 /* Set the cpu port to be the only one in the port matrix of 896 * this port. 897 */ 898 if (priv->ports[port].enable) 899 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 900 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 901 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 902 903 mutex_unlock(&priv->reg_mutex); 904 } 905 906 static int 907 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 908 const unsigned char *addr, u16 vid) 909 { 910 struct mt7530_priv *priv = ds->priv; 911 int ret; 912 u8 port_mask = BIT(port); 913 914 mutex_lock(&priv->reg_mutex); 915 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 916 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 917 mutex_unlock(&priv->reg_mutex); 918 919 return ret; 920 } 921 922 static int 923 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 924 const unsigned char *addr, u16 vid) 925 { 926 struct mt7530_priv *priv = ds->priv; 927 int ret; 928 u8 port_mask = BIT(port); 929 930 mutex_lock(&priv->reg_mutex); 931 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 932 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 933 mutex_unlock(&priv->reg_mutex); 934 935 return ret; 936 } 937 938 static int 939 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 940 dsa_fdb_dump_cb_t *cb, void *data) 941 { 942 struct mt7530_priv *priv = ds->priv; 943 struct mt7530_fdb _fdb = { 0 }; 944 int cnt = MT7530_NUM_FDB_RECORDS; 945 int ret = 0; 946 u32 rsp = 0; 947 948 mutex_lock(&priv->reg_mutex); 949 950 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 951 if (ret < 0) 952 goto err; 953 954 do { 955 if (rsp & ATC_SRCH_HIT) { 956 mt7530_fdb_read(priv, &_fdb); 957 if (_fdb.port_mask & BIT(port)) { 958 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 959 data); 960 if (ret < 0) 961 break; 962 } 963 } 964 } while (--cnt && 965 !(rsp & ATC_SRCH_END) && 966 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 967 err: 968 mutex_unlock(&priv->reg_mutex); 969 970 return 0; 971 } 972 973 static int 974 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 975 { 976 struct mt7530_dummy_poll p; 977 u32 val; 978 int ret; 979 980 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 981 mt7530_write(priv, MT7530_VTCR, val); 982 983 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 984 ret = readx_poll_timeout(_mt7530_read, &p, val, 985 !(val & VTCR_BUSY), 20, 20000); 986 if (ret < 0) { 987 dev_err(priv->dev, "poll timeout\n"); 988 return ret; 989 } 990 991 val = mt7530_read(priv, MT7530_VTCR); 992 if (val & VTCR_INVALID) { 993 dev_err(priv->dev, "read VTCR invalid\n"); 994 return -EINVAL; 995 } 996 997 return 0; 998 } 999 1000 static int 1001 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, 1002 bool vlan_filtering) 1003 { 1004 if (vlan_filtering) { 1005 /* The port is being kept as VLAN-unaware port when bridge is 1006 * set up with vlan_filtering not being set, Otherwise, the 1007 * port and the corresponding CPU port is required the setup 1008 * for becoming a VLAN-aware port. 1009 */ 1010 mt7530_port_set_vlan_aware(ds, port); 1011 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1012 } else { 1013 mt7530_port_set_vlan_unaware(ds, port); 1014 } 1015 1016 return 0; 1017 } 1018 1019 static int 1020 mt7530_port_vlan_prepare(struct dsa_switch *ds, int port, 1021 const struct switchdev_obj_port_vlan *vlan) 1022 { 1023 /* nothing needed */ 1024 1025 return 0; 1026 } 1027 1028 static void 1029 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1030 struct mt7530_hw_vlan_entry *entry) 1031 { 1032 u8 new_members; 1033 u32 val; 1034 1035 new_members = entry->old_members | BIT(entry->port) | 1036 BIT(MT7530_CPU_PORT); 1037 1038 /* Validate the entry with independent learning, create egress tag per 1039 * VLAN and joining the port as one of the port members. 1040 */ 1041 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1042 mt7530_write(priv, MT7530_VAWD1, val); 1043 1044 /* Decide whether adding tag or not for those outgoing packets from the 1045 * port inside the VLAN. 1046 */ 1047 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1048 MT7530_VLAN_EGRESS_TAG; 1049 mt7530_rmw(priv, MT7530_VAWD2, 1050 ETAG_CTRL_P_MASK(entry->port), 1051 ETAG_CTRL_P(entry->port, val)); 1052 1053 /* CPU port is always taken as a tagged port for serving more than one 1054 * VLANs across and also being applied with egress type stack mode for 1055 * that VLAN tags would be appended after hardware special tag used as 1056 * DSA tag. 1057 */ 1058 mt7530_rmw(priv, MT7530_VAWD2, 1059 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1060 ETAG_CTRL_P(MT7530_CPU_PORT, 1061 MT7530_VLAN_EGRESS_STACK)); 1062 } 1063 1064 static void 1065 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1066 struct mt7530_hw_vlan_entry *entry) 1067 { 1068 u8 new_members; 1069 u32 val; 1070 1071 new_members = entry->old_members & ~BIT(entry->port); 1072 1073 val = mt7530_read(priv, MT7530_VAWD1); 1074 if (!(val & VLAN_VALID)) { 1075 dev_err(priv->dev, 1076 "Cannot be deleted due to invalid entry\n"); 1077 return; 1078 } 1079 1080 /* If certain member apart from CPU port is still alive in the VLAN, 1081 * the entry would be kept valid. Otherwise, the entry is got to be 1082 * disabled. 1083 */ 1084 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1085 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1086 VLAN_VALID; 1087 mt7530_write(priv, MT7530_VAWD1, val); 1088 } else { 1089 mt7530_write(priv, MT7530_VAWD1, 0); 1090 mt7530_write(priv, MT7530_VAWD2, 0); 1091 } 1092 } 1093 1094 static void 1095 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1096 struct mt7530_hw_vlan_entry *entry, 1097 mt7530_vlan_op vlan_op) 1098 { 1099 u32 val; 1100 1101 /* Fetch entry */ 1102 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1103 1104 val = mt7530_read(priv, MT7530_VAWD1); 1105 1106 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1107 1108 /* Manipulate entry */ 1109 vlan_op(priv, entry); 1110 1111 /* Flush result to hardware */ 1112 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1113 } 1114 1115 static void 1116 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1117 const struct switchdev_obj_port_vlan *vlan) 1118 { 1119 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1120 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1121 struct mt7530_hw_vlan_entry new_entry; 1122 struct mt7530_priv *priv = ds->priv; 1123 u16 vid; 1124 1125 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1126 * being set. 1127 */ 1128 if (!dsa_port_is_vlan_filtering(&ds->ports[port])) 1129 return; 1130 1131 mutex_lock(&priv->reg_mutex); 1132 1133 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1134 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1135 mt7530_hw_vlan_update(priv, vid, &new_entry, 1136 mt7530_hw_vlan_add); 1137 } 1138 1139 if (pvid) { 1140 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1141 G0_PORT_VID(vlan->vid_end)); 1142 priv->ports[port].pvid = vlan->vid_end; 1143 } 1144 1145 mutex_unlock(&priv->reg_mutex); 1146 } 1147 1148 static int 1149 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1150 const struct switchdev_obj_port_vlan *vlan) 1151 { 1152 struct mt7530_hw_vlan_entry target_entry; 1153 struct mt7530_priv *priv = ds->priv; 1154 u16 vid, pvid; 1155 1156 /* The port is kept as VLAN-unaware if bridge with vlan_filtering not 1157 * being set. 1158 */ 1159 if (!dsa_port_is_vlan_filtering(&ds->ports[port])) 1160 return 0; 1161 1162 mutex_lock(&priv->reg_mutex); 1163 1164 pvid = priv->ports[port].pvid; 1165 for (vid = vlan->vid_begin; vid <= vlan->vid_end; ++vid) { 1166 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1167 mt7530_hw_vlan_update(priv, vid, &target_entry, 1168 mt7530_hw_vlan_del); 1169 1170 /* PVID is being restored to the default whenever the PVID port 1171 * is being removed from the VLAN. 1172 */ 1173 if (pvid == vid) 1174 pvid = G0_PORT_VID_DEF; 1175 } 1176 1177 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1178 priv->ports[port].pvid = pvid; 1179 1180 mutex_unlock(&priv->reg_mutex); 1181 1182 return 0; 1183 } 1184 1185 static enum dsa_tag_protocol 1186 mtk_get_tag_protocol(struct dsa_switch *ds, int port) 1187 { 1188 struct mt7530_priv *priv = ds->priv; 1189 1190 if (port != MT7530_CPU_PORT) { 1191 dev_warn(priv->dev, 1192 "port not matched with tagging CPU port\n"); 1193 return DSA_TAG_PROTO_NONE; 1194 } else { 1195 return DSA_TAG_PROTO_MTK; 1196 } 1197 } 1198 1199 static int 1200 mt7530_setup(struct dsa_switch *ds) 1201 { 1202 struct mt7530_priv *priv = ds->priv; 1203 int ret, i; 1204 u32 id, val; 1205 struct device_node *dn; 1206 struct mt7530_dummy_poll p; 1207 1208 /* The parent node of master netdev which holds the common system 1209 * controller also is the container for two GMACs nodes representing 1210 * as two netdev instances. 1211 */ 1212 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent; 1213 1214 if (priv->id == ID_MT7530) { 1215 priv->ethernet = syscon_node_to_regmap(dn); 1216 if (IS_ERR(priv->ethernet)) 1217 return PTR_ERR(priv->ethernet); 1218 1219 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1220 ret = regulator_enable(priv->core_pwr); 1221 if (ret < 0) { 1222 dev_err(priv->dev, 1223 "Failed to enable core power: %d\n", ret); 1224 return ret; 1225 } 1226 1227 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1228 ret = regulator_enable(priv->io_pwr); 1229 if (ret < 0) { 1230 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1231 ret); 1232 return ret; 1233 } 1234 } 1235 1236 /* Reset whole chip through gpio pin or memory-mapped registers for 1237 * different type of hardware 1238 */ 1239 if (priv->mcm) { 1240 reset_control_assert(priv->rstc); 1241 usleep_range(1000, 1100); 1242 reset_control_deassert(priv->rstc); 1243 } else { 1244 gpiod_set_value_cansleep(priv->reset, 0); 1245 usleep_range(1000, 1100); 1246 gpiod_set_value_cansleep(priv->reset, 1); 1247 } 1248 1249 /* Waiting for MT7530 got to stable */ 1250 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1251 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1252 20, 1000000); 1253 if (ret < 0) { 1254 dev_err(priv->dev, "reset timeout\n"); 1255 return ret; 1256 } 1257 1258 id = mt7530_read(priv, MT7530_CREV); 1259 id >>= CHIP_NAME_SHIFT; 1260 if (id != MT7530_ID) { 1261 dev_err(priv->dev, "chip %x can't be supported\n", id); 1262 return -ENODEV; 1263 } 1264 1265 /* Reset the switch through internal reset */ 1266 mt7530_write(priv, MT7530_SYS_CTRL, 1267 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1268 SYS_CTRL_REG_RST); 1269 1270 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1271 val = mt7530_read(priv, MT7530_MHWTRAP); 1272 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1273 val |= MHWTRAP_MANUAL; 1274 mt7530_write(priv, MT7530_MHWTRAP, val); 1275 1276 /* Enable and reset MIB counters */ 1277 mt7530_mib_reset(ds); 1278 1279 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); 1280 1281 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1282 /* Disable forwarding by default on all ports */ 1283 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1284 PCR_MATRIX_CLR); 1285 1286 if (dsa_is_cpu_port(ds, i)) 1287 mt7530_cpu_port_enable(priv, i); 1288 else 1289 mt7530_port_disable(ds, i); 1290 } 1291 1292 /* Flush the FDB table */ 1293 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1294 if (ret < 0) 1295 return ret; 1296 1297 return 0; 1298 } 1299 1300 static const struct dsa_switch_ops mt7530_switch_ops = { 1301 .get_tag_protocol = mtk_get_tag_protocol, 1302 .setup = mt7530_setup, 1303 .get_strings = mt7530_get_strings, 1304 .phy_read = mt7530_phy_read, 1305 .phy_write = mt7530_phy_write, 1306 .get_ethtool_stats = mt7530_get_ethtool_stats, 1307 .get_sset_count = mt7530_get_sset_count, 1308 .adjust_link = mt7530_adjust_link, 1309 .port_enable = mt7530_port_enable, 1310 .port_disable = mt7530_port_disable, 1311 .port_stp_state_set = mt7530_stp_state_set, 1312 .port_bridge_join = mt7530_port_bridge_join, 1313 .port_bridge_leave = mt7530_port_bridge_leave, 1314 .port_fdb_add = mt7530_port_fdb_add, 1315 .port_fdb_del = mt7530_port_fdb_del, 1316 .port_fdb_dump = mt7530_port_fdb_dump, 1317 .port_vlan_filtering = mt7530_port_vlan_filtering, 1318 .port_vlan_prepare = mt7530_port_vlan_prepare, 1319 .port_vlan_add = mt7530_port_vlan_add, 1320 .port_vlan_del = mt7530_port_vlan_del, 1321 }; 1322 1323 static const struct of_device_id mt7530_of_match[] = { 1324 { .compatible = "mediatek,mt7621", .data = (void *)ID_MT7621, }, 1325 { .compatible = "mediatek,mt7530", .data = (void *)ID_MT7530, }, 1326 { /* sentinel */ }, 1327 }; 1328 MODULE_DEVICE_TABLE(of, mt7530_of_match); 1329 1330 static int 1331 mt7530_probe(struct mdio_device *mdiodev) 1332 { 1333 struct mt7530_priv *priv; 1334 struct device_node *dn; 1335 1336 dn = mdiodev->dev.of_node; 1337 1338 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1339 if (!priv) 1340 return -ENOMEM; 1341 1342 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS); 1343 if (!priv->ds) 1344 return -ENOMEM; 1345 1346 /* Use medatek,mcm property to distinguish hardware type that would 1347 * casues a little bit differences on power-on sequence. 1348 */ 1349 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 1350 if (priv->mcm) { 1351 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 1352 1353 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 1354 if (IS_ERR(priv->rstc)) { 1355 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1356 return PTR_ERR(priv->rstc); 1357 } 1358 } 1359 1360 /* Get the hardware identifier from the devicetree node. 1361 * We will need it for some of the clock and regulator setup. 1362 */ 1363 priv->id = (unsigned int)(unsigned long) 1364 of_device_get_match_data(&mdiodev->dev); 1365 1366 if (priv->id == ID_MT7530) { 1367 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 1368 if (IS_ERR(priv->core_pwr)) 1369 return PTR_ERR(priv->core_pwr); 1370 1371 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 1372 if (IS_ERR(priv->io_pwr)) 1373 return PTR_ERR(priv->io_pwr); 1374 } 1375 1376 /* Not MCM that indicates switch works as the remote standalone 1377 * integrated circuit so the GPIO pin would be used to complete 1378 * the reset, otherwise memory-mapped register accessing used 1379 * through syscon provides in the case of MCM. 1380 */ 1381 if (!priv->mcm) { 1382 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 1383 GPIOD_OUT_LOW); 1384 if (IS_ERR(priv->reset)) { 1385 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1386 return PTR_ERR(priv->reset); 1387 } 1388 } 1389 1390 priv->bus = mdiodev->bus; 1391 priv->dev = &mdiodev->dev; 1392 priv->ds->priv = priv; 1393 priv->ds->ops = &mt7530_switch_ops; 1394 mutex_init(&priv->reg_mutex); 1395 dev_set_drvdata(&mdiodev->dev, priv); 1396 1397 return dsa_register_switch(priv->ds); 1398 } 1399 1400 static void 1401 mt7530_remove(struct mdio_device *mdiodev) 1402 { 1403 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 1404 int ret = 0; 1405 1406 ret = regulator_disable(priv->core_pwr); 1407 if (ret < 0) 1408 dev_err(priv->dev, 1409 "Failed to disable core power: %d\n", ret); 1410 1411 ret = regulator_disable(priv->io_pwr); 1412 if (ret < 0) 1413 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 1414 ret); 1415 1416 dsa_unregister_switch(priv->ds); 1417 mutex_destroy(&priv->reg_mutex); 1418 } 1419 1420 static struct mdio_driver mt7530_mdio_driver = { 1421 .probe = mt7530_probe, 1422 .remove = mt7530_remove, 1423 .mdiodrv.driver = { 1424 .name = "mt7530", 1425 .of_match_table = mt7530_of_match, 1426 }, 1427 }; 1428 1429 mdio_module_driver(mt7530_mdio_driver); 1430 1431 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1432 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 1433 MODULE_LICENSE("GPL"); 1434