1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149 } 150 151 static void 152 mt7530_mutex_unlock(struct mt7530_priv *priv) 153 { 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156 } 157 158 static void 159 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160 { 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166 } 167 168 static void 169 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170 { 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181 } 182 183 static void 184 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 core_rmw(priv, reg, 0, val); 187 } 188 189 static void 190 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191 { 192 core_rmw(priv, reg, val, 0); 193 } 194 195 static int 196 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197 { 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207 } 208 209 static u32 210 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211 { 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224 } 225 226 static void 227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static u32 237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238 { 239 return mt7530_mii_read(p->priv, p->reg); 240 } 241 242 static u32 243 _mt7530_read(struct mt7530_dummy_poll *p) 244 { 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254 } 255 256 static u32 257 mt7530_read(struct mt7530_priv *priv, u32 reg) 258 { 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263 } 264 265 static void 266 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268 { 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274 } 275 276 static void 277 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 mt7530_rmw(priv, reg, val, val); 280 } 281 282 static void 283 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284 { 285 mt7530_rmw(priv, reg, val, 0); 286 } 287 288 static int 289 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290 { 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318 } 319 320 static void 321 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322 { 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344 } 345 346 static void 347 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350 { 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374 } 375 376 /* Set up switch core clock for MT7530 */ 377 static void mt7530_pll_setup(struct mt7530_priv *priv) 378 { 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400 } 401 402 /* Setup port 6 interface mode and TRGMII TX circuit */ 403 static int 404 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 405 { 406 struct mt7530_priv *priv = ds->priv; 407 u32 ncpo1, ssc_delta, trgint, xtal; 408 409 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 410 411 if (xtal == HWTRAP_XTAL_20MHZ) { 412 dev_err(priv->dev, 413 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 414 __func__); 415 return -EINVAL; 416 } 417 418 switch (interface) { 419 case PHY_INTERFACE_MODE_RGMII: 420 trgint = 0; 421 break; 422 case PHY_INTERFACE_MODE_TRGMII: 423 trgint = 1; 424 if (xtal == HWTRAP_XTAL_25MHZ) 425 ssc_delta = 0x57; 426 else 427 ssc_delta = 0x87; 428 if (priv->id == ID_MT7621) { 429 /* PLL frequency: 125MHz: 1.0GBit */ 430 if (xtal == HWTRAP_XTAL_40MHZ) 431 ncpo1 = 0x0640; 432 if (xtal == HWTRAP_XTAL_25MHZ) 433 ncpo1 = 0x0a00; 434 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 435 if (xtal == HWTRAP_XTAL_40MHZ) 436 ncpo1 = 0x0c80; 437 if (xtal == HWTRAP_XTAL_25MHZ) 438 ncpo1 = 0x1400; 439 } 440 break; 441 default: 442 dev_err(priv->dev, "xMII interface %d not supported\n", 443 interface); 444 return -EINVAL; 445 } 446 447 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 448 P6_INTF_MODE(trgint)); 449 450 if (trgint) { 451 /* Disable the MT7530 TRGMII clocks */ 452 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 453 454 /* Setup the MT7530 TRGMII Tx Clock */ 455 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 456 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 457 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 458 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 459 core_write(priv, CORE_PLL_GROUP4, 460 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 461 RG_SYSPLL_BIAS_LPF_EN); 462 core_write(priv, CORE_PLL_GROUP2, 463 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 464 RG_SYSPLL_POSDIV(1)); 465 core_write(priv, CORE_PLL_GROUP7, 466 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 467 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 468 469 /* Enable the MT7530 TRGMII clocks */ 470 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 471 } 472 473 return 0; 474 } 475 476 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 477 { 478 u32 val; 479 480 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 481 482 return (val & PAD_DUAL_SGMII_EN) != 0; 483 } 484 485 static int 486 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 487 { 488 return 0; 489 } 490 491 static void 492 mt7531_pll_setup(struct mt7530_priv *priv) 493 { 494 u32 top_sig; 495 u32 hwstrap; 496 u32 xtal; 497 u32 val; 498 499 if (mt7531_dual_sgmii_supported(priv)) 500 return; 501 502 val = mt7530_read(priv, MT7531_CREV); 503 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 504 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 505 if ((val & CHIP_REV_M) > 0) 506 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 507 HWTRAP_XTAL_FSEL_25MHZ; 508 else 509 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 510 511 /* Step 1 : Disable MT7531 COREPLL */ 512 val = mt7530_read(priv, MT7531_PLLGP_EN); 513 val &= ~EN_COREPLL; 514 mt7530_write(priv, MT7531_PLLGP_EN, val); 515 516 /* Step 2: switch to XTAL output */ 517 val = mt7530_read(priv, MT7531_PLLGP_EN); 518 val |= SW_CLKSW; 519 mt7530_write(priv, MT7531_PLLGP_EN, val); 520 521 val = mt7530_read(priv, MT7531_PLLGP_CR0); 522 val &= ~RG_COREPLL_EN; 523 mt7530_write(priv, MT7531_PLLGP_CR0, val); 524 525 /* Step 3: disable PLLGP and enable program PLLGP */ 526 val = mt7530_read(priv, MT7531_PLLGP_EN); 527 val |= SW_PLLGP; 528 mt7530_write(priv, MT7531_PLLGP_EN, val); 529 530 /* Step 4: program COREPLL output frequency to 500MHz */ 531 val = mt7530_read(priv, MT7531_PLLGP_CR0); 532 val &= ~RG_COREPLL_POSDIV_M; 533 val |= 2 << RG_COREPLL_POSDIV_S; 534 mt7530_write(priv, MT7531_PLLGP_CR0, val); 535 usleep_range(25, 35); 536 537 switch (xtal) { 538 case HWTRAP_XTAL_FSEL_25MHZ: 539 val = mt7530_read(priv, MT7531_PLLGP_CR0); 540 val &= ~RG_COREPLL_SDM_PCW_M; 541 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 542 mt7530_write(priv, MT7531_PLLGP_CR0, val); 543 break; 544 case HWTRAP_XTAL_FSEL_40MHZ: 545 val = mt7530_read(priv, MT7531_PLLGP_CR0); 546 val &= ~RG_COREPLL_SDM_PCW_M; 547 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 548 mt7530_write(priv, MT7531_PLLGP_CR0, val); 549 break; 550 } 551 552 /* Set feedback divide ratio update signal to high */ 553 val = mt7530_read(priv, MT7531_PLLGP_CR0); 554 val |= RG_COREPLL_SDM_PCW_CHG; 555 mt7530_write(priv, MT7531_PLLGP_CR0, val); 556 /* Wait for at least 16 XTAL clocks */ 557 usleep_range(10, 20); 558 559 /* Step 5: set feedback divide ratio update signal to low */ 560 val = mt7530_read(priv, MT7531_PLLGP_CR0); 561 val &= ~RG_COREPLL_SDM_PCW_CHG; 562 mt7530_write(priv, MT7531_PLLGP_CR0, val); 563 564 /* Enable 325M clock for SGMII */ 565 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 566 567 /* Enable 250SSC clock for RGMII */ 568 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 569 570 /* Step 6: Enable MT7531 PLL */ 571 val = mt7530_read(priv, MT7531_PLLGP_CR0); 572 val |= RG_COREPLL_EN; 573 mt7530_write(priv, MT7531_PLLGP_CR0, val); 574 575 val = mt7530_read(priv, MT7531_PLLGP_EN); 576 val |= EN_COREPLL; 577 mt7530_write(priv, MT7531_PLLGP_EN, val); 578 usleep_range(25, 35); 579 } 580 581 static void 582 mt7530_mib_reset(struct dsa_switch *ds) 583 { 584 struct mt7530_priv *priv = ds->priv; 585 586 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 587 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 588 } 589 590 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 591 { 592 return mdiobus_read_nested(priv->bus, port, regnum); 593 } 594 595 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 596 u16 val) 597 { 598 return mdiobus_write_nested(priv->bus, port, regnum, val); 599 } 600 601 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 602 int devad, int regnum) 603 { 604 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 605 } 606 607 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 608 int regnum, u16 val) 609 { 610 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 611 } 612 613 static int 614 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 615 int regnum) 616 { 617 struct mt7530_dummy_poll p; 618 u32 reg, val; 619 int ret; 620 621 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 622 623 mt7530_mutex_lock(priv); 624 625 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 626 !(val & MT7531_PHY_ACS_ST), 20, 100000); 627 if (ret < 0) { 628 dev_err(priv->dev, "poll timeout\n"); 629 goto out; 630 } 631 632 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 633 MT7531_MDIO_DEV_ADDR(devad) | regnum; 634 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 635 636 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 637 !(val & MT7531_PHY_ACS_ST), 20, 100000); 638 if (ret < 0) { 639 dev_err(priv->dev, "poll timeout\n"); 640 goto out; 641 } 642 643 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 644 MT7531_MDIO_DEV_ADDR(devad); 645 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 646 647 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 648 !(val & MT7531_PHY_ACS_ST), 20, 100000); 649 if (ret < 0) { 650 dev_err(priv->dev, "poll timeout\n"); 651 goto out; 652 } 653 654 ret = val & MT7531_MDIO_RW_DATA_MASK; 655 out: 656 mt7530_mutex_unlock(priv); 657 658 return ret; 659 } 660 661 static int 662 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 663 int regnum, u16 data) 664 { 665 struct mt7530_dummy_poll p; 666 u32 val, reg; 667 int ret; 668 669 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 670 671 mt7530_mutex_lock(priv); 672 673 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 674 !(val & MT7531_PHY_ACS_ST), 20, 100000); 675 if (ret < 0) { 676 dev_err(priv->dev, "poll timeout\n"); 677 goto out; 678 } 679 680 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 681 MT7531_MDIO_DEV_ADDR(devad) | regnum; 682 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 683 684 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 685 !(val & MT7531_PHY_ACS_ST), 20, 100000); 686 if (ret < 0) { 687 dev_err(priv->dev, "poll timeout\n"); 688 goto out; 689 } 690 691 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 692 MT7531_MDIO_DEV_ADDR(devad) | data; 693 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 694 695 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 696 !(val & MT7531_PHY_ACS_ST), 20, 100000); 697 if (ret < 0) { 698 dev_err(priv->dev, "poll timeout\n"); 699 goto out; 700 } 701 702 out: 703 mt7530_mutex_unlock(priv); 704 705 return ret; 706 } 707 708 static int 709 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 710 { 711 struct mt7530_dummy_poll p; 712 int ret; 713 u32 val; 714 715 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 716 717 mt7530_mutex_lock(priv); 718 719 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 720 !(val & MT7531_PHY_ACS_ST), 20, 100000); 721 if (ret < 0) { 722 dev_err(priv->dev, "poll timeout\n"); 723 goto out; 724 } 725 726 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 727 MT7531_MDIO_REG_ADDR(regnum); 728 729 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 730 731 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 732 !(val & MT7531_PHY_ACS_ST), 20, 100000); 733 if (ret < 0) { 734 dev_err(priv->dev, "poll timeout\n"); 735 goto out; 736 } 737 738 ret = val & MT7531_MDIO_RW_DATA_MASK; 739 out: 740 mt7530_mutex_unlock(priv); 741 742 return ret; 743 } 744 745 static int 746 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 747 u16 data) 748 { 749 struct mt7530_dummy_poll p; 750 int ret; 751 u32 reg; 752 753 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 754 755 mt7530_mutex_lock(priv); 756 757 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 758 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 759 if (ret < 0) { 760 dev_err(priv->dev, "poll timeout\n"); 761 goto out; 762 } 763 764 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 765 MT7531_MDIO_REG_ADDR(regnum) | data; 766 767 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 768 769 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 770 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 771 if (ret < 0) { 772 dev_err(priv->dev, "poll timeout\n"); 773 goto out; 774 } 775 776 out: 777 mt7530_mutex_unlock(priv); 778 779 return ret; 780 } 781 782 static int 783 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 784 { 785 struct mt7530_priv *priv = bus->priv; 786 787 return priv->info->phy_read_c22(priv, port, regnum); 788 } 789 790 static int 791 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 792 { 793 struct mt7530_priv *priv = bus->priv; 794 795 return priv->info->phy_read_c45(priv, port, devad, regnum); 796 } 797 798 static int 799 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 800 { 801 struct mt7530_priv *priv = bus->priv; 802 803 return priv->info->phy_write_c22(priv, port, regnum, val); 804 } 805 806 static int 807 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 808 u16 val) 809 { 810 struct mt7530_priv *priv = bus->priv; 811 812 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 813 } 814 815 static void 816 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 817 uint8_t *data) 818 { 819 int i; 820 821 if (stringset != ETH_SS_STATS) 822 return; 823 824 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 825 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 826 ETH_GSTRING_LEN); 827 } 828 829 static void 830 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 831 uint64_t *data) 832 { 833 struct mt7530_priv *priv = ds->priv; 834 const struct mt7530_mib_desc *mib; 835 u32 reg, i; 836 u64 hi; 837 838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 839 mib = &mt7530_mib[i]; 840 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 841 842 data[i] = mt7530_read(priv, reg); 843 if (mib->size == 2) { 844 hi = mt7530_read(priv, reg + 4); 845 data[i] |= hi << 32; 846 } 847 } 848 } 849 850 static int 851 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 852 { 853 if (sset != ETH_SS_STATS) 854 return 0; 855 856 return ARRAY_SIZE(mt7530_mib); 857 } 858 859 static int 860 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 861 { 862 struct mt7530_priv *priv = ds->priv; 863 unsigned int secs = msecs / 1000; 864 unsigned int tmp_age_count; 865 unsigned int error = -1; 866 unsigned int age_count; 867 unsigned int age_unit; 868 869 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 870 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 871 return -ERANGE; 872 873 /* iterate through all possible age_count to find the closest pair */ 874 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 875 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 876 877 if (tmp_age_unit <= AGE_UNIT_MAX) { 878 unsigned int tmp_error = secs - 879 (tmp_age_count + 1) * (tmp_age_unit + 1); 880 881 /* found a closer pair */ 882 if (error > tmp_error) { 883 error = tmp_error; 884 age_count = tmp_age_count; 885 age_unit = tmp_age_unit; 886 } 887 888 /* found the exact match, so break the loop */ 889 if (!error) 890 break; 891 } 892 } 893 894 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 895 896 return 0; 897 } 898 899 static const char *p5_intf_modes(unsigned int p5_interface) 900 { 901 switch (p5_interface) { 902 case P5_DISABLED: 903 return "DISABLED"; 904 case P5_INTF_SEL_PHY_P0: 905 return "PHY P0"; 906 case P5_INTF_SEL_PHY_P4: 907 return "PHY P4"; 908 case P5_INTF_SEL_GMAC5: 909 return "GMAC5"; 910 case P5_INTF_SEL_GMAC5_SGMII: 911 return "GMAC5_SGMII"; 912 default: 913 return "unknown"; 914 } 915 } 916 917 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 918 { 919 struct mt7530_priv *priv = ds->priv; 920 u8 tx_delay = 0; 921 int val; 922 923 mutex_lock(&priv->reg_mutex); 924 925 val = mt7530_read(priv, MT7530_MHWTRAP); 926 927 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 928 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 929 930 switch (priv->p5_intf_sel) { 931 case P5_INTF_SEL_PHY_P0: 932 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 933 val |= MHWTRAP_PHY0_SEL; 934 fallthrough; 935 case P5_INTF_SEL_PHY_P4: 936 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 937 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 938 939 /* Setup the MAC by default for the cpu port */ 940 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 941 break; 942 case P5_INTF_SEL_GMAC5: 943 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 944 val &= ~MHWTRAP_P5_DIS; 945 break; 946 case P5_DISABLED: 947 interface = PHY_INTERFACE_MODE_NA; 948 break; 949 default: 950 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 951 priv->p5_intf_sel); 952 goto unlock_exit; 953 } 954 955 /* Setup RGMII settings */ 956 if (phy_interface_mode_is_rgmii(interface)) { 957 val |= MHWTRAP_P5_RGMII_MODE; 958 959 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 960 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 961 962 /* Don't set delay in DSA mode */ 963 if (!dsa_is_dsa_port(priv->ds, 5) && 964 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 965 interface == PHY_INTERFACE_MODE_RGMII_ID)) 966 tx_delay = 4; /* n * 0.5 ns */ 967 968 /* P5 RGMII TX Clock Control: delay x */ 969 mt7530_write(priv, MT7530_P5RGMIITXCR, 970 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 971 972 /* reduce P5 RGMII Tx driving, 8mA */ 973 mt7530_write(priv, MT7530_IO_DRV_CR, 974 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 975 } 976 977 mt7530_write(priv, MT7530_MHWTRAP, val); 978 979 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 980 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 981 982 priv->p5_interface = interface; 983 984 unlock_exit: 985 mutex_unlock(&priv->reg_mutex); 986 } 987 988 static int 989 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 990 { 991 struct mt7530_priv *priv = ds->priv; 992 int ret; 993 994 /* Setup max capability of CPU port at first */ 995 if (priv->info->cpu_port_config) { 996 ret = priv->info->cpu_port_config(ds, port); 997 if (ret) 998 return ret; 999 } 1000 1001 /* Enable Mediatek header mode on the cpu port */ 1002 mt7530_write(priv, MT7530_PVC_P(port), 1003 PORT_SPEC_TAG); 1004 1005 /* Enable flooding on the CPU port */ 1006 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1007 UNU_FFP(BIT(port))); 1008 1009 /* Set CPU port number */ 1010 if (priv->id == ID_MT7621) 1011 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1012 1013 /* CPU port gets connected to all user ports of 1014 * the switch. 1015 */ 1016 mt7530_write(priv, MT7530_PCR_P(port), 1017 PCR_MATRIX(dsa_user_ports(priv->ds))); 1018 1019 /* Set to fallback mode for independent VLAN learning */ 1020 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1021 MT7530_PORT_FALLBACK_MODE); 1022 1023 return 0; 1024 } 1025 1026 static int 1027 mt7530_port_enable(struct dsa_switch *ds, int port, 1028 struct phy_device *phy) 1029 { 1030 struct dsa_port *dp = dsa_to_port(ds, port); 1031 struct mt7530_priv *priv = ds->priv; 1032 1033 mutex_lock(&priv->reg_mutex); 1034 1035 /* Allow the user port gets connected to the cpu port and also 1036 * restore the port matrix if the port is the member of a certain 1037 * bridge. 1038 */ 1039 if (dsa_port_is_user(dp)) { 1040 struct dsa_port *cpu_dp = dp->cpu_dp; 1041 1042 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1043 } 1044 priv->ports[port].enable = true; 1045 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1046 priv->ports[port].pm); 1047 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1048 1049 mutex_unlock(&priv->reg_mutex); 1050 1051 return 0; 1052 } 1053 1054 static void 1055 mt7530_port_disable(struct dsa_switch *ds, int port) 1056 { 1057 struct mt7530_priv *priv = ds->priv; 1058 1059 mutex_lock(&priv->reg_mutex); 1060 1061 /* Clear up all port matrix which could be restored in the next 1062 * enablement for the port. 1063 */ 1064 priv->ports[port].enable = false; 1065 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1066 PCR_MATRIX_CLR); 1067 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1068 1069 mutex_unlock(&priv->reg_mutex); 1070 } 1071 1072 static int 1073 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1074 { 1075 struct mt7530_priv *priv = ds->priv; 1076 int length; 1077 u32 val; 1078 1079 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1080 * largest MTU of the slave ports. Because the switch only has a global 1081 * RX length register, only allowing CPU port here is enough. 1082 */ 1083 if (!dsa_is_cpu_port(ds, port)) 1084 return 0; 1085 1086 mt7530_mutex_lock(priv); 1087 1088 val = mt7530_mii_read(priv, MT7530_GMACCR); 1089 val &= ~MAX_RX_PKT_LEN_MASK; 1090 1091 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1092 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1093 if (length <= 1522) { 1094 val |= MAX_RX_PKT_LEN_1522; 1095 } else if (length <= 1536) { 1096 val |= MAX_RX_PKT_LEN_1536; 1097 } else if (length <= 1552) { 1098 val |= MAX_RX_PKT_LEN_1552; 1099 } else { 1100 val &= ~MAX_RX_JUMBO_MASK; 1101 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1102 val |= MAX_RX_PKT_LEN_JUMBO; 1103 } 1104 1105 mt7530_mii_write(priv, MT7530_GMACCR, val); 1106 1107 mt7530_mutex_unlock(priv); 1108 1109 return 0; 1110 } 1111 1112 static int 1113 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1114 { 1115 return MT7530_MAX_MTU; 1116 } 1117 1118 static void 1119 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1120 { 1121 struct mt7530_priv *priv = ds->priv; 1122 u32 stp_state; 1123 1124 switch (state) { 1125 case BR_STATE_DISABLED: 1126 stp_state = MT7530_STP_DISABLED; 1127 break; 1128 case BR_STATE_BLOCKING: 1129 stp_state = MT7530_STP_BLOCKING; 1130 break; 1131 case BR_STATE_LISTENING: 1132 stp_state = MT7530_STP_LISTENING; 1133 break; 1134 case BR_STATE_LEARNING: 1135 stp_state = MT7530_STP_LEARNING; 1136 break; 1137 case BR_STATE_FORWARDING: 1138 default: 1139 stp_state = MT7530_STP_FORWARDING; 1140 break; 1141 } 1142 1143 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1144 FID_PST(FID_BRIDGED, stp_state)); 1145 } 1146 1147 static int 1148 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1149 struct switchdev_brport_flags flags, 1150 struct netlink_ext_ack *extack) 1151 { 1152 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1153 BR_BCAST_FLOOD)) 1154 return -EINVAL; 1155 1156 return 0; 1157 } 1158 1159 static int 1160 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1161 struct switchdev_brport_flags flags, 1162 struct netlink_ext_ack *extack) 1163 { 1164 struct mt7530_priv *priv = ds->priv; 1165 1166 if (flags.mask & BR_LEARNING) 1167 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1168 flags.val & BR_LEARNING ? 0 : SA_DIS); 1169 1170 if (flags.mask & BR_FLOOD) 1171 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1172 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1173 1174 if (flags.mask & BR_MCAST_FLOOD) 1175 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1176 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1177 1178 if (flags.mask & BR_BCAST_FLOOD) 1179 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1180 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1181 1182 return 0; 1183 } 1184 1185 static int 1186 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1187 struct dsa_bridge bridge, bool *tx_fwd_offload, 1188 struct netlink_ext_ack *extack) 1189 { 1190 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1191 struct dsa_port *cpu_dp = dp->cpu_dp; 1192 u32 port_bitmap = BIT(cpu_dp->index); 1193 struct mt7530_priv *priv = ds->priv; 1194 1195 mutex_lock(&priv->reg_mutex); 1196 1197 dsa_switch_for_each_user_port(other_dp, ds) { 1198 int other_port = other_dp->index; 1199 1200 if (dp == other_dp) 1201 continue; 1202 1203 /* Add this port to the port matrix of the other ports in the 1204 * same bridge. If the port is disabled, port matrix is kept 1205 * and not being setup until the port becomes enabled. 1206 */ 1207 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1208 continue; 1209 1210 if (priv->ports[other_port].enable) 1211 mt7530_set(priv, MT7530_PCR_P(other_port), 1212 PCR_MATRIX(BIT(port))); 1213 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1214 1215 port_bitmap |= BIT(other_port); 1216 } 1217 1218 /* Add the all other ports to this port matrix. */ 1219 if (priv->ports[port].enable) 1220 mt7530_rmw(priv, MT7530_PCR_P(port), 1221 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1222 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1223 1224 /* Set to fallback mode for independent VLAN learning */ 1225 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1226 MT7530_PORT_FALLBACK_MODE); 1227 1228 mutex_unlock(&priv->reg_mutex); 1229 1230 return 0; 1231 } 1232 1233 static void 1234 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1235 { 1236 struct mt7530_priv *priv = ds->priv; 1237 bool all_user_ports_removed = true; 1238 int i; 1239 1240 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1241 * bridge. Don't set standalone ports to fallback mode. 1242 */ 1243 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1244 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1245 MT7530_PORT_FALLBACK_MODE); 1246 1247 mt7530_rmw(priv, MT7530_PVC_P(port), 1248 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1249 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1250 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1251 MT7530_VLAN_ACC_ALL); 1252 1253 /* Set PVID to 0 */ 1254 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1255 G0_PORT_VID_DEF); 1256 1257 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1258 if (dsa_is_user_port(ds, i) && 1259 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1260 all_user_ports_removed = false; 1261 break; 1262 } 1263 } 1264 1265 /* CPU port also does the same thing until all user ports belonging to 1266 * the CPU port get out of VLAN filtering mode. 1267 */ 1268 if (all_user_ports_removed) { 1269 struct dsa_port *dp = dsa_to_port(ds, port); 1270 struct dsa_port *cpu_dp = dp->cpu_dp; 1271 1272 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1273 PCR_MATRIX(dsa_user_ports(priv->ds))); 1274 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1275 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1276 } 1277 } 1278 1279 static void 1280 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1281 { 1282 struct mt7530_priv *priv = ds->priv; 1283 1284 /* Trapped into security mode allows packet forwarding through VLAN 1285 * table lookup. 1286 */ 1287 if (dsa_is_user_port(ds, port)) { 1288 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1289 MT7530_PORT_SECURITY_MODE); 1290 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1291 G0_PORT_VID(priv->ports[port].pvid)); 1292 1293 /* Only accept tagged frames if PVID is not set */ 1294 if (!priv->ports[port].pvid) 1295 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1296 MT7530_VLAN_ACC_TAGGED); 1297 1298 /* Set the port as a user port which is to be able to recognize 1299 * VID from incoming packets before fetching entry within the 1300 * VLAN table. 1301 */ 1302 mt7530_rmw(priv, MT7530_PVC_P(port), 1303 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1304 VLAN_ATTR(MT7530_VLAN_USER) | 1305 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1306 } else { 1307 /* Also set CPU ports to the "user" VLAN port attribute, to 1308 * allow VLAN classification, but keep the EG_TAG attribute as 1309 * "consistent" (i.o.w. don't change its value) for packets 1310 * received by the switch from the CPU, so that tagged packets 1311 * are forwarded to user ports as tagged, and untagged as 1312 * untagged. 1313 */ 1314 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1315 VLAN_ATTR(MT7530_VLAN_USER)); 1316 } 1317 } 1318 1319 static void 1320 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1321 struct dsa_bridge bridge) 1322 { 1323 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1324 struct dsa_port *cpu_dp = dp->cpu_dp; 1325 struct mt7530_priv *priv = ds->priv; 1326 1327 mutex_lock(&priv->reg_mutex); 1328 1329 dsa_switch_for_each_user_port(other_dp, ds) { 1330 int other_port = other_dp->index; 1331 1332 if (dp == other_dp) 1333 continue; 1334 1335 /* Remove this port from the port matrix of the other ports 1336 * in the same bridge. If the port is disabled, port matrix 1337 * is kept and not being setup until the port becomes enabled. 1338 */ 1339 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1340 continue; 1341 1342 if (priv->ports[other_port].enable) 1343 mt7530_clear(priv, MT7530_PCR_P(other_port), 1344 PCR_MATRIX(BIT(port))); 1345 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1346 } 1347 1348 /* Set the cpu port to be the only one in the port matrix of 1349 * this port. 1350 */ 1351 if (priv->ports[port].enable) 1352 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1353 PCR_MATRIX(BIT(cpu_dp->index))); 1354 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1355 1356 /* When a port is removed from the bridge, the port would be set up 1357 * back to the default as is at initial boot which is a VLAN-unaware 1358 * port. 1359 */ 1360 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1361 MT7530_PORT_MATRIX_MODE); 1362 1363 mutex_unlock(&priv->reg_mutex); 1364 } 1365 1366 static int 1367 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1368 const unsigned char *addr, u16 vid, 1369 struct dsa_db db) 1370 { 1371 struct mt7530_priv *priv = ds->priv; 1372 int ret; 1373 u8 port_mask = BIT(port); 1374 1375 mutex_lock(&priv->reg_mutex); 1376 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1377 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1378 mutex_unlock(&priv->reg_mutex); 1379 1380 return ret; 1381 } 1382 1383 static int 1384 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1385 const unsigned char *addr, u16 vid, 1386 struct dsa_db db) 1387 { 1388 struct mt7530_priv *priv = ds->priv; 1389 int ret; 1390 u8 port_mask = BIT(port); 1391 1392 mutex_lock(&priv->reg_mutex); 1393 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1394 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1395 mutex_unlock(&priv->reg_mutex); 1396 1397 return ret; 1398 } 1399 1400 static int 1401 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1402 dsa_fdb_dump_cb_t *cb, void *data) 1403 { 1404 struct mt7530_priv *priv = ds->priv; 1405 struct mt7530_fdb _fdb = { 0 }; 1406 int cnt = MT7530_NUM_FDB_RECORDS; 1407 int ret = 0; 1408 u32 rsp = 0; 1409 1410 mutex_lock(&priv->reg_mutex); 1411 1412 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1413 if (ret < 0) 1414 goto err; 1415 1416 do { 1417 if (rsp & ATC_SRCH_HIT) { 1418 mt7530_fdb_read(priv, &_fdb); 1419 if (_fdb.port_mask & BIT(port)) { 1420 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1421 data); 1422 if (ret < 0) 1423 break; 1424 } 1425 } 1426 } while (--cnt && 1427 !(rsp & ATC_SRCH_END) && 1428 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1429 err: 1430 mutex_unlock(&priv->reg_mutex); 1431 1432 return 0; 1433 } 1434 1435 static int 1436 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1437 const struct switchdev_obj_port_mdb *mdb, 1438 struct dsa_db db) 1439 { 1440 struct mt7530_priv *priv = ds->priv; 1441 const u8 *addr = mdb->addr; 1442 u16 vid = mdb->vid; 1443 u8 port_mask = 0; 1444 int ret; 1445 1446 mutex_lock(&priv->reg_mutex); 1447 1448 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1449 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1450 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1451 & PORT_MAP_MASK; 1452 1453 port_mask |= BIT(port); 1454 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1455 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1456 1457 mutex_unlock(&priv->reg_mutex); 1458 1459 return ret; 1460 } 1461 1462 static int 1463 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1464 const struct switchdev_obj_port_mdb *mdb, 1465 struct dsa_db db) 1466 { 1467 struct mt7530_priv *priv = ds->priv; 1468 const u8 *addr = mdb->addr; 1469 u16 vid = mdb->vid; 1470 u8 port_mask = 0; 1471 int ret; 1472 1473 mutex_lock(&priv->reg_mutex); 1474 1475 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1476 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1477 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1478 & PORT_MAP_MASK; 1479 1480 port_mask &= ~BIT(port); 1481 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1482 port_mask ? STATIC_ENT : STATIC_EMP); 1483 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1484 1485 mutex_unlock(&priv->reg_mutex); 1486 1487 return ret; 1488 } 1489 1490 static int 1491 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1492 { 1493 struct mt7530_dummy_poll p; 1494 u32 val; 1495 int ret; 1496 1497 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1498 mt7530_write(priv, MT7530_VTCR, val); 1499 1500 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1501 ret = readx_poll_timeout(_mt7530_read, &p, val, 1502 !(val & VTCR_BUSY), 20, 20000); 1503 if (ret < 0) { 1504 dev_err(priv->dev, "poll timeout\n"); 1505 return ret; 1506 } 1507 1508 val = mt7530_read(priv, MT7530_VTCR); 1509 if (val & VTCR_INVALID) { 1510 dev_err(priv->dev, "read VTCR invalid\n"); 1511 return -EINVAL; 1512 } 1513 1514 return 0; 1515 } 1516 1517 static int 1518 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1519 struct netlink_ext_ack *extack) 1520 { 1521 struct dsa_port *dp = dsa_to_port(ds, port); 1522 struct dsa_port *cpu_dp = dp->cpu_dp; 1523 1524 if (vlan_filtering) { 1525 /* The port is being kept as VLAN-unaware port when bridge is 1526 * set up with vlan_filtering not being set, Otherwise, the 1527 * port and the corresponding CPU port is required the setup 1528 * for becoming a VLAN-aware port. 1529 */ 1530 mt7530_port_set_vlan_aware(ds, port); 1531 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1532 } else { 1533 mt7530_port_set_vlan_unaware(ds, port); 1534 } 1535 1536 return 0; 1537 } 1538 1539 static void 1540 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1541 struct mt7530_hw_vlan_entry *entry) 1542 { 1543 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1544 u8 new_members; 1545 u32 val; 1546 1547 new_members = entry->old_members | BIT(entry->port); 1548 1549 /* Validate the entry with independent learning, create egress tag per 1550 * VLAN and joining the port as one of the port members. 1551 */ 1552 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1553 VLAN_VALID; 1554 mt7530_write(priv, MT7530_VAWD1, val); 1555 1556 /* Decide whether adding tag or not for those outgoing packets from the 1557 * port inside the VLAN. 1558 * CPU port is always taken as a tagged port for serving more than one 1559 * VLANs across and also being applied with egress type stack mode for 1560 * that VLAN tags would be appended after hardware special tag used as 1561 * DSA tag. 1562 */ 1563 if (dsa_port_is_cpu(dp)) 1564 val = MT7530_VLAN_EGRESS_STACK; 1565 else if (entry->untagged) 1566 val = MT7530_VLAN_EGRESS_UNTAG; 1567 else 1568 val = MT7530_VLAN_EGRESS_TAG; 1569 mt7530_rmw(priv, MT7530_VAWD2, 1570 ETAG_CTRL_P_MASK(entry->port), 1571 ETAG_CTRL_P(entry->port, val)); 1572 } 1573 1574 static void 1575 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1576 struct mt7530_hw_vlan_entry *entry) 1577 { 1578 u8 new_members; 1579 u32 val; 1580 1581 new_members = entry->old_members & ~BIT(entry->port); 1582 1583 val = mt7530_read(priv, MT7530_VAWD1); 1584 if (!(val & VLAN_VALID)) { 1585 dev_err(priv->dev, 1586 "Cannot be deleted due to invalid entry\n"); 1587 return; 1588 } 1589 1590 if (new_members) { 1591 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1592 VLAN_VALID; 1593 mt7530_write(priv, MT7530_VAWD1, val); 1594 } else { 1595 mt7530_write(priv, MT7530_VAWD1, 0); 1596 mt7530_write(priv, MT7530_VAWD2, 0); 1597 } 1598 } 1599 1600 static void 1601 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1602 struct mt7530_hw_vlan_entry *entry, 1603 mt7530_vlan_op vlan_op) 1604 { 1605 u32 val; 1606 1607 /* Fetch entry */ 1608 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1609 1610 val = mt7530_read(priv, MT7530_VAWD1); 1611 1612 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1613 1614 /* Manipulate entry */ 1615 vlan_op(priv, entry); 1616 1617 /* Flush result to hardware */ 1618 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1619 } 1620 1621 static int 1622 mt7530_setup_vlan0(struct mt7530_priv *priv) 1623 { 1624 u32 val; 1625 1626 /* Validate the entry with independent learning, keep the original 1627 * ingress tag attribute. 1628 */ 1629 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1630 VLAN_VALID; 1631 mt7530_write(priv, MT7530_VAWD1, val); 1632 1633 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1634 } 1635 1636 static int 1637 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1638 const struct switchdev_obj_port_vlan *vlan, 1639 struct netlink_ext_ack *extack) 1640 { 1641 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1642 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1643 struct mt7530_hw_vlan_entry new_entry; 1644 struct mt7530_priv *priv = ds->priv; 1645 1646 mutex_lock(&priv->reg_mutex); 1647 1648 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1649 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1650 1651 if (pvid) { 1652 priv->ports[port].pvid = vlan->vid; 1653 1654 /* Accept all frames if PVID is set */ 1655 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1656 MT7530_VLAN_ACC_ALL); 1657 1658 /* Only configure PVID if VLAN filtering is enabled */ 1659 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1660 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1661 G0_PORT_VID_MASK, 1662 G0_PORT_VID(vlan->vid)); 1663 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1664 /* This VLAN is overwritten without PVID, so unset it */ 1665 priv->ports[port].pvid = G0_PORT_VID_DEF; 1666 1667 /* Only accept tagged frames if the port is VLAN-aware */ 1668 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1669 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1670 MT7530_VLAN_ACC_TAGGED); 1671 1672 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1673 G0_PORT_VID_DEF); 1674 } 1675 1676 mutex_unlock(&priv->reg_mutex); 1677 1678 return 0; 1679 } 1680 1681 static int 1682 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1683 const struct switchdev_obj_port_vlan *vlan) 1684 { 1685 struct mt7530_hw_vlan_entry target_entry; 1686 struct mt7530_priv *priv = ds->priv; 1687 1688 mutex_lock(&priv->reg_mutex); 1689 1690 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1691 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1692 mt7530_hw_vlan_del); 1693 1694 /* PVID is being restored to the default whenever the PVID port 1695 * is being removed from the VLAN. 1696 */ 1697 if (priv->ports[port].pvid == vlan->vid) { 1698 priv->ports[port].pvid = G0_PORT_VID_DEF; 1699 1700 /* Only accept tagged frames if the port is VLAN-aware */ 1701 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1702 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1703 MT7530_VLAN_ACC_TAGGED); 1704 1705 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1706 G0_PORT_VID_DEF); 1707 } 1708 1709 1710 mutex_unlock(&priv->reg_mutex); 1711 1712 return 0; 1713 } 1714 1715 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1716 { 1717 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1718 MIRROR_PORT(val); 1719 } 1720 1721 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1722 { 1723 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1724 MIRROR_PORT(val); 1725 } 1726 1727 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1728 struct dsa_mall_mirror_tc_entry *mirror, 1729 bool ingress, struct netlink_ext_ack *extack) 1730 { 1731 struct mt7530_priv *priv = ds->priv; 1732 int monitor_port; 1733 u32 val; 1734 1735 /* Check for existent entry */ 1736 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1737 return -EEXIST; 1738 1739 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1740 1741 /* MT7530 only supports one monitor port */ 1742 monitor_port = mt753x_mirror_port_get(priv->id, val); 1743 if (val & MT753X_MIRROR_EN(priv->id) && 1744 monitor_port != mirror->to_local_port) 1745 return -EEXIST; 1746 1747 val |= MT753X_MIRROR_EN(priv->id); 1748 val &= ~MT753X_MIRROR_MASK(priv->id); 1749 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1750 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1751 1752 val = mt7530_read(priv, MT7530_PCR_P(port)); 1753 if (ingress) { 1754 val |= PORT_RX_MIR; 1755 priv->mirror_rx |= BIT(port); 1756 } else { 1757 val |= PORT_TX_MIR; 1758 priv->mirror_tx |= BIT(port); 1759 } 1760 mt7530_write(priv, MT7530_PCR_P(port), val); 1761 1762 return 0; 1763 } 1764 1765 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1766 struct dsa_mall_mirror_tc_entry *mirror) 1767 { 1768 struct mt7530_priv *priv = ds->priv; 1769 u32 val; 1770 1771 val = mt7530_read(priv, MT7530_PCR_P(port)); 1772 if (mirror->ingress) { 1773 val &= ~PORT_RX_MIR; 1774 priv->mirror_rx &= ~BIT(port); 1775 } else { 1776 val &= ~PORT_TX_MIR; 1777 priv->mirror_tx &= ~BIT(port); 1778 } 1779 mt7530_write(priv, MT7530_PCR_P(port), val); 1780 1781 if (!priv->mirror_rx && !priv->mirror_tx) { 1782 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1783 val &= ~MT753X_MIRROR_EN(priv->id); 1784 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1785 } 1786 } 1787 1788 static enum dsa_tag_protocol 1789 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1790 enum dsa_tag_protocol mp) 1791 { 1792 return DSA_TAG_PROTO_MTK; 1793 } 1794 1795 #ifdef CONFIG_GPIOLIB 1796 static inline u32 1797 mt7530_gpio_to_bit(unsigned int offset) 1798 { 1799 /* Map GPIO offset to register bit 1800 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1801 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1802 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1803 * [14:12] port 3 LED 0..2 as GPIO 9..11 1804 * [18:16] port 4 LED 0..2 as GPIO 12..14 1805 */ 1806 return BIT(offset + offset / 3); 1807 } 1808 1809 static int 1810 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1811 { 1812 struct mt7530_priv *priv = gpiochip_get_data(gc); 1813 u32 bit = mt7530_gpio_to_bit(offset); 1814 1815 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1816 } 1817 1818 static void 1819 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1820 { 1821 struct mt7530_priv *priv = gpiochip_get_data(gc); 1822 u32 bit = mt7530_gpio_to_bit(offset); 1823 1824 if (value) 1825 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1826 else 1827 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1828 } 1829 1830 static int 1831 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1832 { 1833 struct mt7530_priv *priv = gpiochip_get_data(gc); 1834 u32 bit = mt7530_gpio_to_bit(offset); 1835 1836 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1837 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1838 } 1839 1840 static int 1841 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1842 { 1843 struct mt7530_priv *priv = gpiochip_get_data(gc); 1844 u32 bit = mt7530_gpio_to_bit(offset); 1845 1846 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1847 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1848 1849 return 0; 1850 } 1851 1852 static int 1853 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1854 { 1855 struct mt7530_priv *priv = gpiochip_get_data(gc); 1856 u32 bit = mt7530_gpio_to_bit(offset); 1857 1858 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1859 1860 if (value) 1861 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1862 else 1863 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1864 1865 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1866 1867 return 0; 1868 } 1869 1870 static int 1871 mt7530_setup_gpio(struct mt7530_priv *priv) 1872 { 1873 struct device *dev = priv->dev; 1874 struct gpio_chip *gc; 1875 1876 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1877 if (!gc) 1878 return -ENOMEM; 1879 1880 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1881 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1882 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1883 1884 gc->label = "mt7530"; 1885 gc->parent = dev; 1886 gc->owner = THIS_MODULE; 1887 gc->get_direction = mt7530_gpio_get_direction; 1888 gc->direction_input = mt7530_gpio_direction_input; 1889 gc->direction_output = mt7530_gpio_direction_output; 1890 gc->get = mt7530_gpio_get; 1891 gc->set = mt7530_gpio_set; 1892 gc->base = -1; 1893 gc->ngpio = 15; 1894 gc->can_sleep = true; 1895 1896 return devm_gpiochip_add_data(dev, gc, priv); 1897 } 1898 #endif /* CONFIG_GPIOLIB */ 1899 1900 static irqreturn_t 1901 mt7530_irq_thread_fn(int irq, void *dev_id) 1902 { 1903 struct mt7530_priv *priv = dev_id; 1904 bool handled = false; 1905 u32 val; 1906 int p; 1907 1908 mt7530_mutex_lock(priv); 1909 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1910 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1911 mt7530_mutex_unlock(priv); 1912 1913 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1914 if (BIT(p) & val) { 1915 unsigned int irq; 1916 1917 irq = irq_find_mapping(priv->irq_domain, p); 1918 handle_nested_irq(irq); 1919 handled = true; 1920 } 1921 } 1922 1923 return IRQ_RETVAL(handled); 1924 } 1925 1926 static void 1927 mt7530_irq_mask(struct irq_data *d) 1928 { 1929 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1930 1931 priv->irq_enable &= ~BIT(d->hwirq); 1932 } 1933 1934 static void 1935 mt7530_irq_unmask(struct irq_data *d) 1936 { 1937 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1938 1939 priv->irq_enable |= BIT(d->hwirq); 1940 } 1941 1942 static void 1943 mt7530_irq_bus_lock(struct irq_data *d) 1944 { 1945 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1946 1947 mt7530_mutex_lock(priv); 1948 } 1949 1950 static void 1951 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1952 { 1953 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1954 1955 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1956 mt7530_mutex_unlock(priv); 1957 } 1958 1959 static struct irq_chip mt7530_irq_chip = { 1960 .name = KBUILD_MODNAME, 1961 .irq_mask = mt7530_irq_mask, 1962 .irq_unmask = mt7530_irq_unmask, 1963 .irq_bus_lock = mt7530_irq_bus_lock, 1964 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1965 }; 1966 1967 static int 1968 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 1969 irq_hw_number_t hwirq) 1970 { 1971 irq_set_chip_data(irq, domain->host_data); 1972 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 1973 irq_set_nested_thread(irq, true); 1974 irq_set_noprobe(irq); 1975 1976 return 0; 1977 } 1978 1979 static const struct irq_domain_ops mt7530_irq_domain_ops = { 1980 .map = mt7530_irq_map, 1981 .xlate = irq_domain_xlate_onecell, 1982 }; 1983 1984 static void 1985 mt7988_irq_mask(struct irq_data *d) 1986 { 1987 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1988 1989 priv->irq_enable &= ~BIT(d->hwirq); 1990 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1991 } 1992 1993 static void 1994 mt7988_irq_unmask(struct irq_data *d) 1995 { 1996 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1997 1998 priv->irq_enable |= BIT(d->hwirq); 1999 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2000 } 2001 2002 static struct irq_chip mt7988_irq_chip = { 2003 .name = KBUILD_MODNAME, 2004 .irq_mask = mt7988_irq_mask, 2005 .irq_unmask = mt7988_irq_unmask, 2006 }; 2007 2008 static int 2009 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2010 irq_hw_number_t hwirq) 2011 { 2012 irq_set_chip_data(irq, domain->host_data); 2013 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2014 irq_set_nested_thread(irq, true); 2015 irq_set_noprobe(irq); 2016 2017 return 0; 2018 } 2019 2020 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2021 .map = mt7988_irq_map, 2022 .xlate = irq_domain_xlate_onecell, 2023 }; 2024 2025 static void 2026 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2027 { 2028 struct dsa_switch *ds = priv->ds; 2029 int p; 2030 2031 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2032 if (BIT(p) & ds->phys_mii_mask) { 2033 unsigned int irq; 2034 2035 irq = irq_create_mapping(priv->irq_domain, p); 2036 ds->slave_mii_bus->irq[p] = irq; 2037 } 2038 } 2039 } 2040 2041 static int 2042 mt7530_setup_irq(struct mt7530_priv *priv) 2043 { 2044 struct device *dev = priv->dev; 2045 struct device_node *np = dev->of_node; 2046 int ret; 2047 2048 if (!of_property_read_bool(np, "interrupt-controller")) { 2049 dev_info(dev, "no interrupt support\n"); 2050 return 0; 2051 } 2052 2053 priv->irq = of_irq_get(np, 0); 2054 if (priv->irq <= 0) { 2055 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2056 return priv->irq ? : -EINVAL; 2057 } 2058 2059 if (priv->id == ID_MT7988) 2060 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2061 &mt7988_irq_domain_ops, 2062 priv); 2063 else 2064 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2065 &mt7530_irq_domain_ops, 2066 priv); 2067 2068 if (!priv->irq_domain) { 2069 dev_err(dev, "failed to create IRQ domain\n"); 2070 return -ENOMEM; 2071 } 2072 2073 /* This register must be set for MT7530 to properly fire interrupts */ 2074 if (priv->id != ID_MT7531) 2075 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2076 2077 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2078 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2079 if (ret) { 2080 irq_domain_remove(priv->irq_domain); 2081 dev_err(dev, "failed to request IRQ: %d\n", ret); 2082 return ret; 2083 } 2084 2085 return 0; 2086 } 2087 2088 static void 2089 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2090 { 2091 int p; 2092 2093 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2094 if (BIT(p) & priv->ds->phys_mii_mask) { 2095 unsigned int irq; 2096 2097 irq = irq_find_mapping(priv->irq_domain, p); 2098 irq_dispose_mapping(irq); 2099 } 2100 } 2101 } 2102 2103 static void 2104 mt7530_free_irq_common(struct mt7530_priv *priv) 2105 { 2106 free_irq(priv->irq, priv); 2107 irq_domain_remove(priv->irq_domain); 2108 } 2109 2110 static void 2111 mt7530_free_irq(struct mt7530_priv *priv) 2112 { 2113 mt7530_free_mdio_irq(priv); 2114 mt7530_free_irq_common(priv); 2115 } 2116 2117 static int 2118 mt7530_setup_mdio(struct mt7530_priv *priv) 2119 { 2120 struct dsa_switch *ds = priv->ds; 2121 struct device *dev = priv->dev; 2122 struct mii_bus *bus; 2123 static int idx; 2124 int ret; 2125 2126 bus = devm_mdiobus_alloc(dev); 2127 if (!bus) 2128 return -ENOMEM; 2129 2130 ds->slave_mii_bus = bus; 2131 bus->priv = priv; 2132 bus->name = KBUILD_MODNAME "-mii"; 2133 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2134 bus->read = mt753x_phy_read_c22; 2135 bus->write = mt753x_phy_write_c22; 2136 bus->read_c45 = mt753x_phy_read_c45; 2137 bus->write_c45 = mt753x_phy_write_c45; 2138 bus->parent = dev; 2139 bus->phy_mask = ~ds->phys_mii_mask; 2140 2141 if (priv->irq) 2142 mt7530_setup_mdio_irq(priv); 2143 2144 ret = devm_mdiobus_register(dev, bus); 2145 if (ret) { 2146 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2147 if (priv->irq) 2148 mt7530_free_mdio_irq(priv); 2149 } 2150 2151 return ret; 2152 } 2153 2154 static int 2155 mt7530_setup(struct dsa_switch *ds) 2156 { 2157 struct mt7530_priv *priv = ds->priv; 2158 struct device_node *dn = NULL; 2159 struct device_node *phy_node; 2160 struct device_node *mac_np; 2161 struct mt7530_dummy_poll p; 2162 phy_interface_t interface; 2163 struct dsa_port *cpu_dp; 2164 u32 id, val; 2165 int ret, i; 2166 2167 /* The parent node of master netdev which holds the common system 2168 * controller also is the container for two GMACs nodes representing 2169 * as two netdev instances. 2170 */ 2171 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2172 dn = cpu_dp->master->dev.of_node->parent; 2173 /* It doesn't matter which CPU port is found first, 2174 * their masters should share the same parent OF node 2175 */ 2176 break; 2177 } 2178 2179 if (!dn) { 2180 dev_err(ds->dev, "parent OF node of DSA master not found"); 2181 return -EINVAL; 2182 } 2183 2184 ds->assisted_learning_on_cpu_port = true; 2185 ds->mtu_enforcement_ingress = true; 2186 2187 if (priv->id == ID_MT7530) { 2188 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2189 ret = regulator_enable(priv->core_pwr); 2190 if (ret < 0) { 2191 dev_err(priv->dev, 2192 "Failed to enable core power: %d\n", ret); 2193 return ret; 2194 } 2195 2196 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2197 ret = regulator_enable(priv->io_pwr); 2198 if (ret < 0) { 2199 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2200 ret); 2201 return ret; 2202 } 2203 } 2204 2205 /* Reset whole chip through gpio pin or memory-mapped registers for 2206 * different type of hardware 2207 */ 2208 if (priv->mcm) { 2209 reset_control_assert(priv->rstc); 2210 usleep_range(1000, 1100); 2211 reset_control_deassert(priv->rstc); 2212 } else { 2213 gpiod_set_value_cansleep(priv->reset, 0); 2214 usleep_range(1000, 1100); 2215 gpiod_set_value_cansleep(priv->reset, 1); 2216 } 2217 2218 /* Waiting for MT7530 got to stable */ 2219 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2220 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2221 20, 1000000); 2222 if (ret < 0) { 2223 dev_err(priv->dev, "reset timeout\n"); 2224 return ret; 2225 } 2226 2227 id = mt7530_read(priv, MT7530_CREV); 2228 id >>= CHIP_NAME_SHIFT; 2229 if (id != MT7530_ID) { 2230 dev_err(priv->dev, "chip %x can't be supported\n", id); 2231 return -ENODEV; 2232 } 2233 2234 /* Reset the switch through internal reset */ 2235 mt7530_write(priv, MT7530_SYS_CTRL, 2236 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2237 SYS_CTRL_REG_RST); 2238 2239 mt7530_pll_setup(priv); 2240 2241 /* Lower Tx driving for TRGMII path */ 2242 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2243 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2244 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2245 2246 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2247 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2248 RD_TAP_MASK, RD_TAP(16)); 2249 2250 /* Enable port 6 */ 2251 val = mt7530_read(priv, MT7530_MHWTRAP); 2252 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2253 val |= MHWTRAP_MANUAL; 2254 mt7530_write(priv, MT7530_MHWTRAP, val); 2255 2256 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2257 2258 /* Enable and reset MIB counters */ 2259 mt7530_mib_reset(ds); 2260 2261 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2262 /* Disable forwarding by default on all ports */ 2263 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2264 PCR_MATRIX_CLR); 2265 2266 /* Disable learning by default on all ports */ 2267 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2268 2269 if (dsa_is_cpu_port(ds, i)) { 2270 ret = mt753x_cpu_port_enable(ds, i); 2271 if (ret) 2272 return ret; 2273 } else { 2274 mt7530_port_disable(ds, i); 2275 2276 /* Set default PVID to 0 on all user ports */ 2277 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2278 G0_PORT_VID_DEF); 2279 } 2280 /* Enable consistent egress tag */ 2281 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2282 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2283 } 2284 2285 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2286 ret = mt7530_setup_vlan0(priv); 2287 if (ret) 2288 return ret; 2289 2290 /* Setup port 5 */ 2291 priv->p5_intf_sel = P5_DISABLED; 2292 interface = PHY_INTERFACE_MODE_NA; 2293 2294 if (!dsa_is_unused_port(ds, 5)) { 2295 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2296 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2297 if (ret && ret != -ENODEV) 2298 return ret; 2299 } else { 2300 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2301 for_each_child_of_node(dn, mac_np) { 2302 if (!of_device_is_compatible(mac_np, 2303 "mediatek,eth-mac")) 2304 continue; 2305 2306 ret = of_property_read_u32(mac_np, "reg", &id); 2307 if (ret < 0 || id != 1) 2308 continue; 2309 2310 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2311 if (!phy_node) 2312 continue; 2313 2314 if (phy_node->parent == priv->dev->of_node->parent) { 2315 ret = of_get_phy_mode(mac_np, &interface); 2316 if (ret && ret != -ENODEV) { 2317 of_node_put(mac_np); 2318 of_node_put(phy_node); 2319 return ret; 2320 } 2321 id = of_mdio_parse_addr(ds->dev, phy_node); 2322 if (id == 0) 2323 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2324 if (id == 4) 2325 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2326 } 2327 of_node_put(mac_np); 2328 of_node_put(phy_node); 2329 break; 2330 } 2331 } 2332 2333 #ifdef CONFIG_GPIOLIB 2334 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2335 ret = mt7530_setup_gpio(priv); 2336 if (ret) 2337 return ret; 2338 } 2339 #endif /* CONFIG_GPIOLIB */ 2340 2341 mt7530_setup_port5(ds, interface); 2342 2343 /* Flush the FDB table */ 2344 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2345 if (ret < 0) 2346 return ret; 2347 2348 return 0; 2349 } 2350 2351 static int 2352 mt7531_setup_common(struct dsa_switch *ds) 2353 { 2354 struct mt7530_priv *priv = ds->priv; 2355 struct dsa_port *cpu_dp; 2356 int ret, i; 2357 2358 /* BPDU to CPU port */ 2359 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2360 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2361 BIT(cpu_dp->index)); 2362 break; 2363 } 2364 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2365 MT753X_BPDU_CPU_ONLY); 2366 2367 /* Enable and reset MIB counters */ 2368 mt7530_mib_reset(ds); 2369 2370 /* Disable flooding on all ports */ 2371 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2372 UNU_FFP_MASK); 2373 2374 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2375 /* Disable forwarding by default on all ports */ 2376 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2377 PCR_MATRIX_CLR); 2378 2379 /* Disable learning by default on all ports */ 2380 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2381 2382 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2383 2384 if (dsa_is_cpu_port(ds, i)) { 2385 ret = mt753x_cpu_port_enable(ds, i); 2386 if (ret) 2387 return ret; 2388 } else { 2389 mt7530_port_disable(ds, i); 2390 2391 /* Set default PVID to 0 on all user ports */ 2392 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2393 G0_PORT_VID_DEF); 2394 } 2395 2396 /* Enable consistent egress tag */ 2397 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2398 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2399 } 2400 2401 /* Flush the FDB table */ 2402 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2403 if (ret < 0) 2404 return ret; 2405 2406 return 0; 2407 } 2408 2409 static int 2410 mt7531_setup(struct dsa_switch *ds) 2411 { 2412 struct mt7530_priv *priv = ds->priv; 2413 struct mt7530_dummy_poll p; 2414 u32 val, id; 2415 int ret, i; 2416 2417 /* Reset whole chip through gpio pin or memory-mapped registers for 2418 * different type of hardware 2419 */ 2420 if (priv->mcm) { 2421 reset_control_assert(priv->rstc); 2422 usleep_range(1000, 1100); 2423 reset_control_deassert(priv->rstc); 2424 } else { 2425 gpiod_set_value_cansleep(priv->reset, 0); 2426 usleep_range(1000, 1100); 2427 gpiod_set_value_cansleep(priv->reset, 1); 2428 } 2429 2430 /* Waiting for MT7530 got to stable */ 2431 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2432 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2433 20, 1000000); 2434 if (ret < 0) { 2435 dev_err(priv->dev, "reset timeout\n"); 2436 return ret; 2437 } 2438 2439 id = mt7530_read(priv, MT7531_CREV); 2440 id >>= CHIP_NAME_SHIFT; 2441 2442 if (id != MT7531_ID) { 2443 dev_err(priv->dev, "chip %x can't be supported\n", id); 2444 return -ENODEV; 2445 } 2446 2447 /* all MACs must be forced link-down before sw reset */ 2448 for (i = 0; i < MT7530_NUM_PORTS; i++) 2449 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2450 2451 /* Reset the switch through internal reset */ 2452 mt7530_write(priv, MT7530_SYS_CTRL, 2453 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2454 SYS_CTRL_REG_RST); 2455 2456 mt7531_pll_setup(priv); 2457 2458 if (mt7531_dual_sgmii_supported(priv)) { 2459 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2460 2461 /* Let ds->slave_mii_bus be able to access external phy. */ 2462 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2463 MT7531_EXT_P_MDC_11); 2464 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2465 MT7531_EXT_P_MDIO_12); 2466 } else { 2467 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2468 } 2469 dev_dbg(ds->dev, "P5 support %s interface\n", 2470 p5_intf_modes(priv->p5_intf_sel)); 2471 2472 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2473 MT7531_GPIO0_INTERRUPT); 2474 2475 /* Let phylink decide the interface later. */ 2476 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2477 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2478 2479 /* Enable PHY core PLL, since phy_device has not yet been created 2480 * provided for phy_[read,write]_mmd_indirect is called, we provide 2481 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2482 * function. 2483 */ 2484 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2485 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2486 val |= MT7531_PHY_PLL_BYPASS_MODE; 2487 val &= ~MT7531_PHY_PLL_OFF; 2488 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2489 CORE_PLL_GROUP4, val); 2490 2491 mt7531_setup_common(ds); 2492 2493 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2494 ret = mt7530_setup_vlan0(priv); 2495 if (ret) 2496 return ret; 2497 2498 ds->assisted_learning_on_cpu_port = true; 2499 ds->mtu_enforcement_ingress = true; 2500 2501 return 0; 2502 } 2503 2504 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2505 struct phylink_config *config) 2506 { 2507 switch (port) { 2508 case 0 ... 4: /* Internal phy */ 2509 __set_bit(PHY_INTERFACE_MODE_GMII, 2510 config->supported_interfaces); 2511 break; 2512 2513 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2514 phy_interface_set_rgmii(config->supported_interfaces); 2515 __set_bit(PHY_INTERFACE_MODE_MII, 2516 config->supported_interfaces); 2517 __set_bit(PHY_INTERFACE_MODE_GMII, 2518 config->supported_interfaces); 2519 break; 2520 2521 case 6: /* 1st cpu port */ 2522 __set_bit(PHY_INTERFACE_MODE_RGMII, 2523 config->supported_interfaces); 2524 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2525 config->supported_interfaces); 2526 break; 2527 } 2528 } 2529 2530 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2531 { 2532 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2533 } 2534 2535 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2536 struct phylink_config *config) 2537 { 2538 struct mt7530_priv *priv = ds->priv; 2539 2540 switch (port) { 2541 case 0 ... 4: /* Internal phy */ 2542 __set_bit(PHY_INTERFACE_MODE_GMII, 2543 config->supported_interfaces); 2544 break; 2545 2546 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2547 if (mt7531_is_rgmii_port(priv, port)) { 2548 phy_interface_set_rgmii(config->supported_interfaces); 2549 break; 2550 } 2551 fallthrough; 2552 2553 case 6: /* 1st cpu port supports sgmii/8023z only */ 2554 __set_bit(PHY_INTERFACE_MODE_SGMII, 2555 config->supported_interfaces); 2556 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2557 config->supported_interfaces); 2558 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2559 config->supported_interfaces); 2560 2561 config->mac_capabilities |= MAC_2500FD; 2562 break; 2563 } 2564 } 2565 2566 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2567 struct phylink_config *config) 2568 { 2569 phy_interface_zero(config->supported_interfaces); 2570 2571 switch (port) { 2572 case 0 ... 4: /* Internal phy */ 2573 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2574 config->supported_interfaces); 2575 break; 2576 2577 case 6: 2578 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2579 config->supported_interfaces); 2580 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2581 MAC_10000FD; 2582 } 2583 } 2584 2585 static int 2586 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2587 { 2588 struct mt7530_priv *priv = ds->priv; 2589 2590 return priv->info->pad_setup(ds, state->interface); 2591 } 2592 2593 static int 2594 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2595 phy_interface_t interface) 2596 { 2597 struct mt7530_priv *priv = ds->priv; 2598 2599 /* Only need to setup port5. */ 2600 if (port != 5) 2601 return 0; 2602 2603 mt7530_setup_port5(priv->ds, interface); 2604 2605 return 0; 2606 } 2607 2608 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2609 phy_interface_t interface, 2610 struct phy_device *phydev) 2611 { 2612 u32 val; 2613 2614 if (!mt7531_is_rgmii_port(priv, port)) { 2615 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2616 port); 2617 return -EINVAL; 2618 } 2619 2620 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2621 val |= GP_CLK_EN; 2622 val &= ~GP_MODE_MASK; 2623 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2624 val &= ~CLK_SKEW_IN_MASK; 2625 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2626 val &= ~CLK_SKEW_OUT_MASK; 2627 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2628 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2629 2630 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2631 if (!phydev || phy_driver_is_genphy(phydev)) { 2632 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2633 switch (interface) { 2634 case PHY_INTERFACE_MODE_RGMII: 2635 val |= TXCLK_NO_REVERSE; 2636 val |= RXCLK_NO_DELAY; 2637 break; 2638 case PHY_INTERFACE_MODE_RGMII_RXID: 2639 val |= TXCLK_NO_REVERSE; 2640 break; 2641 case PHY_INTERFACE_MODE_RGMII_TXID: 2642 val |= RXCLK_NO_DELAY; 2643 break; 2644 case PHY_INTERFACE_MODE_RGMII_ID: 2645 break; 2646 default: 2647 return -EINVAL; 2648 } 2649 } 2650 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2651 2652 return 0; 2653 } 2654 2655 static bool mt753x_is_mac_port(u32 port) 2656 { 2657 return (port == 5 || port == 6); 2658 } 2659 2660 static int 2661 mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2662 phy_interface_t interface) 2663 { 2664 if (dsa_is_cpu_port(ds, port) && 2665 interface == PHY_INTERFACE_MODE_INTERNAL) 2666 return 0; 2667 2668 return -EINVAL; 2669 } 2670 2671 static int 2672 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2673 phy_interface_t interface) 2674 { 2675 struct mt7530_priv *priv = ds->priv; 2676 struct phy_device *phydev; 2677 struct dsa_port *dp; 2678 2679 if (!mt753x_is_mac_port(port)) { 2680 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2681 return -EINVAL; 2682 } 2683 2684 switch (interface) { 2685 case PHY_INTERFACE_MODE_RGMII: 2686 case PHY_INTERFACE_MODE_RGMII_ID: 2687 case PHY_INTERFACE_MODE_RGMII_RXID: 2688 case PHY_INTERFACE_MODE_RGMII_TXID: 2689 dp = dsa_to_port(ds, port); 2690 phydev = dp->slave->phydev; 2691 return mt7531_rgmii_setup(priv, port, interface, phydev); 2692 case PHY_INTERFACE_MODE_SGMII: 2693 case PHY_INTERFACE_MODE_NA: 2694 case PHY_INTERFACE_MODE_1000BASEX: 2695 case PHY_INTERFACE_MODE_2500BASEX: 2696 /* handled in SGMII PCS driver */ 2697 return 0; 2698 default: 2699 return -EINVAL; 2700 } 2701 2702 return -EINVAL; 2703 } 2704 2705 static int 2706 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2707 const struct phylink_link_state *state) 2708 { 2709 struct mt7530_priv *priv = ds->priv; 2710 2711 return priv->info->mac_port_config(ds, port, mode, state->interface); 2712 } 2713 2714 static struct phylink_pcs * 2715 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2716 phy_interface_t interface) 2717 { 2718 struct mt7530_priv *priv = ds->priv; 2719 2720 switch (interface) { 2721 case PHY_INTERFACE_MODE_TRGMII: 2722 return &priv->pcs[port].pcs; 2723 case PHY_INTERFACE_MODE_SGMII: 2724 case PHY_INTERFACE_MODE_1000BASEX: 2725 case PHY_INTERFACE_MODE_2500BASEX: 2726 return priv->ports[port].sgmii_pcs; 2727 default: 2728 return NULL; 2729 } 2730 } 2731 2732 static void 2733 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2734 const struct phylink_link_state *state) 2735 { 2736 struct mt7530_priv *priv = ds->priv; 2737 u32 mcr_cur, mcr_new; 2738 2739 switch (port) { 2740 case 0 ... 4: /* Internal phy */ 2741 if (state->interface != PHY_INTERFACE_MODE_GMII && 2742 state->interface != PHY_INTERFACE_MODE_INTERNAL) 2743 goto unsupported; 2744 break; 2745 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2746 if (priv->p5_interface == state->interface) 2747 break; 2748 2749 if (mt753x_mac_config(ds, port, mode, state) < 0) 2750 goto unsupported; 2751 2752 if (priv->p5_intf_sel != P5_DISABLED) 2753 priv->p5_interface = state->interface; 2754 break; 2755 case 6: /* 1st cpu port */ 2756 if (priv->p6_interface == state->interface) 2757 break; 2758 2759 mt753x_pad_setup(ds, state); 2760 2761 if (mt753x_mac_config(ds, port, mode, state) < 0) 2762 goto unsupported; 2763 2764 priv->p6_interface = state->interface; 2765 break; 2766 default: 2767 unsupported: 2768 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2769 __func__, phy_modes(state->interface), port); 2770 return; 2771 } 2772 2773 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2774 mcr_new = mcr_cur; 2775 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2776 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2777 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2778 2779 /* Are we connected to external phy */ 2780 if (port == 5 && dsa_is_user_port(ds, 5)) 2781 mcr_new |= PMCR_EXT_PHY; 2782 2783 if (mcr_new != mcr_cur) 2784 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2785 } 2786 2787 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2788 unsigned int mode, 2789 phy_interface_t interface) 2790 { 2791 struct mt7530_priv *priv = ds->priv; 2792 2793 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2794 } 2795 2796 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2797 unsigned int mode, 2798 phy_interface_t interface, 2799 int speed, int duplex) 2800 { 2801 if (pcs->ops->pcs_link_up) 2802 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2803 } 2804 2805 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2806 unsigned int mode, 2807 phy_interface_t interface, 2808 struct phy_device *phydev, 2809 int speed, int duplex, 2810 bool tx_pause, bool rx_pause) 2811 { 2812 struct mt7530_priv *priv = ds->priv; 2813 u32 mcr; 2814 2815 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2816 2817 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2818 * variants. 2819 */ 2820 if (interface == PHY_INTERFACE_MODE_INTERNAL || 2821 interface == PHY_INTERFACE_MODE_TRGMII || 2822 (phy_interface_mode_is_8023z(interface))) { 2823 speed = SPEED_1000; 2824 duplex = DUPLEX_FULL; 2825 } 2826 2827 switch (speed) { 2828 case SPEED_1000: 2829 mcr |= PMCR_FORCE_SPEED_1000; 2830 break; 2831 case SPEED_100: 2832 mcr |= PMCR_FORCE_SPEED_100; 2833 break; 2834 } 2835 if (duplex == DUPLEX_FULL) { 2836 mcr |= PMCR_FORCE_FDX; 2837 if (tx_pause) 2838 mcr |= PMCR_TX_FC_EN; 2839 if (rx_pause) 2840 mcr |= PMCR_RX_FC_EN; 2841 } 2842 2843 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2844 switch (speed) { 2845 case SPEED_1000: 2846 mcr |= PMCR_FORCE_EEE1G; 2847 break; 2848 case SPEED_100: 2849 mcr |= PMCR_FORCE_EEE100; 2850 break; 2851 } 2852 } 2853 2854 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2855 } 2856 2857 static int 2858 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2859 { 2860 struct mt7530_priv *priv = ds->priv; 2861 phy_interface_t interface; 2862 int speed; 2863 int ret; 2864 2865 switch (port) { 2866 case 5: 2867 if (mt7531_is_rgmii_port(priv, port)) 2868 interface = PHY_INTERFACE_MODE_RGMII; 2869 else 2870 interface = PHY_INTERFACE_MODE_2500BASEX; 2871 2872 priv->p5_interface = interface; 2873 break; 2874 case 6: 2875 interface = PHY_INTERFACE_MODE_2500BASEX; 2876 2877 priv->p6_interface = interface; 2878 break; 2879 default: 2880 return -EINVAL; 2881 } 2882 2883 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2884 speed = SPEED_2500; 2885 else 2886 speed = SPEED_1000; 2887 2888 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2889 if (ret) 2890 return ret; 2891 mt7530_write(priv, MT7530_PMCR_P(port), 2892 PMCR_CPU_PORT_SETTING(priv->id)); 2893 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2894 interface, speed, DUPLEX_FULL); 2895 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2896 speed, DUPLEX_FULL, true, true); 2897 2898 return 0; 2899 } 2900 2901 static int 2902 mt7988_cpu_port_config(struct dsa_switch *ds, int port) 2903 { 2904 struct mt7530_priv *priv = ds->priv; 2905 2906 mt7530_write(priv, MT7530_PMCR_P(port), 2907 PMCR_CPU_PORT_SETTING(priv->id)); 2908 2909 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, 2910 PHY_INTERFACE_MODE_INTERNAL, NULL, 2911 SPEED_10000, DUPLEX_FULL, true, true); 2912 2913 return 0; 2914 } 2915 2916 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2917 struct phylink_config *config) 2918 { 2919 struct mt7530_priv *priv = ds->priv; 2920 2921 /* This switch only supports full-duplex at 1Gbps */ 2922 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2923 MAC_10 | MAC_100 | MAC_1000FD; 2924 2925 /* This driver does not make use of the speed, duplex, pause or the 2926 * advertisement in its mac_config, so it is safe to mark this driver 2927 * as non-legacy. 2928 */ 2929 config->legacy_pre_march2020 = false; 2930 2931 priv->info->mac_port_get_caps(ds, port, config); 2932 } 2933 2934 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2935 unsigned long *supported, 2936 const struct phylink_link_state *state) 2937 { 2938 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2939 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2940 phy_interface_mode_is_8023z(state->interface)) 2941 phylink_clear(supported, Autoneg); 2942 2943 return 0; 2944 } 2945 2946 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2947 struct phylink_link_state *state) 2948 { 2949 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2950 int port = pcs_to_mt753x_pcs(pcs)->port; 2951 u32 pmsr; 2952 2953 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2954 2955 state->link = (pmsr & PMSR_LINK); 2956 state->an_complete = state->link; 2957 state->duplex = !!(pmsr & PMSR_DPX); 2958 2959 switch (pmsr & PMSR_SPEED_MASK) { 2960 case PMSR_SPEED_10: 2961 state->speed = SPEED_10; 2962 break; 2963 case PMSR_SPEED_100: 2964 state->speed = SPEED_100; 2965 break; 2966 case PMSR_SPEED_1000: 2967 state->speed = SPEED_1000; 2968 break; 2969 default: 2970 state->speed = SPEED_UNKNOWN; 2971 break; 2972 } 2973 2974 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2975 if (pmsr & PMSR_RX_FC) 2976 state->pause |= MLO_PAUSE_RX; 2977 if (pmsr & PMSR_TX_FC) 2978 state->pause |= MLO_PAUSE_TX; 2979 } 2980 2981 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 2982 phy_interface_t interface, 2983 const unsigned long *advertising, 2984 bool permit_pause_to_mac) 2985 { 2986 return 0; 2987 } 2988 2989 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 2990 { 2991 } 2992 2993 static const struct phylink_pcs_ops mt7530_pcs_ops = { 2994 .pcs_validate = mt753x_pcs_validate, 2995 .pcs_get_state = mt7530_pcs_get_state, 2996 .pcs_config = mt753x_pcs_config, 2997 .pcs_an_restart = mt7530_pcs_an_restart, 2998 }; 2999 3000 static int 3001 mt753x_setup(struct dsa_switch *ds) 3002 { 3003 struct mt7530_priv *priv = ds->priv; 3004 int i, ret; 3005 3006 /* Initialise the PCS devices */ 3007 for (i = 0; i < priv->ds->num_ports; i++) { 3008 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3009 priv->pcs[i].priv = priv; 3010 priv->pcs[i].port = i; 3011 } 3012 3013 ret = priv->info->sw_setup(ds); 3014 if (ret) 3015 return ret; 3016 3017 ret = mt7530_setup_irq(priv); 3018 if (ret) 3019 return ret; 3020 3021 ret = mt7530_setup_mdio(priv); 3022 if (ret && priv->irq) 3023 mt7530_free_irq_common(priv); 3024 3025 if (priv->create_sgmii) { 3026 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); 3027 if (ret && priv->irq) 3028 mt7530_free_irq(priv); 3029 } 3030 3031 return ret; 3032 } 3033 3034 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3035 struct ethtool_eee *e) 3036 { 3037 struct mt7530_priv *priv = ds->priv; 3038 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3039 3040 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3041 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3042 3043 return 0; 3044 } 3045 3046 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3047 struct ethtool_eee *e) 3048 { 3049 struct mt7530_priv *priv = ds->priv; 3050 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3051 3052 if (e->tx_lpi_timer > 0xFFF) 3053 return -EINVAL; 3054 3055 set = SET_LPI_THRESH(e->tx_lpi_timer); 3056 if (!e->tx_lpi_enabled) 3057 /* Force LPI Mode without a delay */ 3058 set |= LPI_MODE_EN; 3059 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3060 3061 return 0; 3062 } 3063 3064 static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 3065 { 3066 return 0; 3067 } 3068 3069 static int mt7988_setup(struct dsa_switch *ds) 3070 { 3071 struct mt7530_priv *priv = ds->priv; 3072 3073 /* Reset the switch */ 3074 reset_control_assert(priv->rstc); 3075 usleep_range(20, 50); 3076 reset_control_deassert(priv->rstc); 3077 usleep_range(20, 50); 3078 3079 /* Reset the switch PHYs */ 3080 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3081 3082 return mt7531_setup_common(ds); 3083 } 3084 3085 const struct dsa_switch_ops mt7530_switch_ops = { 3086 .get_tag_protocol = mtk_get_tag_protocol, 3087 .setup = mt753x_setup, 3088 .get_strings = mt7530_get_strings, 3089 .get_ethtool_stats = mt7530_get_ethtool_stats, 3090 .get_sset_count = mt7530_get_sset_count, 3091 .set_ageing_time = mt7530_set_ageing_time, 3092 .port_enable = mt7530_port_enable, 3093 .port_disable = mt7530_port_disable, 3094 .port_change_mtu = mt7530_port_change_mtu, 3095 .port_max_mtu = mt7530_port_max_mtu, 3096 .port_stp_state_set = mt7530_stp_state_set, 3097 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3098 .port_bridge_flags = mt7530_port_bridge_flags, 3099 .port_bridge_join = mt7530_port_bridge_join, 3100 .port_bridge_leave = mt7530_port_bridge_leave, 3101 .port_fdb_add = mt7530_port_fdb_add, 3102 .port_fdb_del = mt7530_port_fdb_del, 3103 .port_fdb_dump = mt7530_port_fdb_dump, 3104 .port_mdb_add = mt7530_port_mdb_add, 3105 .port_mdb_del = mt7530_port_mdb_del, 3106 .port_vlan_filtering = mt7530_port_vlan_filtering, 3107 .port_vlan_add = mt7530_port_vlan_add, 3108 .port_vlan_del = mt7530_port_vlan_del, 3109 .port_mirror_add = mt753x_port_mirror_add, 3110 .port_mirror_del = mt753x_port_mirror_del, 3111 .phylink_get_caps = mt753x_phylink_get_caps, 3112 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3113 .phylink_mac_config = mt753x_phylink_mac_config, 3114 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3115 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3116 .get_mac_eee = mt753x_get_mac_eee, 3117 .set_mac_eee = mt753x_set_mac_eee, 3118 }; 3119 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3120 3121 const struct mt753x_info mt753x_table[] = { 3122 [ID_MT7621] = { 3123 .id = ID_MT7621, 3124 .pcs_ops = &mt7530_pcs_ops, 3125 .sw_setup = mt7530_setup, 3126 .phy_read_c22 = mt7530_phy_read_c22, 3127 .phy_write_c22 = mt7530_phy_write_c22, 3128 .phy_read_c45 = mt7530_phy_read_c45, 3129 .phy_write_c45 = mt7530_phy_write_c45, 3130 .pad_setup = mt7530_pad_clk_setup, 3131 .mac_port_get_caps = mt7530_mac_port_get_caps, 3132 .mac_port_config = mt7530_mac_config, 3133 }, 3134 [ID_MT7530] = { 3135 .id = ID_MT7530, 3136 .pcs_ops = &mt7530_pcs_ops, 3137 .sw_setup = mt7530_setup, 3138 .phy_read_c22 = mt7530_phy_read_c22, 3139 .phy_write_c22 = mt7530_phy_write_c22, 3140 .phy_read_c45 = mt7530_phy_read_c45, 3141 .phy_write_c45 = mt7530_phy_write_c45, 3142 .pad_setup = mt7530_pad_clk_setup, 3143 .mac_port_get_caps = mt7530_mac_port_get_caps, 3144 .mac_port_config = mt7530_mac_config, 3145 }, 3146 [ID_MT7531] = { 3147 .id = ID_MT7531, 3148 .pcs_ops = &mt7530_pcs_ops, 3149 .sw_setup = mt7531_setup, 3150 .phy_read_c22 = mt7531_ind_c22_phy_read, 3151 .phy_write_c22 = mt7531_ind_c22_phy_write, 3152 .phy_read_c45 = mt7531_ind_c45_phy_read, 3153 .phy_write_c45 = mt7531_ind_c45_phy_write, 3154 .pad_setup = mt7531_pad_setup, 3155 .cpu_port_config = mt7531_cpu_port_config, 3156 .mac_port_get_caps = mt7531_mac_port_get_caps, 3157 .mac_port_config = mt7531_mac_config, 3158 }, 3159 [ID_MT7988] = { 3160 .id = ID_MT7988, 3161 .pcs_ops = &mt7530_pcs_ops, 3162 .sw_setup = mt7988_setup, 3163 .phy_read_c22 = mt7531_ind_c22_phy_read, 3164 .phy_write_c22 = mt7531_ind_c22_phy_write, 3165 .phy_read_c45 = mt7531_ind_c45_phy_read, 3166 .phy_write_c45 = mt7531_ind_c45_phy_write, 3167 .pad_setup = mt7988_pad_setup, 3168 .cpu_port_config = mt7988_cpu_port_config, 3169 .mac_port_get_caps = mt7988_mac_port_get_caps, 3170 .mac_port_config = mt7988_mac_config, 3171 }, 3172 }; 3173 EXPORT_SYMBOL_GPL(mt753x_table); 3174 3175 int 3176 mt7530_probe_common(struct mt7530_priv *priv) 3177 { 3178 struct device *dev = priv->dev; 3179 3180 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3181 if (!priv->ds) 3182 return -ENOMEM; 3183 3184 priv->ds->dev = dev; 3185 priv->ds->num_ports = MT7530_NUM_PORTS; 3186 3187 /* Get the hardware identifier from the devicetree node. 3188 * We will need it for some of the clock and regulator setup. 3189 */ 3190 priv->info = of_device_get_match_data(dev); 3191 if (!priv->info) 3192 return -EINVAL; 3193 3194 /* Sanity check if these required device operations are filled 3195 * properly. 3196 */ 3197 if (!priv->info->sw_setup || !priv->info->pad_setup || 3198 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3199 !priv->info->mac_port_get_caps || 3200 !priv->info->mac_port_config) 3201 return -EINVAL; 3202 3203 priv->id = priv->info->id; 3204 priv->dev = dev; 3205 priv->ds->priv = priv; 3206 priv->ds->ops = &mt7530_switch_ops; 3207 mutex_init(&priv->reg_mutex); 3208 dev_set_drvdata(dev, priv); 3209 3210 return 0; 3211 } 3212 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3213 3214 void 3215 mt7530_remove_common(struct mt7530_priv *priv) 3216 { 3217 if (priv->irq) 3218 mt7530_free_irq(priv); 3219 3220 dsa_unregister_switch(priv->ds); 3221 3222 mutex_destroy(&priv->reg_mutex); 3223 } 3224 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3225 3226 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3227 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3228 MODULE_LICENSE("GPL"); 3229