1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_irq.h> 14 #include <linux/of_mdio.h> 15 #include <linux/of_net.h> 16 #include <linux/of_platform.h> 17 #include <linux/phylink.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/gpio/consumer.h> 22 #include <linux/gpio/driver.h> 23 #include <net/dsa.h> 24 25 #include "mt7530.h" 26 27 static struct mt753x_pcs *pcs_to_mt753x_pcs(struct phylink_pcs *pcs) 28 { 29 return container_of(pcs, struct mt753x_pcs, pcs); 30 } 31 32 /* String, offset, and register size in bytes if different from 4 bytes */ 33 static const struct mt7530_mib_desc mt7530_mib[] = { 34 MIB_DESC(1, 0x00, "TxDrop"), 35 MIB_DESC(1, 0x04, "TxCrcErr"), 36 MIB_DESC(1, 0x08, "TxUnicast"), 37 MIB_DESC(1, 0x0c, "TxMulticast"), 38 MIB_DESC(1, 0x10, "TxBroadcast"), 39 MIB_DESC(1, 0x14, "TxCollision"), 40 MIB_DESC(1, 0x18, "TxSingleCollision"), 41 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 42 MIB_DESC(1, 0x20, "TxDeferred"), 43 MIB_DESC(1, 0x24, "TxLateCollision"), 44 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 45 MIB_DESC(1, 0x2c, "TxPause"), 46 MIB_DESC(1, 0x30, "TxPktSz64"), 47 MIB_DESC(1, 0x34, "TxPktSz65To127"), 48 MIB_DESC(1, 0x38, "TxPktSz128To255"), 49 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 50 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 51 MIB_DESC(1, 0x44, "Tx1024ToMax"), 52 MIB_DESC(2, 0x48, "TxBytes"), 53 MIB_DESC(1, 0x60, "RxDrop"), 54 MIB_DESC(1, 0x64, "RxFiltering"), 55 MIB_DESC(1, 0x68, "RxUnicast"), 56 MIB_DESC(1, 0x6c, "RxMulticast"), 57 MIB_DESC(1, 0x70, "RxBroadcast"), 58 MIB_DESC(1, 0x74, "RxAlignErr"), 59 MIB_DESC(1, 0x78, "RxCrcErr"), 60 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 61 MIB_DESC(1, 0x80, "RxFragErr"), 62 MIB_DESC(1, 0x84, "RxOverSzErr"), 63 MIB_DESC(1, 0x88, "RxJabberErr"), 64 MIB_DESC(1, 0x8c, "RxPause"), 65 MIB_DESC(1, 0x90, "RxPktSz64"), 66 MIB_DESC(1, 0x94, "RxPktSz65To127"), 67 MIB_DESC(1, 0x98, "RxPktSz128To255"), 68 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 69 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 70 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 71 MIB_DESC(2, 0xa8, "RxBytes"), 72 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 73 MIB_DESC(1, 0xb4, "RxIngressDrop"), 74 MIB_DESC(1, 0xb8, "RxArlDrop"), 75 }; 76 77 /* Since phy_device has not yet been created and 78 * phy_{read,write}_mmd_indirect is not available, we provide our own 79 * core_{read,write}_mmd_indirect with core_{clear,write,set} wrappers 80 * to complete this function. 81 */ 82 static int 83 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 84 { 85 struct mii_bus *bus = priv->bus; 86 int value, ret; 87 88 /* Write the desired MMD Devad */ 89 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 90 if (ret < 0) 91 goto err; 92 93 /* Write the desired MMD register address */ 94 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 95 if (ret < 0) 96 goto err; 97 98 /* Select the Function : DATA with no post increment */ 99 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 100 if (ret < 0) 101 goto err; 102 103 /* Read the content of the MMD's selected register */ 104 value = bus->read(bus, 0, MII_MMD_DATA); 105 106 return value; 107 err: 108 dev_err(&bus->dev, "failed to read mmd register\n"); 109 110 return ret; 111 } 112 113 static int 114 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 115 int devad, u32 data) 116 { 117 struct mii_bus *bus = priv->bus; 118 int ret; 119 120 /* Write the desired MMD Devad */ 121 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 122 if (ret < 0) 123 goto err; 124 125 /* Write the desired MMD register address */ 126 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 127 if (ret < 0) 128 goto err; 129 130 /* Select the Function : DATA with no post increment */ 131 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 132 if (ret < 0) 133 goto err; 134 135 /* Write the data into MMD's selected register */ 136 ret = bus->write(bus, 0, MII_MMD_DATA, data); 137 err: 138 if (ret < 0) 139 dev_err(&bus->dev, 140 "failed to write mmd register\n"); 141 return ret; 142 } 143 144 static void 145 mt7530_mutex_lock(struct mt7530_priv *priv) 146 { 147 if (priv->bus) 148 mutex_lock_nested(&priv->bus->mdio_lock, MDIO_MUTEX_NESTED); 149 } 150 151 static void 152 mt7530_mutex_unlock(struct mt7530_priv *priv) 153 { 154 if (priv->bus) 155 mutex_unlock(&priv->bus->mdio_lock); 156 } 157 158 static void 159 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 160 { 161 mt7530_mutex_lock(priv); 162 163 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 164 165 mt7530_mutex_unlock(priv); 166 } 167 168 static void 169 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 170 { 171 u32 val; 172 173 mt7530_mutex_lock(priv); 174 175 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 176 val &= ~mask; 177 val |= set; 178 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 179 180 mt7530_mutex_unlock(priv); 181 } 182 183 static void 184 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 185 { 186 core_rmw(priv, reg, 0, val); 187 } 188 189 static void 190 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 191 { 192 core_rmw(priv, reg, val, 0); 193 } 194 195 static int 196 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 197 { 198 int ret; 199 200 ret = regmap_write(priv->regmap, reg, val); 201 202 if (ret < 0) 203 dev_err(priv->dev, 204 "failed to write mt7530 register\n"); 205 206 return ret; 207 } 208 209 static u32 210 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 211 { 212 int ret; 213 u32 val; 214 215 ret = regmap_read(priv->regmap, reg, &val); 216 if (ret) { 217 WARN_ON_ONCE(1); 218 dev_err(priv->dev, 219 "failed to read mt7530 register\n"); 220 return 0; 221 } 222 223 return val; 224 } 225 226 static void 227 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 mt7530_mutex_lock(priv); 230 231 mt7530_mii_write(priv, reg, val); 232 233 mt7530_mutex_unlock(priv); 234 } 235 236 static u32 237 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 238 { 239 return mt7530_mii_read(p->priv, p->reg); 240 } 241 242 static u32 243 _mt7530_read(struct mt7530_dummy_poll *p) 244 { 245 u32 val; 246 247 mt7530_mutex_lock(p->priv); 248 249 val = mt7530_mii_read(p->priv, p->reg); 250 251 mt7530_mutex_unlock(p->priv); 252 253 return val; 254 } 255 256 static u32 257 mt7530_read(struct mt7530_priv *priv, u32 reg) 258 { 259 struct mt7530_dummy_poll p; 260 261 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 262 return _mt7530_read(&p); 263 } 264 265 static void 266 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 267 u32 mask, u32 set) 268 { 269 mt7530_mutex_lock(priv); 270 271 regmap_update_bits(priv->regmap, reg, mask, set); 272 273 mt7530_mutex_unlock(priv); 274 } 275 276 static void 277 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 278 { 279 mt7530_rmw(priv, reg, val, val); 280 } 281 282 static void 283 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 284 { 285 mt7530_rmw(priv, reg, val, 0); 286 } 287 288 static int 289 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 290 { 291 u32 val; 292 int ret; 293 struct mt7530_dummy_poll p; 294 295 /* Set the command operating upon the MAC address entries */ 296 val = ATC_BUSY | ATC_MAT(0) | cmd; 297 mt7530_write(priv, MT7530_ATC, val); 298 299 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 300 ret = readx_poll_timeout(_mt7530_read, &p, val, 301 !(val & ATC_BUSY), 20, 20000); 302 if (ret < 0) { 303 dev_err(priv->dev, "reset timeout\n"); 304 return ret; 305 } 306 307 /* Additional sanity for read command if the specified 308 * entry is invalid 309 */ 310 val = mt7530_read(priv, MT7530_ATC); 311 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 312 return -EINVAL; 313 314 if (rsp) 315 *rsp = val; 316 317 return 0; 318 } 319 320 static void 321 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 322 { 323 u32 reg[3]; 324 int i; 325 326 /* Read from ARL table into an array */ 327 for (i = 0; i < 3; i++) { 328 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 329 330 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 331 __func__, __LINE__, i, reg[i]); 332 } 333 334 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 335 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 336 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 337 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 338 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 339 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 340 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 341 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 342 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 343 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 344 } 345 346 static void 347 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 348 u8 port_mask, const u8 *mac, 349 u8 aging, u8 type) 350 { 351 u32 reg[3] = { 0 }; 352 int i; 353 354 reg[1] |= vid & CVID_MASK; 355 reg[1] |= ATA2_IVL; 356 reg[1] |= ATA2_FID(FID_BRIDGED); 357 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 358 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 359 /* STATIC_ENT indicate that entry is static wouldn't 360 * be aged out and STATIC_EMP specified as erasing an 361 * entry 362 */ 363 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 364 reg[1] |= mac[5] << MAC_BYTE_5; 365 reg[1] |= mac[4] << MAC_BYTE_4; 366 reg[0] |= mac[3] << MAC_BYTE_3; 367 reg[0] |= mac[2] << MAC_BYTE_2; 368 reg[0] |= mac[1] << MAC_BYTE_1; 369 reg[0] |= mac[0] << MAC_BYTE_0; 370 371 /* Write array into the ARL table */ 372 for (i = 0; i < 3; i++) 373 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 374 } 375 376 /* Set up switch core clock for MT7530 */ 377 static void mt7530_pll_setup(struct mt7530_priv *priv) 378 { 379 /* Disable core clock */ 380 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 381 382 /* Disable PLL */ 383 core_write(priv, CORE_GSWPLL_GRP1, 0); 384 385 /* Set core clock into 500Mhz */ 386 core_write(priv, CORE_GSWPLL_GRP2, 387 RG_GSWPLL_POSDIV_500M(1) | 388 RG_GSWPLL_FBKDIV_500M(25)); 389 390 /* Enable PLL */ 391 core_write(priv, CORE_GSWPLL_GRP1, 392 RG_GSWPLL_EN_PRE | 393 RG_GSWPLL_POSDIV_200M(2) | 394 RG_GSWPLL_FBKDIV_200M(32)); 395 396 udelay(20); 397 398 /* Enable core clock */ 399 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 400 } 401 402 /* If port 6 is available as a CPU port, always prefer that as the default, 403 * otherwise don't care. 404 */ 405 static struct dsa_port * 406 mt753x_preferred_default_local_cpu_port(struct dsa_switch *ds) 407 { 408 struct dsa_port *cpu_dp = dsa_to_port(ds, 6); 409 410 if (dsa_port_is_cpu(cpu_dp)) 411 return cpu_dp; 412 413 return NULL; 414 } 415 416 /* Setup port 6 interface mode and TRGMII TX circuit */ 417 static int 418 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 419 { 420 struct mt7530_priv *priv = ds->priv; 421 u32 ncpo1, ssc_delta, trgint, xtal; 422 423 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 424 425 if (xtal == HWTRAP_XTAL_20MHZ) { 426 dev_err(priv->dev, 427 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 428 __func__); 429 return -EINVAL; 430 } 431 432 switch (interface) { 433 case PHY_INTERFACE_MODE_RGMII: 434 trgint = 0; 435 break; 436 case PHY_INTERFACE_MODE_TRGMII: 437 trgint = 1; 438 if (xtal == HWTRAP_XTAL_25MHZ) 439 ssc_delta = 0x57; 440 else 441 ssc_delta = 0x87; 442 if (priv->id == ID_MT7621) { 443 /* PLL frequency: 125MHz: 1.0GBit */ 444 if (xtal == HWTRAP_XTAL_40MHZ) 445 ncpo1 = 0x0640; 446 if (xtal == HWTRAP_XTAL_25MHZ) 447 ncpo1 = 0x0a00; 448 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 449 if (xtal == HWTRAP_XTAL_40MHZ) 450 ncpo1 = 0x0c80; 451 if (xtal == HWTRAP_XTAL_25MHZ) 452 ncpo1 = 0x1400; 453 } 454 break; 455 default: 456 dev_err(priv->dev, "xMII interface %d not supported\n", 457 interface); 458 return -EINVAL; 459 } 460 461 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 462 P6_INTF_MODE(trgint)); 463 464 if (trgint) { 465 /* Disable the MT7530 TRGMII clocks */ 466 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 467 468 /* Setup the MT7530 TRGMII Tx Clock */ 469 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 470 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 471 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 472 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 473 core_write(priv, CORE_PLL_GROUP4, 474 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 475 RG_SYSPLL_BIAS_LPF_EN); 476 core_write(priv, CORE_PLL_GROUP2, 477 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 478 RG_SYSPLL_POSDIV(1)); 479 core_write(priv, CORE_PLL_GROUP7, 480 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 481 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 482 483 /* Enable the MT7530 TRGMII clocks */ 484 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_TRGMIICK_EN); 485 } 486 487 return 0; 488 } 489 490 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 491 { 492 u32 val; 493 494 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 495 496 return (val & PAD_DUAL_SGMII_EN) != 0; 497 } 498 499 static int 500 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 501 { 502 return 0; 503 } 504 505 static void 506 mt7531_pll_setup(struct mt7530_priv *priv) 507 { 508 u32 top_sig; 509 u32 hwstrap; 510 u32 xtal; 511 u32 val; 512 513 if (mt7531_dual_sgmii_supported(priv)) 514 return; 515 516 val = mt7530_read(priv, MT7531_CREV); 517 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 518 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 519 if ((val & CHIP_REV_M) > 0) 520 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 521 HWTRAP_XTAL_FSEL_25MHZ; 522 else 523 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 524 525 /* Step 1 : Disable MT7531 COREPLL */ 526 val = mt7530_read(priv, MT7531_PLLGP_EN); 527 val &= ~EN_COREPLL; 528 mt7530_write(priv, MT7531_PLLGP_EN, val); 529 530 /* Step 2: switch to XTAL output */ 531 val = mt7530_read(priv, MT7531_PLLGP_EN); 532 val |= SW_CLKSW; 533 mt7530_write(priv, MT7531_PLLGP_EN, val); 534 535 val = mt7530_read(priv, MT7531_PLLGP_CR0); 536 val &= ~RG_COREPLL_EN; 537 mt7530_write(priv, MT7531_PLLGP_CR0, val); 538 539 /* Step 3: disable PLLGP and enable program PLLGP */ 540 val = mt7530_read(priv, MT7531_PLLGP_EN); 541 val |= SW_PLLGP; 542 mt7530_write(priv, MT7531_PLLGP_EN, val); 543 544 /* Step 4: program COREPLL output frequency to 500MHz */ 545 val = mt7530_read(priv, MT7531_PLLGP_CR0); 546 val &= ~RG_COREPLL_POSDIV_M; 547 val |= 2 << RG_COREPLL_POSDIV_S; 548 mt7530_write(priv, MT7531_PLLGP_CR0, val); 549 usleep_range(25, 35); 550 551 switch (xtal) { 552 case HWTRAP_XTAL_FSEL_25MHZ: 553 val = mt7530_read(priv, MT7531_PLLGP_CR0); 554 val &= ~RG_COREPLL_SDM_PCW_M; 555 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 556 mt7530_write(priv, MT7531_PLLGP_CR0, val); 557 break; 558 case HWTRAP_XTAL_FSEL_40MHZ: 559 val = mt7530_read(priv, MT7531_PLLGP_CR0); 560 val &= ~RG_COREPLL_SDM_PCW_M; 561 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 562 mt7530_write(priv, MT7531_PLLGP_CR0, val); 563 break; 564 } 565 566 /* Set feedback divide ratio update signal to high */ 567 val = mt7530_read(priv, MT7531_PLLGP_CR0); 568 val |= RG_COREPLL_SDM_PCW_CHG; 569 mt7530_write(priv, MT7531_PLLGP_CR0, val); 570 /* Wait for at least 16 XTAL clocks */ 571 usleep_range(10, 20); 572 573 /* Step 5: set feedback divide ratio update signal to low */ 574 val = mt7530_read(priv, MT7531_PLLGP_CR0); 575 val &= ~RG_COREPLL_SDM_PCW_CHG; 576 mt7530_write(priv, MT7531_PLLGP_CR0, val); 577 578 /* Enable 325M clock for SGMII */ 579 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 580 581 /* Enable 250SSC clock for RGMII */ 582 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 583 584 /* Step 6: Enable MT7531 PLL */ 585 val = mt7530_read(priv, MT7531_PLLGP_CR0); 586 val |= RG_COREPLL_EN; 587 mt7530_write(priv, MT7531_PLLGP_CR0, val); 588 589 val = mt7530_read(priv, MT7531_PLLGP_EN); 590 val |= EN_COREPLL; 591 mt7530_write(priv, MT7531_PLLGP_EN, val); 592 usleep_range(25, 35); 593 } 594 595 static void 596 mt7530_mib_reset(struct dsa_switch *ds) 597 { 598 struct mt7530_priv *priv = ds->priv; 599 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 601 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 602 } 603 604 static int mt7530_phy_read_c22(struct mt7530_priv *priv, int port, int regnum) 605 { 606 return mdiobus_read_nested(priv->bus, port, regnum); 607 } 608 609 static int mt7530_phy_write_c22(struct mt7530_priv *priv, int port, int regnum, 610 u16 val) 611 { 612 return mdiobus_write_nested(priv->bus, port, regnum, val); 613 } 614 615 static int mt7530_phy_read_c45(struct mt7530_priv *priv, int port, 616 int devad, int regnum) 617 { 618 return mdiobus_c45_read_nested(priv->bus, port, devad, regnum); 619 } 620 621 static int mt7530_phy_write_c45(struct mt7530_priv *priv, int port, int devad, 622 int regnum, u16 val) 623 { 624 return mdiobus_c45_write_nested(priv->bus, port, devad, regnum, val); 625 } 626 627 static int 628 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 629 int regnum) 630 { 631 struct mt7530_dummy_poll p; 632 u32 reg, val; 633 int ret; 634 635 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 636 637 mt7530_mutex_lock(priv); 638 639 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 640 !(val & MT7531_PHY_ACS_ST), 20, 100000); 641 if (ret < 0) { 642 dev_err(priv->dev, "poll timeout\n"); 643 goto out; 644 } 645 646 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 647 MT7531_MDIO_DEV_ADDR(devad) | regnum; 648 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 649 650 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 651 !(val & MT7531_PHY_ACS_ST), 20, 100000); 652 if (ret < 0) { 653 dev_err(priv->dev, "poll timeout\n"); 654 goto out; 655 } 656 657 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 658 MT7531_MDIO_DEV_ADDR(devad); 659 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 660 661 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 662 !(val & MT7531_PHY_ACS_ST), 20, 100000); 663 if (ret < 0) { 664 dev_err(priv->dev, "poll timeout\n"); 665 goto out; 666 } 667 668 ret = val & MT7531_MDIO_RW_DATA_MASK; 669 out: 670 mt7530_mutex_unlock(priv); 671 672 return ret; 673 } 674 675 static int 676 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 677 int regnum, u16 data) 678 { 679 struct mt7530_dummy_poll p; 680 u32 val, reg; 681 int ret; 682 683 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 684 685 mt7530_mutex_lock(priv); 686 687 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 688 !(val & MT7531_PHY_ACS_ST), 20, 100000); 689 if (ret < 0) { 690 dev_err(priv->dev, "poll timeout\n"); 691 goto out; 692 } 693 694 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 695 MT7531_MDIO_DEV_ADDR(devad) | regnum; 696 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 697 698 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 699 !(val & MT7531_PHY_ACS_ST), 20, 100000); 700 if (ret < 0) { 701 dev_err(priv->dev, "poll timeout\n"); 702 goto out; 703 } 704 705 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 706 MT7531_MDIO_DEV_ADDR(devad) | data; 707 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 708 709 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 710 !(val & MT7531_PHY_ACS_ST), 20, 100000); 711 if (ret < 0) { 712 dev_err(priv->dev, "poll timeout\n"); 713 goto out; 714 } 715 716 out: 717 mt7530_mutex_unlock(priv); 718 719 return ret; 720 } 721 722 static int 723 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 724 { 725 struct mt7530_dummy_poll p; 726 int ret; 727 u32 val; 728 729 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 730 731 mt7530_mutex_lock(priv); 732 733 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 734 !(val & MT7531_PHY_ACS_ST), 20, 100000); 735 if (ret < 0) { 736 dev_err(priv->dev, "poll timeout\n"); 737 goto out; 738 } 739 740 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 741 MT7531_MDIO_REG_ADDR(regnum); 742 743 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 744 745 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 746 !(val & MT7531_PHY_ACS_ST), 20, 100000); 747 if (ret < 0) { 748 dev_err(priv->dev, "poll timeout\n"); 749 goto out; 750 } 751 752 ret = val & MT7531_MDIO_RW_DATA_MASK; 753 out: 754 mt7530_mutex_unlock(priv); 755 756 return ret; 757 } 758 759 static int 760 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 761 u16 data) 762 { 763 struct mt7530_dummy_poll p; 764 int ret; 765 u32 reg; 766 767 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 768 769 mt7530_mutex_lock(priv); 770 771 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 772 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 773 if (ret < 0) { 774 dev_err(priv->dev, "poll timeout\n"); 775 goto out; 776 } 777 778 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 779 MT7531_MDIO_REG_ADDR(regnum) | data; 780 781 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 782 783 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 784 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 785 if (ret < 0) { 786 dev_err(priv->dev, "poll timeout\n"); 787 goto out; 788 } 789 790 out: 791 mt7530_mutex_unlock(priv); 792 793 return ret; 794 } 795 796 static int 797 mt753x_phy_read_c22(struct mii_bus *bus, int port, int regnum) 798 { 799 struct mt7530_priv *priv = bus->priv; 800 801 return priv->info->phy_read_c22(priv, port, regnum); 802 } 803 804 static int 805 mt753x_phy_read_c45(struct mii_bus *bus, int port, int devad, int regnum) 806 { 807 struct mt7530_priv *priv = bus->priv; 808 809 return priv->info->phy_read_c45(priv, port, devad, regnum); 810 } 811 812 static int 813 mt753x_phy_write_c22(struct mii_bus *bus, int port, int regnum, u16 val) 814 { 815 struct mt7530_priv *priv = bus->priv; 816 817 return priv->info->phy_write_c22(priv, port, regnum, val); 818 } 819 820 static int 821 mt753x_phy_write_c45(struct mii_bus *bus, int port, int devad, int regnum, 822 u16 val) 823 { 824 struct mt7530_priv *priv = bus->priv; 825 826 return priv->info->phy_write_c45(priv, port, devad, regnum, val); 827 } 828 829 static void 830 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 831 uint8_t *data) 832 { 833 int i; 834 835 if (stringset != ETH_SS_STATS) 836 return; 837 838 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 839 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 840 ETH_GSTRING_LEN); 841 } 842 843 static void 844 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 845 uint64_t *data) 846 { 847 struct mt7530_priv *priv = ds->priv; 848 const struct mt7530_mib_desc *mib; 849 u32 reg, i; 850 u64 hi; 851 852 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 853 mib = &mt7530_mib[i]; 854 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 855 856 data[i] = mt7530_read(priv, reg); 857 if (mib->size == 2) { 858 hi = mt7530_read(priv, reg + 4); 859 data[i] |= hi << 32; 860 } 861 } 862 } 863 864 static int 865 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 866 { 867 if (sset != ETH_SS_STATS) 868 return 0; 869 870 return ARRAY_SIZE(mt7530_mib); 871 } 872 873 static int 874 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 875 { 876 struct mt7530_priv *priv = ds->priv; 877 unsigned int secs = msecs / 1000; 878 unsigned int tmp_age_count; 879 unsigned int error = -1; 880 unsigned int age_count; 881 unsigned int age_unit; 882 883 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 884 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 885 return -ERANGE; 886 887 /* iterate through all possible age_count to find the closest pair */ 888 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 889 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 890 891 if (tmp_age_unit <= AGE_UNIT_MAX) { 892 unsigned int tmp_error = secs - 893 (tmp_age_count + 1) * (tmp_age_unit + 1); 894 895 /* found a closer pair */ 896 if (error > tmp_error) { 897 error = tmp_error; 898 age_count = tmp_age_count; 899 age_unit = tmp_age_unit; 900 } 901 902 /* found the exact match, so break the loop */ 903 if (!error) 904 break; 905 } 906 } 907 908 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 909 910 return 0; 911 } 912 913 static const char *p5_intf_modes(unsigned int p5_interface) 914 { 915 switch (p5_interface) { 916 case P5_DISABLED: 917 return "DISABLED"; 918 case P5_INTF_SEL_PHY_P0: 919 return "PHY P0"; 920 case P5_INTF_SEL_PHY_P4: 921 return "PHY P4"; 922 case P5_INTF_SEL_GMAC5: 923 return "GMAC5"; 924 case P5_INTF_SEL_GMAC5_SGMII: 925 return "GMAC5_SGMII"; 926 default: 927 return "unknown"; 928 } 929 } 930 931 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 932 { 933 struct mt7530_priv *priv = ds->priv; 934 u8 tx_delay = 0; 935 int val; 936 937 mutex_lock(&priv->reg_mutex); 938 939 val = mt7530_read(priv, MT7530_MHWTRAP); 940 941 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 942 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 943 944 switch (priv->p5_intf_sel) { 945 case P5_INTF_SEL_PHY_P0: 946 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 947 val |= MHWTRAP_PHY0_SEL; 948 fallthrough; 949 case P5_INTF_SEL_PHY_P4: 950 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 951 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 952 953 /* Setup the MAC by default for the cpu port */ 954 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 955 break; 956 case P5_INTF_SEL_GMAC5: 957 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 958 val &= ~MHWTRAP_P5_DIS; 959 break; 960 case P5_DISABLED: 961 interface = PHY_INTERFACE_MODE_NA; 962 break; 963 default: 964 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 965 priv->p5_intf_sel); 966 goto unlock_exit; 967 } 968 969 /* Setup RGMII settings */ 970 if (phy_interface_mode_is_rgmii(interface)) { 971 val |= MHWTRAP_P5_RGMII_MODE; 972 973 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 974 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 975 976 /* Don't set delay in DSA mode */ 977 if (!dsa_is_dsa_port(priv->ds, 5) && 978 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 979 interface == PHY_INTERFACE_MODE_RGMII_ID)) 980 tx_delay = 4; /* n * 0.5 ns */ 981 982 /* P5 RGMII TX Clock Control: delay x */ 983 mt7530_write(priv, MT7530_P5RGMIITXCR, 984 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 985 986 /* reduce P5 RGMII Tx driving, 8mA */ 987 mt7530_write(priv, MT7530_IO_DRV_CR, 988 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 989 } 990 991 mt7530_write(priv, MT7530_MHWTRAP, val); 992 993 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 994 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 995 996 priv->p5_interface = interface; 997 998 unlock_exit: 999 mutex_unlock(&priv->reg_mutex); 1000 } 1001 1002 static void 1003 mt753x_trap_frames(struct mt7530_priv *priv) 1004 { 1005 /* Trap BPDUs to the CPU port(s) */ 1006 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 1007 MT753X_BPDU_CPU_ONLY); 1008 1009 /* Trap LLDP frames with :0E MAC DA to the CPU port(s) */ 1010 mt7530_rmw(priv, MT753X_RGAC2, MT753X_R0E_PORT_FW_MASK, 1011 MT753X_R0E_PORT_FW(MT753X_BPDU_CPU_ONLY)); 1012 } 1013 1014 static int 1015 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 1016 { 1017 struct mt7530_priv *priv = ds->priv; 1018 int ret; 1019 1020 /* Setup max capability of CPU port at first */ 1021 if (priv->info->cpu_port_config) { 1022 ret = priv->info->cpu_port_config(ds, port); 1023 if (ret) 1024 return ret; 1025 } 1026 1027 /* Enable Mediatek header mode on the cpu port */ 1028 mt7530_write(priv, MT7530_PVC_P(port), 1029 PORT_SPEC_TAG); 1030 1031 /* Enable flooding on the CPU port */ 1032 mt7530_set(priv, MT7530_MFC, BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | 1033 UNU_FFP(BIT(port))); 1034 1035 /* Set CPU port number */ 1036 if (priv->id == ID_MT7530 || priv->id == ID_MT7621) 1037 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1038 1039 /* Add the CPU port to the CPU port bitmap for MT7531 and the switch on 1040 * the MT7988 SoC. Trapped frames will be forwarded to the CPU port that 1041 * is affine to the inbound user port. 1042 */ 1043 if (priv->id == ID_MT7531 || priv->id == ID_MT7988) 1044 mt7530_set(priv, MT7531_CFC, MT7531_CPU_PMAP(BIT(port))); 1045 1046 /* CPU port gets connected to all user ports of 1047 * the switch. 1048 */ 1049 mt7530_write(priv, MT7530_PCR_P(port), 1050 PCR_MATRIX(dsa_user_ports(priv->ds))); 1051 1052 /* Set to fallback mode for independent VLAN learning */ 1053 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1054 MT7530_PORT_FALLBACK_MODE); 1055 1056 return 0; 1057 } 1058 1059 static int 1060 mt7530_port_enable(struct dsa_switch *ds, int port, 1061 struct phy_device *phy) 1062 { 1063 struct dsa_port *dp = dsa_to_port(ds, port); 1064 struct mt7530_priv *priv = ds->priv; 1065 1066 mutex_lock(&priv->reg_mutex); 1067 1068 /* Allow the user port gets connected to the cpu port and also 1069 * restore the port matrix if the port is the member of a certain 1070 * bridge. 1071 */ 1072 if (dsa_port_is_user(dp)) { 1073 struct dsa_port *cpu_dp = dp->cpu_dp; 1074 1075 priv->ports[port].pm |= PCR_MATRIX(BIT(cpu_dp->index)); 1076 } 1077 priv->ports[port].enable = true; 1078 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1079 priv->ports[port].pm); 1080 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1081 1082 mutex_unlock(&priv->reg_mutex); 1083 1084 return 0; 1085 } 1086 1087 static void 1088 mt7530_port_disable(struct dsa_switch *ds, int port) 1089 { 1090 struct mt7530_priv *priv = ds->priv; 1091 1092 mutex_lock(&priv->reg_mutex); 1093 1094 /* Clear up all port matrix which could be restored in the next 1095 * enablement for the port. 1096 */ 1097 priv->ports[port].enable = false; 1098 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1099 PCR_MATRIX_CLR); 1100 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1101 1102 mutex_unlock(&priv->reg_mutex); 1103 } 1104 1105 static int 1106 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1107 { 1108 struct mt7530_priv *priv = ds->priv; 1109 int length; 1110 u32 val; 1111 1112 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1113 * largest MTU of the slave ports. Because the switch only has a global 1114 * RX length register, only allowing CPU port here is enough. 1115 */ 1116 if (!dsa_is_cpu_port(ds, port)) 1117 return 0; 1118 1119 mt7530_mutex_lock(priv); 1120 1121 val = mt7530_mii_read(priv, MT7530_GMACCR); 1122 val &= ~MAX_RX_PKT_LEN_MASK; 1123 1124 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1125 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1126 if (length <= 1522) { 1127 val |= MAX_RX_PKT_LEN_1522; 1128 } else if (length <= 1536) { 1129 val |= MAX_RX_PKT_LEN_1536; 1130 } else if (length <= 1552) { 1131 val |= MAX_RX_PKT_LEN_1552; 1132 } else { 1133 val &= ~MAX_RX_JUMBO_MASK; 1134 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1135 val |= MAX_RX_PKT_LEN_JUMBO; 1136 } 1137 1138 mt7530_mii_write(priv, MT7530_GMACCR, val); 1139 1140 mt7530_mutex_unlock(priv); 1141 1142 return 0; 1143 } 1144 1145 static int 1146 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1147 { 1148 return MT7530_MAX_MTU; 1149 } 1150 1151 static void 1152 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1153 { 1154 struct mt7530_priv *priv = ds->priv; 1155 u32 stp_state; 1156 1157 switch (state) { 1158 case BR_STATE_DISABLED: 1159 stp_state = MT7530_STP_DISABLED; 1160 break; 1161 case BR_STATE_BLOCKING: 1162 stp_state = MT7530_STP_BLOCKING; 1163 break; 1164 case BR_STATE_LISTENING: 1165 stp_state = MT7530_STP_LISTENING; 1166 break; 1167 case BR_STATE_LEARNING: 1168 stp_state = MT7530_STP_LEARNING; 1169 break; 1170 case BR_STATE_FORWARDING: 1171 default: 1172 stp_state = MT7530_STP_FORWARDING; 1173 break; 1174 } 1175 1176 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK(FID_BRIDGED), 1177 FID_PST(FID_BRIDGED, stp_state)); 1178 } 1179 1180 static int 1181 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1182 struct switchdev_brport_flags flags, 1183 struct netlink_ext_ack *extack) 1184 { 1185 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1186 BR_BCAST_FLOOD)) 1187 return -EINVAL; 1188 1189 return 0; 1190 } 1191 1192 static int 1193 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1194 struct switchdev_brport_flags flags, 1195 struct netlink_ext_ack *extack) 1196 { 1197 struct mt7530_priv *priv = ds->priv; 1198 1199 if (flags.mask & BR_LEARNING) 1200 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1201 flags.val & BR_LEARNING ? 0 : SA_DIS); 1202 1203 if (flags.mask & BR_FLOOD) 1204 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1205 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1206 1207 if (flags.mask & BR_MCAST_FLOOD) 1208 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1209 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1210 1211 if (flags.mask & BR_BCAST_FLOOD) 1212 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1213 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1214 1215 return 0; 1216 } 1217 1218 static int 1219 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1220 struct dsa_bridge bridge, bool *tx_fwd_offload, 1221 struct netlink_ext_ack *extack) 1222 { 1223 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1224 struct dsa_port *cpu_dp = dp->cpu_dp; 1225 u32 port_bitmap = BIT(cpu_dp->index); 1226 struct mt7530_priv *priv = ds->priv; 1227 1228 mutex_lock(&priv->reg_mutex); 1229 1230 dsa_switch_for_each_user_port(other_dp, ds) { 1231 int other_port = other_dp->index; 1232 1233 if (dp == other_dp) 1234 continue; 1235 1236 /* Add this port to the port matrix of the other ports in the 1237 * same bridge. If the port is disabled, port matrix is kept 1238 * and not being setup until the port becomes enabled. 1239 */ 1240 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1241 continue; 1242 1243 if (priv->ports[other_port].enable) 1244 mt7530_set(priv, MT7530_PCR_P(other_port), 1245 PCR_MATRIX(BIT(port))); 1246 priv->ports[other_port].pm |= PCR_MATRIX(BIT(port)); 1247 1248 port_bitmap |= BIT(other_port); 1249 } 1250 1251 /* Add the all other ports to this port matrix. */ 1252 if (priv->ports[port].enable) 1253 mt7530_rmw(priv, MT7530_PCR_P(port), 1254 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1255 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1256 1257 /* Set to fallback mode for independent VLAN learning */ 1258 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1259 MT7530_PORT_FALLBACK_MODE); 1260 1261 mutex_unlock(&priv->reg_mutex); 1262 1263 return 0; 1264 } 1265 1266 static void 1267 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1268 { 1269 struct mt7530_priv *priv = ds->priv; 1270 bool all_user_ports_removed = true; 1271 int i; 1272 1273 /* This is called after .port_bridge_leave when leaving a VLAN-aware 1274 * bridge. Don't set standalone ports to fallback mode. 1275 */ 1276 if (dsa_port_bridge_dev_get(dsa_to_port(ds, port))) 1277 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1278 MT7530_PORT_FALLBACK_MODE); 1279 1280 mt7530_rmw(priv, MT7530_PVC_P(port), 1281 VLAN_ATTR_MASK | PVC_EG_TAG_MASK | ACC_FRM_MASK, 1282 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1283 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT) | 1284 MT7530_VLAN_ACC_ALL); 1285 1286 /* Set PVID to 0 */ 1287 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1288 G0_PORT_VID_DEF); 1289 1290 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1291 if (dsa_is_user_port(ds, i) && 1292 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1293 all_user_ports_removed = false; 1294 break; 1295 } 1296 } 1297 1298 /* CPU port also does the same thing until all user ports belonging to 1299 * the CPU port get out of VLAN filtering mode. 1300 */ 1301 if (all_user_ports_removed) { 1302 struct dsa_port *dp = dsa_to_port(ds, port); 1303 struct dsa_port *cpu_dp = dp->cpu_dp; 1304 1305 mt7530_write(priv, MT7530_PCR_P(cpu_dp->index), 1306 PCR_MATRIX(dsa_user_ports(priv->ds))); 1307 mt7530_write(priv, MT7530_PVC_P(cpu_dp->index), PORT_SPEC_TAG 1308 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1309 } 1310 } 1311 1312 static void 1313 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1314 { 1315 struct mt7530_priv *priv = ds->priv; 1316 1317 /* Trapped into security mode allows packet forwarding through VLAN 1318 * table lookup. 1319 */ 1320 if (dsa_is_user_port(ds, port)) { 1321 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1322 MT7530_PORT_SECURITY_MODE); 1323 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1324 G0_PORT_VID(priv->ports[port].pvid)); 1325 1326 /* Only accept tagged frames if PVID is not set */ 1327 if (!priv->ports[port].pvid) 1328 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1329 MT7530_VLAN_ACC_TAGGED); 1330 1331 /* Set the port as a user port which is to be able to recognize 1332 * VID from incoming packets before fetching entry within the 1333 * VLAN table. 1334 */ 1335 mt7530_rmw(priv, MT7530_PVC_P(port), 1336 VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1337 VLAN_ATTR(MT7530_VLAN_USER) | 1338 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1339 } else { 1340 /* Also set CPU ports to the "user" VLAN port attribute, to 1341 * allow VLAN classification, but keep the EG_TAG attribute as 1342 * "consistent" (i.o.w. don't change its value) for packets 1343 * received by the switch from the CPU, so that tagged packets 1344 * are forwarded to user ports as tagged, and untagged as 1345 * untagged. 1346 */ 1347 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK, 1348 VLAN_ATTR(MT7530_VLAN_USER)); 1349 } 1350 } 1351 1352 static void 1353 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1354 struct dsa_bridge bridge) 1355 { 1356 struct dsa_port *dp = dsa_to_port(ds, port), *other_dp; 1357 struct dsa_port *cpu_dp = dp->cpu_dp; 1358 struct mt7530_priv *priv = ds->priv; 1359 1360 mutex_lock(&priv->reg_mutex); 1361 1362 dsa_switch_for_each_user_port(other_dp, ds) { 1363 int other_port = other_dp->index; 1364 1365 if (dp == other_dp) 1366 continue; 1367 1368 /* Remove this port from the port matrix of the other ports 1369 * in the same bridge. If the port is disabled, port matrix 1370 * is kept and not being setup until the port becomes enabled. 1371 */ 1372 if (!dsa_port_offloads_bridge(other_dp, &bridge)) 1373 continue; 1374 1375 if (priv->ports[other_port].enable) 1376 mt7530_clear(priv, MT7530_PCR_P(other_port), 1377 PCR_MATRIX(BIT(port))); 1378 priv->ports[other_port].pm &= ~PCR_MATRIX(BIT(port)); 1379 } 1380 1381 /* Set the cpu port to be the only one in the port matrix of 1382 * this port. 1383 */ 1384 if (priv->ports[port].enable) 1385 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1386 PCR_MATRIX(BIT(cpu_dp->index))); 1387 priv->ports[port].pm = PCR_MATRIX(BIT(cpu_dp->index)); 1388 1389 /* When a port is removed from the bridge, the port would be set up 1390 * back to the default as is at initial boot which is a VLAN-unaware 1391 * port. 1392 */ 1393 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1394 MT7530_PORT_MATRIX_MODE); 1395 1396 mutex_unlock(&priv->reg_mutex); 1397 } 1398 1399 static int 1400 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1401 const unsigned char *addr, u16 vid, 1402 struct dsa_db db) 1403 { 1404 struct mt7530_priv *priv = ds->priv; 1405 int ret; 1406 u8 port_mask = BIT(port); 1407 1408 mutex_lock(&priv->reg_mutex); 1409 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1410 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1411 mutex_unlock(&priv->reg_mutex); 1412 1413 return ret; 1414 } 1415 1416 static int 1417 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1418 const unsigned char *addr, u16 vid, 1419 struct dsa_db db) 1420 { 1421 struct mt7530_priv *priv = ds->priv; 1422 int ret; 1423 u8 port_mask = BIT(port); 1424 1425 mutex_lock(&priv->reg_mutex); 1426 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1427 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1428 mutex_unlock(&priv->reg_mutex); 1429 1430 return ret; 1431 } 1432 1433 static int 1434 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1435 dsa_fdb_dump_cb_t *cb, void *data) 1436 { 1437 struct mt7530_priv *priv = ds->priv; 1438 struct mt7530_fdb _fdb = { 0 }; 1439 int cnt = MT7530_NUM_FDB_RECORDS; 1440 int ret = 0; 1441 u32 rsp = 0; 1442 1443 mutex_lock(&priv->reg_mutex); 1444 1445 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1446 if (ret < 0) 1447 goto err; 1448 1449 do { 1450 if (rsp & ATC_SRCH_HIT) { 1451 mt7530_fdb_read(priv, &_fdb); 1452 if (_fdb.port_mask & BIT(port)) { 1453 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1454 data); 1455 if (ret < 0) 1456 break; 1457 } 1458 } 1459 } while (--cnt && 1460 !(rsp & ATC_SRCH_END) && 1461 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1462 err: 1463 mutex_unlock(&priv->reg_mutex); 1464 1465 return 0; 1466 } 1467 1468 static int 1469 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1470 const struct switchdev_obj_port_mdb *mdb, 1471 struct dsa_db db) 1472 { 1473 struct mt7530_priv *priv = ds->priv; 1474 const u8 *addr = mdb->addr; 1475 u16 vid = mdb->vid; 1476 u8 port_mask = 0; 1477 int ret; 1478 1479 mutex_lock(&priv->reg_mutex); 1480 1481 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1482 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1483 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1484 & PORT_MAP_MASK; 1485 1486 port_mask |= BIT(port); 1487 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1488 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1489 1490 mutex_unlock(&priv->reg_mutex); 1491 1492 return ret; 1493 } 1494 1495 static int 1496 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1497 const struct switchdev_obj_port_mdb *mdb, 1498 struct dsa_db db) 1499 { 1500 struct mt7530_priv *priv = ds->priv; 1501 const u8 *addr = mdb->addr; 1502 u16 vid = mdb->vid; 1503 u8 port_mask = 0; 1504 int ret; 1505 1506 mutex_lock(&priv->reg_mutex); 1507 1508 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1509 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1510 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1511 & PORT_MAP_MASK; 1512 1513 port_mask &= ~BIT(port); 1514 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1515 port_mask ? STATIC_ENT : STATIC_EMP); 1516 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1517 1518 mutex_unlock(&priv->reg_mutex); 1519 1520 return ret; 1521 } 1522 1523 static int 1524 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1525 { 1526 struct mt7530_dummy_poll p; 1527 u32 val; 1528 int ret; 1529 1530 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1531 mt7530_write(priv, MT7530_VTCR, val); 1532 1533 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1534 ret = readx_poll_timeout(_mt7530_read, &p, val, 1535 !(val & VTCR_BUSY), 20, 20000); 1536 if (ret < 0) { 1537 dev_err(priv->dev, "poll timeout\n"); 1538 return ret; 1539 } 1540 1541 val = mt7530_read(priv, MT7530_VTCR); 1542 if (val & VTCR_INVALID) { 1543 dev_err(priv->dev, "read VTCR invalid\n"); 1544 return -EINVAL; 1545 } 1546 1547 return 0; 1548 } 1549 1550 static int 1551 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1552 struct netlink_ext_ack *extack) 1553 { 1554 struct dsa_port *dp = dsa_to_port(ds, port); 1555 struct dsa_port *cpu_dp = dp->cpu_dp; 1556 1557 if (vlan_filtering) { 1558 /* The port is being kept as VLAN-unaware port when bridge is 1559 * set up with vlan_filtering not being set, Otherwise, the 1560 * port and the corresponding CPU port is required the setup 1561 * for becoming a VLAN-aware port. 1562 */ 1563 mt7530_port_set_vlan_aware(ds, port); 1564 mt7530_port_set_vlan_aware(ds, cpu_dp->index); 1565 } else { 1566 mt7530_port_set_vlan_unaware(ds, port); 1567 } 1568 1569 return 0; 1570 } 1571 1572 static void 1573 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1574 struct mt7530_hw_vlan_entry *entry) 1575 { 1576 struct dsa_port *dp = dsa_to_port(priv->ds, entry->port); 1577 u8 new_members; 1578 u32 val; 1579 1580 new_members = entry->old_members | BIT(entry->port); 1581 1582 /* Validate the entry with independent learning, create egress tag per 1583 * VLAN and joining the port as one of the port members. 1584 */ 1585 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | FID(FID_BRIDGED) | 1586 VLAN_VALID; 1587 mt7530_write(priv, MT7530_VAWD1, val); 1588 1589 /* Decide whether adding tag or not for those outgoing packets from the 1590 * port inside the VLAN. 1591 * CPU port is always taken as a tagged port for serving more than one 1592 * VLANs across and also being applied with egress type stack mode for 1593 * that VLAN tags would be appended after hardware special tag used as 1594 * DSA tag. 1595 */ 1596 if (dsa_port_is_cpu(dp)) 1597 val = MT7530_VLAN_EGRESS_STACK; 1598 else if (entry->untagged) 1599 val = MT7530_VLAN_EGRESS_UNTAG; 1600 else 1601 val = MT7530_VLAN_EGRESS_TAG; 1602 mt7530_rmw(priv, MT7530_VAWD2, 1603 ETAG_CTRL_P_MASK(entry->port), 1604 ETAG_CTRL_P(entry->port, val)); 1605 } 1606 1607 static void 1608 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1609 struct mt7530_hw_vlan_entry *entry) 1610 { 1611 u8 new_members; 1612 u32 val; 1613 1614 new_members = entry->old_members & ~BIT(entry->port); 1615 1616 val = mt7530_read(priv, MT7530_VAWD1); 1617 if (!(val & VLAN_VALID)) { 1618 dev_err(priv->dev, 1619 "Cannot be deleted due to invalid entry\n"); 1620 return; 1621 } 1622 1623 if (new_members) { 1624 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1625 VLAN_VALID; 1626 mt7530_write(priv, MT7530_VAWD1, val); 1627 } else { 1628 mt7530_write(priv, MT7530_VAWD1, 0); 1629 mt7530_write(priv, MT7530_VAWD2, 0); 1630 } 1631 } 1632 1633 static void 1634 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1635 struct mt7530_hw_vlan_entry *entry, 1636 mt7530_vlan_op vlan_op) 1637 { 1638 u32 val; 1639 1640 /* Fetch entry */ 1641 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1642 1643 val = mt7530_read(priv, MT7530_VAWD1); 1644 1645 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1646 1647 /* Manipulate entry */ 1648 vlan_op(priv, entry); 1649 1650 /* Flush result to hardware */ 1651 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1652 } 1653 1654 static int 1655 mt7530_setup_vlan0(struct mt7530_priv *priv) 1656 { 1657 u32 val; 1658 1659 /* Validate the entry with independent learning, keep the original 1660 * ingress tag attribute. 1661 */ 1662 val = IVL_MAC | EG_CON | PORT_MEM(MT7530_ALL_MEMBERS) | FID(FID_BRIDGED) | 1663 VLAN_VALID; 1664 mt7530_write(priv, MT7530_VAWD1, val); 1665 1666 return mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, 0); 1667 } 1668 1669 static int 1670 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1671 const struct switchdev_obj_port_vlan *vlan, 1672 struct netlink_ext_ack *extack) 1673 { 1674 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1675 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1676 struct mt7530_hw_vlan_entry new_entry; 1677 struct mt7530_priv *priv = ds->priv; 1678 1679 mutex_lock(&priv->reg_mutex); 1680 1681 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1682 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1683 1684 if (pvid) { 1685 priv->ports[port].pvid = vlan->vid; 1686 1687 /* Accept all frames if PVID is set */ 1688 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1689 MT7530_VLAN_ACC_ALL); 1690 1691 /* Only configure PVID if VLAN filtering is enabled */ 1692 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1693 mt7530_rmw(priv, MT7530_PPBV1_P(port), 1694 G0_PORT_VID_MASK, 1695 G0_PORT_VID(vlan->vid)); 1696 } else if (vlan->vid && priv->ports[port].pvid == vlan->vid) { 1697 /* This VLAN is overwritten without PVID, so unset it */ 1698 priv->ports[port].pvid = G0_PORT_VID_DEF; 1699 1700 /* Only accept tagged frames if the port is VLAN-aware */ 1701 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1702 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1703 MT7530_VLAN_ACC_TAGGED); 1704 1705 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1706 G0_PORT_VID_DEF); 1707 } 1708 1709 mutex_unlock(&priv->reg_mutex); 1710 1711 return 0; 1712 } 1713 1714 static int 1715 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1716 const struct switchdev_obj_port_vlan *vlan) 1717 { 1718 struct mt7530_hw_vlan_entry target_entry; 1719 struct mt7530_priv *priv = ds->priv; 1720 1721 mutex_lock(&priv->reg_mutex); 1722 1723 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1724 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1725 mt7530_hw_vlan_del); 1726 1727 /* PVID is being restored to the default whenever the PVID port 1728 * is being removed from the VLAN. 1729 */ 1730 if (priv->ports[port].pvid == vlan->vid) { 1731 priv->ports[port].pvid = G0_PORT_VID_DEF; 1732 1733 /* Only accept tagged frames if the port is VLAN-aware */ 1734 if (dsa_port_is_vlan_filtering(dsa_to_port(ds, port))) 1735 mt7530_rmw(priv, MT7530_PVC_P(port), ACC_FRM_MASK, 1736 MT7530_VLAN_ACC_TAGGED); 1737 1738 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1739 G0_PORT_VID_DEF); 1740 } 1741 1742 1743 mutex_unlock(&priv->reg_mutex); 1744 1745 return 0; 1746 } 1747 1748 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1749 { 1750 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1751 MIRROR_PORT(val); 1752 } 1753 1754 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1755 { 1756 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1757 MIRROR_PORT(val); 1758 } 1759 1760 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1761 struct dsa_mall_mirror_tc_entry *mirror, 1762 bool ingress, struct netlink_ext_ack *extack) 1763 { 1764 struct mt7530_priv *priv = ds->priv; 1765 int monitor_port; 1766 u32 val; 1767 1768 /* Check for existent entry */ 1769 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1770 return -EEXIST; 1771 1772 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1773 1774 /* MT7530 only supports one monitor port */ 1775 monitor_port = mt753x_mirror_port_get(priv->id, val); 1776 if (val & MT753X_MIRROR_EN(priv->id) && 1777 monitor_port != mirror->to_local_port) 1778 return -EEXIST; 1779 1780 val |= MT753X_MIRROR_EN(priv->id); 1781 val &= ~MT753X_MIRROR_MASK(priv->id); 1782 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1783 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1784 1785 val = mt7530_read(priv, MT7530_PCR_P(port)); 1786 if (ingress) { 1787 val |= PORT_RX_MIR; 1788 priv->mirror_rx |= BIT(port); 1789 } else { 1790 val |= PORT_TX_MIR; 1791 priv->mirror_tx |= BIT(port); 1792 } 1793 mt7530_write(priv, MT7530_PCR_P(port), val); 1794 1795 return 0; 1796 } 1797 1798 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1799 struct dsa_mall_mirror_tc_entry *mirror) 1800 { 1801 struct mt7530_priv *priv = ds->priv; 1802 u32 val; 1803 1804 val = mt7530_read(priv, MT7530_PCR_P(port)); 1805 if (mirror->ingress) { 1806 val &= ~PORT_RX_MIR; 1807 priv->mirror_rx &= ~BIT(port); 1808 } else { 1809 val &= ~PORT_TX_MIR; 1810 priv->mirror_tx &= ~BIT(port); 1811 } 1812 mt7530_write(priv, MT7530_PCR_P(port), val); 1813 1814 if (!priv->mirror_rx && !priv->mirror_tx) { 1815 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1816 val &= ~MT753X_MIRROR_EN(priv->id); 1817 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1818 } 1819 } 1820 1821 static enum dsa_tag_protocol 1822 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1823 enum dsa_tag_protocol mp) 1824 { 1825 return DSA_TAG_PROTO_MTK; 1826 } 1827 1828 #ifdef CONFIG_GPIOLIB 1829 static inline u32 1830 mt7530_gpio_to_bit(unsigned int offset) 1831 { 1832 /* Map GPIO offset to register bit 1833 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1834 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1835 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1836 * [14:12] port 3 LED 0..2 as GPIO 9..11 1837 * [18:16] port 4 LED 0..2 as GPIO 12..14 1838 */ 1839 return BIT(offset + offset / 3); 1840 } 1841 1842 static int 1843 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1844 { 1845 struct mt7530_priv *priv = gpiochip_get_data(gc); 1846 u32 bit = mt7530_gpio_to_bit(offset); 1847 1848 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1849 } 1850 1851 static void 1852 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1853 { 1854 struct mt7530_priv *priv = gpiochip_get_data(gc); 1855 u32 bit = mt7530_gpio_to_bit(offset); 1856 1857 if (value) 1858 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1859 else 1860 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1861 } 1862 1863 static int 1864 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1865 { 1866 struct mt7530_priv *priv = gpiochip_get_data(gc); 1867 u32 bit = mt7530_gpio_to_bit(offset); 1868 1869 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1870 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1871 } 1872 1873 static int 1874 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1875 { 1876 struct mt7530_priv *priv = gpiochip_get_data(gc); 1877 u32 bit = mt7530_gpio_to_bit(offset); 1878 1879 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1880 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1881 1882 return 0; 1883 } 1884 1885 static int 1886 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1887 { 1888 struct mt7530_priv *priv = gpiochip_get_data(gc); 1889 u32 bit = mt7530_gpio_to_bit(offset); 1890 1891 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1892 1893 if (value) 1894 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1895 else 1896 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1897 1898 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1899 1900 return 0; 1901 } 1902 1903 static int 1904 mt7530_setup_gpio(struct mt7530_priv *priv) 1905 { 1906 struct device *dev = priv->dev; 1907 struct gpio_chip *gc; 1908 1909 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1910 if (!gc) 1911 return -ENOMEM; 1912 1913 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1914 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1915 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1916 1917 gc->label = "mt7530"; 1918 gc->parent = dev; 1919 gc->owner = THIS_MODULE; 1920 gc->get_direction = mt7530_gpio_get_direction; 1921 gc->direction_input = mt7530_gpio_direction_input; 1922 gc->direction_output = mt7530_gpio_direction_output; 1923 gc->get = mt7530_gpio_get; 1924 gc->set = mt7530_gpio_set; 1925 gc->base = -1; 1926 gc->ngpio = 15; 1927 gc->can_sleep = true; 1928 1929 return devm_gpiochip_add_data(dev, gc, priv); 1930 } 1931 #endif /* CONFIG_GPIOLIB */ 1932 1933 static irqreturn_t 1934 mt7530_irq_thread_fn(int irq, void *dev_id) 1935 { 1936 struct mt7530_priv *priv = dev_id; 1937 bool handled = false; 1938 u32 val; 1939 int p; 1940 1941 mt7530_mutex_lock(priv); 1942 val = mt7530_mii_read(priv, MT7530_SYS_INT_STS); 1943 mt7530_mii_write(priv, MT7530_SYS_INT_STS, val); 1944 mt7530_mutex_unlock(priv); 1945 1946 for (p = 0; p < MT7530_NUM_PHYS; p++) { 1947 if (BIT(p) & val) { 1948 unsigned int irq; 1949 1950 irq = irq_find_mapping(priv->irq_domain, p); 1951 handle_nested_irq(irq); 1952 handled = true; 1953 } 1954 } 1955 1956 return IRQ_RETVAL(handled); 1957 } 1958 1959 static void 1960 mt7530_irq_mask(struct irq_data *d) 1961 { 1962 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1963 1964 priv->irq_enable &= ~BIT(d->hwirq); 1965 } 1966 1967 static void 1968 mt7530_irq_unmask(struct irq_data *d) 1969 { 1970 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1971 1972 priv->irq_enable |= BIT(d->hwirq); 1973 } 1974 1975 static void 1976 mt7530_irq_bus_lock(struct irq_data *d) 1977 { 1978 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1979 1980 mt7530_mutex_lock(priv); 1981 } 1982 1983 static void 1984 mt7530_irq_bus_sync_unlock(struct irq_data *d) 1985 { 1986 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 1987 1988 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 1989 mt7530_mutex_unlock(priv); 1990 } 1991 1992 static struct irq_chip mt7530_irq_chip = { 1993 .name = KBUILD_MODNAME, 1994 .irq_mask = mt7530_irq_mask, 1995 .irq_unmask = mt7530_irq_unmask, 1996 .irq_bus_lock = mt7530_irq_bus_lock, 1997 .irq_bus_sync_unlock = mt7530_irq_bus_sync_unlock, 1998 }; 1999 2000 static int 2001 mt7530_irq_map(struct irq_domain *domain, unsigned int irq, 2002 irq_hw_number_t hwirq) 2003 { 2004 irq_set_chip_data(irq, domain->host_data); 2005 irq_set_chip_and_handler(irq, &mt7530_irq_chip, handle_simple_irq); 2006 irq_set_nested_thread(irq, true); 2007 irq_set_noprobe(irq); 2008 2009 return 0; 2010 } 2011 2012 static const struct irq_domain_ops mt7530_irq_domain_ops = { 2013 .map = mt7530_irq_map, 2014 .xlate = irq_domain_xlate_onecell, 2015 }; 2016 2017 static void 2018 mt7988_irq_mask(struct irq_data *d) 2019 { 2020 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2021 2022 priv->irq_enable &= ~BIT(d->hwirq); 2023 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2024 } 2025 2026 static void 2027 mt7988_irq_unmask(struct irq_data *d) 2028 { 2029 struct mt7530_priv *priv = irq_data_get_irq_chip_data(d); 2030 2031 priv->irq_enable |= BIT(d->hwirq); 2032 mt7530_mii_write(priv, MT7530_SYS_INT_EN, priv->irq_enable); 2033 } 2034 2035 static struct irq_chip mt7988_irq_chip = { 2036 .name = KBUILD_MODNAME, 2037 .irq_mask = mt7988_irq_mask, 2038 .irq_unmask = mt7988_irq_unmask, 2039 }; 2040 2041 static int 2042 mt7988_irq_map(struct irq_domain *domain, unsigned int irq, 2043 irq_hw_number_t hwirq) 2044 { 2045 irq_set_chip_data(irq, domain->host_data); 2046 irq_set_chip_and_handler(irq, &mt7988_irq_chip, handle_simple_irq); 2047 irq_set_nested_thread(irq, true); 2048 irq_set_noprobe(irq); 2049 2050 return 0; 2051 } 2052 2053 static const struct irq_domain_ops mt7988_irq_domain_ops = { 2054 .map = mt7988_irq_map, 2055 .xlate = irq_domain_xlate_onecell, 2056 }; 2057 2058 static void 2059 mt7530_setup_mdio_irq(struct mt7530_priv *priv) 2060 { 2061 struct dsa_switch *ds = priv->ds; 2062 int p; 2063 2064 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2065 if (BIT(p) & ds->phys_mii_mask) { 2066 unsigned int irq; 2067 2068 irq = irq_create_mapping(priv->irq_domain, p); 2069 ds->slave_mii_bus->irq[p] = irq; 2070 } 2071 } 2072 } 2073 2074 static int 2075 mt7530_setup_irq(struct mt7530_priv *priv) 2076 { 2077 struct device *dev = priv->dev; 2078 struct device_node *np = dev->of_node; 2079 int ret; 2080 2081 if (!of_property_read_bool(np, "interrupt-controller")) { 2082 dev_info(dev, "no interrupt support\n"); 2083 return 0; 2084 } 2085 2086 priv->irq = of_irq_get(np, 0); 2087 if (priv->irq <= 0) { 2088 dev_err(dev, "failed to get parent IRQ: %d\n", priv->irq); 2089 return priv->irq ? : -EINVAL; 2090 } 2091 2092 if (priv->id == ID_MT7988) 2093 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2094 &mt7988_irq_domain_ops, 2095 priv); 2096 else 2097 priv->irq_domain = irq_domain_add_linear(np, MT7530_NUM_PHYS, 2098 &mt7530_irq_domain_ops, 2099 priv); 2100 2101 if (!priv->irq_domain) { 2102 dev_err(dev, "failed to create IRQ domain\n"); 2103 return -ENOMEM; 2104 } 2105 2106 /* This register must be set for MT7530 to properly fire interrupts */ 2107 if (priv->id != ID_MT7531) 2108 mt7530_set(priv, MT7530_TOP_SIG_CTRL, TOP_SIG_CTRL_NORMAL); 2109 2110 ret = request_threaded_irq(priv->irq, NULL, mt7530_irq_thread_fn, 2111 IRQF_ONESHOT, KBUILD_MODNAME, priv); 2112 if (ret) { 2113 irq_domain_remove(priv->irq_domain); 2114 dev_err(dev, "failed to request IRQ: %d\n", ret); 2115 return ret; 2116 } 2117 2118 return 0; 2119 } 2120 2121 static void 2122 mt7530_free_mdio_irq(struct mt7530_priv *priv) 2123 { 2124 int p; 2125 2126 for (p = 0; p < MT7530_NUM_PHYS; p++) { 2127 if (BIT(p) & priv->ds->phys_mii_mask) { 2128 unsigned int irq; 2129 2130 irq = irq_find_mapping(priv->irq_domain, p); 2131 irq_dispose_mapping(irq); 2132 } 2133 } 2134 } 2135 2136 static void 2137 mt7530_free_irq_common(struct mt7530_priv *priv) 2138 { 2139 free_irq(priv->irq, priv); 2140 irq_domain_remove(priv->irq_domain); 2141 } 2142 2143 static void 2144 mt7530_free_irq(struct mt7530_priv *priv) 2145 { 2146 mt7530_free_mdio_irq(priv); 2147 mt7530_free_irq_common(priv); 2148 } 2149 2150 static int 2151 mt7530_setup_mdio(struct mt7530_priv *priv) 2152 { 2153 struct dsa_switch *ds = priv->ds; 2154 struct device *dev = priv->dev; 2155 struct mii_bus *bus; 2156 static int idx; 2157 int ret; 2158 2159 bus = devm_mdiobus_alloc(dev); 2160 if (!bus) 2161 return -ENOMEM; 2162 2163 ds->slave_mii_bus = bus; 2164 bus->priv = priv; 2165 bus->name = KBUILD_MODNAME "-mii"; 2166 snprintf(bus->id, MII_BUS_ID_SIZE, KBUILD_MODNAME "-%d", idx++); 2167 bus->read = mt753x_phy_read_c22; 2168 bus->write = mt753x_phy_write_c22; 2169 bus->read_c45 = mt753x_phy_read_c45; 2170 bus->write_c45 = mt753x_phy_write_c45; 2171 bus->parent = dev; 2172 bus->phy_mask = ~ds->phys_mii_mask; 2173 2174 if (priv->irq) 2175 mt7530_setup_mdio_irq(priv); 2176 2177 ret = devm_mdiobus_register(dev, bus); 2178 if (ret) { 2179 dev_err(dev, "failed to register MDIO bus: %d\n", ret); 2180 if (priv->irq) 2181 mt7530_free_mdio_irq(priv); 2182 } 2183 2184 return ret; 2185 } 2186 2187 static int 2188 mt7530_setup(struct dsa_switch *ds) 2189 { 2190 struct mt7530_priv *priv = ds->priv; 2191 struct device_node *dn = NULL; 2192 struct device_node *phy_node; 2193 struct device_node *mac_np; 2194 struct mt7530_dummy_poll p; 2195 phy_interface_t interface; 2196 struct dsa_port *cpu_dp; 2197 u32 id, val; 2198 int ret, i; 2199 2200 /* The parent node of master netdev which holds the common system 2201 * controller also is the container for two GMACs nodes representing 2202 * as two netdev instances. 2203 */ 2204 dsa_switch_for_each_cpu_port(cpu_dp, ds) { 2205 dn = cpu_dp->master->dev.of_node->parent; 2206 /* It doesn't matter which CPU port is found first, 2207 * their masters should share the same parent OF node 2208 */ 2209 break; 2210 } 2211 2212 if (!dn) { 2213 dev_err(ds->dev, "parent OF node of DSA master not found"); 2214 return -EINVAL; 2215 } 2216 2217 ds->assisted_learning_on_cpu_port = true; 2218 ds->mtu_enforcement_ingress = true; 2219 2220 if (priv->id == ID_MT7530) { 2221 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 2222 ret = regulator_enable(priv->core_pwr); 2223 if (ret < 0) { 2224 dev_err(priv->dev, 2225 "Failed to enable core power: %d\n", ret); 2226 return ret; 2227 } 2228 2229 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 2230 ret = regulator_enable(priv->io_pwr); 2231 if (ret < 0) { 2232 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 2233 ret); 2234 return ret; 2235 } 2236 } 2237 2238 /* Reset whole chip through gpio pin or memory-mapped registers for 2239 * different type of hardware 2240 */ 2241 if (priv->mcm) { 2242 reset_control_assert(priv->rstc); 2243 usleep_range(1000, 1100); 2244 reset_control_deassert(priv->rstc); 2245 } else { 2246 gpiod_set_value_cansleep(priv->reset, 0); 2247 usleep_range(1000, 1100); 2248 gpiod_set_value_cansleep(priv->reset, 1); 2249 } 2250 2251 /* Waiting for MT7530 got to stable */ 2252 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2253 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2254 20, 1000000); 2255 if (ret < 0) { 2256 dev_err(priv->dev, "reset timeout\n"); 2257 return ret; 2258 } 2259 2260 id = mt7530_read(priv, MT7530_CREV); 2261 id >>= CHIP_NAME_SHIFT; 2262 if (id != MT7530_ID) { 2263 dev_err(priv->dev, "chip %x can't be supported\n", id); 2264 return -ENODEV; 2265 } 2266 2267 /* Reset the switch through internal reset */ 2268 mt7530_write(priv, MT7530_SYS_CTRL, 2269 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2270 SYS_CTRL_REG_RST); 2271 2272 mt7530_pll_setup(priv); 2273 2274 /* Lower Tx driving for TRGMII path */ 2275 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2276 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 2277 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 2278 2279 for (i = 0; i < NUM_TRGMII_CTRL; i++) 2280 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 2281 RD_TAP_MASK, RD_TAP(16)); 2282 2283 /* Enable port 6 */ 2284 val = mt7530_read(priv, MT7530_MHWTRAP); 2285 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 2286 val |= MHWTRAP_MANUAL; 2287 mt7530_write(priv, MT7530_MHWTRAP, val); 2288 2289 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2290 2291 mt753x_trap_frames(priv); 2292 2293 /* Enable and reset MIB counters */ 2294 mt7530_mib_reset(ds); 2295 2296 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2297 /* Disable forwarding by default on all ports */ 2298 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2299 PCR_MATRIX_CLR); 2300 2301 /* Disable learning by default on all ports */ 2302 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2303 2304 if (dsa_is_cpu_port(ds, i)) { 2305 ret = mt753x_cpu_port_enable(ds, i); 2306 if (ret) 2307 return ret; 2308 } else { 2309 mt7530_port_disable(ds, i); 2310 2311 /* Set default PVID to 0 on all user ports */ 2312 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2313 G0_PORT_VID_DEF); 2314 } 2315 /* Enable consistent egress tag */ 2316 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2317 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2318 } 2319 2320 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2321 ret = mt7530_setup_vlan0(priv); 2322 if (ret) 2323 return ret; 2324 2325 /* Setup port 5 */ 2326 priv->p5_intf_sel = P5_DISABLED; 2327 interface = PHY_INTERFACE_MODE_NA; 2328 2329 if (!dsa_is_unused_port(ds, 5)) { 2330 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2331 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 2332 if (ret && ret != -ENODEV) 2333 return ret; 2334 } else { 2335 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 2336 for_each_child_of_node(dn, mac_np) { 2337 if (!of_device_is_compatible(mac_np, 2338 "mediatek,eth-mac")) 2339 continue; 2340 2341 ret = of_property_read_u32(mac_np, "reg", &id); 2342 if (ret < 0 || id != 1) 2343 continue; 2344 2345 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 2346 if (!phy_node) 2347 continue; 2348 2349 if (phy_node->parent == priv->dev->of_node->parent) { 2350 ret = of_get_phy_mode(mac_np, &interface); 2351 if (ret && ret != -ENODEV) { 2352 of_node_put(mac_np); 2353 of_node_put(phy_node); 2354 return ret; 2355 } 2356 id = of_mdio_parse_addr(ds->dev, phy_node); 2357 if (id == 0) 2358 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 2359 if (id == 4) 2360 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 2361 } 2362 of_node_put(mac_np); 2363 of_node_put(phy_node); 2364 break; 2365 } 2366 } 2367 2368 #ifdef CONFIG_GPIOLIB 2369 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 2370 ret = mt7530_setup_gpio(priv); 2371 if (ret) 2372 return ret; 2373 } 2374 #endif /* CONFIG_GPIOLIB */ 2375 2376 mt7530_setup_port5(ds, interface); 2377 2378 /* Flush the FDB table */ 2379 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2380 if (ret < 0) 2381 return ret; 2382 2383 return 0; 2384 } 2385 2386 static int 2387 mt7531_setup_common(struct dsa_switch *ds) 2388 { 2389 struct mt7530_priv *priv = ds->priv; 2390 int ret, i; 2391 2392 mt753x_trap_frames(priv); 2393 2394 /* Enable and reset MIB counters */ 2395 mt7530_mib_reset(ds); 2396 2397 /* Disable flooding on all ports */ 2398 mt7530_clear(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | 2399 UNU_FFP_MASK); 2400 2401 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2402 /* Disable forwarding by default on all ports */ 2403 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2404 PCR_MATRIX_CLR); 2405 2406 /* Disable learning by default on all ports */ 2407 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2408 2409 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2410 2411 if (dsa_is_cpu_port(ds, i)) { 2412 ret = mt753x_cpu_port_enable(ds, i); 2413 if (ret) 2414 return ret; 2415 } else { 2416 mt7530_port_disable(ds, i); 2417 2418 /* Set default PVID to 0 on all user ports */ 2419 mt7530_rmw(priv, MT7530_PPBV1_P(i), G0_PORT_VID_MASK, 2420 G0_PORT_VID_DEF); 2421 } 2422 2423 /* Enable consistent egress tag */ 2424 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2425 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2426 } 2427 2428 /* Flush the FDB table */ 2429 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2430 if (ret < 0) 2431 return ret; 2432 2433 return 0; 2434 } 2435 2436 static int 2437 mt7531_setup(struct dsa_switch *ds) 2438 { 2439 struct mt7530_priv *priv = ds->priv; 2440 struct mt7530_dummy_poll p; 2441 u32 val, id; 2442 int ret, i; 2443 2444 /* Reset whole chip through gpio pin or memory-mapped registers for 2445 * different type of hardware 2446 */ 2447 if (priv->mcm) { 2448 reset_control_assert(priv->rstc); 2449 usleep_range(1000, 1100); 2450 reset_control_deassert(priv->rstc); 2451 } else { 2452 gpiod_set_value_cansleep(priv->reset, 0); 2453 usleep_range(1000, 1100); 2454 gpiod_set_value_cansleep(priv->reset, 1); 2455 } 2456 2457 /* Waiting for MT7530 got to stable */ 2458 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2459 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2460 20, 1000000); 2461 if (ret < 0) { 2462 dev_err(priv->dev, "reset timeout\n"); 2463 return ret; 2464 } 2465 2466 id = mt7530_read(priv, MT7531_CREV); 2467 id >>= CHIP_NAME_SHIFT; 2468 2469 if (id != MT7531_ID) { 2470 dev_err(priv->dev, "chip %x can't be supported\n", id); 2471 return -ENODEV; 2472 } 2473 2474 /* all MACs must be forced link-down before sw reset */ 2475 for (i = 0; i < MT7530_NUM_PORTS; i++) 2476 mt7530_write(priv, MT7530_PMCR_P(i), MT7531_FORCE_LNK); 2477 2478 /* Reset the switch through internal reset */ 2479 mt7530_write(priv, MT7530_SYS_CTRL, 2480 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2481 SYS_CTRL_REG_RST); 2482 2483 mt7531_pll_setup(priv); 2484 2485 if (mt7531_dual_sgmii_supported(priv)) { 2486 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2487 2488 /* Let ds->slave_mii_bus be able to access external phy. */ 2489 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2490 MT7531_EXT_P_MDC_11); 2491 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2492 MT7531_EXT_P_MDIO_12); 2493 } else { 2494 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2495 } 2496 dev_dbg(ds->dev, "P5 support %s interface\n", 2497 p5_intf_modes(priv->p5_intf_sel)); 2498 2499 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2500 MT7531_GPIO0_INTERRUPT); 2501 2502 /* Let phylink decide the interface later. */ 2503 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2504 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2505 2506 /* Enable PHY core PLL, since phy_device has not yet been created 2507 * provided for phy_[read,write]_mmd_indirect is called, we provide 2508 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2509 * function. 2510 */ 2511 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2512 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2513 val |= MT7531_PHY_PLL_BYPASS_MODE; 2514 val &= ~MT7531_PHY_PLL_OFF; 2515 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2516 CORE_PLL_GROUP4, val); 2517 2518 mt7531_setup_common(ds); 2519 2520 /* Setup VLAN ID 0 for VLAN-unaware bridges */ 2521 ret = mt7530_setup_vlan0(priv); 2522 if (ret) 2523 return ret; 2524 2525 ds->assisted_learning_on_cpu_port = true; 2526 ds->mtu_enforcement_ingress = true; 2527 2528 return 0; 2529 } 2530 2531 static void mt7530_mac_port_get_caps(struct dsa_switch *ds, int port, 2532 struct phylink_config *config) 2533 { 2534 switch (port) { 2535 case 0 ... 4: /* Internal phy */ 2536 __set_bit(PHY_INTERFACE_MODE_GMII, 2537 config->supported_interfaces); 2538 break; 2539 2540 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2541 phy_interface_set_rgmii(config->supported_interfaces); 2542 __set_bit(PHY_INTERFACE_MODE_MII, 2543 config->supported_interfaces); 2544 __set_bit(PHY_INTERFACE_MODE_GMII, 2545 config->supported_interfaces); 2546 break; 2547 2548 case 6: /* 1st cpu port */ 2549 __set_bit(PHY_INTERFACE_MODE_RGMII, 2550 config->supported_interfaces); 2551 __set_bit(PHY_INTERFACE_MODE_TRGMII, 2552 config->supported_interfaces); 2553 break; 2554 } 2555 } 2556 2557 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2558 { 2559 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2560 } 2561 2562 static void mt7531_mac_port_get_caps(struct dsa_switch *ds, int port, 2563 struct phylink_config *config) 2564 { 2565 struct mt7530_priv *priv = ds->priv; 2566 2567 switch (port) { 2568 case 0 ... 4: /* Internal phy */ 2569 __set_bit(PHY_INTERFACE_MODE_GMII, 2570 config->supported_interfaces); 2571 break; 2572 2573 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2574 if (mt7531_is_rgmii_port(priv, port)) { 2575 phy_interface_set_rgmii(config->supported_interfaces); 2576 break; 2577 } 2578 fallthrough; 2579 2580 case 6: /* 1st cpu port supports sgmii/8023z only */ 2581 __set_bit(PHY_INTERFACE_MODE_SGMII, 2582 config->supported_interfaces); 2583 __set_bit(PHY_INTERFACE_MODE_1000BASEX, 2584 config->supported_interfaces); 2585 __set_bit(PHY_INTERFACE_MODE_2500BASEX, 2586 config->supported_interfaces); 2587 2588 config->mac_capabilities |= MAC_2500FD; 2589 break; 2590 } 2591 } 2592 2593 static void mt7988_mac_port_get_caps(struct dsa_switch *ds, int port, 2594 struct phylink_config *config) 2595 { 2596 phy_interface_zero(config->supported_interfaces); 2597 2598 switch (port) { 2599 case 0 ... 4: /* Internal phy */ 2600 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2601 config->supported_interfaces); 2602 break; 2603 2604 case 6: 2605 __set_bit(PHY_INTERFACE_MODE_INTERNAL, 2606 config->supported_interfaces); 2607 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2608 MAC_10000FD; 2609 } 2610 } 2611 2612 static int 2613 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2614 { 2615 struct mt7530_priv *priv = ds->priv; 2616 2617 return priv->info->pad_setup(ds, state->interface); 2618 } 2619 2620 static int 2621 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2622 phy_interface_t interface) 2623 { 2624 struct mt7530_priv *priv = ds->priv; 2625 2626 /* Only need to setup port5. */ 2627 if (port != 5) 2628 return 0; 2629 2630 mt7530_setup_port5(priv->ds, interface); 2631 2632 return 0; 2633 } 2634 2635 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2636 phy_interface_t interface, 2637 struct phy_device *phydev) 2638 { 2639 u32 val; 2640 2641 if (!mt7531_is_rgmii_port(priv, port)) { 2642 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2643 port); 2644 return -EINVAL; 2645 } 2646 2647 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2648 val |= GP_CLK_EN; 2649 val &= ~GP_MODE_MASK; 2650 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2651 val &= ~CLK_SKEW_IN_MASK; 2652 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2653 val &= ~CLK_SKEW_OUT_MASK; 2654 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2655 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2656 2657 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2658 if (!phydev || phy_driver_is_genphy(phydev)) { 2659 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2660 switch (interface) { 2661 case PHY_INTERFACE_MODE_RGMII: 2662 val |= TXCLK_NO_REVERSE; 2663 val |= RXCLK_NO_DELAY; 2664 break; 2665 case PHY_INTERFACE_MODE_RGMII_RXID: 2666 val |= TXCLK_NO_REVERSE; 2667 break; 2668 case PHY_INTERFACE_MODE_RGMII_TXID: 2669 val |= RXCLK_NO_DELAY; 2670 break; 2671 case PHY_INTERFACE_MODE_RGMII_ID: 2672 break; 2673 default: 2674 return -EINVAL; 2675 } 2676 } 2677 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2678 2679 return 0; 2680 } 2681 2682 static bool mt753x_is_mac_port(u32 port) 2683 { 2684 return (port == 5 || port == 6); 2685 } 2686 2687 static int 2688 mt7988_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2689 phy_interface_t interface) 2690 { 2691 if (dsa_is_cpu_port(ds, port) && 2692 interface == PHY_INTERFACE_MODE_INTERNAL) 2693 return 0; 2694 2695 return -EINVAL; 2696 } 2697 2698 static int 2699 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2700 phy_interface_t interface) 2701 { 2702 struct mt7530_priv *priv = ds->priv; 2703 struct phy_device *phydev; 2704 struct dsa_port *dp; 2705 2706 if (!mt753x_is_mac_port(port)) { 2707 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2708 return -EINVAL; 2709 } 2710 2711 switch (interface) { 2712 case PHY_INTERFACE_MODE_RGMII: 2713 case PHY_INTERFACE_MODE_RGMII_ID: 2714 case PHY_INTERFACE_MODE_RGMII_RXID: 2715 case PHY_INTERFACE_MODE_RGMII_TXID: 2716 dp = dsa_to_port(ds, port); 2717 phydev = dp->slave->phydev; 2718 return mt7531_rgmii_setup(priv, port, interface, phydev); 2719 case PHY_INTERFACE_MODE_SGMII: 2720 case PHY_INTERFACE_MODE_NA: 2721 case PHY_INTERFACE_MODE_1000BASEX: 2722 case PHY_INTERFACE_MODE_2500BASEX: 2723 /* handled in SGMII PCS driver */ 2724 return 0; 2725 default: 2726 return -EINVAL; 2727 } 2728 2729 return -EINVAL; 2730 } 2731 2732 static int 2733 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2734 const struct phylink_link_state *state) 2735 { 2736 struct mt7530_priv *priv = ds->priv; 2737 2738 return priv->info->mac_port_config(ds, port, mode, state->interface); 2739 } 2740 2741 static struct phylink_pcs * 2742 mt753x_phylink_mac_select_pcs(struct dsa_switch *ds, int port, 2743 phy_interface_t interface) 2744 { 2745 struct mt7530_priv *priv = ds->priv; 2746 2747 switch (interface) { 2748 case PHY_INTERFACE_MODE_TRGMII: 2749 return &priv->pcs[port].pcs; 2750 case PHY_INTERFACE_MODE_SGMII: 2751 case PHY_INTERFACE_MODE_1000BASEX: 2752 case PHY_INTERFACE_MODE_2500BASEX: 2753 return priv->ports[port].sgmii_pcs; 2754 default: 2755 return NULL; 2756 } 2757 } 2758 2759 static void 2760 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2761 const struct phylink_link_state *state) 2762 { 2763 struct mt7530_priv *priv = ds->priv; 2764 u32 mcr_cur, mcr_new; 2765 2766 switch (port) { 2767 case 0 ... 4: /* Internal phy */ 2768 if (state->interface != PHY_INTERFACE_MODE_GMII && 2769 state->interface != PHY_INTERFACE_MODE_INTERNAL) 2770 goto unsupported; 2771 break; 2772 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2773 if (priv->p5_interface == state->interface) 2774 break; 2775 2776 if (mt753x_mac_config(ds, port, mode, state) < 0) 2777 goto unsupported; 2778 2779 if (priv->p5_intf_sel != P5_DISABLED) 2780 priv->p5_interface = state->interface; 2781 break; 2782 case 6: /* 1st cpu port */ 2783 if (priv->p6_interface == state->interface) 2784 break; 2785 2786 mt753x_pad_setup(ds, state); 2787 2788 if (mt753x_mac_config(ds, port, mode, state) < 0) 2789 goto unsupported; 2790 2791 priv->p6_interface = state->interface; 2792 break; 2793 default: 2794 unsupported: 2795 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2796 __func__, phy_modes(state->interface), port); 2797 return; 2798 } 2799 2800 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2801 mcr_new = mcr_cur; 2802 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2803 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2804 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2805 2806 /* Are we connected to external phy */ 2807 if (port == 5 && dsa_is_user_port(ds, 5)) 2808 mcr_new |= PMCR_EXT_PHY; 2809 2810 if (mcr_new != mcr_cur) 2811 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2812 } 2813 2814 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2815 unsigned int mode, 2816 phy_interface_t interface) 2817 { 2818 struct mt7530_priv *priv = ds->priv; 2819 2820 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2821 } 2822 2823 static void mt753x_phylink_pcs_link_up(struct phylink_pcs *pcs, 2824 unsigned int mode, 2825 phy_interface_t interface, 2826 int speed, int duplex) 2827 { 2828 if (pcs->ops->pcs_link_up) 2829 pcs->ops->pcs_link_up(pcs, mode, interface, speed, duplex); 2830 } 2831 2832 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2833 unsigned int mode, 2834 phy_interface_t interface, 2835 struct phy_device *phydev, 2836 int speed, int duplex, 2837 bool tx_pause, bool rx_pause) 2838 { 2839 struct mt7530_priv *priv = ds->priv; 2840 u32 mcr; 2841 2842 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2843 2844 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2845 * variants. 2846 */ 2847 if (interface == PHY_INTERFACE_MODE_INTERNAL || 2848 interface == PHY_INTERFACE_MODE_TRGMII || 2849 (phy_interface_mode_is_8023z(interface))) { 2850 speed = SPEED_1000; 2851 duplex = DUPLEX_FULL; 2852 } 2853 2854 switch (speed) { 2855 case SPEED_1000: 2856 mcr |= PMCR_FORCE_SPEED_1000; 2857 break; 2858 case SPEED_100: 2859 mcr |= PMCR_FORCE_SPEED_100; 2860 break; 2861 } 2862 if (duplex == DUPLEX_FULL) { 2863 mcr |= PMCR_FORCE_FDX; 2864 if (tx_pause) 2865 mcr |= PMCR_TX_FC_EN; 2866 if (rx_pause) 2867 mcr |= PMCR_RX_FC_EN; 2868 } 2869 2870 if (mode == MLO_AN_PHY && phydev && phy_init_eee(phydev, false) >= 0) { 2871 switch (speed) { 2872 case SPEED_1000: 2873 mcr |= PMCR_FORCE_EEE1G; 2874 break; 2875 case SPEED_100: 2876 mcr |= PMCR_FORCE_EEE100; 2877 break; 2878 } 2879 } 2880 2881 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2882 } 2883 2884 static int 2885 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2886 { 2887 struct mt7530_priv *priv = ds->priv; 2888 phy_interface_t interface; 2889 int speed; 2890 int ret; 2891 2892 switch (port) { 2893 case 5: 2894 if (mt7531_is_rgmii_port(priv, port)) 2895 interface = PHY_INTERFACE_MODE_RGMII; 2896 else 2897 interface = PHY_INTERFACE_MODE_2500BASEX; 2898 2899 priv->p5_interface = interface; 2900 break; 2901 case 6: 2902 interface = PHY_INTERFACE_MODE_2500BASEX; 2903 2904 priv->p6_interface = interface; 2905 break; 2906 default: 2907 return -EINVAL; 2908 } 2909 2910 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2911 speed = SPEED_2500; 2912 else 2913 speed = SPEED_1000; 2914 2915 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2916 if (ret) 2917 return ret; 2918 mt7530_write(priv, MT7530_PMCR_P(port), 2919 PMCR_CPU_PORT_SETTING(priv->id)); 2920 mt753x_phylink_pcs_link_up(&priv->pcs[port].pcs, MLO_AN_FIXED, 2921 interface, speed, DUPLEX_FULL); 2922 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2923 speed, DUPLEX_FULL, true, true); 2924 2925 return 0; 2926 } 2927 2928 static int 2929 mt7988_cpu_port_config(struct dsa_switch *ds, int port) 2930 { 2931 struct mt7530_priv *priv = ds->priv; 2932 2933 mt7530_write(priv, MT7530_PMCR_P(port), 2934 PMCR_CPU_PORT_SETTING(priv->id)); 2935 2936 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, 2937 PHY_INTERFACE_MODE_INTERNAL, NULL, 2938 SPEED_10000, DUPLEX_FULL, true, true); 2939 2940 return 0; 2941 } 2942 2943 static void mt753x_phylink_get_caps(struct dsa_switch *ds, int port, 2944 struct phylink_config *config) 2945 { 2946 struct mt7530_priv *priv = ds->priv; 2947 2948 /* This switch only supports full-duplex at 1Gbps */ 2949 config->mac_capabilities = MAC_ASYM_PAUSE | MAC_SYM_PAUSE | 2950 MAC_10 | MAC_100 | MAC_1000FD; 2951 2952 /* This driver does not make use of the speed, duplex, pause or the 2953 * advertisement in its mac_config, so it is safe to mark this driver 2954 * as non-legacy. 2955 */ 2956 config->legacy_pre_march2020 = false; 2957 2958 priv->info->mac_port_get_caps(ds, port, config); 2959 } 2960 2961 static int mt753x_pcs_validate(struct phylink_pcs *pcs, 2962 unsigned long *supported, 2963 const struct phylink_link_state *state) 2964 { 2965 /* Autonegotiation is not supported in TRGMII nor 802.3z modes */ 2966 if (state->interface == PHY_INTERFACE_MODE_TRGMII || 2967 phy_interface_mode_is_8023z(state->interface)) 2968 phylink_clear(supported, Autoneg); 2969 2970 return 0; 2971 } 2972 2973 static void mt7530_pcs_get_state(struct phylink_pcs *pcs, 2974 struct phylink_link_state *state) 2975 { 2976 struct mt7530_priv *priv = pcs_to_mt753x_pcs(pcs)->priv; 2977 int port = pcs_to_mt753x_pcs(pcs)->port; 2978 u32 pmsr; 2979 2980 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2981 2982 state->link = (pmsr & PMSR_LINK); 2983 state->an_complete = state->link; 2984 state->duplex = !!(pmsr & PMSR_DPX); 2985 2986 switch (pmsr & PMSR_SPEED_MASK) { 2987 case PMSR_SPEED_10: 2988 state->speed = SPEED_10; 2989 break; 2990 case PMSR_SPEED_100: 2991 state->speed = SPEED_100; 2992 break; 2993 case PMSR_SPEED_1000: 2994 state->speed = SPEED_1000; 2995 break; 2996 default: 2997 state->speed = SPEED_UNKNOWN; 2998 break; 2999 } 3000 3001 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 3002 if (pmsr & PMSR_RX_FC) 3003 state->pause |= MLO_PAUSE_RX; 3004 if (pmsr & PMSR_TX_FC) 3005 state->pause |= MLO_PAUSE_TX; 3006 } 3007 3008 static int mt753x_pcs_config(struct phylink_pcs *pcs, unsigned int mode, 3009 phy_interface_t interface, 3010 const unsigned long *advertising, 3011 bool permit_pause_to_mac) 3012 { 3013 return 0; 3014 } 3015 3016 static void mt7530_pcs_an_restart(struct phylink_pcs *pcs) 3017 { 3018 } 3019 3020 static const struct phylink_pcs_ops mt7530_pcs_ops = { 3021 .pcs_validate = mt753x_pcs_validate, 3022 .pcs_get_state = mt7530_pcs_get_state, 3023 .pcs_config = mt753x_pcs_config, 3024 .pcs_an_restart = mt7530_pcs_an_restart, 3025 }; 3026 3027 static int 3028 mt753x_setup(struct dsa_switch *ds) 3029 { 3030 struct mt7530_priv *priv = ds->priv; 3031 int i, ret; 3032 3033 /* Initialise the PCS devices */ 3034 for (i = 0; i < priv->ds->num_ports; i++) { 3035 priv->pcs[i].pcs.ops = priv->info->pcs_ops; 3036 priv->pcs[i].priv = priv; 3037 priv->pcs[i].port = i; 3038 } 3039 3040 ret = priv->info->sw_setup(ds); 3041 if (ret) 3042 return ret; 3043 3044 ret = mt7530_setup_irq(priv); 3045 if (ret) 3046 return ret; 3047 3048 ret = mt7530_setup_mdio(priv); 3049 if (ret && priv->irq) 3050 mt7530_free_irq_common(priv); 3051 3052 if (priv->create_sgmii) { 3053 ret = priv->create_sgmii(priv, mt7531_dual_sgmii_supported(priv)); 3054 if (ret && priv->irq) 3055 mt7530_free_irq(priv); 3056 } 3057 3058 return ret; 3059 } 3060 3061 static int mt753x_get_mac_eee(struct dsa_switch *ds, int port, 3062 struct ethtool_eee *e) 3063 { 3064 struct mt7530_priv *priv = ds->priv; 3065 u32 eeecr = mt7530_read(priv, MT7530_PMEEECR_P(port)); 3066 3067 e->tx_lpi_enabled = !(eeecr & LPI_MODE_EN); 3068 e->tx_lpi_timer = GET_LPI_THRESH(eeecr); 3069 3070 return 0; 3071 } 3072 3073 static int mt753x_set_mac_eee(struct dsa_switch *ds, int port, 3074 struct ethtool_eee *e) 3075 { 3076 struct mt7530_priv *priv = ds->priv; 3077 u32 set, mask = LPI_THRESH_MASK | LPI_MODE_EN; 3078 3079 if (e->tx_lpi_timer > 0xFFF) 3080 return -EINVAL; 3081 3082 set = SET_LPI_THRESH(e->tx_lpi_timer); 3083 if (!e->tx_lpi_enabled) 3084 /* Force LPI Mode without a delay */ 3085 set |= LPI_MODE_EN; 3086 mt7530_rmw(priv, MT7530_PMEEECR_P(port), mask, set); 3087 3088 return 0; 3089 } 3090 3091 static int mt7988_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 3092 { 3093 return 0; 3094 } 3095 3096 static int mt7988_setup(struct dsa_switch *ds) 3097 { 3098 struct mt7530_priv *priv = ds->priv; 3099 3100 /* Reset the switch */ 3101 reset_control_assert(priv->rstc); 3102 usleep_range(20, 50); 3103 reset_control_deassert(priv->rstc); 3104 usleep_range(20, 50); 3105 3106 /* Reset the switch PHYs */ 3107 mt7530_write(priv, MT7530_SYS_CTRL, SYS_CTRL_PHY_RST); 3108 3109 return mt7531_setup_common(ds); 3110 } 3111 3112 const struct dsa_switch_ops mt7530_switch_ops = { 3113 .get_tag_protocol = mtk_get_tag_protocol, 3114 .setup = mt753x_setup, 3115 .preferred_default_local_cpu_port = mt753x_preferred_default_local_cpu_port, 3116 .get_strings = mt7530_get_strings, 3117 .get_ethtool_stats = mt7530_get_ethtool_stats, 3118 .get_sset_count = mt7530_get_sset_count, 3119 .set_ageing_time = mt7530_set_ageing_time, 3120 .port_enable = mt7530_port_enable, 3121 .port_disable = mt7530_port_disable, 3122 .port_change_mtu = mt7530_port_change_mtu, 3123 .port_max_mtu = mt7530_port_max_mtu, 3124 .port_stp_state_set = mt7530_stp_state_set, 3125 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 3126 .port_bridge_flags = mt7530_port_bridge_flags, 3127 .port_bridge_join = mt7530_port_bridge_join, 3128 .port_bridge_leave = mt7530_port_bridge_leave, 3129 .port_fdb_add = mt7530_port_fdb_add, 3130 .port_fdb_del = mt7530_port_fdb_del, 3131 .port_fdb_dump = mt7530_port_fdb_dump, 3132 .port_mdb_add = mt7530_port_mdb_add, 3133 .port_mdb_del = mt7530_port_mdb_del, 3134 .port_vlan_filtering = mt7530_port_vlan_filtering, 3135 .port_vlan_add = mt7530_port_vlan_add, 3136 .port_vlan_del = mt7530_port_vlan_del, 3137 .port_mirror_add = mt753x_port_mirror_add, 3138 .port_mirror_del = mt753x_port_mirror_del, 3139 .phylink_get_caps = mt753x_phylink_get_caps, 3140 .phylink_mac_select_pcs = mt753x_phylink_mac_select_pcs, 3141 .phylink_mac_config = mt753x_phylink_mac_config, 3142 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 3143 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 3144 .get_mac_eee = mt753x_get_mac_eee, 3145 .set_mac_eee = mt753x_set_mac_eee, 3146 }; 3147 EXPORT_SYMBOL_GPL(mt7530_switch_ops); 3148 3149 const struct mt753x_info mt753x_table[] = { 3150 [ID_MT7621] = { 3151 .id = ID_MT7621, 3152 .pcs_ops = &mt7530_pcs_ops, 3153 .sw_setup = mt7530_setup, 3154 .phy_read_c22 = mt7530_phy_read_c22, 3155 .phy_write_c22 = mt7530_phy_write_c22, 3156 .phy_read_c45 = mt7530_phy_read_c45, 3157 .phy_write_c45 = mt7530_phy_write_c45, 3158 .pad_setup = mt7530_pad_clk_setup, 3159 .mac_port_get_caps = mt7530_mac_port_get_caps, 3160 .mac_port_config = mt7530_mac_config, 3161 }, 3162 [ID_MT7530] = { 3163 .id = ID_MT7530, 3164 .pcs_ops = &mt7530_pcs_ops, 3165 .sw_setup = mt7530_setup, 3166 .phy_read_c22 = mt7530_phy_read_c22, 3167 .phy_write_c22 = mt7530_phy_write_c22, 3168 .phy_read_c45 = mt7530_phy_read_c45, 3169 .phy_write_c45 = mt7530_phy_write_c45, 3170 .pad_setup = mt7530_pad_clk_setup, 3171 .mac_port_get_caps = mt7530_mac_port_get_caps, 3172 .mac_port_config = mt7530_mac_config, 3173 }, 3174 [ID_MT7531] = { 3175 .id = ID_MT7531, 3176 .pcs_ops = &mt7530_pcs_ops, 3177 .sw_setup = mt7531_setup, 3178 .phy_read_c22 = mt7531_ind_c22_phy_read, 3179 .phy_write_c22 = mt7531_ind_c22_phy_write, 3180 .phy_read_c45 = mt7531_ind_c45_phy_read, 3181 .phy_write_c45 = mt7531_ind_c45_phy_write, 3182 .pad_setup = mt7531_pad_setup, 3183 .cpu_port_config = mt7531_cpu_port_config, 3184 .mac_port_get_caps = mt7531_mac_port_get_caps, 3185 .mac_port_config = mt7531_mac_config, 3186 }, 3187 [ID_MT7988] = { 3188 .id = ID_MT7988, 3189 .pcs_ops = &mt7530_pcs_ops, 3190 .sw_setup = mt7988_setup, 3191 .phy_read_c22 = mt7531_ind_c22_phy_read, 3192 .phy_write_c22 = mt7531_ind_c22_phy_write, 3193 .phy_read_c45 = mt7531_ind_c45_phy_read, 3194 .phy_write_c45 = mt7531_ind_c45_phy_write, 3195 .pad_setup = mt7988_pad_setup, 3196 .cpu_port_config = mt7988_cpu_port_config, 3197 .mac_port_get_caps = mt7988_mac_port_get_caps, 3198 .mac_port_config = mt7988_mac_config, 3199 }, 3200 }; 3201 EXPORT_SYMBOL_GPL(mt753x_table); 3202 3203 int 3204 mt7530_probe_common(struct mt7530_priv *priv) 3205 { 3206 struct device *dev = priv->dev; 3207 3208 priv->ds = devm_kzalloc(dev, sizeof(*priv->ds), GFP_KERNEL); 3209 if (!priv->ds) 3210 return -ENOMEM; 3211 3212 priv->ds->dev = dev; 3213 priv->ds->num_ports = MT7530_NUM_PORTS; 3214 3215 /* Get the hardware identifier from the devicetree node. 3216 * We will need it for some of the clock and regulator setup. 3217 */ 3218 priv->info = of_device_get_match_data(dev); 3219 if (!priv->info) 3220 return -EINVAL; 3221 3222 /* Sanity check if these required device operations are filled 3223 * properly. 3224 */ 3225 if (!priv->info->sw_setup || !priv->info->pad_setup || 3226 !priv->info->phy_read_c22 || !priv->info->phy_write_c22 || 3227 !priv->info->mac_port_get_caps || 3228 !priv->info->mac_port_config) 3229 return -EINVAL; 3230 3231 priv->id = priv->info->id; 3232 priv->dev = dev; 3233 priv->ds->priv = priv; 3234 priv->ds->ops = &mt7530_switch_ops; 3235 mutex_init(&priv->reg_mutex); 3236 dev_set_drvdata(dev, priv); 3237 3238 return 0; 3239 } 3240 EXPORT_SYMBOL_GPL(mt7530_probe_common); 3241 3242 void 3243 mt7530_remove_common(struct mt7530_priv *priv) 3244 { 3245 if (priv->irq) 3246 mt7530_free_irq(priv); 3247 3248 dsa_unregister_switch(priv->ds); 3249 3250 mutex_destroy(&priv->reg_mutex); 3251 } 3252 EXPORT_SYMBOL_GPL(mt7530_remove_common); 3253 3254 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3255 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3256 MODULE_LICENSE("GPL"); 3257