1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Mediatek MT7530 DSA Switch driver 4 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 5 */ 6 #include <linux/etherdevice.h> 7 #include <linux/if_bridge.h> 8 #include <linux/iopoll.h> 9 #include <linux/mdio.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/module.h> 12 #include <linux/netdevice.h> 13 #include <linux/of_mdio.h> 14 #include <linux/of_net.h> 15 #include <linux/of_platform.h> 16 #include <linux/phylink.h> 17 #include <linux/regmap.h> 18 #include <linux/regulator/consumer.h> 19 #include <linux/reset.h> 20 #include <linux/gpio/consumer.h> 21 #include <linux/gpio/driver.h> 22 #include <net/dsa.h> 23 24 #include "mt7530.h" 25 26 /* String, offset, and register size in bytes if different from 4 bytes */ 27 static const struct mt7530_mib_desc mt7530_mib[] = { 28 MIB_DESC(1, 0x00, "TxDrop"), 29 MIB_DESC(1, 0x04, "TxCrcErr"), 30 MIB_DESC(1, 0x08, "TxUnicast"), 31 MIB_DESC(1, 0x0c, "TxMulticast"), 32 MIB_DESC(1, 0x10, "TxBroadcast"), 33 MIB_DESC(1, 0x14, "TxCollision"), 34 MIB_DESC(1, 0x18, "TxSingleCollision"), 35 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 36 MIB_DESC(1, 0x20, "TxDeferred"), 37 MIB_DESC(1, 0x24, "TxLateCollision"), 38 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 39 MIB_DESC(1, 0x2c, "TxPause"), 40 MIB_DESC(1, 0x30, "TxPktSz64"), 41 MIB_DESC(1, 0x34, "TxPktSz65To127"), 42 MIB_DESC(1, 0x38, "TxPktSz128To255"), 43 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 44 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 45 MIB_DESC(1, 0x44, "Tx1024ToMax"), 46 MIB_DESC(2, 0x48, "TxBytes"), 47 MIB_DESC(1, 0x60, "RxDrop"), 48 MIB_DESC(1, 0x64, "RxFiltering"), 49 MIB_DESC(1, 0x6c, "RxMulticast"), 50 MIB_DESC(1, 0x70, "RxBroadcast"), 51 MIB_DESC(1, 0x74, "RxAlignErr"), 52 MIB_DESC(1, 0x78, "RxCrcErr"), 53 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 54 MIB_DESC(1, 0x80, "RxFragErr"), 55 MIB_DESC(1, 0x84, "RxOverSzErr"), 56 MIB_DESC(1, 0x88, "RxJabberErr"), 57 MIB_DESC(1, 0x8c, "RxPause"), 58 MIB_DESC(1, 0x90, "RxPktSz64"), 59 MIB_DESC(1, 0x94, "RxPktSz65To127"), 60 MIB_DESC(1, 0x98, "RxPktSz128To255"), 61 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 62 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 63 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 64 MIB_DESC(2, 0xa8, "RxBytes"), 65 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 66 MIB_DESC(1, 0xb4, "RxIngressDrop"), 67 MIB_DESC(1, 0xb8, "RxArlDrop"), 68 }; 69 70 static int 71 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 72 { 73 struct mii_bus *bus = priv->bus; 74 int value, ret; 75 76 /* Write the desired MMD Devad */ 77 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 78 if (ret < 0) 79 goto err; 80 81 /* Write the desired MMD register address */ 82 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 83 if (ret < 0) 84 goto err; 85 86 /* Select the Function : DATA with no post increment */ 87 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 88 if (ret < 0) 89 goto err; 90 91 /* Read the content of the MMD's selected register */ 92 value = bus->read(bus, 0, MII_MMD_DATA); 93 94 return value; 95 err: 96 dev_err(&bus->dev, "failed to read mmd register\n"); 97 98 return ret; 99 } 100 101 static int 102 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 103 int devad, u32 data) 104 { 105 struct mii_bus *bus = priv->bus; 106 int ret; 107 108 /* Write the desired MMD Devad */ 109 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 110 if (ret < 0) 111 goto err; 112 113 /* Write the desired MMD register address */ 114 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 115 if (ret < 0) 116 goto err; 117 118 /* Select the Function : DATA with no post increment */ 119 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 120 if (ret < 0) 121 goto err; 122 123 /* Write the data into MMD's selected register */ 124 ret = bus->write(bus, 0, MII_MMD_DATA, data); 125 err: 126 if (ret < 0) 127 dev_err(&bus->dev, 128 "failed to write mmd register\n"); 129 return ret; 130 } 131 132 static void 133 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 134 { 135 struct mii_bus *bus = priv->bus; 136 137 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 138 139 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 140 141 mutex_unlock(&bus->mdio_lock); 142 } 143 144 static void 145 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 146 { 147 struct mii_bus *bus = priv->bus; 148 u32 val; 149 150 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 151 152 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 153 val &= ~mask; 154 val |= set; 155 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 156 157 mutex_unlock(&bus->mdio_lock); 158 } 159 160 static void 161 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 162 { 163 core_rmw(priv, reg, 0, val); 164 } 165 166 static void 167 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 168 { 169 core_rmw(priv, reg, val, 0); 170 } 171 172 static int 173 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 174 { 175 struct mii_bus *bus = priv->bus; 176 u16 page, r, lo, hi; 177 int ret; 178 179 page = (reg >> 6) & 0x3ff; 180 r = (reg >> 2) & 0xf; 181 lo = val & 0xffff; 182 hi = val >> 16; 183 184 /* MT7530 uses 31 as the pseudo port */ 185 ret = bus->write(bus, 0x1f, 0x1f, page); 186 if (ret < 0) 187 goto err; 188 189 ret = bus->write(bus, 0x1f, r, lo); 190 if (ret < 0) 191 goto err; 192 193 ret = bus->write(bus, 0x1f, 0x10, hi); 194 err: 195 if (ret < 0) 196 dev_err(&bus->dev, 197 "failed to write mt7530 register\n"); 198 return ret; 199 } 200 201 static u32 202 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 203 { 204 struct mii_bus *bus = priv->bus; 205 u16 page, r, lo, hi; 206 int ret; 207 208 page = (reg >> 6) & 0x3ff; 209 r = (reg >> 2) & 0xf; 210 211 /* MT7530 uses 31 as the pseudo port */ 212 ret = bus->write(bus, 0x1f, 0x1f, page); 213 if (ret < 0) { 214 dev_err(&bus->dev, 215 "failed to read mt7530 register\n"); 216 return ret; 217 } 218 219 lo = bus->read(bus, 0x1f, r); 220 hi = bus->read(bus, 0x1f, 0x10); 221 222 return (hi << 16) | (lo & 0xffff); 223 } 224 225 static void 226 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 227 { 228 struct mii_bus *bus = priv->bus; 229 230 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 231 232 mt7530_mii_write(priv, reg, val); 233 234 mutex_unlock(&bus->mdio_lock); 235 } 236 237 static u32 238 _mt7530_unlocked_read(struct mt7530_dummy_poll *p) 239 { 240 return mt7530_mii_read(p->priv, p->reg); 241 } 242 243 static u32 244 _mt7530_read(struct mt7530_dummy_poll *p) 245 { 246 struct mii_bus *bus = p->priv->bus; 247 u32 val; 248 249 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 250 251 val = mt7530_mii_read(p->priv, p->reg); 252 253 mutex_unlock(&bus->mdio_lock); 254 255 return val; 256 } 257 258 static u32 259 mt7530_read(struct mt7530_priv *priv, u32 reg) 260 { 261 struct mt7530_dummy_poll p; 262 263 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 264 return _mt7530_read(&p); 265 } 266 267 static void 268 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 269 u32 mask, u32 set) 270 { 271 struct mii_bus *bus = priv->bus; 272 u32 val; 273 274 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 275 276 val = mt7530_mii_read(priv, reg); 277 val &= ~mask; 278 val |= set; 279 mt7530_mii_write(priv, reg, val); 280 281 mutex_unlock(&bus->mdio_lock); 282 } 283 284 static void 285 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 286 { 287 mt7530_rmw(priv, reg, 0, val); 288 } 289 290 static void 291 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 292 { 293 mt7530_rmw(priv, reg, val, 0); 294 } 295 296 static int 297 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 298 { 299 u32 val; 300 int ret; 301 struct mt7530_dummy_poll p; 302 303 /* Set the command operating upon the MAC address entries */ 304 val = ATC_BUSY | ATC_MAT(0) | cmd; 305 mt7530_write(priv, MT7530_ATC, val); 306 307 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 308 ret = readx_poll_timeout(_mt7530_read, &p, val, 309 !(val & ATC_BUSY), 20, 20000); 310 if (ret < 0) { 311 dev_err(priv->dev, "reset timeout\n"); 312 return ret; 313 } 314 315 /* Additional sanity for read command if the specified 316 * entry is invalid 317 */ 318 val = mt7530_read(priv, MT7530_ATC); 319 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 320 return -EINVAL; 321 322 if (rsp) 323 *rsp = val; 324 325 return 0; 326 } 327 328 static void 329 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 330 { 331 u32 reg[3]; 332 int i; 333 334 /* Read from ARL table into an array */ 335 for (i = 0; i < 3; i++) { 336 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 337 338 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 339 __func__, __LINE__, i, reg[i]); 340 } 341 342 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 343 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 344 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 345 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 346 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 347 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 348 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 349 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 350 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 351 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 352 } 353 354 static void 355 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 356 u8 port_mask, const u8 *mac, 357 u8 aging, u8 type) 358 { 359 u32 reg[3] = { 0 }; 360 int i; 361 362 reg[1] |= vid & CVID_MASK; 363 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 364 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 365 /* STATIC_ENT indicate that entry is static wouldn't 366 * be aged out and STATIC_EMP specified as erasing an 367 * entry 368 */ 369 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 370 reg[1] |= mac[5] << MAC_BYTE_5; 371 reg[1] |= mac[4] << MAC_BYTE_4; 372 reg[0] |= mac[3] << MAC_BYTE_3; 373 reg[0] |= mac[2] << MAC_BYTE_2; 374 reg[0] |= mac[1] << MAC_BYTE_1; 375 reg[0] |= mac[0] << MAC_BYTE_0; 376 377 /* Write array into the ARL table */ 378 for (i = 0; i < 3; i++) 379 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 380 } 381 382 /* Setup TX circuit including relevant PAD and driving */ 383 static int 384 mt7530_pad_clk_setup(struct dsa_switch *ds, phy_interface_t interface) 385 { 386 struct mt7530_priv *priv = ds->priv; 387 u32 ncpo1, ssc_delta, trgint, i, xtal; 388 389 xtal = mt7530_read(priv, MT7530_MHWTRAP) & HWTRAP_XTAL_MASK; 390 391 if (xtal == HWTRAP_XTAL_20MHZ) { 392 dev_err(priv->dev, 393 "%s: MT7530 with a 20MHz XTAL is not supported!\n", 394 __func__); 395 return -EINVAL; 396 } 397 398 switch (interface) { 399 case PHY_INTERFACE_MODE_RGMII: 400 trgint = 0; 401 /* PLL frequency: 125MHz */ 402 ncpo1 = 0x0c80; 403 break; 404 case PHY_INTERFACE_MODE_TRGMII: 405 trgint = 1; 406 if (priv->id == ID_MT7621) { 407 /* PLL frequency: 150MHz: 1.2GBit */ 408 if (xtal == HWTRAP_XTAL_40MHZ) 409 ncpo1 = 0x0780; 410 if (xtal == HWTRAP_XTAL_25MHZ) 411 ncpo1 = 0x0a00; 412 } else { /* PLL frequency: 250MHz: 2.0Gbit */ 413 if (xtal == HWTRAP_XTAL_40MHZ) 414 ncpo1 = 0x0c80; 415 if (xtal == HWTRAP_XTAL_25MHZ) 416 ncpo1 = 0x1400; 417 } 418 break; 419 default: 420 dev_err(priv->dev, "xMII interface %d not supported\n", 421 interface); 422 return -EINVAL; 423 } 424 425 if (xtal == HWTRAP_XTAL_25MHZ) 426 ssc_delta = 0x57; 427 else 428 ssc_delta = 0x87; 429 430 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 431 P6_INTF_MODE(trgint)); 432 433 /* Lower Tx Driving for TRGMII path */ 434 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 435 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 436 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 437 438 /* Setup core clock for MT7530 */ 439 if (!trgint) { 440 /* Disable MT7530 core clock */ 441 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 442 443 /* Disable PLL, since phy_device has not yet been created 444 * provided for phy_[read,write]_mmd_indirect is called, we 445 * provide our own core_write_mmd_indirect to complete this 446 * function. 447 */ 448 core_write_mmd_indirect(priv, 449 CORE_GSWPLL_GRP1, 450 MDIO_MMD_VEND2, 451 0); 452 453 /* Set core clock into 500Mhz */ 454 core_write(priv, CORE_GSWPLL_GRP2, 455 RG_GSWPLL_POSDIV_500M(1) | 456 RG_GSWPLL_FBKDIV_500M(25)); 457 458 /* Enable PLL */ 459 core_write(priv, CORE_GSWPLL_GRP1, 460 RG_GSWPLL_EN_PRE | 461 RG_GSWPLL_POSDIV_200M(2) | 462 RG_GSWPLL_FBKDIV_200M(32)); 463 464 /* Enable MT7530 core clock */ 465 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 466 } 467 468 /* Setup the MT7530 TRGMII Tx Clock */ 469 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 470 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 471 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 472 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 473 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 474 core_write(priv, CORE_PLL_GROUP4, 475 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 476 RG_SYSPLL_BIAS_LPF_EN); 477 core_write(priv, CORE_PLL_GROUP2, 478 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 479 RG_SYSPLL_POSDIV(1)); 480 core_write(priv, CORE_PLL_GROUP7, 481 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 482 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 483 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 484 REG_GSWCK_EN | REG_TRGMIICK_EN); 485 486 if (!trgint) 487 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 488 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 489 RD_TAP_MASK, RD_TAP(16)); 490 return 0; 491 } 492 493 static bool mt7531_dual_sgmii_supported(struct mt7530_priv *priv) 494 { 495 u32 val; 496 497 val = mt7530_read(priv, MT7531_TOP_SIG_SR); 498 499 return (val & PAD_DUAL_SGMII_EN) != 0; 500 } 501 502 static int 503 mt7531_pad_setup(struct dsa_switch *ds, phy_interface_t interface) 504 { 505 struct mt7530_priv *priv = ds->priv; 506 u32 top_sig; 507 u32 hwstrap; 508 u32 xtal; 509 u32 val; 510 511 if (mt7531_dual_sgmii_supported(priv)) 512 return 0; 513 514 val = mt7530_read(priv, MT7531_CREV); 515 top_sig = mt7530_read(priv, MT7531_TOP_SIG_SR); 516 hwstrap = mt7530_read(priv, MT7531_HWTRAP); 517 if ((val & CHIP_REV_M) > 0) 518 xtal = (top_sig & PAD_MCM_SMI_EN) ? HWTRAP_XTAL_FSEL_40MHZ : 519 HWTRAP_XTAL_FSEL_25MHZ; 520 else 521 xtal = hwstrap & HWTRAP_XTAL_FSEL_MASK; 522 523 /* Step 1 : Disable MT7531 COREPLL */ 524 val = mt7530_read(priv, MT7531_PLLGP_EN); 525 val &= ~EN_COREPLL; 526 mt7530_write(priv, MT7531_PLLGP_EN, val); 527 528 /* Step 2: switch to XTAL output */ 529 val = mt7530_read(priv, MT7531_PLLGP_EN); 530 val |= SW_CLKSW; 531 mt7530_write(priv, MT7531_PLLGP_EN, val); 532 533 val = mt7530_read(priv, MT7531_PLLGP_CR0); 534 val &= ~RG_COREPLL_EN; 535 mt7530_write(priv, MT7531_PLLGP_CR0, val); 536 537 /* Step 3: disable PLLGP and enable program PLLGP */ 538 val = mt7530_read(priv, MT7531_PLLGP_EN); 539 val |= SW_PLLGP; 540 mt7530_write(priv, MT7531_PLLGP_EN, val); 541 542 /* Step 4: program COREPLL output frequency to 500MHz */ 543 val = mt7530_read(priv, MT7531_PLLGP_CR0); 544 val &= ~RG_COREPLL_POSDIV_M; 545 val |= 2 << RG_COREPLL_POSDIV_S; 546 mt7530_write(priv, MT7531_PLLGP_CR0, val); 547 usleep_range(25, 35); 548 549 switch (xtal) { 550 case HWTRAP_XTAL_FSEL_25MHZ: 551 val = mt7530_read(priv, MT7531_PLLGP_CR0); 552 val &= ~RG_COREPLL_SDM_PCW_M; 553 val |= 0x140000 << RG_COREPLL_SDM_PCW_S; 554 mt7530_write(priv, MT7531_PLLGP_CR0, val); 555 break; 556 case HWTRAP_XTAL_FSEL_40MHZ: 557 val = mt7530_read(priv, MT7531_PLLGP_CR0); 558 val &= ~RG_COREPLL_SDM_PCW_M; 559 val |= 0x190000 << RG_COREPLL_SDM_PCW_S; 560 mt7530_write(priv, MT7531_PLLGP_CR0, val); 561 break; 562 } 563 564 /* Set feedback divide ratio update signal to high */ 565 val = mt7530_read(priv, MT7531_PLLGP_CR0); 566 val |= RG_COREPLL_SDM_PCW_CHG; 567 mt7530_write(priv, MT7531_PLLGP_CR0, val); 568 /* Wait for at least 16 XTAL clocks */ 569 usleep_range(10, 20); 570 571 /* Step 5: set feedback divide ratio update signal to low */ 572 val = mt7530_read(priv, MT7531_PLLGP_CR0); 573 val &= ~RG_COREPLL_SDM_PCW_CHG; 574 mt7530_write(priv, MT7531_PLLGP_CR0, val); 575 576 /* Enable 325M clock for SGMII */ 577 mt7530_write(priv, MT7531_ANA_PLLGP_CR5, 0xad0000); 578 579 /* Enable 250SSC clock for RGMII */ 580 mt7530_write(priv, MT7531_ANA_PLLGP_CR2, 0x4f40000); 581 582 /* Step 6: Enable MT7531 PLL */ 583 val = mt7530_read(priv, MT7531_PLLGP_CR0); 584 val |= RG_COREPLL_EN; 585 mt7530_write(priv, MT7531_PLLGP_CR0, val); 586 587 val = mt7530_read(priv, MT7531_PLLGP_EN); 588 val |= EN_COREPLL; 589 mt7530_write(priv, MT7531_PLLGP_EN, val); 590 usleep_range(25, 35); 591 592 return 0; 593 } 594 595 static void 596 mt7530_mib_reset(struct dsa_switch *ds) 597 { 598 struct mt7530_priv *priv = ds->priv; 599 600 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 601 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 602 } 603 604 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 605 { 606 struct mt7530_priv *priv = ds->priv; 607 608 return mdiobus_read_nested(priv->bus, port, regnum); 609 } 610 611 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 612 u16 val) 613 { 614 struct mt7530_priv *priv = ds->priv; 615 616 return mdiobus_write_nested(priv->bus, port, regnum, val); 617 } 618 619 static int 620 mt7531_ind_c45_phy_read(struct mt7530_priv *priv, int port, int devad, 621 int regnum) 622 { 623 struct mii_bus *bus = priv->bus; 624 struct mt7530_dummy_poll p; 625 u32 reg, val; 626 int ret; 627 628 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 629 630 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 631 632 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 633 !(val & MT7531_PHY_ACS_ST), 20, 100000); 634 if (ret < 0) { 635 dev_err(priv->dev, "poll timeout\n"); 636 goto out; 637 } 638 639 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 640 MT7531_MDIO_DEV_ADDR(devad) | regnum; 641 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 642 643 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 644 !(val & MT7531_PHY_ACS_ST), 20, 100000); 645 if (ret < 0) { 646 dev_err(priv->dev, "poll timeout\n"); 647 goto out; 648 } 649 650 reg = MT7531_MDIO_CL45_READ | MT7531_MDIO_PHY_ADDR(port) | 651 MT7531_MDIO_DEV_ADDR(devad); 652 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 653 654 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 655 !(val & MT7531_PHY_ACS_ST), 20, 100000); 656 if (ret < 0) { 657 dev_err(priv->dev, "poll timeout\n"); 658 goto out; 659 } 660 661 ret = val & MT7531_MDIO_RW_DATA_MASK; 662 out: 663 mutex_unlock(&bus->mdio_lock); 664 665 return ret; 666 } 667 668 static int 669 mt7531_ind_c45_phy_write(struct mt7530_priv *priv, int port, int devad, 670 int regnum, u32 data) 671 { 672 struct mii_bus *bus = priv->bus; 673 struct mt7530_dummy_poll p; 674 u32 val, reg; 675 int ret; 676 677 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 678 679 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 680 681 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 682 !(val & MT7531_PHY_ACS_ST), 20, 100000); 683 if (ret < 0) { 684 dev_err(priv->dev, "poll timeout\n"); 685 goto out; 686 } 687 688 reg = MT7531_MDIO_CL45_ADDR | MT7531_MDIO_PHY_ADDR(port) | 689 MT7531_MDIO_DEV_ADDR(devad) | regnum; 690 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 691 692 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 693 !(val & MT7531_PHY_ACS_ST), 20, 100000); 694 if (ret < 0) { 695 dev_err(priv->dev, "poll timeout\n"); 696 goto out; 697 } 698 699 reg = MT7531_MDIO_CL45_WRITE | MT7531_MDIO_PHY_ADDR(port) | 700 MT7531_MDIO_DEV_ADDR(devad) | data; 701 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 702 703 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 704 !(val & MT7531_PHY_ACS_ST), 20, 100000); 705 if (ret < 0) { 706 dev_err(priv->dev, "poll timeout\n"); 707 goto out; 708 } 709 710 out: 711 mutex_unlock(&bus->mdio_lock); 712 713 return ret; 714 } 715 716 static int 717 mt7531_ind_c22_phy_read(struct mt7530_priv *priv, int port, int regnum) 718 { 719 struct mii_bus *bus = priv->bus; 720 struct mt7530_dummy_poll p; 721 int ret; 722 u32 val; 723 724 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 725 726 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 727 728 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 729 !(val & MT7531_PHY_ACS_ST), 20, 100000); 730 if (ret < 0) { 731 dev_err(priv->dev, "poll timeout\n"); 732 goto out; 733 } 734 735 val = MT7531_MDIO_CL22_READ | MT7531_MDIO_PHY_ADDR(port) | 736 MT7531_MDIO_REG_ADDR(regnum); 737 738 mt7530_mii_write(priv, MT7531_PHY_IAC, val | MT7531_PHY_ACS_ST); 739 740 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, val, 741 !(val & MT7531_PHY_ACS_ST), 20, 100000); 742 if (ret < 0) { 743 dev_err(priv->dev, "poll timeout\n"); 744 goto out; 745 } 746 747 ret = val & MT7531_MDIO_RW_DATA_MASK; 748 out: 749 mutex_unlock(&bus->mdio_lock); 750 751 return ret; 752 } 753 754 static int 755 mt7531_ind_c22_phy_write(struct mt7530_priv *priv, int port, int regnum, 756 u16 data) 757 { 758 struct mii_bus *bus = priv->bus; 759 struct mt7530_dummy_poll p; 760 int ret; 761 u32 reg; 762 763 INIT_MT7530_DUMMY_POLL(&p, priv, MT7531_PHY_IAC); 764 765 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 766 767 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 768 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 769 if (ret < 0) { 770 dev_err(priv->dev, "poll timeout\n"); 771 goto out; 772 } 773 774 reg = MT7531_MDIO_CL22_WRITE | MT7531_MDIO_PHY_ADDR(port) | 775 MT7531_MDIO_REG_ADDR(regnum) | data; 776 777 mt7530_mii_write(priv, MT7531_PHY_IAC, reg | MT7531_PHY_ACS_ST); 778 779 ret = readx_poll_timeout(_mt7530_unlocked_read, &p, reg, 780 !(reg & MT7531_PHY_ACS_ST), 20, 100000); 781 if (ret < 0) { 782 dev_err(priv->dev, "poll timeout\n"); 783 goto out; 784 } 785 786 out: 787 mutex_unlock(&bus->mdio_lock); 788 789 return ret; 790 } 791 792 static int 793 mt7531_ind_phy_read(struct dsa_switch *ds, int port, int regnum) 794 { 795 struct mt7530_priv *priv = ds->priv; 796 int devad; 797 int ret; 798 799 if (regnum & MII_ADDR_C45) { 800 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 801 ret = mt7531_ind_c45_phy_read(priv, port, devad, 802 regnum & MII_REGADDR_C45_MASK); 803 } else { 804 ret = mt7531_ind_c22_phy_read(priv, port, regnum); 805 } 806 807 return ret; 808 } 809 810 static int 811 mt7531_ind_phy_write(struct dsa_switch *ds, int port, int regnum, 812 u16 data) 813 { 814 struct mt7530_priv *priv = ds->priv; 815 int devad; 816 int ret; 817 818 if (regnum & MII_ADDR_C45) { 819 devad = (regnum >> MII_DEVADDR_C45_SHIFT) & 0x1f; 820 ret = mt7531_ind_c45_phy_write(priv, port, devad, 821 regnum & MII_REGADDR_C45_MASK, 822 data); 823 } else { 824 ret = mt7531_ind_c22_phy_write(priv, port, regnum, data); 825 } 826 827 return ret; 828 } 829 830 static void 831 mt7530_get_strings(struct dsa_switch *ds, int port, u32 stringset, 832 uint8_t *data) 833 { 834 int i; 835 836 if (stringset != ETH_SS_STATS) 837 return; 838 839 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 840 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 841 ETH_GSTRING_LEN); 842 } 843 844 static void 845 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 846 uint64_t *data) 847 { 848 struct mt7530_priv *priv = ds->priv; 849 const struct mt7530_mib_desc *mib; 850 u32 reg, i; 851 u64 hi; 852 853 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 854 mib = &mt7530_mib[i]; 855 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 856 857 data[i] = mt7530_read(priv, reg); 858 if (mib->size == 2) { 859 hi = mt7530_read(priv, reg + 4); 860 data[i] |= hi << 32; 861 } 862 } 863 } 864 865 static int 866 mt7530_get_sset_count(struct dsa_switch *ds, int port, int sset) 867 { 868 if (sset != ETH_SS_STATS) 869 return 0; 870 871 return ARRAY_SIZE(mt7530_mib); 872 } 873 874 static int 875 mt7530_set_ageing_time(struct dsa_switch *ds, unsigned int msecs) 876 { 877 struct mt7530_priv *priv = ds->priv; 878 unsigned int secs = msecs / 1000; 879 unsigned int tmp_age_count; 880 unsigned int error = -1; 881 unsigned int age_count; 882 unsigned int age_unit; 883 884 /* Applied timer is (AGE_CNT + 1) * (AGE_UNIT + 1) seconds */ 885 if (secs < 1 || secs > (AGE_CNT_MAX + 1) * (AGE_UNIT_MAX + 1)) 886 return -ERANGE; 887 888 /* iterate through all possible age_count to find the closest pair */ 889 for (tmp_age_count = 0; tmp_age_count <= AGE_CNT_MAX; ++tmp_age_count) { 890 unsigned int tmp_age_unit = secs / (tmp_age_count + 1) - 1; 891 892 if (tmp_age_unit <= AGE_UNIT_MAX) { 893 unsigned int tmp_error = secs - 894 (tmp_age_count + 1) * (tmp_age_unit + 1); 895 896 /* found a closer pair */ 897 if (error > tmp_error) { 898 error = tmp_error; 899 age_count = tmp_age_count; 900 age_unit = tmp_age_unit; 901 } 902 903 /* found the exact match, so break the loop */ 904 if (!error) 905 break; 906 } 907 } 908 909 mt7530_write(priv, MT7530_AAC, AGE_CNT(age_count) | AGE_UNIT(age_unit)); 910 911 return 0; 912 } 913 914 static void mt7530_setup_port5(struct dsa_switch *ds, phy_interface_t interface) 915 { 916 struct mt7530_priv *priv = ds->priv; 917 u8 tx_delay = 0; 918 int val; 919 920 mutex_lock(&priv->reg_mutex); 921 922 val = mt7530_read(priv, MT7530_MHWTRAP); 923 924 val |= MHWTRAP_MANUAL | MHWTRAP_P5_MAC_SEL | MHWTRAP_P5_DIS; 925 val &= ~MHWTRAP_P5_RGMII_MODE & ~MHWTRAP_PHY0_SEL; 926 927 switch (priv->p5_intf_sel) { 928 case P5_INTF_SEL_PHY_P0: 929 /* MT7530_P5_MODE_GPHY_P0: 2nd GMAC -> P5 -> P0 */ 930 val |= MHWTRAP_PHY0_SEL; 931 fallthrough; 932 case P5_INTF_SEL_PHY_P4: 933 /* MT7530_P5_MODE_GPHY_P4: 2nd GMAC -> P5 -> P4 */ 934 val &= ~MHWTRAP_P5_MAC_SEL & ~MHWTRAP_P5_DIS; 935 936 /* Setup the MAC by default for the cpu port */ 937 mt7530_write(priv, MT7530_PMCR_P(5), 0x56300); 938 break; 939 case P5_INTF_SEL_GMAC5: 940 /* MT7530_P5_MODE_GMAC: P5 -> External phy or 2nd GMAC */ 941 val &= ~MHWTRAP_P5_DIS; 942 break; 943 case P5_DISABLED: 944 interface = PHY_INTERFACE_MODE_NA; 945 break; 946 default: 947 dev_err(ds->dev, "Unsupported p5_intf_sel %d\n", 948 priv->p5_intf_sel); 949 goto unlock_exit; 950 } 951 952 /* Setup RGMII settings */ 953 if (phy_interface_mode_is_rgmii(interface)) { 954 val |= MHWTRAP_P5_RGMII_MODE; 955 956 /* P5 RGMII RX Clock Control: delay setting for 1000M */ 957 mt7530_write(priv, MT7530_P5RGMIIRXCR, CSR_RGMII_EDGE_ALIGN); 958 959 /* Don't set delay in DSA mode */ 960 if (!dsa_is_dsa_port(priv->ds, 5) && 961 (interface == PHY_INTERFACE_MODE_RGMII_TXID || 962 interface == PHY_INTERFACE_MODE_RGMII_ID)) 963 tx_delay = 4; /* n * 0.5 ns */ 964 965 /* P5 RGMII TX Clock Control: delay x */ 966 mt7530_write(priv, MT7530_P5RGMIITXCR, 967 CSR_RGMII_TXC_CFG(0x10 + tx_delay)); 968 969 /* reduce P5 RGMII Tx driving, 8mA */ 970 mt7530_write(priv, MT7530_IO_DRV_CR, 971 P5_IO_CLK_DRV(1) | P5_IO_DATA_DRV(1)); 972 } 973 974 mt7530_write(priv, MT7530_MHWTRAP, val); 975 976 dev_dbg(ds->dev, "Setup P5, HWTRAP=0x%x, intf_sel=%s, phy-mode=%s\n", 977 val, p5_intf_modes(priv->p5_intf_sel), phy_modes(interface)); 978 979 priv->p5_interface = interface; 980 981 unlock_exit: 982 mutex_unlock(&priv->reg_mutex); 983 } 984 985 static int 986 mt753x_cpu_port_enable(struct dsa_switch *ds, int port) 987 { 988 struct mt7530_priv *priv = ds->priv; 989 int ret; 990 991 /* Setup max capability of CPU port at first */ 992 if (priv->info->cpu_port_config) { 993 ret = priv->info->cpu_port_config(ds, port); 994 if (ret) 995 return ret; 996 } 997 998 /* Enable Mediatek header mode on the cpu port */ 999 mt7530_write(priv, MT7530_PVC_P(port), 1000 PORT_SPEC_TAG); 1001 1002 /* Disable flooding by default */ 1003 mt7530_rmw(priv, MT7530_MFC, BC_FFP_MASK | UNM_FFP_MASK | UNU_FFP_MASK, 1004 BC_FFP(BIT(port)) | UNM_FFP(BIT(port)) | UNU_FFP(BIT(port))); 1005 1006 /* Set CPU port number */ 1007 if (priv->id == ID_MT7621) 1008 mt7530_rmw(priv, MT7530_MFC, CPU_MASK, CPU_EN | CPU_PORT(port)); 1009 1010 /* CPU port gets connected to all user ports of 1011 * the switch. 1012 */ 1013 mt7530_write(priv, MT7530_PCR_P(port), 1014 PCR_MATRIX(dsa_user_ports(priv->ds))); 1015 1016 return 0; 1017 } 1018 1019 static int 1020 mt7530_port_enable(struct dsa_switch *ds, int port, 1021 struct phy_device *phy) 1022 { 1023 struct mt7530_priv *priv = ds->priv; 1024 1025 if (!dsa_is_user_port(ds, port)) 1026 return 0; 1027 1028 mutex_lock(&priv->reg_mutex); 1029 1030 /* Allow the user port gets connected to the cpu port and also 1031 * restore the port matrix if the port is the member of a certain 1032 * bridge. 1033 */ 1034 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1035 priv->ports[port].enable = true; 1036 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1037 priv->ports[port].pm); 1038 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1039 1040 mutex_unlock(&priv->reg_mutex); 1041 1042 return 0; 1043 } 1044 1045 static void 1046 mt7530_port_disable(struct dsa_switch *ds, int port) 1047 { 1048 struct mt7530_priv *priv = ds->priv; 1049 1050 if (!dsa_is_user_port(ds, port)) 1051 return; 1052 1053 mutex_lock(&priv->reg_mutex); 1054 1055 /* Clear up all port matrix which could be restored in the next 1056 * enablement for the port. 1057 */ 1058 priv->ports[port].enable = false; 1059 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1060 PCR_MATRIX_CLR); 1061 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 1062 1063 mutex_unlock(&priv->reg_mutex); 1064 } 1065 1066 static int 1067 mt7530_port_change_mtu(struct dsa_switch *ds, int port, int new_mtu) 1068 { 1069 struct mt7530_priv *priv = ds->priv; 1070 struct mii_bus *bus = priv->bus; 1071 int length; 1072 u32 val; 1073 1074 /* When a new MTU is set, DSA always set the CPU port's MTU to the 1075 * largest MTU of the slave ports. Because the switch only has a global 1076 * RX length register, only allowing CPU port here is enough. 1077 */ 1078 if (!dsa_is_cpu_port(ds, port)) 1079 return 0; 1080 1081 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 1082 1083 val = mt7530_mii_read(priv, MT7530_GMACCR); 1084 val &= ~MAX_RX_PKT_LEN_MASK; 1085 1086 /* RX length also includes Ethernet header, MTK tag, and FCS length */ 1087 length = new_mtu + ETH_HLEN + MTK_HDR_LEN + ETH_FCS_LEN; 1088 if (length <= 1522) { 1089 val |= MAX_RX_PKT_LEN_1522; 1090 } else if (length <= 1536) { 1091 val |= MAX_RX_PKT_LEN_1536; 1092 } else if (length <= 1552) { 1093 val |= MAX_RX_PKT_LEN_1552; 1094 } else { 1095 val &= ~MAX_RX_JUMBO_MASK; 1096 val |= MAX_RX_JUMBO(DIV_ROUND_UP(length, 1024)); 1097 val |= MAX_RX_PKT_LEN_JUMBO; 1098 } 1099 1100 mt7530_mii_write(priv, MT7530_GMACCR, val); 1101 1102 mutex_unlock(&bus->mdio_lock); 1103 1104 return 0; 1105 } 1106 1107 static int 1108 mt7530_port_max_mtu(struct dsa_switch *ds, int port) 1109 { 1110 return MT7530_MAX_MTU; 1111 } 1112 1113 static void 1114 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 1115 { 1116 struct mt7530_priv *priv = ds->priv; 1117 u32 stp_state; 1118 1119 switch (state) { 1120 case BR_STATE_DISABLED: 1121 stp_state = MT7530_STP_DISABLED; 1122 break; 1123 case BR_STATE_BLOCKING: 1124 stp_state = MT7530_STP_BLOCKING; 1125 break; 1126 case BR_STATE_LISTENING: 1127 stp_state = MT7530_STP_LISTENING; 1128 break; 1129 case BR_STATE_LEARNING: 1130 stp_state = MT7530_STP_LEARNING; 1131 break; 1132 case BR_STATE_FORWARDING: 1133 default: 1134 stp_state = MT7530_STP_FORWARDING; 1135 break; 1136 } 1137 1138 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 1139 } 1140 1141 static int 1142 mt7530_port_pre_bridge_flags(struct dsa_switch *ds, int port, 1143 struct switchdev_brport_flags flags, 1144 struct netlink_ext_ack *extack) 1145 { 1146 if (flags.mask & ~(BR_LEARNING | BR_FLOOD | BR_MCAST_FLOOD | 1147 BR_BCAST_FLOOD)) 1148 return -EINVAL; 1149 1150 return 0; 1151 } 1152 1153 static int 1154 mt7530_port_bridge_flags(struct dsa_switch *ds, int port, 1155 struct switchdev_brport_flags flags, 1156 struct netlink_ext_ack *extack) 1157 { 1158 struct mt7530_priv *priv = ds->priv; 1159 1160 if (flags.mask & BR_LEARNING) 1161 mt7530_rmw(priv, MT7530_PSC_P(port), SA_DIS, 1162 flags.val & BR_LEARNING ? 0 : SA_DIS); 1163 1164 if (flags.mask & BR_FLOOD) 1165 mt7530_rmw(priv, MT7530_MFC, UNU_FFP(BIT(port)), 1166 flags.val & BR_FLOOD ? UNU_FFP(BIT(port)) : 0); 1167 1168 if (flags.mask & BR_MCAST_FLOOD) 1169 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1170 flags.val & BR_MCAST_FLOOD ? UNM_FFP(BIT(port)) : 0); 1171 1172 if (flags.mask & BR_BCAST_FLOOD) 1173 mt7530_rmw(priv, MT7530_MFC, BC_FFP(BIT(port)), 1174 flags.val & BR_BCAST_FLOOD ? BC_FFP(BIT(port)) : 0); 1175 1176 return 0; 1177 } 1178 1179 static int 1180 mt7530_port_set_mrouter(struct dsa_switch *ds, int port, bool mrouter, 1181 struct netlink_ext_ack *extack) 1182 { 1183 struct mt7530_priv *priv = ds->priv; 1184 1185 mt7530_rmw(priv, MT7530_MFC, UNM_FFP(BIT(port)), 1186 mrouter ? UNM_FFP(BIT(port)) : 0); 1187 1188 return 0; 1189 } 1190 1191 static int 1192 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 1193 struct net_device *bridge) 1194 { 1195 struct mt7530_priv *priv = ds->priv; 1196 u32 port_bitmap = BIT(MT7530_CPU_PORT); 1197 int i; 1198 1199 mutex_lock(&priv->reg_mutex); 1200 1201 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1202 /* Add this port to the port matrix of the other ports in the 1203 * same bridge. If the port is disabled, port matrix is kept 1204 * and not being setup until the port becomes enabled. 1205 */ 1206 if (dsa_is_user_port(ds, i) && i != port) { 1207 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1208 continue; 1209 if (priv->ports[i].enable) 1210 mt7530_set(priv, MT7530_PCR_P(i), 1211 PCR_MATRIX(BIT(port))); 1212 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 1213 1214 port_bitmap |= BIT(i); 1215 } 1216 } 1217 1218 /* Add the all other ports to this port matrix. */ 1219 if (priv->ports[port].enable) 1220 mt7530_rmw(priv, MT7530_PCR_P(port), 1221 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 1222 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 1223 1224 mutex_unlock(&priv->reg_mutex); 1225 1226 return 0; 1227 } 1228 1229 static void 1230 mt7530_port_set_vlan_unaware(struct dsa_switch *ds, int port) 1231 { 1232 struct mt7530_priv *priv = ds->priv; 1233 bool all_user_ports_removed = true; 1234 int i; 1235 1236 /* When a port is removed from the bridge, the port would be set up 1237 * back to the default as is at initial boot which is a VLAN-unaware 1238 * port. 1239 */ 1240 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1241 MT7530_PORT_MATRIX_MODE); 1242 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1243 VLAN_ATTR(MT7530_VLAN_TRANSPARENT) | 1244 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1245 1246 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1247 if (dsa_is_user_port(ds, i) && 1248 dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1249 all_user_ports_removed = false; 1250 break; 1251 } 1252 } 1253 1254 /* CPU port also does the same thing until all user ports belonging to 1255 * the CPU port get out of VLAN filtering mode. 1256 */ 1257 if (all_user_ports_removed) { 1258 mt7530_write(priv, MT7530_PCR_P(MT7530_CPU_PORT), 1259 PCR_MATRIX(dsa_user_ports(priv->ds))); 1260 mt7530_write(priv, MT7530_PVC_P(MT7530_CPU_PORT), PORT_SPEC_TAG 1261 | PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1262 } 1263 } 1264 1265 static void 1266 mt7530_port_set_vlan_aware(struct dsa_switch *ds, int port) 1267 { 1268 struct mt7530_priv *priv = ds->priv; 1269 1270 /* The real fabric path would be decided on the membership in the 1271 * entry of VLAN table. PCR_MATRIX set up here with ALL_MEMBERS 1272 * means potential VLAN can be consisting of certain subset of all 1273 * ports. 1274 */ 1275 mt7530_rmw(priv, MT7530_PCR_P(port), 1276 PCR_MATRIX_MASK, PCR_MATRIX(MT7530_ALL_MEMBERS)); 1277 1278 /* Trapped into security mode allows packet forwarding through VLAN 1279 * table lookup. CPU port is set to fallback mode to let untagged 1280 * frames pass through. 1281 */ 1282 if (dsa_is_cpu_port(ds, port)) 1283 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1284 MT7530_PORT_FALLBACK_MODE); 1285 else 1286 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_PORT_VLAN_MASK, 1287 MT7530_PORT_SECURITY_MODE); 1288 1289 /* Set the port as a user port which is to be able to recognize VID 1290 * from incoming packets before fetching entry within the VLAN table. 1291 */ 1292 mt7530_rmw(priv, MT7530_PVC_P(port), VLAN_ATTR_MASK | PVC_EG_TAG_MASK, 1293 VLAN_ATTR(MT7530_VLAN_USER) | 1294 PVC_EG_TAG(MT7530_VLAN_EG_DISABLED)); 1295 } 1296 1297 static void 1298 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 1299 struct net_device *bridge) 1300 { 1301 struct mt7530_priv *priv = ds->priv; 1302 int i; 1303 1304 mutex_lock(&priv->reg_mutex); 1305 1306 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1307 /* Remove this port from the port matrix of the other ports 1308 * in the same bridge. If the port is disabled, port matrix 1309 * is kept and not being setup until the port becomes enabled. 1310 * And the other port's port matrix cannot be broken when the 1311 * other port is still a VLAN-aware port. 1312 */ 1313 if (dsa_is_user_port(ds, i) && i != port && 1314 !dsa_port_is_vlan_filtering(dsa_to_port(ds, i))) { 1315 if (dsa_to_port(ds, i)->bridge_dev != bridge) 1316 continue; 1317 if (priv->ports[i].enable) 1318 mt7530_clear(priv, MT7530_PCR_P(i), 1319 PCR_MATRIX(BIT(port))); 1320 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 1321 } 1322 } 1323 1324 /* Set the cpu port to be the only one in the port matrix of 1325 * this port. 1326 */ 1327 if (priv->ports[port].enable) 1328 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 1329 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 1330 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 1331 1332 mutex_unlock(&priv->reg_mutex); 1333 } 1334 1335 static int 1336 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 1337 const unsigned char *addr, u16 vid) 1338 { 1339 struct mt7530_priv *priv = ds->priv; 1340 int ret; 1341 u8 port_mask = BIT(port); 1342 1343 mutex_lock(&priv->reg_mutex); 1344 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1345 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1346 mutex_unlock(&priv->reg_mutex); 1347 1348 return ret; 1349 } 1350 1351 static int 1352 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 1353 const unsigned char *addr, u16 vid) 1354 { 1355 struct mt7530_priv *priv = ds->priv; 1356 int ret; 1357 u8 port_mask = BIT(port); 1358 1359 mutex_lock(&priv->reg_mutex); 1360 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 1361 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1362 mutex_unlock(&priv->reg_mutex); 1363 1364 return ret; 1365 } 1366 1367 static int 1368 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 1369 dsa_fdb_dump_cb_t *cb, void *data) 1370 { 1371 struct mt7530_priv *priv = ds->priv; 1372 struct mt7530_fdb _fdb = { 0 }; 1373 int cnt = MT7530_NUM_FDB_RECORDS; 1374 int ret = 0; 1375 u32 rsp = 0; 1376 1377 mutex_lock(&priv->reg_mutex); 1378 1379 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 1380 if (ret < 0) 1381 goto err; 1382 1383 do { 1384 if (rsp & ATC_SRCH_HIT) { 1385 mt7530_fdb_read(priv, &_fdb); 1386 if (_fdb.port_mask & BIT(port)) { 1387 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 1388 data); 1389 if (ret < 0) 1390 break; 1391 } 1392 } 1393 } while (--cnt && 1394 !(rsp & ATC_SRCH_END) && 1395 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 1396 err: 1397 mutex_unlock(&priv->reg_mutex); 1398 1399 return 0; 1400 } 1401 1402 static int 1403 mt7530_port_mdb_add(struct dsa_switch *ds, int port, 1404 const struct switchdev_obj_port_mdb *mdb) 1405 { 1406 struct mt7530_priv *priv = ds->priv; 1407 const u8 *addr = mdb->addr; 1408 u16 vid = mdb->vid; 1409 u8 port_mask = 0; 1410 int ret; 1411 1412 mutex_lock(&priv->reg_mutex); 1413 1414 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1415 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1416 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1417 & PORT_MAP_MASK; 1418 1419 port_mask |= BIT(port); 1420 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 1421 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1422 1423 mutex_unlock(&priv->reg_mutex); 1424 1425 return ret; 1426 } 1427 1428 static int 1429 mt7530_port_mdb_del(struct dsa_switch *ds, int port, 1430 const struct switchdev_obj_port_mdb *mdb) 1431 { 1432 struct mt7530_priv *priv = ds->priv; 1433 const u8 *addr = mdb->addr; 1434 u16 vid = mdb->vid; 1435 u8 port_mask = 0; 1436 int ret; 1437 1438 mutex_lock(&priv->reg_mutex); 1439 1440 mt7530_fdb_write(priv, vid, 0, addr, 0, STATIC_EMP); 1441 if (!mt7530_fdb_cmd(priv, MT7530_FDB_READ, NULL)) 1442 port_mask = (mt7530_read(priv, MT7530_ATRD) >> PORT_MAP) 1443 & PORT_MAP_MASK; 1444 1445 port_mask &= ~BIT(port); 1446 mt7530_fdb_write(priv, vid, port_mask, addr, -1, 1447 port_mask ? STATIC_ENT : STATIC_EMP); 1448 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, NULL); 1449 1450 mutex_unlock(&priv->reg_mutex); 1451 1452 return ret; 1453 } 1454 1455 static int 1456 mt7530_vlan_cmd(struct mt7530_priv *priv, enum mt7530_vlan_cmd cmd, u16 vid) 1457 { 1458 struct mt7530_dummy_poll p; 1459 u32 val; 1460 int ret; 1461 1462 val = VTCR_BUSY | VTCR_FUNC(cmd) | vid; 1463 mt7530_write(priv, MT7530_VTCR, val); 1464 1465 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_VTCR); 1466 ret = readx_poll_timeout(_mt7530_read, &p, val, 1467 !(val & VTCR_BUSY), 20, 20000); 1468 if (ret < 0) { 1469 dev_err(priv->dev, "poll timeout\n"); 1470 return ret; 1471 } 1472 1473 val = mt7530_read(priv, MT7530_VTCR); 1474 if (val & VTCR_INVALID) { 1475 dev_err(priv->dev, "read VTCR invalid\n"); 1476 return -EINVAL; 1477 } 1478 1479 return 0; 1480 } 1481 1482 static int 1483 mt7530_port_vlan_filtering(struct dsa_switch *ds, int port, bool vlan_filtering, 1484 struct netlink_ext_ack *extack) 1485 { 1486 if (vlan_filtering) { 1487 /* The port is being kept as VLAN-unaware port when bridge is 1488 * set up with vlan_filtering not being set, Otherwise, the 1489 * port and the corresponding CPU port is required the setup 1490 * for becoming a VLAN-aware port. 1491 */ 1492 mt7530_port_set_vlan_aware(ds, port); 1493 mt7530_port_set_vlan_aware(ds, MT7530_CPU_PORT); 1494 } else { 1495 mt7530_port_set_vlan_unaware(ds, port); 1496 } 1497 1498 return 0; 1499 } 1500 1501 static void 1502 mt7530_hw_vlan_add(struct mt7530_priv *priv, 1503 struct mt7530_hw_vlan_entry *entry) 1504 { 1505 u8 new_members; 1506 u32 val; 1507 1508 new_members = entry->old_members | BIT(entry->port) | 1509 BIT(MT7530_CPU_PORT); 1510 1511 /* Validate the entry with independent learning, create egress tag per 1512 * VLAN and joining the port as one of the port members. 1513 */ 1514 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | VLAN_VALID; 1515 mt7530_write(priv, MT7530_VAWD1, val); 1516 1517 /* Decide whether adding tag or not for those outgoing packets from the 1518 * port inside the VLAN. 1519 */ 1520 val = entry->untagged ? MT7530_VLAN_EGRESS_UNTAG : 1521 MT7530_VLAN_EGRESS_TAG; 1522 mt7530_rmw(priv, MT7530_VAWD2, 1523 ETAG_CTRL_P_MASK(entry->port), 1524 ETAG_CTRL_P(entry->port, val)); 1525 1526 /* CPU port is always taken as a tagged port for serving more than one 1527 * VLANs across and also being applied with egress type stack mode for 1528 * that VLAN tags would be appended after hardware special tag used as 1529 * DSA tag. 1530 */ 1531 mt7530_rmw(priv, MT7530_VAWD2, 1532 ETAG_CTRL_P_MASK(MT7530_CPU_PORT), 1533 ETAG_CTRL_P(MT7530_CPU_PORT, 1534 MT7530_VLAN_EGRESS_STACK)); 1535 } 1536 1537 static void 1538 mt7530_hw_vlan_del(struct mt7530_priv *priv, 1539 struct mt7530_hw_vlan_entry *entry) 1540 { 1541 u8 new_members; 1542 u32 val; 1543 1544 new_members = entry->old_members & ~BIT(entry->port); 1545 1546 val = mt7530_read(priv, MT7530_VAWD1); 1547 if (!(val & VLAN_VALID)) { 1548 dev_err(priv->dev, 1549 "Cannot be deleted due to invalid entry\n"); 1550 return; 1551 } 1552 1553 /* If certain member apart from CPU port is still alive in the VLAN, 1554 * the entry would be kept valid. Otherwise, the entry is got to be 1555 * disabled. 1556 */ 1557 if (new_members && new_members != BIT(MT7530_CPU_PORT)) { 1558 val = IVL_MAC | VTAG_EN | PORT_MEM(new_members) | 1559 VLAN_VALID; 1560 mt7530_write(priv, MT7530_VAWD1, val); 1561 } else { 1562 mt7530_write(priv, MT7530_VAWD1, 0); 1563 mt7530_write(priv, MT7530_VAWD2, 0); 1564 } 1565 } 1566 1567 static void 1568 mt7530_hw_vlan_update(struct mt7530_priv *priv, u16 vid, 1569 struct mt7530_hw_vlan_entry *entry, 1570 mt7530_vlan_op vlan_op) 1571 { 1572 u32 val; 1573 1574 /* Fetch entry */ 1575 mt7530_vlan_cmd(priv, MT7530_VTCR_RD_VID, vid); 1576 1577 val = mt7530_read(priv, MT7530_VAWD1); 1578 1579 entry->old_members = (val >> PORT_MEM_SHFT) & PORT_MEM_MASK; 1580 1581 /* Manipulate entry */ 1582 vlan_op(priv, entry); 1583 1584 /* Flush result to hardware */ 1585 mt7530_vlan_cmd(priv, MT7530_VTCR_WR_VID, vid); 1586 } 1587 1588 static int 1589 mt7530_port_vlan_add(struct dsa_switch *ds, int port, 1590 const struct switchdev_obj_port_vlan *vlan, 1591 struct netlink_ext_ack *extack) 1592 { 1593 bool untagged = vlan->flags & BRIDGE_VLAN_INFO_UNTAGGED; 1594 bool pvid = vlan->flags & BRIDGE_VLAN_INFO_PVID; 1595 struct mt7530_hw_vlan_entry new_entry; 1596 struct mt7530_priv *priv = ds->priv; 1597 1598 mutex_lock(&priv->reg_mutex); 1599 1600 mt7530_hw_vlan_entry_init(&new_entry, port, untagged); 1601 mt7530_hw_vlan_update(priv, vlan->vid, &new_entry, mt7530_hw_vlan_add); 1602 1603 if (pvid) { 1604 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, 1605 G0_PORT_VID(vlan->vid)); 1606 priv->ports[port].pvid = vlan->vid; 1607 } 1608 1609 mutex_unlock(&priv->reg_mutex); 1610 1611 return 0; 1612 } 1613 1614 static int 1615 mt7530_port_vlan_del(struct dsa_switch *ds, int port, 1616 const struct switchdev_obj_port_vlan *vlan) 1617 { 1618 struct mt7530_hw_vlan_entry target_entry; 1619 struct mt7530_priv *priv = ds->priv; 1620 u16 pvid; 1621 1622 mutex_lock(&priv->reg_mutex); 1623 1624 pvid = priv->ports[port].pvid; 1625 mt7530_hw_vlan_entry_init(&target_entry, port, 0); 1626 mt7530_hw_vlan_update(priv, vlan->vid, &target_entry, 1627 mt7530_hw_vlan_del); 1628 1629 /* PVID is being restored to the default whenever the PVID port 1630 * is being removed from the VLAN. 1631 */ 1632 if (pvid == vlan->vid) 1633 pvid = G0_PORT_VID_DEF; 1634 1635 mt7530_rmw(priv, MT7530_PPBV1_P(port), G0_PORT_VID_MASK, pvid); 1636 priv->ports[port].pvid = pvid; 1637 1638 mutex_unlock(&priv->reg_mutex); 1639 1640 return 0; 1641 } 1642 1643 static int mt753x_mirror_port_get(unsigned int id, u32 val) 1644 { 1645 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_GET(val) : 1646 MIRROR_PORT(val); 1647 } 1648 1649 static int mt753x_mirror_port_set(unsigned int id, u32 val) 1650 { 1651 return (id == ID_MT7531) ? MT7531_MIRROR_PORT_SET(val) : 1652 MIRROR_PORT(val); 1653 } 1654 1655 static int mt753x_port_mirror_add(struct dsa_switch *ds, int port, 1656 struct dsa_mall_mirror_tc_entry *mirror, 1657 bool ingress) 1658 { 1659 struct mt7530_priv *priv = ds->priv; 1660 int monitor_port; 1661 u32 val; 1662 1663 /* Check for existent entry */ 1664 if ((ingress ? priv->mirror_rx : priv->mirror_tx) & BIT(port)) 1665 return -EEXIST; 1666 1667 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1668 1669 /* MT7530 only supports one monitor port */ 1670 monitor_port = mt753x_mirror_port_get(priv->id, val); 1671 if (val & MT753X_MIRROR_EN(priv->id) && 1672 monitor_port != mirror->to_local_port) 1673 return -EEXIST; 1674 1675 val |= MT753X_MIRROR_EN(priv->id); 1676 val &= ~MT753X_MIRROR_MASK(priv->id); 1677 val |= mt753x_mirror_port_set(priv->id, mirror->to_local_port); 1678 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1679 1680 val = mt7530_read(priv, MT7530_PCR_P(port)); 1681 if (ingress) { 1682 val |= PORT_RX_MIR; 1683 priv->mirror_rx |= BIT(port); 1684 } else { 1685 val |= PORT_TX_MIR; 1686 priv->mirror_tx |= BIT(port); 1687 } 1688 mt7530_write(priv, MT7530_PCR_P(port), val); 1689 1690 return 0; 1691 } 1692 1693 static void mt753x_port_mirror_del(struct dsa_switch *ds, int port, 1694 struct dsa_mall_mirror_tc_entry *mirror) 1695 { 1696 struct mt7530_priv *priv = ds->priv; 1697 u32 val; 1698 1699 val = mt7530_read(priv, MT7530_PCR_P(port)); 1700 if (mirror->ingress) { 1701 val &= ~PORT_RX_MIR; 1702 priv->mirror_rx &= ~BIT(port); 1703 } else { 1704 val &= ~PORT_TX_MIR; 1705 priv->mirror_tx &= ~BIT(port); 1706 } 1707 mt7530_write(priv, MT7530_PCR_P(port), val); 1708 1709 if (!priv->mirror_rx && !priv->mirror_tx) { 1710 val = mt7530_read(priv, MT753X_MIRROR_REG(priv->id)); 1711 val &= ~MT753X_MIRROR_EN(priv->id); 1712 mt7530_write(priv, MT753X_MIRROR_REG(priv->id), val); 1713 } 1714 } 1715 1716 static enum dsa_tag_protocol 1717 mtk_get_tag_protocol(struct dsa_switch *ds, int port, 1718 enum dsa_tag_protocol mp) 1719 { 1720 struct mt7530_priv *priv = ds->priv; 1721 1722 if (port != MT7530_CPU_PORT) { 1723 dev_warn(priv->dev, 1724 "port not matched with tagging CPU port\n"); 1725 return DSA_TAG_PROTO_NONE; 1726 } else { 1727 return DSA_TAG_PROTO_MTK; 1728 } 1729 } 1730 1731 #ifdef CONFIG_GPIOLIB 1732 static inline u32 1733 mt7530_gpio_to_bit(unsigned int offset) 1734 { 1735 /* Map GPIO offset to register bit 1736 * [ 2: 0] port 0 LED 0..2 as GPIO 0..2 1737 * [ 6: 4] port 1 LED 0..2 as GPIO 3..5 1738 * [10: 8] port 2 LED 0..2 as GPIO 6..8 1739 * [14:12] port 3 LED 0..2 as GPIO 9..11 1740 * [18:16] port 4 LED 0..2 as GPIO 12..14 1741 */ 1742 return BIT(offset + offset / 3); 1743 } 1744 1745 static int 1746 mt7530_gpio_get(struct gpio_chip *gc, unsigned int offset) 1747 { 1748 struct mt7530_priv *priv = gpiochip_get_data(gc); 1749 u32 bit = mt7530_gpio_to_bit(offset); 1750 1751 return !!(mt7530_read(priv, MT7530_LED_GPIO_DATA) & bit); 1752 } 1753 1754 static void 1755 mt7530_gpio_set(struct gpio_chip *gc, unsigned int offset, int value) 1756 { 1757 struct mt7530_priv *priv = gpiochip_get_data(gc); 1758 u32 bit = mt7530_gpio_to_bit(offset); 1759 1760 if (value) 1761 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1762 else 1763 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1764 } 1765 1766 static int 1767 mt7530_gpio_get_direction(struct gpio_chip *gc, unsigned int offset) 1768 { 1769 struct mt7530_priv *priv = gpiochip_get_data(gc); 1770 u32 bit = mt7530_gpio_to_bit(offset); 1771 1772 return (mt7530_read(priv, MT7530_LED_GPIO_DIR) & bit) ? 1773 GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; 1774 } 1775 1776 static int 1777 mt7530_gpio_direction_input(struct gpio_chip *gc, unsigned int offset) 1778 { 1779 struct mt7530_priv *priv = gpiochip_get_data(gc); 1780 u32 bit = mt7530_gpio_to_bit(offset); 1781 1782 mt7530_clear(priv, MT7530_LED_GPIO_OE, bit); 1783 mt7530_clear(priv, MT7530_LED_GPIO_DIR, bit); 1784 1785 return 0; 1786 } 1787 1788 static int 1789 mt7530_gpio_direction_output(struct gpio_chip *gc, unsigned int offset, int value) 1790 { 1791 struct mt7530_priv *priv = gpiochip_get_data(gc); 1792 u32 bit = mt7530_gpio_to_bit(offset); 1793 1794 mt7530_set(priv, MT7530_LED_GPIO_DIR, bit); 1795 1796 if (value) 1797 mt7530_set(priv, MT7530_LED_GPIO_DATA, bit); 1798 else 1799 mt7530_clear(priv, MT7530_LED_GPIO_DATA, bit); 1800 1801 mt7530_set(priv, MT7530_LED_GPIO_OE, bit); 1802 1803 return 0; 1804 } 1805 1806 static int 1807 mt7530_setup_gpio(struct mt7530_priv *priv) 1808 { 1809 struct device *dev = priv->dev; 1810 struct gpio_chip *gc; 1811 1812 gc = devm_kzalloc(dev, sizeof(*gc), GFP_KERNEL); 1813 if (!gc) 1814 return -ENOMEM; 1815 1816 mt7530_write(priv, MT7530_LED_GPIO_OE, 0); 1817 mt7530_write(priv, MT7530_LED_GPIO_DIR, 0); 1818 mt7530_write(priv, MT7530_LED_IO_MODE, 0); 1819 1820 gc->label = "mt7530"; 1821 gc->parent = dev; 1822 gc->owner = THIS_MODULE; 1823 gc->get_direction = mt7530_gpio_get_direction; 1824 gc->direction_input = mt7530_gpio_direction_input; 1825 gc->direction_output = mt7530_gpio_direction_output; 1826 gc->get = mt7530_gpio_get; 1827 gc->set = mt7530_gpio_set; 1828 gc->base = -1; 1829 gc->ngpio = 15; 1830 gc->can_sleep = true; 1831 1832 return devm_gpiochip_add_data(dev, gc, priv); 1833 } 1834 #endif /* CONFIG_GPIOLIB */ 1835 1836 static int 1837 mt7530_setup(struct dsa_switch *ds) 1838 { 1839 struct mt7530_priv *priv = ds->priv; 1840 struct device_node *phy_node; 1841 struct device_node *mac_np; 1842 struct mt7530_dummy_poll p; 1843 phy_interface_t interface; 1844 struct device_node *dn; 1845 u32 id, val; 1846 int ret, i; 1847 1848 /* The parent node of master netdev which holds the common system 1849 * controller also is the container for two GMACs nodes representing 1850 * as two netdev instances. 1851 */ 1852 dn = dsa_to_port(ds, MT7530_CPU_PORT)->master->dev.of_node->parent; 1853 ds->mtu_enforcement_ingress = true; 1854 1855 if (priv->id == ID_MT7530) { 1856 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 1857 ret = regulator_enable(priv->core_pwr); 1858 if (ret < 0) { 1859 dev_err(priv->dev, 1860 "Failed to enable core power: %d\n", ret); 1861 return ret; 1862 } 1863 1864 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 1865 ret = regulator_enable(priv->io_pwr); 1866 if (ret < 0) { 1867 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 1868 ret); 1869 return ret; 1870 } 1871 } 1872 1873 /* Reset whole chip through gpio pin or memory-mapped registers for 1874 * different type of hardware 1875 */ 1876 if (priv->mcm) { 1877 reset_control_assert(priv->rstc); 1878 usleep_range(1000, 1100); 1879 reset_control_deassert(priv->rstc); 1880 } else { 1881 gpiod_set_value_cansleep(priv->reset, 0); 1882 usleep_range(1000, 1100); 1883 gpiod_set_value_cansleep(priv->reset, 1); 1884 } 1885 1886 /* Waiting for MT7530 got to stable */ 1887 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 1888 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 1889 20, 1000000); 1890 if (ret < 0) { 1891 dev_err(priv->dev, "reset timeout\n"); 1892 return ret; 1893 } 1894 1895 id = mt7530_read(priv, MT7530_CREV); 1896 id >>= CHIP_NAME_SHIFT; 1897 if (id != MT7530_ID) { 1898 dev_err(priv->dev, "chip %x can't be supported\n", id); 1899 return -ENODEV; 1900 } 1901 1902 /* Reset the switch through internal reset */ 1903 mt7530_write(priv, MT7530_SYS_CTRL, 1904 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 1905 SYS_CTRL_REG_RST); 1906 1907 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 1908 val = mt7530_read(priv, MT7530_MHWTRAP); 1909 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 1910 val |= MHWTRAP_MANUAL; 1911 mt7530_write(priv, MT7530_MHWTRAP, val); 1912 1913 priv->p6_interface = PHY_INTERFACE_MODE_NA; 1914 1915 /* Enable and reset MIB counters */ 1916 mt7530_mib_reset(ds); 1917 1918 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1919 /* Disable forwarding by default on all ports */ 1920 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1921 PCR_MATRIX_CLR); 1922 1923 if (dsa_is_cpu_port(ds, i)) { 1924 ret = mt753x_cpu_port_enable(ds, i); 1925 if (ret) 1926 return ret; 1927 } else { 1928 mt7530_port_disable(ds, i); 1929 1930 /* Disable learning by default on all user ports */ 1931 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 1932 } 1933 /* Enable consistent egress tag */ 1934 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 1935 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 1936 } 1937 1938 /* Setup port 5 */ 1939 priv->p5_intf_sel = P5_DISABLED; 1940 interface = PHY_INTERFACE_MODE_NA; 1941 1942 if (!dsa_is_unused_port(ds, 5)) { 1943 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 1944 ret = of_get_phy_mode(dsa_to_port(ds, 5)->dn, &interface); 1945 if (ret && ret != -ENODEV) 1946 return ret; 1947 } else { 1948 /* Scan the ethernet nodes. look for GMAC1, lookup used phy */ 1949 for_each_child_of_node(dn, mac_np) { 1950 if (!of_device_is_compatible(mac_np, 1951 "mediatek,eth-mac")) 1952 continue; 1953 1954 ret = of_property_read_u32(mac_np, "reg", &id); 1955 if (ret < 0 || id != 1) 1956 continue; 1957 1958 phy_node = of_parse_phandle(mac_np, "phy-handle", 0); 1959 if (!phy_node) 1960 continue; 1961 1962 if (phy_node->parent == priv->dev->of_node->parent) { 1963 ret = of_get_phy_mode(mac_np, &interface); 1964 if (ret && ret != -ENODEV) { 1965 of_node_put(mac_np); 1966 return ret; 1967 } 1968 id = of_mdio_parse_addr(ds->dev, phy_node); 1969 if (id == 0) 1970 priv->p5_intf_sel = P5_INTF_SEL_PHY_P0; 1971 if (id == 4) 1972 priv->p5_intf_sel = P5_INTF_SEL_PHY_P4; 1973 } 1974 of_node_put(mac_np); 1975 of_node_put(phy_node); 1976 break; 1977 } 1978 } 1979 1980 #ifdef CONFIG_GPIOLIB 1981 if (of_property_read_bool(priv->dev->of_node, "gpio-controller")) { 1982 ret = mt7530_setup_gpio(priv); 1983 if (ret) 1984 return ret; 1985 } 1986 #endif /* CONFIG_GPIOLIB */ 1987 1988 mt7530_setup_port5(ds, interface); 1989 1990 /* Flush the FDB table */ 1991 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 1992 if (ret < 0) 1993 return ret; 1994 1995 return 0; 1996 } 1997 1998 static int 1999 mt7531_setup(struct dsa_switch *ds) 2000 { 2001 struct mt7530_priv *priv = ds->priv; 2002 struct mt7530_dummy_poll p; 2003 u32 val, id; 2004 int ret, i; 2005 2006 /* Reset whole chip through gpio pin or memory-mapped registers for 2007 * different type of hardware 2008 */ 2009 if (priv->mcm) { 2010 reset_control_assert(priv->rstc); 2011 usleep_range(1000, 1100); 2012 reset_control_deassert(priv->rstc); 2013 } else { 2014 gpiod_set_value_cansleep(priv->reset, 0); 2015 usleep_range(1000, 1100); 2016 gpiod_set_value_cansleep(priv->reset, 1); 2017 } 2018 2019 /* Waiting for MT7530 got to stable */ 2020 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 2021 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 2022 20, 1000000); 2023 if (ret < 0) { 2024 dev_err(priv->dev, "reset timeout\n"); 2025 return ret; 2026 } 2027 2028 id = mt7530_read(priv, MT7531_CREV); 2029 id >>= CHIP_NAME_SHIFT; 2030 2031 if (id != MT7531_ID) { 2032 dev_err(priv->dev, "chip %x can't be supported\n", id); 2033 return -ENODEV; 2034 } 2035 2036 /* Reset the switch through internal reset */ 2037 mt7530_write(priv, MT7530_SYS_CTRL, 2038 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 2039 SYS_CTRL_REG_RST); 2040 2041 if (mt7531_dual_sgmii_supported(priv)) { 2042 priv->p5_intf_sel = P5_INTF_SEL_GMAC5_SGMII; 2043 2044 /* Let ds->slave_mii_bus be able to access external phy. */ 2045 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO11_RG_RXD2_MASK, 2046 MT7531_EXT_P_MDC_11); 2047 mt7530_rmw(priv, MT7531_GPIO_MODE1, MT7531_GPIO12_RG_RXD3_MASK, 2048 MT7531_EXT_P_MDIO_12); 2049 } else { 2050 priv->p5_intf_sel = P5_INTF_SEL_GMAC5; 2051 } 2052 dev_dbg(ds->dev, "P5 support %s interface\n", 2053 p5_intf_modes(priv->p5_intf_sel)); 2054 2055 mt7530_rmw(priv, MT7531_GPIO_MODE0, MT7531_GPIO0_MASK, 2056 MT7531_GPIO0_INTERRUPT); 2057 2058 /* Let phylink decide the interface later. */ 2059 priv->p5_interface = PHY_INTERFACE_MODE_NA; 2060 priv->p6_interface = PHY_INTERFACE_MODE_NA; 2061 2062 /* Enable PHY core PLL, since phy_device has not yet been created 2063 * provided for phy_[read,write]_mmd_indirect is called, we provide 2064 * our own mt7531_ind_mmd_phy_[read,write] to complete this 2065 * function. 2066 */ 2067 val = mt7531_ind_c45_phy_read(priv, MT753X_CTRL_PHY_ADDR, 2068 MDIO_MMD_VEND2, CORE_PLL_GROUP4); 2069 val |= MT7531_PHY_PLL_BYPASS_MODE; 2070 val &= ~MT7531_PHY_PLL_OFF; 2071 mt7531_ind_c45_phy_write(priv, MT753X_CTRL_PHY_ADDR, MDIO_MMD_VEND2, 2072 CORE_PLL_GROUP4, val); 2073 2074 /* BPDU to CPU port */ 2075 mt7530_rmw(priv, MT7531_CFC, MT7531_CPU_PMAP_MASK, 2076 BIT(MT7530_CPU_PORT)); 2077 mt7530_rmw(priv, MT753X_BPC, MT753X_BPDU_PORT_FW_MASK, 2078 MT753X_BPDU_CPU_ONLY); 2079 2080 /* Enable and reset MIB counters */ 2081 mt7530_mib_reset(ds); 2082 2083 for (i = 0; i < MT7530_NUM_PORTS; i++) { 2084 /* Disable forwarding by default on all ports */ 2085 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 2086 PCR_MATRIX_CLR); 2087 2088 mt7530_set(priv, MT7531_DBG_CNT(i), MT7531_DIS_CLR); 2089 2090 if (dsa_is_cpu_port(ds, i)) { 2091 ret = mt753x_cpu_port_enable(ds, i); 2092 if (ret) 2093 return ret; 2094 } else { 2095 mt7530_port_disable(ds, i); 2096 2097 /* Disable learning by default on all user ports */ 2098 mt7530_set(priv, MT7530_PSC_P(i), SA_DIS); 2099 } 2100 2101 /* Enable consistent egress tag */ 2102 mt7530_rmw(priv, MT7530_PVC_P(i), PVC_EG_TAG_MASK, 2103 PVC_EG_TAG(MT7530_VLAN_EG_CONSISTENT)); 2104 } 2105 2106 ds->mtu_enforcement_ingress = true; 2107 2108 /* Flush the FDB table */ 2109 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, NULL); 2110 if (ret < 0) 2111 return ret; 2112 2113 return 0; 2114 } 2115 2116 static bool 2117 mt7530_phy_mode_supported(struct dsa_switch *ds, int port, 2118 const struct phylink_link_state *state) 2119 { 2120 struct mt7530_priv *priv = ds->priv; 2121 2122 switch (port) { 2123 case 0 ... 4: /* Internal phy */ 2124 if (state->interface != PHY_INTERFACE_MODE_GMII) 2125 return false; 2126 break; 2127 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2128 if (!phy_interface_mode_is_rgmii(state->interface) && 2129 state->interface != PHY_INTERFACE_MODE_MII && 2130 state->interface != PHY_INTERFACE_MODE_GMII) 2131 return false; 2132 break; 2133 case 6: /* 1st cpu port */ 2134 if (state->interface != PHY_INTERFACE_MODE_RGMII && 2135 state->interface != PHY_INTERFACE_MODE_TRGMII) 2136 return false; 2137 break; 2138 default: 2139 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2140 port); 2141 return false; 2142 } 2143 2144 return true; 2145 } 2146 2147 static bool mt7531_is_rgmii_port(struct mt7530_priv *priv, u32 port) 2148 { 2149 return (port == 5) && (priv->p5_intf_sel != P5_INTF_SEL_GMAC5_SGMII); 2150 } 2151 2152 static bool 2153 mt7531_phy_mode_supported(struct dsa_switch *ds, int port, 2154 const struct phylink_link_state *state) 2155 { 2156 struct mt7530_priv *priv = ds->priv; 2157 2158 switch (port) { 2159 case 0 ... 4: /* Internal phy */ 2160 if (state->interface != PHY_INTERFACE_MODE_GMII) 2161 return false; 2162 break; 2163 case 5: /* 2nd cpu port supports either rgmii or sgmii/8023z */ 2164 if (mt7531_is_rgmii_port(priv, port)) 2165 return phy_interface_mode_is_rgmii(state->interface); 2166 fallthrough; 2167 case 6: /* 1st cpu port supports sgmii/8023z only */ 2168 if (state->interface != PHY_INTERFACE_MODE_SGMII && 2169 !phy_interface_mode_is_8023z(state->interface)) 2170 return false; 2171 break; 2172 default: 2173 dev_err(priv->dev, "%s: unsupported port: %i\n", __func__, 2174 port); 2175 return false; 2176 } 2177 2178 return true; 2179 } 2180 2181 static bool 2182 mt753x_phy_mode_supported(struct dsa_switch *ds, int port, 2183 const struct phylink_link_state *state) 2184 { 2185 struct mt7530_priv *priv = ds->priv; 2186 2187 return priv->info->phy_mode_supported(ds, port, state); 2188 } 2189 2190 static int 2191 mt753x_pad_setup(struct dsa_switch *ds, const struct phylink_link_state *state) 2192 { 2193 struct mt7530_priv *priv = ds->priv; 2194 2195 return priv->info->pad_setup(ds, state->interface); 2196 } 2197 2198 static int 2199 mt7530_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2200 phy_interface_t interface) 2201 { 2202 struct mt7530_priv *priv = ds->priv; 2203 2204 /* Only need to setup port5. */ 2205 if (port != 5) 2206 return 0; 2207 2208 mt7530_setup_port5(priv->ds, interface); 2209 2210 return 0; 2211 } 2212 2213 static int mt7531_rgmii_setup(struct mt7530_priv *priv, u32 port, 2214 phy_interface_t interface, 2215 struct phy_device *phydev) 2216 { 2217 u32 val; 2218 2219 if (!mt7531_is_rgmii_port(priv, port)) { 2220 dev_err(priv->dev, "RGMII mode is not available for port %d\n", 2221 port); 2222 return -EINVAL; 2223 } 2224 2225 val = mt7530_read(priv, MT7531_CLKGEN_CTRL); 2226 val |= GP_CLK_EN; 2227 val &= ~GP_MODE_MASK; 2228 val |= GP_MODE(MT7531_GP_MODE_RGMII); 2229 val &= ~CLK_SKEW_IN_MASK; 2230 val |= CLK_SKEW_IN(MT7531_CLK_SKEW_NO_CHG); 2231 val &= ~CLK_SKEW_OUT_MASK; 2232 val |= CLK_SKEW_OUT(MT7531_CLK_SKEW_NO_CHG); 2233 val |= TXCLK_NO_REVERSE | RXCLK_NO_DELAY; 2234 2235 /* Do not adjust rgmii delay when vendor phy driver presents. */ 2236 if (!phydev || phy_driver_is_genphy(phydev)) { 2237 val &= ~(TXCLK_NO_REVERSE | RXCLK_NO_DELAY); 2238 switch (interface) { 2239 case PHY_INTERFACE_MODE_RGMII: 2240 val |= TXCLK_NO_REVERSE; 2241 val |= RXCLK_NO_DELAY; 2242 break; 2243 case PHY_INTERFACE_MODE_RGMII_RXID: 2244 val |= TXCLK_NO_REVERSE; 2245 break; 2246 case PHY_INTERFACE_MODE_RGMII_TXID: 2247 val |= RXCLK_NO_DELAY; 2248 break; 2249 case PHY_INTERFACE_MODE_RGMII_ID: 2250 break; 2251 default: 2252 return -EINVAL; 2253 } 2254 } 2255 mt7530_write(priv, MT7531_CLKGEN_CTRL, val); 2256 2257 return 0; 2258 } 2259 2260 static void mt7531_sgmii_validate(struct mt7530_priv *priv, int port, 2261 unsigned long *supported) 2262 { 2263 /* Port5 supports ethier RGMII or SGMII. 2264 * Port6 supports SGMII only. 2265 */ 2266 switch (port) { 2267 case 5: 2268 if (mt7531_is_rgmii_port(priv, port)) 2269 break; 2270 fallthrough; 2271 case 6: 2272 phylink_set(supported, 1000baseX_Full); 2273 phylink_set(supported, 2500baseX_Full); 2274 phylink_set(supported, 2500baseT_Full); 2275 } 2276 } 2277 2278 static void 2279 mt7531_sgmii_link_up_force(struct dsa_switch *ds, int port, 2280 unsigned int mode, phy_interface_t interface, 2281 int speed, int duplex) 2282 { 2283 struct mt7530_priv *priv = ds->priv; 2284 unsigned int val; 2285 2286 /* For adjusting speed and duplex of SGMII force mode. */ 2287 if (interface != PHY_INTERFACE_MODE_SGMII || 2288 phylink_autoneg_inband(mode)) 2289 return; 2290 2291 /* SGMII force mode setting */ 2292 val = mt7530_read(priv, MT7531_SGMII_MODE(port)); 2293 val &= ~MT7531_SGMII_IF_MODE_MASK; 2294 2295 switch (speed) { 2296 case SPEED_10: 2297 val |= MT7531_SGMII_FORCE_SPEED_10; 2298 break; 2299 case SPEED_100: 2300 val |= MT7531_SGMII_FORCE_SPEED_100; 2301 break; 2302 case SPEED_1000: 2303 val |= MT7531_SGMII_FORCE_SPEED_1000; 2304 break; 2305 } 2306 2307 /* MT7531 SGMII 1G force mode can only work in full duplex mode, 2308 * no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2309 */ 2310 if ((speed == SPEED_10 || speed == SPEED_100) && 2311 duplex != DUPLEX_FULL) 2312 val |= MT7531_SGMII_FORCE_HALF_DUPLEX; 2313 2314 mt7530_write(priv, MT7531_SGMII_MODE(port), val); 2315 } 2316 2317 static bool mt753x_is_mac_port(u32 port) 2318 { 2319 return (port == 5 || port == 6); 2320 } 2321 2322 static int mt7531_sgmii_setup_mode_force(struct mt7530_priv *priv, u32 port, 2323 phy_interface_t interface) 2324 { 2325 u32 val; 2326 2327 if (!mt753x_is_mac_port(port)) 2328 return -EINVAL; 2329 2330 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2331 MT7531_SGMII_PHYA_PWD); 2332 2333 val = mt7530_read(priv, MT7531_PHYA_CTRL_SIGNAL3(port)); 2334 val &= ~MT7531_RG_TPHY_SPEED_MASK; 2335 /* Setup 2.5 times faster clock for 2.5Gbps data speeds with 10B/8B 2336 * encoding. 2337 */ 2338 val |= (interface == PHY_INTERFACE_MODE_2500BASEX) ? 2339 MT7531_RG_TPHY_SPEED_3_125G : MT7531_RG_TPHY_SPEED_1_25G; 2340 mt7530_write(priv, MT7531_PHYA_CTRL_SIGNAL3(port), val); 2341 2342 mt7530_clear(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2343 2344 /* MT7531 SGMII 1G and 2.5G force mode can only work in full duplex 2345 * mode, no matter MT7531_SGMII_FORCE_HALF_DUPLEX is set or not. 2346 */ 2347 mt7530_rmw(priv, MT7531_SGMII_MODE(port), 2348 MT7531_SGMII_IF_MODE_MASK | MT7531_SGMII_REMOTE_FAULT_DIS, 2349 MT7531_SGMII_FORCE_SPEED_1000); 2350 2351 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2352 2353 return 0; 2354 } 2355 2356 static int mt7531_sgmii_setup_mode_an(struct mt7530_priv *priv, int port, 2357 phy_interface_t interface) 2358 { 2359 if (!mt753x_is_mac_port(port)) 2360 return -EINVAL; 2361 2362 mt7530_set(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 2363 MT7531_SGMII_PHYA_PWD); 2364 2365 mt7530_rmw(priv, MT7531_PHYA_CTRL_SIGNAL3(port), 2366 MT7531_RG_TPHY_SPEED_MASK, MT7531_RG_TPHY_SPEED_1_25G); 2367 2368 mt7530_set(priv, MT7531_SGMII_MODE(port), 2369 MT7531_SGMII_REMOTE_FAULT_DIS | 2370 MT7531_SGMII_SPEED_DUPLEX_AN); 2371 2372 mt7530_rmw(priv, MT7531_PCS_SPEED_ABILITY(port), 2373 MT7531_SGMII_TX_CONFIG_MASK, 1); 2374 2375 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_ENABLE); 2376 2377 mt7530_set(priv, MT7531_PCS_CONTROL_1(port), MT7531_SGMII_AN_RESTART); 2378 2379 mt7530_write(priv, MT7531_QPHY_PWR_STATE_CTRL(port), 0); 2380 2381 return 0; 2382 } 2383 2384 static void mt7531_sgmii_restart_an(struct dsa_switch *ds, int port) 2385 { 2386 struct mt7530_priv *priv = ds->priv; 2387 u32 val; 2388 2389 /* Only restart AN when AN is enabled */ 2390 val = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2391 if (val & MT7531_SGMII_AN_ENABLE) { 2392 val |= MT7531_SGMII_AN_RESTART; 2393 mt7530_write(priv, MT7531_PCS_CONTROL_1(port), val); 2394 } 2395 } 2396 2397 static int 2398 mt7531_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2399 phy_interface_t interface) 2400 { 2401 struct mt7530_priv *priv = ds->priv; 2402 struct phy_device *phydev; 2403 struct dsa_port *dp; 2404 2405 if (!mt753x_is_mac_port(port)) { 2406 dev_err(priv->dev, "port %d is not a MAC port\n", port); 2407 return -EINVAL; 2408 } 2409 2410 switch (interface) { 2411 case PHY_INTERFACE_MODE_RGMII: 2412 case PHY_INTERFACE_MODE_RGMII_ID: 2413 case PHY_INTERFACE_MODE_RGMII_RXID: 2414 case PHY_INTERFACE_MODE_RGMII_TXID: 2415 dp = dsa_to_port(ds, port); 2416 phydev = dp->slave->phydev; 2417 return mt7531_rgmii_setup(priv, port, interface, phydev); 2418 case PHY_INTERFACE_MODE_SGMII: 2419 return mt7531_sgmii_setup_mode_an(priv, port, interface); 2420 case PHY_INTERFACE_MODE_NA: 2421 case PHY_INTERFACE_MODE_1000BASEX: 2422 case PHY_INTERFACE_MODE_2500BASEX: 2423 if (phylink_autoneg_inband(mode)) 2424 return -EINVAL; 2425 2426 return mt7531_sgmii_setup_mode_force(priv, port, interface); 2427 default: 2428 return -EINVAL; 2429 } 2430 2431 return -EINVAL; 2432 } 2433 2434 static int 2435 mt753x_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2436 const struct phylink_link_state *state) 2437 { 2438 struct mt7530_priv *priv = ds->priv; 2439 2440 return priv->info->mac_port_config(ds, port, mode, state->interface); 2441 } 2442 2443 static void 2444 mt753x_phylink_mac_config(struct dsa_switch *ds, int port, unsigned int mode, 2445 const struct phylink_link_state *state) 2446 { 2447 struct mt7530_priv *priv = ds->priv; 2448 u32 mcr_cur, mcr_new; 2449 2450 if (!mt753x_phy_mode_supported(ds, port, state)) 2451 goto unsupported; 2452 2453 switch (port) { 2454 case 0 ... 4: /* Internal phy */ 2455 if (state->interface != PHY_INTERFACE_MODE_GMII) 2456 goto unsupported; 2457 break; 2458 case 5: /* 2nd cpu port with phy of port 0 or 4 / external phy */ 2459 if (priv->p5_interface == state->interface) 2460 break; 2461 2462 if (mt753x_mac_config(ds, port, mode, state) < 0) 2463 goto unsupported; 2464 2465 if (priv->p5_intf_sel != P5_DISABLED) 2466 priv->p5_interface = state->interface; 2467 break; 2468 case 6: /* 1st cpu port */ 2469 if (priv->p6_interface == state->interface) 2470 break; 2471 2472 mt753x_pad_setup(ds, state); 2473 2474 if (mt753x_mac_config(ds, port, mode, state) < 0) 2475 goto unsupported; 2476 2477 priv->p6_interface = state->interface; 2478 break; 2479 default: 2480 unsupported: 2481 dev_err(ds->dev, "%s: unsupported %s port: %i\n", 2482 __func__, phy_modes(state->interface), port); 2483 return; 2484 } 2485 2486 if (phylink_autoneg_inband(mode) && 2487 state->interface != PHY_INTERFACE_MODE_SGMII) { 2488 dev_err(ds->dev, "%s: in-band negotiation unsupported\n", 2489 __func__); 2490 return; 2491 } 2492 2493 mcr_cur = mt7530_read(priv, MT7530_PMCR_P(port)); 2494 mcr_new = mcr_cur; 2495 mcr_new &= ~PMCR_LINK_SETTINGS_MASK; 2496 mcr_new |= PMCR_IFG_XMIT(1) | PMCR_MAC_MODE | PMCR_BACKOFF_EN | 2497 PMCR_BACKPR_EN | PMCR_FORCE_MODE_ID(priv->id); 2498 2499 /* Are we connected to external phy */ 2500 if (port == 5 && dsa_is_user_port(ds, 5)) 2501 mcr_new |= PMCR_EXT_PHY; 2502 2503 if (mcr_new != mcr_cur) 2504 mt7530_write(priv, MT7530_PMCR_P(port), mcr_new); 2505 } 2506 2507 static void 2508 mt753x_phylink_mac_an_restart(struct dsa_switch *ds, int port) 2509 { 2510 struct mt7530_priv *priv = ds->priv; 2511 2512 if (!priv->info->mac_pcs_an_restart) 2513 return; 2514 2515 priv->info->mac_pcs_an_restart(ds, port); 2516 } 2517 2518 static void mt753x_phylink_mac_link_down(struct dsa_switch *ds, int port, 2519 unsigned int mode, 2520 phy_interface_t interface) 2521 { 2522 struct mt7530_priv *priv = ds->priv; 2523 2524 mt7530_clear(priv, MT7530_PMCR_P(port), PMCR_LINK_SETTINGS_MASK); 2525 } 2526 2527 static void mt753x_mac_pcs_link_up(struct dsa_switch *ds, int port, 2528 unsigned int mode, phy_interface_t interface, 2529 int speed, int duplex) 2530 { 2531 struct mt7530_priv *priv = ds->priv; 2532 2533 if (!priv->info->mac_pcs_link_up) 2534 return; 2535 2536 priv->info->mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2537 } 2538 2539 static void mt753x_phylink_mac_link_up(struct dsa_switch *ds, int port, 2540 unsigned int mode, 2541 phy_interface_t interface, 2542 struct phy_device *phydev, 2543 int speed, int duplex, 2544 bool tx_pause, bool rx_pause) 2545 { 2546 struct mt7530_priv *priv = ds->priv; 2547 u32 mcr; 2548 2549 mt753x_mac_pcs_link_up(ds, port, mode, interface, speed, duplex); 2550 2551 mcr = PMCR_RX_EN | PMCR_TX_EN | PMCR_FORCE_LNK; 2552 2553 /* MT753x MAC works in 1G full duplex mode for all up-clocked 2554 * variants. 2555 */ 2556 if (interface == PHY_INTERFACE_MODE_TRGMII || 2557 (phy_interface_mode_is_8023z(interface))) { 2558 speed = SPEED_1000; 2559 duplex = DUPLEX_FULL; 2560 } 2561 2562 switch (speed) { 2563 case SPEED_1000: 2564 mcr |= PMCR_FORCE_SPEED_1000; 2565 break; 2566 case SPEED_100: 2567 mcr |= PMCR_FORCE_SPEED_100; 2568 break; 2569 } 2570 if (duplex == DUPLEX_FULL) { 2571 mcr |= PMCR_FORCE_FDX; 2572 if (tx_pause) 2573 mcr |= PMCR_TX_FC_EN; 2574 if (rx_pause) 2575 mcr |= PMCR_RX_FC_EN; 2576 } 2577 2578 mt7530_set(priv, MT7530_PMCR_P(port), mcr); 2579 } 2580 2581 static int 2582 mt7531_cpu_port_config(struct dsa_switch *ds, int port) 2583 { 2584 struct mt7530_priv *priv = ds->priv; 2585 phy_interface_t interface; 2586 int speed; 2587 int ret; 2588 2589 switch (port) { 2590 case 5: 2591 if (mt7531_is_rgmii_port(priv, port)) 2592 interface = PHY_INTERFACE_MODE_RGMII; 2593 else 2594 interface = PHY_INTERFACE_MODE_2500BASEX; 2595 2596 priv->p5_interface = interface; 2597 break; 2598 case 6: 2599 interface = PHY_INTERFACE_MODE_2500BASEX; 2600 2601 mt7531_pad_setup(ds, interface); 2602 2603 priv->p6_interface = interface; 2604 break; 2605 default: 2606 return -EINVAL; 2607 } 2608 2609 if (interface == PHY_INTERFACE_MODE_2500BASEX) 2610 speed = SPEED_2500; 2611 else 2612 speed = SPEED_1000; 2613 2614 ret = mt7531_mac_config(ds, port, MLO_AN_FIXED, interface); 2615 if (ret) 2616 return ret; 2617 mt7530_write(priv, MT7530_PMCR_P(port), 2618 PMCR_CPU_PORT_SETTING(priv->id)); 2619 mt753x_phylink_mac_link_up(ds, port, MLO_AN_FIXED, interface, NULL, 2620 speed, DUPLEX_FULL, true, true); 2621 2622 return 0; 2623 } 2624 2625 static void 2626 mt7530_mac_port_validate(struct dsa_switch *ds, int port, 2627 unsigned long *supported) 2628 { 2629 if (port == 5) 2630 phylink_set(supported, 1000baseX_Full); 2631 } 2632 2633 static void mt7531_mac_port_validate(struct dsa_switch *ds, int port, 2634 unsigned long *supported) 2635 { 2636 struct mt7530_priv *priv = ds->priv; 2637 2638 mt7531_sgmii_validate(priv, port, supported); 2639 } 2640 2641 static void 2642 mt753x_phylink_validate(struct dsa_switch *ds, int port, 2643 unsigned long *supported, 2644 struct phylink_link_state *state) 2645 { 2646 __ETHTOOL_DECLARE_LINK_MODE_MASK(mask) = { 0, }; 2647 struct mt7530_priv *priv = ds->priv; 2648 2649 if (state->interface != PHY_INTERFACE_MODE_NA && 2650 !mt753x_phy_mode_supported(ds, port, state)) { 2651 linkmode_zero(supported); 2652 return; 2653 } 2654 2655 phylink_set_port_modes(mask); 2656 2657 if (state->interface != PHY_INTERFACE_MODE_TRGMII || 2658 !phy_interface_mode_is_8023z(state->interface)) { 2659 phylink_set(mask, 10baseT_Half); 2660 phylink_set(mask, 10baseT_Full); 2661 phylink_set(mask, 100baseT_Half); 2662 phylink_set(mask, 100baseT_Full); 2663 phylink_set(mask, Autoneg); 2664 } 2665 2666 /* This switch only supports 1G full-duplex. */ 2667 if (state->interface != PHY_INTERFACE_MODE_MII) 2668 phylink_set(mask, 1000baseT_Full); 2669 2670 priv->info->mac_port_validate(ds, port, mask); 2671 2672 phylink_set(mask, Pause); 2673 phylink_set(mask, Asym_Pause); 2674 2675 linkmode_and(supported, supported, mask); 2676 linkmode_and(state->advertising, state->advertising, mask); 2677 2678 /* We can only operate at 2500BaseX or 1000BaseX. If requested 2679 * to advertise both, only report advertising at 2500BaseX. 2680 */ 2681 phylink_helper_basex_speed(state); 2682 } 2683 2684 static int 2685 mt7530_phylink_mac_link_state(struct dsa_switch *ds, int port, 2686 struct phylink_link_state *state) 2687 { 2688 struct mt7530_priv *priv = ds->priv; 2689 u32 pmsr; 2690 2691 if (port < 0 || port >= MT7530_NUM_PORTS) 2692 return -EINVAL; 2693 2694 pmsr = mt7530_read(priv, MT7530_PMSR_P(port)); 2695 2696 state->link = (pmsr & PMSR_LINK); 2697 state->an_complete = state->link; 2698 state->duplex = !!(pmsr & PMSR_DPX); 2699 2700 switch (pmsr & PMSR_SPEED_MASK) { 2701 case PMSR_SPEED_10: 2702 state->speed = SPEED_10; 2703 break; 2704 case PMSR_SPEED_100: 2705 state->speed = SPEED_100; 2706 break; 2707 case PMSR_SPEED_1000: 2708 state->speed = SPEED_1000; 2709 break; 2710 default: 2711 state->speed = SPEED_UNKNOWN; 2712 break; 2713 } 2714 2715 state->pause &= ~(MLO_PAUSE_RX | MLO_PAUSE_TX); 2716 if (pmsr & PMSR_RX_FC) 2717 state->pause |= MLO_PAUSE_RX; 2718 if (pmsr & PMSR_TX_FC) 2719 state->pause |= MLO_PAUSE_TX; 2720 2721 return 1; 2722 } 2723 2724 static int 2725 mt7531_sgmii_pcs_get_state_an(struct mt7530_priv *priv, int port, 2726 struct phylink_link_state *state) 2727 { 2728 u32 status, val; 2729 u16 config_reg; 2730 2731 status = mt7530_read(priv, MT7531_PCS_CONTROL_1(port)); 2732 state->link = !!(status & MT7531_SGMII_LINK_STATUS); 2733 if (state->interface == PHY_INTERFACE_MODE_SGMII && 2734 (status & MT7531_SGMII_AN_ENABLE)) { 2735 val = mt7530_read(priv, MT7531_PCS_SPEED_ABILITY(port)); 2736 config_reg = val >> 16; 2737 2738 switch (config_reg & LPA_SGMII_SPD_MASK) { 2739 case LPA_SGMII_1000: 2740 state->speed = SPEED_1000; 2741 break; 2742 case LPA_SGMII_100: 2743 state->speed = SPEED_100; 2744 break; 2745 case LPA_SGMII_10: 2746 state->speed = SPEED_10; 2747 break; 2748 default: 2749 dev_err(priv->dev, "invalid sgmii PHY speed\n"); 2750 state->link = false; 2751 return -EINVAL; 2752 } 2753 2754 if (config_reg & LPA_SGMII_FULL_DUPLEX) 2755 state->duplex = DUPLEX_FULL; 2756 else 2757 state->duplex = DUPLEX_HALF; 2758 } 2759 2760 return 0; 2761 } 2762 2763 static int 2764 mt7531_phylink_mac_link_state(struct dsa_switch *ds, int port, 2765 struct phylink_link_state *state) 2766 { 2767 struct mt7530_priv *priv = ds->priv; 2768 2769 if (state->interface == PHY_INTERFACE_MODE_SGMII) 2770 return mt7531_sgmii_pcs_get_state_an(priv, port, state); 2771 2772 return -EOPNOTSUPP; 2773 } 2774 2775 static int 2776 mt753x_phylink_mac_link_state(struct dsa_switch *ds, int port, 2777 struct phylink_link_state *state) 2778 { 2779 struct mt7530_priv *priv = ds->priv; 2780 2781 return priv->info->mac_port_get_state(ds, port, state); 2782 } 2783 2784 static int 2785 mt753x_setup(struct dsa_switch *ds) 2786 { 2787 struct mt7530_priv *priv = ds->priv; 2788 2789 return priv->info->sw_setup(ds); 2790 } 2791 2792 static int 2793 mt753x_phy_read(struct dsa_switch *ds, int port, int regnum) 2794 { 2795 struct mt7530_priv *priv = ds->priv; 2796 2797 return priv->info->phy_read(ds, port, regnum); 2798 } 2799 2800 static int 2801 mt753x_phy_write(struct dsa_switch *ds, int port, int regnum, u16 val) 2802 { 2803 struct mt7530_priv *priv = ds->priv; 2804 2805 return priv->info->phy_write(ds, port, regnum, val); 2806 } 2807 2808 static const struct dsa_switch_ops mt7530_switch_ops = { 2809 .get_tag_protocol = mtk_get_tag_protocol, 2810 .setup = mt753x_setup, 2811 .get_strings = mt7530_get_strings, 2812 .phy_read = mt753x_phy_read, 2813 .phy_write = mt753x_phy_write, 2814 .get_ethtool_stats = mt7530_get_ethtool_stats, 2815 .get_sset_count = mt7530_get_sset_count, 2816 .set_ageing_time = mt7530_set_ageing_time, 2817 .port_enable = mt7530_port_enable, 2818 .port_disable = mt7530_port_disable, 2819 .port_change_mtu = mt7530_port_change_mtu, 2820 .port_max_mtu = mt7530_port_max_mtu, 2821 .port_stp_state_set = mt7530_stp_state_set, 2822 .port_pre_bridge_flags = mt7530_port_pre_bridge_flags, 2823 .port_bridge_flags = mt7530_port_bridge_flags, 2824 .port_set_mrouter = mt7530_port_set_mrouter, 2825 .port_bridge_join = mt7530_port_bridge_join, 2826 .port_bridge_leave = mt7530_port_bridge_leave, 2827 .port_fdb_add = mt7530_port_fdb_add, 2828 .port_fdb_del = mt7530_port_fdb_del, 2829 .port_fdb_dump = mt7530_port_fdb_dump, 2830 .port_mdb_add = mt7530_port_mdb_add, 2831 .port_mdb_del = mt7530_port_mdb_del, 2832 .port_vlan_filtering = mt7530_port_vlan_filtering, 2833 .port_vlan_add = mt7530_port_vlan_add, 2834 .port_vlan_del = mt7530_port_vlan_del, 2835 .port_mirror_add = mt753x_port_mirror_add, 2836 .port_mirror_del = mt753x_port_mirror_del, 2837 .phylink_validate = mt753x_phylink_validate, 2838 .phylink_mac_link_state = mt753x_phylink_mac_link_state, 2839 .phylink_mac_config = mt753x_phylink_mac_config, 2840 .phylink_mac_an_restart = mt753x_phylink_mac_an_restart, 2841 .phylink_mac_link_down = mt753x_phylink_mac_link_down, 2842 .phylink_mac_link_up = mt753x_phylink_mac_link_up, 2843 }; 2844 2845 static const struct mt753x_info mt753x_table[] = { 2846 [ID_MT7621] = { 2847 .id = ID_MT7621, 2848 .sw_setup = mt7530_setup, 2849 .phy_read = mt7530_phy_read, 2850 .phy_write = mt7530_phy_write, 2851 .pad_setup = mt7530_pad_clk_setup, 2852 .phy_mode_supported = mt7530_phy_mode_supported, 2853 .mac_port_validate = mt7530_mac_port_validate, 2854 .mac_port_get_state = mt7530_phylink_mac_link_state, 2855 .mac_port_config = mt7530_mac_config, 2856 }, 2857 [ID_MT7530] = { 2858 .id = ID_MT7530, 2859 .sw_setup = mt7530_setup, 2860 .phy_read = mt7530_phy_read, 2861 .phy_write = mt7530_phy_write, 2862 .pad_setup = mt7530_pad_clk_setup, 2863 .phy_mode_supported = mt7530_phy_mode_supported, 2864 .mac_port_validate = mt7530_mac_port_validate, 2865 .mac_port_get_state = mt7530_phylink_mac_link_state, 2866 .mac_port_config = mt7530_mac_config, 2867 }, 2868 [ID_MT7531] = { 2869 .id = ID_MT7531, 2870 .sw_setup = mt7531_setup, 2871 .phy_read = mt7531_ind_phy_read, 2872 .phy_write = mt7531_ind_phy_write, 2873 .pad_setup = mt7531_pad_setup, 2874 .cpu_port_config = mt7531_cpu_port_config, 2875 .phy_mode_supported = mt7531_phy_mode_supported, 2876 .mac_port_validate = mt7531_mac_port_validate, 2877 .mac_port_get_state = mt7531_phylink_mac_link_state, 2878 .mac_port_config = mt7531_mac_config, 2879 .mac_pcs_an_restart = mt7531_sgmii_restart_an, 2880 .mac_pcs_link_up = mt7531_sgmii_link_up_force, 2881 }, 2882 }; 2883 2884 static const struct of_device_id mt7530_of_match[] = { 2885 { .compatible = "mediatek,mt7621", .data = &mt753x_table[ID_MT7621], }, 2886 { .compatible = "mediatek,mt7530", .data = &mt753x_table[ID_MT7530], }, 2887 { .compatible = "mediatek,mt7531", .data = &mt753x_table[ID_MT7531], }, 2888 { /* sentinel */ }, 2889 }; 2890 MODULE_DEVICE_TABLE(of, mt7530_of_match); 2891 2892 static int 2893 mt7530_probe(struct mdio_device *mdiodev) 2894 { 2895 struct mt7530_priv *priv; 2896 struct device_node *dn; 2897 2898 dn = mdiodev->dev.of_node; 2899 2900 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 2901 if (!priv) 2902 return -ENOMEM; 2903 2904 priv->ds = devm_kzalloc(&mdiodev->dev, sizeof(*priv->ds), GFP_KERNEL); 2905 if (!priv->ds) 2906 return -ENOMEM; 2907 2908 priv->ds->dev = &mdiodev->dev; 2909 priv->ds->num_ports = DSA_MAX_PORTS; 2910 2911 /* Use medatek,mcm property to distinguish hardware type that would 2912 * casues a little bit differences on power-on sequence. 2913 */ 2914 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 2915 if (priv->mcm) { 2916 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 2917 2918 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 2919 if (IS_ERR(priv->rstc)) { 2920 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2921 return PTR_ERR(priv->rstc); 2922 } 2923 } 2924 2925 /* Get the hardware identifier from the devicetree node. 2926 * We will need it for some of the clock and regulator setup. 2927 */ 2928 priv->info = of_device_get_match_data(&mdiodev->dev); 2929 if (!priv->info) 2930 return -EINVAL; 2931 2932 /* Sanity check if these required device operations are filled 2933 * properly. 2934 */ 2935 if (!priv->info->sw_setup || !priv->info->pad_setup || 2936 !priv->info->phy_read || !priv->info->phy_write || 2937 !priv->info->phy_mode_supported || 2938 !priv->info->mac_port_validate || 2939 !priv->info->mac_port_get_state || !priv->info->mac_port_config) 2940 return -EINVAL; 2941 2942 priv->id = priv->info->id; 2943 2944 if (priv->id == ID_MT7530) { 2945 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 2946 if (IS_ERR(priv->core_pwr)) 2947 return PTR_ERR(priv->core_pwr); 2948 2949 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 2950 if (IS_ERR(priv->io_pwr)) 2951 return PTR_ERR(priv->io_pwr); 2952 } 2953 2954 /* Not MCM that indicates switch works as the remote standalone 2955 * integrated circuit so the GPIO pin would be used to complete 2956 * the reset, otherwise memory-mapped register accessing used 2957 * through syscon provides in the case of MCM. 2958 */ 2959 if (!priv->mcm) { 2960 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 2961 GPIOD_OUT_LOW); 2962 if (IS_ERR(priv->reset)) { 2963 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 2964 return PTR_ERR(priv->reset); 2965 } 2966 } 2967 2968 priv->bus = mdiodev->bus; 2969 priv->dev = &mdiodev->dev; 2970 priv->ds->priv = priv; 2971 priv->ds->ops = &mt7530_switch_ops; 2972 mutex_init(&priv->reg_mutex); 2973 dev_set_drvdata(&mdiodev->dev, priv); 2974 2975 return dsa_register_switch(priv->ds); 2976 } 2977 2978 static void 2979 mt7530_remove(struct mdio_device *mdiodev) 2980 { 2981 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 2982 int ret = 0; 2983 2984 ret = regulator_disable(priv->core_pwr); 2985 if (ret < 0) 2986 dev_err(priv->dev, 2987 "Failed to disable core power: %d\n", ret); 2988 2989 ret = regulator_disable(priv->io_pwr); 2990 if (ret < 0) 2991 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 2992 ret); 2993 2994 dsa_unregister_switch(priv->ds); 2995 mutex_destroy(&priv->reg_mutex); 2996 } 2997 2998 static struct mdio_driver mt7530_mdio_driver = { 2999 .probe = mt7530_probe, 3000 .remove = mt7530_remove, 3001 .mdiodrv.driver = { 3002 .name = "mt7530", 3003 .of_match_table = mt7530_of_match, 3004 }, 3005 }; 3006 3007 mdio_module_driver(mt7530_mdio_driver); 3008 3009 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 3010 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 3011 MODULE_LICENSE("GPL"); 3012