1 /* 2 * Mediatek MT7530 DSA Switch driver 3 * Copyright (C) 2017 Sean Wang <sean.wang@mediatek.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License version 2 as 7 * published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope that it will be useful, 10 * but WITHOUT ANY WARRANTY; without even the implied warranty of 11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 12 * GNU General Public License for more details. 13 */ 14 #include <linux/etherdevice.h> 15 #include <linux/if_bridge.h> 16 #include <linux/iopoll.h> 17 #include <linux/mdio.h> 18 #include <linux/mfd/syscon.h> 19 #include <linux/module.h> 20 #include <linux/netdevice.h> 21 #include <linux/of_gpio.h> 22 #include <linux/of_mdio.h> 23 #include <linux/of_net.h> 24 #include <linux/of_platform.h> 25 #include <linux/phy.h> 26 #include <linux/regmap.h> 27 #include <linux/regulator/consumer.h> 28 #include <linux/reset.h> 29 #include <linux/gpio/consumer.h> 30 #include <net/dsa.h> 31 32 #include "mt7530.h" 33 34 /* String, offset, and register size in bytes if different from 4 bytes */ 35 static const struct mt7530_mib_desc mt7530_mib[] = { 36 MIB_DESC(1, 0x00, "TxDrop"), 37 MIB_DESC(1, 0x04, "TxCrcErr"), 38 MIB_DESC(1, 0x08, "TxUnicast"), 39 MIB_DESC(1, 0x0c, "TxMulticast"), 40 MIB_DESC(1, 0x10, "TxBroadcast"), 41 MIB_DESC(1, 0x14, "TxCollision"), 42 MIB_DESC(1, 0x18, "TxSingleCollision"), 43 MIB_DESC(1, 0x1c, "TxMultipleCollision"), 44 MIB_DESC(1, 0x20, "TxDeferred"), 45 MIB_DESC(1, 0x24, "TxLateCollision"), 46 MIB_DESC(1, 0x28, "TxExcessiveCollistion"), 47 MIB_DESC(1, 0x2c, "TxPause"), 48 MIB_DESC(1, 0x30, "TxPktSz64"), 49 MIB_DESC(1, 0x34, "TxPktSz65To127"), 50 MIB_DESC(1, 0x38, "TxPktSz128To255"), 51 MIB_DESC(1, 0x3c, "TxPktSz256To511"), 52 MIB_DESC(1, 0x40, "TxPktSz512To1023"), 53 MIB_DESC(1, 0x44, "Tx1024ToMax"), 54 MIB_DESC(2, 0x48, "TxBytes"), 55 MIB_DESC(1, 0x60, "RxDrop"), 56 MIB_DESC(1, 0x64, "RxFiltering"), 57 MIB_DESC(1, 0x6c, "RxMulticast"), 58 MIB_DESC(1, 0x70, "RxBroadcast"), 59 MIB_DESC(1, 0x74, "RxAlignErr"), 60 MIB_DESC(1, 0x78, "RxCrcErr"), 61 MIB_DESC(1, 0x7c, "RxUnderSizeErr"), 62 MIB_DESC(1, 0x80, "RxFragErr"), 63 MIB_DESC(1, 0x84, "RxOverSzErr"), 64 MIB_DESC(1, 0x88, "RxJabberErr"), 65 MIB_DESC(1, 0x8c, "RxPause"), 66 MIB_DESC(1, 0x90, "RxPktSz64"), 67 MIB_DESC(1, 0x94, "RxPktSz65To127"), 68 MIB_DESC(1, 0x98, "RxPktSz128To255"), 69 MIB_DESC(1, 0x9c, "RxPktSz256To511"), 70 MIB_DESC(1, 0xa0, "RxPktSz512To1023"), 71 MIB_DESC(1, 0xa4, "RxPktSz1024ToMax"), 72 MIB_DESC(2, 0xa8, "RxBytes"), 73 MIB_DESC(1, 0xb0, "RxCtrlDrop"), 74 MIB_DESC(1, 0xb4, "RxIngressDrop"), 75 MIB_DESC(1, 0xb8, "RxArlDrop"), 76 }; 77 78 static int 79 mt7623_trgmii_write(struct mt7530_priv *priv, u32 reg, u32 val) 80 { 81 int ret; 82 83 ret = regmap_write(priv->ethernet, TRGMII_BASE(reg), val); 84 if (ret < 0) 85 dev_err(priv->dev, 86 "failed to priv write register\n"); 87 return ret; 88 } 89 90 static u32 91 mt7623_trgmii_read(struct mt7530_priv *priv, u32 reg) 92 { 93 int ret; 94 u32 val; 95 96 ret = regmap_read(priv->ethernet, TRGMII_BASE(reg), &val); 97 if (ret < 0) { 98 dev_err(priv->dev, 99 "failed to priv read register\n"); 100 return ret; 101 } 102 103 return val; 104 } 105 106 static void 107 mt7623_trgmii_rmw(struct mt7530_priv *priv, u32 reg, 108 u32 mask, u32 set) 109 { 110 u32 val; 111 112 val = mt7623_trgmii_read(priv, reg); 113 val &= ~mask; 114 val |= set; 115 mt7623_trgmii_write(priv, reg, val); 116 } 117 118 static void 119 mt7623_trgmii_set(struct mt7530_priv *priv, u32 reg, u32 val) 120 { 121 mt7623_trgmii_rmw(priv, reg, 0, val); 122 } 123 124 static void 125 mt7623_trgmii_clear(struct mt7530_priv *priv, u32 reg, u32 val) 126 { 127 mt7623_trgmii_rmw(priv, reg, val, 0); 128 } 129 130 static int 131 core_read_mmd_indirect(struct mt7530_priv *priv, int prtad, int devad) 132 { 133 struct mii_bus *bus = priv->bus; 134 int value, ret; 135 136 /* Write the desired MMD Devad */ 137 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 138 if (ret < 0) 139 goto err; 140 141 /* Write the desired MMD register address */ 142 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 143 if (ret < 0) 144 goto err; 145 146 /* Select the Function : DATA with no post increment */ 147 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 148 if (ret < 0) 149 goto err; 150 151 /* Read the content of the MMD's selected register */ 152 value = bus->read(bus, 0, MII_MMD_DATA); 153 154 return value; 155 err: 156 dev_err(&bus->dev, "failed to read mmd register\n"); 157 158 return ret; 159 } 160 161 static int 162 core_write_mmd_indirect(struct mt7530_priv *priv, int prtad, 163 int devad, u32 data) 164 { 165 struct mii_bus *bus = priv->bus; 166 int ret; 167 168 /* Write the desired MMD Devad */ 169 ret = bus->write(bus, 0, MII_MMD_CTRL, devad); 170 if (ret < 0) 171 goto err; 172 173 /* Write the desired MMD register address */ 174 ret = bus->write(bus, 0, MII_MMD_DATA, prtad); 175 if (ret < 0) 176 goto err; 177 178 /* Select the Function : DATA with no post increment */ 179 ret = bus->write(bus, 0, MII_MMD_CTRL, (devad | MII_MMD_CTRL_NOINCR)); 180 if (ret < 0) 181 goto err; 182 183 /* Write the data into MMD's selected register */ 184 ret = bus->write(bus, 0, MII_MMD_DATA, data); 185 err: 186 if (ret < 0) 187 dev_err(&bus->dev, 188 "failed to write mmd register\n"); 189 return ret; 190 } 191 192 static void 193 core_write(struct mt7530_priv *priv, u32 reg, u32 val) 194 { 195 struct mii_bus *bus = priv->bus; 196 197 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 198 199 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 200 201 mutex_unlock(&bus->mdio_lock); 202 } 203 204 static void 205 core_rmw(struct mt7530_priv *priv, u32 reg, u32 mask, u32 set) 206 { 207 struct mii_bus *bus = priv->bus; 208 u32 val; 209 210 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 211 212 val = core_read_mmd_indirect(priv, reg, MDIO_MMD_VEND2); 213 val &= ~mask; 214 val |= set; 215 core_write_mmd_indirect(priv, reg, MDIO_MMD_VEND2, val); 216 217 mutex_unlock(&bus->mdio_lock); 218 } 219 220 static void 221 core_set(struct mt7530_priv *priv, u32 reg, u32 val) 222 { 223 core_rmw(priv, reg, 0, val); 224 } 225 226 static void 227 core_clear(struct mt7530_priv *priv, u32 reg, u32 val) 228 { 229 core_rmw(priv, reg, val, 0); 230 } 231 232 static int 233 mt7530_mii_write(struct mt7530_priv *priv, u32 reg, u32 val) 234 { 235 struct mii_bus *bus = priv->bus; 236 u16 page, r, lo, hi; 237 int ret; 238 239 page = (reg >> 6) & 0x3ff; 240 r = (reg >> 2) & 0xf; 241 lo = val & 0xffff; 242 hi = val >> 16; 243 244 /* MT7530 uses 31 as the pseudo port */ 245 ret = bus->write(bus, 0x1f, 0x1f, page); 246 if (ret < 0) 247 goto err; 248 249 ret = bus->write(bus, 0x1f, r, lo); 250 if (ret < 0) 251 goto err; 252 253 ret = bus->write(bus, 0x1f, 0x10, hi); 254 err: 255 if (ret < 0) 256 dev_err(&bus->dev, 257 "failed to write mt7530 register\n"); 258 return ret; 259 } 260 261 static u32 262 mt7530_mii_read(struct mt7530_priv *priv, u32 reg) 263 { 264 struct mii_bus *bus = priv->bus; 265 u16 page, r, lo, hi; 266 int ret; 267 268 page = (reg >> 6) & 0x3ff; 269 r = (reg >> 2) & 0xf; 270 271 /* MT7530 uses 31 as the pseudo port */ 272 ret = bus->write(bus, 0x1f, 0x1f, page); 273 if (ret < 0) { 274 dev_err(&bus->dev, 275 "failed to read mt7530 register\n"); 276 return ret; 277 } 278 279 lo = bus->read(bus, 0x1f, r); 280 hi = bus->read(bus, 0x1f, 0x10); 281 282 return (hi << 16) | (lo & 0xffff); 283 } 284 285 static void 286 mt7530_write(struct mt7530_priv *priv, u32 reg, u32 val) 287 { 288 struct mii_bus *bus = priv->bus; 289 290 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 291 292 mt7530_mii_write(priv, reg, val); 293 294 mutex_unlock(&bus->mdio_lock); 295 } 296 297 static u32 298 _mt7530_read(struct mt7530_dummy_poll *p) 299 { 300 struct mii_bus *bus = p->priv->bus; 301 u32 val; 302 303 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 304 305 val = mt7530_mii_read(p->priv, p->reg); 306 307 mutex_unlock(&bus->mdio_lock); 308 309 return val; 310 } 311 312 static u32 313 mt7530_read(struct mt7530_priv *priv, u32 reg) 314 { 315 struct mt7530_dummy_poll p; 316 317 INIT_MT7530_DUMMY_POLL(&p, priv, reg); 318 return _mt7530_read(&p); 319 } 320 321 static void 322 mt7530_rmw(struct mt7530_priv *priv, u32 reg, 323 u32 mask, u32 set) 324 { 325 struct mii_bus *bus = priv->bus; 326 u32 val; 327 328 mutex_lock_nested(&bus->mdio_lock, MDIO_MUTEX_NESTED); 329 330 val = mt7530_mii_read(priv, reg); 331 val &= ~mask; 332 val |= set; 333 mt7530_mii_write(priv, reg, val); 334 335 mutex_unlock(&bus->mdio_lock); 336 } 337 338 static void 339 mt7530_set(struct mt7530_priv *priv, u32 reg, u32 val) 340 { 341 mt7530_rmw(priv, reg, 0, val); 342 } 343 344 static void 345 mt7530_clear(struct mt7530_priv *priv, u32 reg, u32 val) 346 { 347 mt7530_rmw(priv, reg, val, 0); 348 } 349 350 static int 351 mt7530_fdb_cmd(struct mt7530_priv *priv, enum mt7530_fdb_cmd cmd, u32 *rsp) 352 { 353 u32 val; 354 int ret; 355 struct mt7530_dummy_poll p; 356 357 /* Set the command operating upon the MAC address entries */ 358 val = ATC_BUSY | ATC_MAT(0) | cmd; 359 mt7530_write(priv, MT7530_ATC, val); 360 361 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_ATC); 362 ret = readx_poll_timeout(_mt7530_read, &p, val, 363 !(val & ATC_BUSY), 20, 20000); 364 if (ret < 0) { 365 dev_err(priv->dev, "reset timeout\n"); 366 return ret; 367 } 368 369 /* Additional sanity for read command if the specified 370 * entry is invalid 371 */ 372 val = mt7530_read(priv, MT7530_ATC); 373 if ((cmd == MT7530_FDB_READ) && (val & ATC_INVALID)) 374 return -EINVAL; 375 376 if (rsp) 377 *rsp = val; 378 379 return 0; 380 } 381 382 static void 383 mt7530_fdb_read(struct mt7530_priv *priv, struct mt7530_fdb *fdb) 384 { 385 u32 reg[3]; 386 int i; 387 388 /* Read from ARL table into an array */ 389 for (i = 0; i < 3; i++) { 390 reg[i] = mt7530_read(priv, MT7530_TSRA1 + (i * 4)); 391 392 dev_dbg(priv->dev, "%s(%d) reg[%d]=0x%x\n", 393 __func__, __LINE__, i, reg[i]); 394 } 395 396 fdb->vid = (reg[1] >> CVID) & CVID_MASK; 397 fdb->aging = (reg[2] >> AGE_TIMER) & AGE_TIMER_MASK; 398 fdb->port_mask = (reg[2] >> PORT_MAP) & PORT_MAP_MASK; 399 fdb->mac[0] = (reg[0] >> MAC_BYTE_0) & MAC_BYTE_MASK; 400 fdb->mac[1] = (reg[0] >> MAC_BYTE_1) & MAC_BYTE_MASK; 401 fdb->mac[2] = (reg[0] >> MAC_BYTE_2) & MAC_BYTE_MASK; 402 fdb->mac[3] = (reg[0] >> MAC_BYTE_3) & MAC_BYTE_MASK; 403 fdb->mac[4] = (reg[1] >> MAC_BYTE_4) & MAC_BYTE_MASK; 404 fdb->mac[5] = (reg[1] >> MAC_BYTE_5) & MAC_BYTE_MASK; 405 fdb->noarp = ((reg[2] >> ENT_STATUS) & ENT_STATUS_MASK) == STATIC_ENT; 406 } 407 408 static void 409 mt7530_fdb_write(struct mt7530_priv *priv, u16 vid, 410 u8 port_mask, const u8 *mac, 411 u8 aging, u8 type) 412 { 413 u32 reg[3] = { 0 }; 414 int i; 415 416 reg[1] |= vid & CVID_MASK; 417 reg[2] |= (aging & AGE_TIMER_MASK) << AGE_TIMER; 418 reg[2] |= (port_mask & PORT_MAP_MASK) << PORT_MAP; 419 /* STATIC_ENT indicate that entry is static wouldn't 420 * be aged out and STATIC_EMP specified as erasing an 421 * entry 422 */ 423 reg[2] |= (type & ENT_STATUS_MASK) << ENT_STATUS; 424 reg[1] |= mac[5] << MAC_BYTE_5; 425 reg[1] |= mac[4] << MAC_BYTE_4; 426 reg[0] |= mac[3] << MAC_BYTE_3; 427 reg[0] |= mac[2] << MAC_BYTE_2; 428 reg[0] |= mac[1] << MAC_BYTE_1; 429 reg[0] |= mac[0] << MAC_BYTE_0; 430 431 /* Write array into the ARL table */ 432 for (i = 0; i < 3; i++) 433 mt7530_write(priv, MT7530_ATA1 + (i * 4), reg[i]); 434 } 435 436 static int 437 mt7530_pad_clk_setup(struct dsa_switch *ds, int mode) 438 { 439 struct mt7530_priv *priv = ds->priv; 440 u32 ncpo1, ssc_delta, trgint, i; 441 442 switch (mode) { 443 case PHY_INTERFACE_MODE_RGMII: 444 trgint = 0; 445 ncpo1 = 0x0c80; 446 ssc_delta = 0x87; 447 break; 448 case PHY_INTERFACE_MODE_TRGMII: 449 trgint = 1; 450 ncpo1 = 0x1400; 451 ssc_delta = 0x57; 452 break; 453 default: 454 dev_err(priv->dev, "xMII mode %d not supported\n", mode); 455 return -EINVAL; 456 } 457 458 mt7530_rmw(priv, MT7530_P6ECR, P6_INTF_MODE_MASK, 459 P6_INTF_MODE(trgint)); 460 461 /* Lower Tx Driving for TRGMII path */ 462 for (i = 0 ; i < NUM_TRGMII_CTRL ; i++) 463 mt7530_write(priv, MT7530_TRGMII_TD_ODT(i), 464 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 465 466 /* Setup core clock for MT7530 */ 467 if (!trgint) { 468 /* Disable MT7530 core clock */ 469 core_clear(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 470 471 /* Disable PLL, since phy_device has not yet been created 472 * provided for phy_[read,write]_mmd_indirect is called, we 473 * provide our own core_write_mmd_indirect to complete this 474 * function. 475 */ 476 core_write_mmd_indirect(priv, 477 CORE_GSWPLL_GRP1, 478 MDIO_MMD_VEND2, 479 0); 480 481 /* Set core clock into 500Mhz */ 482 core_write(priv, CORE_GSWPLL_GRP2, 483 RG_GSWPLL_POSDIV_500M(1) | 484 RG_GSWPLL_FBKDIV_500M(25)); 485 486 /* Enable PLL */ 487 core_write(priv, CORE_GSWPLL_GRP1, 488 RG_GSWPLL_EN_PRE | 489 RG_GSWPLL_POSDIV_200M(2) | 490 RG_GSWPLL_FBKDIV_200M(32)); 491 492 /* Enable MT7530 core clock */ 493 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 494 } 495 496 /* Setup the MT7530 TRGMII Tx Clock */ 497 core_set(priv, CORE_TRGMII_GSW_CLK_CG, REG_GSWCK_EN); 498 core_write(priv, CORE_PLL_GROUP5, RG_LCDDS_PCW_NCPO1(ncpo1)); 499 core_write(priv, CORE_PLL_GROUP6, RG_LCDDS_PCW_NCPO0(0)); 500 core_write(priv, CORE_PLL_GROUP10, RG_LCDDS_SSC_DELTA(ssc_delta)); 501 core_write(priv, CORE_PLL_GROUP11, RG_LCDDS_SSC_DELTA1(ssc_delta)); 502 core_write(priv, CORE_PLL_GROUP4, 503 RG_SYSPLL_DDSFBK_EN | RG_SYSPLL_BIAS_EN | 504 RG_SYSPLL_BIAS_LPF_EN); 505 core_write(priv, CORE_PLL_GROUP2, 506 RG_SYSPLL_EN_NORMAL | RG_SYSPLL_VODEN | 507 RG_SYSPLL_POSDIV(1)); 508 core_write(priv, CORE_PLL_GROUP7, 509 RG_LCDDS_PCW_NCPO_CHG | RG_LCCDS_C(3) | 510 RG_LCDDS_PWDB | RG_LCDDS_ISO_EN); 511 core_set(priv, CORE_TRGMII_GSW_CLK_CG, 512 REG_GSWCK_EN | REG_TRGMIICK_EN); 513 514 if (!trgint) 515 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 516 mt7530_rmw(priv, MT7530_TRGMII_RD(i), 517 RD_TAP_MASK, RD_TAP(16)); 518 else 519 mt7623_trgmii_set(priv, GSW_INTF_MODE, INTF_MODE_TRGMII); 520 521 return 0; 522 } 523 524 static int 525 mt7623_pad_clk_setup(struct dsa_switch *ds) 526 { 527 struct mt7530_priv *priv = ds->priv; 528 int i; 529 530 for (i = 0 ; i < NUM_TRGMII_CTRL; i++) 531 mt7623_trgmii_write(priv, GSW_TRGMII_TD_ODT(i), 532 TD_DM_DRVP(8) | TD_DM_DRVN(8)); 533 534 mt7623_trgmii_set(priv, GSW_TRGMII_RCK_CTRL, RX_RST | RXC_DQSISEL); 535 mt7623_trgmii_clear(priv, GSW_TRGMII_RCK_CTRL, RX_RST); 536 537 return 0; 538 } 539 540 static void 541 mt7530_mib_reset(struct dsa_switch *ds) 542 { 543 struct mt7530_priv *priv = ds->priv; 544 545 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_FLUSH); 546 mt7530_write(priv, MT7530_MIB_CCR, CCR_MIB_ACTIVATE); 547 } 548 549 static void 550 mt7530_port_set_status(struct mt7530_priv *priv, int port, int enable) 551 { 552 u32 mask = PMCR_TX_EN | PMCR_RX_EN; 553 554 if (enable) 555 mt7530_set(priv, MT7530_PMCR_P(port), mask); 556 else 557 mt7530_clear(priv, MT7530_PMCR_P(port), mask); 558 } 559 560 static int mt7530_phy_read(struct dsa_switch *ds, int port, int regnum) 561 { 562 struct mt7530_priv *priv = ds->priv; 563 564 return mdiobus_read_nested(priv->bus, port, regnum); 565 } 566 567 static int mt7530_phy_write(struct dsa_switch *ds, int port, int regnum, 568 u16 val) 569 { 570 struct mt7530_priv *priv = ds->priv; 571 572 return mdiobus_write_nested(priv->bus, port, regnum, val); 573 } 574 575 static void 576 mt7530_get_strings(struct dsa_switch *ds, int port, uint8_t *data) 577 { 578 int i; 579 580 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) 581 strncpy(data + i * ETH_GSTRING_LEN, mt7530_mib[i].name, 582 ETH_GSTRING_LEN); 583 } 584 585 static void 586 mt7530_get_ethtool_stats(struct dsa_switch *ds, int port, 587 uint64_t *data) 588 { 589 struct mt7530_priv *priv = ds->priv; 590 const struct mt7530_mib_desc *mib; 591 u32 reg, i; 592 u64 hi; 593 594 for (i = 0; i < ARRAY_SIZE(mt7530_mib); i++) { 595 mib = &mt7530_mib[i]; 596 reg = MT7530_PORT_MIB_COUNTER(port) + mib->offset; 597 598 data[i] = mt7530_read(priv, reg); 599 if (mib->size == 2) { 600 hi = mt7530_read(priv, reg + 4); 601 data[i] |= hi << 32; 602 } 603 } 604 } 605 606 static int 607 mt7530_get_sset_count(struct dsa_switch *ds) 608 { 609 return ARRAY_SIZE(mt7530_mib); 610 } 611 612 static void mt7530_adjust_link(struct dsa_switch *ds, int port, 613 struct phy_device *phydev) 614 { 615 struct mt7530_priv *priv = ds->priv; 616 617 if (phy_is_pseudo_fixed_link(phydev)) { 618 dev_dbg(priv->dev, "phy-mode for master device = %x\n", 619 phydev->interface); 620 621 /* Setup TX circuit incluing relevant PAD and driving */ 622 mt7530_pad_clk_setup(ds, phydev->interface); 623 624 /* Setup RX circuit, relevant PAD and driving on the host 625 * which must be placed after the setup on the device side is 626 * all finished. 627 */ 628 mt7623_pad_clk_setup(ds); 629 } else { 630 u16 lcl_adv = 0, rmt_adv = 0; 631 u8 flowctrl; 632 u32 mcr = PMCR_USERP_LINK | PMCR_FORCE_MODE; 633 634 switch (phydev->speed) { 635 case SPEED_1000: 636 mcr |= PMCR_FORCE_SPEED_1000; 637 break; 638 case SPEED_100: 639 mcr |= PMCR_FORCE_SPEED_100; 640 break; 641 }; 642 643 if (phydev->link) 644 mcr |= PMCR_FORCE_LNK; 645 646 if (phydev->duplex) { 647 mcr |= PMCR_FORCE_FDX; 648 649 if (phydev->pause) 650 rmt_adv = LPA_PAUSE_CAP; 651 if (phydev->asym_pause) 652 rmt_adv |= LPA_PAUSE_ASYM; 653 654 if (phydev->advertising & ADVERTISED_Pause) 655 lcl_adv |= ADVERTISE_PAUSE_CAP; 656 if (phydev->advertising & ADVERTISED_Asym_Pause) 657 lcl_adv |= ADVERTISE_PAUSE_ASYM; 658 659 flowctrl = mii_resolve_flowctrl_fdx(lcl_adv, rmt_adv); 660 661 if (flowctrl & FLOW_CTRL_TX) 662 mcr |= PMCR_TX_FC_EN; 663 if (flowctrl & FLOW_CTRL_RX) 664 mcr |= PMCR_RX_FC_EN; 665 } 666 mt7530_write(priv, MT7530_PMCR_P(port), mcr); 667 } 668 } 669 670 static int 671 mt7530_cpu_port_enable(struct mt7530_priv *priv, 672 int port) 673 { 674 /* Enable Mediatek header mode on the cpu port */ 675 mt7530_write(priv, MT7530_PVC_P(port), 676 PORT_SPEC_TAG); 677 678 /* Setup the MAC by default for the cpu port */ 679 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_CPUP_LINK); 680 681 /* Disable auto learning on the cpu port */ 682 mt7530_set(priv, MT7530_PSC_P(port), SA_DIS); 683 684 /* Unknown unicast frame fordwarding to the cpu port */ 685 mt7530_set(priv, MT7530_MFC, UNU_FFP(BIT(port))); 686 687 /* CPU port gets connected to all user ports of 688 * the switch 689 */ 690 mt7530_write(priv, MT7530_PCR_P(port), 691 PCR_MATRIX(dsa_user_ports(priv->ds))); 692 693 return 0; 694 } 695 696 static int 697 mt7530_port_enable(struct dsa_switch *ds, int port, 698 struct phy_device *phy) 699 { 700 struct mt7530_priv *priv = ds->priv; 701 702 mutex_lock(&priv->reg_mutex); 703 704 /* Setup the MAC for the user port */ 705 mt7530_write(priv, MT7530_PMCR_P(port), PMCR_USERP_LINK); 706 707 /* Allow the user port gets connected to the cpu port and also 708 * restore the port matrix if the port is the member of a certain 709 * bridge. 710 */ 711 priv->ports[port].pm |= PCR_MATRIX(BIT(MT7530_CPU_PORT)); 712 priv->ports[port].enable = true; 713 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 714 priv->ports[port].pm); 715 mt7530_port_set_status(priv, port, 1); 716 717 mutex_unlock(&priv->reg_mutex); 718 719 return 0; 720 } 721 722 static void 723 mt7530_port_disable(struct dsa_switch *ds, int port, 724 struct phy_device *phy) 725 { 726 struct mt7530_priv *priv = ds->priv; 727 728 mutex_lock(&priv->reg_mutex); 729 730 /* Clear up all port matrix which could be restored in the next 731 * enablement for the port. 732 */ 733 priv->ports[port].enable = false; 734 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 735 PCR_MATRIX_CLR); 736 mt7530_port_set_status(priv, port, 0); 737 738 mutex_unlock(&priv->reg_mutex); 739 } 740 741 static void 742 mt7530_stp_state_set(struct dsa_switch *ds, int port, u8 state) 743 { 744 struct mt7530_priv *priv = ds->priv; 745 u32 stp_state; 746 747 switch (state) { 748 case BR_STATE_DISABLED: 749 stp_state = MT7530_STP_DISABLED; 750 break; 751 case BR_STATE_BLOCKING: 752 stp_state = MT7530_STP_BLOCKING; 753 break; 754 case BR_STATE_LISTENING: 755 stp_state = MT7530_STP_LISTENING; 756 break; 757 case BR_STATE_LEARNING: 758 stp_state = MT7530_STP_LEARNING; 759 break; 760 case BR_STATE_FORWARDING: 761 default: 762 stp_state = MT7530_STP_FORWARDING; 763 break; 764 } 765 766 mt7530_rmw(priv, MT7530_SSP_P(port), FID_PST_MASK, stp_state); 767 } 768 769 static int 770 mt7530_port_bridge_join(struct dsa_switch *ds, int port, 771 struct net_device *bridge) 772 { 773 struct mt7530_priv *priv = ds->priv; 774 u32 port_bitmap = BIT(MT7530_CPU_PORT); 775 int i; 776 777 mutex_lock(&priv->reg_mutex); 778 779 for (i = 0; i < MT7530_NUM_PORTS; i++) { 780 /* Add this port to the port matrix of the other ports in the 781 * same bridge. If the port is disabled, port matrix is kept 782 * and not being setup until the port becomes enabled. 783 */ 784 if (dsa_is_user_port(ds, i) && i != port) { 785 if (dsa_to_port(ds, i)->bridge_dev != bridge) 786 continue; 787 if (priv->ports[i].enable) 788 mt7530_set(priv, MT7530_PCR_P(i), 789 PCR_MATRIX(BIT(port))); 790 priv->ports[i].pm |= PCR_MATRIX(BIT(port)); 791 792 port_bitmap |= BIT(i); 793 } 794 } 795 796 /* Add the all other ports to this port matrix. */ 797 if (priv->ports[port].enable) 798 mt7530_rmw(priv, MT7530_PCR_P(port), 799 PCR_MATRIX_MASK, PCR_MATRIX(port_bitmap)); 800 priv->ports[port].pm |= PCR_MATRIX(port_bitmap); 801 802 mutex_unlock(&priv->reg_mutex); 803 804 return 0; 805 } 806 807 static void 808 mt7530_port_bridge_leave(struct dsa_switch *ds, int port, 809 struct net_device *bridge) 810 { 811 struct mt7530_priv *priv = ds->priv; 812 int i; 813 814 mutex_lock(&priv->reg_mutex); 815 816 for (i = 0; i < MT7530_NUM_PORTS; i++) { 817 /* Remove this port from the port matrix of the other ports 818 * in the same bridge. If the port is disabled, port matrix 819 * is kept and not being setup until the port becomes enabled. 820 */ 821 if (dsa_is_user_port(ds, i) && i != port) { 822 if (dsa_to_port(ds, i)->bridge_dev != bridge) 823 continue; 824 if (priv->ports[i].enable) 825 mt7530_clear(priv, MT7530_PCR_P(i), 826 PCR_MATRIX(BIT(port))); 827 priv->ports[i].pm &= ~PCR_MATRIX(BIT(port)); 828 } 829 } 830 831 /* Set the cpu port to be the only one in the port matrix of 832 * this port. 833 */ 834 if (priv->ports[port].enable) 835 mt7530_rmw(priv, MT7530_PCR_P(port), PCR_MATRIX_MASK, 836 PCR_MATRIX(BIT(MT7530_CPU_PORT))); 837 priv->ports[port].pm = PCR_MATRIX(BIT(MT7530_CPU_PORT)); 838 839 mutex_unlock(&priv->reg_mutex); 840 } 841 842 static int 843 mt7530_port_fdb_add(struct dsa_switch *ds, int port, 844 const unsigned char *addr, u16 vid) 845 { 846 struct mt7530_priv *priv = ds->priv; 847 int ret; 848 u8 port_mask = BIT(port); 849 850 mutex_lock(&priv->reg_mutex); 851 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_ENT); 852 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); 853 mutex_unlock(&priv->reg_mutex); 854 855 return ret; 856 } 857 858 static int 859 mt7530_port_fdb_del(struct dsa_switch *ds, int port, 860 const unsigned char *addr, u16 vid) 861 { 862 struct mt7530_priv *priv = ds->priv; 863 int ret; 864 u8 port_mask = BIT(port); 865 866 mutex_lock(&priv->reg_mutex); 867 mt7530_fdb_write(priv, vid, port_mask, addr, -1, STATIC_EMP); 868 ret = mt7530_fdb_cmd(priv, MT7530_FDB_WRITE, 0); 869 mutex_unlock(&priv->reg_mutex); 870 871 return ret; 872 } 873 874 static int 875 mt7530_port_fdb_dump(struct dsa_switch *ds, int port, 876 dsa_fdb_dump_cb_t *cb, void *data) 877 { 878 struct mt7530_priv *priv = ds->priv; 879 struct mt7530_fdb _fdb = { 0 }; 880 int cnt = MT7530_NUM_FDB_RECORDS; 881 int ret = 0; 882 u32 rsp = 0; 883 884 mutex_lock(&priv->reg_mutex); 885 886 ret = mt7530_fdb_cmd(priv, MT7530_FDB_START, &rsp); 887 if (ret < 0) 888 goto err; 889 890 do { 891 if (rsp & ATC_SRCH_HIT) { 892 mt7530_fdb_read(priv, &_fdb); 893 if (_fdb.port_mask & BIT(port)) { 894 ret = cb(_fdb.mac, _fdb.vid, _fdb.noarp, 895 data); 896 if (ret < 0) 897 break; 898 } 899 } 900 } while (--cnt && 901 !(rsp & ATC_SRCH_END) && 902 !mt7530_fdb_cmd(priv, MT7530_FDB_NEXT, &rsp)); 903 err: 904 mutex_unlock(&priv->reg_mutex); 905 906 return 0; 907 } 908 909 static enum dsa_tag_protocol 910 mtk_get_tag_protocol(struct dsa_switch *ds, int port) 911 { 912 struct mt7530_priv *priv = ds->priv; 913 914 if (port != MT7530_CPU_PORT) { 915 dev_warn(priv->dev, 916 "port not matched with tagging CPU port\n"); 917 return DSA_TAG_PROTO_NONE; 918 } else { 919 return DSA_TAG_PROTO_MTK; 920 } 921 } 922 923 static int 924 mt7530_setup(struct dsa_switch *ds) 925 { 926 struct mt7530_priv *priv = ds->priv; 927 int ret, i; 928 u32 id, val; 929 struct device_node *dn; 930 struct mt7530_dummy_poll p; 931 932 /* The parent node of master netdev which holds the common system 933 * controller also is the container for two GMACs nodes representing 934 * as two netdev instances. 935 */ 936 dn = ds->ports[MT7530_CPU_PORT].master->dev.of_node->parent; 937 priv->ethernet = syscon_node_to_regmap(dn); 938 if (IS_ERR(priv->ethernet)) 939 return PTR_ERR(priv->ethernet); 940 941 regulator_set_voltage(priv->core_pwr, 1000000, 1000000); 942 ret = regulator_enable(priv->core_pwr); 943 if (ret < 0) { 944 dev_err(priv->dev, 945 "Failed to enable core power: %d\n", ret); 946 return ret; 947 } 948 949 regulator_set_voltage(priv->io_pwr, 3300000, 3300000); 950 ret = regulator_enable(priv->io_pwr); 951 if (ret < 0) { 952 dev_err(priv->dev, "Failed to enable io pwr: %d\n", 953 ret); 954 return ret; 955 } 956 957 /* Reset whole chip through gpio pin or memory-mapped registers for 958 * different type of hardware 959 */ 960 if (priv->mcm) { 961 reset_control_assert(priv->rstc); 962 usleep_range(1000, 1100); 963 reset_control_deassert(priv->rstc); 964 } else { 965 gpiod_set_value_cansleep(priv->reset, 0); 966 usleep_range(1000, 1100); 967 gpiod_set_value_cansleep(priv->reset, 1); 968 } 969 970 /* Waiting for MT7530 got to stable */ 971 INIT_MT7530_DUMMY_POLL(&p, priv, MT7530_HWTRAP); 972 ret = readx_poll_timeout(_mt7530_read, &p, val, val != 0, 973 20, 1000000); 974 if (ret < 0) { 975 dev_err(priv->dev, "reset timeout\n"); 976 return ret; 977 } 978 979 id = mt7530_read(priv, MT7530_CREV); 980 id >>= CHIP_NAME_SHIFT; 981 if (id != MT7530_ID) { 982 dev_err(priv->dev, "chip %x can't be supported\n", id); 983 return -ENODEV; 984 } 985 986 /* Reset the switch through internal reset */ 987 mt7530_write(priv, MT7530_SYS_CTRL, 988 SYS_CTRL_PHY_RST | SYS_CTRL_SW_RST | 989 SYS_CTRL_REG_RST); 990 991 /* Enable Port 6 only; P5 as GMAC5 which currently is not supported */ 992 val = mt7530_read(priv, MT7530_MHWTRAP); 993 val &= ~MHWTRAP_P6_DIS & ~MHWTRAP_PHY_ACCESS; 994 val |= MHWTRAP_MANUAL; 995 mt7530_write(priv, MT7530_MHWTRAP, val); 996 997 /* Enable and reset MIB counters */ 998 mt7530_mib_reset(ds); 999 1000 mt7530_clear(priv, MT7530_MFC, UNU_FFP_MASK); 1001 1002 for (i = 0; i < MT7530_NUM_PORTS; i++) { 1003 /* Disable forwarding by default on all ports */ 1004 mt7530_rmw(priv, MT7530_PCR_P(i), PCR_MATRIX_MASK, 1005 PCR_MATRIX_CLR); 1006 1007 if (dsa_is_cpu_port(ds, i)) 1008 mt7530_cpu_port_enable(priv, i); 1009 else 1010 mt7530_port_disable(ds, i, NULL); 1011 } 1012 1013 /* Flush the FDB table */ 1014 ret = mt7530_fdb_cmd(priv, MT7530_FDB_FLUSH, 0); 1015 if (ret < 0) 1016 return ret; 1017 1018 return 0; 1019 } 1020 1021 static const struct dsa_switch_ops mt7530_switch_ops = { 1022 .get_tag_protocol = mtk_get_tag_protocol, 1023 .setup = mt7530_setup, 1024 .get_strings = mt7530_get_strings, 1025 .phy_read = mt7530_phy_read, 1026 .phy_write = mt7530_phy_write, 1027 .get_ethtool_stats = mt7530_get_ethtool_stats, 1028 .get_sset_count = mt7530_get_sset_count, 1029 .adjust_link = mt7530_adjust_link, 1030 .port_enable = mt7530_port_enable, 1031 .port_disable = mt7530_port_disable, 1032 .port_stp_state_set = mt7530_stp_state_set, 1033 .port_bridge_join = mt7530_port_bridge_join, 1034 .port_bridge_leave = mt7530_port_bridge_leave, 1035 .port_fdb_add = mt7530_port_fdb_add, 1036 .port_fdb_del = mt7530_port_fdb_del, 1037 .port_fdb_dump = mt7530_port_fdb_dump, 1038 }; 1039 1040 static int 1041 mt7530_probe(struct mdio_device *mdiodev) 1042 { 1043 struct mt7530_priv *priv; 1044 struct device_node *dn; 1045 1046 dn = mdiodev->dev.of_node; 1047 1048 priv = devm_kzalloc(&mdiodev->dev, sizeof(*priv), GFP_KERNEL); 1049 if (!priv) 1050 return -ENOMEM; 1051 1052 priv->ds = dsa_switch_alloc(&mdiodev->dev, DSA_MAX_PORTS); 1053 if (!priv->ds) 1054 return -ENOMEM; 1055 1056 /* Use medatek,mcm property to distinguish hardware type that would 1057 * casues a little bit differences on power-on sequence. 1058 */ 1059 priv->mcm = of_property_read_bool(dn, "mediatek,mcm"); 1060 if (priv->mcm) { 1061 dev_info(&mdiodev->dev, "MT7530 adapts as multi-chip module\n"); 1062 1063 priv->rstc = devm_reset_control_get(&mdiodev->dev, "mcm"); 1064 if (IS_ERR(priv->rstc)) { 1065 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1066 return PTR_ERR(priv->rstc); 1067 } 1068 } 1069 1070 priv->core_pwr = devm_regulator_get(&mdiodev->dev, "core"); 1071 if (IS_ERR(priv->core_pwr)) 1072 return PTR_ERR(priv->core_pwr); 1073 1074 priv->io_pwr = devm_regulator_get(&mdiodev->dev, "io"); 1075 if (IS_ERR(priv->io_pwr)) 1076 return PTR_ERR(priv->io_pwr); 1077 1078 /* Not MCM that indicates switch works as the remote standalone 1079 * integrated circuit so the GPIO pin would be used to complete 1080 * the reset, otherwise memory-mapped register accessing used 1081 * through syscon provides in the case of MCM. 1082 */ 1083 if (!priv->mcm) { 1084 priv->reset = devm_gpiod_get_optional(&mdiodev->dev, "reset", 1085 GPIOD_OUT_LOW); 1086 if (IS_ERR(priv->reset)) { 1087 dev_err(&mdiodev->dev, "Couldn't get our reset line\n"); 1088 return PTR_ERR(priv->reset); 1089 } 1090 } 1091 1092 priv->bus = mdiodev->bus; 1093 priv->dev = &mdiodev->dev; 1094 priv->ds->priv = priv; 1095 priv->ds->ops = &mt7530_switch_ops; 1096 mutex_init(&priv->reg_mutex); 1097 dev_set_drvdata(&mdiodev->dev, priv); 1098 1099 return dsa_register_switch(priv->ds); 1100 } 1101 1102 static void 1103 mt7530_remove(struct mdio_device *mdiodev) 1104 { 1105 struct mt7530_priv *priv = dev_get_drvdata(&mdiodev->dev); 1106 int ret = 0; 1107 1108 ret = regulator_disable(priv->core_pwr); 1109 if (ret < 0) 1110 dev_err(priv->dev, 1111 "Failed to disable core power: %d\n", ret); 1112 1113 ret = regulator_disable(priv->io_pwr); 1114 if (ret < 0) 1115 dev_err(priv->dev, "Failed to disable io pwr: %d\n", 1116 ret); 1117 1118 dsa_unregister_switch(priv->ds); 1119 mutex_destroy(&priv->reg_mutex); 1120 } 1121 1122 static const struct of_device_id mt7530_of_match[] = { 1123 { .compatible = "mediatek,mt7530" }, 1124 { /* sentinel */ }, 1125 }; 1126 1127 static struct mdio_driver mt7530_mdio_driver = { 1128 .probe = mt7530_probe, 1129 .remove = mt7530_remove, 1130 .mdiodrv.driver = { 1131 .name = "mt7530", 1132 .of_match_table = mt7530_of_match, 1133 }, 1134 }; 1135 1136 mdio_module_driver(mt7530_mdio_driver); 1137 1138 MODULE_AUTHOR("Sean Wang <sean.wang@mediatek.com>"); 1139 MODULE_DESCRIPTION("Driver for Mediatek MT7530 Switch"); 1140 MODULE_LICENSE("GPL"); 1141 MODULE_ALIAS("platform:mediatek-mt7530"); 1142